NXP Semiconductors Data Sheet: Technical Data Document Number MPC5746R Rev. 7, 02/2020 MPC5746R SPC5746R Microcontroller Data Sheet Features * This document provides electrical specifications, pin assignments, and package diagrams for the MPC5746R series of microcontroller units (MCUs). * For functional characteristics, see the MPC5746R Microcontroller Reference Manual. NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products. Table of Contents 1 Introduction........................................................................................ 3 1.1 17.2 Flash memory Array Integrity and Margin Read Block diagram......................................................................... 3 specifications...........................................................................55 2 Package pinouts and signal descriptions............................................ 5 17.3 Flash memory module life specifications................................55 3 Absolute maximum ratings................................................................ 6 17.4 Data retention vs program/erase cycles...................................56 4 Electromagnetic Compatibility (EMC).............................................. 7 17.5 Flash memory AC timing specifications.................................57 5 Electrostatic discharge (ESD)............................................................ 7 17.6 Flash read wait state and address pipeline control settings.....58 6 Operating conditions.......................................................................... 8 18 AC specifications............................................................................... 58 7 DC electrical specifications................................................................11 8 I/O pad specification.......................................................................... 12 18.1.1 JTAG interface timing............................................ 58 8.1 Input pad specifications...........................................................12 18.1.2 Nexus interface timing............................................61 8.2 Output pad specifications........................................................ 15 18.1.3 Aurora LVDS interface timing............................... 63 8.3 I/O pad current specifications................................................. 17 9 Reset pad (PORST, RESET) electrical characteristics...................... 18 18.1 Debug and calibration interface timing...................................58 18.2 DSPI timing with CMOS and LVDS...................................... 65 18.2.1 10 Oscillator and FMPLL....................................................................... 22 11 ADC modules.....................................................................................26 11.1 ADC input description............................................................ 26 11.2 SAR ADC................................................................................26 and LVDS pads....................................................... 66 18.2.2 18.3.1 18.3.2 18.3.3 MII-lite async inputs signal timing (CRS and COL)....................................................................... 82 18.3.4 characteristics.......................................................................... 42 14 LFAST PLL electrical characteristics................................................45 MII-lite transmit signal timing (TXD[3:0], TX_EN, TX_ER, TX_CLK)...................................81 13.1 LFAST interface timing diagrams...........................................40 13.2 LFAST and MSC /DSPI LVDS interface electrical MII-lite receive signal timing (RXD[3:0], RX_DV, RX_ER, and RX_CLK)...........................80 13 LVDS fast asynchronous serial transmission (LFAST) pad electrical characteristics..................................................................... 40 DSPI CMOS slave mode........................................ 78 18.3 FEC timing.............................................................................. 80 11.3 S/D ADC................................................................................. 29 12 Temperature sensor............................................................................ 39 DSPI master mode full duplex timing with CMOS MII-lite serial management channel timing (MDIO and MDC).................................................. 82 18.3.5 15 Aurora LVDS electrical characteristics............................................. 46 RMII serial management channel timing (MDIO and MDC)............................................................... 83 16 Power management PMC POR LVD sequencing..............................47 18.3.6 RMII receive signal timing (RXD[1:0], CRS_DV)84 16.1 Power management electrical characteristics..........................47 18.3.7 RMII transmit signal timing (TXD[1:0], TX_EN). 85 16.1.1 Recommended power transistors............................ 47 18.4 UART timings......................................................................... 86 16.1.2 Power management integration.............................. 48 18.5 eMIOS timing..........................................................................86 16.1.3 Regulator example for the NJD2873 transistor...... 50 19 Obtaining package dimensions.......................................................... 86 16.1.4 Regulator example for the 2SCR574d transistor.... 51 20 Thermal characteristics...................................................................... 87 16.1.5 Device voltage monitoring......................................51 16.1.6 Power up/down sequencing.................................... 53 temperature..............................................................................89 17 Flash memory specifications..............................................................54 21 Ordering information......................................................................... 90 17.1 Flash memory program and erase specifications.................... 54 22 Revision history................................................................................. 91 20.1 General notes for specifications at maximum junction SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 2 NXP Semiconductors Introduction 1 Introduction The MPC5746R family of 32-bit microcontrollers is the latest achievement in integrated automotive application controllers. It belongs to an expanding range of automotivefocused products designed for flexibility to support a variety of applications. The advanced and cost-efficient host processor core of the MPC5746R automotive controller family complies with the Power Architecture embedded category. It operates at speeds as high as 200 MHz and offers high-performance processing optimized for low power consumption. It capitalizes on the available development infrastructure of current Power Architecture devices and is supported with software drivers, operating systems, and configuration code to assist with users' implementations. This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications. Note Within this document, VDD_HV_IO refers to supply pins VDD_HV_IO_MAIN, VDD_HV_IO_JTAG, VDD_HV_IO_FEC, and VDD_HV_IO_MSC SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 NXP Semiconductors 3 Introduction 1.1 Block diagram MPC5746R Computational Shell - Fast Domain 200MHz Double INTC JTAGM JTAGC DCI Nexus Aurora Router SPU Safety Lake Concentrator w/ E2E Ecc 50 MHz Nexus Data Trace w/ E2E Ecc 100 MHz 32 ADD 32 DATA DSP Nexus Data Trace VLE VLE I -Mem ctrl I-Cache ctrl I -Mem ctrl I-Cache ctrl 16kB IMEM 8kB - 2way 16kB IMEM 8kB - 2way D -Mem ctrl D -Mem ctrl 32kB DMEM 32kB DMEM Core Memory Protection Unit (CMPU) Core Memory Protection Unit (CMPU) BIU with E2E ECC BIU with E2E ECC 32 ADD 64 DATA Slow Cross Bar Switch (AMBA 2.0 v6 AHB) - 32 bit - 100 MHz System Memory Protection Unit (SMPU_1) S3 AIPS PBridge_0 E2E Ecc Decorate Storage 50MHz 32 ADD 32 DATA Peripheral Cluster A M3 M4 S0 M2 Intelligent Bridging Bus gasket SRAM Ctrl w/ E2E Ecc Decorated access SRAM 224KB Standby Supply Scalar SP-FPU I-Cache ctrl D -Mem ctrl Core Memory Protection Unit (CMPU) BIU with E2E ECC Safety Lake M1 S2 Standby Regulator Standby SRAM 32KB S1 S0 32 ADD 64 DATA 32 ADD 32 DATA Peripheral Cluster B RCCU Load/ 32 ADD Store 64 DATA 32 ADD 64 DATA M0 M3 Delay RCCU VLE I -Mem ctrl System Memory Protection Unit (SMPU_0) S3 AIPS PBridge_1 E2E Ecc Decorate Storage 50MHz Instruction Delay E200 z424 - 200 MHz Checker Core_0s DSP Fast Cross Bar Switch (AMBA 2.0 v6 AHB) - 64 bit - 200 MHz S7 S2 Load/ 32 ADD Store 64 DATA Nexus RWA Delayed Lock-step with Redundnacy Checkers DSP Scalar SP-FPU Instruction M1 Nexus3p Scalar SP-FPU 32 ADD 32 DATA M2 Nexus3p Unified Backdoor I/F w/ E2E Ecc Concentrator STM_0 E200 z425 - 200 MHz Main Core_0 Unified Backdoor I/F w/ E2E Ecc RCCU Unified Backdoor I/F w/ E2E Ecc Delay SWT_0 STM_1 64ch. eDMA w/ E2E Ecc DMACHMUX 64ch. eDMA w/ E2E Ecc Ethernet LFAST & SIPI SWT_1 E200 z425 - 200 MHz Main Core_1 32 ADD 64 DATA Overlay Backdoor for system RAM S4 32 ADD 64 DATA FLASH Controller Dual Ported Incl. Set-Associative Prefetch Buffers w/ E2E Ecc 256 Page Line 2 stage Pipeline Overlay RAM 16kB Flash 4MB EEPROM 256k Calibration Bus Buddy Device Interface NVM (Single Module) Peripherals allocation to the bridges is based on safety and pinout requirements Peripheral Domain - 50 MHz Figure 1. Core block diagram SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 4 NXP Semiconductors Package pinouts and signal descriptions LINFlex_M0 DSPI_M0 LINFlex_2 DSPI_4 LINFlex_0 DSPI_2 FlexCAN_2 DSPI_0 FlexCAN_0 DECFILTER_0 PMC PIT_RTI PCU ATX DECFILTER_1 MEMU BAR JTAGM SSCM STCU2 PASS JDC CFLASH TDM LFAST ADC_SD_2 Zipwire ADC_SD_0 SIUL2 DMAMUX_3 FlexCAN_3 FlexCAN_1 ADC_SAR_2 ME ADC_SAR_0 CGM SENT_0 BCTU DTS CRC_1 PLLs CRC_0 CMU XOSC REACM FCCU RCOSC eMIOS_1 eTPU_0 Reg. RGM PIT eTPU_0 Code. RAM eTPU_0 Par. RAM DMAMUX_0 eMIOS_0 DMAMUX_1 IGF DMAMUX_2 EIM DSPI_M1 DSPI_3 DSPI_1 LINFlex_M1 LINFlex_3 LINFlex_1 ADC_SD_1 ADC_SAR_3 ADC_SAR_1 PBRIDGE_1 WKPU PERIPHERAL CLUSTER A PERIPHERAL CLUSTER B SENT_1 FEC eDMA 3x SWT 2x STM INTC SEMA4 PFLASH PCM PRAM 2 x SMPU 2x XBIC 2x XBAR PBRIDGE_0 Figure 2. Peripherals allocation 2 Package pinouts and signal descriptions For package pinouts and signal descriptions, refer to the Reference Manual. SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 NXP Semiconductors 5 Absolute maximum ratings 3 Absolute maximum ratings Functional operating conditions are given in the DC electrical specifications. Absolute maximum voltages are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond listed maxima may affect device reliability or cause permanent damage to the device. Table 1. Absolute maximum ratings Symbol Cycle VDD_LV VDD_LV_BD Conditions1 Parameter Lifetime power cycles Emulation module Min -- Unit -- -0.3 1.5 V -- -0.3 1.5 V -- -0.3 6.0 V -- voltage2, 3, 4 voltage5 Max 1000k 2, 3, 4 1.2 V core supply voltage Value VDD_HV_IO_MAIN I/O supply VDD_HV_IO_JTAG Crystal oscillator and JTAG supply Reference to VSS -0.3 6.0 V VDD_HV_IO_FEC FEC supply voltage Not using Ethernet Reference to VSS -0.3 6.0 V VDD_HV_IO_MSC MSC supply voltage Reference to VSS -0.3 6.0 V VDD_HV_PMC Power Management Controller supply 6 voltage -- -0.3 6.0 V VDD_HV_FLA Decoupling pin for flash regulator6 -- -0.3 -- V RAM standby supply voltage -- -0.3 6.0 V VDDSTBY 6 VSS_HV_ADV_SD S/D ADC ground voltage Reference to VSS -0.3 0.3 V VSS_HV_ADV_SAR SAR ADC ground voltage Reference to VSS -0.3 0.3 V VDD_HV_ADV_SAR SAR ADC supply voltage Reference to VSS_HV_ADV_SAR -0.3 6.0 V VDD_HV_ADV_SD S/D ADC supply voltage Reference to VSS_HV_ADV_SD -0.3 6.0 V VSS_HV_ADR_SD S/D ADC ground reference Reference to VSS -0.3 0.3 V VSS_HV_ADR_SAR SAR ADC ground reference Reference to VSS -0.3 0.3 V VDD_HV_ADR_SAR SAR ADC alternate reference Reference to VSS_HV_ADR_SAR -0.3 6.0 V VDD_HV_ADR_SD S/D ADC alternate reference Reference to VSS_HV_ADR_SD -0.3 6.0 V -0.3 1.5 V VDD_LV_BD - VDD_LV Emulation module supply differential to 1.2 -- V core supply VSS - VSS_HV_ADR_SAR VSS_HV_ADR_SAR differential voltage -- -0.3 0.3 V VSS - VSS_HV_ADR_SD -- -0.3 0.3 V VSS - VSS_HV_ADV_SAR VSS_HV_ADV_SAR differential voltage -- -0.3 0.3 V VSS - VSS_HV_ADV_SD -- -0.3 0.3 V -0.3 6.0 V VIN VSS_HV_ADR_SD differential voltage VSS_HV_ADV_SD differential voltage I/O input voltage range7 -- Relative to IINJD Maximum DC injection current for digital pad VSS_HV_IO, 8, 9 -0.3 -- Relative to VDD_HV_IO8, 9 -- 0.3 Per pin, applies to all digital pins -5 5 mA Table continues on the next page... SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 6 NXP Semiconductors Electromagnetic Compatibility (EMC) Table 1. Absolute maximum ratings (continued) Symbol IINJA IMAXSEG10, 11 TSTG STORAGE TSDR Parameter Conditions1 Maximum DC injection current for analog pad Per pin, applies to all analog pins Maximum current per I/O segment -- Storage temperature range and nonoperating times -- Maximum storage time, assembled part programmed in ECU No supply; storage temperature in range -40 C to 60 C Maximum solder temperature12 Pb-free package MSL Moisture sensitivity level13 -- -- Value Unit Min Max -5 5 mA -120 120 mA -55 175 C -- 20 yrs -- 260 C -- 3 -- 1. Voltage is referenced to VSS unless otherwise noted. 2. Allowed 1.45 - 1.5 V for 60 seconds cumulative time at maximum TJ = 150 C, remaining time as defined in note -1 and note -1. 3. Allowed 1.375 - 1.45 V for 10 hours cumulative time at maximum TJ = 150 C, remaining time as defined in note -1. 4. 1.32 - 1.375 V range allowed periodically for supply with sinusoidal shape and average supply value below 1.275 V at maximum TJ = 150 C. 5. Allowed 5.5 - 6.0 V for 10 hours cumulative time at maximum TJ = 150 C, remaining time at or below 5.0 V +10%. 6. Allowed 3.6 - 4.5 V for 10 hours cumulative time at maximum TJ = 150 C, remaining time at or below 3.3 V +10%. This is an internally regulated supply. Values given are for reference only. 7. The maximum input voltage on an I/O pin tracks with the associated I/P supply maximum. For the injection current condition on a pin, the voltage will be equal to the supply plus the voltage drop across the internal ESD diode from I/O pin to supply. The diode voltage varies greatly across process and temperature, but a value of 0.3V can be used for nominal calculations. 8. Relative value can be exceeded, if design measures are taken to ensure injection current limitation (parameters IINJD and IINJA). 9. VDD_HV_IO/VSS_HV_IO refers to supply pins and corresponding grounds: VDD_HV_IO_MAIN, VDD_HV_IO_JTAG, VDD_HV_IO_FEC, VDD_HV_IO_MSC. 10. Sum of all controller pins (including both digital and analog) must not exceed 200 mA. A VDD_HV_IO power segment is defined as one or more GPIO pins located between two VDD_HV_IO supply pins. 11. The average current values given in the "I/O pad current specifications" section should be used to calculate total I/O segment current. 12. Solder profile per IPC/JEDEC J-STD-020D. 13. Moisture sensitivity per JEDEC test method A112. 4 Electromagnetic Compatibility (EMC) EMC measurements to IC-level IEC standards are available from NXP on request. 5 Electrostatic discharge (ESD) The following table describes the ESD ratings of the device. SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 NXP Semiconductors 7 Operating conditions All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. Device failure is defined as: "If after exposure to ESD pulses, the device does not meet the device specification requirements, which includes the complete DC parametric and functional testing at room temperature and hot temperature. Maximum DC parametrics variation within 10% of maximum specification." Table 2. ESD ratings Parameter ESD for Human Body Model (HBM)1 (CDM)2 ESD for field induced Charged Device Model Conditions Value Unit All pins 2000 V All pins 500 V 1. This parameter tested in conformity with ANSI/ESD STM5.1-2007 Electrostatic Discharge Sensitivity Testing 2. This parameter tested in conformity with ANSI/ESD STM5.3-1990 Charged Device Model - Component Level 6 Operating conditions The following table describes the operating conditions for the device, and for which all specifications in the data sheet are valid, except where explicitly noted. The device operating conditions must not be exceeded in order to guarantee proper operation and reliability. NOTE All power supplies need to be powered up to ensure normal operation of the device. Table 3. Device operating conditions Symbol Parameter Value Conditions Unit Min Typ Max -- -- 200 MHz Frequency fSYS Device operating frequency1 TJ -40 C to 150 C Temperature TJ Operating temperature range junction -40.0 -- 150.0 C TA (TL to TH) Operating temperature range ambient -40.0 -- 125.0 C VDD_LV External core supply voltage2, 3 LVD/HVD enabled 1.2 -- 1.32 V LVD/HVD disabled4, 5, 6 1.18 -- 1.38 3.5 -- 5.5 Voltage VDD_HV_IO_MAIN I/O supply voltage 7 V Table continues on the next page... SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 8 NXP Semiconductors Operating conditions Table 3. Device operating conditions (continued) Symbol Parameter Conditions FEC I/O supply voltage8 Value Unit Min Typ Max 5 V range 3.5 -- 5.5 3.3 V range 3.0 -- 3.6 5 V range 3.5 -- 5.5 3.3 V range 3.0 -- 3.6 5 V range 3.5 -- 5.5 3.3 V range 3.0 -- 3.6 Power Management Controller (PMC) supply voltage Full functionality 3.5 -- 5.5 V VDDSTBY13 RAM standby supply voltage14 -- 1.3 -- 5.9 V VSTBY_BO Standby RAM brownout voltage -- -- -- 0.9 V VDD_HV_IO_FEC VDD_HV_IO_MSC 10 VDD_HV_IO_JTAG VDD_HV_PMC 12 MSC I/O supply voltage9 JTAG I/O supply voltage11 V V V VDD_LV_STBY_SW Standby RAM switch VDD_LV voltage -- threshold 0.95 -- -- V VDD_HV_ADV_SD S/D ADC supply voltage15, 16 4.5 -- 5.5 V VDD_HV_ADV_SAR SAR ADC supply voltage 3.0 -- 5.5 V 3.0 -- 5.5 V -- -- 25 mV -25 -- 25 mV 3.0 -- 5.5 V -- -- 25 mV -25 -- 25 mV -- 17 VDD_HV_ADR_SD -- S/D ADC reference -- VDD_HV_ADR_SD - VDD_HV_ADV_SD S/D ADC reference differential voltage -- VSS_HV_ADR_SD - VSS_HV_ADV_SD VSS_HV_ADR_SD differential voltage -- VDD_HV_ADR_SAR SAR ADC reference -- VDD_HV_ADR_SAR - VDD_HV_ADV_SAR SAR ADC reference differential voltage -- VSS_HV_ADR_SAR - VSS_HV_ADV_SAR VSS_HV_ADR_SAR differential voltage -- VSS_HV_ADV_SD - VSS VSS_HV_ADV_SD differential voltage -- -25 -- 25 mV -- -25 -- 25 mV V/ms VSS_HV_ADV_SAR - VSS VSS_HV_ADV_SAR differential voltage VRAMP_VDD_LV Slew rate on power supply pins (VDD_LV) Ramp up 0.069 -- 100 Ramp down 0.0345 -- 100 VRAMP_VDD_HV_IO_MAIN, Slew rate on power supply pins VRAMP_VDD_HV_PMC (VDD_HV_IO_MAIN, VDD_HV_PMC) Ramp up 0.148 -- 100 Ramp down 0.125 -- 100 DC injection current (per pin)18, 19, 20 Digital pins and analog pins -3.0 -- 3.0 mA Maximum current per power segment21, 22 -80 -- 80 mA V/ms Injection current IIC IMAXSEG -- 1. Maximum operating frequency is applicable to the computational cores and platform for the device. 2. Core voltage as measured on device pin to guarantee published silicon performance. 3. During power ramp, voltage measured on silicon might be lower. maximum performance is not guaranteed, but correct silicon operation is guaranteed. See power management and reset management for description. 4. Maximum core voltage is not permitted for entire product life. See absolute maximum rating. 5. When internal LVD/HVDs are disabled, external monitoring is required to guarantee device operation. Failure to monitor externally supply voltage may result in erroneous operation of the device. SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 NXP Semiconductors 9 Operating conditions 6. This LVD/HVD disabled supply voltage condition only applies after LVD/HVD are disabled by the application during the reset sequence, and the LVD/HVD are active until that point. 7. The pad are operative till 3.0V full performance. The IRC oscillator is supplied by this pin and it is setting the min voltage limit. 8. FEC will be used only in 3.3V mode. In 5V mode the segment is a general IO segment with the same characteristics of IO_MAIN. 9. MSC will be used only in 3.3V mode. In 5V mode the segment is a general IO segment with the same characteristics of IO_MAIN. 10. If XOSC is enabled via DCF_UTEST_Miscellaneous[XOSC_EN], VDD_HV_IO_JTAG must be within the operating range before RESET pin is released. 11. JTAG will be used only in 3.3V mode. In 5V mode the segment is a general IO segment with the same characteristics of IO_MAIN. 12. The startup of flash regulator and memory initialization immediately after Phase0 of reset sequence could cause a drop of the PMC supply. No LVD event will be generated as during this time the LVD monitors are not enabled. 13. VDDSTBY supply must be present before and after power up/down of the device supplies and the ramp rate should be less than 33.3 kV/s. 14. RAM retention is not guaranteed below 1.3 V, but no effect on RAM operation for voltages below 1.3 V when VDD_LV is above the minimum value. 15. For supply voltages between 3.6V and 4.5V there will be no guaranteed precision of ADC (accuracy/linearity). ADC will recover to a fully functional state when the voltage rises above 4.5V. 16. VDD_HV_ADV_SD must be higher or equal than the VDD_HV_ADV_SAR supply to guarantee full performance. It is recommended to connect the VDD_HV_ADV_SD to VDD_HV_ADV_SAR at board level. 17. Temperature Sensor and its associated Band-Gap reference are supplied by this pin. The temperature sensor performance is guaranteed only between 4.5 V and 5.5 V. 18. Full device lifetime without performance degradation. 19. I/O and analog input specifications are only valid if the injection current on adjacent pins is within these limits. See the absolute maximum ratings table for maximum input current for reliability requirements. 20. The I/O pins on the device are clamped to the I/O supply rails for ESD protection. When the voltage of the input pin is above the supply rail, current will be injected through the clamp diode to the supply rail. For external RC network calculation, assume typical 0.3 V drop across the active diode. The diode voltage drop varies with temperature. For more information, see the device characterization report. 21. Sum of all controller pins (including both digital and analog) must not exceed 200 mA. A VDD_HV_IO power segment is defined as one or more GPIO pins located between two VDD_HV_IO supply pins. 22. The average current values given in the "I/O pad current specifications" section should be used to calculate total I/O segment current. Table 4. Emulation (buddy) device operating conditions Symbol Parameter Conditions Value Min Typ Max Unit Frequency -- Standard JTAG 1149.1/1149.7 frequency -- -- -- 50 MHz -- High-speed debug frequency -- -- -- 320 MHz -- Data trace frequency -- -- -- 1250 MHz Temperature TJ_BD Device junction operating temperature range Packaged devices -40.0 -- 150.0 C TA _BD Ambient operating temperature range Packaged devices -40.0 -- 125.0 C Voltage VDD_LV_BD Buddy core supply voltage VDD_HV_IO_B Buddy I/O supply voltage -- 1.18 -- 1.32 V -- 3.0 -- 5.5 V -- -- -- 500 V/ms D VRAMP_BD Buddy slew rate on power supply pins SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 10 NXP Semiconductors DC electrical specifications 7 DC electrical specifications The following table describes the DC electrical specifications. Table 5. DC electrical specifications Symbol IDD_LV Parameter Conditions Maximum operating current on the VDD_LV supply 1 Typ Max MPC5746R/ MPC5745R -- -- 700 MPC5743R/ MPC5742R -- -- 610 -- -- 40 mA Flash read -- -- 40 mA Flash P/E -- -- 70 PMC only -- -- 35 Flash read -- -- 10 Flash P/E -- -- 40 Core regulator DC current -- output on VRC_CTRL pin -- -- 25 mA 32 KB RAM Standby Leakage Current (standby regulator on, RAM not operational)3, 4, 5 VDDSTBY @1.3 V to 5.9 V, TJ = 150 C -- -- 575 A VDDSTBY @1.3 V to 5.9 V, TA = 40 C -- -- 55 VDDSTBY @1.3 V to 5.9 V, TA = 85 C -- -- 65 VDDSTBY @1.2 V to 5.9 V, Tj = 150 C -- -- 50 A -- 250 mA -- -- 130 mA Bandgap reference current consumption -- -- 600 A BD Debug/Emulation low TJ = 150 C voltage supply standby VDD_LV_BD = 1.32 current V -- -- 120 mA VDDA supply current -- 16 25 mA Operating current on the VDD_LV supply for flash program/erase IDD_HV_PMC Operating current on the VDD_HV_PMC supply2 Operating current on the VDD_HV_PMC supply (internal core reg bypassed) IDDSTBY_ON IDDSTBY_REG IDD_LV_BD IDD_HV_IO_BD IBG IDD_BD_STBY IVDDA Unit Min IDD_LV_PE IVRCCTRL Value 32 KB RAM Standby Regulator Current 6 -- BD Debug/Emulation low TJ = 150 C voltage supply operating VDD_LV_BD = 1.32 current7 V Debug/Emulation high voltage supply operating current (Aurora + JTAG/ LFAST) mA TJ = 150 C mA -- 1. Value is derived from a typical application at 200MHz, Core 0 Data and Instruction Cache On, Core 1 in Lockstep mode, typical usage for SARADC, SDADC, DMA, eTPU, eMIOS, CAN, MSC, SPI, SENT, PIT, and Flash reads. SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 NXP Semiconductors 11 I/O pad specification 2. This value is considering the use of the internal core regulator with an external ballast with the minimum value of hFE of 60. 3. Data is retained for full TB range of -40 C to 125 C. RAM supply switch to the standby regulator occurs when the VDD_LV supply falls below 0.95V. 4. VDDSTBY may be supplied with a non-regulated power supply, but the absolute maximum voltage on VDDSTBY given in the absolute maximum ratings table must be observed. 5. The maximum value for IDDSTBY_ON is also valid when switching from the core supply to the standby supply, and when powering up the device and switching the RAM supply back to VDD_LV 6. When the VDDSTBY pin is powered, the standby RAM regulator current is present on the pin, regardless if the device is in standby mode or not. No current is present on the pin when VDDSTBY pin is set to 0V, disabling the standby regulator. 7. Worst case usage (data trace, data overlay, full Aurora utilization). 8 I/O pad specification The following table describes the different pad type configurations. Table 6. I/O pad specification descriptions Pad type Description General-purpose I/O pad General-purpose I/O pads with four selectable output slew rate settings. The GPIO pads have CMOS input threshold levels. LVDS pads Low Voltage Differential Signal interface pads Input only pads These pads, which ensure low input leakage, are associated with the ADC channels. The digital inputs of these pads have CMOS, and TTL input threshold levels. Note Each I/O pin on the device supports specific drive configurations. See the signal description table in the device reference manual for the available drive configurations for each I/O pin. 8.1 Input pad specifications SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 12 NXP Semiconductors I/O pad specification VIN VDD VIH VHYS VIL VINTERNAL (SIUL register) Figure 3. I/O input DC electrical characteristics definition Table 7. I/O input DC electrical characteristics Parameter1 Symbol Value2 Conditions Min Unit Typ Max VIHTTL TTL input high level 3.0 V < VDD_HV_IO < 5.5 V 2.0 -- VDD_HV_IO + 0.3 V VILTTL TTL input low level 3.0 V < VDD_HV_IO < 5.5 V VSS -0.3 -- 0.6 V VHYSTTL TTL level input hysteresis 3.0 V < VDD_HV_IO < 5.5 V 0.3 -- -- V mV V -- -- -- 1003 VIHCMOS_H CMOS input high level (with hysteresis) 3.0 V < VDD_HV_IO < 5.5 V 0.65 * VDD_HV_IO -- VDD_HV_IO VIHCMOS 3.0 V < VDD_HV_IO < 5.5 V 0.55 * VDD_HV_IO -- VDD_HV_IO + 0.3 V VILCMOS_H CMOS input low level (with 3.0 V < VDD_HV_IO < 5.5 V hysteresis) VSS -0.3 -- 0.35 * V VILCMOS VSS -0.3 VDRFTTTL TTL Input VIL/VIH temperature drift CMOS input high level (without hysteresis) CMOS input low level (without hysteresis) VHYSCMOS CMOS input hysteresis 3.0 V < VDD_HV_IO < 5.5 V + 0.3 VDD_HV_IO -- 0.4 * V VDD_HV_IO 3.0 V < VDD_HV_IO < 5.5 V 0.1 * -- -- V VDD_HV_IO VDRFTCMO CMOS Input VIL/VIH S temperature drift -- -- -- 1003 mV GPIO pins -1.0 -- 1.0 A -- -- 8 pF INPUT CHARACTERISTICS4 ILKG Digital input leakage VSS < VIN < VDD_HV_IO CIN Input capacitance GPIO and Input pins 1. Supported input levels vary according to pad types. Pad type "pad_sr_hv" supports only the CMOS input level, while pad type "pad_isatww_st_hv" supports TTL and CMOS levels. Refer to the IO spreadsheet attached to the Reference Manual for the pad type of each pin. SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 NXP Semiconductors 13 I/O pad specification 2. TTL level input specifications apply to the digital inputs on the analog input pins, and not the GPIO pins on the device. 3. In a 1 ms period, assuming stable voltage and a temperature variation of 30 AC, VIL/VIH shift is within 50 mV. For SENT requirement, refer to Note in the "I/O pad current specifications" section. 4. For LFAST, microsecond bus, and LVDS input characteristics, refer to dedicated communication module chapters. The following table provides the current specifications for the GPIO pad weak pull-up and pull-down. Table 8. GPIO Pull-Up/Down DC electrical characteristics Symbol Parameter Conditions Value Min |IWPU| Weak pull-up current absolute value1 Typ Unit Max Vin = VIH = 0.65 * VDD_HV_IO A 4.5V < VDD_HV_IO < 5.5V 30 -- -- 3.0V < VDD_HV_IO < 3.6V 18 -- -- 4.5V < VDD_HV_IO < 5.5V -- -- 120 3.0V < VDD_HV_IO < 3.6V -- -- 80 -- -- 130 Vin = VIL = 0.35 * VDD_HV_IO Vin = VIL = 1.1V (TTL) 4.5V < VDD_HV_IO < 5.5V |IWPD| Weak pull-down current absolute value Vin = VIH = 0.65 * VDD_HV_IO A 4.5V < VDD_HV_IO < 5.5V -- -- 120 3.0V < VDD_HV_IO < 3.6V -- -- 80 4.5V < VDD_HV_IO < 5.5V 30 -- -- 3.0V < VDD_HV_IO < 3.6V 18 -- -- 16 -- -- Vin = VIL = 0.35 * VDD_HV_IO Vin = VIL = 0.9V (TTL) 4.5V < VDD_HV_IO < 5.5V 1. Weak pull-up/down is enabled within tWK_PU = 1 s after internal/external reset has been asserted. Output voltage will depend on the amount of capacitance connected to the pin. SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 14 NXP Semiconductors I/O pad specification tWK_PU tWK_PU VDD_HV_IO VDD_POR RESET(INTERNAL) pull-up enabled YES NO (1) PAD (1) (1) POWER-UP 1 Application defined RESET Application defined POWER-DOWN Actual PAD slopes will depend on external capacitances and VDD_HV_IO supply. Figure 4. Weak pull-up electrical characteristics definition Analog input leakage and pull up/down information is located in the ADC input description section. 8.2 Output pad specifications The following figure provides the description of output DC electrical characteristics. SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 NXP Semiconductors 15 I/O pad specification VINTERNAL (SIUL2 register) VHYS tPD tPD tSKEW20-80 Vout 90% 80% 50% 20% 10% tR20-80 tF20-80 tR10-90 tF10-90 tTR(max) = MAX(tR10-90;tF10-90) tTR20-80(max) = MAX(tR20-80;tF20-80) tTR(min) = MIN(tR10-90;tF10-90) tTR20-80(min) = MIN(tR20-80;tF20-80) tSKEW20-80 = tR20-80-tF20-80 Figure 5. I/O output DC electrical characteristics definition Table 9. GPIO pad output buffer electrical characteristics Symbol Parameter Value 1, 2 Conditions Min VOH GPIO pad output high voltage 4.5V < VDD_HV_IO < 5.0V MSCR[OERC] = 11, IOH = 38mA Unit Typ Max 0.8 * -- VDD_H V_IO -- V 0.8 * -- VDD_H V_IO -- -- 0.2 * V VDD_H V_IO MSCR[OERC] = 10, IOH = 19mA MSCR[OERC] = 01, IOH = 10mA MSCR[OERC] = 00, IOH = 5mA 3.0V < VDD_HV_IO < 3.6V MSCR[OERC] = 11, IOH = 19mA MSCR[OERC] = 10, IOH = 10mA MSCR[OERC] = 01, IOH = 7mA MSCR[OERC] = 00, IOH = 5mA VOL GPIO pad output low voltage 4.5V < VDD_HV_IO < 5.0V MSCR[OERC] = 11, IOL = 48mA -- MSCR[OERC] = 10, IOL = 24mA MSCR[OERC] = 01, IOL = 12mA Table continues on the next page... SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 16 NXP Semiconductors I/O pad specification Table 9. GPIO pad output buffer electrical characteristics (continued) Symbol Parameter Value 1, 2 Conditions Min Unit Typ Max MSCR[OERC] = 00, IOL = 6mA 3.0V < VDD_HV_IO < 3.6V -- -- 0.2 * VDD_H V_IO CL = 25pF -- -- 1.5 CL = 50pF -- -- 3 MSCR[OERC] = 10 CL = 50pF -- -- 6.5 MSCR[OERC] = 01 CL = 50pF -- -- 25 MSCR[OERC] = 00 CL = 50pF -- -- 40 GPIO pad output propagation MSCR[OERC] = 11 delay time CL = 25pF -- -- 6 CL = 50pF -- -- 7.5 MSCR[OERC] = 10 CL = 50pF -- -- 11.5 MSCR[OERC] = 01 CL = 50pF -- -- 45 MSCR[OERC] = 00 CL = 50pF -- -- 75 -- -- 10 MSCR[OERC] = 11, IOL = 24mA MSCR[OERC] = 10, IOL = 12mA MSCR[OERC] = 01, IOL = 9mA MSCR[OERC] = 00, IOL = 6mA tR_F GPIO pad output transition time (rise/fall) tPD |tSKEW_W| MSCR[OERC] = 11 Difference between rise and fall time - ns ns % 1. All GPIO pad output specifications are valid for 3.0V < VDD_HV_IO < 5.5V, except where explicitly stated. 2. All values need to be confirmed during device validation. 8.3 I/O pad current specifications The I/O pads are distributed across the I/O supply segment. Each I/O supply segment is associated to a VDD_HV_IO/VSS_HV_IO supply pair. The following tables provides I/O consumption figures. Table 10. I/O current consumption at VDD_HV_IO = 3.6 V Cell VDD_HV_IO (V) Load (pF) Period1 (ns) MSCR[OERC] pad_sr_hv 3.63 25 12 11 50 Idde AVG (mA) Idde RMS (mA) 13 37 15 16 36 200 39 20 44 25 16 8 20 50 23 9 21 200 66 12 37 50 90 1.4 4 10 01 Table continues on the next page... SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 NXP Semiconductors 17 Reset pad (PORST, RESET) electrical characteristics Table 10. I/O current consumption at VDD_HV_IO = 3.6 V (continued) Cell VDD_HV_IO (V) Load (pF) Period1 (ns) 200 130 50 150 200 200 MSCR[OERC] Idde AVG (mA) Idde RMS (mA) 00 3 9 1.6 4 4 11 Table 11. I/O current consumption at VDD_HV_IO = 5.5 V Cell VDD_HV_IO (V) Load (pF) Period1 (ns) MSCR[OERC] pad_sr_hv 5.5 25 9 11 50 Idde AVG (mA) Idde RMS (mA) 37 83 10.2 42 89 200 26 46 92 25 10.5 25 53 50 16 21 44 200 44 26 49 50 54 200 80 50 80 200 130 10 01 00 6 14 15 35 4 9 9 22 In order to ensure device reliability, the average current of the I/O on a single segment should remain below the IMAXSEG value given in the table "Absolute maximum ratings". In order to ensure device functionality, the sum of the dynamic and static current of the I/O on a single segment should remain below the IMAXSEG value given in the table "Device operating conditions". Note The MPC5746R I/O Signal Description and Input Multiplexing Tables are contained in a Microsoft Excel workbook file attached to the Reference Manual. 9 Reset pad (PORST, RESET) electrical characteristics The device implements a dedicated bidirectional reset pin (PORST). SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 18 NXP Semiconductors Reset pad (PORST, RESET) electrical characteristics NOTE PORST pin does not require active control. It is possible to implement an external pull-up to ensure correct reset exit sequence. Recommended value is 4.7 kohm. PORST can optionally be connected to an external power-on supply circuitry. No restrictions exist on reset signal slew rate apart from absolute maximum rating compliance. VDD VDDMIN VDDPOR PORST VIH VIL device start-up phase PORST undriven device reset PORST driven low device reset by by internal power-on reset forced by external circuitry internal power-on reset Figure 6. Start-up reset requirements The following figure describes device behavior depending on supply signal on PORST: 1. PORST low pulse amplitude is too low--it is filtered by input buffer hysteresis. Device remains in current state. 2. PORST low pulse duration is too short--it is filtered by a low pass filter. Device remains in current state. 3. PORST low pulse is generating a reset: * a) PORST low but initially filtered during at least WFRST. Device remains initially in current state. * b) PORST potentially filtered until WNFRST. Device state is unknown. It may either be reset or remains in current state depending on extra condition (temperature, voltage, device). * c) PORST asserted for longer than WNFRST. Device is under reset. SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 NXP Semiconductors 19 Reset pad (PORST, RESET) electrical characteristics VPORST VDD VIH VHYS VIL internal reset filtered by filtered by lowp ass filter hyst er esi s filtered by lowp ass filter WFRST 1 WFRST 2 3a unknown reset state device under hardware reset WNFRST 3b 3c Figure 7. Noise filtering on reset signal Table 12. Reset electrical characteristics Symbol Parameter Value1 Conditions Unit Min Typ Max VIH Reset Input high level TTL 3.5 V < VDD_HV_IO < 5.5 V 2.0 -- VDD_HV_IO + 0.3 V VIL Reset Input low level TTL 3.5 V < VDD_HV_IO < 3.6 V VSS - 0.3 -- 0.6 V 4.5 V < VDD_HV_IO < 5.5 V VSS - 0.3 -- 0.8 VHYS Reset Input hysteresis TTL 3.5 V < VDD_HV_IO < 5.5 V 300 -- -- mV VIH PORST Input high level CMOS 3.5 V < VDD_HV_IO < 5.5 V 0.65 * VDD_HV_IO -- VDD_HV_IO + 0.3 V VIL PORST Input low level CMOS 3.5 V < VDD_HV_IO < 5.5 V VSS - 0.3 -- 0.35 * VDD_HV_IO V VHYS PORST Input hysteresis CMOS 3.5 V < VDD_HV_IO < 5.5 V 0.1 * VDD_HV_IO -- -- mV VDD_POR Minimum supply for strong pulldown -- activation -- -- 1.2 V Table continues on the next page... SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 20 NXP Semiconductors Reset pad (PORST, RESET) electrical characteristics Table 12. Reset electrical characteristics (continued) Symbol IOL_R Parameter Value1 Conditions Strong pull-down current2 Device under power-on reset Unit Min Typ Max 14 -- -- 35 -- -- 30 -- -- 18 -- -- -- -- 120 -- -- 80 -- -- 120 -- -- 80 30 -- -- 18 -- -- mA VOL = 0.35 * VDD_HV_IO 3.5 V < VDD_HV_IO < 3.6 V Device under power-on reset VOL = 0.35 * VDD_HV_IO 4.5 V < VDD_HV_IO < 5.5 V |IWPU| Reset Weak pull-up current absolute value RESET pin A VIN = VIH = 0.65 * VDD_HV_IO 4.5 V < VDD_HV_IO < 5.5 V RESET pin VIN = VIH = 0.65 * VDD_HV_IO 3.5 V < VDD_HV_IO < 3.6 V RESET pin VIN = VIL = 0.35 * VDD_HV_IO 4.5 V < VDD_HV_IO < 5.5 V RESET pin VIN = VIL = 0.35 * VDD_HV_IO 3.5 V < VDD_HV_IO < 3.6 V |IWPD| PORST Weak pull-down current absolute value PORST pin A VIN = VIH = 0.65 * VDD_HV_IO 4.5 V < VDD_HV_IO < 5.5 V PORST pin VIN = VIH = 0.65 * VDD_HV_IO 3.5 V < VDD_HV_IO < 3.6 V PORST pin VIN = VIL = 0.35 * VDD_HV_IO 4.5 V < VDD_HV_IO < 5.5 V PORST pin VIN = VIL = 0.35 * VDD_HV_IO 3.5 V < VDD_HV_IO < 3.6 V WFRST PORST and RESET input filtered pulse -- -- -- 500 ns WNFRST PORST and RESET input not filtered pulse -- 2000 -- -- ns WFNMI ESR1 input filtered pulse -- -- -- 20 ns WNFNMI ESR1 input not filtered pulse -- 400 -- -- ns 1. An external 4.7 KOhm pull-up resistor is recommended to be used with the PORST and RESET pins for fast negation of the signals. SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 NXP Semiconductors 21 Oscillator and FMPLL 2. Strong pull-down is enabled during power up / phase0 on both pads but after that a weak pull-down is enabled on PORST and a weak pull-up is enabled on RESET. 10 Oscillator and FMPLL Two on-chip PLLs, the peripheral clock and reference PLL (PLL0), and the frequency modulated system PLL (PLL1) generate the system and auxiliary clocks from the external oscillator. PLL0_PHI0 RCOSC PLL0 PLL0_PHI1 XOSC PLL1_PHI0 PLL1 Figure 8. PLL integration Table 13. PLL0 electrical characteristics Symbol Parameter Conditions Value Unit Min Typ Max -- 8 -- 40 MHz -- 40 -- 60 % fPLL0IN PLL0 input clock1 PLL0IN PLL0 input clock duty cycle fPLL0VCO PLL0 VCO frequency -- 600 -- 1250 MHz fPLL0PHI0 PLL0 output clock PHI0 -- 4.762 -- 400 MHz tPLL0LOCK PLL0 lock time -- -- -- 110 s -- -- 3002 ps 10 periods accumulated jitter (80 MHz frequency), 6-sigma pk-pk -250 -- 250 ps 16 periods accumulated jitter (50 MHz frequency), 6-sigma pk-pk -300 -- 300 ps long term jitter -650 -- 650 ps -- -- 5 mA | PLL0PHI1SPJ| PLL0LTJ 1 PLL0_PHI1 single period jitter fPLL0IN = 20 MHz (resonator) 2 PLL0 output long term jitter fPLL0IN = 20 MHz (resonator), VCO frequency = 800 MHz fPLL0PHI1 = 40 MHz, 6sigma (< 1MHz frequency), 6sigma pk-pk IPLL0 PLL0 consumption FINE LOCK state 1. PLL0IN clock retrieved directly from either internal RCOSC or external FXOSC clock. Input characteristics are granted when using internal RCOSC or external oscillator is used in functional mode. SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 22 NXP Semiconductors Oscillator and FMPLL 2. VDD_LV noise due to application in the range VDD_LV = 1.25V (+/-5%) with frequency below PLL bandwidth (40 KHz) will be filtered. Table 14. FMPLL1 electrical characteristics Symbol fPLL1IN Parameter Value Conditions PLL1 input clock1 1 Unit Min Typ Max -- 38 -- 78 MHz -- 35 -- 65 % PLL1IN PLL1 input clock duty cycle fPLL1VCO PLL1 VCO frequency -- 600 -- 1250 MHz fPLL1PHI0 PLL1 output clock PHI0 -- 4.762 -- 200 MHz tPLL1LOCK PLL1 lock time -- -- -- 100 s fPLL1MOD PLL1 modulation frequency -- -- -- 250 kHz 0.25 -- 2 % | PLL1MOD| PLL1 modulation depth (when enabled) Center spread | Down spread 0.5 -- 4 % PLL1_PHI0 single period peak to peak jitter fPLL1PHI0 = 200 MHz, 6sigma pk-pk -- -- 5002 ps PLL1 consumption FINE LOCK state -- -- 6 mA PLL1PHI0SPJ| IPLL1 1. PLL1IN clock retrieved directly from either internal PLL0 or external XOSC clock. Input characteristics are granted when using internal PLL0 or external oscillator is used in functional mode. 2. 1.25V +/-5%, application noise below 40kHz at VDD_LV pin - no frequency modulation All oscillator specifications are valid for VDD_HV_IO_JTAG = 3.0 V to 5.5 V. Table 15. XOSC External Oscillator electrical specifications Symbol fXTAL tcst trec Parameter Conditions Crystal Frequency Range1 Crystal start-up time2, 3 Crystal recovery -- Min Max 4 8 Unit MHz -- >8 20 16MHz < freq < 40MHz (at present, freq = 20M and 40M have been validated, but still needs to be carried out for freq = 16MHz) >20 40 TJ = 150 C, 20 MHz f 40 MHz -- 5 ms -- -- 0.5 ms time4 voltage5 Value VIHEXT EXTAL input high (External Reference) VREF = 0.28 * VDD_HV_IO_JTAG VREF + 0.6 -- V VILEXT EXTAL input low voltage (External Reference) VREF = 0.28 * VDD_HV_IO_JTAG -- VREF 0.6 V pF CS_EXTAL CS_XTAL gm Total on-chip stray capacitance on EXTAL pin6 BGA 4.75 5.25 QFP 5.25 5.75 Total on-chip stray capacitance 6 on XTAL pin BGA 4.75 5.25 QFP 5.25 5.75 fXTAL 8 MHz 3 13 fXTAL 20 MHz 9 35 Oscillator Transconductance TJ = -40 C to 150 C pF mA/V Table continues on the next page... SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 NXP Semiconductors 23 Oscillator and FMPLL Table 15. XOSC External Oscillator electrical specifications (continued) Symbol Parameter Value Conditions fXTAL 40 MHz VEXTAL IXTAL 1. 2. 3. 4. 5. 6. 7. 8. Min Max 12 43 Unit Oscillation Amplitude on the EXTAL pin after startup7 TJ = -40 C to 150 C 0.5 1.6 V XTAL current7,8 TJ = -40 C to 150 C -- 14 mA The range is selectable by UTEST miscellaneous DCF clients XOSC_LF_EN and XOSC_EN_40MHZ. This value is determined by the crystal manufacturer and board design. Proper PC board layout procedures must be followed to achieve specifications. Crystal recovery time is the time for the oscillator to settle to the correct frequency after adjustment of the integrated load capacitor value. This parameter is guaranteed by design rather than 100% tested. See crystal manufacturer's specification for recommended load capacitor (CL) values.The external oscillator requires external load capacitors when operating from 8 MHz to 16 MHz. Account for on-chip stray capacitance (CS_EXTAL/CS_XTAL) and PCB capacitance when selecting a load capacitor value. When operating at 20 MHz/40 MHz, the integrated load capacitor value is selected via S/W to match the crystal manufacturer's specification, while accounting for on-chip and PCB capacitance. The capacitance on "EXTAL" and "XTAL" by internal capacitance array is controlled by the XOSC LOAD CAP SEL field of the UTEST Miscellaneous DCF client. See the DCF Records chapter of the Reference Manual. Amplitude on the EXTAL pin after startup is determined by the ALC block, i.e., the Automatic Level Control Circuit. The function of the ALC is to provide high drive current during oscillator startup, but reduce current after oscillation in order to reduce power, distortion, and RFI, and to avoid overdriving the crystal. The operating point of the ALC is dependent on the crystal value and loading conditions. IXTAL is the oscillator bias current out on the XTAL pin with both EXTAL and XTAL pins grounded. This is the maximum current during startup of the oscillator. The current after oscillation is typically in the 2-3 mA range and is dependant on the load and series resistance of the crystal. Test circuit is shown in the figure below. Table 16. Selectable load capacitance load_cap_sel[4:0] from DCF record Capacitance on EXTAL (CEXTAL)/XTAL (CXTAL) , 1, 2 (pF) 00000 1.0 00001 2.0 00010 2.9 00011 3.8 00100 4.8 00101 5.7 00110 6.6 00111 7.5 01000 8.5 01001 9.4 01010 10.3 01011 11.2 01100 12.2 01101 13.1 01110 14.0 Table continues on the next page... SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 24 NXP Semiconductors Oscillator and FMPLL Table 16. Selectable load capacitance (continued) load_cap_sel[4:0] from DCF record Capacitance on EXTAL (CEXTAL)/XTAL (CXTAL) , 1, 2 (pF) 01111 15.0 10000-11111 N/A 1. Values are determined from simulation across process corners and voltage and temperature variation. Capacitance values vary 12% across process, 0.25% across voltage, and no variation across temperature. 2. Values in this table do not include the internal stray capacitances Cxtal/Cextal. VDDOSC Bias Current ALC IXTAL XTAL EXTAL Comparator A OFF VSSOSC V VSS Tester Conditions Z=R+j L VEXTAL =0 V VXTAL =0 V ALC INACTIVE PCB GND Figure 9. Test circuit Table 17. Internal RC Oscillator electrical specifications Symbol fTarget fvar_noT fvar_T fvar_SW fTRIM Tstart_noT Tstart_T Parameter Conditions IRCOSC target frequency Value Unit Min Typ Max -- -- 16 -- MHz IRC frequency variation without temperature compensation T < 150 C -8 -- 8 % IRC frequency variation with temperature compensation T < 150 C -3 -- 3 % IRC software trimming accuracy Trimming temperature -1 -- 1 % IRC software trimming step -- -- +40/-48 -- kHz Startup time to reach within fvar_noT Factory trimming already applied -- -- 5 s Startup time to reach within fvar_T Factory trimming already applied -- -- 120 s Table continues on the next page... SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 NXP Semiconductors 25 ADC modules Table 17. Internal RC Oscillator electrical specifications (continued) Symbol Parameter Conditions IAVDD5 Current consumption on 5 V power supply IDVDD12 Current consumption on 1.2 V power supply Value Unit Min Typ Max After Tstart_T -- -- 400 A After Tstart_T -- -- 175 A 11 ADC modules This device's analog sub-system contains a total of four independent 12-bit Successive Approximation (SAR) ADCs and three independent 16-bit Sigma-Delta (S/D) ADCs. 11.1 ADC input description The following table provides the current specifications for the analog input pad weak pull-up and pull-down, and the resistance for the analog input bias/diagnostic pull up/ down. Table 18. Analog Input Leakage and Pull-Up/Down DC electrical characteristics Symbol Parameter Conditions Value Min ILK_AD Analog input leakage current Input channel off Unit Typ Max -200 -- 200 nA 130 200 280 K 65 100 140 1.4 5 8.8 -- -- 5 4.5V < VDD_HV_IO < 5.5V VSS_HV_ADV_SAR < VIN < VDD_HV_ADV_SAR VSS_HV_ADV_SD < VIN < VDD_HV_ADV_SD RPUPD Analog input bias/ diagnostic pull up/down resistance 200K 3.0V < VDD_HV_IO < 5.5V 100K 3.0V < VDD_HV_IO < 5.5V 5K 3.0V < VDD_HV_IO < 5.5V PUPD RPUPD pull up/down resistance mismatch 3.0V < VDD_HV_IO < 5.5V % SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 26 NXP Semiconductors ADC modules 11.2 SAR ADC The device provides a 12-bit Successive Approximation Register (SAR) Analog-toDigital Converter. Offset Error OSE Gain Error GE 4095 4094 4093 4092 4091 4090 ( 2) 1 LSB ideal =(VrefH-VrefL)/ 4096 = 3.3V/ 4096 = 0.806 mV Total Unadjusted Error TUE = +/- 6 LSB = +/- 4.84mV code out 7 ( 1) 6 5 (5) 4 (4) 3 (3) 2 1 (1) Example of an actual transfer curve (2) The ideal transfer curve (3) Differential non-linearity error (DNL) (4) Integral non-linearity error (INL) (5) Center of a step of the actual transfer curve 1 LSB (ideal) 0 1 2 3 Offset Error OSE 4 5 6 7 4089 4090 4091 4092 4093 4094 4095 Vin(A) (LSBideal) Figure 10. ADC characteristics and error definitions SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 NXP Semiconductors 27 ADC modules 11.2.1 Input equivalent circuit and ADC conversion characteristics EXTERNAL CIRCUIT INTERNAL CIRCUIT SCHEME VDD_HV_IO Source Filter RS RF Current Limiter RL CF VA Channel Selection Sampling RSW1 RAD CP1 CS CP2 RS Source Impedance RF Filter Resistance CF Filter Capacitance RL Current Limiter Resistance RSW1 Channel Selection Switch Impedance RAD Sampling Switch Impedance CP Pin Capacitance (two contributions, CP1 and CP2) CS Sampling Capacitance Figure 11. Input equivalent circuit Table 19. ADC conversion characteristics Symbol ,2 fCK fs tsample Conditions1 Parameter Min Typ Max Unit ADC Clock frequency (depends -- on ADC configuration) (The duty cycle depends on AD_CK3 frequency.) 20 -- 80 MHz Sampling frequency -- -- -- 1.00 MHz -- 250 -- -- ns 80 MHz Sample time4 time5 tconv Conversion 700 -- -- ns CS, 6 ADC input sampling capacitance -- -- 3 5 pF CP16 ADC input pin capacitance 1 -- -- -- 5 pF 6 ADC input pin capacitance 2 -- -- -- 0.8 pF Internal resistance of analog source VREF range = 4.5 to 5.5 V -- -- 0.3 k 875 Internal resistance of analog source -- -- -- 825 INL Integral non-linearity -- -2 -- 2 LSB DNL Differential non-linearity -- -1 -- 1 LSB OFS7 Offset error -- -6 -- 6 LSB GNE7 Gain error -- -6 -- 6 LSB Max leakage 150 C -- -- 300 nA CP2 6 RSW1 6 RAD Input (double ADC channel) VREF range = 3.0 to 3.6 V -- -- Table continues on the next page... SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 28 NXP Semiconductors ADC modules Table 19. ADC conversion characteristics (continued) Symbol Parameter Conditions1 Min Typ Max Unit SNR Signal-to-noise ratio VREF = 3.3 V, Fin 125 kHz 66 -- -- dB SNR Signal-to-noise ratio VREF = 5.0 V, Fin 125 kHz 68 -- -- dB THD Total harmonic distortion @ 125 kHz 65 70 -- dB ENOB8 Effective number of bits Fin < 125 kHz 10.5 -- -- bits SINAD Signal-to-noise and distortion Fin < 125 kHz TUEIS1WINJ Total unadjusted error for IS1WINJ Without current injection -6 (6.02*ENOB)+1.76 -- 6 LSB dB TUEIS1WWINJ Total unadjusted error for IS1WWINJ Without current injection -6 -- 6 LSB IDD_VDDA Maximum operating current on VDDA Tj = 150C VDD_LV_COR = 1.32 V -- 3.7 5 mA IDD_VDDR Maximum operating current on VREF Tj = 150C VDD_LV_COR = 1.32 V -- 150 600 A VBG_REF, 9 Band gap reference for self test Trimmed, INPSAMP=0xFF 1.164 --10 1.236 V 1. VDD_HV_IO = 3.3 V -5%,+10%, TJ = -40 to +150 C, unless otherwise specified, and analog input voltage from VAGND to VAREF 2. SAR ADC performance is not guaranteed when IRC is used as clock source for PLL0 to generate SAR ADC clock. 3. AD_CK clock is always half of the ADC module input clock defined via the auxiliary clock divider for the ADC. 4. During the sample time the input capacitance CS can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within tsample. After the end of the sample time tsample, changes of the analog input voltage have no effect on the conversion result. Values for the sample clock tsample depend on programming. 5. This parameter does not include the sample time tsample, but only the time for determining the digital result and the time to load the result register with the conversion result. 6. See the above figure. 7. Subject to change with additional -40C characterization on final silicon version. 8. Below 4.5V, ENOB - 9.5b, THD- 60dB at Fin= 125KHz 9. Band gap reference only applies to Cut 2 silicon. 10. Minimum and maximum values are typical +/-3% NOTE * For spec complaint operation, do not expose clock sources, including crystal oscillator, IRC, PLL0, and PLL1 on the CLKOUT pads while the SAR ADC is converting. * The ADC performance specifications are not guaranteed if two or more ADCs simultaneously sample the same shared channel. 11.3 S/D ADC The SD ADCs are Sigma Delta 16-bit analog-to-digital converters with 333 Ksps maximum output rate. SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 NXP Semiconductors 29 ADC modules Functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect device reliability or cause permanent damage to the device. Table 20. SDn ADC electrical specification Symbol VIN Parameter Conditions ADC input signal -- Input range peak to peak Single ended. Value Min Typ Max 0 -- VDD_HV_ Unit V ADV_SD VIN_PK2PK1 VIN_PK2PK = VINP2 - VINM, 3 VDD_HV_ADR_SD/GAIN VINM = VSS_HV_ADR_SD V Single ended. VINM = 0.5*VDD_HV_ADR_SD 0.5*VDD_HV_ADR_SD GAIN = 1 Single ended. VINM = 0.5*VDD_HV_ADR_SD VDD_HV_ADR_SD/GAIN GAIN = 2,4,8,16 Differential 0 < VIN < VDD_HV_IO_MAIN VDD_HV_ADR_SD/GAIN fADCD_M S/D clock frequency TJ < 150 C 4 14.4 16 MHz fADCD_S Conversion rate TJ < 150 C -- -- 333 ksps Oversampling ratio Internal modulator 24 -- 256 -- -- RESOLUTION 164 S/D register resolution 2's complement notation bit GAIN ADC gain Defined through ADC_SD[PGA] register. Only integer power of 2 are valid gain. 1 -- 16 -- |GAIN| Absolute value of the ADC gain error5 Before calibration (applies to gain settings =1) -- -- 1 % After calibration6 -- -- 0.1 % -- -- 0.2 % -- 10* 20 mV VDD_HV_ADR_SD < 5% VDD_HV_ADV_SD < 10% TJ < 50 C After calibration6 VDD_HV_ADR_SD < 5% VDD_HV_ADV_SD < 10% TJ < 150 C VOFFSET Conversion offset Before calibration (applies to all gain settings - 1, 2, 4, 8, 16) After calibration6 SNRDIFF150, 7 Signal to noise ratio in differential mode 150 ksps output rate 4.5 < VDD_HV_ADV_SD < 5.57 (1+1/ gain) -- -- 5 mV 78 -- -- dB VDD_HV_ADR_D = VDD_HV_ADV_D Table continues on the next page... SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 30 NXP Semiconductors ADC modules Table 20. SDn ADC electrical specification (continued) Symbol Parameter Conditions Value Min Typ Max 75 -- -- 72 -- -- 69 -- -- 65 -- -- 72 -- -- 69 -- -- 66 -- -- Unit GAIN = 1 TJ < 150 C 4.5 < VDD_HV_ADV_SD < 5.57 VDD_HV_ADR_SD = VDD_HV_ADV_SD GAIN = 2 TJ < 150 C 4.5 < VDD_HV_ADV_SD < 5.57 VDD_HV_ADR_SD = VDD_HV_ADV_SD GAIN = 4 TJ < 150 C 4.5 < VDD_HV_ADV_SD < 5.57 VDD_HV_ADR_SD = VDD_HV_ADV_SD GAIN = 8 TJ < 150 C 4.5 < VDD_HV_ADV_SD < 5.57 VDD_HV_ADR_SD = VDD_HV_ADV_SD GAIN = 16 TJ < 150 C SNRDIFF3337 Signal to noise ratio in differential mode 333 ksps output rate 4.5 < VDD_HV_ADV_SD < 5.57 dB VDD_HV_ADR_SD = VDD_HV_ADV_SD GAIN = 1 TJ < 150 C 4.5 < VDD_HV_ADV_SD < 5.57 VDD_HV_ADR_SD = VDD_HV_ADV_SD GAIN = 2 TJ < 150 C 4.5 < VDD_HV_ADV_SD < 5.57 VDD_HV_ADR_SD = VDD_HV_ADV_SD GAIN = 4 TJ < 150 C Table continues on the next page... SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 NXP Semiconductors 31 ADC modules Table 20. SDn ADC electrical specification (continued) Symbol Parameter Conditions 4.5 < VDD_HV_ADV_SD < 5.57 Value Min Typ Max 63 -- -- 60 -- -- 72 -- -- 69 -- -- 66 -- -- 63 -- -- 55 -- -- Unit VDD_HV_ADR_SD = VDD_HV_ADV_SD GAIN = 8 TJ < 150 C 4.5 < VDD_HV_ADV_SD < 5.57 VDD_HV_ADR_SD = VDD_HV_ADV_SD GAIN = 16 TJ < 150 C SNRSE1507 Signal to noise ratio in 4.5 < VDD_HV_ADV_SD < 5.57 single ended mode 150 VDD_HV_ADR_SD = ksps output rate VDD_HV_ADV_SD dB GAIN = 1 TJ < 150 C 4.5 < VDD_HV_ADV_SD < 5.57 VDD_HV_ADR_SD = VDD_HV_ADV_SD GAIN = 2 TJ < 150 C 4.5 < VDD_HV_ADV_SD < 5.57 VDD_HV_ADR_SD = VDD_HV_ADV_SD GAIN = 4 TJ < 150 C 4.5 < VDD_HV_ADV_SD < 5.57 VDD_HV_ADR_SD = VDD_HV_ADV_SD GAIN = 8 TJ < 150 C 4.5 < VDD_HV_ADV_SD < 5.57 VDD_HV_ADR_DS = VDD_HV_ADV_SD GAIN = 16 TJ < 150 C Table continues on the next page... SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 32 NXP Semiconductors ADC modules Table 20. SDn ADC electrical specification (continued) Symbol THDDIFF150 Parameter Conditions Total Harmonic Distortion in differential mode 150 ksps output rate 4.5 < VDD_HV_ADV_SD < 5.57 Value Min Typ Max 65 -- -- 68 -- -- 74 -- -- 80 -- -- 80 -- -- 65 -- -- 68 -- -- 74 -- -- Unit dB VDD_HV_ADR_D = VDD_HV_ADV_D GAIN = 1 TJ < 150 C 4.5 < VDD_HV_ADV_SD < 5.57 VDD_HV_ADR_SD = VDD_HV_ADV_SD GAIN = 2 TJ < 150 C 4.5 < VDD_HV_ADV_SD < 5.57 VDD_HV_ADR_SD = VDD_HV_ADV_SD GAIN = 4 TJ < 150 C 4.5 < VDD_HV_ADV_SD < 5.57 VDD_HV_ADR_SD = VDD_HV_ADV_SD GAIN = 8 TJ < 150 C 4.5 < VDD_HV_ADV_SD < 5.57 VDD_HV_ADR_SD = VDD_HV_ADV_SD GAIN = 16 TJ < 150 C THDDIFF333 Total Harmonic Distortion in differential mode 333 ksps output rate 4.5 < VDD_HV_ADV_SD < 5.57 dB VDD_HV_ADR_SD = VDD_HV_ADV_SD GAIN = 1 TJ < 150 C 4.5 < VDD_HV_ADV_SD < 5.57 VDD_HV_ADR_SD = VDD_HV_ADV_SD GAIN = 2 TJ < 150 C 4.5 < VDD_HV_ADV_SD < 5.57 VDD_HV_ADR_SD = VDD_HV_ADV_SD Table continues on the next page... SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 NXP Semiconductors 33 ADC modules Table 20. SDn ADC electrical specification (continued) Symbol Parameter Conditions Value Min Typ Max 80 -- -- 77 -- -- 68 -- -- 68 -- -- 68 -- -- 68 -- -- 68 -- -- Unit GAIN = 4 TJ < 150 C 4.5 < VDD_HV_ADV_SD < 5.57 VDD_HV_ADR_SD = VDD_HV_ADV_SD GAIN = 8 TJ < 150 C 4.5 < VDD_HV_ADV_SD < 5.57 VDD_HV_ADR_SD = VDD_HV_ADV_SD GAIN = 16 TJ < 150 C THDSE150 Total Harmonic Distortion in single ended mode 150 ksps output rate 4.5 < VDD_HV_ADV_SD < 5.57 dB VDD_HV_ADR_SD = VDD_HV_ADV_SD GAIN = 1 TJ < 150 C 4.5 < VDD_HV_ADV_SD < 5.57 VDD_HV_ADR_SD = VDD_HV_ADV_SD GAIN = 2 TJ < 150 C 4.5 < VDD_HV_ADV_SD < 5.57 VDD_HV_ADR_SD = VDD_HV_ADV_SD GAIN = 4 TJ < 150 C 4.5 < VDD_HV_ADV_SD < 5.57 VDD_HV_ADR_SD = VDD_HV_ADV_SD GAIN = 8 TJ < 150 C 4.5 < VDD_HV_ADV_SD < 5.57 VDD_HV_ADR_DS = VDD_HV_ADV_SD GAIN = 16 TJ < 150 C Table continues on the next page... SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 34 NXP Semiconductors ADC modules Table 20. SDn ADC electrical specification (continued) Symbol SINADDIFF150 Parameter Conditions Signal to Noise Distortion Ratio in differential mode 150 ksps output rate 4.5 < VDD_HV_ADV_SD < 5.57 Value Min Typ Max 72 -- -- 72 -- -- 69 -- -- 68.8 -- -- 64.8 -- -- 66 -- -- 66 -- -- 63 -- -- Unit dB VDD_HV_ADR_D = VDD_HV_ADV_D GAIN = 1 TJ < 150 C 4.5 < VDD_HV_ADV_SD < 5.57 VDD_HV_ADR_SD = VDD_HV_ADV_SD GAIN = 2 TJ < 150 C 4.5 < VDD_HV_ADV_SD < 5.57 VDD_HV_ADR_SD = VDD_HV_ADV_SD GAIN = 4 TJ < 150 C 4.5 < VDD_HV_ADV_SD < 5.57 VDD_HV_ADR_SD = VDD_HV_ADV_SD GAIN = 8 TJ < 150 C 4.5 < VDD_HV_ADV_SD < 5.57 VDD_HV_ADR_SD = VDD_HV_ADV_SD GAIN = 16 TJ < 150 C SINADDIFF333 Signal to Noise Distortion Ratio in differential mode 333 ksps output rate 4.5 < VDD_HV_ADV_SD < 5.57 dB VDD_HV_ADR_SD = VDD_HV_ADV_SD GAIN = 1 TJ < 150 C 4.5 < VDD_HV_ADV_SD < 5.57 VDD_HV_ADR_SD = VDD_HV_ADV_SD GAIN = 2 TJ < 150 C 4.5 < VDD_HV_ADV_SD < 5.57 VDD_HV_ADR_SD = VDD_HV_ADV_SD Table continues on the next page... SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 NXP Semiconductors 35 ADC modules Table 20. SDn ADC electrical specification (continued) Symbol Parameter Conditions Value Min Typ Max 62 -- -- 59 -- -- 66 -- -- 66 -- -- 63 -- -- 62 -- -- 54 -- -- Unit GAIN = 4 TJ < 150 C 4.5 < VDD_HV_ADV_SD < 5.57 VDD_HV_ADR_SD = VDD_HV_ADV_SD GAIN = 8 TJ < 150 C 4.5 < VDD_HV_ADV_SD < 5.57 VDD_HV_ADR_SD = VDD_HV_ADV_SD GAIN = 16 TJ < 150 C SINADSE150 Signal to Noise 4.5 < VDD_HV_ADV_SD < 5.57 Distortion Ratio in single VDD_HV_ADR_SD = ended mode 150 ksps VDD_HV_ADV_SD output rate dB GAIN = 1 TJ < 150 C 4.5 < VDD_HV_ADV_SD < 5.57 VDD_HV_ADR_SD = VDD_HV_ADV_SD GAIN = 2 TJ < 150 C 4.5 < VDD_HV_ADV_SD < 5.57 VDD_HV_ADR_SD = VDD_HV_ADV_SD GAIN = 4 TJ < 150 C 4.5 < VDD_HV_ADV_SD < 5.57 VDD_HV_ADR_SD = VDD_HV_ADV_SD GAIN = 8 TJ < 150 C 4.5 < VDD_HV_ADV_SD < 5.57 VDD_HV_ADR_DS = VDD_HV_ADV_SD GAIN = 16 TJ < 150 C Table continues on the next page... SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 36 NXP Semiconductors ADC modules Table 20. SDn ADC electrical specification (continued) Symbol Parameter Conditions SFDR Spurious free dynamic range ZDIFF Differential input impedance8, 9 ZCM Common Mode input impedance9, 10 Value Unit Min Typ Max Any GAIN 60 -- -- dB GAIN = 1 1000 1250 1500 k GAIN = 2 600 800 1000 GAIN = 4 300 400 500 GAIN = 8 200 250 300 GAIN = 16 200 250 300 GAIN = 1 1400 1800 2200 GAIN = 2 1000 1300 1600 GAIN = 4 700 950 1150 GAIN = 8 500 650 800 GAIN = 16 500 650 800 k RBIAS Bare bias resistance -- 110 144 180 k VINTCM Common Mode input reference voltage11 -- -12 -- +12 % Bias voltage -- -- VDD_ HV_ -- V VBIAS ADR_S D/2 VBIAS Bias voltage accuracy -- -2.5 -- +2.5 % CMRR Common mode rejection ratio -- 55 -- -- dB Anti-aliasing filter External series resistance -- -- 20 k Filter capacitances 220 -- -- pF 0.333 * fADCD_S -1 -- 1 % [0.5 * fADCD_S, 40 -- -- dB 45 -- -- 50 -- -- 55 -- -- [2.5 * fADCD_S, fADCD_M/2] 60 -- -- Within pass band - Tclk is 2/fADCD_M -- -- -- -- OSR = 24 -- -- 235.5 Tclk OSR = 28 -- -- 275 OSR = 32 -- -- 314.5 OSR = 36 -- -- 354 -- RIPPLE -- Pass band ripple 12 Stop band attenuation 1.0 * fADCD_S] [1.0 * fADCD_S, 1.5 * fADCD_S] [1.5 * fADCD_S, 2.0 * fADCD_S] [2.0 * fADCD_S, 2.5 * fADCD_S] GROUP Group delay Table continues on the next page... SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 NXP Semiconductors 37 ADC modules Table 20. SDn ADC electrical specification (continued) Symbol Parameter Conditions Value Typ Max OSR = 40 -- -- 393.5 OSR = 44 -- -- 433 OSR = 48 -- -- 472.5 OSR = 56 -- -- 551.5 OSR = 64 -- -- 630.5 OSR = 72 -- -- 709.5 OSR = 75 -- -- 696 OSR = 80 -- -- 788.5 OSR = 88 -- -- 867.5 OSR = 96 -- -- 946.5 OSR = 112 -- -- 1104.5 OSR = 128 -- -- 1262.5 OSR = 144 -- -- 1420.5 OSR = 160 -- -- 1578.5 OSR = 176 -- -- 1736.5 OSR = 192 -- -- 1894.5 OSR = 224 -- -- 2210.5 OSR = 256 -- -- 2526.5 -0.5/ -- +0.5/ Distortion within pass band fADCD_S fHIGH High pass filter 3dB frequency Enabled tSTARTUP Start-up time from power down state -- tLATENCY tSETTLING Unit Min -- -- fADCD_S 10e-5* -- -- fADCD_S -- -- 100 s Latency between input HPF = ON data and converted data when input mux does note change13 HPF = OFF -- -- GROUP + fADCD_S -- -- -- GROUP -- Settling time after mux change -- -- 2* -- Analog inputs are muxed GROUP HPF = ON + 3*fADCD_ S HPF = OFF -- -- 2* GROUP -- + 2*fADCD_ S tODRECOVERY Overdrive recovery time After input comes within range from saturation -- -- -- GROUP + fADCD_S HPF = ON HPF = OFF 2* -- -- 2* -- GROUP Table continues on the next page... SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 38 NXP Semiconductors Temperature sensor Table 20. SDn ADC electrical specification (continued) Symbol CS_D IBIAS IADV_D IADR_D Parameter Conditions S/D ADC sampling capacitance after sampling switch14 Value Unit Min Typ Max GAIN = 1, 2, 4, 8 -- -- 75*GAI N fF GAIN = 16 -- -- 600 fF Bias consumption At least 1 ADCD enabled -- -- 3.5 mA ADCD supply consumption ADCD enabled -- 2.5 8 mA Reference current for one SDADC ADCD enabled -- 10 50 A 1. For input voltage above the maximum and below the clamp voltage of the input pad, there is no latch-up concern, and the signal will only be 'clipped'. 2. VINP is the input voltage applied to the positive terminal of the SD ADC. 3. VINM is the input voltage applied to the negative terminal of the SD ADC. 4. For Gain=16, SDADC Resolution is 15 bit. 5. Offset and gain error due to temperature drift can occur in either direction (+/-) for each of the SDADCs on the device. 6. Calibration of gain is possible when gain = 1. Offset Calibration should be done with respect to 0.5*VDD_HV_ADR_SD for differential "differential mode" and single ended mode with negative input=0.5*VDD_HV_ADR_SD ". Offset Calibration should be done with respect to 0 for "single ended mode with negative input=0". Both Offset and Gain Calibration is guaranteed for +/-5% variation of VDD_HV_ADR_SD, +/-10% variation of VDD_HV_ADV_SD, +/-50 C temperature variation. 7. S/D ADC is functional in the range 3.6V < VDD_HV_ADV_SD < 4.5V and 3.0V < VDD_HV_ADR_SD < 4.5 V, SNR paramter degrades by 9 dB. 8. Input impedance in differential mode ZIN = ZDIFF 9. Input impedance given at fADCD_M = 16 MHz. Impedance is inversely proportional to SDADC clock frequency. ZDIFF (fADCD_M) = (16 MHz / fADCD_M) * ZDIFF, ZCM (fADCD_M) = (16 MHz / fADCD_M) * ZCM. 10. Input impedance in single-ended mode ZIN = (2 * ZDIFF * ZCM) / (ZDIFF + ZCM) 11. VINTCM is the Common Mode input reference voltage for the SDADC. It has a nominal value of (VRH_SD - VRL_SD) / 2. 12. The 1% passband ripple specification is equivalent to 20 * log10 (0.99) = 0.873 dB. 13. Propagation of the information from the pin to the register CDR[CDATA] and flags SFR[DFEF], SFR[DFFF] is given by the different modules that need to be crossed: delta/sigma filters, high pass filter, fifo module, clock domain synchronizers. The time elapsed between data availability at pin and internal S/D module registers is given by the following formula: REGISTER LATENCY = tLATENCY + 0.5/fADCD_S + 2 (~+1)/fADCD_M + 2(~+1)/fPBRIDGEx_CLK where fADCD_S is the afterdecimation ADC output data rate, fADCD_M/2 is the modulator sampling rate and fPBRIDGEx_CLK is the frequency of the peripheral bridge clock feeds to the ADC S/D module. The (~+1) symbol refers to the number of clock cycles uncertainty (from 0 to 1 clock cycle) to be added due to resynchronization of the signal during clock domain crossing. Some further latency may be added by the target module (core, DMA, interrupt) controller to process the data received from the ADC S/D module. 14. This capacitance does not include pin capacitance, that can be considered together with external capacitance, before sampling switch. 12 Temperature sensor The following table describes the temperature sensor electrical characteristics. SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 NXP Semiconductors 39 LVDS fast asynchronous serial transmission (LFAST) pad electrical characteristics Table 21. Temperature sensor electrical characteristics Symbol -- Parameter Conditions Value Unit Min Typ Max -40 -- 150 C Junction temperature monitoring range -- TSENS Sensitivity -- -- 5.18 -- mV/C TACC Accuracy -- -7 -- 7 C 13 LVDS fast asynchronous serial transmission (LFAST) pad electrical characteristics The LFAST pad electrical characteristics apply to both the LFAST and high-speed debug serial interfaces on the device. The same LVDS pad is used for the Microsecond Channel (MSC) and DSPI LVDS interfaces, with different characteristics given in the following tables. 13.1 LFAST interface timing diagrams SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 40 NXP Semiconductors LVDS fast asynchronous serial transmission (LFAST) pad electrical characteristics Signal excursions above this level NOT allowed Max. common mode input at RX 1743 mV 1600 mV I VOD I Maximum Differential Voltage 285 mV p-p (LFAST) 400 mV p-p (MSC/DSPI) Minimum Data Bit Time Opening = 0.55 * T (LFAST) 0.50 * T (MSC/SIPI) "No-Go" Area VOS = 1.2 V +/- 10% TX common mode IVOD I Minimum Differential Voltage = 100 mV p-p (LFAST) 150 mV p-p (MSC/SIPI) Data Bit Period T = 1 / FDATA Min. common mode input at RX Signal excursions below this level NOT allowed 150 mV 0V Figure 12. LFAST timing definition SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 NXP Semiconductors 41 LVDS fast asynchronous serial transmission (LFAST) pad electrical characteristics H Ifast_pwr_down L tPD2NM_TX Differential Data Lines TX pad_p/pad_n Data Valid Figure 13. Power-down exit time VIH Differential Data Lines TX 90% 10% pad_p/pad_n VIL trise tfall Figure 14. Rise/fall time 13.2 LFAST and MSC /DSPI LVDS interface electrical characteristics The following table contains the electrical characteristics for the LFAST interface. The LVDS pad electrical characteristics in this table apply to both the LFAST and Highspeed Debug (HSD) LVDS pad, and the MSC/DSPI LVDS pad except where noted in the conditions. All LVDS pad electrical characteristics are valid from -40 C to 150 C. SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 42 NXP Semiconductors LVDS fast asynchronous serial transmission (LFAST) pad electrical characteristics Table 22. LVDS pad startup and receiver electrical characteristics Symbol Value Parameter Conditions tPD2NM_TX Transmitter startup time (power down to normal mode)1 -- tSM2NM_TX Transmitter startup time (sleep mode to normal mode)2 Not applicable to the MSC/ DSPI LVDS pad tPD2NM_RX Receiver startup time (power down to normal mode)3 -- tPD2SM_RX Receiver startup time (power down to sleep mode)4 ILVDS_BIAS LVDS bias current consumption Unit Min Typ Max -- 0.4 0.55 s -- 0.2 0.5 s -- 20 40 ns Not applicable to the MSC/ DSPI LVDS pad -- 20 50 ns Tx or Rx enabled -- -- 0.95 mA 47.5 50 52.5 95 100 105 TRANSMISSION LINE CHARACTERISTICS (PCB Track) Z0 ZDIFF Transmission line characteristic impedance -- Transmission line differential impedance -- RECEIVER VICOM Common mode voltage -- 0.155 -- 1.66 V |VI| Differential input voltage -- 100 -- -- mV VHYS Input hysteresis -- 25 -- -- mV Terminating resistance VDD_HV_IO = 5.0 V 10% 80 100 120 VDD_HV_IO = 3.3 V 10% 80 115 150 -- -- 3.5 6.0 pF Enabled -- -- 0.5 mA RIN CIN ILVDS_RX Differential input capacitance7 Receiver DC current consumption 1. Total transmitter startup time from power down to normal mode is tSTRT_BIAS + tPD2NM_TX + 2 peripheral bridge clock periods. The LFAST and High-Speed Debug LFAST pad electrical characteristics are based on worst case internal capacitance values. 2. Total transmitter startup time from sleep mode to normal mode is tSM2NM_TX + 2 peripheral bridge clock periods. Bias block remains enabled in sleep mode. All LFAST and High-Speed Debug LVDS pad electrical characteristics are valid from -40 C to 150 C. 3. Total receiver startup time from power down to normal mode is tSTRT_BIAS + tPD2NM_RX + 2 peripheral bridge clock periods. 4. Total receiver startup time from power down to sleep mode is tPD2SM_RX + 2 peripheral bridge clock periods. Bias block remains enabled in sleep mode. 5. Absolute min = 0.15 V - (285 mV/2) = 0 V 6. Absolute max = 1.6 V + (285 mV/2) = 1.743 V 7. Total internal capacitance including receiver and termination, co-bonded GPIO pads, and package contributions. Table 23. LFAST transmitter electrical characteristics Symbol Parameter Conditions Value Min Typ Max Unit fDATA Data rate -- -- -- 320 Mbps VOS Common mode voltage -- 1.08 -- 1.32 V |VOD| Differential output voltage swing (terminated)1, 2 -- 100 200 285 mV -- 0.26 -- 1.5 ns tTR Rise/Fall time (10%-90% of swing) 3, 4 Table continues on the next page... SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 NXP Semiconductors 43 LVDS fast asynchronous serial transmission (LFAST) pad electrical characteristics Table 23. LFAST transmitter electrical characteristics (continued) Symbol CL Parameter Conditions External lumped differential load capacitance1 ILVDS_TX Transmitter DC current consumption Value Min Typ Max VDD_HV_IO = 4.5 V -- -- 10.0 VDD_HV_IO = 3.0 V -- -- 8.5 Enabled -- -- 3.2 Unit pF mA 1. Valid for maximum data rate fDATA. Value given is the capacitance on each terminal of the differential pair, as shown in the figure below. 2. Valid for maximum external load CL. 3. The LFAST and High-Speed Debug LFAST pad electrical characteristics are based on worst case internal capacitance values. 4. All LFAST and High-Speed Debug LVDS pad electrical characteristics are valid from -40 C to 150 C. The MSC and DSPI LVDS pad electrical characteristics are based on the application circuit and typical worst case internal capacitance values given in Figure 14. All MSC and DSPI LVDS pad electrical characteristics are valid from -40 C to 150 C. Table 24. MSC/DSPI LVDS transmitter electrical characteristics Symbol Parameter Conditions Value Min Typ Max Unit Data Rate fDATA Data rate -- -- -- 80 Mbps VOS Common mode voltage -- 1.08 -- 1.32 V |VOD| Differential output voltage swing (terminated)1, 2 -- 150 200 400 mV -- 0.8 -- 5.7 ns VDD_HV_IO = 4.5 V -- -- 40 pF VDD_HV_IO = 3.0 V -- -- 30 Enabled -- -- 4.0 tTR CL Rise/Fall time (10%-90% of swing) External lumped differential load 3, 4 capacitance3 ILVDS_TX Transmitter DC current consumption mA 1. Valid for maximum data rate fDATA. Value given is the capacitance on each terminal of the differential pair, as shown in the figure below. 2. Valid for maximum external load CL. 3. The LFAST and High-Speed Debug LFAST pad electrical characteristics are based on worst case internal capacitance values. 4. All LFAST and High-Speed Debug LVDS pad electrical characteristics are valid from -40 C to 150 C. NOTE For optimum LVDS performance, it is recommended to set the neighbouring GPIO pads to use Weak Drive. SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 44 NXP Semiconductors LFAST PLL electrical characteristics bond pad GPIO Driver CL 1pF 2.5pF 100 termination LVDS Driver bond pad GPIO Driver CL 1pF 2.5pF Die Package PCB Figure 15. LVDS pad external load diagram 14 LFAST PLL electrical characteristics The following table contains the electrical characteristics for the LFAST PLL. The specifications in this table apply to both the interprocessor bus and debug LFAST interfaces. Table 25. LFAST PLL electrical characteristics Symbol Parameter fRF_REF PLL reference clock frequency ERRREF DCREF PN fVCO tLOCK PERREF Conditions Value Unit Min Nominal Max -- 10 -- 26 MHz PLL reference clock frequency error -- -1 -- 1 % PLL reference clock duty cycle -- 45 -- 55 % fRF_REF = 20 MHz -- -- -58 dBc fRF_REF = 10 MHz -- -- -64 -- -- 6401 -- MHz -- -- -- 40 s Single period, -- -- 300 ps Integrated phase noise (single side band) PLL VCO frequency PLL phase lock2 Input reference clock single period jitter (peak to peak) fRF_REF = 10 MHz Table continues on the next page... SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 NXP Semiconductors 45 Aurora LVDS electrical characteristics Table 25. LFAST PLL electrical characteristics (continued) Symbol Parameter Conditions Long term, Value Unit Min Nominal Max -500 -- 500 ps -- 550 -- ps fRF_REF = 10 MHz PEREYE Output Eye Jitter (peak to peak)3 -- 1. The 640 MHz frequency is achieved with a 10 MHz or 20 MHz reference clock. With a 26 MHz reference, the VCO frequency is 624 MHz. 2. The time from the PLL enable bit register write to the start of phase locks is maximum 2 clock cycles of the peripheral bridge clock that is connected to the PLL on the device. 3. Measured at the transmitter output across a 100 Ohm termination resistor on a device evaluation board. Refer to the figure below. Data Bit Period, T TX+ TXEye Jitter Eye Jitter Figure 16. LFAST output 'eye' diagram 15 Aurora LVDS electrical characteristics The following table describes the Aurora LVDS electrical characteristics. All Aurora electrical characteristics are valid from -40 C to 150 C. All specifications valid for maximum transmit data rate FTX. SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 46 NXP Semiconductors Power management PMC POR LVD sequencing Table 26. Aurora LVDS electrical characteristics Symbol Parameter Conditions Value1 Min Typ Max Unit Transmitter FTX Transmit Data Rate -- -- -- 1.25 Gbps |VOD_LVDS| Differential output voltage swing (terminated)2 -- 400 600 800 mV tTR_LVDS Rise/Fall time (10%-90% of swing) -- 60 -- -- ps RTV_L Differential Terminating resistance -- 81 100 120 -- -- 1003 dB TLoss Transmission Line Loss due to loading effects -- Transmission line characteristics (PCB track) LLINE Transmission line length -- -- -- 20 cm ZLINE Transmission line characteristic impedance -- 45 50 55 CAC External AC Coupling Capacitance Values are nominal, valid up to 50% 100 -- 270 pF Receiver FRX Receive Data Rate -- -- -- 1.25 GHz |VI_L| Differential input voltage -- 200 -- 1000 mV RRV_L Terminating resistance VDD_HV_IO_BD = 5V 10% 81 100 120 1. All specifications valid for maximum transmit data rate FTX. 2. The minimum value of 400 mV is only valid for differential resistance (RV_L) = 99 ohm to 101 ohm. The differential output voltage swing tracks with the value of RV_L. 3. Transimission line loss maximum value is specified for the maximum drive level of the Aurora transmit pad. 16 Power management PMC POR LVD sequencing 16.1 Power management electrical characteristics The power management module monitors the different power supplies. It also generates the internal supplies that are required for correct device functionality. The power management is supplied by the VDD_HV_PMC supply. 16.1.1 Recommended power transistors The following NPN transistors are recommended for use with the on-chip voltage regulator controller: ON SemiconductorTM NJD2873. The collector of the external transistor is preferably connected to the same voltage supply source as the VDD_HV_PMC pin. SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 NXP Semiconductors 47 Power management PMC POR LVD sequencing The following table describes the characteristics of the power transistors. Table 27. Recommended operating characteristics Symbol Parameter Value Unit hFE DC current gain (Beta) 60-550 -- PD Absolute minimum power dissipation 1.60 W ICMaxDC Maximum DC collector current 2.0 A VCESAT Collector to emitter saturation voltage 300 mV VBE Base to emitter voltage 0.95 V VC Minimum voltage at transistor collector 2.5 V 16.1.2 Power management integration In order to ensure correct functionality of the device, it is recommended to follow the integration scheme shown below. SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 48 NXP Semiconductors Power management PMC POR LVD sequencing CHV_PMC VSS VDD_HV_PMC VDD_HV_FLA CHV_FLA VDD_HV_IO One capacitance near each VDD_LV pin One capacitance near each VDD_HV pin VSS_HV_ADV_SAR VDD_HV_ADV_SAR VSS_HV_ADV_SD CLV1 VSS CHV_ADC_SAR 2 CHV_ADC_D VSS VDD_HV_ADV_SD n x CHV_IO2 1 VDD_LV RAINIER Figure 17. Recommended supply pin circuits The following table describes the supply stability capacitances required on the device for proper operation. Table 28. Device power supply integration Symbol Parameter Conditions Value1 Min Typ Max Unit Minimum VDD_LV external bulk capacitance, -- 4.7 -- -- F Minimum VDD_HV_PMC external bulk capacitance 2, 4 -- 4.7 -- -- F CHV_IO Minimum VDD_HV_IO external 2 capacitance -- 4.7 -- -- F CHV_FLA Minimum VDD_HV_FLA external capacitance, 5 -- CLV CHV_PMC 2, 3 CHV_ADC_SA Minimum VDD_HV_ADV_SAR external capacitance, 6 R 2.0 10 -- F -- F Table continues on the next page... SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 NXP Semiconductors 49 Power management PMC POR LVD sequencing Table 28. Device power supply integration (continued) Symbol Parameter Value1 Conditions CHV_ADC_SD Minimum VDD_HV_ADV_SD external capacitance, 7 Min Typ Max 1 2.2 -- Unit F 1. See the above figure for capacitor integration. 2. Recommended X7R or X5R ceramic low ESR capacitors, 15% variation over process, voltage, temperature, and aging. 3. Each VDD_LV pin requires both a 47nF and 0.01F capacitor for high-frequency bypass and EMC requirements. Remaining capacitance to meet minimum CLV requirement should be placed near the emitter of NPN ballast (if using internal regulation mode), or it should be evenly distributed across VDD_LV pins (if using external regulation mode). 4. Each VDD_HV_PMC pin requires both a 47nF and 0.01F capacitor for high-frequency bypass and EMC requirements. 5. The recommended flash regulator composition capacitor is 1.5F typical X7R or X5R, with -50% and +35% as min and max. This puts the min cap at 0.75 F. 6. For noise filtering it is recommended to add high frequency bypass capacitors of three each 0.1 F and three each 1nF between VDD_HV_ADV_SAR and VSS_HV_ADV_SAR. These capacitors need to be placed very close to the MCU pins/balls to have minimum PCB routing between pin/ball and the capacitors. 7. For noise filtering it is recommended to add a high frequency bypass capacitance of 0.1 F between VDD_HV_ADV_SD and VSS_HV_ADV_SD. 16.1.3 Regulator example for the NJD2873 transistor VDD_HV_PMC The bypass transistor MUST be operated out of saturation region. VRC_CTL MCU VDD_LV Mandatory decoupling capacitor network C1 VSS VRC_CTL capacitor: may or may not be required Figure 18. Regulator example SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 50 NXP Semiconductors Power management PMC POR LVD sequencing VDDIO Lb= 50n, 100n -- + Cc= 4u, 14u ESR= 15m, 150m Beta= 120, 360 Vrctl Cb= 0.6u, 1.4u ESR= 15m, 150m ILoad 3.3V or Vcollector Vdd_core Le= 50n, 100n Vref Lc = 50n, 100n 16.1.4 Regulator example for the 2SCR574d transistor Cl= 4u, 14u ESR= 15m, 150m Figure 19. Regulator example 16.1.5 Device voltage monitoring The LVD/HVDs for the device and their levels are given in the following table. Voltage monitoring threshold definition is provided in the following figure. SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 NXP Semiconductors 51 Power management PMC POR LVD sequencing VDD_xxx VHVD(rise) VHVD(fall) VLVD(rise) VLVD(fall) tVDRELEASE tVDASSERT HVD TRIGGER (INTERNAL) tVDASSERT tVDRELEASE LVD TRIGGER (INTERNAL) Figure 20. Voltage monitor threshold definition For VDD_LV levels, a maximum of 30 mV IR drop is incurred from the pin to all sinks on the die. For other LVD, the IR drop is estimated by multiplying the supply current by 0.5 ohm. LVD is released after tVDRELEASE temporization when upper threshold is crossed, LVD is asserted tVDASSERT after detection when lower threshold is crossed. HVD is released after tVDRELEASE temporization when lower threshold is crossed, HVD is asserted tVDASSERT after detection when upper threshold is crossed. Table 29. Voltage monitor electrical characteristics Configuration Symbol Parameter POR085_c1 LV internal supply power on reset Conditions Trim Mas Pow bits k . Up Opt. Rising voltage (power up) N/A Falling voltage (power down) No Value Min Typ Max Unit Enab 870 . 850 920 970 mV 900 950 Table continues on the next page... SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 52 NXP Semiconductors Power management PMC POR LVD sequencing Table 29. Voltage monitor electrical characteristics (continued) Configuration Conditions Trim Mas Pow bits k . Up Opt. POR098_c LV internal supply power on reset Rising voltage (power up) N/A internal2 Rising voltage (trimmed) Symbol Parameter LVD_core_ LV supply low voltage hot monitoring external3 LVD_core_ LV cold monitoring Falling voltage (power down) HV internal supply low voltage monitoring Max Unit 1010 1060 990 mV 1040 Enab 1146 1169 1193 . 1146 1169 1193 mV 6bit Yes Disa 1161 1185 1208 b. 1161 1185 1208 mV 6bit Yes Disa 1353 1395 1438 b. 1343 1385 1438 mV 6bit No Enab 3300 3400 3500 . 3270 3370 3470 mV Falling voltage Rising voltage (trimmed) Enab 960 . 940 Typ No Falling voltage Rising voltage Min 6bit Falling voltage (trimmed) supply low voltage Rising voltage HVD_core LV internal cold supply high voltage monitoring LVD_HV No Value Falling voltage (trimmed) HVD_HV HV internal supply high voltage Rising voltage monitoring Falling voltage 6bit Yes Disa 5530 5700 5870 b. 5500 5670 5840 mV LVD_IO Main IO and RC oscillator supply voltage monitoring 6bit No Enab 3300 3400 3500 . 3270 3370 3470 mV 6bit Yes Disa 2820 2910 3000 b. 2790 2880 2970 mV Rising voltage (trimmed) Falling voltage (trimmed) LVD_SAR SAR ADC supply low voltage monitoring Rising voltage tVDASSERT Voltage detector threshold crossing assertion -- -- -- -- 0.1 -- 2.0 s tVDRELEASE Voltage detector threshold crossing de-assertion -- -- -- -- 5 -- 20 s Falling voltage 1. POR085_c and POR096_c threshold are untrimmed value, before the completion of the power-up sequence. All other LVD/HVD thresholds are provided after trimming. 2. LV internal supply levels are measured on device internal supply grid after internal voltage drop. 3. LV external supply levels are measured on the die size of the package bond wire after package voltage drop. 16.1.6 Power up/down sequencing The following shows the constraints and relationships for the different power supplies. VDD_STDBY=0 VDD_LV=0 VDD_HV_PMC=0 VDD_HV_IO_MAIN=0 VDD_HV_IO_JTAG=0 VDD_HV_IO_FEC=0 VDD_HV_IO_MSC=0 VDD_HV_ADR_SD=0 VDD_HV_ADV_SD=0 VDD_STDBY VDD_LV VDD_HV_PMC VDD_HV_IO_MAIN VDD_HV_IO_JTAG VDD_HV_IO_FEC VDD_HV_IO_MSC VDD_HV_ADR_SD VDD_HV_ADV_SD VDD_HV_ADR_SAR VDD_HV_ADV_SAR VDD_HV_ADR_SAR=0 VDD_HV_ADV_SAR=0 Amps Amps 2mA Figure 21. Device supply relation during power-up/power-down sequence SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 NXP Semiconductors 53 Flash memory specifications Each column indicates that the corresponding supply is 0 and the other supplies are UP. For example, the "Amps" cell in the "VDD_HV_ADV_SD=0" column shows that when VDD_HV_ADR_SD supply is 0 and all other supplies are UP, this supply has a current in Amp flowing into VDD_HV_ADR_SD. 17 Flash memory specifications 17.1 Flash memory program and erase specifications NOTE All timing, voltage, and current numbers specified in this section are defined for a single embedded flash memory within an SoC, and represent average currents for given supplies and operations. Table 30 shows the estimated Program/Erase times. Table 30. Flash memory program and erase specifications Symbol Characteristic1 Typ2 Factory Programming3, 4 Field Update Initial Max Initial Max, Full Temp Typical End of Life5 20C TA 30C -40C TJ 150C -40C TJ 150C Unit Lifetime Max6 1,000 cycles 250,000 cycles tdwpgm Doubleword (64 bits) program time 43 100 150 55 500 s tppgm Page (256 bits) program time 73 200 300 108 500 s tqppgm Quad-page (1024 bits) program time 268 800 1,200 396 2,000 s t16kers 16 KB Block erase time 168 290 320 250 1,000 ms t16kpgm 16 KB Block program time 34 45 50 40 1,000 ms t32kers 32 KB Block erase time 217 360 390 310 1,200 ms t32kpgm 32 KB Block program time 69 100 110 90 1,200 ms t64kers 64 KB Block erase time 315 490 590 420 1,600 ms t64kpgm 64 KB Block program time 138 180 210 170 1,600 ms t256kers 256 KB Block erase time 884 1,520 2,030 1,080 4,000 -- ms t256kpgm 256 KB Block program time 552 720 880 650 4,000 -- ms 1. Program times are actual hardware programming times and do not include software overhead. Block program times assume quad-page programming. 2. Typical program and erase times represent the median performance and assume nominal supply values and operation at 25 C. Typical program and erase times may be used for throughput calculations. 3. Conditions: 150 cycles, nominal voltage. 4. Plant Programing times provide guidance for timeout limits used in the factory. SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 54 NXP Semiconductors Flash memory specifications 5. Typical End of Life program and erase times represent the median performance and assume nominal supply values. Typical End of Life program and erase values may be used for throughput calculations. 6. Conditions: -40C TJ 150C, full spec voltage. 17.2 Flash memory Array Integrity and Margin Read specifications Table 31. Flash memory Array Integrity and Margin Read specifications Symbol Characteristic Min Typical Max1 Units tai16kseq Array Integrity time for sequential sequence on 16 KB block. -- -- 512 x Tperiod x Nread -- tai32kseq Array Integrity time for sequential sequence on 32 KB block. -- -- 1024 x Tperiod x Nread -- tai64kseq Array Integrity time for sequential sequence on 64 KB block. -- -- 2048 x Tperiod x Nread -- tai256kseq Array Integrity time for sequential sequence on 256 KB block. -- -- 8192 x Tperiod x Nread -- tmr16kseq Margin Read time for sequential sequence on 16 KB block. 73.81 -- 110.7 s tmr32kseq Margin Read time for sequential sequence on 32 KB block. 128.43 -- 192.6 s tmr64kseq Margin Read time for sequential sequence on 64 KB block. 237.65 -- 356.5 s tmr256kseq Margin Read time for sequential sequence on 256 KB block. 893.01 -- 1,339.5 s 2 1. Array Integrity times need to be calculated and is dependent on system frequency and number of clocks per read. The equation presented require Tperiod (which is the unit accurate period, thus for 200 MHz, Tperiod would equal 5e-9) and Nread (which is the number of clocks required for read, including pipeline contribution. Thus for a read setup that requires 6 clocks to read with no pipeline, Nread would equal 6. For a read setup that requires 6 clocks to read, and has the address pipeline set to 2, Nread would equal 4 (or 6 - 2).) 2. The units for Array Integrity are determined by the period of the system clock. If unit accurate period is used in the equation, the results of the equation are also unit accurate. 17.3 Flash memory module life specifications Table 32. Flash memory module life specifications Symbol Array P/E cycles Data retention Characteristic Conditions Min Typical Units Number of program/erase cycles per block for 16 KB, 32 KB and 64 KB blocks.1 -- 250,000 -- P/E cycles Number of program/erase cycles per block for 256 KB blocks.2 -- 1,000 250,000 P/E cycles Minimum data retention. Blocks with 0 - 1,000 P/E cycles. 50 -- Years Table continues on the next page... SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 NXP Semiconductors 55 Flash memory specifications Table 32. Flash memory module life specifications (continued) Symbol Characteristic Conditions Min Typical Units Blocks with 100,000 P/E cycles. 20 -- Years Blocks with 250,000 P/E cycles. 10 -- Years 1. Program and erase supported across standard temperature specs. 2. Program and erase supported across standard temperature specs. 17.4 Data retention vs program/erase cycles Graphically, Data Retention versus Program/Erase Cycles can be represented by the following figure. The spec window represents qualified limits. The extrapolated dotted line demonstrates technology capability, however is beyond the qualification limits. SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 56 NXP Semiconductors Flash memory specifications 17.5 Flash memory AC timing specifications Table 33. Flash memory AC timing specifications Symbol Characteristic Min Typical Max Units Time from setting the MCR-PSUS bit until MCR-DONE bit is set to a 1. -- 9.4 11.5 s plus four system clock periods plus four system clock periods Time from setting the MCR-ESUS bit until MCR-DONE bit is set to a 1. -- 16 20.8 plus four system clock periods plus four system clock periods Time from clearing the MCR-ESUS or PSUS bit with EHV = 1 until DONE goes low. -- -- 100 ns tdone Time from 0 to 1 transition on the MCR-EHV bit initiating a program/erase until the MCR-DONE bit is cleared. -- -- 5 ns tdones Time from 1 to 0 transition on the MCR-EHV bit aborting a program/erase until the MCR-DONE bit is set to a 1. -- 16 20.8 s plus four system clock periods plus four system clock periods Time to recover once exiting low power mode. 16 -- 45 tpsus tesus tres tdrcv plus seven system clock periods. s s plus seven system clock periods taistart Time from 0 to 1 transition of UT0-AIE initiating a Margin Read or Array Integrity until the UT0-AID bit is cleared. This time also applies to the resuming from a suspend or breakpoint by clearing AISUS or clearing NAIBP -- -- 5 ns taistop Time from 1 to 0 transition of UT0-AIE initiating an Array Integrity abort until the UT0-AID bit is set. This time also applies to the UT0-AISUS to UT0-AID setting in the event of a Array Integrity suspend request. -- -- 80 ns Time from 1 to 0 transition of UT0-AIE initiating a Margin Read abort until the UT0-AID bit is set. This time also applies to the UT0-AISUS to UT0-AID setting in the event of a Margin Read suspend request. 10.36 tmrstop plus fifteen system clock periods plus four system clock periods -- 20.42 s plus four system clock periods SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 NXP Semiconductors 57 AC specifications 17.6 Flash read wait state and address pipeline control settings Table 34 describes the recommended RWSC and APC settings at various operating frequencies based on specified intrinsic flash access times of the C55FMC array at 150 C. Table 34. Flash Read Wait State and Address Pipeline Control Guidelines Operating Frequency fSYS RWSC APC Flash read latency on minicache miss (# of fSYS clock periods) Flash read latency on minicache hit (# of fSYS clock periods) 30 MHz 0 0 3 1 100 MHz 2 1 5 1 133 MHz 3 1 6 1 167 MHz 4 1 7 1 200 MHz 5 2 8 1 18 AC specifications 18.1 Debug and calibration interface timing 18.1.1 JTAG interface timing These specifications apply to JTAG boundary scan only. See Table 36 for functional specifications. Table 35. JTAG pin AC electrical characteristics # Symbol Characteristic 1 tJCYC 2 3 Value Unit Min Max TCK cycle time 100 -- ns tJDC TCK clock pulse width 40 60 ns tTCKRISE TCK rise and fall times -- 3 ns 4 tTMSS, tTDIS TMS, TDI data setup time 5 -- ns 5 tTMSH, tTDIH TMS, TDI data hold time 5 -- ns 6 tTDOV TCK low to TDO data valid -- 161 ns Table continues on the next page... SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 58 NXP Semiconductors AC specifications Table 35. JTAG pin AC electrical characteristics (continued) # Symbol 7 tTDOI 8 tTDOHZ 9 tJCMPPW 10 tJCMPS Value Characteristic Unit Min Max TCK low to TDO data invalid 0 -- ns TCK low to TDO high impedance -- 15 ns JCOMP assertion time 100 -- ns JCOMP setup time to TCK low 40 -- ns ns 11 tBSDV TCK falling edge to output valid -- 6002 12 tBSDVZ TCK falling edge to output valid out of high impedance -- 600 ns 13 tBSDHZ TCK falling edge to output high impedance -- 600 ns 14 tBSDST Boundary scan input valid to TCK rising edge 15 -- ns 15 tBSDHT TCK rising edge to boundary scan input invalid 15 -- ns 1. Timing includes TCK pad delay, clock tree delay, logic delay and TDO output pad delay. 2. Applies to all pins, limited by pad slew rate. Refer to IO delay and transition specification and add 20 ns for JTAG delay. TCK 2 2 3 1 3 Figure 22. JTAG test clock input timing SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 NXP Semiconductors 59 AC specifications TCK 4 5 TMS, TDI 6 8 7 TDO Figure 23. JTAG test access port timing TCK 10 JCOMP 9 Figure 24. JTAG JCOMP timing SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 60 NXP Semiconductors AC specifications TCK 11 13 Output Signals 12 Output Signals 14 15 Input Signals Figure 25. JTAG boundary scan timing 18.1.2 Nexus interface timing Nexus timing specified for the whole VDD_LV and VDD_HV_IO dynamic, TA = TL to TH, and maximum loading per pad type as specified in the I/O section of the data sheet. Table 36. Nexus debug port timing # Symbol Characteristic 1 tEVTIPW 2 tEVTOPW Value Unit Min Max EVTI Pulse Width 4 -- tCYC, 1 EVTO Pulse Width 40 -- ns -- tCYC1 -- ns 3 tTCYC TCK cycle time 42, 3 4 tTCYC Absolute minimum TCK cycle time4 (TDO sampled on posedge of TCK) 405 Table continues on the next page... SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 NXP Semiconductors 61 AC specifications Table 36. Nexus debug port timing (continued) # Symbol Value Characteristic Absolute minimum TCK cycle time6 (TDO sampled on negedge of TCK) Unit Min Max 205 -- 5 tNTDIS TDI data setup time 5 -- ns 6 tNTDIH TDI data hold time 5 -- ns 7 tNTMSS TMS data setup time 5 -- ns 8 tNTMSH TMS data hold time 5 -- ns -- 16 ns 2.25 -- ns TCK7 9 -- TDO propagation delay from falling edge of 10 -- TDO hold time with respect to TCK falling edge (minimum TDO propagation delay) 1. tCYC is system clock period. 2. Achieving the absolute minimum TCK cycle time may require a maximum clock speed (system frequency / 8) that is less than the maximum functional capability of the design (system frequency / 4) depending on the actual peripheral frequency being used. To ensure proper operation TCK frequency should be set to the peripheral frequency divided by a number greater than or equal to that specified here. 3. This is a functionally allowable feature. However, it may be limited by the maximum frequency specified by the Absolute minimum TCK period specification. 4. This value is TDO propagation time 36ns + 4ns setup time to sampling edge. 5. This may require a maximum clock speed (system frequency / 8) that is less than the maximum functional capability of the design (system frequency / 4) depending on the actual system frequency being used. 6. This value is TDO propagation time 16ns + 4ns setup time to sampling edge. 7. Timing includes TCK pad delay, clock tree delay, logic delay and TDO output pad delay. Figure 26. Nexus output timing TCK EVTI EVTO 3 Figure 27. Nexus event trigger and test clock timings SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 62 NXP Semiconductors AC specifications TCK 5 7 6 8 TMS, TDI 9 10 TDO Figure 28. Nexus TDI, TMS, TDO timing 18.1.3 Aurora LVDS interface timing Table 37. Aurora LVDS interface timing specifications Symbol Value Parameter Min Typ Max Unit Data Rate -- Data rate -- 1250 Mbps STARTUP tSTRT_BIAS tSTRT_TX tSTRT_RX Bias startup time1 -- -- 5 s Transmitter startup time2 -- -- 5 s -- -- 4 s Receiver startup time3 1. Startup time is defined as the time taken by LVDS current reference block for settling bias current after its pwr_down (power down) has been deasserted. LVDS functionality is guaranteed only after the startup time. 2. Startup time is defined as the time taken by LVDS transmitter for settling after its pwr_down (power down) has been deasserted. Here it is assumed that current reference is already stable (see Bias start-up time). LVDS functionality is guaranteed only after the startup time. SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 NXP Semiconductors 63 AC specifications 3. Startup time is defined as the time taken by LVDS receiver for settling after its pwr_down (power down) has been deasserted. Here it is assumed that current reference is already stable (see Bias start-up time). LVDS functionality is guaranteed only after the startup time. 18.1.3.1 Aurora debug port timing Table 38. Aurora debug port timing # Symbol Parameter 1 tREFCLK Reference clock frequency 1a tMCYC 2 tRCDC 3 JRC 4 tSTABILITY Value Unit Min Max 625 1200 MHz Reference clock rise/fall time -- 400 ps Reference clock duty cycle 45 55 % Reference clock jitter -- 40 ps Reference clock stability 50 -- PPM Bit error rate -- 10-12 -- 5 BER 6 JD Transmit lane deterministic jitter -- 0.17 OUI 7 JT Transmit lane total jitter -- 0.35 OUI 8 SO Differential output skew -- 20 ps 9 SMO Lane to lane output skew 10 OUI Aurora lane unit interval1 -- 1000 ps 625 Mbps 1600 1600 ps 1.25Gbps 800 800 ps 1. 100 PPM SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 64 NXP Semiconductors AC specifications 1 2 2 CLOCKREF Zero Crossover CLOCKREF 1a 1a 1a 8 8 1a 8 Tx Data Ideal Zero Crossover Tx Data Tx Data [n] Zero Crossover Tx Data [n+1] Zero Crossover Tx Data [m] Zero Crossover 9 9 Figure 29. Aurora timings 18.2 DSPI timing with CMOS and LVDS DSPI in TSB mode with LVDS pads can be used to implement Micro Second Channel bus protocol. DSPI channel frequency support is shown in Table 39. Timing specifications are shown in Table 40, Table 41, Table 42, Table 43, Table 44. Table 39. DSPI channel frequency support Max usable frequency (MHz)1,2 DSPI use mode CMOS (Master mode) LVDS (Master mode) Full duplex - Classic timing (Table 40) 17 Full duplex - Modified timing (Table 41) 30 Output only mode (SCK/SOUT/PCS) (Table 40 and Table 41) 30 Output only mode TSB mode (SCK/SOUT/PCS) (Table 44) 30 Full duplex - Modified timing (Table 42) 40 SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 NXP Semiconductors 65 AC specifications 1. Maximum usable frequency can be achieved if used with fastest configuration of the highest drive pads. 2. Maximum usable frequency does not take into account external device propagation delay. 18.2.1 DSPI master mode full duplex timing with CMOS and LVDS pads The values presented in these sections are target values. A complete performance characterization of the pads (in all configuration combinations) is required before the final specifications can be released. 18.2.1.1 DSPI CMOS master mode - classic timing All output timing is worst case and includes the mismatching of rise and fall times of the output pads. NOTE In Table 40, all output timing is worst case and includes the mismatching of rise and fall times of the output pads. Table 40. DSPI CMOS master classic timing (full duplex and output only) - MTFE = 0, CPHA = 0 or 1 # Symbol Characteristic Pad drive2 1 2 tSCK tCSC SCK cycle time PCS to SCK delay Load (CL) After SCK delay Min Max Very strong 25 pF 33.0 -- Strong 50 pF 80.0 -- Medium 50 pF 200.0 -- 25 pF (N3 x tSYS, 4) - 16 -- Strong 50 pF (N3 - 16 -- Medium 50 pF (N3 x tSYS, 4) - 16 -- (N3 x tSYS, 4) - 29 -- (M5 x tSYS4) - 35 -- (M5 x tSYS, 4) - 35 -- (M5 x tSYS, 4) - 35 -- (M5 x tSYS, 4) - 35 -- ns SCK and PCS drive strength PCS medium and PCS = 50 pF SCK strong SCK = 50 pF tASC Unit SCK drive strength Very strong 3 Value1 Condition x tSYS , 4) ns SCK and PCS drive strength Very strong PCS = 0 pF ns SCK = 50 pF Strong PCS = 0 pF SCK = 50 pF Medium PCS = 0 pF SCK = 50 pF PCS medium and PCS = 0 pF SCK strong Table continues on the next page... SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 66 NXP Semiconductors AC specifications Table 40. DSPI CMOS master classic timing (full duplex and output only) - MTFE = 0, CPHA = 0 or 1 (continued) # Symbol Characteristic Value1 Condition Pad drive2 Load (CL) Unit Min Max SCK = 50 pF 4 tSDC SCK duty cycle6 SCK drive strength Very strong Strong Medium 0 to 50 pF 1/ 0 to 50 pF 1/ 0 to 50 pF 1/ 2tSCK 2tSCK 2tSCK -2 1/ +2 -2 1/ +2 -5 1/ +5 2tSCK 2tSCK 2tSCK ns PCS strobe timing 5 tPCSC PCSx to PCSS time, 6 tPASC PCSS to PCSx time7 PCS and PCSS drive strength 7 PCS and PCSS drive strength Strong 13.0 -- ns 25 pF 13.0 -- ns Very strong 25 pF 25.0 -- ns Strong 50 pF 31.0 -- Medium 50 pF 52.0 -- Very strong 0 pF -1.0 -- Strong 0 pF -1.0 -- Medium 0 pF -1.0 -- SOUT data valid time SOUT and SCK drive strength from SCK9 Very strong 25 pF -- 7.0 Strong 50 pF -- 8.0 Medium 50 pF -- 16.0 SOUT data hold time SOUT and SCK drive strength after SCK9 Very strong 25 pF -7.7 -- Strong 50 pF -11.0 -- Medium 50 pF -15.0 -- Strong 25 pF SIN setup time 7 tSUI SIN setup time to SCK8 SCK drive strength SIN hold time 8 tHI SIN hold time from SCK8 SCK drive strength ns SOUT data valid time (after SCK edge) 9 tSUO ns SOUT data hold time (after SCK edge) 10 tHO ns 1. All timing values for output signals in this table are measured to 50% of the output voltage. 2. Timing is guaranteed to same drive capabilities for all signals, mixing of pad drives may reduce operating speeds and may cause incorrect operation. 3. N is the number of clock cycles added to time between PCS assertion and SCK assertion and is software programmable using DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK]. The minimum value is 2 cycles unless TSB mode or Continuous SCK clock mode is selected, in which case, N is automatically set to 0 clock cycles (PCS and SCK are driven by the same edge of DSPI_CLKn). 4. tSYS is the period of DSPI_CLKn clock, the input clock to the DSPI module. Maximum frequency is 100 MHz (min tSYS = 10 ns). SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 NXP Semiconductors 67 AC specifications 5. M is the number of clock cycles added to time between SCK negation and PCS negation and is software programmable using DSPI_CTARx[PASC] and DSPI_CTARx[ASC]. The minimum value is 2 cycles unless TSB mode or Continuous SCK clock mode is selected, in which case, M is automatically set to 0 clock cycles (PCS and SCK are driven by the same edge of DSPI_CLKn). 6. tSDC is only valid for even divide ratios. For odd divide ratios the fundamental duty cycle is not 50:50. For these odd divide ratios cases, the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time. 7. PCSx and PCSS using same pad configuration. 8. Input timing assumes an input slew rate of 1 ns (10% - 90%) and uses TTL voltage thresholds. 9. SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the same value. tCSC tASC PCSx tSCK tSDC SCK Output (CPOL = 0) SCK Output (CPOL = 1) SIN tSDC tSUI First Data tHI Data tSUO SOUT First Data Data LastData tHO Last Data Figure 30. DSPI CMOS master mode - classic timing, CPHA = 0 SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 68 NXP Semiconductors AC specifications PCSx SCK Output (CPOL = 0) SCK Output (CPOL = 1) tSUI tHI Data Fist Data SIN LastData tSUO SOUT Data Fist Data tHO Last Data Figure 31. DSPI CMOS master mode - classic timing, CPHA = 1 tPCSC tPASC PCSS PCSx Figure 32. DSPI PCS strobe (PCSS) timing (master mode) 18.2.1.2 DSPI CMOS master mode - modified timing All output timing is worst case and includes the mismatching of rise and fall times of the output pads. NOTE In Table 41, all output timing is worst case and includes the mismatching of rise and fall times of the output pads. Table 41. DSPI CMOS master modified timing (full duplex and output only) - MTFE = 1, CPHA = 0 or 1 # Symbol Characteristic Pad 1 tSCK SCK cycle time Value1 Condition drive2 Load (CL) Unit Min Max SCK drive strength Very strong 25 pF 33.0 -- Strong 50 pF 80.0 -- ns Table continues on the next page... SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 NXP Semiconductors 69 AC specifications Table 41. DSPI CMOS master modified timing (full duplex and output only) - MTFE = 1, CPHA = 0 or 1 (continued) # Symbol Characteristic Pad drive2 Medium 2 tCSC PCS to SCK delay Load (CL) 50 pF tASC After SCK delay Unit Min Max 200.0 -- SCK and PCS drive strength Very strong 25 pF (N3 x tSYS, 4) - 16 -- Strong 50 pF (N3 x tSYS, 4) - 16 -- Medium 50 pF (N3 x tSYS, 4) - 16 -- (N3 - 29 -- (M5 x tSYS4) - 35 -- (M5 x tSYS, 4) - 35 -- (M5 x tSYS, 4) - 35 -- (M5 x tSYS, 4) - 35 -- PCS medium and PCS = 50 pF SCK strong SCK = 50 pF 3 Value1 Condition , 4) x tSYS ns SCK and PCS drive strength Very strong PCS = 0 pF ns SCK = 50 pF Strong PCS = 0 pF SCK = 50 pF Medium PCS = 0 pF SCK = 50 pF PCS medium and PCS = 0 pF SCK strong SCK = 50 pF 4 tSDC SCK duty cycle6 SCK drive strength Very strong Strong Medium 0 to 50 pF 1/ 0 to 50 pF 1/ 0 to 50 pF 1/ 2tSCK 2tSCK 2tSCK -2 1/ +2 -2 1/ +2 -5 1/ +5 2tSCK 2tSCK 2tSCK ns PCS strobe timing 5 6 tPCSC PCSx to PCSS time, tPASC time7 7 PCS and PCSS drive strength Strong PCSS to PCSx 25 pF 13.0 -- ns 25 pF 13.0 -- ns Very strong 25 pF 25 - (P9 x tSYS4) -- ns Strong 50 pF 31 - (P9 x tSYS, 4) -- Medium 50 pF 52 - (P9 x tSYS, 4) -- Very strong 25 pF 25.0 -- Strong 50 pF 31.0 -- Medium 50 pF 52.0 -- 0 pF -1 + (P8 x tSYS, 3) -- PCS and PCSS drive strength Strong SIN setup time 7 tSUI SIN setup time to SCK CPHA = 08 SIN setup time to SCK CPHA = 18 SCK drive strength SCK drive strength ns SIN hold time 8 tHI SIN hold time from SCK SCK drive strength Very strong ns Table continues on the next page... SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 70 NXP Semiconductors AC specifications Table 41. DSPI CMOS master modified timing (full duplex and output only) - MTFE = 1, CPHA = 0 or 1 (continued) # Symbol Characteristic Pad CPHA = 09 drive2 Strong Medium SIN hold time from SCK CPHA = 19 Value1 Condition Load (CL) 0 pF 0 pF Min -1 + (P8 -1 + (P8 Unit Max , 3) -- , 3) -- x tSYS x tSYS SCK drive strength Very strong 0 pF -1.0 -- Strong 0 pF -1.0 -- ns Medium 0 pF -1.0 -- SOUT data valid time SOUT and SCK drive strength from SCK Very strong 25 pF CPHA = 09 Strong 50 pF -- 7.0 + tSYS4 -- 8.0 + tSYS 4 Medium -- 16.0 + tSYS4 SOUT data valid time SOUT and SCK drive strength from SCK Very strong 25 pF CPHA = 19 Strong 50 pF -- 7.0 -- 8.0 Medium -- 16.0 SOUT data valid time (after SCK edge) 9 tSUO 50 pF 50 pF ns ns SOUT data hold time (after SCK edge) 10 tHO SOUT data hold time SOUT and SCK drive strength after SCK Very strong 25 pF CPHA = 010 Strong 50 pF Medium 50 pF -7.7 + tSYS4 -- -11.0 + tSYS4 -- -15.0 + tSYS4 -- SOUT data hold time SOUT and SCK drive strength after SCK Very strong 25 pF CPHA = 110 Strong 50 pF -7.7 -- -11.0 -- Medium -15.0 -- 50 pF ns ns 1. All timing values for output signals in this table are measured to 50% of the output voltage. 2. Timing is guaranteed to same drive capabilities for all signals, mixing of pad drives may reduce operating speeds and may cause incorrect operation. 3. N is the number of clock cycles added to time between PCS assertion and SCK assertion and is software programmable using DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK]. The minimum value is 2 cycles unless TSB mode or Continuous SCK clock mode is selected, in which case, N is automatically set to 0 clock cycles (PCS and SCK are driven by the same edge of DSPI_CLKn). 4. tSYS is the period of DSPI_CLKn clock, the input clock to the DSPI module. Maximum frequency is 100 MHz (min tSYS = 10 ns). 5. M is the number of clock cycles added to time between SCK negation and PCS negation and is software programmable using DSPI_CTARx[PASC] and DSPI_CTARx[ASC]. The minimum value is 2 cycles unless TSB mode or Continuous SCK clock mode is selected, in which case, M is automatically set to 0 clock cycles (PCS and SCK are driven by the same edge of DSPI_CLKn). 6. tSDC is only valid for even divide ratios. For odd divide ratios the fundamental duty cycle is not 50:50. For these odd divide ratios cases, the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time. 7. PCSx and PCSS using same pad configuration. 8. Input timing assumes an input slew rate of 1 ns (10% - 90%) and uses TTL voltage thresholds. SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 NXP Semiconductors 71 AC specifications 9. P is the number of clock cycles added to delay the DSPI input sample point and is software programmable using DSPI_MCR[SMPL_PT]. The value must be 0, 1 or 2. If the baud rate divide ratio is /2 or /3, this value is automatically set to 1. 10. SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the same value. tCSC tASC PCSx SCK Output (CPOL = 0) SCK Output (CPOL = 1) SIN tSCK t SDC tSDC tSUI tHI First Data LastData Data tSUO SOUT tHO Data First Data Last Data Figure 33. DSPI CMOS master mode - modified timing, CPHA = 0 PCSx SCK Output (CPOL=0) SCK Output (CPOL=1) tSUI SIN tHI tHI Data First Data tSUO SOUT First Data Data LastData tHO Last Data Figure 34. DSPI CMOS master mode - modified timing, CPHA = 1 SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 72 NXP Semiconductors AC specifications tPCSC tPASC PCSS PCSx Figure 35. DSPI PCS strobe (PCSS) timing (master mode)1 18.2.1.3 DSPI LVDS master mode - modified timing Table 42. DSPI LVDS master timing - full duplex - modified transfer format (MTFE = 1), CPHA = 0 or 1 # Symbol Characteristic Pad drive 1 tSCK SCK cycle time Value1 Condition LVDS Load Unit Min Max 30.0 -- ns 25 pF (N2 x tSYS, 3) - 10 -- ns 50 pF (N2 50 pF (N2 15 pF to 25 pF differential 2 tCSC PCS to SCK delay (LVDS SCK) PCS drive strength Very strong Strong Medium 3 tASC After SCK delay Very strong (LVDS SCK) PCS = 0 pF , 3) - 10 -- ns , 3) - 32 -- ns -8 -- ns (M4 x tSYS, 3) - 8 -- ns (M4 x tSYS, 3) - 8 -- ns x tSYS x tSYS (M4 3) x tSYS SCK = 25 pF Strong PCS = 0 pF SCK = 25 pF Medium PCS = 0 pF SCK = 25 pF 4 tSDC SCK duty cycle5 LVDS 1/ 15 pF 2tSCK -2 1/ 2tSCK +2 ns to 25 pF differential 7 tSUI SIN setup time SIN setup time to SCK SCK drive strength LVDS 15 pF CPHA = 06 23 - (P7 x tSYS3) -- ns 23 -- ns to 25 pF differential SIN setup time to SCK CPHA = 16 SCK drive strength LVDS 15 pF to 25 pF differential 8 tHI SIN Hold Time Table continues on the next page... SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 NXP Semiconductors 73 AC specifications Table 42. DSPI LVDS master timing - full duplex - modified transfer format (MTFE = 1), CPHA = 0 or 1 (continued) # Symbol Characteristic Pad drive SIN hold time from SCK CPHA = Value1 Condition Load Min Max 0 pF differential -1 + (P7 x tSYS, 3) -- ns 0 pF differential -1 -- ns -- 7.0 + tSYS3 ns -- 7.0 ns -7.5 + tSYS3 -- ns -7.5 -- ns SCK drive strength LVDS 06 SIN hold time from SCK Unit SCK drive strength LVDS CPHA = 16 9 tSUO SOUT data valid time (after SCK edge) SOUT data valid time SOUT and SCK drive strength from SCK LVDS 15 pF CPHA = 08 to 25 pF differential SOUT data valid time SOUT and SCK drive strength from SCK LVDS 15 pF CPHA = 18 to 25 pF differential 10 tHO SOUT data hold time (after SCK edge) SOUT data hold time SOUT and SCK drive strength after SCK LVDS 15 pF CPHA = 08 to 25 pF differential SOUT data hold time SOUT and SCK drive strength after SCK LVDS 15 pF CPHA = 18 to 25 pF differential 1. All timing values for output signals in this table are measured to 50% of the output voltage. 2. N is the number of clock cycles added to time between PCS assertion and SCK assertion and is software programmable using DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK]. The minimum value is 2 cycles unless TSB mode or Continuous SCK clock mode is selected, in which case, N is automatically set to 0 clock cycles (PCS and SCK are driven by the same edge of DSPI_CLKn). 3. tSYS is the period of DSPI_CLKn clock, the input clock to the DSPI module. Maximum frequency is 100 MHz (min tSYS = 10 ns). 4. M is the number of clock cycles added to time between SCK negation and PCS negation and is software programmable using DSPI_CTARx[PASC] and DSPI_CTARx[ASC]. The minimum value is 2 cycles unless TSB mode or Continuous SCK clock mode is selected, in which case, M is automatically set to 0 clock cycles (PCS and SCK are driven by the same edge of DSPI_CLKn). 5. tSDC is only valid for even divide ratios. For odd divide ratios the fundamental duty cycle is not 50:50. For these odd divide ratios cases, the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time. 6. Input timing assumes an input slew rate of 1 ns (10% - 90%) and LVDS differential voltage = 100 mV. 7. P is the number of clock cycles added to delay the DSPI input sample point and is software programmable using DSPI_MCR[SMPL_PT]. The value must be 0, 1 or 2. If the baud rate divide ratio is /2 or /3, this value is automatically set to 1. 8. SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the same value. SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 74 NXP Semiconductors AC specifications tCSC tASC PCSx tSCK tSDC SCK Output (CPOL = 0) SCK Output (CPOL = 1) SIN tSDC tSUI tHI First Data Data LastData tSUO SOUT tHO Data First Data Last Data Figure 36. DSPI LVDS master mode - modified timing, CPHA = 0 PCSx SCK Output (CPOL = 0) SCK Output (CPOL = 1) tSUI SIN tHI tHI Data First Data tSUO SOUT First Data Data Last Data tHO Last Data Figure 37. DSPI LVDS master mode - modified timing, CPHA = 1 18.2.1.4 DSPI master mode - output only For Table 43 : SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 NXP Semiconductors 75 AC specifications * All DSPI timing specifications apply to pins when using LVDS pads for SCK and SOUT and CMOS pad for PCS with pad driver strength as defined. Timing may degrade for weaker output drivers. * TSB = 1 or ITSB = 1 automatically selects MTFE = 1 and CPHA = 1. Table 43. DSPI LVDS master timing - output only - timed serial bus mode TSB = 1 or ITSB = 1, CPOL = 0 or 1, continuous SCK clock # Symbol Characteristic Condition Pad drive 1 tSCK SCK cycle time LVDS Value Load 15 pF Unit Min Max 25.0 -- ns to 50 pF differential 2 tCSV SCK1 PCS valid after Very strong 25 pF -- 6.0 ns Strong 50 pF -- 6.0 ns PCS hold after SCK1 Very strong 0 pF -4.0 -- ns Strong (SCK with 50 pF differential load cap.) 0 pF -4.0 -- ns SCK duty cycle 15 pF (SCK with 50 pF differential load cap.) 3 4 tCSH tSDC LVDS (SCK with 50 pF differential load cap.) 1/ 2tSCK -2 1/ 2tSCK +2 ns to 50 pF differential SOUT data valid time (after SCK edge) 5 tSUO SOUT data valid time SOUT and SCK drive strength from SCK2 LVDS 15 pF -- 3.5 ns -3.5 -- ns to 50 pF differential SOUT data hold time (after SCK edge) 6 tHO SOUT data hold time SOUT and SCK drive strength after SCK2 LVDS 15 pF to 50 pF differential 1. With TSB mode or Continuous SCK clock mode selected, PCS and SCK are driven by the same edge of DSPI_CLKn. This timing value is due to pad delays and signal propagation delays. 2. SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the same value. For Table 44 : * TSB = 1 or ITSB = 1 automatically selects MTFE = 1 and CPHA = 1. * All output timing is worst case and includes the mismatching of rise and fall times of the output pads. SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 76 NXP Semiconductors AC specifications Table 44. DSPI CMOS master timing - output only - timed serial bus mode TSB = 1 or ITSB = 1, CPOL = 0 or 1, continuous SCK clock # Symbol Characteristic Pad 1 2 tSCK tCSV SCK cycle time Value1 Condition drive2 Load (CL) tCSH Min Max SCK drive strength Very strong 25 pF 33.0 -- ns Strong 50 pF 80.0 -- ns Medium 50 pF 200.0 -- ns PCS valid after SCK3 SCK and PCS drive strength Very strong 25 pF 7 -- ns Strong 50 pF 8 -- ns Medium 50 pF 16 -- ns 29 -- ns -14 -- ns -14 -- ns -33 -- ns -35 -- ns PCS medium and PCS = 50 pF SCK strong SCK = 50 pF 3 Unit PCS hold after SCK3 SCK and PCS drive strength Very strong PCS = 0 pF SCK = 50 pF Strong PCS = 0 pF SCK = 50 pF Medium PCS = 0 pF SCK = 50 pF PCS medium and PCS = 0 pF SCK strong SCK = 50 pF 4 tSDC SCK duty cycle4 SCK drive strength Very strong 0 to 50 pF 1/ Strong 0 to 50 pF 1/ Medium 0 to 50 pF 1/ -2 1/ 2tSCK - 2 1/ 2tSCK 2tSCK -5 2tSCK +2 ns 2tSCK + 2 ns 1/ 2tSCK +5 ns SOUT data valid time (after SCK edge) 9 tSUO SOUT data valid time SOUT and SCK drive strength from SCK Very strong 25 pF CPHA = 1, 5 Strong 50 pF -- 7.0 ns -- 8.0 ns Medium -- 16.0 ns SOUT data hold time SOUT and SCK drive strength after SCK CPHA = 15 Very strong 25 pF -7.7 -- ns Strong 50 pF -11.0 -- ns Medium 50 pF -15.0 -- ns 50 pF SOUT data hold time (after SCK edge) 10 tHO 1. All timing values for output signals in this table are measured to 50% of the output voltage. 2. Timing is guaranteed to same drive capabilities for all signals, mixing of pad drives may reduce operating speeds and may cause incorrect operation. 3. With TSB mode or Continuous SCK clock mode selected, PCS and SCK are driven by the same edge of DSPI_CLKn. This timing value is due to pad delays and signal propagation delays. SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 NXP Semiconductors 77 AC specifications 4. tSDC is only valid for even divide ratios. For odd divide ratios the fundamental duty cycle is not 50:50. For these odd divide ratios cases, the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time. 5. SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the same value. PCSx tCSV tSCK tSDC tCSH SCK Output (CPOL = 0) tSUO First Data SOUT Data tHO Last Data Figure 38. DSPI LVDS and CMOS master timing - output only - modified transfer format MTFE = 1, CHPA = 1 18.2.2 DSPI CMOS slave mode NOTE DSPI slave operation is only supported for a single master and single slave on the device. Timing is valid for that case only. Table 45. DSPI CMOS slave timing - Modified Transfer Format (MTFE = 0/1) # Symbol Characteristic1 Condition Pad drive Value Load Unit Min Max 1 tSCK SCK Cycle Time -- -- 62 -- ns 2 tCSC SS to SCK Delay -- -- 16 -- ns 3 tASC SCK to SS Delay -- -- 16 -- ns 4 tSDC SCK Duty Cycle -- -- 30 -- ns Very strong 25 pF -- 50 ns Strong 50 pF -- 50 ns Medium 50 pF -- 60 ns Slave SOUT Disable Very strong Time2 Strong (SS inactive to SOUT Medium High-Z or invalid) 25 pF -- 5 ns 50 pF -- 5 ns 50 pF -- 10 ns Data Setup Time for Inputs -- 10 -- ns 5 tA Slave Access Time2 (SS active to SOUT driven) 6 9 tDIS tSUI -- Table continues on the next page... SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 78 NXP Semiconductors AC specifications Table 45. DSPI CMOS slave timing - Modified Transfer Format (MTFE = 0/1) (continued) # Symbol Characteristic1 Condition Pad drive Value Load Unit Min Max 10 tHI Data Hold Time for Inputs -- -- 10 -- ns 11 tSUO SOUT Valid Time2 Very strong 25 pF -- 30 ns (after SCK edge) Strong 50 pF -- 30 ns Medium 50 pF -- 50 ns Very strong 25 pF 2.5 -- ns Strong 50 pF 2.5 -- ns Medium 50 pF 2.5 -- ns 12 tHO SOUT Hold Time2 (after SCK edge) 1. Input timing assumes an input slew rate of 1 ns (10% - 90%) and uses TTL / Automotive voltage thresholds. 2. All timing values for output signals in this table, are measured to 50% of the output voltage. All output timing is worst case and includes the mismatching of rise and fall times of the output pads. tASC tCSC SS tSCK S C K In p u t (C P O L = 0 ) tSDC tSDC S C K In p u t (C P O L = 1 ) tSUO tA SOUT F irs t D a ta D a ta tSUI S IN F irst D a ta tHO tDIS L a s t D a ta tHI D a ta L a s t D a ta Figure 39. DSPI Slave Mode - Modified transfer format timing (MFTE = 0/1) -- CPHA = 0 SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 NXP Semiconductors 79 AC specifications SS S C K In p u t (C P O L = 0 ) S C K In p u t (C P O L = 1 ) tSUO tA SOUT F irs t D a ta tSUI S IN tDIS tHO D a ta L a s t D a ta D a ta L a s t D a ta tHI F irs t D a ta Figure 40. DSPI Slave Mode - Modified transfer format timing (MFTE = 0/1) -- CPHA = 1 18.3 FEC timing The FEC supports the 10/100 Mbps MII, 10/100 Mbps MII-lite, and the 10 Mbps-only 7wire interface. 18.3.1 MII-lite receive signal timing (RXD[3:0], RX_DV, RX_ER, and RX_CLK) The receiver functions correctly up to a RX_CLK maximum frequency of 25 MHz +1%. There is no minimum frequency requirement. The system clock frequency must be at least equal to or greater than the RX_CLK frequency. All timing specifications are referenced from RX_CLK = 1.4 V to the valid input levels. Table 46. MII-lite receive signal timing Spec Characteristic M1 Value Unit Min Max RXD[3:0], RX_DV, RX_ER to RX_CLK setup 5 -- ns M2 RX_CLK to RXD[3:0], RX_DV, RX_ER hold 5 -- ns M3 RX_CLK pulse width high 35% 65% RX_CLK period M4 RX_CLK pulse width low 35% 65% RX_CLK period SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 80 NXP Semiconductors AC specifications M3 RX_CLK (input) M4 RXD[3:0] (inputs) RX_DV RX_ER M1 M2 Figure 41. MII-lite receive signal timing diagram 18.3.2 MII-lite transmit signal timing (TXD[3:0], TX_EN, TX_ER, TX_CLK) The transmitter functions correctly up to a TX_CLK maximum frequency of 25 MHz +1%. There is no minimum frequency requirement. The system clock frequency must be at least equal to or greater than the TX_CLK frequency. The transmit outputs (TXD[3:0], TX_EN, TX_ER) can be programmed to transition from either the rising or falling edge of TX_CLK, and the timing is the same in either case. This options allows the use of non-compliant MII PHYs. All timing specifications are referenced from TX_CLK = 1.4 V to the valid output levels. Table 47. MII-lite transmit signal timing Spec Characteristic M5 Value1 Unit Min Max TX_CLK to TXD[3:0], TX_EN, TX_ER invalid 5 -- ns M6 TX_CLK to TXD[3:0], TX_EN, TX_ER valid -- 25 ns M7 TX_CLK pulse width high 35% 65% TX_CLK period M8 TX_CLK pulse width low 35% 65% TX_CLK period 1. Output parameters are valid for CL = 25 pF, where CL is the external load to the device. The internal package capacitance is accounted for, and does not need to be subtracted from the 25 pF value. SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 NXP Semiconductors 81 AC specifications M7 TX_CLK (input) M5 M8 TXD[3:0] (outputs) TX_EN TX_ER M6 Figure 42. MII-lite transmit signal timing diagram 18.3.3 MII-lite async inputs signal timing (CRS and COL) Table 48. MII-lite async inputs signal timing Spec Characteristic M9 CRS, COL minimum pulse width Value Unit Min Max 1.5 -- TX_CLK period CRS, COL M9 Figure 43. MII-lite async inputs timing diagram 18.3.4 MII-lite serial management channel timing (MDIO and MDC) The FEC functions correctly with a maximum MDC frequency of 2.5 MHz. NOTE All timing specifications are referenced from MDC = 1.4 V (TTL levels) to the valid input and output levels, 0.8 V and 2.0 V (TTL levels). For 5 V operation, timing is referenced from MDC = 50% to 2.2 V/3.5 V input and output levels. SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 82 NXP Semiconductors AC specifications Table 49. MII-lite serial management channel timing Spec Characteristic M10 Value Unit Min Max MDC falling edge to MDIO output invalid (minimum propagation delay) 0 -- ns M11 MDC falling edge to MDIO output valid (max prop delay) -- 25 ns M12 MDIO (input) to MDC rising edge setup 10 -- ns M13 MDIO (input) to MDC rising edge hold 0 -- ns M14 MDC pulse width high 40% 60% MDC period M15 MDC pulse width low 40% 60% MDC period M14 M15 MDC (output) M10 MDIO (output) M11 MDIO (input) M12 M13 Figure 44. MII-lite serial management channel timing diagram 18.3.5 RMII serial management channel timing (MDIO and MDC) The FEC functions correctly with a maximum MDC frequency of 2.5 MHz. Table 50. RMII serial management channel timing Spec Characteristic M10 MDC falling edge to MDIO output invalid (minimum propagation delay) Value Unit Min Max 0 -- ns Table continues on the next page... SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 NXP Semiconductors 83 AC specifications Table 50. RMII serial management channel timing (continued) Spec Characteristic M11 Value Unit Min Max MDC falling edge to MDIO output valid (max prop delay) -- 25 ns M12 MDIO (input) to MDC rising edge setup 10 -- ns M13 MDIO (input) to MDC rising edge hold 0 -- ns M14 MDC pulse width high 40% 60% MDC period M15 MDC pulse width low 40% 60% MDC period M14 M15 MDC (output) M10 MDIO (output) M11 MDIO (input) M12 M13 Figure 45. RMII-lite serial management channel timing diagram 18.3.6 RMII receive signal timing (RXD[1:0], CRS_DV) The receiver functions correctly up to a REF_CLK maximum frequency of 50 MHz +1%. There is no minimum frequency requirement. The system clock frequency must be at least equal to or greater than the RX_CLK frequency, which is half that of the REF_CLK frequency. All timing specifications are referenced from REF_CLK = 1.4 V to the valid input levels. SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 84 NXP Semiconductors AC specifications Table 51. RMII receive signal timing Spec Characteristic R1 Value Unit Min Max RXD[1:0], CRS_DV to REF_CLK setup 4 -- ns R2 REF_CLK to RXD[1:0], CRS_DV hold 2 -- ns R3 REF_CLK pulse width high 35% 65% REF_CLK period R4 REF_CLK pulse width low 35% 65% REF_CLK period R3 REF_CLK (input) R4 RXD[1:0] (inputs) CRS_DV R1 R2 Figure 46. RMII receive signal timing diagram 18.3.7 RMII transmit signal timing (TXD[1:0], TX_EN) The transmitter functions correctly up to a REF_CLK maximum frequency of 50 MHz + 1%. There is no minimum frequency requirement. The system clock frequency must be at least equal to or greater than the TX_CLK frequency, which is half that of the REF_CLK frequency. The transmit outputs (TXD[1:0], TX_EN) can be programmed to transition from either the rising or falling edge of REF_CLK, and the timing is the same in either case. This options allows the use of non-compliant RMII PHYs. All timing specifications are referenced from REF_CLK = 1.4 V to the valid output levels. Table 52. RMII transmit signal timing Spec Characteristic R5 Value Unit Min Max REF_CLK to TXD[1:0], TX_EN invalid 2 -- ns R6 REF_CLK to TXD[1:0], TX_EN valid -- 16 ns R7 REF_CLK pulse width high 35% 65% REF_CLK period R8 REF_CLK pulse width low 35% 65% REF_CLK period SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 NXP Semiconductors 85 Obtaining package dimensions R7 REF_CLK (input) R5 R8 TXD[1:0] (outputs) TX_EN R6 Figure 47. RMII transmit signal timing diagram 18.4 UART timings UART channel frequency support is shown in the following table. Table 53. UART frequency support LINFlexD clock frequency LIN_CLK (MHz) Oversampling rate Voting scheme Max usable frequency (Mbaud) 80 16 3:1 majority voting 5 8 10 6 Limited voting on one sample with configurable sampling point 5 4 13.33 16 20 18.5 eMIOS timing Table 54. eMIOS timing Symbol Characteristic Condition tMIPW eMIOS Input Pulse Width eMIOS_CLK = 100 MHz Min. Value Max. Value Unit 2 -- cycles 19 Obtaining package dimensions Package dimensions are provided in package drawings. To find a package drawing, go to http://www.nxp.com and perform a keyword search for the drawing's document number. SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 86 NXP Semiconductors Thermal characteristics If you want the drawing for this package Then use this document number LQFP 144 PD 98ASS23177W LQFP 176 PD 98ASS23479W MAPBGA 252 PD 98ASA00468D MAPBGA 292 ED 98ASA00261D 20 Thermal characteristics The following tables describe the thermal characteristics of the device. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting side (board) temperature, ambient temperature, air flow, power dissipation or other components on the board, and board thermal resistance. Table 56. Thermal characteristics for the 144-pin LQFP package Rating Junction to Ambient Natural Convection Junction to Ambient Natural 1, 2 Convection1, 2, 3 Conditions Symbol Value Unit Single layer board (1s) RJA 41.3 C/W Four layer board (2s2p) RJA 33.0 C/W ft/min)1, 3 Single layer board (1s) RJMA 32.4 C/W Junction to Ambient (@200 ft/min)1, 3 Four layer board (2s2p) RJMA 26.7 C/W Junction to Board4 -- RJB 21.5 C/W 5 Junction to Ambient (@200 Junction to Case -- RJC 7.0 C/W Junction to Package Top6 Natural Convection JT 0.25 C/W Junction to Package Lead7 Natural Convection JB 16.5 C/W 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal. 3. Per JEDEC JESD51-6 with the board horizontal. 4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. 7. Thermal characterization parameter indicating the temperature difference between package bottom center and the junction temperature per JEDEC JESD51-12. Table 57. Thermal characteristics for the 176-pin LQFP package Rating Junction to Ambient Natural Convection Junction to Ambient Natural 1, 2 Convection1, 2, 3 Conditions Symbol Value Unit Single layer board (1s) RJA 49.9 C/W Four layer board (2s2p) RJA 33.8 C/W Table continues on the next page... SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 NXP Semiconductors 87 Thermal characteristics Table 57. Thermal characteristics for the 176-pin LQFP package (continued) Rating Conditions Symbol Value Unit Junction to Ambient (@200 ft/min)1, 3 Single layer board (1s) RJMA 37.8 C/W Junction to Ambient (@200 ft/min)1, 3 Four layer board (2s2p) RJMA 28.2 C/W Junction to Board4 -- RJB 21.0 C/W Case5 Junction to -- RJC 7.8 C/W Junction to Package Top6 Natural Convection JT 0.3 C/W Junction to Package Lead7 Natural Convection JB 13.0 C/W 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal. 3. Per JEDEC JESD51-6 with the board horizontal. 4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. 7. Thermal characterization parameter indicating the temperature difference between package bottom center and the junction temperature per JEDEC JESD51-12. Table 58. Thermal characteristics for the 252-pin MAPBGA package with full solder balls Rating Conditions Symbol Value Unit Junction to Ambient Natural Convection 1, 2 Single layer board (1s) RJA 43.0 C/W Convection1, 2, 3 Four layer board (2s2p) RJA 26.5 C/W Junction to Ambient (@200 ft/min)1, 3 Single layer board (1s) RJMA 33.2 C/W Junction to Ambient (@200 ft/min)1, 3 Junction to Ambient Natural Four layer board (2s2p) RJMA 22.2 C/W Junction to Board4 -- RJB 12.5 C/W Junction to Case5 -- RJC 6.3 C/W Top6 Natural Convection JT 0.3 C/W Junction to Package Lead7 Natural Convection JB 8.7 C/W Junction to Package 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal. 3. Per JEDEC JESD51-6 with the board horizontal. 4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 88 NXP Semiconductors Thermal characteristics 7. Thermal characterization parameter indicating the temperature difference between package bottom center and the junction temperature per JEDEC JESD51-12. Table 59. Thermal characteristics for the 252-pin MAPBGA package 16 removed balls: 12 central, 4 corner peripheral Rating Junction to Ambient Natural Junction to Convection1, 2, 3 Board4 Junction to Package Lead5 Conditions Symbol Value Unit Four layer board (2s2p) RJA 23.8 C/W Four layer board (2s2p) RJB 15.9 C/W Natural Convection JB 4.8 C/W 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal. 3. Per JEDEC JESD51-6 with the board horizontal. 4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 5. Thermal characterization parameter indicating the temperature difference between package bottom center and the junction temperature per JEDEC JESD51-12. 20.1 General notes for specifications at maximum junction temperature An estimation of the chip junction temperature, TJ, can be obtained from this equation: TJ = TA + (RJA x PD) where: * TA = ambient temperature for the package (C) * RJA = junction to ambient thermal resistance (C/W) * PD = power dissipation in the package (W) The junction to ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal performance. Unfortunately, there are two values in common usage: the value determined on a single layer board and the value obtained on a board with two planes. For packages such as the PBGA, these values can be different by a factor of two. Which value is closer to the application depends on the power dissipated by other components on the board. The value obtained on a single layer board is appropriate for the tightly packed printed circuit board. The value obtained on the board with the internal planes is usually appropriate if the board has low power dissipation and the components are well separated. When a heat sink is used, the thermal resistance is expressed in the following equation as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: RJA = RJC + RCA SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 NXP Semiconductors 89 Ordering information where: * RJA = junction to ambient thermal resistance (C/W) * RJC = junction to case thermal resistance (C/W) * RCA = case to ambient thermal resistance (C/W) RJC is device related and cannot be influenced by the user. The user controls the thermal environment to change the case to ambient thermal resistance, RCA. For instance, the user can change the size of the heat sink, the air flow around the device, the interface material, the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. To determine the junction temperature of the device in the application when heat sinks are not used, the Thermal Characterization Parameter (JT) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using this equation: TJ = TT + (JT x PD) where: * TT = thermocouple temperature on top of the package (C) * JT = thermal characterization parameter (C/W) * PD = power dissipation in the package (W) The thermal characterization parameter is measured per JESD51-2 specification using a 40 gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. 21 Ordering information Table 60. Ordering information Part Number Device Type Flash/SRAM Emulation RAM Package Frequency PD1 SPC5746RK1MMT5 Sample 4M / 256 KB - 252 MAPBGA 200 MHz SPC5746RK1MLU3 Sample PD 4M/256KB - 176 LQFP 150 MHz SPC5745RK1MMT5 Sample PD 3M/192KB - 252 MAPBGA 200 MHz SPC5745RK1MLU3 Sample PD 3M / 192 KB - 176 LQFP 150 MHz SPC5743RK1MLU5 Sample PD 2M / 128KB - 176 LQFP 200 MHz SPC5743RK1MLQ5 Sample PD 2M / 128 KB - 144 LQFP 200 MHz ED2 4M / 256 KB 1 MB 292 MAPBGA 200 MHz PPC5746R2K1MMZ5A Sample SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 90 NXP Semiconductors Revision history 1. "PD" refers to a production device, orderable in quantity. 2. "ED" refers to an emulation device, orderable in limited quantities. An emulation device (ED) is for use during system development only and is not to be used in production. An ED is a Production PD chip combined with a companion chip to form an Emulation and Debug Device (ED) and includes additional RAM memory and debug features. EDs are provided "as is" without warranty of any kind. In the event of a suspected ED failure, NXP agrees to exchange the suspected failing ED from the customer at no additional charge, however NXP will not analyze ED returns. 22 Revision history Table 61. Revision history Revision Date Description of changes 1 05/2013 Initial release. 2 12/2014 Overall: * Editorial changes. * Removed the Classification columns in spec tables and removed statements that values need to be characterized. * In footnotes changed cross references to figures to static text. In section Block diagram : * In Figure 1, changed "AIPS Bridge 0/1" to "AIPS PBridge_0/1". * In Figure 2 : * Changed figure title (was "Peripherals block diagram"). * Changed "BAF" to "BAR". * Added PBRIDGE_1, EIM, XBAR, and PBRIDGE_0. In section Introduction, removed section "Parameter classification". In section Absolute maximum ratings, Table 1 : * VDD_HV_IO_FEC spec: removed row for "Using Ethernet Reference to VSS" condition. * Corrected "VIDD_HV_IO_MSC" to "VDD_HV_IO_MSC". * Add parameter IIOMAX. * Deleted IMAXSEG parameter. In section Operating conditions : * Deleted sentence "The ranges in this table are design targets...". * Added a NOTE that all power supplies need to be powered up. * In Table 3 : * Removed VDD_HV_FLA. * Changed minimum voltage of VDD_HV_ADV_SD. * Modified footnote for S/D ADC supply voltage. * Modified footnote for SAR ADC supply voltage. * Modified VRAMP spec to two separate specs for "VRAMP_VDD_LV" and "VRAMP_VDD_HV_IO_MAIN, VRAMP_VDD_HV_PMC". In section DC electrical specifications : * Removed the statement that the ranges are design targets. * In Table 5 : * Modified IDD_LV to show specs depending on device model. Modified footnote. * Removed the "PMC only" row of the IDD_HV_PMC "internal core reg bypassed" spec. * Removed IDD_MAIN_CORE_AC. * Removed IDD_LKSTP_AC. * Changed IDDSTBY_ON value at 40 C. * Changed IDDSTBY_REG parameter to "32 KB RAM Standby Regulator Current" (was "Standby Leakage Current"); changed condition to "VDDSTBY @1.2 V to 5.9 V, Tj = 150C" (was "VDDSTBY @1.3 V...") Table continues on the next page... SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 NXP Semiconductors 91 Revision history Table 61. Revision history Revision Date Description of changes * Removed IDDOFF. * Added IDD_BD_STBY. * Added IVDDA. In section Input pad specifications : * In Table 7 : * Added footnote that supported input levels vary according to pad types. * Corrected VILTTL Min and Max values. * Corrected VIHAUTO, VILCMOS_H and VILCMOS Min value. * In Table 8 : * Modified |IWPU| Min values for condition Vin = VIH = 0.65 * VDD_HV_IO. * Modified |IWPD| Min values for condition Vin = VIL = 0.35 * VDD_HV_IO. * Removed the "Analog Input Leakeage and Pull-Up/Down DC electrical characteristics" table and the preceding introductory paragraph to be moved to the ADC input description section. In section Output pad specifications, Table 9, changed VOH and VOL specs to two separate specs for 3V pads and 5V pads respectively. Corrected VOH Min and VOL Max values. In section I/O pad current specifications : * Added I/O Current Consumption tables. * Modified NOTE on Excel file attached to the Reference Manual. Added section Reset pad (PORST, RESET) electrical characteristics. In section Oscillator and FMPLL : * In Table 13, removed PLL0_PHI0 single period jitter row. * In Table 15 : * Modified footnote for CS_EXTAL and CS_XTAL. * Modified gm (Oscillator Transconductance) spec. * Removed VHYS. In section ADC modules, revised the subsection structure and titles: * Added section ADC input description with content moved from the "Input pad specifications" section. * Section "Input impedance and ADC accuracy" renamed to Input equivalent circuit and ADC conversion characteristics with all content except Figure 11 and Table 19 removed. * Removed erroneous section "SAR ADC electrical specification". In section SAR ADC, Table 19 : * Added footnote ("SAR ADC performance is not guaranteed...") to fCK symbol. * Changed tsample specification min value to 250 ns (was 275). * Added footnote to OFS and GNE. Changed OFS and GNE min and max values. * Removed "Input (singe ADC channel)". * Removed injection row for "Input (double ADC channel)". * SNR, THD, SINAD, and ENOB specifications: changed frequency condition to 50 kHz (was 125 kHz). * Changed SNR Min values. * Added footnote to ENOB. * Added IDD_VDDA, IDD_VDDR, and VBG_REF parameters. In section S/D ADC, Table 20 : * For VIN_PK2PK parameter second and third rows, changed VSS in Conditions to VDD. * For fADCD_M specification, removed sampling frequency footnote from parameter. * Added footnote to RESOLUTION value. * For |GAIN| specification added footnote to parameter and added new row with more detailed "After calibration" conditions. * Moved footnote "S/D ADC is functional in the range..." from the ZIN to the SNR parameters. Table continues on the next page... SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 92 NXP Semiconductors Revision history Table 61. Revision history Revision Date Description of changes * Changed all instances of "4.0 < VDD_HV_ADV_SD < 5.5" in the Conditions column to "4.5 < VDD_HV_ADV_SD < 5.5". Modified voltage range in its footnote. * Changed SNRSE150, GAIN = 16 condition min value to 55 dB (was 60). * Changed SINADSE150, GAIN = 16 condition min value to 54 dB (was 59). * Unit for SINADDIFF150, SINADDIFF333 and SINADSE150 changed from dBFs to dB. * For ZIN specification, revised parameter footnote. * Added CMRR to symbol column for Common mode rejection ratio specification. Changed min value to 55 dB. * For GROUP specification, revised maximum values for OSR = 24 to OSR = 256 conditions. * Revised entire row for tLATENCY, tSETTLING, and tODRECOVERY specifications. Footnote added to tLATENCY parameter. * Added IBIAS specification. * Changed IADV_D and IADR_D values. In section Temperature sensor, Table 21 : * Changed TACC values. * Removed ITEMP_SENS spec item. In section LFAST interface timing diagrams, Figure 12, "|VOD|" changed to "|VOD|". In section LFAST and MSC /DSPI LVDS interface electrical characteristics, Table 24, the max. value for Rise/ Fall time specs changed from 4.0 to 5.7 ns. In section LFAST PLL electrical characteristics, Table 25, PEREYE specification, changed Nominal value to 550 (was blank) and Max value to blank (was 400). In section Recommended power transistors, Table 27, added the specification for VC. In section Power management integration : * In Figure 17 : * Changed "n x CLV" to "CLV". * Changed CHV_ADC_S to CHV_ADC_SAR. * In Table 28 : * Changed the first footnote for CHV_PMC to have the same footnote number as the first footnote for CLV as they were identical. * Modified Minimum VDD_HV_ADV_SAR external capacitance and associated footnote. Added section Regulator example for the NJD2873 transistor. Added section Regulator example for the 2SCR574d transistor. In section Device voltage monitoring, Table 29 : * Updated following specs: * LVD_core_hot * LVD_core_cold * HVD_core * LVD_HV * HVD_HV * LVD_IO * LVD_SAR * Removed following specs: * LVD_FLASH * HVD_FLASH * LVD_MSC_3V3 * LVD_MSC_5V0 * LVD_FEC_5V0 * LVD_JTAG * HVD_SAR Table continues on the next page... SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 NXP Semiconductors 93 Revision history Table 61. Revision history Revision Date Description of changes * LVD_SD * HVD_SD * Corrected Voltage detector threshold crossing assertion Unit. In section Flash memory program and erase specifications, Table 30 : * Removed parenthetical phrase from table title. * Made overall updates to spec values. * Removed footnote 7. In section Flash memory Array Integrity and Margin Read specifications, Table 31 : * Removed parenthetical phrase from table title. * Made overall updates to spec values. In section Flash memory module life specifications, Table 32, removed parenthetical phrase from table title. In section Flash memory AC timing specifications, Table 33, removed parenthetical phrase from table title. Added section Flash read wait state and address pipeline control settings. In section Power management integration, Table 28, changed the footnotes for tTCYC Min values to have the same footnote number as they were identical. In section DSPI timing with CMOS and LVDS, Table 39, LVDS (Master mode) specification: changed Max usuable frequency to 40 MHz (was 33 MHz). In section DSPI CMOS master mode - classic timing : * Added NOTE. * In Table 40, changed PCS strobe timing values. In section DSPI CMOS master mode - modified timing : * Added NOTE. * In Table 41, changed PCS strobe timing values. In section DSPI LVDS master mode - modified timing, Table 42, changed significant digits for some values. In section DSPI master mode - output only : * Modified format paragraphs leading the tables. Removed NOTE. * In Table 43, changed the tCSV strong drive value and tHO LVDS value. * In Table 44, changed significant digits for some values. In section FEC timing, corrected the title of MII-lite and RMII serial management channel timing subsections. In section MII-lite transmit signal timing (TXD[3:0], TX_EN, TX_ER, TX_CLK), Table 47, modified footnote for output parameters. In section RMII serial management channel timing (MDIO and MDC), added Note on reference for timing specifications. In section RMII transmit signal timing (TXD[1:0], TX_EN), Table 52, modified R6 max value. In section UART timings, Table 53, removed 100 MHz specification. "Package drawings" section renamed to Obtaining package dimensions, with package drawing document numbers to search at the Freescale website. Drawings removed from this document. In section Thermal characteristics : * Added table for 144 LQFP. Table continues on the next page... SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 94 NXP Semiconductors Revision history Table 61. Revision history (continued) Revision Date Description of changes * Moved table for 176 LQFP before 252 MAPBGA and updated table. * Replaced table for 252 MAPBGA with two separate tables for package with full solder balls and package with 16 removed balls. In section Ordering information, replaced the table. 3 09/2015 On the cover page: * Changed doctype from "Data Sheet: Product Preview" to "Data Sheet: Technical Data" at the upper left corner. * Changed statement on status of doc at the bottom of the page. Removed "Preliminary" and "Non-Disclosure Agreement required" from footers on each page. In section Electromagnetic Compatibility (EMC) removed content of entire section and replaced it with statement: "EMC measurements to IC-level IEC standards are available from Freescale on request." In section Operating conditions : * In Table 3 * For VDD_HV_PMC, removed the two footnotes. * For VDDSTBY, added statement on ramp rate to footnote. * For VSTBY_BO, removed Min value and added Max value. In section DC electrical specifications : * In Table 5 : * IDD_LV spec: * MPC5746R/MPC5745R Max value changed to 700 mA. * MPC5743R/MPC5742R Max value changed to 610 mA. * IDDSTBY_ON TA=40C and TA=85C values updated. * IVDDA values updated. In section I/O pad specification, Table 6 Description for Input only pads, removed reference to "Automotive" input. In section Input pad specifications, Table 7 removed VIHAUTO, VILAUTO, VHYSAUTO, and VDRFTAUTO specs and references to "Automotive" input in footnotes. In section Output pad specifications : * In Table 9, removed footnote for tR_F spec Parameter about transition time maximum value approximation formula. In section Reset pad (PORST, RESET) electrical characteristics : * In Table 12 : * Changed specs for VIH, VIL, and VHYS to VIH Reset, VIL Reset, and VHYS Reset respectively. * Added specs for VIH PORST, VIL PORST, VHYS PORST. * Generally added Conditions and updated spec values. In the Conditions column, changed all instances of "3.0 V" to "3.5 V". In section Oscillator and FMPLL : * In Table 13, for PLL0LTJ spec, modified long term jitter Min and Max values. * In Table 16, values updated. * In Table 17, added spec for dfTRIM (IRC software trimming step). In section ADC input description : * In Table 18 : * RPUPD 5K spec Max value changed to 8.8K. In section Input equivalent circuit and ADC conversion characteristics : Table continues on the next page... SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 NXP Semiconductors 95 Revision history Table 61. Revision history (continued) Revision Date Description of changes * In Table 19 : * In the SNR, THD, SINAD, and ENOB rows Conditions, changed "50 kHz" to "125 kHz". Modified footnote to ENOB * In IDD_VDDA and IDD_VDDR rows, modified values. * In VBG_REF row's Conditions, added "INPSAMP=0xFF" * Added NOTE "For spec complaint operation, do not expose clock sources, including crystal oscillator, IRC, PLL0, and PLL1 on the CLKOUT pads while the SAR ADC is converting." * Added NOTE: "The ADC performance specifications are not guaranteed if two or more ADCs simultaneously sample the same shared channel". In section S/D ADC : * In Table 20 : * For THDDIFF333 GAIN = 16, updated Min value. * For IADV_D, updated Max value. In section LFAST and MSC /DSPI LVDS interface electrical characteristics : * After table Table 24 added NOTE "For optimum LVDS performance, it is recommended to set the neighbouring GPIO pads to use Weak Drive". In section Device voltage monitoring : * In Table 29 : * For LVD_core_hot, LVD_HV, and LVD_IO specs, removed the untrimmed Rising voltage and Falling voltage rows. * For LVD_core_hot, changed Mask Opt. value to "No". In section Regulator example for the 2SCR574d transistor, figure "Regulator example", changed "5V or Vcollector" to "3.3V or Vcollector". In section DSPI CMOS master mode - classic timing, Table 40 : * Changed tSDC spec's Condition SCK drive strength from "0 pF" to "0 to 50 pF". * In tSUI and tHI specs' footnote, removed reference to "Automotive" thresholds. In section DSPI CMOS master mode - modified timing, Table 41 : * Changed tSDC spec's Condition SCK drive strength from "0 pF" to "0 to 50 pF". * In tSUI and tHI specs' footnote, removed reference to "Automotive" thresholds. In section DSPI master mode - output only, Table 44, changed tSDC spec's Condition SCK drive strength from "0 pF" to "0 to 50 pF". Added section eMIOS timing. In section Ordering information, Table 60 : * Updated Part Numbers. * Updated Emulation device footnote. 4 03/2016 In section Block diagram, Figure 2 : * "DECIM" changed to "DECFILTER". * "SIPI" changed to "Zipwire". * I/O lines added to Zipwire, SIUL2, REACM, eTPU, eMIOS, IGF, and XOSC. In section Absolute maximum ratings table "Absolute maximum ratings", removed IIOMAX spec and added IMAXSEG spec. In section Operating conditions table "Device operating conditions": * For the FEC I/O supply voltage, MSC I/O supply voltage, and JTAG I/O supply voltage specs, removed the LVD enabled/disabled distinction. * Added footnote to IMAXSEG. In section I/O pad current specifications : Table continues on the next page... SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 96 NXP Semiconductors Revision history Table 61. Revision history (continued) Revision Date Description of changes * Modified the descriptions in the two paragraphs after the tables. * Removed the third paragraph after the tables and the first Note. Added section DSPI CMOS slave mode. In section Ordering information table "Ordering Information", changed Part Numbers for the 176 LQFP PD and the ED. 5 10/2016 Editorial updates. In section Operating conditions table "Device operating conditions" added foootnote to VDD_HV_IO_JTAG. In section Input pad specifications table "I/O input DC electrical characteristics" for ILKG added condition "VSS < VIN < VDD_HV_IO*" In section ADC input description table "Analog Input Leakage and Pull-Up/Down DC electrical characteristics" for ILK_AD added conditions "VSS_HV_ADV_SAR < VIN < VDD_HV_ADV_SAR" and "VSS_HV_ADV_SD < VIN < VDD_HV_ADV_SD". In section Recommended power transistors table "Recommended operating characteristics" for ICMaxDC changed the parameter from "Minimum peak collector current" to "Maximum DC collector current". In section SAR ADC table "ADC conversion characteristics": * Removed the condition for tsample. * Removed the Min and added the formula (6.02*ENOB) + 1.76 for SINAD. * Changed the Min value from 650 to 700 for tconv. In section S/D ADC table "SDn ADC electrical specification": * Removed ZIN specification * Added ZDIFF, ZCM, and VINTCM specifications * For RBIAS: * Changed Parameter description from "Bias resistance" to "Bare bias resistance" * Changed Min from 100 k to 110 k * Changed Typ from 125 k to 144 k * Changed Max from 160 k to 180 k In section Flash memory AC timing specifications table "Flash memory AC timing specifications" for tpsus: * Changed Typical from 7 s plus four system clock periods to 9.4 s plus four system clock periods * Changed Max from 9.1 s plus four system clock periods to 11.5 s plus four system clock periods 6 05/2017 Changed Freescale to NXP throughout the datasheet. In Ordering information added rows for SPC5746RK1MLU3, SPC5745RK1MMT5 and SPC5743RK1MLU5. In Table 3 added footnote in VDD_HV_PMC In Table 28 for the rowset CHV_FLA changed the Minimum and Typical values. 7 01/2020 In Table 20 : * Changed the condition of GROUP from "Within pass band - Tclk is fADCD_M/ 2" to "Within pass band - Tclk is 2/fADCD_M". * In the footnote of tLATENCY changed the Register Latency formula from "REGISTER LATENCY = tLATENCY + 0.5/fADCD_S + 2 (~+1)/fADCD_M + 2(~+1)fPBRIDGEx_CLK where fADCD_S is the frequency of the sampling clock, fADCD_M is the frequency of the modulator" to "REGISTER LATENCY = tLATENCY + 0.5/fADCD_S + 2 (~+1)/fADCD_M + 2(~+1)/fPBRIDGEx_CLK SPC5746R Microcontroller Data Sheet, Rev. 7, 02/2020 NXP Semiconductors 97 Revision history Table 61. Revision history Revision Date Description of changes where fADCD_S is the after-decimation ADC output data rate, fADCD_M/2 is the modulator sampling rate and fPBRIDGEx_CLK is the frequency of the peripheral bridge clock feeds to the ADC S/D module". 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All other product or service names are the property of their respective owners. AMBA, Arm, Arm7, Arm7TDMI, Arm9, Arm11, Artisan, big.LITTLE, Cordio, CoreLink, CoreSight, Cortex, DesignStart, DynamIQ, Jazelle, Keil, Mali, Mbed, Mbed Enabled, NEON, POP, RealView, SecurCore, Socrates, Thumb, TrustZone, ULINK, ULINK2, ULINK-ME, ULINK-PLUS, ULINKpro, Vision, Versatile are trademarks or registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere. The related technology may be protected by any or all of patents, copyrights, designs and trade secrets. All rights reserved. Oracle and Java are registered trademarks of Oracle and/or its affiliates. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. (c) 2013-2020 NXP B.V. Document Number MPC5746R Revision 7, 02/2020