1
Copyright
©
Cirrus Logic, Inc. 1997
(All Rights Reserved)
Cirrus Logic, Inc.
Crystal Semiconductor Products Divisio n
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.crystal.com
CS5505/6/7/8
Very Low Power, 16-Bit and 20-Bit A/D Converters
Features
lVery Low Power Consumption
-Single supply +5 V operation: 1.7 mW
-Dual supply ±5 V operati on: 3.2 mW
lOffers superior performance to VFCs and
multi-slope integrating ADCs
lDifferential Inputs
-Single Channel (CS5507/8) and Four-Channel
(CS5505/6) pseudo- differential versions
lEither 5 V or 3.3 V Digital Interface
lLineari ty Error:
-±0.0015% FS (16-bit CS5505/ 7)
-±0.0007% FS (20-bit CS5506/ 8)
lOutput update rates up to 100 Sps
lFlexible Serial Port
lPin-Selectable Unipolar/Bipolar Ranges
Description
The CS5505/6/7/8 are a family of low power CMOS A/D
conver ters whi ch are idea l for m easurin g low- frequen cy
signals representing physical, chemical, and biological
processes.
The CS5507/8 have single-channel differential analog
and reference inputs while the CS5505/6 have four
pseudo-differential analog input channels. The
CS5505/7 have a 16-bit output word. The CS5506/8
have a 20-bit output word.The CS5505/6/7/8 sample
upon command up to 100 Sps.
The on-chip digital filter offers superior line rejection at
50 and 60 Hz when the device is operated from a
32.768 kHz clock (output word rate = 20 Sps).
The CS5505/6/7/8 include on-chip self-calibration cir-
cuitry which can be ini tiated at any time or temper ature
to ensure minimum offset and full-scale errors.
The CS5505/6/7/8 serial port offers two general-purpose
modes for the direct interface to shift registers or syn-
chronous serial ports of industry-standard
microcontrollers.
ORDERING INFORMATION
See page 30.
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MAR ‘95
DS59F4
Copyright © Cirrus Logic, Inc. 2005
(All Rights Reserved)
http://www.cirrus.com
CS5505/6/7/8
Very Low-power, 16-bit & 20-bit A/D Converters
AUG ‘05
DS59F5
Copyright © Cirrus Logic, Inc. 2005
(All Rights Reserved)
http://www.cirrus.com
CDB5505/6/7/8
Evaluation Board for CS5505/6/7/8 Series of ADCs
AUG ‘05
DS59DB3
Copyright © Cirrus Logic, Inc. 2005
(All Rights Reserved)
http://www.cirrus.com
CS5505/6/7/8
Very Low-power, 16-bit & 20-bit A/D Converters
AUG ‘05
DS59F5
ANALOG CHARACTERISTICS (TA = TMIN to TMAX; VA+ = 5V ± 10%; VA- = -5V ± 10%; VD+ =
3.3V ± 5%; VRE F+ = 2.5V(external); VREF- = 0V ; fCLK = 32.768kHz; Bi polar Mode; Rsource = 1kΩ with a 10nF
to AGND at AIN; Analog input channel AIN1+; AIN- = AGND; unless otherwise specified.) (Notes 1, 2)
CS5505/7-A CS5507-S
Parameter* Min Typ Max Min Typ Max Units
Specified Temperature Range -40 to +85 -55 to +125 °C
Accuracy
Linearity Error - 0.0015 0.003 - 0.0015 0.003 ±%FS
Differential Nonlinear ity - ±0.25 ±0.5 -±0.25 ±0.5 LSB16
Full Scale Error (Note 3) - ±0.25 ±2-±0.5 ±2LSB16
Full Scale Drift (Note 4) - ±0.5 --
±
2
-LSB
16
Unipolar Offset (Note 3) - ±0.5 ±2-±1±4LSB16
Unipolar Offset Drift (Note 4) - ±0.5 --
±
1
-LSB
16
Bipolar Offset (Note 3) - ±0.25 ±1-±0.5 ±2LSB16
Bipolar Offset Drift (Note 4) - ±0.25 --
±
0.5 -LSB
16
Noise (Referred to Output) - 0.16 - - 0.16 - LSB-
rms16
Notes: 1. The AIN pin presents a very high input r esistance at dc and a minor dynamic load whi ch scales to the
master clock frequency. Both source resistance and shunt capacitance are therefore critical in
determining the CS5505/6/7/8’s source impedance requirements. For more information refer to the
text section
Analog Input Impedance Considerations.
2. Specifications guaranteed by design, characterization and/or test.
3. Applies after c alibration at the temperature of i nterest.
4. Total drift over the specified temperature range since calibration at power-up at 25°C.
Recalibration at any temperature will remove these er rors.
Specific ations are subject to change without notice.
* Refer to the Specification Definitions immediately following the Pin Description Section.
Unipolar Mode Bipolar Mode
mV LSB’s % FS ppm FS LSB’s % FS ppm FS
10 0.26 0.0004 4 0.13 0.0002 2
19 0.50 0.0008 8 0.26 0.0004 4
38 1.00 0.0015 15 0.50 0.0008 8
76 2.00 0.0030 30 1.00 0.0015 15
152 4.00 0.0061 61 2.00 0.0030 30
VREF = 2.5V
CS5505/7; 16-Bit Unit Convers ion Factors
CS5505/6/7/8
2 DS59F4
CS5505/6/7/8
2DS59F5
ANALOG CHARACTERISTICS (TA = TMIN to TMAX; VA+ = 5V ± 10%; VA- = -5V ± 10%; VD+ =
3.3V ± 5%; VREF+ = 2.5V (exter nal); VREF- = 0V; fCLK = 32.768kHz; Bipolar Mode; Rsource = 1kΩ with a
10nF to AGND at AIN; Analog input channel AIN1+; AIN- = AG ND; unless otherwise speci fied.) (Notes 1, 2)
CS5506/8-B CS5508-S
Parameter* Min Typ Max Min Typ Max Units
Specified Temperature Range -40 to +85 -55 to +125 °C
Accuracy
Linearity Error - 0.0007 0.0015 - 0.0015 0.003 ±%FS
Differential Nonlinear ity
(No Missing Codes) 20 - - 20 - - Bits
Full Scale Error (Note 3) - ±4±32 -±8±32 LSB20
Full Scale Drift (Note 4) - ±8--
±
32 -LSB
20
Unipolar Offset (Note 3) - ±8±32 -±16 ±64 LSB20
Unipolar Offset Drift (Note 4) - ±8--
±
16 -LSB
20
Bipolar Offset (Note 3) - ±4±16 -±8±32 LSB20
Bipolar Offset Drift (Note 4) - ±4--
±
8
-LSB
20
Noise (Referred to Output) - 2.6 - - 2.6 - LSB-
rms20
Unipolar Mode Bipolar Mode
mV LSB’s % FS ppm FS LSB’s % FS ppm FS
0.596 0.25 0.0000238 0.24 0.13 0.0000119 0.12
1.192 0.50 0.0000477 0.47 0.26 0.0000238 0.24
2.384 1.00 0.0000954 0.95 0.50 0.0000477 0.47
4.768 2.00 0.0001907 1.91 1.00 0.0000954 0.95
9.537 4.00 0.0003814 3.81 2.00 0.0001907 1.91
VREF = 2.5V
CS5506/8; 20-Bit Unit Convers ion Factors
DYNAMIC CHARACTERISTICS
Parameter Symbol Ratio Units
Modulator Sampling Frequenc y fsfclk/2 Hz
Output Update Rate (CONV = 1) fout fclk/1622 Sps
Filter Corner Frequency f-3dB fclk/1928 Hz
Settling Time to 1⁄2 LSB (FS Step) ts1/fout s
CS5505/6/7/8
DS59F4 3
CS5505/6/7/8
DS59F5 3
ANALOG CHARACTERISTICS (TA = TMIN to TMAX; VA+ = 5V ± 10%; VA- = -5V ± 10%; VD+ =
3.3V ± 5%; VRE F+ = 2.5V (external); VREF- = 0V; f CLK = 32.768kHz; Bipolar Mode; Rsource = 1kΩ with a
10nF to AGND at AIN; Analog input channel AIN1+; AIN- = AG ND; unless otherwise speci fied.) (Notes 1, 2)
CS5505/7
CS5506/8 CS5507/8-S
Parameter* Min Typ Max Min Typ Max Units
Specified Temperature Range -40 to +85 -55 to +125 °C
Ana log Inpu t
Analog Input Range: Unipolar
(VAIN+)-(VAIN-) Bipolar (Note 5) 0 to +2.5
±2.5 0 to +2.5
±2.5 Volts
Volts
Common Mode Rejection: dc
50, 60 Hz (Note 6) -
120 105
--
--
120 105
--
-dB
dB
Off Channel Isolati on - 120 - - 120 - dB
Input Capacitance - 15 - - 15 - pF
DC Bias Current (Note 1) - 5 - - 5 - nA
Voltage Reference (Output)
VREFOUT Voltage - (VA+)-2.5 - - (VA+)-2.5 - Volts
VREFOUT Voltage Tolerance - - 4.0 - - 4.0 %
VREFOUT Voltage Temperature Coefficient - 60 - - 60 - ppm/°C
VREFOUT Line Regul ation - 1.5 - - 1.5 - mV/Volt
VREFOUT Output V oltage Noise
0.1 to 10 Hz -50- -50-
µ
V
p-p
VREFOUT: Source Current
Sink Current -
--
-3
50 -
--
-3
50 µA
µA
Power Supplies
DC Power S upply Currents: ITotal
IAnalog
IDigital
-
-
-
340
300
40
450
-
-
-
-
-
340
300
40
450
-
-
µA
µA
µA
Power Dissipation: (Note 7)
SLEEP inactive
SLEEP active -
-3.2
54.5
10 -
-3.2
10 4.5
25 mW
µW
Power Supply Rejection: Positive Supplies
Negative Suppli es -
-80
80 -
--
-80
80 -
-dB
dB
Notes: 5. Common mode voltage may be at any value as long as AIN+ and AIN- remain within the VA+ and
VA- supply voltages.
6. XIN = 32.768 kHz. Guaranteed by design and / or characterization.
7. All outputs unloaded. All inputs CMOS levels. SLEEP mode controlled by M/SLP pin.
SLEEP ac tive = M/SLP pin at (VD+)/2 input level.
CS5505/6/7/8
4 DS59F4
CS5505/6/7/8
4DS59F5
5V DIGITAL CHARACTERISTICS (TA = TMIN to TMAX; VA+VD+ = 5V ± 10%; VA-= -5V ± 10%;
DGND = 0.) All measurements below are performed under static c onditions. (Note 2)
Parameter Symbol Min Typ Max Units
High-Level Input Voltage: XIN
M/SLP
All Pins Except XIN and M/SLP
VIH
VIH
VIH
3.5
0.9VD+
2.0
-
-
-
-
-
-
V
V
V
Low-Level Input Voltage: XIN
M/SLP
All Pins Except XIN and M/SLP
VIL
VIL
VIL
-
-
-
-
-
-
1.5
0.1VD+
0.8
V
V
V
M/SLP SLEE P Active Thres hold (Note 8) VSLP 0.45VD+ 0.5VD+ 0.55VD+ V
High-Level Output V oltage (Note 9) VOH (VD+)-1.0 - - V
Low Level Output Voltage Iout = 1.6 mA VOL --0.4V
Input Leakage Current Iin -110
µ
A
3-State Leakage Current IOZ --
±
10 µA
Digital Output Pin Capacitance Cout -9-pF
Notes: 8. Under normal operation this pin should be ti ed to VD+ or DGND. Anyti me the voltage on the M/S LP
pin enters the SLEEP active threshold range the device will enter the power down condition. Returning
to the active state requires elapse of the power-on reset period, the oscillator to start-up, and elapse
of the wake-up period.
9. Iout = -100 µA. This guarantees the ability to driv e one TTL load. (VOH = 2.4V @ Iout = -40 µA).
3.3V DIGITAL CHARACTERISTICS (TA = TMIN to TMAX; VA+ = 5V ± 10%; VD+ = 3.3V ± 5%;
VA-= -5V ± 10%; DGND = 0.) All measurements below are performed under static conditions. (Note 2)
Parameter Symbol Min Typ Max Units
High-Level Input Voltage: XIN
M/SLP
All Pins Except XIN and M/SLP
VIH
VIH
VIH
0.7VD+
0.9VD+
0.6VD+
-
-
-
-
-
-
V
V
V
Low-Level Input Voltage: XIN
M/SLP
All Pins Except XIN and M/SLP
VIL
VIL
VIL
-
-
-
-
-
-
0.3VD+
0.1VD+
0.16VD+
V
V
V
M/SLP SLEE P Active Thres hold (Note 8) VSLP 0.43VD+ 0.45VD+ 0.47VD+ V
High-Level Output V oltage Iout = -400 µAVOH (VD+)-0.3 - - V
Low Level Output Voltage Iout = 400 µAVOL --0.3V
Input Leakage Current Iin -110
µA
3-State Leakage Current IOZ --
±10 µA
Digital Output Pin Capacitance Cout -9-pF
CS5505/6/7/8
DS59F4 5
CS5505/6/7/8
DS59F5 5
5V SWITCHING CHARACTERISTICS (TA = TMIN to TMAX; VA+, VD+ = 5V ± 10%;
VA- = -5V ± 10%; Input Levels: Logic 0 = 0V, Logic 1 = V D+; CL = 50 pF.) (Note 2)
Parameter Symbol Min Typ Max Units
Master Clock Frequency: Internal Oscillator: -A,B
-S
External Clock:
XIN
or
fclk
30.0
30.0
30
32.768
32.768
-
53.0
34.0
163
kHz
kHz
kHz
Master Clock Duty Cycle 40 - 60 %
Rise Times: Any Digital Input (Note 10)
Any Digital Output trise -
--
50 1.0
-µs
ns
Fall Times: Any Digital Input (Note 10)
Any Digital Output tfall -
--
20 1.0
-µs
ns
Start-Up
Power-On Reset Peri od (Note 11) tres -10-ms
Oscillator Start-up Time XTAL=32.768 kHz (Note 12) tosu - 500 - ms
Wake-up Period (Note 13) twup - 1800/fclk -s
Calibration
CONV Puls e Width (CAL = 1) (Note 14) tccw 100 - - ns
CONV and CAL High to Start of Calibration tscl --2/f
clk+200 ns
Start of Calibration to End of Calibration tcal - 3246/fclk -s
Conversion
Set Up Time A0, A1 to CONV Hi gh tsac 50 - - ns
Hold Time A0, A1 after CONV High thca 100 - - ns
CONV Pulse Width tcpw 100 - - ns
CONV High to Start of Conversion tscn --2/f
clk+200 ns
Set Up Time BP/UP stable prior to DRDY falling tbus 82/fclk --s
Hold Time BP/UP stable after DRDY falls tbuh 0--ns
Start of Conversion to End of Conversion (Note 15) tcon - 1624/fclk -s
Notes: 10. Specified using 10% and 90% points on wav eform of interest.
11. An internal power-on-reset is activated whenever power is applied to the device, or when coming out
of a SLEEP state.
12. Oscillator start-up time varies with the crystal parameters. This specification does not apply when
using an external clock source.
13. The wake-up period begins once the oscillator starts;
or when using an external fclk, after the power-on reset time elapses.
14. Calibration can al so be initiated by pul sing CAL high while CONV=1.
15. Conversion time wi ll be 1622/fclk if CONV remains hi gh continuously.
CS5505/6/7/8
6 DS59F4
CS5505/6/7/8
6DS59F5
3.3V SWITCHING CHARACTERISTICS (TA = TMIN to TMAX VA+ = 5V ± 10%;
VD+ = 3.3V ± 5%; VA- = -5V ± 10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF.) (Note 2)
Parameter Symbol Min Typ Max Units
Master Clock Frequency: Internal Oscillator: -A,B
-S
External Clock:
XIN
or
fclk
30.0
30.0
30
32.768
32.768
-
53.0
34.0
163
kHz
kHz
kHz
Master Clock Duty Cycle 40 - 60 %
Rise Times: Any Digital Input (Note 10)
Any Digital Output trise -
--
50 1.0
-µs
ns
Fall Times: Any Digital Input (Note 10)
Any Digital Output tfall -
--
20 1.0
-µs
ns
Start-Up
Power-On Reset Peri od (Note 11) tres -10-ms
Oscillator Start-up Time XTAL=32.768 kHz (Note 12) tosu - 500 - ms
Wake-up Period (Note 13) twup - 1800/fclk -s
Calibration
CONV Puls e Width (CAL = 1) (Note 14) tccw 100 - - ns
CONV and CAL High to Start of Calibration tscl --2/f
clk+200 ns
Start of Calibration to End of Calibration tcal - 3246/fclk -s
Conversion
Set Up Time A0, A1 to CONV Hi gh tsac 50 - - ns
Hold Time A0, A1 after CONV High thca 100 - - ns
CONV Pulse Width tcpw 100 - - ns
CONV High to Start of Conversion tscn --2/f
clk+200 ns
Set Up Time BP/UP stable prior to DRDY falling tbus 82/fclk --s
Hold Time BP/UP stable after DRDY falls tbuh 0--ns
Start of Conversion to End of Conversion (Note 15) tcon - 1624/fclk -s
CS5505/6/7/8
DS59F4 7
CS5505/6/7/8
DS59F5 7
t
ccw
XIN
Calibration StandbyStandby
t
scl
t
cal
XIN/2
STATE
CAL
CONV
Figure 1. Calibration Timing (Not to Scale)
t
buh
XIN
XIN/2
Conversion StandbyStandby
CONV
STATE
t
sac
t
hca
A0, A1
t
scn
t
con
DRDY
BP/UP t
bus
t
cpw
Figure 2. Conversion Timing (Not to Scale)
CS5505/6/7/8
8 DS59F4
CS5505/6/7/8
8DS59F5
5V SWITCHING CHARACTERISTICS (TA = TMIN to TMAX; VA+, VD+ = 5V ± 10%;
VA- = -5V ± 10%; Input Levels: Logic 0 = 0V, Logic 1 = V D+; CL = 50 pF.) (Note 2)
Parameter Symbol Min Typ Max Units
SSC M ode (M/S LP = V D+)
Access Time: CS Low to SDATA out (DRDY = low)
DRDY falling to MSB (CS = low) tcsd1
tdfd -
--
2/fclk 2/fclk
3/fclk ns
ns
SDATA Delay Time: SCLK falling to next SDATA bit tdd1 - 80 250 ns
SCLK Delay Time SDATA MSB bi t to SCLK rising t cd1 -1/f
clk -ns
Serial Clock (Out) Pulse W idth High
Pulse Width Low tph1
tpl1 -
-1/fclk
1/fclk -
-ns
ns
Output Float Delay: CS high to output Hi-Z (Note 16)
SCLK rising to SDATA Hi-Z tfd1
tfd2 -
--
1/fclk 2/fclk
-ns
ns
SEC Mode (M/SLP = DGND)
Serial Clock (In) fsclk 0-2.5MHz
Serial Clock (In) Pulse W idth High
Pulse Width Low tph2
tpl2 200
200 -
--
-ns
ns
Access Time: CS Low to data valid (Note 17) tcsd2 - 60 200 ns
Maximum Delay time: (Note 18)
SCLK falling to new SDATA bit tdd2 - 150 310 ns
Output Float Delay: CS high to output Hi-Z (Note 16)
SCLK falling to SDATA Hi-Z tfd3
tfd4 -
-60
160 150
300 ns
ns
Notes: 16. If CS is returned high before al l data bits are output, the SDATA and SCLK outputs will complete the
current data bit and then go to high impedance.
17. If CS is activated asynchronously to DRDY, CS will not be recognized if it occurs when DRDY is high
for 2 clock cycles. The propagation delay time may be as great as 2 fclk cycles plus 200 ns. To
guarantee proper clocki ng of SDATA when usi ng asynchronous CS , SCLK(i) should not be taken high
sooner than 2 f clk + 200 ns after CS goes low.
18. SDATA transi tions on the falling edge of SCLK. Note that a ris ing SCLK must occur to enable the
serial port s hifting mechanism before falling edges can be recognized.
CS5505/6/7/8
DS59F4 9
CS5505/6/7/8
DS59F5 9
3.3V SWITCHING CHARACTERISTICS (TA = TMIN to TMAX VA + = 5V ± 10%; VD+ = 3.3V ±
5%; VA - = -5V ± 10%; Input Levels: Logic 0 = 0V, Logic 1 = V D+; CL = 50 pF.) (Note 2)
Parameter Symbol Min Typ Max Units
SSC M ode (M/S LP = V D+)
Access Time: CS Low to SDATA out (DRDY = low)
DRDY falling to MSB (CS = low) tcsd1
tdfd -
--
2/fclk 2/fclk
3/fclk ns
ns
SDATA Delay Time: SCLK falling to next SDATA bit tdd1 - 265 400 ns
SCLK Delay Time SDATA MSB bi t to SCLK rising t cd1 -1/f
clk -ns
Serial Clock (Out) Pulse W idth High
Pulse Width Low tph1
tpl1 -
-1/fclk
1/fclk -
-ns
ns
Output Float Delay: CS high to output Hi-Z (Note 16)
SCLK rising to SDATA Hi-Z tfd1
tfd2 -
--
1/fclk 2/fclk
-ns
ns
SEC Mode (M/SLP = DGND)
Serial Clock (In) fsclk 0 - 1.25 MHz
Serial Clock (In) Pulse W idth High
Pulse Width Low tph2
tpl2 200
200 -
--
-ns
ns
Access Time: CS Low to data valid (Note 17) tcsd2 - 100 200 ns
Maximum Delay time: (Note 18)
SCLK falling to new SDATA bit tdd2 - 400 600 ns
Output Float Delay: CS high to output Hi-Z (Note 16)
SCLK falling to SDATA Hi-Z tfd3
tfd4 -
-70
320 150
500 ns
ns
CS5505/6/7/8
10 DS59F4
CS5505/6/7/8
10 DS59F5
XIN
XIN/2
CONV
STATE
t
cd1
t
dd1
MSB MSB-1
pl1
t
ph1
t
fd2
t
LSB+1 LSB
Conversion2
STATE (CONV held high)
SDATA(o)
SCLK(o)
Conversion1
CS
DRDY
StandbyStandby Conversion Conversion
Hi-Z
Hi-Z
Hi-Z
Hi-Z
t
csd1
Figure 3. Timing Relationships; SSC Mode (Not to Scale)
DRDY
CS
SCLK(i)
MSB-1MSB MSB-2
SDATA(o) Hi-Z
MSB-1MSB LSB+2 LSB+1 LSB
DRDY
CS
SCLK(i)
SDATA(o) Hi-Z
t
fd3
t
csd2
t
dd2
t
ph2
t
pl2
t
fd4
t
dd2
t
csd2
Figure 4. Timing Relationships ; SEC Mode (Not to Scale)
CS5505/6/7/8
DS59F4 11
CS5505/6/7/8
DS59F5 11
RECOMMENDED OPERATING CONDITIONS (DGND = 0V) (Note 19)
Parameter Symbol Min Typ Max Units
DC Power Supplies : Positiv e Digital
(VA+)-(VA-)
Positiv e Analog
Negative Analog
VD+
Vdiff
VA+
VA-
3.15
4.5
4.5
0
5.0
10
5.0
-5.0
5.5
11
11
-5.5
V
V
V
V
Analog Reference Voltage (Note 20) (VREF+)-(VREF-) 1.0 2.5 3.6 V
Analog Input Voltage: (Note 21)
Unipolar
Bipolar VAIN
VAIN 0
-((VREF+)-(VREF-)) -
-(VREF+)-(VREF-)
+((VREF+)-(VREF-)) V
V
Notes: 19. All voltages with respect to ground.
20. The CS5505/6/7/8 can be operated with a reference vol tage as low as 100 mV; but with a
corresponding reduction in noise-free resolution. The common mode voltage of the voltage reference
may be any value as long as +VREF and -VREF remain inside the supply values of VA+ and VA-.
21. The CS5505/6/7/8 can accept input voltages up to the analog supplies (VA+ and VA-). In unipolar
mode the CS5505/6/7/8 will output all 1’s if the dc input magnitude ((AIN+)-(AIN-)) exceeds
((VREF+)-(VREF-)) and will output all 0’s if the input becomes more negative than 0 Volts.
In bipolar mode the CS5505/6/7/8 will output all 1’s if the dc i nput magnitude ((AIN+)-(AIN-)) exceeds
((VREF+)-(VREF-)) and wi ll output all 0’s if the input becomes more negative in magnitude than
-((VREF+)-(VREF-)).
ABSOLUTE MAXIMUM RATINGS*
Parameter Symbol Min Typ Max Units
DC Power Supplies : Di gital Ground (Note 22)
Positiv e Digital (Note 23)
Positiv e Analog
Negative Analog
(VA+)-(VA-)
(VA+)-(VD+)
DGND
VD+
VA+
VA-
Vdiff1
Vdiff2
-0.3
-0.3
-0.3
+0.3
-0.3
-0.3
-
-
-
-
-
-
(VD+)-0.3
6.0 or VA+
12.0
-6.0
12.0
12.0
V
V
V
V
V
V
Input Current, Any Pin Except Supplies (Notes 24, 25) Iin --±
10 mA
Analog Input Voltage AIN and VREF pins VINA (VA-)-0.3 - (VA+)+0.3 V
Digital Input Voltage VIND -0.3 - (VD+)+0.3 V
Ambient Operating Temperature T A-55 - 125 °C
Storage Temperature T stg -65 - 150 °C
Notes: 22. No pin should go more positive than (VA +)+0.3V.
23. VD+ must always be less than (VA+)+0.3 V,and can never exceed 6.0V.
24. Applies to all pins includi ng continuous overvoltage condi tions at the analog input (AIN) pin.
25. Transient currents of up to 100mA will not cause SCR latch-up. Max imum input current for a power
supply pin is ± 50 mA.
* WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
CS5505/6/7/8
12 DS59F4
CS5505/6/7/8
12 DS59F5
GENERAL DESCRIPTION
The CS5505/6/7/8 are very low power mono-
lithic CMOS A/D converters designed
specifically for measurement of dc signals. The
CS5505/7 are 16-bit converters (a four channel
and a single channel version). The CS5506/8 are
20-bit converters (a four channel and a single
channel version). Each of the devices includes a
delta-sigma charge-balance converter, a voltage
reference, a calibration microcontroller with
SRAM, a digital filter and a serial interface. The
CS5505 and CS5506 include a four channel
pseudo-differential (all four channels have the
same reference measurement node) multiplexer.
The CS5505/6/7/8 include an on-chip reference
but can also utilize an off-chip reference for pre-
cision applications. The CS5505/6/7/8 can be
used to measure either unipolar or bipolar sig-
nals. The devices use self-calibration to insure
excellent offset and gain accuracy.
The CS5505/6/7/8 are optimized to operate from
a 32.768 kHz crystal but can be driven by an
external clock whose frequency is between
30 kHz and 163 kHz. When the digital filter is
operated with a 32.768 kHz clock, the filter has
zeros precisely at 50 and 60 Hz line frequencies
and multiples thereof.
The CS5505/6/7/8 use a "start convert" com-
mand to latch the input channel selection and to
start a convolution cycle on the digital filter.
Once the filter cycle is completed, the output
port is updated. When operated with a
32.768 kHz clock the ADC converts and updates
its output port at 20 samples/sec. The throughput
rate per channel is the output update rate divided
by the number of channels being multi-
plexed. The output port includes a serial
interface with two modes of operation.
The CS5505/6/7/8 can operate from dual polar-
ity power supplies (+5 and -5), from a single +5
volt supply, or with +10 volts on the analog and
+5 on the digital. They can also operate with
dual polarity (+5 and -5), or from a single +5
volt supply on the analog and + 3.3 on the digi-
tal.
THEORY OF OPERATION FOR THE
CS5505/6/7/8
The front page of this data sheet illustrates the
block diagram of the CS5505/6.
Basic Converter Operation
The CS5505/6/7/8 A/D converters have four op-
erating states. These are start-up, calibration,
conversion and sleep. When power is first ap-
plied, the device enters the start-up state. The
first step is a power-on reset delay of about
10 ms which resets all of the logic in the device.
To proceed with start-up, the oscillator must
then begin oscillating. After the power-on reset
the device enters the wake-up period for 1800
clock cycles after clock is present. This allows
the delta-sigma modulator and other circuitry
(which are operating with very low currents) to
reach a stable bias condition prior to entering
into either the calibration or conversion states.
During the 1800 cycle wake-up period, the de-
vice can accept an input command. Execution of
this command will not occur until the complete
wake-up period elapses. If no command is given,
the device enters the standby mode.
Calibration
After the initial application of power, the
CS5505/6/7/8 must enter the calibration state
prior to performing accurate conversions. During
calibration, the chip executes a two-step process.
The device first performs an offset calibration
and then follows this with a gain calibration.
The two calibration steps determine the zero ref-
erence point and the full scale reference point of
the converter’s transfer function. From these
points it calibrates the zero point and a gain
CS5505/6/7/8
DS59F4 13
CS5505/6/7/8
DS59F5 13
slope to be used to properly scale the output
digital codes when doing conversions.
The calibration state is entered whenever the
CAL and CONV pins are high at the same time.
The state of the CAL and CONV pins at power-
on and when coming out of sleep are recognized
as commands, but will not be executed until the
end of the 1800 clock cycle wake-up period.
Note that any time CONV transitions from low
to high, the multiplexer inputs A0 and A1 are
latched internal to the CS5505 and CS5506 de-
vices. These latched inputs select the analog
input channel which will be used once conver-
sion commences.
If CAL and CONV become active (high) during
the 1800 clock cycle wake-up time, the con-
verter will wait until the wake-up period elapses
before executing the calibration. If the wake-up
time has elapsed, the converter will be in the
standby mode waiting for instruction and will
enter the calibration cycle immediately. The cali-
bration lasts for 3246 clock cycles. Calibration
coefficients are then retained in the SRAM
(static RAM) for use during conversion.
At the end of the calibration cycle, the on-chip
microcontroller checks the logic state of the
CONV signal. If the CONV input is low the de-
vice will enter the standby mode where it waits
for further instruction. If the CONV signal is
high at the end of the calibration cycle, the con-
verter will enter the conversion state and
perform a conversion on the input channel which
was selected when CONV transitioned from low
to high. The CAL signal can be returned low
any time after calibration is initiated. CONV can
also be returned low, but it should never be
taken low and then taken back high until the
calibration period has ended and the converter is
in the standby state. If CONV is taken low and
then high again with CAL high while the con-
verter is calibrating, the device will interrupt the
current calibration cycle and start a new one. If
CAL is taken low and CONV is taken low and
then high during calibration, the calibration cy-
cle will continue as the conversion command is
disregarded. The states of A0, A1 and BP/UP
are not important during calibrations.
If an "end of calibration" signal is desired, pulse
the CAL signal high while leaving the CONV
signal high continuously. Once the calibration is
completed, a conversion will be performed. At
the end of the conversion, DRDY will fall to in-
dicate the first valid conversion after the
calibration has been completed.
See Understanding Converter Calibration for de-
tails on how the converter calibrates its transfer
function.
Conversion
The conversion state can be entered at the end of
the calibration cycle, or whenever the converter
is idle in the standby mode. If CONV is taken
high to initiate a calibration cycle ( CAL also
high), and remains high until the calibration cy-
cle is completed (CAL is taken low after CONV
transitions high), the converter will begin a con-
version upon completion of the calibration
period. The device will perform a conversion on
the input channel selected by the A0 and A1 in-
puts when CONV transitioned high. Table 1
indicates the multiplexer channel selection truth
table for A0 and A1.
The A0 and A1 inputs are latched internal to the
4-channel devices (CS5505/6) when CONV
rises. A0 and A1 have internal pull-down cir-
cuits which default the multiplexer to channel
A1 A0 Channel address ed
00 AIN1
01 AIN2
10 AIN3
11 AIN4
Table 1. Multiplexer T ruth Table
CS5505/6/7/8
14 DS59F4
CS5505/6/7/8
14 DS59F5
AIN1. The BP/UP pin is not a latched input. The
BP/UP pin controls how the output word from
the digital filter is processed. In bipolar mode
the output word computed by the digital filter is
offset by 8000H in the 16-bit CS5505/7 or
80000H in 20-bit CS5506/8 (see Understanding
Converter Calibration). BP/UP can be changed
after a conversion is started as long as it is stable
for 82 clock cycles of the conversion period
prior to DRDY falling. If one wishes to intermix
measurement of bipolar and unipolar signals on
various input channels, it is best to switch the
BP/UP pin immediately after DRDY falls and
leave BP/UP stable until DRDY falls again. If
the converter is beginning a conversion starting
from the standby state, BP/UP can be changed at
the same time as A0 and A1.
The digital filter in the CS5505/6/7/8 has a Fi-
nite Impulse Response and is designed to settle
to full accuracy in one conversion time. There-
fore, the multiplexer can be changed at the
conversion rate.
If CONV is left high, the CS5505/6/7/8 will per-
form continuous conversions on one channel.
The conversion time will be 1622 clock cycles.
If conversion is initiated from the standby state,
there may be up to two XIN clock cycles of un-
certainty as to when conversion actually begins.
This is because the internal logic operates at one
half the external clock rate and the exact phase
of the internal clock may be 180° out of phase
relative to the XIN clock. When a new conver-
sion is initiated from the standby state, it will
take up to two XIN clock cycles to begin. Actual
conversion will use 1624 clock cycles before
DRDY goes low to indicate that the serial port
has been updated. See the Serial Interface Logic
section of the data sheet for information on read-
ing data from the serial port.
In the event the A/D conversion command
(CONV going positive) is issued during the con-
version state, the current conversion will be
terminated and a new conversion will be initi-
ated.
Voltage Reference
The CS5505/6/7/8 uses a differential voltage ref-
erence input. The positive input is VREF+ and
the negative input is VREF-. The voltage be-
tween VREF+ and VREF- can range from 1 volt
minimum to 3.6 volts maximum. The gain slope
will track changes in the reference without re-
calibration, accommodating ratiometric
applications.
The CS5505/6/7/8 include an on-chip voltage
reference which outputs 2.5 volts on the VRE-
FOUT pin. This voltage is referenced to the
VA+ pin and will track changes relative to VA+.
The VREFOUT output requires a 0.1 µF capaci-
tor connected between VREFOUT and VA+ for
stability. When using the internal reference, the
VREFOUT signal should be connected to the
VREF- input and the VREF+ pin should be con-
nected to the VA+ supply. The internal voltage
reference is capable of sourcing 3 µA maximum
and sinking 50 µA maximum. If a more precise
reference voltage is required, an external voltage
reference should be used. If an external voltage
reference is used, the VREFOUT pin of the in-
ternal reference should be connected directly to
VA-. It cannot be left open unless the 0.1 µF ca-
pacitor is in place for stability.
CS5505/6/7/8
VA+
VREF+
VREF-
VREFOUT
VA-
2.5V
-VA
+VA
LT1019,
REF43
or
LM368
Figure 5. External Reference Connections
CS5505/6/7/8
DS59F4 15
CS5505/6/7/8
DS59F5 15
External reference voltages can range from 1.0
volt minimum to 3.6 volts maximum. The com-
mon mode voltage range of the external
reference can allow the reference to lie at any
voltage between the VA+ and VA- supply rails.
Figures 5 and 6 illustrate how the CS5505/6/7/8
converters are connected for external and for in-
ternal voltage reference use, respectively.
Analog Input Range
The analog input range is set by the magnitude
of the voltage between the VREF+ and VREF-
pins. In unipolar mode the input range will equal
the magnitude of the voltage reference. In bipo-
lar mode the input voltage range will equate to
plus and minus the magnitude of the voltage ref-
erence. While the voltage reference can be as
great as 3.6 volts, its common mode voltage can
be any value as long as the reference inputs
VREF+ and VREF- stay within the supply volt-
ages for the A/D. The differential input voltage
can also have any common mode value as long
as the maximum signal magnitude stays within
the supply voltages.
The A/D converter is intended to measure dc or
low frequency inputs. It is designed to yield ac-
curate conversions even with noise exceeding
the input voltage range as long as the spectral
components of this noise will be filtered out by
the digital filter. For example, with a 3.0 volt
reference in unipolar mode, the converter will
accurately convert an input dc signal up to
3.0 volts with up to 15% overrange for 60 Hz
noise. A 3.0 volt dc signal could have a 60 Hz
component which is 0.5 volts above the maxi-
mum input of 3.0 (3.5 volts peak; 3.0 volts dc
plus 0.5 volts peak noise) and still accurately
convert the input signal (XIN = 32.768 kHz).
This assumes that the signal plus noise ampli-
tude stays within the supply voltages.
The CS5505/6/7/8 converters output data in bi-
nary format when converting unipolar signals
and in offset binary format when converting bi-
polar signals. Table 2 outlines the output coding
for the 16-bit CS5505/7 and the 20-bit CS5506/8
in both unipolar and bipolar measurement
modes.
CS5505 and CS5507 (16 Bit) CS5506 and CS5508 (20 Bit )
Unipolar Input
Voltage Output
Codes Bipolar Input
Voltage Unipolar Input
Voltage Output
Codes Bipolar Input
Voltage
>(VREF - 1.5 LSB) FFFF >(VREF - 1.5 LSB) >(VRE F - 1.5 LSB) FFFFF >(VREF - 1.5 LSB)
VREF - 1.5 LSB FFFF
FFFE VREF - 1.5 LSB VREF - 1.5 LSB FFFFF
FFFFE V REF - 1.5 LSB
VREF/2 - 0.5 LSB 8000
7FFF -0.5 LSB VREF/2 - 0.5 LSB 80000
7FFFF -0.5 LSB
+0.5 LSB 0001
0000 -VREF + 0.5 LSB +0.5 LSB 00001
00000 -VREF + 0.5 LSB
<(+0.5 LSB) 0000 <(-VREF + 0.5 LSB) <(+0.5 LSB) 00000 <(-VREF + 0.5 LSB)
Note: VREF = (VREF+) - (VREF-); Table excludes common mode volt age on the signal and reference inputs.
Table 2. Output Co ding
-VA
+VA
0.1
µ
F
CS5505/6/7/8
VA+
VREF+
VREF-
VREFOUT
VA-
Figure 6. Internal Reference Connections
CS5505/6/7/8
16 DS59F4
CS5505/6/7/8
16 DS59F5
Understanding Converter Calibration
Calibration can be performed at any time. A
calibration sequence will minimize offset errors
and set the gain slope scale factor. The delta-
sigma modulator in the converter is a differential
modulator. To calibrate out offset error, the
converter internally connects the modulator dif-
ferential inputs to an internal VREF- voltage and
measures the 1’s density output from the modu-
lator. It stores the digital code representation for
this 1’s density in SRAM and remembers this
code as being the zero scale point for the A/D
conversion. The converter then connects the
negative modulator differential input to the
VREF- input and the positive modulator differ-
ential input to the VREF+ voltage. The 1’s
density output from the modulator is then re-
corded. The converter uses the digital
representation of this 1’s density along with the
digital code for the zero scale point and calcu-
lates a gain scale factor. The gain scale factor is
stored in SRAM and used for calculating the
proper output codes during conversions.
The states of A0, A1 and BP/UP are ignored
during calibration but should remain stable
throughout the calibration period to minimize
noise.
When conversions are performed in unipolar
mode or in bipolar mode, the converter uses the
same calibration factors to compute the digital
output code. The only difference is that in bipo-
lar mode the on-chip microcontroller offsets the
computed output word by a code value of
8000H (16-bit) or 80000H (20-bit) and multi-
plies the LSB size by two. This means that the
bipolar measurement range is not calibrated from
full scale positive to full scale negative. Instead
it is calibrated from the bipolar zero scale point
to full scale positive. The slope factor is then
extended below bipolar zero to accommodate the
negative input signals. The converter can be
used to convert both unipolar and bipolar signals
by changing the BP/UP pin. Recalibration is not
required when switching between unipolar and
bipolar modes.
Converter Performance
The CS5505/6/7/8 A/D converters have excellent
linearity performance. Calibration minimizes the
errors in offset and gain. The CS5505/7 devices
have no missing code performance to 16-bits.
The CS5506/8 devices have no missing code
performance to 20-bits. Figure 7 illustrates the
DNL of the 16-bit CS5505. The converters
achieve Common Mode Rejection (CMR) at dc
of 105 dB typical, and CMR at 50 and 60 Hz of
120 dB typical.
The CS5505/6/7/8 can experience some drift as
temperature changes. The CS5505/6/7/8 use
chopper-stabilized techniques to minimize drift.
Measurement errors due to offset or gain drift
can be eliminated at any time by recalibrating
the converter.
065,535
Codes
32,768
DNL (LSB)
+1
0
-1
+1/2
-1/2
Figure 7. CS5505 Differential Nonlinearity plot.
CS5505/6/7/8
DS59F4 17
CS5505/6/7/8
DS59F5 17
Analog Input Impedance Considerations
The analog input of the CS5505/6/7/8 can be
modeled as illustrated in Figure 8 (the model ig-
nores the multiplexer switch resistance).
Capacitors (15 pF each) are used to dynamically
sample each of the inputs (AIN+ and AIN-).
Every half XIN cycle the switch alternately con-
nects the capacitor to the output of the buffer
and then directly to the AIN pin. Whenever the
sample capacitor is switched from the output of
the buffer to the AIN pin, a small packet of
charge (a dynamic demand of current) is re-
quired from the input source to settle the voltage
of the sample capacitor to its final value. The
voltage on the output of the buffer may differ up
to 100 mV from the actual input voltage due to
the offset voltage of the buffer. Timing allows
one half of a XIN clock cycle for the voltage on
the sample capacitor to settle to its final value.
The equation which defines the settling time is:
Ve = Vmax e−t⁄RC
Where Ve is the final settled value, Vmax is the
maximum error voltage value of the input signal,
R is the value of the input source resistance, C is
the 15 pF sample capacitor plus the value of any
stray or additional capacitance at the input pin.
The value of t is equal to 1/(2XIN).
Vmax occurs the instant the sample capacitor is
switched from the buffer output to the AIN pin.
Prior to switching, AIN has an error estimated as
being less than or equal to Ve. Vmax is equal to
the prior error (Ve) plus the additional error
from the buffer offset. The estimate for Vmax is:
Vmax = Ve + 100mV 15pF
(15pF + CEXT )
Where CEXT is the combination of any external
or stray capacitance.
From the settling time equation, an equation for
the maximum acceptable source resistance is de-
rived.
Rsmax = −1
2XIN (15p F + CEXT ) ln
Ve
Ve + 15pF(100mv)
(15pF + CEXT )
This equation assumes that the offset voltage of
the buffer is 100 mV, which is the worst case.
The value of Ve is the maximum error voltage
which is acceptable.
For a maximum error voltage (Ve) of 10 µV in
the CS5505 (1/4LSB at 16-bits) and 600 nV in
the CS5506 (1/4LSB at 20-bits), the above equa-
tion indicates that when operating from a
32.768 kHz XIN, source resistances up to
110 kΩ in the CS5505 or 84 kΩ in the CS5506
are acceptable in the absence of external capaci-
tance (CEXT = 0). If higher input source
resistances are desired the master clock rate can
be reduced to yield a longer settling time.
The VREF+ and VREF- inputs have nearly the
same structure as the AIN+ and AIN- inputs.
Therefore, the discussion on analog input imped-
ance applies to the voltage reference inputs as
well.
+
-15 pF
V
os
< 100 mV
+
-
V
os
< 100 mV
Internal
Bias
Voltage
15 pF
AIN+
AIN-
CS5505/6/7/8
Figure 8. Ana log Input Model
CS5505/6/7/8
18 DS59F4
CS5505/6/7/8
18 DS59F5
Digital Filter Characteristics
The digital filter in the CS5505/6/7/8 is the com-
bination of a comb filter and a low pass filter.
The comb filter has zeros in its transfer function
which are optimally placed to reject line interfer-
ence frequencies (50 and 60 Hz and their
multiples) when the CS5505/6/7/8 is clocked at
32.768 kHz. Figures 9, 10 and 11 illustrate the
magnitude and phase characteristics of the filter.
Figure 9 illustrates the filter attenuation from dc
to 260 Hz. At exactly 50, 60, 100, and 120 Hz
the filter provides over 120 dB of rejection. Ta-
ble 3 indicates the filter attenuation for each of
the potential line interference frequencies when
the converter is operating with a 32.768 kHz
clock. The converter yields excellent attenuation
of these interference frequencies even if the fun-
damental line frequency should vary ±1% from
its specified frequency. The -3 dB corner fre-
quency of the filter when operating from a
32.768 kHz clock is 17 Hz. Figure 11 illustrates
that the phase characteristics of the filter are pre-
cisely linear phase.
0 5 10 15 20 25 30 35 40 45 50
Frequency (Hz)
-180
-135
-90
-45
0
45
90
135
180
Phase (Degrees)
XIN = 32.768 kHz
Figure 11. Filter Phase Plot to 50 Hz
0 5 10 15 20 25 30 35 40 45 50
Frequency (Hz)
-140
-120
-100
-80
-60
-40
-20
0
Attenuation (dB)
Flatness
dB
-0.010
-0.041
-0.093
-0.166
-0.259
-0.510
-0.667
-0.846
-1.047
-3.093
1
2
3
4
5
6
7
8
9
10
17
XIN = 32.768 kHz
Frequency
-0.374
Figure 10. Filter Magnitude Plot to 50 Hz
Frequency
(Hz) Notch
Depth
(dB)
Frequency
(Hz) Minimum
Attenuation
(dB)
50 125.6 50±1% 55.5
60 126.7 60±1% 58.4
100 145.7 100±1% 62.2
120 136.0 120±1% 68.4
150 118.4 150±1% 74.9
180 132.9 180±1% 87.9
200 102.5 200±1% 94.0
240 108.4 240±1% 104.4
Table 3. Filter Notch Attenuation (XIN = 32.768 kHz)
0
0
40
198.97 80
397.95 120
596.92 160
795.10 200
993.87 240
1193.85
Frequency (Hz)
-160
-140
-120
-100
-80
-60
-40
-20
0
Attenua tion (dB)
XIN = 32.768 kHz
X1
X2
X1 = 32.768kHz
X2 = 163. 0 0kH z
Figure 9. Filter Ma gnitude Plot to 260 Hz
CS5505/6/7/8
DS59F4 19
CS5505/6/7/8
DS59F5 19
If the CS5505/6/7/8 is operated at a clock rate
other than 32.768 kHz, the filter characteristics,
including the comb filter zeros, will scale with
the operating clock frequency. Therefore, opti-
mum rejection of line frequency interference will
occur with the CS5505/6/7/8 running at
32.768 kHz. The CS5505/6/7/8 can be used with
external clock rates from 30 kHz to 163 kHz.
Anti-Alias Considerations for Spectral
Measurement Applications
Input frequencies greater than one half the out-
put word rate (CONV = 1) may be aliased by
the converter. To prevent this, input signals
should be limited in frequency to no greater than
one half the output word rate of the converter
(when CONV =1). Frequencies close to the
modulator sample rate (XIN/2) and multiples
thereof may also be aliased. If the signal source
includes spectral components above one half the
output word rate (when CONV = 1) these com-
ponents should be removed by means of low-
pass filtering prior to the A/D input to prevent
aliasing. Spectral components greater than one
half the output word rate on the VREF inputs
(VREF+ and VREF-) may also be aliased. Fil-
tering of the reference voltage to remove these
spectral components from the reference voltage
is desirable.
Crystal Oscillator
The CS5505/6/7/8 is designed to be operated us-
ing a 32.768 kHz "tuning fork" type crystal. One
end of the crystal should be connected to the
XIN input. The other end should be attached to
XOUT. Short lead lengths should be used to
minimize stray capacitance. Figure 12 illustrates
the gate oscillator, and a simplified version of
the control logic used on the chip.
Over the industrial temperature range (-40 to
+85 °C) the on-chip gate oscillator will oscillate
Start
Conversion
D
Q
CLK
D
Q
CLK
Input
Mux
Decoder 4
3
2
1
T
QModulator
Sample
Clock
XTL =32. 76 8 kHz
A0
A1
CONV
CS5505/6
CAL
D
Q
CLK
D
Q
CLK
Start
Calibration
S
Q
S
Q
R
R
R
Channel A0 A1
1
1
0
0
1
0
1
0
10 M
Ω
22. 5 pF 15 pF
gm
~
~19 um h o
XOUT
XIN
Figure 12. Gate Oscillator and Control Logic
CS5505/6/7/8
20 DS59F4
CS5505/6/7/8
20 DS59F5
with other crystals in the range of 30 kHz to
53 kHz. Over the military temperature range (-
55 to +125 °C) the on-chip gate oscillator is
designed to work only with a 32.768 kHz crys-
tal. The chip will operate with external clock
frequencies from 30 kHz to 163 kHz.over all
temperature ranges. The 32.768 kHz crystal is
normally specified as a time-keeping crystal with
tight specifications for both initial frequency and
for drift over temperature. To maintain excellent
frequency stability, these crystals are specified
only over limited operating temperature ranges
(i.e. -10 to +60 °C) by the manufacturers. Appli-
cations of these crystals with the CS5505/6/7/8
do not require tight initial tolerance or low
tempco drift. Therefore, a lower cost crystal with
looser initial tolerance and tempco will generally
be adequate for use with the CS5505/6/7/8 con-
verters. Also check with the manufacturer about
wide temperature range application of their
standard crystals. Generally, even those crystals
specified for limited temperature range will op-
erate over much larger ranges if frequency
stability over temperature is not a requirement.
The frequency stability can be as bad as ±3000
ppm over the operating temperature range and
still be typically better than the line frequency
(50 or 60 Hz) stability over cycle to cycle during
the course of a day. There are crystals available
for operation over the military temperature range
(-55 to +125 °C). See the Appendix for suppliers
of 32.768 kHz crystals.
Serial Interface Logic
The digital filter in the CS5505/6/7/8 takes 1624
clock cycles to compute an output word once a
conversion begins. At the end of the conversion
cycle, the filter will attempt to update the serial
port. Two clock cycles prior to the update
DRDY will go high. When DRDY goes high
just prior to a port update it checks to see if the
port is either empty or unselected (CS = 1). If
the port is empty or unselected, the digital filter
will update the port with a new output word.
When new data is put into the port DRDY will
go low.
Data can be read from the serial port in either of
two modes. The M/SLP pin determines which
serial mode is selected. Serial port mode selec-
tion is as follows:
SSC (Synchronous Self-Clocking) mode;
M/SLP = VD+, or SEC (Synchronous External
Clocking) mode; M/SLP = DGND. Timing dia-
grams which illustrate the SSC and SEC timing
are in the tables section of this data sheet.
Synchronous Self-Clocking Mode
The serial port operates in the SSC mode when
the M/SLP pin is connected to the VD+ pin on
the part. In SSC mode the CS5505/6/7/8 fur-
nishes both the serial output data (SDATA) and
the serial clock (SCLK). When the serial port is
updated at the end of a conversion, DRDY falls.
If CS is low, the SDATA and SCLK pins will
come out of the high impedance state two XIN
clock cycles after DRDY falls. The MSB data
bit will be presented for two cycles of XIN
clock. The SCLK signal will rise in the middle
of the MSB data bit. When SCLK then returns
low the (MSB - 1) bit will appear. Subsequent
data bits will be output on each falling edge of
SCLK until the LSB data bit is output. After the
LSB data bit is output, the SCLK will fall at
which time both the SDATA and SCLK outputs
will return to the high impedance output state.
DRDY will return high at this time.
If CS is taken low after DRDY falls, the MSB
data bit will appear within two XIN clock cycles
after CS is taken low. CS need not be held low
for the entire data output. If CS is returned high
during a data bit the port will complete the out-
put of that bit and then go into the Hi-Z state.
The port can be reselected any time prior to the
completion of the next conversion (DRDY fall-
ing) to allow the remaining data bits to be
output.
CS5505/6/7/8
DS59F4 21
CS5505/6/7/8
DS59F5 21
Synchronous External-Clocking Mode
The serial port operates in the SEC mode when
the M/SLP pin is connected to the DGND pin.
SDATA is the output pin for the serial data.
When CS goes low after new data becomes
available (DRDY goes low), the SDATA pin
comes out of Hi-Z with the MSB data bit pre-
sent. SCLK is the input pin for the serial clock
in the SEC mode. If the MSB data bit is on the
SDATA pin, the first rising edge of SCLK en-
ables the shifting mechanism. This allows the
falling edges of SCLK to shift subsequent data
bits out of the port. Note that if the MSB data
bit is output and the SCLK signal is high, the
first falling edge of SCLK will be ignored be-
cause the shifting mechanism has not become
activated. After the first rising edge of SCLK,
each subsequent falling edge will shift out the
serial data. Once the LSB is present, the falling
edge of SCLK will cause the SDATA output to
go to Hi-Z and DRDY to return high. The serial
port register will be updated with a new data
word upon the completion of another conversion
if the serial port has been emptied, or if the CS
is inactive (high).
CS can be operated asynchronously to the
DRDY signal. The DRDY signal need not be
monitored as long as the CS signal is taken low
for at least two XIN clock cycles plus 200 ns
prior to SCLK being toggled. This ensures that
CS has gained control over the serial port.
Sleep Mode
The CS5505/6/7/8 devices offer two methods of
putting the device into a SLEEP condition to
conserve power. Calibration words will be re-
tained in SRAM during either sleep condition.
The M/SLP pin can be put into the SLEEP
threshold to lower the operating power used by
the device to about 1% of nominal. Alternately,
the clock into the XIN pin can be stopped. This
will lower the power consumed by the converter
to about 30% of nominal. In both cases, the
converter must go through a wake-up sequence
prior to conversions being initiated. This wake-
up sequence includes the 10 msec. (typ.)
power-on-reset delay, the start-up of the oscilla-
tor (unless an external clock is used), and the
1800 clock cycle wake-up delay after the clock
begins. When coming out of the sleep condi-
tion, the converter will latch the A0 and A1
inputs.
Figure 13 illustrates how to use a gate and resis-
tors to bias the M/SLP pin into the SLEEP
threshold region when using the converter in the
SSC mode. To use the SEC mode return resistor
R1 to DGND instead of the supply. When in
the SEC mode configuration the CS5505/6/7/8
will enter the SLEEP threshold when the logic
control input is a logic 1 (VD+). Note that large
resistors can be used to conserve power while in
sleep. The input leakage of the pin is typically
less than 1 µA even at 125 °C, although the
worst case specification tables indicate a leakage
of 10 µA maximum.
Power Supplies and Grounding
The analog and digital supply pins to the
CS5505/6/7/8 are brought out on separate pins to
minimize noise coupling between the analog and
digital sections of the chip. Note that there is no
M/SLP
CS5505/6/7/8
*
’1’ = SSC Mode
’0’ = SLEEP
R
1
Control
Input
R
2
VD+
*
Tie R to DGND for SEC mode; cont rol input
logic inverts.
1
0.01
µ
F
R = 499k, V + = 5V; R = 590k, V + = 3.3V
1 1
DD
499k
1%
1%
**
**
Figure 13. Sleep Threshold Control
CS5505/6/7/8
22 DS59F4
CS5505/6/7/8
22 DS59F5
analog ground pin. No analog ground pin is re-
quired because the inputs for measurement and
for the voltage reference are differential and re-
quire no ground. In the digital section of the
chip the supply current flows into the VD+ pin
and out of the DGND pin. As a CMOS device,
the CS5505/6/7/8 requires that the supply volt-
age on the VA+ pin always be more positive
than the voltage on any other pin of the device.
If this requirement is not met, the device can
latch-up or be damaged. In all circumstances the
VA+ voltage must remain more positive than the
VD+ or DGND pins; VD+ must remain more
positive than the DGND pin.
The following power supply options are possi-
ble:
VA+ = +5V to +10V, VA- = 0V, VD+ = +5V
VA+ = +5V, VA- = -5V, VD+ = +5V
VA+ = +5V, VA- = 0V to -5V, VD+ = +3.3V
The CS5505/6/7/8 cannot be operated with a
3.3V digital supply if VA+ is greater than
+5.5V.
CS5505/6
+5V
Analog
Supply VD+
10
Ω
VA+
M/SLP
SCLK
SDATA
CAL
VREF+
VREF-
DGND
VA-
DRDY
CS
A0
A1
BP/UP
AIN1+
AIN-
AIN2+
AIN3+
AIN4+
CONV
Note:
XIN
XOUT
To use the internal 2.5 volt reference see Figure 6.
*U nu s ed ana l og i npu t s
should be tied to AIN-
0.1
µ
F
0.1
µ
F
4
8
13
12
11
10
9
14
15
1
2
3
5
6
7
17
18
19
20
21
22
23
24
Analog*
Signal
Sources
Signal
Ground
32.768 kHz
Voltage
Reference
16
VREFOUT
+
-
Calibration
Control
Bipolar/
Unipolar
Input Select
Unused Logic
inputs must be
connected t o
VD+ or DGND.
Control
Logic
Serial
Data
Interface
Sleep Mode
Control
and
Outp ut Mod e
Select
Optional
Clock
Source
Figure 14. CS5 505/6 System Connection Diagram Using Ex ternal Reference, Single Supply
CS5505/6/7/8
DS59F4 23
CS5505/6/7/8
DS59F5 23
Figure 14 illustrates the System Connection Dia-
gram for the CS5505/6 using a single +5V
supply. Note that all supply pins are bypassed
with 0.1 µF capacitors and that the VD+ digital
supply is derived from the VA+ supply.
Figure 15 illustrates the CS5505/6 using dual
supplies of +5 and -5V.
Figure 16 illustrates the CS5505/6 using dual
supplies of +10V analog and +5V digital.
When using separate supplies for VA+ and
VD+, VA+ must be established first. VD+
should never become more positive than VA+
under any operating condition. Remember to in-
vestigate transient power-up conditions, when
one power supply may have a faster rise time.
CS5505/6
+5V
Analog
Supply VD+
10
Ω
VA+
M/SLP
SCLK
SDATA
CAL
VREF+
VREF-
DGND
VA-
DRDY
CS
A0
A1
BP/UP
AIN1+
AIN-
AIN2+
AIN3+
AIN4+
CONV
Note:
XIN
XOUT
To use the internal 2.5 volt reference see Figure 6.
*Unused analog inputs
should be tied to AIN-
0.1
µ
F
0.1
µ
F
4
8
13
12
11
10
9
14
15
1
2
3
5
6
7
17
18
19
20
21
22
23
24
Analog*
Signal
Sources
Signal
Ground
32.768 kHz
Voltage
Reference
16
VREFOUT
+
-
Calibration
Control
Bipolar/
Unipolar
In put Selec t
Unused Lo gi c
inputs must be
connected to
VD+ or DGND.
Control
Logic
Serial
Data
Interface
Sleep Mode
Control
and
Output Mode
Select
Optional
Clock
Source
0.1
µ
F
-5V
Analog
Supply
Figure 15. CS5505/6 System Connection Diagram Using External Reference, Dual Supplies
CS5505/6/7/8
24 DS59F4
CS5505/6/7/8
24 DS59F5
CS5505/6
+10V
Analog
Supply VD+VA+
M/SLP
SCLK
SDATA
CAL
VREF+
VREF-
DGND
VA-
DRDY
CS
A0
A1
BP/UP
AIN1+
AIN-
AIN2+
AIN3+
AIN4+
CONV
Note:
XIN
XOUT
(1 ) To use the i nter na l 2. 5 volt refer ence see Figure 6.
(2) VD+ must never exceed VA+. Examine power-up conditions.
*Unused analog inputs
should be tied to AIN-
0.1
µ
F
0.1
µ
F
4
8
13
12
11
10
9
14
15
1
2
3
5
6
7
17
18
19
20
21
22
23
24
Analog*
Signal
Sources
Signal
Ground
32.768 kHz
Voltage
Reference
16
VREFOUT
+
-
Calibration
Control
Bipolar/
Unipolar
Input Se lect
Unused Logic
inputs must be
connected to
VD+ or DGND.
Control
Logic
Serial
Data
Interface
Sleep Mode
Control
and
Output Mode
Select
Optional
Clock
Source
(1)
+5V
Analog
Supply
(2)
Figure 16. CS5505/6 System Connection Diagram Using External Reference,
Dual Supply, +10 V Analog, +5V Dig ital
Schematic & Layout Review Service
Confirm Optimum
Schematic & Layout
Before Building Your Board.
Confirm Optimum
Schematic & Layout
Before Building Your Board.
For Our Free Review Service
Call Applications Engineering.
For Our Free Review Service
Call Applications Engineering.
Call:(512)445-7222
CS5505/6/7/8
DS59F4 25
CS5505/6/7/8
DS59F5 25
PIN CONNECTIONS*
1
2
3
4
5
24
14
13
19
18
17
16
15
6
7
8
9
10
12
11
20
21
22
23
CS5505/6
1
2
3
4
5
20
15
14
13
12
11
6
7
8
9
10
16
17
18
19
CS5507/8
MULTIPLEXER SELECTION INPUT A0 A1 MULTIPLEXER SELECTION INPUT
CHIP SELECT CS DRDY DATA READY
CONVERT CONV SDATA SERIAL DATA OUTPUT
CALIBRATE CAL SCLK SERIAL CLOCK INPUT/OUTPUT
CRYSTAL IN XIN VD+ POSITIVE DIGITAL P OWER
CRYSTAL OUT XOUT DGND DIGITAL GROUND
SERIAL MODE/ SLEEP M/SLP VA- NEGATIVE A NALOG POWER
BIPOLAR/UNIPOLAR BP/UP VA+ PO SITIVE ANALO G POWER
DIFFEREN TIAL ANALOG INPUT AIN1+ VREFOUT VOLTAGE REFERENCE OUTPUT
DIFFEREN TIAL ANALOG INPUT AIN2+ VREF- VOLTAGE REFERENCE INPUT
DIFFERENTIAL ANALOG RETURN AIN- VREF+ VOLTAGE REFERENCE INPUT
DIFFEREN TIAL ANALOG INPUT AIN3+ AIN4+ DIFFERENTIAL ANALOG INPUT
CHIP SELECT CS DRDY DATA READY
CONVERT CONV SDATA SERIAL DATA OUTPUT
CALIBRATE CAL SCLK SERIAL CLOCK INPUT/OUTPUT
CRYSTAL IN XIN VD+ POSITIVE DIG ITAL POWER
CRYSTAL OUT XOUT DGND DIGITAL GROUND
SERIAL MODE/ SLEEP M/SLP VA- NEGATIVE A NALOG POWE R
BIPOLAR/UNIPOLAR BP/UP VA+ POSITIVE ANALOG PO WER
DIFFERENTIAL ANALOG INPUT AIN+ VREFOUT VOLTAGE REFERENCE OUTPUT
NO CONNECTION NC VREF- VOLTAGE REFERENCE INPUT
DIFFERENTIAL ANALOG INPUT AIN- VREF+ VOLTAGE REFERENCE INPUT
*Pinout appl ies to both DIP and SO IC
CS5505/6/7/8
26 DS59F4
CS5505/6/7/8
26 DS59F5
PIN DESCRIPTIONS
Pin numbers for four channel devices are in parentheses.
Clock Generator
XIN; XOUT - Crystal In; Crystal Out, Pins 4 (5) and 5 (6).
A gate inside the chip is connected to these pins and can be used with a crystal to provide the
master clock for the device. Alternatively, an external (CMOS compatible) clock can be
supplied into the XIN pin to provide the master clock for the device. Loss of clock will put the
device into a lower powered state (approximately 70% power reduction).
Serial Output I/O
M/SLP - Serial Interface Mode Select/ Sleep, Pin 6 (7).
Dual function pin which selects the operating mode of the serial port and provides a very low
power sleep function. When M/SLP is tied to the VD+ pin the serial port will operate in the
Synchronous Self-Clocking (SSC) mode. When M/SLP is tied to the DGND pin the serial port
will operate in the Synchronous External Clocking (SEC) mode. When the M/SLP pin is tied
half way between VD+ and DGND the chip will enter into a very low powered sleep mode in
which its calibration data will be maintained.
CS - Chip Select, Pin 1 (2).
This input allows an external device to access the serial port.
DRDY - Data Ready, Pin 20 (23)
Data Ready goes low at the end of a digital filter convolution cycle to indicate that a new
output word has been placed into the serial port. DRDY will return high after all data bits are
shifted out of the serial port or two master clock cycles before new data becomes available if
the CS pin is inactive (high).
SDATA - Serial Data Output, Pin 19 (22).
SDATA is the output pin of the serial output port. Data from this pin will be output at a rate
determined by SCLK and in a format determined by the M/SLP pin. Data is output MSB first
and advances to the next data bit on the falling edges of SCLK. SDATA will be in a high
impedance state when not transmitting data.
SCLK - Serial Clock Input/Output, Pin 18 (21).
A clock signal on this pin determines the output rate of the data from the SDATA pin. The
M/SLP pin determines whether SCLK is an input or and output. When used as an input, it must
not be allowed to float.
CS5505/6/7/8
DS59F4 27
CS5505/6/7/8
DS59F5 27
Control Input Pins
CAL - Calibrate, Pin 3 (4).
When taken high the same time that the CONV pin is taken high the converter will perform a
self-calibration which includes calibration of the offset and gain scale factors in the converter.
CONV - Convert, Pin 2 (3).
The CONV pin initiates a calibration cycle if it is taken from low to high while the CAL pin is
high, or it initiates a conversion if it is taken from low to high with the CAL pin low. CONV
latches the multiplexer selection when it transitions from low to high on the multiple channel
devices. If CONV is held high (CAL low) the converter will do continuous conversions.
A0, A1 - Multiplexer Selection Inputs, Pins (1, 24).
A0 and A1 select the input channel for conversion on the multi-channel input devices. A0 and
A1 are latched when CONV transitions from low to high. These two inputs have pull-down
resistors internal to the chip.
BP/UP - Bipolar/Unipolar, Pin 7 (8).
The BP/UP pin selects the conversion mode of the converter. When high the converter will
convert bipolar input signals; when low it will convert unipolar input signals.
Measurement and Reference Inputs
AIN+, AIN-, (AIN1+, AIN2+, AIN3+, AIN4+, AIN-) - Differential Analog Inputs, Pins 8, 10 (9,
10, 12, 13, 11).
AIN- in the CS5505/6 is a common measurement node for AIN1+, AIN2+, AIN3+ and AIN4+.
VREF+, VREF- - Differential Voltage Reference Inputs, Pins 11, 12 (14, 15).
A differential voltage reference on these pins operates as the voltage reference for the
converter. The voltage between these pins can be any voltage between 1.0 and 3.6 volts.
Voltage Reference
VREFOUT - Voltage Reference Output, Pin 13 (16).
The on-chip voltage reference is output from this pin. The voltage reference has a nominal
magnitude of 2.5 volts and is referenced to the VA+ pin on the converter.
Power Supply Connections
VA+ - Positive Analog Power, Pin 14 (17).
Positive analog supply voltage. Nominally +5 volts.
VA- - Negative Analog Power, Pin 15 (18).
Negative analog supply voltage. Nominally -5 volts when using dual polarity supplies; or 0
volts (tied to system analog ground) when using single supply operation.
CS5505/6/7/8
28 DS59F4
CS5505/6/7/8
28 DS59F5
VD+ - Positive Digital Power, Pin 17 (20).
Positive digital supply voltage. Nominally +5 volts or 3.3 volts.
DGND - Digital Ground, Pin 16 (19).
Digital Ground.
Other
NC - No Connection, Pin 9.
Pin should be left floating.
SPECIFICATION DEFINITIONS
Linearity Error
The deviation of a code from a straight line which connects the two endpoints of the A/D
Converter transfer function. One endpoint is located 1/2 LSB below the first code transition
and the other endpoint is located 1/2 LSB beyond the code transition to all ones. Units in
percent of full-scale.
Differential Nonlinearity
The deviation of a code’s width from the ideal width. Units in LSBs.
Full Scale Error
The deviation of the last code transition from the ideal [{(VREF+) - (VREF-)} - 3⁄2 LSB].
Units are in LSBs.
Unipolar Offset
The deviation of the first code transition from the ideal (1⁄2 LSB above the voltage on the AIN-
pin.) when in unipolar mode (BP/UP low). Units are in LSBs.
Bipolar Offset
The deviation of the mid-scale transition (011...111 to 100...000) from the ideal (1⁄2 LSB below
the voltage on the AIN- pin.) when in bipolar mode (BP/UP high). Units are in LSBs
CS5505/6/7/8
DS59F4 29
CS5505/6/7/8
DS59F5 29
Ordering Guide
Model # of Resolution Linearity Temperature Package Type
Number Channels Error Range (°C)
CS5505-AP 4 16-B its 0.0030% -40 to +85 24-pin 0.3" P lastic DIP
CS5505-AS 4 16-B its 0.0030% -40 to +85 24-pin 0.3" S OIC
CS5506-BP 4 20-B its 0.0015% -40 to +85 24-pin 0.3" P lastic DIP
CS5506-BS 4 20-B its 0.0015% -40 to +85 24-pin 0.3" S OIC
CS5507-AP 1 16-B its 0.0030% -40 to +85 20-pin 0.3" P lastic DIP
CS5507-AS 1 16-B its 0.0030% -40 to +85 20-pin 0.3" S OIC
CS5507-SD 1 16-Bits 0.0030% -55 to + 125 20-pin 0.3" CerDIP
CS5508-BP 1 20-B its 0.0015% -40 to +85 20-pin 0.3" P lastic DIP
CS5508-BS 1 20-B its 0.0015% -40 to +85 20-pin 0.3" S OIC
CS5508-SD 1 20-Bits 0.0030% -55 to + 125 20-pin 0.3" CerDIP
CS5505/6/7/8
30 DS59F4
CS5505/6/7/8
30 DS59F5
ORDERING INFORMATION
ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION
* MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020.
Model Package Resolution Liearity
Error Channels Temperature
CS5505-AP 24-pin Plastic DIP
16 Bits 0.0030%
4
-40 to +85 °C
CS5505-AS 24-pin SOIC
CS5505-ASZ (lead free)
CS5506-BP 24-pin Plastic DIP
20 Bits 0.0015%CS5506-BS 24-pin SOIC
CS5506-BSZ (lead free)
CS5507-AP 20-pin Plastic DIP
16 Bits 0.0030%
1
CS5507-AS 20-pin SOIC
CS5507-ASZ (lead free)
CS5508-BP 20-pin Plastic DIP
20 Bits 0.0015%CS5508-BS 20-pin SOIC
CS5508-BSZ (lead free)
Model Number Peak Reflow Temp MSL Rating* Max Floor Life
CS5505-AP 260 °C 1 No Limit
CS5505-AS 240 °C 2 365 Days
CS5505-A SZ (lea d fre e ) 260 °C 3 7 Days
CS5506-BP 260 °C 1 No Limit
CS5506-BS 240 °C 2 365 Days
CS5506-B SZ (lea d fre e ) 260 °C 3 7 Days
CS5507-AP 260 °C 1 No Limit
CS5507-AS 240 °C 2 365 Days
CS5507-A SZ (lea d fre e ) 260 °C 3 7 Days
CS5508-BP 260 °C 1 No Limit
CS5508-BS 240 °C 2 365 Days
CS5508-B SZ (lea d fre e ) 260 °C 3 7 Days
APPENDIX
The following companies provide 32.768 kHz crystals in many package varieties and temperature
ranges.
Fox Electronics
5570 Enterprise Parkway
Fort Meyers, FL 33905
(813) 693-0099
Micro Crystal Division / SMH
702 West Algonquin Road
Arlington Heights, IL 60005
(708) 806-1485
SaRonix
4010 Transport Street
Palo Alto, California 94303
(415) 856-6900
Statek
512 North Main
Orange, California 92668
(714) 639-7810
IQD Ltd.
North Street
Crewkerne
Somerset TA18 7AK
England
01460 77155
Mr. Pierre Hersberger
Microcrystal/DIV. ETA S.A.
Schild-Rust-Strasse 17
Grenchen CH-2540
Switzerland
065 53 05 57
Taiwan X’tal Corp.
5F. No. 16, Sec 2, Chung Yang S. RD.
Reitou, Taipei, Taiwan R. O. C.
Tel: 02-894-1202
Fax: 02-895-6207
Interquip Limited
24/F Million Fortune Industrial Centre
34-36 Chai Wan Kok Street, Tsuen Wan N T
Tel: 4135515
Fax: 4137053
S& T Enterprises, Ltd.
Rm 404 Blk B
Sea View Estate
North Point, Hong Kong
Tel: 5784921
Fax: 8073126
Mr. Darren Mcleod
Hy-Q International Pty. Ltd.
12 Rosella Road,
FRANKSON, 3199
Victoria, Australia
Tel: 61-3-783 9611
Fax: 61-3-783 9703
CS5505/6/7/8
DS59F4 31
CS5505/6/7/8
DS59F5 31
REVISION HISTORY
Revision Date Changes
F4 MAR 1995 First Final Release
F5 AUG 2005 Updated device ordering info. Updated legal notice. Added MSL data..
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find the one nearest to you go to www.cirrus.com
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Cirrus L ogic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be tr ademarks
or service marks of their respective owners.
• Notes •
CS5505/6/7/8
32 DS59F5
- NOTES -
33
Copyright
©
Cirrus Logic, Inc. 19 98
(All Rights Rese rved)
Cirrus Logic, Inc.
Crystal Semiconductor Products Division
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.crystal.com
CDB5505/6/7/8
Evaluation Board for CS5505/6/7/8 Series of ADC’s
Features
l
Operation with on-board 32.768 kHz crystal
or off-board clock source
l
Jumper selectable:
-SSC mode; SEC mode; Sleep
l
DIP Switch Selectable:
-BP/UP mode; A0, & A1 channel selection
l
On-board precision voltage reference
l
Access to all digital control pins
l
On-board patch area
Description
The CDB5505/5506/5507/5508 is a circuit board de-
signed to provide quick evaluation of the CS5505/6/7/8
seri es of A/D c onverter s. The boar d can be c onfigured to
evaluate the CS5505/6/7/8 in either SSC (Synchronous
Self-Clocking) or SEC (Synchronous External-Clocking)
serial port mode.
The board allows access to al l of the digital inter face pins
of the CS5505/ 6/7/8 chip.
ORDERING INFORMATION
CDB5505 Evaluat ion Board
CDB5506 Evaluat ion Board
CDB5507 Evaluat ion Board
CDB5508 Evaluat ion Board
I
AIN4+
AIN3+
AIN2+
AIN1+
AIN-
+5V
GND
-5V
CS5505/6/7/8
CLKI
N
VREF
H
E
A
D
E
R
B
U
F
F
E
R
S
MAR ‘95
DS59DB2
Copyright © Cirrus Logic, Inc. 2005
(All Rights Reserved)
http://www.cirrus.com
CDB5505/6/7/8
Evaluation Board for CS5505/6/7/8 Series of ADCs
AUG ‘05
DS59DB3
Introduction
The CDB5505/6/7/8 evaluation board provides a
quick means of testing the CS5505/6/7/8 series
A/D converters. The CS5505/6/7/8 converters
require a minimal amount of external circuitry.
The evaluation board comes configured with the
A/D converter chip operating from a 32.768 kHz
crystal and with an off-chip precision 2.5 volt
reference. The board provides access to all of
the digital interface pins of the CS5505/6/7/8
chip.
The board is configured for operation from +5
and -5 volt power supplies, but can be operated
from a single +5 volt supply if the -5V binding
post is shorted to the GND binding post.
Evaluation Board Overview
The board provides a complete means of making
the CS5505/6/7/8 A/D converter chip function.
The user must provide a means of taking the
output data from the board in serial format and
using it in his system.
Figure 1 illustrates the schematic for the board.
The board comes configured for the A/D con-
verter chip to operate from the 32.768 kHz
watch crystal. A BNC connector for an external
clock is provided on the board. To connect the
external BNC source to the converter chip, a cir-
cuit trace must be cut. Then a jumper must be
inserted in the proper holes to connect the XIN
pin of the converter to the input line from the
BNC. The BNC input is terminated with a 50Ω
resistor. Remove this resistor if driving from a
logic gate. See the schematic in Figure 1.
The board comes with the A/D converter
VREF+ and VREF- pins hard-wired to the
2.5 volt bandgap voltage reference IC on the
board. The VREF+ and VREF- pins can be con-
nected to either the on chip reference or an
off-board reference if the connections (2A and
2B) to the bandgap IC are cut.
Note that the pin-out of the CS5505/6/7/8 series
chips allows the 20-pin single channel devices to
be plugged into the 24-pin, four channel foot-
print. See Figure 2 which illustrates the footprint
compatibility.
Prior to powering up the board, select the serial
port operating mode with the appropriate jumper
on the M/SLP header. The device can be oper-
ated in either the SSC (Synchronous
Self-Clocking) or the SEC (Synchronous Exter-
nal Clocking) mode. See the device data sheet
for an explanation of these modes.
All of the control pins of the CS5505/6/7/8 are
available at the J1 header connector. Buffer ICs
U2 and U3 are used to buffer the converter for
interface to off-board circuits. The buffers are
used on the evaluation board only because the
exact loading and off-board circuitry is un-
known. Most applications will not require the
buffer ICs for proper operation.
To put the board in operation, select either bipo-
lar or unipolar mode with DIP switch S2. Then
press the CAL pushbutton after the board is
powered up. This initiates calibration of the con-
verter which is required before measurements
can be taken.
To select an input channel on the four channel
devices, use DIP switch S2 to select the inputs
A1 A0 Channel addressed
00 AIN1
01 AIN2
10 AIN3
11 AIN4
Table 1. Multiplexer T ruth Table
CS5505/6/7/8
34 DS59DB2
CDB5505/6/7/8
34 DS59DB3
Figure 1. ADC Connections
0.01
µ
F
C6
0.1
µ
F
1A
1B
2A
2B
3A
C8
0.1
µ
F
6
5
4
2
LT1019
-2.5 V
+5
C9
0.1
µ
F
External
VREF
+
_
R8
25k
3B
VA+
VA- DGND
VD+
XIN XOUT
M/SLP
BP/UP
SCLK
SDATA
CAL
CONV
CS
A0
A1
DRDY
VREFOUT
VREF+
VREF-
16
14
15
11
7
8
21
22
23
24
1
2
3
4
10
R9
C10
0.1
µ
F
17 20
VD+
+5
C7
0.1
µ
F
C11
0.01
µ
F
CAL
R11
100k
18 19
0.1
µ
F
Y1
C1
-5
32.768
kHz
R2
R3
50
CLKIN 56
TP15
200
AIN4+
13
R7
AIN4+ TP3
402
AIN3+
12
R6
AIN3+
TP4
402
AIN2+
10
R5
AIN2+
TP5
402
AIN1+
9
R4
AIN1+
TP6
402
AIN-
R13
R12 100k
AIN-
C12
0.01
µ
F
C13
0.01
µ
F
C14
0.01
µ
F
C15
402
100k
100k
100k
100k
R28
R29
R30
R31
R27
R26 C19
C20
1K
1K 10nF
10nF
U1
CS5505
CS5506
CS5507
OR
CS5508
SLEEP
SSC
SEC
VD+ U3C
R14
100k
R15
100k
R21
47k
VD+
U3D
7
810 9
TP14
13
11 12
VD+
R16 100k
TP13 U3B
U3A
56
4
3
1
2
VD+
C18
0.1
µ
F
14 SCLKI
SCLKO
SDATA
DRDY
A1
A0
CS
CONV
CAL
U2F
8
15
14
U2E 12
11
U2D
10 9
U2C
67
U2B
45
U2A 3
R20
R19 R18
47k
R17
47k VD+
VD+
C17
0.1
µ
F
2
1
TP12
TP11
TP7
TP8
TP9
TP10
R1
100k
SCLK
DRDY
SDATA
+5 C16
10
µ
F
R22
10
+
J2
J1
R10 20k
U2 74HC4050
U3 74HC125
VD+
100k
VD+
100k
R25
100k
R24
100k
R23
100k
S2 A1
A0
CONV
BP/UP
BP/UP
+5
+5
+5V
-5V
GND
C5
C4
0.1
µ
F
+5
- 5
+
C2
10
µ
F
C3
+
10
µ
F
0.1
µ
F
D2
D1
6.8V
6.8V
AGND
DGND
CS5505/6/7/8
DS59DB2 35
CDB5505/6/7/8
DS59DB3 35
for A0 and A1 (see Table 1). Once A0 and A1
are selected, the CONV switch (S2-3) must be
switched on (closed) and then open to cause the
CONV signal to transition low to high. This
latches the A0 and A1 channel selection into the
converter. With CONV high (S2-3 open) the
converter will convert continuously.
Figures 3 and 4 illustrate the evaluation board
layout while Figure 5 illustrates the component
placement (silkscreen) of the evaluation board.
1
2/1
3/2
4/3
5/4
6/5
7/6
8/7
9/8
10/9
11/10
12 13
11/14
24
20/23
19/22
18/21
17/20
16/19
15/18
14/17
13/16
12/15
CS5505/6
CS5507/8
Figure 2. CS5505/6 and CS5507/8 Pin Layouts
A0 A1
CS DRDY
CONV SDATA
CAL SCLK
XIN VD+
XOUT DGND
M/SLP VA-
BU/UP VA+
AIN1+ VREFOUT
AIN2+/NC VREF-
AIN- VREF+
AIN3+ AIN4+
CS5505/6/7/8
36 DS59DB2
CDB5505/6/7/8
36 DS59DB3
Figure 3. Top Ground Plane Layer (NOT TO SCALE)
CS5505/6/7/8
DS59DB2 37
CDB5505/6/7/8
DS59DB3 37
Figure 4. Bottom Trace Layer (NOT TO SCALE)
CS5505/6/7/8
38 DS59DB2
CDB5505/6/7/8
38 DS59DB3
Figure 5. Silk Screen Layer (NOT TO SCALE)
CS5505/6/7/8
DS59DB2 39
CDB5505/6/7/8
DS59DB3 39
CDB5505/6/7/8
40 DS59DB3
REVISION HISTORY
Revision Date Changes
DB2 MAR 1995 First Release
F5 AUG 2005 Updated legal notice.
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find the one nearest to you go to www.cirrus.com
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to change without notice and is pr ovided “ AS IS” wit hout warr anty of any kind (express or impli ed). Cust omers are advised t o ob tain the latest version of relevant
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AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH
THESE USES.
Cirrus L ogic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be tr ademarks
or service marks of their respective owners.
