Intel386™ EX Embedded
Microprocessor
Dat ash e et
Pr oduct Features
This datashe et a pplies to devices marked EXTB and EXTC. If you require information about
devices marked EXSA or EXTA, refe r to a pre vious re vision of this datasheet, order number
272420-004.
■Sta tic Intel386™ CPU Core
—Low Power Consumption
—Operat ing P ower Supply
EXTB: 2.7 V to 3.6 V
EXTC: 4.5 V to 5.5 V
—Operat ing F requenc y
20 MHz EXTB at 2.7 V to 3.6 V
25 MHz EXTB at 3.0 V to 3.6 V;
25/33 MHz EXTC at 4.5 V to 5.5 V
■Transp a r en t Pow er -m an a ge ment S y ste m
Architecture
—Intel System Management Mode
Architecture Extension for Truly
Compatible Systems
—Power Management Transparent to
Operating Systems and Application
Programs
—Programmable Power-management
Modes
■Powerdown Mode
—Clock Stopping at Any T im e
—Only 10–20 µA Typical CPU Sink
Current
■Full 32-bit Internal A rchitecture
—8-, 16-, 32-bit Data Types
—8 General Pur pose 32-bit Register s
■Runs Int el386 Architect ure Software in a
Cost-effective 16-bi t Hardware
Environment
—Runs Same Applicati ons and Operating
Syste ms as the Int el386 SX and I nte l386
DX Processors
—Object Code Com patible with 8086,
80186, 80286, and Intel386 Proces sors
■High-performance 16-bit Dat a Bus
—Two-clock Bus Cycles
—Addres s Pipelining Al lows Use of
Slower, Inexpensive Mem ories
■Extended Te mper ature Range
■Integrated Memory Management Unit
—Virtual Memory Support
—Optional On-chip Paging
—4 Levels of Hardwa re-enforced
Protection
—MMU Fully Compa tible with MMUs of
the 80286 and Int el386 DX Processors
■Virtual 8086 Mode Allows Execut ion of
8086 S oftware in a Prot ected and Paged
System
■Large U n ifo rm Address Space
—64 Megabyte Phys ical
—64 Terabyte Virtual
—4 Gigabyte Maximum Segment Size
■On-chip Debugging Support Inc luding
Br eakpoint Registers
■Comp lete System Development Supp ort
■High S peed CHMOS Technology
■Two Package Types
—132-pin Plastic Quad Flatpack
—144-pin Thin Quad Flat pack
■Integrated Peripheral Functions
—Clock and Power Management Unit
—Chip-select Unit
—Interrupt Control Unit
—Timer/Counter Unit
—Watchdog Timer Unit
—Asynchronous Serial I/O Unit
—Syn chronous Se rial I/O Unit
—Pa r allel I/O Unit
—DMA and Bus Arbiter Unit
—Refresh Control Unit
—JTAG-compliant Test-logic Unit
Order Num be r : 27 24 20 -007
October 1998
Datasheet
Information in this document is provided in connection with Intel products. No license, expres s or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provid ed in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liabil ity
whatsoever, and Intel disclaims any express or implied warranty, r e lating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property righ t. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserv es these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel386™ EX Microprocessor may contain design defects or errors known as errata which may cause the product to deviate from published
specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-
548-4725 or by visiting Intel's website at http://www.intel.com.
Copyright © Intel Corporation, 1998
*Third-party brands and names are the property of their respec tive owners.
Datasheet 3
Intel386™ E X Em bed ded Microp ro cesso r
Contents
1.0 Introduction..................................................................................................................7
2.0 Pin Assignment...........................................................................................................8
3.0 Pin Description..........................................................................................................12
4.0 Functional Description...........................................................................................19
4.1 Clock Generation and Power Management Unit....................... ................... .......19
4.2 Chip-select Unit...................................................................................................19
4.3 Interrupt Control Unit...........................................................................................19
4.4 Timer/Counter Unit................................................... ...........................................20
4.5 Watchdog Ti me r Unit............................................................ ...............................20
4.6 Asynchronous Serial I/O Unit................... ....... ..... ....... ....... ....... ..... ....... ....... ..... ..20
4.7 Synchronous Se rial I/O Unit........................................................ ........................21
4.8 Parallel I/O Unit...................................................................................................21
4.9 DMA and Bus Arbiter Unit...................................................................................21
4.10 Refre sh Control Unit.. ........ ........... ........ ....... ........... ........ ....... ........... ........ ....... ....22
4.11 JTAG Test-logic Unit...........................................................................................22
5.0 Desi gn Considerat ion s..........................................................................................23
5.1 Instruction Set.....................................................................................................23
5.2 Component and Revision Identifiers ...................................................................24
5.3 Package Therm al Spec ifications. ....................................................... .................24
6.0 Electrical Specifications........................................................................................27
6.1 Maximum Ratings................................................................................................27
6.2 DC Specifications................................................................................................28
6.3 AC Specificati o n s.... ....... ....... ............ ....... ....... ............ ....... ....... ............ ....... .......30
7.0 Bus Cycle Waveforms............................................................................................47
Figures 1Int el386™ EX Embedded Processor Block Diagram.. ..... ....... .. ....... .......... ....... .. ..7
2 Intel386™ EX Embedded Processor 132-Pin PQFP Pin Assignment ..................8
3 Intel386™ EX Embedded Processor 144-Pin TQFP Pin Assignment.......... .......10
4 Maxim um Case Temperature v s. Frequency for Typical Power Values
(132-lead PQFP, Vcc = 5.5 V) .............................................................................25
5 Maxim um Case Temperature v s. Frequency for Typical Power Values
(144-lead TQFP, Vcc = 5.5 V nominal)................................................................25
6 Maxim um Case Temperature v s. Frequency for Typical Power Values
(132-lead PQFP, Vcc = 3.6 V) .............................................................................26
7 Maxim um Case Temperature v s. Frequency for Typical Power Values
(144-lead TQFP, Vcc = 3.6 V)..............................................................................26
8 Drive Levels and Measureme nt Points for AC Specifications (EXTC)................30
9 Drive Levels and Measureme nt Points for AC Specifications (EXTB) ................31
10 AC Test Loads....................... ................... .............. ................... ....... ...................42
Intel386™ E X Embe dde d Micro pro cesso r
4 Datasheet
11 CL K2 Waveform......... ............ ....... ....... ............ ....... ....... ............ ....... ....... ...........42
12 AC Timing Wavef orms — Input Setup and Hold Timing.....................................43
13 AC Timing Waveforms — Output Valid Delay Timing.........................................44
14 AC Timing Wavef orms — Output Valid Delay Timing for
External Late READY#........................................................................................44
15 AC Timing Waveforms — Output Float Delay and HLDA Valid Delay Timing....45
16 AC Timing Wavef orms — RES ET Setup and Hold Timi ng and Internal Phase..45
17 AC Timing Wavef orms — Rela tive Signal Timing...............................................46
18 AC Timing Waveforms — SSIO Timing..............................................................46
19 AC Timing Waveforms — Timer/Count er Timing................................................46
20 Ba sic Internal and External Bus Cycles..............................................................47
21 Nonpipelined Address Read Cycles...................................................... ..............48
22 Pipelined Address Cycle.....................................................................................49
23 16-bit Cycles to 8-bit Devices (using BS8#)........................................................50
24 Ba sic External Bus Cycles..................................................................................51
25 Nonpipelined Address Write Cycles..... ....... ....... ....... ..... ....... ....... ..... ....... ....... ....52
26 Ha lt Cycle.......... ....... ............ ....... ....... ............ ....... ....... ............ ....... ....... ............ .53
27 Ba sic Refresh Cycle............................................................................................54
28 Refresh Cycle During HOLD/HLDA ....................................................................55
29 LOCK# Signal During Address Pipelining...........................................................56
30 Interrupt Acknowled ge Cycles.............................................................................56
Tables 1 132-Pin PQFP Pin Assignment.. ................................. ...................................... ....9
2 144-Pin TQFP Pin Assignment .................................................... ................... ....11
3 Pin Type and Output State Nomenc lature ..........................................................12
4 Intel38 6™ EX M icroprocessor Pin Descriptions .................................................13
5 Microprocessor Clocks Per Instruction................................................................23
6 Thermal Resistances (0°C/W) θJA, θJC................................................................24
7 5 V Intel3 86 EXTC Processor M aximum Ratings ...............................................27
8 3 V Intel3 86 EXTB Processor Maximum Ratings ................................................27
9 5-Volt DC Characte ristics....................................................................................28
10 3-Volt DC Characteristics....................................................................................29
11 5-Volt AC Ch aracteristics....................................................................................32
12 3-Volt AC Ch aracteristics....................................................................................37
Datasheet 5
Intel386™ E X Em bed ded Microp ro cesso r
Revision History
This datas heet applies to devices marked EXTB and EXTC. If you require informa tion about
devices marked EXSA or EXTA, refer to a previous revision of this data sheet, order number
272420-004.
Revision Date Description
007 10/ 98 Th e do cu men t wa s up date d t o t he lar g er pa ge siz e. All kn ow n dev ic e er r ata fo r
the datasheet have been inc orporated into this new revision.
006 5/96 Corrections added.
005 12/95 This dat asheet applied to the new EXTB and EXTC devices.
004 9/94 This datasheet applied to devices marked EXSA or EXTA.
Intel386™ E X Em bed ded Microp ro cesso r
Datasheet 7
1.0 Introduction
The Intel386™ EXTB e mbedded processor operates at 20 or 25 MHz at 3 Volts nominal. The
Intel386 EXTC embedded processor operates at 25 or 33 MHz at 5 Volts. In this datasheet,
“Intel386 EX processor” refers to both the Intel386 EX TB and EXTC processors.
The I ntel386 EX em bedded p roces sor is a hi ghly integ rated, 32-b it, fu lly static proc essor opti mized
for embedded control applicati ons. With a 16-bit external dat a bus , a 26-bit exte rnal address bus,
and Intel’s System Management Mode (SMM), the I ntel386 EX microprocessor brings the vast
soft ware li brar y of Inte l3 86 arch ite cture to em bedded syste ms. It provi des the pe rformanc e ben efits
of 32-bit programming with the cost savings a ssociated with 16-bit h ardwa re s ystems.
Figure 1. Intel386™ EX Embedded Processor Block Diagram
A2849-02
JTAG Unit
Clock and Power
Management Unit
DRAM Refresh
Control Unit
Watchdog Timer Unit
Bus Monitor
Asynchronous Serial I/O
2 channels
(16450 compatible)
Synchronous Serial I/O
1 channel, full duplex
Timer/counter Unit
3 channels
(82C54 compatible)
I/O Ports
Data
Address
Bus Interface
Unit
Intel386™ CX Core
Core Enhancements
- A20 Gate
- CPU Reset
- SMM
Chip-select
Unit
Interrupt Control Unit
DMA Controller
2 channels
(8237A compatible)
and Bus Arbiter Unit
INTR
Address
Data
Processor Core
Intel386™ E X Embe dde d Micro pro cesso r
8Datasheet
2.0 Pin Assignment
Figu re 2. In tel386™ E X Embed ded Processor 132-Pin PQFP Pin Assign ment
Note:
NC = No Connection
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
FLT#
DSR1#/STXCLK
VSS
INT7/TMRGATE1
INT6/TMRCLK1
INT5/TMRGATE0
INT4/TMRCLK0
BUSY#/TMRGATE2
ERROR#/TMROUT2
NMI
PEREQ/TMRCLK2
VCC
P3.7/COMCLK
P3.6/PWRDOWN
P3.5/INT3
P3.4/INT2
VSS
P3.3/INT1
VCC
P3.2/INT0
RTS1#/SSIOTX
RI1#/SSIORX
DTR1#/SRXCLK
TCK
P3.1/TMROUT1/INT8
P3.0/TMROUT0/INT9
SMI#
A25
VCC
A24
VSS
A23
A22
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
UCS#
CS6#/REFRESH#
VSS
LBA#
D0
D1
D2
D3
VCC
D4
D5
D6
D7
D8
VCC
D9
VSS
D10
D11
D12
D13
D14
D15
TDO
TDI
TMS
M/IO#
VCC
D/C#
W/R#
VSS
READY#
BS8#
P2.7/CTS0#
P2.6/TXD0
VSS
P2.5/RXD0
DACK0#/CS5#
VCC
P2.4/CS4#
P2.3/CS3#
P2.2/CS2#
P2.1/CS1#
P2.0/CS0#
VCC
SMIACT#
TRST#
DRQ1/RXD1
DRQ0/DCD1#
VSS
CLK2
WDTOUT
EOP#/CTS1#
DACK1#/TXD1
P1.7/HLDA
RESET
VCC
P1.6/HOLD
P1.5/LOCK#
P1.4/RI0#
P1.3/DSR0#
P1.2/DTR0#
CLKOUT
P1.1/RTS0#
P1.0/DCD0#
VSS
RD#
WR#
VSS
BLE#
VCC
BHE#
ADS#
NA#
A1
A2
A3
A4
VSS
VCC
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16/CAS0
VCC
A17/CAS1
A18/CAS2
A19
VSS
A20
A21
TOP VIEW
A2212-02
Intel386™ E X Em bed ded Microp ro cesso r
Datasheet 9
Table 1. 132-Pin PQFP Pin Assign ment
Pin Symbol Pin Symbol Pin Symbol Pin Symbol
1 UCS# 34 RD# 67 A22 100 VSS
2 CS6#/REFRESH# 35 WR# 68 A23 101 P1.0/DCD0#
3V
SS 36 VSS 69 VSS 102 P1.1/RTS0#
4 LBA# 37 BLE# 70 A24 103 CLKOUT
5D0 38V
CC 71 VCC 104 P1.2/DTR0#
6 D1 39BHE# 72A25 105P1.3/DSR0#
7 D2 40ADS# 73SMI# 106P1.4/RI0#
8 D3 41 NA# 74 P3.0/TMROUT0/INT9 107 P1.5/LOCK#
9V
CC 42 A1 75 P3.1/TMROUT1/INT8 108 P1.6/HOLD
10 D4 43 A2 76 TCK 109 VCC
11 D5 44 A3 77 DTR1#/SRXCLK 110 RESET
12 D6 45 A4 78 RI1#/SSIORX 111 P1.7/HLDA
13 D7 46 VSS 79 RTS1#/SSIOTX 112 DACK1#/TXD1
14 D8 47 VCC 80 P3.2/INT0 113 EOP#/CTS1#
15 Vcc 48 A5 81 VCC 114 WDTOUT
16 D9 49 A6 82 P3.3/INT1 115 CLK2
17 Vss 50 A7 83 VSS 116 VSS
18 D10 51 A8 84 P3.4/INT2 117 DRQ0/DCD1#
19 D11 52 A9 85 P3.5/INT3 118 DRQ1/RXD1
20 D12 53 A10 86 P3.6/PWRDOWN 119 TRST#
21 D13 54 A11 87 P3.7/COMCLK 120 SMIACT#
22 D14 55 A12 88 VCC 121 VCC
23 D15 56 A13 89 PEREQ/TMRCLK2 122 P2.0/CS0#
24 TDO 57 A14 90 NMI 123 P2.1/CS1#
25 TDI 58 A15 91 ERROR#/TMROUT2 124 P2.2/CS2#
26 TMS 59 A16/CAS0 92 BUSY#/TMRGATE2 125 P2.3/CS3#
27 M/IO# 60 VCC 93 INT4/TMRCLK0 126 P2.4/CS4#
28 VCC 61 A17/CAS1 94 INT5/TMRGATE0 127 VCC
29 D/C# 62 A18/CAS2 95 INT6/TMRCLK1 128 DACK0#/CS5#
30 W/R# 63 A19 96 INT7/TMRGATE1 129 P2.5/RXD0
31 VSS 64 VSS 97 VSS 130 VSS
32 READY# 65 A20 98 DSR1#/STXCLK 131 P2.6/TXD0
33 BS8# 66 A21 99 FLT# 132 P2.7/CTS0#
Intel386™ E X Embe dde d Micro pro cesso r
10 Datasheet
Figu re 3. In tel386™ E X Embed ded Processor 144-Pin TQFP Pin Assignment
VSS
FLT#
DSR1#/STXCLK
VSS
INT7/TMRGATE1
INT6/TMRCLK1
INT5/TMRGATE0
INT4/TMRCLK0
BUSY#/TMRGATE2
ERROR#/TMROUT2
NMI
VSS
PEREQ/TMRCLK2
VCC
P3.7/COMCLK
P3.6/PWRDOWN
P3.5/INT3
P3.4/INT2
VSS
P3.3/INT1
VCC
P3.2/INT0
RTS1#/SSIOTX
RI1#/SSIORX
DTR1#/SRXCLK
VSS
TCK
P3.1/TMROUT1/INT8
P3.0/TMROUT0/INT9
SMI#
A25
VCC
A24
VSS
A23
A22
RD#
WR#
VSS
BLE#
VCC
BHE#
ADS#
NA#
A1
A2
VSS
A3
A4
VSS
VCC
A5
A6
A7
A8
A9
A10
A11
A12
VSS
A13
A14
A15
A16/CAS0
VCC
A17/CAS1
A18/CAS2
A19
VSS
A20
A21
VSS
VSS
P2.7/CTS0#
P2.6/TXD0
VSS
P2.5/RXD0
DACK0#/CS5#
VCC
P2.4/CS4#
P2.3/CS3#
P2.2/CS2#
P2.1/CS1#
P2.0/CS0#
VSS
VCC
SMIACT#
TRST#
DRQ1/RXD1
DRQ0/DCD1#
VSS
CLK2
WDTOUT
EOP#/CTS1#
DACK1#/TXD1
P1.7/HLDA
VSS
RESET
VCC
P1.6/HOLD
P1.5/LOCK#
P1.4/RI0#
P1.3/DSR0#
P1.2/DTR0#
CLKOUT
P1.1/RTS0#
P1.0/DCD0#
VSS
UCS#
CS6#/REFRESH#
VSS
LBA#
D0
D1
D2
D3
VCC
D4
VSS
D5
D6
D7
D8
VCC
D9
VSS
D10
D11
D12
D13
D14
VSS
D15
TDO
TDI
TMS
M/IO#
VCC
D/C#
W/R#
VSS
READY#
BS8#
VSS
TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
A2213-03
Intel386™ E X Em bed ded Microp ro cesso r
Datasheet 11
Table 2. 144-Pin TQFP Pin Assignment
Pin Symbol Pin Symbol Pin Symbol Pin Symbol
1 UCS# 37 RD# 73 A22 109 VSS
2 CS6#/REFRESH# 38 WR# 74 A23 110 P1.0/DCD0#
3V
SS 39 VSS 75 VSS 111 P1.1/RTS0#
4 LBA# 40 BLE# 76 A24 112 CLKOUT
5D0 41V
CC 77 VCC 113 P1.2/DTR0#
6 D1 42 BHE# 78 A25 114 P1.3/DSR0#
7 D2 43 ADS# 79 SMI# 115 P1.4/RI0#
8 D3 44 NA# 80 P3.0/TMROUT0/INT9 116 P1.5/LOCK#
9V
CC 45 A1 81 P3.1/TMROUT1/INT8 117 P1.6/HOLD
10 D4 46 A2 82 TCK 118 VCC
11 VSS 47 VSS 83 VSS 119 RESET
12 D5 48 A3 84 DTR1#/SRXCLK 120 VSS
13 D6 49 A4 85 RI1#/SSIORX 121 P1.7/HLDA
14 D7 50 VSS 86 RTS1#/SSIOTX 122 DACK1#/TXD1
15 D8 51 VCC 87 P3.2/INT0 123 EOP#/CTS1#
16 VCC 52 A5 88 VCC 124 WDTOUT
17 D9 53 A6 89 P3.3/INT1 125 CLK2
18 VSS 54 A7 90 VSS 126 VSS
19 D10 55 A8 91 P3.4/INT2 127 DRQ0/DCD1#
20 D11 56 A9 92 P3.5/INT3 128 DRQ1/RXD1
21 D12 57 A10 93 P3.6/PWRDOWN 129 TRST#
22 D13 58 A11 94 P3.7/COMCLK 130 SMIACT#
23 D14 59 A12 95 VCC 131 VCC
24 VSS 60 VSS 96 PEREQ/TMRCLK2 132 VSS
25 D15 61 A13 97 VSS 133 P2.0/CS0#
26 TDO 62 A14 98 NMI 134 P2.1/CS1#
27 TDI 63 A15 99 ERROR#/TMROUT2 135 P2.2/CS2#
28 TMS 64 A16/CAS0 100 BUSY#/TMRGATE2 136 P2.3/CS3#
29 M/IO# 65 VCC 101 INT4/TMRCLK0 137 P2.4/CS4#
30 VCC 66 A17/CAS1 102 INT5/TMRGATE0 138 VCC
31 D/C# 67 A18/CAS2 103 INT6/TMRCLK1 139 DACK0#/CS5#
32 W/R# 68 A19 104 INT7/TMRGATE1 140 P2.5/RXD0
33 VSS 69 VSS 105 VSS 141 VSS
34 READY# 70 A20 106 DSR1#/STXCLK 142 P2.6/TXD0
35 BS8# 71 A21 107 FLT# 143 P2.7/CTS0#
36 VSS 72 VSS 108 VSS 144 VSS
Intel386™ E X Embe dde d Micro pro cesso r
12 Datasheet
3.0 Pin Description
Table 4 lists the Intel386 EX embedded pr ocessor pin descriptions. Table 3 defines the
abbreviations used in the Type and Output S tates columns of Table 4.
Table 3. Pin Type and O utput State Nomencl ature
Symbol Description
Pin T ype
#
I
O
I/O
I/OD
ST
P
G
The named sign al is active low.
Standard TTL input signal.
Standard CMOS output signal.
Input and output signal.
Input and open-drain output signal.
Schmitt-triggered input signal.
Power pin.
Ground pin.
Ou tput Sta te
H(1)
H(0)
H(Z)
H(Q)
H(X)
Output driv en to VCC during Bus Hold
Output driv en to VSS during Bus Hold
Out put floats during Bus Hold
Out put remains active during Bus Hold
Output retains current state during Bus Hold
R(WH)
R(WL)
R(1)
R(0)
R(Z)
R(Q)
R(X)
Output Weakly Held at VCC during Reset
Output Weakly Held at VSS during Reset
Output driv en to VCC during Rese t
Output driv en to VSS durin g Reset
Output floats during Reset
Out put remains active during Reset
Output retains current state during Reset
I(1)†
I(0)
I(Z)
I(Q)
I(X)
Output driv en to VCC during Idle Mode
Output driv en to VSS during Idle Mode
Output floats during Idle Mode
Out put remains active during Idle Mode
Output retains current state during Idle Mode
P(1)
P(0)
P(Z)
P(Q)
P(X)
Output driv en to VCC during Powerd own M ode
Output driv en to VSS du r in g P owe r do w n Mo de
Output floats during Pow erdown Mode
Out put remains active during Powerd own M ode
Output retains current state during Powerdown Mode
†The idle mode output states a ssume that no i nte rnal bus master (DMA or RCU) has control of the bus
during idle mode
Intel386™ E X Em bed ded Microp ro cesso r
Datasheet 13
Table 4. Intel386™ EX Microp ro cesso r Pin Descrip tions (Shee t 1 of 6)
Symbol Type Output States Name and Function
A25:1 O
H(Z)
R(1)
I(1)
P(1)
Add res s Bus outputs phys ical memory o r port I/O addresses.
These signals are valid when ADS# is a c tive an d remai n valid
until the next T1, T2P, or Ti. Du ring HOLD cy cles they are drive n
to a high- impedance st ate. A18:16 are m ultiplexed with C AS2:0.
ADS# O
H(Z)
R(1)
I(1)
P(1)
Address Status indicates that the proc essor is drivi ng a valid
bus-cycle definit ion and address (W/R#, D/C #, M/I O#, A25:1,
BHE#, BLE#) onto its pins.
BHE# O
H(Z)
R(0)
I(X)
P(0)
Byte High Enable indicates that the processor is transferring a
high data byte.
BLE# O
H(Z)
R(0)
I(X)
P(1)
Byte Low Enable indicates that the processor i s transferring a
low data byte.
BS8# I Bus Size indi c ates that an 8-bit d evice is currentl y being
addressed.
BUSY# I
Busy indicates that the math coprocessor is busy. If BUSY# is
sampled LOW at the falling edge of RESET, the processor
performs an internal self test. BUSY# is multiplexed with
TMRGATE2 and has a temporary weak pull-up resistor.
CAS2:0 O
H(Z)
R(1)
I(1)
P(1)
Cascade Address carries the slave address information from
the 8259A master interrupt module during interrupt acknowledge
bus cycles. CAS2:0 are multiplexed with A18:16.
CLK2 ST Clock Input is connected to an e xtern al clo c k that p rovides the
fundamental timing for th e device.
CLKOUT O
H(Q)
R(Q)
I(Q)
P(0)
CLKOUT is a PH1P clock output.
COMCLK I
Serial Communications Baud Clock is a n alternate clock
source for the asynchronous serial ports. COMCLK is
multiple xed with P3.7 and has a temp orary w eak pull-down
resistor.
CS4:0# O
H(1)
R(WH)
I(Q)
P(X)
Chip-selects are activated when the address of a memory or I/O
bus cycle is within the address region programm ed by the u s er .
They are mu ltiplexed as follows: CS6# with REFRESH#, CS5#
with DACK0#, and CS4:0# with P2.4:0.
CS6:5# O
H(1)
R(1)
I(Q)
P(X)
Chip-selects are activated when the address of a memory or I/O
bus cycle is within the address region programm ed by the u s er .
They are mu ltiplexed as follows: CS6# with REFRESH#, CS5#
with DACK0#, and CS4:0# with P2.4:0.
CTS1:0# I
C lear to Send SIO1 and SIO0 prevent the transmission of data
t o the asy nchron ou s se ria l port’s RX D1 and R XD 0 pins ,
respectively. CTS1# is multiplexed with E OP#, and CTS0# is
multiplexed with P2.7. CTS1# requires an external pull-up
resistor. Both have temporary weak pull-up resistors.
NOTES:
1. X if clock source is internal; Q if clock source is external
2. Q if JTAG unit is shifting out data, Z if it is not
Intel386™ E X Embe dde d Micro pro cesso r
14 Datasheet
D15:0 I/O H(Z)
R(Z)
P(Z)
Data Bus inputs data during memory read, I/O read, and
interrupt acknowledge cycles and outputs data during memory
and I/O write cyc les. During wri tes, this bus is d riven during
phase 2 of T1 and remai ns activ e until phase 2 of the nex t T1,
T1P, or Ti. During reads, data is latched on the falling edge of
phase 2.
DACK1:0# O
H(1)
R(1)
I(Q)
P(X)
DMA Acknowledge 1 and 0 signal to an external device that the
processor has acknowledged the corresponding DMA request
and is relinquishing the bus. DACK1# is multiplexed with TXD1,
and DACK0# is multiplexed with CS5#.
D/C# O
H(Z)
R(1)
I(0)
P(0)
Data/Control indi cates whether the current bus cycle is a data
cy cle (memory or I/O read or write) or a con trol cycle ( interrupt
ac knowledge, halt, or code fetch) .
DCD1:0 I
Data Carrier Detect SIO1 and SIO0 indicate that the mode m or
data set has detected the corresponding asynchronous serial
channel’s data carrier. DCD1# is m ultiplexed with DRQ0, and
DCD0# is multiplexed with P1.0 and has a temporary weak pull-
up resistor.
DRQ1:0 I DMA External Request 1 and 0 indicate that a peripheral
requires DMA service. DRQ1 is multiplexed with RXD1, and
DRQ0 is multiplexed with DCD1#.
DSR1:0# I
Data Set Ready SIO1 and SIO 0 indicate that the modem or data
set is ready to establish a communication link with the
corresponding asynchronous serial channe l. DSR1# is
multipl exed with STXCLK and has a p ermanent weak pull-up
resistor, and DSR0# is multiplexed with P1.3 and has a
temporary wea k pull-up resistor.
DTR1:0# O
H(X)
R(WH)
I(X)
P(X)
Data Terminal Ready SIO1 and SIO0 indicate that the
corresponding asyn chronous ser ial ch annel is ready to esta blish
a communication link with the modem or data set. DTR1# is
multipl exed with SR XCLK, and DTR 0# is multiplexed with P1.2.
EOP# I/OD
H(Z)
R(WH)
I(Z)
P(Z)
End of Process i ndicates that th e processor has reached
terminal count during a DMA transfer. An external device can
also pull this pin LOW. EOP# is multip lexed with CTS1#.
ERROR# I Error indi cat es that th e math co proces sor ha s an er ror co nditi on.
ER ROR# is multiplexed with TMROUT2 and has a temporary
weak pull-up resistor.
FLT# I
Float force s all bidirectional and output signals except TDO to a
high-impedance state. It has a permanent weak pull-up resistor.
This pin shou ld be ti ed t o VCC through a 3 to 7 KOhm pull-up
resistor.
HLDA O
H(1)
R(WL)
I(Q)
P(X)
Bus Hold Acknowledge indicates that the processor has
surrender ed control of its local bus to another bus ma ster. HLDA
is multiplexed with P1.7.
HOLD I
Bus Hold Request allows another bus master to request control
of the local bus. HLDA active indicates that bus control has been
granted. HOLD is multiplexed with P1.6. It has a temporary weak
pull-do wn resistor.
Table 4. Intel386™ E X Micr oprocessor Pin Description s (Sheet 2 of 6)
Symbol Type Output States Name and Function
NOTES:
1. X if clo ck source is internal; Q if clock source is ex ternal
2. Q if JTAG unit is shifti ng out data, Z if it i s not
Intel386™ E X Em bed ded Microp ro cesso r
Datasheet 15
INT9:0 I
Interrupt Requests are maskable inputs that caus e the CPU to
sus pend execution of the current program and then execute an
interrupt acknowledge cycle. They are multiplexed as follows:
INT9 with TMROUT0 and P3.0, INT8 with TMROUT1 and P3.1,
INT7 with TMRGATE1, INT6 with TMRCLK1, INT5 with
TMRGATE0, INT4 with TMRCLK0, and INT3:0 with P3.5:2.
INT9, INT8, and INT3:0 have temporary weak pull-down
resistors.
LBA# O
H(1)
R(1)
I(Q)
P(X)
Loca l Bus A cce ss is asserted whenever the processor provides
the READY# signal to terminat e a bus transact ion. This occurs
when an internal peripher al address is accessed or when the
chip-select unit provides the READY# signal.
LOCK# O
H(Z)
R(WH)
I(X)
P(X)
Bus Lock p r event s ot her b us maste r s fr om ga ini ng con tr ol of t h e
system bus.
LOCK# is multiplexed with P1.5.
M/IO# O
H(Z)
R(0)
I(1)
P(1)
Memory/IO Indicates whether the current bus cycle is a memory
cyc le or an I/O c y cle. W hen M/IO# is HIGH, the bus cycle is a
memory cycle; when M/IO# is LOW, the bus cycle is an I/O cycle.
NA# I Next Address requests address pipelining.
NMI ST Nonmaskable Interrupt Request is a non-maskable input that
causes the CPU to suspend execution of the current program
and execute an interrupt acknowledge c ycle.
PEREQ I
Processor Extension Request indicates that the math
coprocessor has data to transfer to t he pro c essor. PERE Q is
multiplexed with TMRCLK2 and has a temporary weak pull-down
resistor.
P1.5:0 I/O
H(X)
R(WH)
I(X)
P(X)
Port 1, Pins 7:0 are multipurpose bid irectional p ort pins. They
are multiplexed as follows: P1.7 with HLDA, P1.6 with HOLD,
P1.5 with LOCK#, P1.4 with RI0#, P1.3 with DSR0#, P1.2 with
DT R0#, P1 .1 with RTS0#, and P1.0 with DCD0#.
P1.7:6 I/O
H(X)
R(WL)
I(X)
P(X)
Port 1, Pins 7:0 are multipurpose bid irectional p ort pins. They
are multiplexed as follows: P1.7 with HLDA, P1.6 with HOLD,
P1.5 with LOCK#, P1.4 with RI0#, P1.3 with DSR0#, P1.2 with
DT R0#, P1 .1 with RTS0#, and P1.0 with DCD0#.
P2.7,4:0 I/O
H(X)
R(WH)
I(X)
P(X)
Port 2, Pins 7:0 are multipurpose bid irectional p ort pins. They
are multiplexed as follows: P2.7 with CTS0#, P2.6 with TXD0,
P2.5 with RXD0, and P2.4:0 with CS4:0#.
P2.6:5 I/O
H(X)
R(WL)
I(X)
P(X)
Port 2, Pins 7:0 are multipurpose bid irectional p ort pins. They
are multiplexed as follows: P2.7 with CTS0#, P2.6 with TXD0,
P2.5 with RXD0, and P2.4:0 with CS4:0#.
P3.7:0 I/O
H(X)
R(WL)
I(X)
P(X)
Port 3, Pins 7:0 are multipurpose bid irectional p ort pins. They
are multiplexed as follows: P3.7 with COMCLK, P3.6 with
PWRDOWN, P3.5:2 with INT3:0, and P3.1:0 with TMROUT1:0
an d INT8:9.
Table 4. Intel386™ EX Microp ro cesso r Pin Descrip tions (Shee t 3 of 6)
Symbol Type Output States Name and Function
NOTES:
1. X if clock source is internal; Q if clock source is external
2. Q if JTAG unit is shifting out data, Z if it is not
Intel386™ E X Embe dde d Micro pro cesso r
16 Datasheet
PWRDOWN O
H(Q)
R(WL)
I(X)
P(1)
Powerdown indicates that the processor is in powerdown mode.
PWRDOWN is multiplexed with P3.6.
RD# O
H(1)
R(1)
I(1)
P(1)
Read Enable indicates that the current bus cycle is a read cycle.
READY# I/O
H(Z)
R(Z)
I(Z)
P(Z)
Ready indicates that the current bus transaction has completed.
An external devi ce or an internal signal can dr ive REA DY#.
Internally, the chip-select wait-s tate logic can gener ate the ready
signal and drive the READY# pin ac tive.
RESET ST Reset su spends any operation in progress an d places the
processor into a known reset state.
REFRESH# O
H(1)
R(1)
I(Q)
P(X)
Refresh indicate s that the c urrent bus cycle is a refresh c ycle.
RE FRESH# is multiplexed with CS6#.
RI1:0# I
Ring Indicator SIO1 and SIO0 in dicate that the m odem or d ata
set has received a telephone ringing signal. RI1# is multiplexed
with SSIORX, and RI0# is multiplexed with P1.4 and has a
temporary wea k pull-up resistor.
RTS1# O
H(X)
R(WL)
I(X)
P(X)
Request-to-send SIO1 and SIO0 indicate that corresponding
asynchronous serial channel is ready to exchange data with the
modem or da ta set. RTS1# is mu ltiplex ed with SSIOTX, and
RTS0# is multiplexed with P1.1.
RTS0# O
H(X)
R(WH)
I(X)
P(X)
Request-to-send SIO1 and SIO0 indicate that corresponding
asynchronous serial channel is ready to exchange data with the
modem or da ta set. RTS1# is mu ltiplex ed with SSIOTX, and
RTS0# is multiplexed with P1.1.
RXD1:0 I
Receive Data SIO1 and SIO0 accept serial data from the
modem or data set to the correspo nding asynchronous seri al
channel. RXD1 is multiplexed with DRQ1, and RXD0 is
multipl exed with P2.5 and has a tem porary w eak pull-down
resistor.
SMI# ST
System Management Interrupt invokes System Management
Mode (SMM). SMI# is the highest priority external interrupt. It is
latched on i ts falling edge and forc es the CPU into SMM upon
completion of the current instruction. SMI# is recognized on an
instruction bo undary and at ea ch iteration for repeat string
instructions. SMI# cannot in terrupt LOCKed bus cy cles or a
currently exec uting SMM. When the proc essor receiv es a
second SMI# while in SMM, it latches the second SM I# on th e
SMI# falling edge. However , the processor must exit SMM by
ex ecuting a resume instruction (RSM) before it can service t he
second SMI#. SMI# has a permanent w eak pull -up resistor.
SMIACT# O
H(1)
R(1)
I(X)
P(X)
System Management Interrupt Active indicates that the
processo r is operating in System M anageme nt Mode (SMM). It
is asserted when the proce ssor initiates an SMM sequence a nd
remains asserted (LOW) until the processor executes the
resume instruction (RSM).
Table 4. Intel386™ E X Micr oprocessor Pin Description s (Sheet 4 of 6)
Symbol Type Output States Name and Function
NOTES:
1. X if clo ck source is internal; Q if clock source is ex ternal
2. Q if JTAG unit is shifti ng out data, Z if it i s not
Intel386™ E X Em bed ded Microp ro cesso r
Datasheet 17
SRXCLK I/O
H(Q)
R(WH)
I(Q)
P(X)/P(Q)Note 1
SSIO Receive Clock s y nchro nizes data be ing accepted by the
synchronous serial port. SRXCLK i s multip lexed with DTR1#.
SSIORX I SSIO Receive Serial Data accepts serial data (most-significant
bit first) being sent to the synchronous serial port. SSIORX is
multiple xed with RI 1#.
SSIOTX O
H(Q)
R(WL)
I(Q)
P(X)/P(Q)Note 1
SSIO Transmit Serial Data sends serial data (most-significant
bit fir st) from the synchronous serial por t. SSI O TX is multiplexed
with RTS1#.
Intel does not specify a data hold time for SSIOTX. Slower
external devices may require additional hardwar e t o properly
interface the SSIO unit.
STXCLK I/O
H(Q)
R(WH)
I(Q)
P(X)/P(Q)Note 1
SSIO Transmit Clock synchronizes da ta being sent by the
synchronous serial port. STXCLK is multiplexed with DSR1.
TCK I TAP (Test Access Port) Controller Clock provides the clock
input for the JTAG logic . It has a pe rmanent weak pull-u p
resistor.
TDI I TAP (Test Access Port) Controller Da ta Input is the serial
input for test instructions and data. It has a permanent weak pull-
up resistor.
TDO O
H(Z)/H(Q)Note 2
R(Z)/R(Q)Note 2
I(Z)/I(Q)Note 2
P(Z)/ P(Q)Note 2
TAP (Test Acc ess Port) Controller Data Output is the serial
output for test instructions and data.
TMRCLK2:0 I
Timer/Counter Clock Inputs can ser v e as external cl ock inputs
for the corresponding timer/counters. (The timer/counters can
also be clocked inter nally.) They are mul tiple xed as follows:
TMRCL K2 with PEREQ, TMRCLK1 with INT6, and TMRCLK0
with INT4. TMRCLK2 has a temporary weak pull-down resistor.
TMRGATE2:0 I
Timer/Counter Gate Inputs can cont rol the corresponding
t im er/ coun te r’s cou nting (ena bl e, disa bl e, or tr ig ge r, depe nd in g
on the programmed mode). They are multiplexed as follows:
TMRGATE2 with BUSY#, TMRGATE1 with INT7, and
TMRGATE0 with INT5. TMRGATE2 has a temporary weak pull-
up resistor.
TMROUT2 O
H(Q)
R(WH)
I(Q)
P(X)/P(Q)Note 1
Timer/Counter Outputs provide the output of the corresponding
timer/counter. The form of the output depends on the
programm ed mode. They are multiplexed as follows: TMROUT2
with ERROR#, TMROUT1 with P3.1 and INT8, and TMROUT0
with P3.0 and INT9.
TMROUT1:0 O
H(Q)
R(WL)
I(Q)
P(X)/P(Q)Note 1
Timer/Counter Outputs provide the output of the corresponding
timer/counter. The form of the output depends on the
programm ed mode. They are multiplexed as follows: TMROUT2
with ERROR#, TMROUT1 with P3.1 and INT8, and TMROUT0
with P3.0 and INT9.
TMS I TAP (Test Access Port) Controller Mode Select controls the
sequence of the TAP controller’s states. It has a permanent
weak pull-up resistor.
Table 4. Intel386™ EX Microp ro cesso r Pin Descrip tions (Shee t 5 of 6)
Symbol Type Output States Name and Function
NOTES:
1. X if clock source is internal; Q if clock source is external
2. Q if JTAG unit is shifting out data, Z if it is not
Intel386™ E X Embe dde d Micro pro cesso r
18 Datasheet
TRST# ST TAP (Test Access Port) Controller Reset resets the TAP
controller at power-up and each time it is activated. It has a
permanent we ak pull-up resistor.
TXD1 O
H(Q)
R(1)
I(Q)
P(X)/P(Q)Note 1
T ra nsmit Data SIO1 and SIO0 transmit serial data from the
individual serial channels. TXD1 is multiplexed with DACK1#,
and TXD0 is multiplexed with P2.6.
TXD0 O
H(Q)
R(WL)
I(Q)
P(X)/P(Q)Note 1
T ra nsmit Data SIO1 and SIO0 transmit serial data from the
individual serial channels. TXD1 is multiplexed with DACK1#,
and TXD0 is multiplexed with P2.6.
UCS# O
H(1)
R(0)
I(Q)
P(X)
Upper Chip-select is activated when the address of a memory
or I/O bus cycle is within the address region programmed by the
user.
VCC PSys tem Powe r provi de s t he nomi na l DC suppl y in pu t. T hi s pi n is
connected ex ternally to a VCC board plane.
VSS GSystem Ground provides the 0 V connection from which al l
inputs and ou tputs are measu red. This pin is co nnected
ex ternally to a gr ound board plane.
WDTOUT O
H(Q)
R(0)
I(Q)
P(X)
Watchdog Timer Output indicates that the watchdog timer has
expired.
W/R# O
H(Z)
R(0)
I(1)
P(1)
Write/Read indicates whether the current bus cycle is a write
cy cle or a read cycl e. When W/R# is HIG H, the bus cycle is a
wr ite cycle; w hen W/R# is LOW, the bus cy cle is a read cycle.
WR# O
H(1)
R(1)
I(1)
P(1)
Write Enable indi cat es t hat t he cur ren t bus cyc le is a wri te cyc le .
Table 4. Intel386™ E X Micr oprocessor Pin Description s (Sheet 6 of 6)
Symbol Type Output States Name and Function
NOTES:
1. X if clo ck source is internal; Q if clock source is ex ternal
2. Q if JTAG unit is shifti ng out data, Z if it i s not
Intel386™ E X Em bed ded Microp ro cesso r
Datasheet 19
4.0 Function al Descripti on
The Int el386 EX microprocessor is a fully st atic, 32-bit proc essor optimized for embe dded
applications . It feat ures low power and low voltage capabilities, integra tion of ma ny commonly
use d DOS-t ype pe ripherals, and a 32-bi t programming architec ture compatible with the large
software ba s e of Intel386 processors . The following secti ons pr ovide an overview of the integrated
peripherals.
4.1 Clock G eneration and Po wer Management Unit
The clock gene ration circuit includes a divide-by-two counter, a programmable divider for
generating a pre scale d cloc k (P S CLK), a divide-by-two counter for generating baud-rate clock
inputs, and Re se t circuitry. The CLK2 input prov ides the fundamental timing for the chi p. It is
divided by two internally to generate a 50% duty cycle Phase1 (PH1) and Phase 2 (PH2) for the
core and integrate d peripheral s. Fo r power mana gement, separate clocks are route d to the core
(PH1C/ P H 2C) and the pe ripheral modules (PH1P/PH 2P ). To help synchronize with externa l
devices, the PH1P clock is provided on the CLKOUT output pin.
Two Power Mana gement m odes ar e provide d for flexibl e po wer- sav ing option s. Durin g Idle m ode,
the clocks to the CPU core are frozen in a known state (PH1C low and PH2C high), while the
cloc ks to the peripherals continue to toggle. In Powerdown mode, the clocks to both core and
peripherals are frozen in a known state (PH1C low and PH2C high ). Th e Bus I nterface Unit will
not hono r any DMA, DRAM ref resh, or HOLD reque sts in Powe rdown mode beca use the c locks to
th e en tire d ev ice are frozen.
4.2 Chip-select Un it
The Chip-Sele ct Unit (CSU) decodes bus cycle address and status information a nd enables the
appropriate chip-selects. The individual chip-selects become valid in the same bus state as the
add r ess an d b ec ome in a ct iv e when ei th er a new ad d r ess is sele ct ed or th e cur r e nt bu s cy cle is
complete.
The CSU is divided into eight s epara te chip-select regions, each of which can enable one of th e
eight chip-select pins. Each chip-select reg ion can be mapped into memor y or I/O space. A
memory-map ped chip -select region c an start on a ny 2 (n+1) Kbyt e addre ss loca tion (wher e n = 0–1 5,
depending upon the mask register). An I/O-m apped chip-select region can start on any 2(n+1) byte
addre ss locat ion (where n = 0–15, depending upon the mask re gis ter). The s ize of the region is also
dependent upon the mask used.
4.3 Interrupt Control Unit
The Intel38 6 EX processor’ s Int err upt Control Un it (ICU) contains two 8259A mod ules con necte d
in a cascade mode. These modules are similar to the industry-standard 8259A a rchitecture.
The Int errupt Control Unit directly supports up to ten external (INT9:0) and up to eig ht internal
interrupt request signals. Pending interrupt requests are posted in the Interrupt Re quest Registers,
which contain one bit for ea ch interrupt reques t s ignal. Whe n an interrupt request is asse rted, the
corresponding Interrupt Request Register bit is set. Th e 8259A mo dules can be programmed to
Intel386™ E X Embe dde d Micro pro cesso r
20 Datasheet
r ecognize either an active-high level or a positive transit ion on the interrupt req ues t lines. An
inte rnal Priori ty Resolver decides which pending interrupt request (if m ore than one exists) is the
highest priorit y, bas ed on the programmed operat ing mode . The Priority Reso lver controls the
sin g l e in terr upt request lin e to th e C P U . T h e P r io r i ty Reso lv er’s def a ult pr io r ity s ch eme p lace s th e
master interrupt controller ’s IR 0 as the highes t priority and the master’s IR7 as the lowest. T he
priority can be modified through software.
Besides the ten interrupt request inputs available to the Intel386 EX microprocessor, additiona l
interrupts can be supported by cascaded exte rnal 8259A modules. Up to four external 8259A units
can be cascaded to the mas ter t hrough c onnections to the INT3:0 pins. In this configuration, the
interrupt acknowledge (INTA#) signal can be decoded externally using the ADS#, D/C#, W/R#,
and M/IO# s ignals.
4.4 Timer/Counter Unit
The Timer/Counter Unit (TCU) on the Intel386 EX microprocessor has the same basic
f unctionality as the indust ry-standard 82C54 counter/timer. The TCU provides three independent
16-bit counters, e ach capable of handling clock inputs up to 8 MHz. This maxim um frequency
must be considered when programming the input clocks for the counters. Six programmable timer
mode s allow the counters to be used as event counters, elapsed- time indicators, programmable one-
shots, and in many other applications. All modes are software programmable.
4.5 Watch dog Timer U nit
The Watchdog Timer (WDT) unit consists of a 32-bit down-counte r tha t decrements every PH1P
cycle, allowing up t o 4.3 billion count intervals. The WDTOUT pin is driv en high for sixteen
CLK2 cycl es when the down-c ounter reache s zero (the WDT times out). The WDTOUT signa l can
b e us ed to reset the chip, to reque st an inter r upt, or to indicate to the use r that a ready-hang
situation has occurred. The down- counter can a ls o be updated with a user-defined 32-bit reload
value under certa in conditions. Alternatively, the WDT uni t can be used as a bus monitor or as a
general-purpos e timer.
4.6 Asyn chronou s Serial I/O Unit
The Intel386 EX microproc essor’ s asynchronous Se rial I/O (SIO) unit i s a Universal
Asynchronous Receive r/ Transmitter (UART). Functionally, it is equivalent to the National
Semiconductor NS16450 and INS8250. The Intel386 EX embedded processor conta ins two full-
duplex, asynchronous serial channels.
The SI O unit con v ert s se ria l da ta char a cter s re ce ive d fr om a pe rip h era l d evi ce o r mo dem to p ara ll el
data and converts parallel data characters re ce ived from the CPU to seri al data. The CPU ca n read
the stat us of t he se rial port at any time during i ts ope ration . The stat us in format ion inc ludes the ty pe
and c ondition of the transfer operations being performed and any errors (parity, framing, overrun,
or break interrupt).
Intel386™ E X Em bed ded Microp ro cesso r
Datasheet 21
Each asynchronous serial channel includes full modem control support (CTS#, RT S#, DSR#,
DTR#, RI#, and DCD#) and is com pletely programm able. The programmable options include
chara cter leng th (5, 6, 7, or 8 bits) , stop bits (1, 1. 5, or 2), and parit y (e ven, odd, forc ed , or none). In
addition, it conta ins a programmable baud-rate gener ator cap able of clock rate s from 0 to 512
Kbaud.
4.7 Synchronous Serial I/O Unit
The Synchronous Serial I/O (S SIO) un it provides for si multaneous, b idirectional communications.
It cons is ts of a tra ns mit channel, a recei ve channel, and a dedica ted baud-rate generator. The
tr ans m it and receive channels can be ope rated independently (with different cloc ks) to provide
non-loc kste p, full-du ple x communi cati ons; eithe r c hannel can orig inate th e clo cking si gna l (Mas ter
Mode) or receive a n externally generated clocking signal (Slave Mode).
The SSIO provides num erous featur es for ease and flexib ili ty of opera tion. Wi th a maximum cloc k
input of CLK2/4 to the baud-rate generator, the SSIO can deliver a baud rate of up to 8.25 Mbit s
per second with a processor clock of 33 MHz. Each channel is double buffered. The two channels
sha re the ba ud-rate genera tor a nd a mul tiply- by-two tra nsmit an d receive c lock. The SSI O supports
16- bit se rial communic ations with i ndependently enable d transmit and receive functions and gated
interrupt outputs to the interrupt controller.
4.8 Paral lel I/O Uni t
The Intel386 EX microprocess or has three 8-bit, general-purpose I/O port s. All port pins are
bidirectional, with TTL-level inputs and CMOS-level outputs. All pins have both a s tandard
opera tin g m ode and a periph era l mode (a multipl exed func ti on), and al l have simila r sets of cont rol
regist ers located in I/O address space.
4.9 DMA and Bus Arbiter Un it
The Intel386 EX microprocess or’s DMA con troller is a two-channel DMA; each channel opera tes
independently of the other . Within the operation of the individual channels, several different da ta
transfer modes are available. These modes can be combined in various configurations to provide a
very versatile DMA controller. Its feat ure set has enha ncements beyond the 8237 DMA famil y;
however, it can be c onfigured such that it can be used in an 8237-like mode. Each channel can
tr ans fer d ata bet ween any combination of memory a nd I /O with any combin ation (8 or 16 bits) of
data path widths. An in ternal temporary register that ca n dis as s em ble or assemble data to or from
either an aligned or a nonaligned dest ination or sour ce optimiz es bus bandwidth.
The bus ar biter, a part of the DMA con tr oller, works muc h like the priority resolving circuitry of a
DMA. It receives service requests from the two DMA channels, the external bus master, and the
DRAM Refres h Control Unit. The bus arbiter requests bus owners hip from the co re and resolv es
priority issues among a ll active reque sts when bus mast ers hip is granted.
Eac h DMA channe l consists of three major com ponents: the Req ues tor, the Target, and the Byte
Count. The se components are identified by the conte nts of programma ble register s that defin e the
memory or I/O de vice being serviced by the DMA. The Reque st or is the device that requires and
requests service from th e DMA c ontroller. Only the Requestor is considered capabl e of initializing
Intel386™ E X Embe dde d Micro pro cesso r
22 Datasheet
or terminating a DMA proces s. The Target is the device with which the Reques tor wi shes to
communicate. The DMA process considers the Target a slave that is incapable of controlling the
pr ocess. The Byte Count dictates the amount of data that must be transferred.
4.10 Refresh Control Unit
The Refresh Control Unit (RCU) simplifies dynamic memory controller design with its inte grated
address and clo ck counters . Integrating the RCU into the proc essor allows an external DRAM
controller to use chip-selects, wait state logic, and stat us l ines.
The Refresh Cont rol Unit:
•Prov i d es a p rog r amma bl e -i n te r v al timer
•Provides the bus arbitrat ion logic to gain control of the bus to run refresh cycles
•Contains the logic to gener ate row addre sses to refresh DRAM rows indivi dually
•Contains the logic to signal the s tart of a refres h cyc le
The RCU conta ins a 13-bit addre ss cou nter tha t f orms the r efres h addres s, su pport ing DRAMs with
up to 13 rows of memo ry cells (13 refre sh address bits). This i nclude s all practi cal DRAM sizes for
the Intel 386 EX microprocessor’s 64 Mbyte address sp ac e.
4.11 JTAG Test-logic Unit
The JTAG Test-logi c Un it provi des acc ess to the devic e pins and to a numbe r of othe r te stable ar eas
on the device. It is f ully compliant with the IEEE 1149.1 standard and thus interfaces with five
dedicated pins: TRST#, TCK, TMS, TDI , and TDO. It contains the Tes t Acce ss P ort (TAP) fini te-
state machine, a 4-bit instruction register , a 32-bit identification regis ter, and a s ingle-bit bypass
register. The test-logic unit also c ontains the necessary logic to generate clock and cont rol signals
for the Boundary Scan cha in.
Si nce the test-logic unit has its own clock and reset s ignals, i t can opera te autonom ously. While the
rest of the microprocessor is in Reset or Powerdown, the JTAG unit can read or write various
register chains.
Intel386™ E X Em bed ded Microp ro cesso r
Datasheet 23
5.0 Design Considerations
This section describes the Intel386 EX microprocessor’s ins truction set and its component and
revision identifiers.
5.1 Instruction Set
The Intel386 EX microprocess or us es the same instruction set as the Intel386 SX microprocessor
with the following exceptions.
The Intel386 EX microprocess or has one new instruction (RSM). This Resume ins truction ca uses
the processor to exit Syste m Management Mode (SMM). RSM requires 338 clocks per instruction
(CPI).
The Intel386 EX microprocess or requires more cloc k cyc les than the Intel386 SX micro processor
to execute s ome instructions. Table 5 lists these ins tructions and the Intel386 EX microproc essor
cloc k count. For the equi valent Inte l386 SX microprocess or clock count, refer to the “Instruction
Set Clock Count Summary” ta ble in the Intel386™ SX Microprocessor datash ee t (o rd er nu mber
240187).
Table 5. Micr oproces sor Cl ocks Per Instruc tio n
Instruction
Clock Count (1)
Virtual 8086 Mode(2) Real Address Mode
or Virtual 8086 Mode Protected V irtual Address Mode(3)
POPA 29 35
IN:
Fixed Port
Variable Port 27
28 14
15 8/29
9/29
OUT:
Fixed Port
Variable Port 27
28 14
15 8/29
9/29
INS 30 17 10/32
OUTS 31 18 11/33
REP INS 31+6
n
(No te 4)17+7
n
(Note 4)11+7
n
/32+6
n
(Note 4)
REP OUTS 30+8
n
(No te 4)16+8
n
(Note 4)10+8
n
/31+8
n
(Note 4)
HLT 7 7
MOV CR0, reg 10 10
NOTES:
1. For IN, OUT, INS, OUTS, REP INS, and REP OUTS instructions, add one clock count for each wait state
genera ted by the peripheral being ac cessed ( the values in the table a re for zero wait state).
2. The clock count values in this column apply if I/O permission allows I/O to the port in virtual 8086 mode. If
the I/O bit map denies permission, exception fault 13 occurs; see clock counts for the INT 3 instruction in
the “Instruction Set Clock Count Summary” table in the
Intel386™ SX Microprocessor
datasheet (order
number 240187).
3. When two clock counts are listed, the smaller value refers to the case where CPL ≤ IOPL and the larger
v a lue re fers t o the case where CPL>IOPL. CPL is the current privilege level, and IOPL is the I/O privilege
level.
4.
n
= the n umber of times repeated .
Intel386™ E X Embe dde d Micro pro cesso r
24 Datasheet
5.2 Com p onen t an d Revision Iden tif ier s
To as sist users, the micr oprocessor holds a component identifier and revi sion identifier in its DX
r egist er after reset. The upper 8 bits of DX hold the com ponent identifie r, 23H. (The lower nibble,
3H , identifies the Intel386 architecture, while the upper nib ble, 2H, identifies the se cond member
of the Int el386 microproc essor family.)
The lower 8 bits of DX hold th e revision level identifier. The revi si on identifier will, in general ,
chron olog icall y tr ack tho se co mponent ste pping s tha t are i nte nded to h ave certa in imp rovements or
distinction from previous s teppings. The revi s ion identifier will track that of the Intel386 CPU
whenever possible. However, the revision identifier va lue is not guarantee d to change with ev ery
stepping re vision or to follow a completely uniform numerica l sequenc e, depending on the type or
intent of the revision or the manufac turing materials require d to be changed. Intel has sole
discreti on over thes e cha r acteris tics of the component. The initial revision identifier for the
Intel386 EX microprocessor is 09H.
5.3 Package Thermal Specifications
The Intel386 EX microproc essor is spec ified for operation with a minimum case temperature
(TCASE(MIN)) of -40° C and a maximum case temperature (TCASE(MAX)) dep end e nt on pow e r
dis sipa tion (se e Figures 4 throu gh 7). The ca se tempera ture can be measured in any environm ent to
determine whether the microprocessor is within the specified operating range. The case
temperature shoul d be measured at the cent er of the top surface opposite the pins.
An increase in the ambient temperature (T A) ca uses a proport ion al increas e in the case tempera tur e
(TCASE) and t h e ju nction temperature (TJ), which is the junction te mperature on the die itself. A
packaged dev ice produces thermal res is tance bet ween junction and case temperatures (θJC) and
betw een junction and ambient tempera tures (θJA). The relationships between the temperature and
thermal resistance parameters are expressed by these equations:
TJ = TCASE + P × θJC
TA = TJ – P × θJA
TCASE = TA + P × [θJA – θJC]
P = power dissipated as heat = VCC × ICC
A safe operating temper ature can be calcu lated fr om the above equations by using the maxim um
safe TJ of 120° C, the power drawn by the chip in the specific design, and the θJC value from Table
6. The θJA value de pends on the airflow (measured at the top of the chip) pr ovided by the system
ventilation, board l ayout, board thickness, and potentially other factors in the design of the
application. The θJA values are given for reference only and a re not guaranteed.
Fi gures 4 through 7 provide maximum case temperature as a function of frequency.
Table 6. Thermal Resistances (0°C/W) θJA, θJC
Package θJC
θJA vs. Airflow (ft/min)
0100200
13 2 PQFP 7 28 2 4 22
14 4 TQFP 4 36 31 27
Intel386™ E X Em bed ded Microp ro cesso r
Datasheet 25
Figure 4. M axi mum Case Temp eratu re vs. Frequency for Typical Power Value s
(132-lead PQFP, VCC = 5.5 V)
Figure 5. M axi mum Case Temp eratu re vs. Frequ ency for Typical Power Value s
(144-lead TQFP, VCC = 5.5 V nominal )
A3346-02
107
16 20 25
113.9
112.25
110.7
132 Lead PQFP
Tc
(deg C)
Operating Frequency (MHz)
108
109
110
111
112
113
114
33
107.8
A3347-02
108
16 20 25
114.9
113.5
112.25
144 Lead TQFP
Tc
(deg C)
Operating Frequency (MHz)
109
110
111
112
113
114
115
116
33
109.8
Intel386™ E X Embe dde d Micro pro cesso r
26 Datasheet
Figure 6. Max imu m Case Tempe rature vs. Frequen cy for Typical Powe r Values
(132-lead PQFP, VCC = 3.6 V)
Figure 7. Max imu m Case Tempe rature vs. Frequen cy for Typical Powe r Values
(144-lead TQFP, VCC = 3.6 V)
A3348-02
117.5
117.0
116.5
16 20 25
117.5
117.0
116.5
132 Lead PQFP
Tc
(deg C)
Operating Frequency (MHz)
A3349-01
118.0
117.5
117.0
16 20 25
118.0
117.5
117.0
144 Lead TQFP
Tc
(deg C)
Operating Frequency (MHz)
Intel386™ E X Em bed ded Microp ro cesso r
Datasheet 27
6.0 Electrical Specifications
6.1 Maximum Ratings
Warning: Stressing the device beyond the “Maximum Ratin gs” may c ause permanent dam age . T hes e are
stress rat ings onl y.
Table 7. 5 V Intel386 EXT C Processo r Max imu m Ratings
Parameter Maximum Rating
Storage Temperature –65°C to +150°C
Supply Voltage with Respect to VSS –0.5 V to 6.5 V
Voltage on Other Pins –0.5 V to VCC + 0.5 V
VCC (Digital Supply Voltage) 4.5 V to 5.5 V
TCASE (Case Temperature Under Bias)
TCASE(MIN)
TCASE(MAX) -40°C
(see Figures 4 and 5)
FOSC (Operating Frequency) 0 MHz to 33 MHz
Table 8. 3 V Intel386 EXT B Processo r Max imu m Ratings
Parameter Maximum Rating
Sto rag e Temp e r atu re –65°C to +1 50 °C
Supply Voltage with Respect to VSS –0.5 V to 4.6 V
Voltage on Other Pins –0.5 V to VCC + 0.5 V
VCC (Digital Supply Voltage) 20 MHz — 2.7 V to 3.6 V
25 MHz — 3.0 V to 3.6 V
TCASE (Case Temperature Under Bias)
TCASE(MIN)
TCASE(MAX) -40°C
(see Figures 6 and 7)
FOSC (Operating Frequency) 0 MHz to 25 MHz
Intel386™ E X Embe dde d Micro pro cesso r
28 Datasheet
6.2 DC Specifications
Table 9. 5-Vo lt DC Chara cteristics
Symbol Parameter Min. Max. Unit T e st Condition
VIL Input Low Voltage for all input pins
ex cept CLK2, TRST#, RESET,
S MI #, an d NMI –0.3 0.8 V
VIH Input Hi gh Voltage for all input pins
ex cept CLK2, TRST#, RESET,
S MI #, an d NMI 2.0 VCC + 0.3 V
VILC Input Low Voltage for CLK2,
TRST#, RESET, SMI#, and NMI -0.3 0.8 V
VIHC Input High Voltage for CLK2,
TRST#, RESET, SMI#, and NMI VCC-0.8 VCC+0.3 V
VOL
Output Low Voltage
All pins except Port 3
Port 3 0.45
0.45 V
VIOL = 8 mA
IOL = 16 mA
VOH
Output High Voltage
A ll ou tp ut pin s
All pins except Port 3
Port 3 pins (2 max)
VCC-0.5
2.45
2.45
V
V
V
IOH = –0.2 mA
IOH = –8 mA
IOH = –16 mA
VOLC CLKOUT 0.45 V IOL = 2 mA
VOHC CLKOUT VCC-0.5
2.45 VIOH = –0.2 mA
IOH = –2 mA
ILI In put Leakage Curren t ±15 µA 0 ≤ VIN ≤ VCC
FL T# is not tes ted for ILI
ILO Ou tp ut Le ak age Curren t ±15 µ A 0 .4 5V ≤ VOUT ≤ VCC
ICC Supply Current
320
250 mA
mA FOSC =3 3 M Hz
FOSC =2 5 MHz
(tested with device held in
reset, inputs held in their
inactive state)
IIDLE Idle Mod e Current 110
85 mA
mA FOSC =3 3 M Hz
FOSC =25 MHz
IPD Powerdown Current 100 µA
CSPin C apacitance (an y pin to VSS) 10 pF Not tested
Intel386™ E X Em bed ded Microp ro cesso r
Datasheet 29
Table 10. 3-Volt DC Characteristics
Symbol Parameter Min. Max. Unit Test Condition
VIL
Input Low Voltage for all
input pin s except CLK2,
TRST#, RESET, SMI#, and
NMI
–0.3 0.8 V
VIH
Input High Voltage for all
input pin s except CLK2,
TRST#, RESET, SMI#, and
NMI
2.0 VCC + 0.3 V
VILC Inp ut Low Vol tage for CLK2,
TRST#, RESET, SMI#, and
NMI -0.3 0.8 V
VIHC Input High Voltage for CLK2,
TRST#, RESET, SMI#, and
NMI VCC-0.6 VCC+0.3 V
VOL
Out put Low Voltage
All pins except Port 3
Port 3 pins (2 max)
0.20
0.45
0.45
V
V
V
IOL = 100 µA , 2.7 V ≤VCC≤3.6 V
(LVCMOS)
IOL = 4mA, 3.0 V≤VCC≤3.6 V (LVTTL)
IOL = 8mA, 3.0 V≤VCC≤3.6 V (LVTTL)
VOH
Output High V oltage
All pins except Port 3
Port 3
VCC-0.2
VCC-0.65
VCC-0.65
V
V
V
IOH= -100 µA, 2.7 V≤VCC≤3.6 V
(LVCMOS)
IOH= -4mA, 3.0 V≤VCC≤3.6V (LVTTL)
IOH= -8mA, 3.0 V≤VCC≤3.6V (LVTTL)
VOLC CLKOUT 0.2
0.45 VIOL = 100 µA, 2.7 V ≤VCC≤3.6 V
IOL = 1 mA, 3.0 V ≤VCC ≤3.6 V
(LVTTL)
VOHC CLKOUT VCC-0.2
VCC-0.65 VIOH = -100 µA, 2.7 V ≤VCC ≤3.6 V
IOH = -1 mA, 3.0 V ≤VCC ≤3.6 V
(LVTTL)
ILI Input Lea kage Current ±5 µA 0 ≤ VIN ≤ VCC
FLT# is no t tested for ILI
ILO Outp ut Leakage Current ±15 µA 0.45V ≤ VOUT ≤ VCC
ICC Supply Current
140
110 mA
mA FOSC = 25 MHz, VCC=3.6 V
FOSC = 20 MHz, VCC=3.6 V
(tested with device held in reset,
inputs held in their inactive state)
IIDLE Idle Mo de Current 50
40 mA
mA FOSC = 25 MHz, VCC=3.6 V
FOSC = 20 MHz, VCC=3.6 V
IPD Powerd own Current 100 µA
CSPin Capacitance (any pi n to
VSS)10 pF Not tested
Intel386™ E X Embe dde d Micro pro cesso r
30 Datasheet
6.3 AC Specifications
Table 11 lists output delays, in put setup requirements , and input hold requirements f or the 5 V
EXTC pr ocessor; Table 12 i s for the EXTB process or. All AC specificati ons are relative to the
CLK2 rising edge crossing the VCC/2 level for the EXTB, or 2.0 Volts for the EXTC.
Fi gures 8 and 9 show the me asureme nt points for AC specifications for t he EXTB and EXTC
processors. Inputs must be driven to the indicated voltage levels w hen AC s pecifications are
me asured. Output dela ys a r e specified with mi nim um and maximum limits mea sured as shown.
The mi nimum del ay times a r e hold times provided to external circuitry. Input setup and hold time s
are spe cified as minim ums, defining the smallest acceptable sampling wi ndow. Within the
sa mpl ing window, a synchrono us input sig nal must be stable for correct operation.
Outputs ADS#, W/R#, CS5:0#, UCS#, D/C#, M/IO#, LOCK#, BHE#, BLE#, REFRESH#/CS6#,
READY#, LBA#, A25:1, HLDA a nd SMIACT# change only at the beginning of phase one. D15:0
( wr ite cycle s) and PWRDOWN change only at the beginning of phas e two. RD# and WR# change
to their active states at the be ginning of phase two. RD# changes to its inact ive state (end of cycle)
at t he begi nni ng of phas e one . See t he I ntel386 ™ EX Embedd ed Mic r oprocesso r User' s Manual for
a de tailed expla nation of early READY# vs. late READY#.
The READY#, HOLD, BUSY#, ER ROR#, PEREQ, BS8#, and D15:0 (read cycles) inputs are
sampled at the beginning of phase one. The NA#, SMI#, and NMI inputs are sampled at the
be g inning of p hase tw o.
Figure 8. Drive Levels and Measurem en t Points for AC Specifications (EXTC)
A
B
Tx
Valid
Output n+1
aa
cc
b
Min Max
CD
CLK2
OUTPUTS
(A25:1,BHE#
BLE#,ADS#,M/IO#
D/C#W/R#,LOCK#
HLDA, SMIACT#)
OUTPUTS
(D15:0)
INPUTS
(N/A#,INTR
NMI,SMI#)
INPUTS
(READY#,HOLD
FLT#,ERROR#
BUSY#,PEREQ
D15:0,A20)
LEGEND
a - V
CC
/2
b - 2.0V
c = 1.5V
A - Maximum Output Delay Spec
B - Minimum Output Delay Spec
C - Minimum Input Setup Spec
D - Minimum Input Hold Spec
PH1 PH2
3.0V
0V
Valid
Output n
A
B
Valid
Output n+1
aa
Min Max
Valid
Output n
Valid
Input
cc
CD
3.0V
0V
Valid
Input
Intel386™ E X Em bed ded Microp ro cesso r
Datasheet 31
Figure 9. Drive Levels and Measurement Poi nts for AC Specification s (EXTB)
A
B
Tx
Valid
Output n+1
aa
bb
a
Min Max
CD
CLK2
OUTPUTS
(A25:1,BHE#
BLE#,ADS#,M/IO#
D/C#W/R#,LOCK#
HLDA, SMIACT#)
OUTPUTS
(D15:0)
INPUTS
(N/A#,INTR
NMI,SMI#)
INPUTS
(READY#,HOLD
FLT#,ERROR#
BUSY#,PEREQ
D15:0,A20)
LEGEND
a - V
CC
/2
b = 1.5V
A - Maximum Output Delay Spec
B - Minimum Output Delay Spec
C - Minimum Input Setup Spec
D - Minimum Input Hold Spec
PH1 PH2
2.0V
0V
Valid
Output n
A
B
Valid
Output n+1
aa
Min Max
Valid
Output n
Valid
Input
bb
CD
2.0V
0V
Valid
Input
A2600-02
Intel386™ E X Embe dde d Micro pro cesso r
32 Datasheet
Table 11. 5-Volt AC Characteristics (Sheet 1 of 5)
Symbol Parameter
33 MHz 25 MHz
Test Condition
Min.
(ns) Max.
(ns) Min.
(ns) Max.
(ns)
Operating Frequency 0 33 0 25 one-half CLK2 frequency
in MHz (1)
t1CLK2 Period 15 20
t2a CLK2 High Time 6.25 7 (2)
t2b CLK2 High Time 4 4 (2)
t3a CLK2 Low Time 6.25 7 (2)
t3b CLK2 Low Time 4.5 5 (2)
t4CLK2 Fall Time 4 7 (2)
t5CLK2 Rise Time 4 7 (2)
t6A25:1 Valid Delay 4 21 4 24 CL = 50 pF
t7A25:1 Float Delay 4 28 4 28 (3)
t8BHE#, BLE#, LOCK# Valid Delay 4 21 4 24 CL = 50 pF
t8a SMIACT# Valid Delay 4 21 4 24 CL = 50 pF
t9BHE#, BLE#, LOCK# Float Delay 4 28 4 28 (3)
t10 M/IO#, D/C#, W/R#, ADS#,
REFRESH# Valid Delay 421424C
L = 50 pF
t10a RD #, WR# Valid Delay 4 18 4 22
t10b WR# Valid Delay for t he rising
edge with respect to phase two
(external late READY#) 4 28 4 28 (6)
t11 M/IO#, D/C#, W/R#, REFRESH#,
ADS# Float Delay 4 28 4 28 (3)
t12 D15 :0 Write Data Va li d D el ay 4 2 3 4 2 3 CL = 50 pF
t13 D15:0 Wri te Data Float delay 4 22 4 22 (3)
t14 HLDA Va li d Delay 4 1 8 4 22 CL = 50 pF
t15 NA# Setup Time 5 5
t16 NA# Hold Time 3 3
t19 READY# Setup Time 8 9
t19a BS8# Setup Time 11 11
NOTE:
1. Tested at maximum operating frequency and guaranteed by design characterization at lower operating
frequencies.
2. Thes e are no t test ed. The y are gua rante ed by charact eriza tion.
3. Float condition occurs when maximum output current becomes less than ILO in magnitude. Float delay is not
fully tested.
4. These inputs may be asynchronous to CLK2. The setu p and hold specif ications are given to ensure recognition
within a specific CLK2 period.
5. Thes e specifica tions ar e for information only and are not test ed. The y are intended t o assist the designer in
selecti ng memory spee ds. For each wait state in the design add two CLK2 cycles to the specificat ion.
6. This specif ication assumes th at READY # g oes active after the rising edge of phase 2, so t hat WR# goes
inactive as a result of READY# falling.
7. This specification assumes that READY# goes active before the rising edge of phase 2, so that WR# goes
inactive as a result of phas e 2 rising.
8. This specification applies if READY# is generated internally.
Intel386™ E X Em bed ded Microp ro cesso r
Datasheet 33
t20 READY#, BS8# Hold Time 4 4
t21 D15:0 Read Setup Time 7 7
t22 D15:0 Read Hold Time 4 4
t23 HOLD Setup Time 8 8
t24 HOLD Hold Ti me 3 3
t25 RESET Setup Time 5 5
t26 RESET Hold Time 2 3
t27 NMI Setup Time 6 6 (4)
t27a SMI# Setup Time 6 6 (4)
t28 NMI Hold Time 6 6 (4)
t28a SMI# Hold Time 6 6 (4)
t29 PEREQ, ERROR#, BUSY# Setup
Time 6 6 (4)
t30 PEREQ, ERROR#, BUSY# Hold
Time 5 5 (4)
t31 READY# Valid Delay 4 24 4 26 CL = 30 pF
t32 READ Y# Float Delay 4 34 4 3 4
t33 LB A# Va li d D ela y 4 20 4 22
t34 CS6:0#, UCS# Valid Delay 4 24 ( 25 i n
SMM) 430C
L = 30 pF
t35 CLKOUT Valid Delay 2 9 2 14 CL = 30 pF
t36 PWRDOWN Valid Delay 4 15 4 18
t41 A25:1, BH E#, BLE# Valid to WR#
Low 00
t41a UCS#, CS6:0# Valid to WR# Low 0 0
t42 A25:1, BHE#, BLE# Hold After
WR# High 0 0 (6)
t42a UCS#, CS6: 0# Hold after WR #
High 00
t42b A25:1. BHE#, BLE# Hold After
WR# High 10 10 (7, 8)
Table 11. 5-Volt AC Characteristics (Sheet 2 o f 5)
Symbol Parameter
33 MHz 25 MHz
Test Con diti on
Min.
(ns) Max.
(ns) Min.
(ns) Max.
(ns)
NOTE:
1. Tested at maximum operating frequency and guaranteed by design characterization at lower operating
frequencies.
2. Th ese are not teste d. They are guaranteed by characte rizat ion.
3. Float con dition occurs when maximum output curren t becomes less than ILO in ma gnitud e. Flo at delay is not
fully tested.
4. Th ese inputs may be asynchr onous to CLK2. The setup and hold speci fications are given to ensure recog nition
within a specific CLK2 period.
5. Th ese specific ations are for information only and are not tested. Th ey are intended to assist the designer in
selectin g memory s peeds. For each wait state in the design add two CLK 2 cycles to the specification.
6. Th is specification assumes that READY# goes act ive aft er the risin g edge of phase 2, so that WR# goes
inactive as a result of READY# falling.
7. Th is specification assumes that READY# goes act ive before the rising edge of phase 2, so tha t WR# goes
inactive as a result of phase 2 rising.
8. Th is specification applies if READ Y# is generated internally.
Intel386™ E X Embe dde d Micro pro cesso r
34 Datasheet
t43 D15:0 Output Vali d to WR# H igh 2CLK2
–10 2CLK2
– 10 (5)
t44 D15:0 Output Hold After WR# High CLK2
–10 CLK2
–10
t45 WR# High to D15:0 Float CLK2
+ 1 0 CLK2
+ 1 0 (3)
t46 WR# Pulse Width 2CLK2
–10 2CLK2
–10 (7)
t47 A25:1, BHE#, BLE# V alid to D15:0
Valid 4C LK2 -
28 4CLK2-
31 (5)
t47a UCS#, CS6:0# Valid to D15-D0
Valid 4C LK2 -
31 4C LK2 -
35 (5)
t48 RD# Low to D15:0 Input Valid 3CLK2 –
25 3CLK2 –
29 (5)
t49 D15:0 Hold After RD# High 0 0
t50 RD# High to D15:0 Float CLK2 CLK2 (3)
t51 A25:1, BHE#, BLE# Hold After
RD# High 00
t51a UCS#, CS6:0# Hol d after RD#
High 00
t52 RD # Pulse Width 3CLK2
–10 3CLK2
–10
Synchronous Serial I/O (SSIO) Unit
t100 STXCLK, SRXCLK Frequency
(Master Mode ) CLK2/8 CLK2/8 (Unit is MHz)
t101 STXCLK, SRXCLK Frequency
(Slave Mode) CLK2/8 CLK2/8 (Unit is MHz)
t102 STXCLK, SRXCLK Low Time 7CLK2/2 7CLK2/2 (2)
t103 STXCLK, SRXCLK High Time 7CLK2/2 7CLK2/2 (2)
t104 STXCLK Low to SSIOTX Delay 3CLK2 3CLK2
t105 SSIORX to SRXCLK High Setup
Time 0 0 (2)
t106 SSIORX from SRXCLK Hold Time 3CLK2 3CLK2
Table 11. 5-Volt AC Characteristics (Sheet 3 of 5)
Symbol Parameter
33 MHz 25 MHz
Test Condition
Min.
(ns) Max.
(ns) Min.
(ns) Max.
(ns)
NOTE:
1. Tested at maximum operating frequency and guaranteed by design characterization at lower operating
frequencies.
2. Thes e are no t test ed. The y are gua rante ed by charact eriza tion.
3. Float condition occurs when maximum output current becomes less than ILO in magnitude. Float delay is not
fully tested.
4. These inputs may be asynchronous to CLK2. The setu p and hold specif ications are given to ensure recognition
within a specific CLK2 period.
5. Thes e specifica tions ar e for information only and are not test ed. The y are intended t o assist the designer in
selecti ng memory spee ds. For each wait state in the design add two CLK2 cycles to the specificat ion.
6. This specif ication assumes th at READY # g oes active after the rising edge of phase 2, so t hat WR# goes
inactive as a result of READY# falling.
7. This specification assumes that READY# goes active before the rising edge of phase 2, so that WR# goes
inactive as a result of phas e 2 rising.
8. This specification applies if READY# is generated internally.
Intel386™ E X Em bed ded Microp ro cesso r
Datasheet 35
Timer Control Unit (TCU) Inputs
t107 TMRCLK
n
Frequenc y 8 8 (Unit is MHz)
t108 TMRCLK
n
Low 60 60
t109 TMRCLK
n
Hig h 60 60
t110 TMRGATE
n
High Width 50 50
t111 TMRGATE
n
Low Width 5 0 50
t112 TMRGATE
n
to TMRCLK Setup
Time (exter nal TMRCLK only) 10 10
t112a TMRGATE
n
to TMRCLK Hold
Time (exter nal TMRCLK only) 11 11
Timer Control Unit (TCU) Outputs
t113 TMRGATE
n
Low to TMROUT
Valid 29 32
t114 TMRCLK
n
Low to TMROUT Valid 29 32
Interrupt Control Unit (ICU) Inputs
t115 D7:0 Setup Ti me
(INTA# Cycle 2) 77
t116 D7:0 Hold Time
(INTA# Cycle 2) 44
Inter rupt Control Unit (ICU) Outputs
t117 CLK2 High to CAS2:0 Valid 25 28
DMA Unit Inputs
t118 DREQ Setup Time
(Sync Mode) 15 15
t119 DREQ Hold Time
(Sync Mode) 4 4 (2)
t120 DREQ Setup Time
(Async Mode) 99
t121 DREQ Hold Time
(Async Mode) 9 9 (2)
Table 11. 5-Volt AC Characteristics (Sheet 4 o f 5)
Symbol Parameter
33 MHz 25 MHz
Test Con diti on
Min.
(ns) Max.
(ns) Min.
(ns) Max.
(ns)
NOTE:
1. Tested at maximum operating frequency and guaranteed by design characterization at lower operating
frequencies.
2. Th ese are not teste d. They are guaranteed by characte rizat ion.
3. Float con dition occurs when maximum output curren t becomes less than ILO in ma gnitud e. Flo at delay is not
fully tested.
4. Th ese inputs may be asynchr onous to CLK2. The setup and hold speci fications are given to ensure recog nition
within a specific CLK2 period.
5. Th ese specific ations are for information only and are not tested. Th ey are intended to assist the designer in
selectin g memory s peeds. For each wait state in the design add two CLK 2 cycles to the specification.
6. Th is specification assumes that READY# goes act ive aft er the risin g edge of phase 2, so that WR# goes
inactive as a result of READY# falling.
7. Th is specification assumes that READY# goes act ive before the rising edge of phase 2, so tha t WR# goes
inactive as a result of phase 2 rising.
8. Th is specification applies if READ Y# is generated internally.
Intel386™ E X Embe dde d Micro pro cesso r
36 Datasheet
t122 EOP# Setup Tim e
(S ync Mode) 15 15
t123 EOP# Hold Ti me
(S ync Mode) 44
t124 EOP# Setup Tim e
(Asy nc Mo de ) 99
t125 EOP# Hold Ti me
(Asy nc Mo de ) 99
DMA Unit Outputs
t126 DACK# Output Valid Delay 4 21 4 25
t127 EOP# Active Delay 4 2 5 4 25
t128 EOP# Float Delay 4 2 5 4 25 (3)
JTAG Tes t-log ic U nit
t129 TCK Frequency 10 10 (Unit is MHz)
Table 11. 5-Volt AC Characteristics (Sheet 5 of 5)
Symbol Parameter
33 MHz 25 MHz
Test Condition
Min.
(ns) Max.
(ns) Min.
(ns) Max.
(ns)
NOTE:
1. Tested at maximum operating frequency and guaranteed by design characterization at lower operating
frequencies.
2. Thes e are no t test ed. The y are gua rante ed by charact eriza tion.
3. Float condition occurs when maximum output current becomes less than ILO in magnitude. Float delay is not
fully tested.
4. These inputs may be asynchronous to CLK2. The setu p and hold specif ications are given to ensure recognition
within a specific CLK2 period.
5. Thes e specifica tions ar e for information only and are not test ed. The y are intended t o assist the designer in
selecti ng memory spee ds. For each wait state in the design add two CLK2 cycles to the specificat ion.
6. This specif ication assumes th at READY # g oes active after the rising edge of phase 2, so t hat WR# goes
inactive as a result of READY# falling.
7. This specification assumes that READY# goes active before the rising edge of phase 2, so that WR# goes
inactive as a result of phas e 2 rising.
8. This specification applies if READY# is generated internally.
Intel386™ E X Em bed ded Microp ro cesso r
Datasheet 37
Table 12. 3-Volt AC Characteristics (Sheet 1 of 5)
Symbol Parameter
25 MHz
3.0 V to 3.6 V 20 MHz
2.7 V to 3.6 V Test Condition
Min.
(ns) Max.
(ns) Min.
(ns) Max.
(ns)
Operating Frequency 0 25 0 20 one-half CLK2 frequency
in MHz(1)
t1CLK2 Peri od 20 25
t2a CLK2 High Time 7 8 (2)
t2b CLK2 High Time 4 5 (2)
t3a CLK2 Low Time 7 8 (2)
t3b CLK2 Low Time 5 6 (2)
t4CLK2 Fall Time 7 8 (2)
t5CLK2 Rise Time 7 8 (2)
t6A25:1 Valid Delay 4 32 4 36 CL = 50 pF
t7A25:1 Float Delay 4 29 4 36 (3)
t8BHE#, BLE#, LO CK# Valid
Delay 432434C
L = 50 pF
t8a SMIACT# Valid Delay 4 32 4 34 CL = 50 pF
t9BHE#, BLE#, LOCK# Float
Delay 423432(3)
t10 M/IO#, D/C#, W/R#, ADS#,
REFRESH# Valid Delay 432434C
L = 50 pF
t10a RD#, WR# Valid Delay 4 30 4 32
t10b WR# Vali d De la y for the ri sing
edge with respect to phase
two (external late READY#) 437437(6)
t11 M/IO#, D/C#, W/R#,
REFRESH#, ADS# Float
Delay 430434(3)
t12 D15:0 Write Data Va lid Delay 4 31 4 34 CL = 50 pF
t13 D15:0 Write Data Float de lay 4 20 4 28 (3)
t14 HLDA Vali d Delay 4 30 4 32 CL = 50 pF
t15 NA# Setup Time 9 9
t16 NA# Hold Time 12 15
NOTE:
1. Tested at maximum operating frequenc y and guarantee d by design characterizati on at lo wer operating
frequencies.
2. These are not tested. They are guaranteed by characterization.
3. Float conditio n occur s when maxi mum output current bec omes less than ILO in magnitude. Float delay is not
fully tested.
4. These inpu ts may be as ynchronous to CLK2. The setup and hol d specif ications are giv en t o e nsure
recognition withi n a specific CLK2 period.
5. These specifications are for information only and are no t tested. They are inte nded to assist the designer in
selecting memory speeds. For each wait state in the design add two CLK2 cycles to the specification.
6. This specification assumes that REA DY# goes active aft er the rising edge of phase 2, so that WR# goes
inactive as a result of READY# falling.
7. This specification assumes that READY# goes active before the rising edge of phase 2, so that WR# goes
inactive as a result of phase 2 rising.
8. This specifica tion applies if READY# i s gener ated internally.
Intel386™ E X Embe dde d Micro pro cesso r
38 Datasheet
t19 READY# Setup Time 15 17
t19a BS8# Setup Time 17 19
t20 READY#, BS8# Hold Time 4 4
t21 D15:0 Read Setup Time 9 11
t22 D15:0 Read Hold Time 6 6
t23 HOLD Setup Time 17 22
t24 HOLD Hold Tim e 5 5
t25 RESET Setup Time 12 13
t26 RESET Hold T ime 4 4
t27 NMI Setup Time 16 16 (4)
t27a SM I# Setup Tim e 1 6 16 (4)
t28 NMI Hold Time 1 6 16 (4)
t28a SMI# Hold Time 16 1 6 (4)
t29 PEREQ, ERROR#, BUSY#
Setup Time 14 16 (4)
t30 PEREQ, ERROR#, BUSY#
Hold Time 5 5 (4)
t31 READY# Valid Delay 4 33 4 42 CL = 30 pF
t32 READY# Float Delay 4 33 4 42
t33 LBA# Valid Delay 4 31 4 40
t34 CS6:0#, UCS# Valid Delay 4 33 (34 in
SMM) 442C
L = 30 pF
t35 CLKOUT Valid Delay 4 14 4 18 CL = 30 pF
t36 PWRD OWN Valid Delay 4 26 4 29
t41 A25:1, BHE#, BLE# Valid to
WR# Low 00
t41a UCS#, CS6:0# Valid to WR#
Low 00
t42 A25:1, BHE#, BLE# Hold
After WR# High 0 0 (6)
Table 12. 3-Volt AC Characteristics (Sheet 2 of 5)
Symbol Parameter
25 MHz
3.0 V to 3.6 V 20 MHz
2.7 V to 3.6 V Tes t Condition
Min.
(ns) Max.
(ns) Min.
(ns) Max.
(ns)
NOTE:
1. Tested at maximum operating frequency and guaranteed by design characterization at lower operating
frequencies.
2. Th ese are not teste d. They are guaranteed by characte rizat ion.
3. Float condition occurs when maximum output current becomes less than ILO in magn itude. Float delay is not
fully tested.
4. Th ese inputs may be asynchronous to CLK2. The set up and hold specific ations are given to ensur e
recognition within a specific CLK2 period.
5. These specifications are for information only and are not tested. They are intended to assist the designer in
selectin g memory s peeds. For each wait state in the design add two CLK 2 cycles to the specification.
6. Th is specification assumes that READY# goes act ive aft er the risin g edge of phase 2, so that WR# goes
inactive as a result of READY# falling.
7. Th is specification assumes that READY# goes act ive before the rising edge of phase 2, so tha t WR# goes
inactive as a result of phase 2 rising.
8. Th is specification applies if READ Y# is generated internally.
Intel386™ E X Em bed ded Microp ro cesso r
Datasheet 39
t42a UCS#, CS6: 0# Hold after
WR# High 00
t42b A25:1. BHE#, BLE# Hold
After WR# High 1 0 10 ( 7 , 8)
t43 D15:0 Output Valid to WR#
High 2CLK2
– 10 2CLK2
– 10 (5)
t44 D15:0 Output Hold After WR#
High CLK2
–10 CL K2
–10
t45 WR# High to D15:0 Float CLK2
+ 10 CLK2
+10 (3)
t46 WR# Pulse Wid th 2CLK2
–10 2CLK2
–10 (7)
t47 A25:1, BHE#, BLE# Valid to
D15:0 Valid 4CLK2-
41 4CLK2
- 45 (5)
t47a UCS#, CS6:0# Va lid to D15-
D0 Vali d 4CLK2 -
42 4CLK2
- 53 (5)
t48 RD# Low to D15:0 Input Valid 3CLK2 –
39 3CLK2
– 43 (5)
t49 D15:0 Hold After RD# High 0 0
t50 RD# High to D15:0 Float CLK2 CL K2 (3)
t51 A25:1, BHE#, BLE# Hold
After RD# High 00
t51a UCS#, CS6: 0# Hold after
RD# High 00
t52 RD# Pulse Width 3CLK2
–13 3CLK2
–15
Synchronous Serial I/O (SSIO) Unit
t100 STXCLK, SRXCLK
Frequency (Master Mode) CLK2/8 CLK2/8 (Unit is MHz)
t101 STXCLK, SRXCLK
Frequency (Slave Mode) CLK2/8 CLK2/8 (Unit is MHz)
t102 STXCLK, SRXCLK Low T ime 7CLK2/
27CLK2/
2(2)
Table 12. 3-Volt AC Characteristics (Sheet 3 of 5)
Symbol Parameter
25 MHz
3.0 V to 3.6 V 20 MHz
2.7 V to 3.6 V Test Condition
Min.
(ns) Max.
(ns) Min.
(ns) Max.
(ns)
NOTE:
1. Tested at maximum operating frequenc y and guarantee d by design characterizati on at lo wer operating
frequencies.
2. These are not tested. They are guaranteed by characterization.
3. Float conditio n occur s when maxi mum output current bec omes less than ILO in magnitude. Float delay is not
fully tested.
4. These inpu ts may be as ynchronous to CLK2. The setup and hol d specif ications are giv en t o e nsure
recognition withi n a specific CLK2 period.
5. These specifications are for information only and are no t tested. They are inte nded to assist the designer in
selecting memory speeds. For each wait state in the design add two CLK2 cycles to the specification.
6. This specification assumes that REA DY# goes active aft er the rising edge of phase 2, so that WR# goes
inactive as a result of READY# falling.
7. This specification assumes that READY# goes active before the rising edge of phase 2, so that WR# goes
inactive as a result of phase 2 rising.
8. This specifica tion applies if READY# i s gener ated internally.
Intel386™ E X Embe dde d Micro pro cesso r
40 Datasheet
t103 STXCLK, SRXCLK High Time 7CLK2/
27CLK2/
2(2)
t104 STXCLK Low to SSIOTX
Delay 3CLK2 3CLK2
t105 SSIORX to SRXCLK High
Setup Time 0 0 (2)
t106 SSIORX from SRXCLK Hold
Time 3CLK2 3CLK2
Timer Control Unit (TCU) Inputs
t107 TMRCLK
n
Frequency 8 8 (Unit is MHz)
t108 TMRCLK
n
Low 60 60
t109 TMRCLK
n
High 60 60
t110 TMRGATE
n
High Width 50 50
t111 TMRGATE
n
Low Width 50 50
t112 TMRGATE
n
to TMRCLK
Setup Time (ex ternal
TMRCLK only) 10 15
t112a TMRGATE
n
to TMRCLK Hold
Time (ex te rnal TM RC LK only) 19 19
Timer Control Unit (TCU) Outputs
t113 TMRGATE
n
Lo w to TMROUT
Valid 44 52
t114 TMRCLK
n
Low to TMROUT
Valid 48 52
Table 12. 3-Volt AC Characteristics (Sheet 4 of 5)
Symbol Parameter
25 MHz
3.0 V to 3.6 V 20 MHz
2.7 V to 3.6 V Tes t Condition
Min.
(ns) Max.
(ns) Min.
(ns) Max.
(ns)
NOTE:
1. Tested at maximum operating frequency and guaranteed by design characterization at lower operating
frequencies.
2. Th ese are not teste d. They are guaranteed by characte rizat ion.
3. Float condition occurs when maximum output current becomes less than ILO in magn itude. Float delay is not
fully tested.
4. Th ese inputs may be asynchronous to CLK2. The set up and hold specific ations are given to ensur e
recognition within a specific CLK2 period.
5. These specifications are for information only and are not tested. They are intended to assist the designer in
selectin g memory s peeds. For each wait state in the design add two CLK 2 cycles to the specification.
6. Th is specification assumes that READY# goes act ive aft er the risin g edge of phase 2, so that WR# goes
inactive as a result of READY# falling.
7. Th is specification assumes that READY# goes act ive before the rising edge of phase 2, so tha t WR# goes
inactive as a result of phase 2 rising.
8. Th is specification applies if READ Y# is generated internally.
Intel386™ E X Em bed ded Microp ro cesso r
Datasheet 41
Interrupt Control Unit (ICU) Inputs
t115 D7:0 Setup Time
(INTA# Cycle 2) 911
t116 D7:0 Hold Time
(INTA# Cycle 2) 66
Interrupt Control Unit (ICU) Outputs
t117 CLK2 High to CAS2:0 V alid 36 46
DMA Unit Inp uts
t118 DREQ Setup Ti me
(Sync Mode) 19 21
t119 DREQ Hold Tim e
(Sync Mode) 4 4 (2)
t120 DREQ Setup Time
(A sync Mode) 11 11
t121 DREQ Hold Time
(A sync Mode) 11 11 (2)
t122 EOP# Setup Time
(Sync Mode) 17 21
t123 EOP# Hold Ti me
(Sync Mode) 44
t124 EOP# Setup Time
(A sync Mode) 11 11
t125 EOP# Hold Ti me
(A sync Mode) 11 11
DMA Unit Outputs
t126 DACK# Output Valid Delay 4 31 4 33
t127 EOP# Active Delay 4 27 4 33
t128 EOP# Float Delay 4 27 4 33 (3)
JTAG Test-logic Unit
t129 TCK Frequency 10 10 ( Unit is MHz)
Table 12. 3-Volt AC Characteristics (Sheet 5 of 5)
Symbol Parameter
25 MHz
3.0 V to 3.6 V 20 MHz
2.7 V to 3.6 V Test Condition
Min.
(ns) Max.
(ns) Min.
(ns) Max.
(ns)
NOTE:
1. Tested at maximum operating frequenc y and guarantee d by design characterizati on at lo wer operating
frequencies.
2. These are not tested. They are guaranteed by characterization.
3. Float conditio n occur s when maxi mum output current bec omes less than ILO in magnitude. Float delay is not
fully tested.
4. These inpu ts may be as ynchronous to CLK2. The setup and hol d specif ications are giv en t o e nsure
recognition withi n a specific CLK2 period.
5. These specifications are for information only and are no t tested. They are inte nded to assist the designer in
selecting memory speeds. For each wait state in the design add two CLK2 cycles to the specification.
6. This specification assumes that REA DY# goes active aft er the rising edge of phase 2, so that WR# goes
inactive as a result of READY# falling.
7. This specification assumes that READY# goes active before the rising edge of phase 2, so that WR# goes
inactive as a result of phase 2 rising.
8. This specifica tion applies if READY# i s gener ated internally.
Intel386™ E X Embe dde d Micro pro cesso r
42 Datasheet
Figure 10. AC Test Lo ads
Figure 11. CLK2 Waveform
CPU Output
CL
CLK2
t4
A
B
C
A = Vcc – 0.8 for Vcc = 4.5 – 5.5, Vcc – 0.6 for Vcc = 2.7 – 3.6
B = Vcc/2
C = 0.8V
t3b
t3a
t1
t2a
t2b
t5
Intel386™ E X Em bed ded Microp ro cesso r
Datasheet 43
Figure 12. AC Timing Waveforms — Input Setup and Hold Ti ming
A2736-01
CLK2
TX TX TX
READY# (Input)
BS8#
DREQ
EOP# (Input)
HOLD
D15:0
(Input)
BUSY#
ERROR#
PEREQ
NA#
NMI
SMI#
PH2 PH1 PH2 PH1
t19 t20
t23 t24
t21 t22
t29 t30
t15 t16
t27 t28
t27a t28a
t19a, t118, t120
t122, t124 t119, t121
t123, t125
t115 t116
Intel386™ E X Embe dde d Micro pro cesso r
44 Datasheet
Figu re 13. AC Timing Waveforms — Ou tput Va lid Delay Timing
Figure 14. AC Timi ng Waveforms — Ou tput Va lid Delay Timing for
External Late READY#
CLK2
TX TX TX
BHE#, BLE#
LOCK#, SMIACT#
W/R#, M/IO#, D/C#
ADS#,REFRESH#
LBA#, DACK#
EOP# (Output)
READY# (Output)
A25:1, CS6:0#,UCS#,
RD# Inactive
D15:0, CAS2:0
RD#, WR# Active,
WR# Inactive
(early READY#)
PH2 PH1 PH2 PH1
Min
Valid n+1
Valid n
Max
Min
Valid n+1
Valid n
Max
Min
Valid n+1
Valid n
Max
Min
Valid n+1
Max
Valid n
HLDA
t8, t8a
t10, t31, t33
t126, t127
t10a, t6, t34
t117, t10a, t12
A2737-01
CLK2
ADS#
External
READY#
WR#
T1 T2 T1
A4398-01
t10b
Intel386™ E X Em bed ded Microp ro cesso r
Datasheet 45
Figure 15. AC Ti min g Waveforms — Output Float Delay and HLDA Valid Delay Timing
Figure 16. AC Timing Waveforms — RESET Setup and Hold Timing and Internal Phase
CLK2
TI or T1
BHE#, BLE#
LOCK#
W/R#, M/IO#
D/C#, ADS#
REFRESH#
READY# (Output)
A25:1
D15:0
PH2 PH1 PH2 PH1
Min Max
HLDA
PH2
Th
Min Max
(High Z)
Min Max Min Max
(High Z)
Min Max Min Max
(High Z)
Min Max Min Max
(High Z)
t13 Also applies to data float when write
cycle is followed by read or idle.
Min Max Min Max
t8
t10
t6
t32, t11
t7
t9
t13
t14 t14
t12
A2738-01
CLK2
RESET
PH2 PH1PH2 or PH1 PH2 or PH1
Reset Initialization Sequence
t26
t25
Intel386™ E X Embe dde d Micro pro cesso r
46 Datasheet
Figu re 17. AC Timing Waveforms — Rel ative Signal Timi ng
Figure 18. AC Timi ng Waveforms — S SIO Timing
Figure 19. AC Ti m ing Waveforms — Timer/Counte r Timing
A2705-01
D15:0 (In)
WR#
A25:1, BLE#, BHE#
PH2
CLK2
t47 t47a
t49
t42a
t46
T1 T2 Ti
UCS#, CS6:0#
D15:0 (Out)
RD# t52
t41
t41a t42
t43 t45
t44
t51a
t51
t48 t50
A2712-01
SSIORX
t104
STXCLK t102 t100, t101 t103
t105 t106
SSIOTX
SRXCLK t102 t100, t101 t103
Valid TX Data
Valid RX Data
TMROUT t113
TMRCLK
t109 t107 t108
TMRGATE
t111 t110
t114
t112at112
Intel386™ E X Em bed ded Microp ro cesso r
Datasheet 47
7.0 Bus Cycle Waveforms
Fig ures 20 through 30 present various bus cyc les t hat are ge nerated by the processor. What is
shown in the figure is th e rel ationshi p of the va ri ous bus sign als to CLK2. T hese figur es alo ng with
the information present in AC Specifications allow the user to determine critical timing analysis for
a give n application.
Figure 20. Basic Internal and External Bus Cycl es
State
A25:1, BHE#
BLE#, D/C#
M/IO#
W/R#
ADS#
NA#
D15:0
RD#
WR#
BS8#
LOCK#
T1 T2 T1 T2 T1 T2 Ti T1 T2
Cycle 1
Nonpipelined
External
(Write)
[Late Ready]
Cycle 2
Nonpipelined
Internal
(Read)
Cycle 3
Nonpipelined
Internal
(Write)
[Early Ready]
Cycle 4
Nonpipelined
External
(Read)
REFRESH#
LBA#
CLK2
CLKOUT
Valid 1 Valid 2 Valid 3
Out 1
Valid 1 Valid 2 Valid 3
In
2Out 3 In
4
Idle
Cycle
Idle
Cycle Idle
Cycle
Ti Ti
End Cycle 1 End Cycle 2 End Cycle 3
READY#
End Cycle 4
Valid 4
Valid 4
A2486-03
Intel386™ E X Embe dde d Micro pro cesso r
48 Datasheet
Figure 21. Nonpipelined Address Read Cycles
A2487-03
LOCK#
D15:0
CLK2
BHE#, BLE#, A25:1
M/IO#, D/C# Valid1
RD#
READY#
Ti T1 T2 T1 T2 T2 Ti
Cycle 1
Non-pipelined
External
(Read)
Cycle 2
Non-pipelined
External
(Read)
Idle
CLKOUT
Idle
ADS#
NA#
REFRESH#
W/R#
End Cycle End Cycle
In1 In2
WR#
LBA#
BS8#
Valid2
Valid1 Valid2
Intel386™ E X Em bed ded Microp ro cesso r
Datasheet 49
Figure 22. P ipeli ned Address Cycle
A2477-03
LOCK#
D15:0
Valid 2 Valid 3 Valid 4
CLK2
BHE#, BLE#, A25:1,
M/IO#, D/C# Valid3 Valid4
Valid2
Valid1
W/R#
ADS#
NA#
T1P T2P T2P T1P T2 T2P T1P T2i T2P T1P
Cycle 1
Pipelined
(Write)
[Late Ready]
Cycle 2
Non-pipelined
(Read)
Cycle 3
Pipelined
(Write)
[Late Ready]
Cycle 4
Pipelined
(Read)
CLKOUT
ADS# is asserted as
soon as the CPU has
another bus cycle to
perform, which is not
always immediately
after NA# is asserted.
As long as the CPU enters the T2P
state during Cycle 3, address
pipelining is maintained in Cycle 4.
Note ADS# is
asserted in
every T2P state.
In
2
Asserting NA# more
than once during
any cycle has no
additional effects
NA# could have been asserted in T1P
if desired. Assertion now is the latest
time possible to allow the CPU to enter
T2P state to maintain pipelining in cycle 3.
READY#
RD#
WR#
LBA#
BS8#
Out 1
Out
Valid 1
Out 3
T2
Intel386™ E X Embe dde d Micro pro cesso r
50 Datasheet
Figure 23. 16-bit Cycles to 8-bit Devices (using BS8#)
State
A25:1
M/IO#
D/C#
W/R#
BHE#
ADS#
NA#
D15:8
RD#
WR#
BS8#
READY#
LOCK#
Low Byte
Write
[Late Ready]
High Byte
Write
[Late Ready]
Low Byte
Read High Byte
Read
T1 T2 T1 T2 T1 T2 T1 T2 Ti
Idle
Cycles
Ti
BLE#
D7:0
Must be high
CLK2
CLKOUT
A3375-01
Data Out High
Data Out
Low Data Out
High
Data
In
High
Data
In
Low
Valid 1 Valid 2
Valid 1 Valid 2
Intel386™ E X Em bed ded Microp ro cesso r
Datasheet 51
Figure 24. Basic External Bus Cycles
State
A25:1, BHE#
BLE#, D/C#
M/IO#
W/R#
ADS#
NA#
D15:0
RD#
WR#
BS8#
READY#
LOCK#
T1 T2 T1 T2 Ti T1 T2 T1 T2
A2305-02
Cycle 1
Nonpipelined
External
(Write)
[Late Ready]
Cycle 2
Nonpipelined
External
(Read)
Cycle 3
Nonpipelined
External
(Write)
[Late Ready]
Cycle 4
Nonpipelined
External
(Read)
Idle
Cycle
REFRESH#
LBA#
CLK2
CLKOUT
Valid 1 Valid 2 Valid 3
Out 1 In 2 Out 3 In 4
Valid 1 Valid 2 Valid 3 Valid 4
Valid 4
Intel386™ E X Embe dde d Micro pro cesso r
52 Datasheet
Figure 25. Nonpipelined Address Write Cycles
A2488-02
LOCK#
D15:0
CLK2
BHE#, BLE#, A25:1
M/IO#, D/C#
RD#
READY#
Ti T1 T2 T1 T2 T2 Ti
Cycle 1
Nonpipelined
External
(Write)
[Late Ready]
Cycle 2
Nonpipelined
External
(Write)
[Early Ready]
Idle
CLKOUT
Idle
ADS#
NA#
REFRESH#
W/R#
End Cycle 1 End Cycle 2
WR#
LBA#
Valid 2
Valid 1
BS8#
Valid2
Valid1
Out 2
Out 1
Intel386™ E X Em bed ded Microp ro cesso r
Datasheet 53
Figure 26. Halt Cycle
A2492-02
LOCK#
D15:0
CLK2
BHE#, A1, M/IO#, W/R#
RD#
READY#
T1 T2 T1 T2 Ti Ti Ti Ti
Cycle 1
Nonpipelined
(Write)
[Late Ready]
CLKOUT
Cycle 2
Nonpipelined
(Halt)
ADS#
NA#
A25:2, BLE#, D/C#
WR#
LBA#
Idle
Float
Valid 1
CPU remains halted until INTR, SMI#,
NMI, or RESET is asserted.
CPU responds to HOLD input
while in the HALT state.
HALT cycle must be acknowledged by READY# asserted. This READY# could be
generated internally or externally.
Valid 2
†
†
Out Undefined
Valid 1
Valid 1
Intel386™ E X Embe dde d Micro pro cesso r
54 Datasheet
Figure 27. Basic Refresh Cycle
A2491-02
LOCK#
D15:0
CLK2
UCS#, CS6:0#,
BHE#, BLE#
M/IO#, D/C# Valid 1
RD#
READY#
Ti T1 T2 Ti T1 T2 T2 Ti Ti T1
Cycle 1
Nonpipelined
External
(Read)
Cycle 2
Refresh
CLKOUT
Idle Idle Cycle 3
Nonpipelined
External
(Write)
[Late Ready]
T2
Valid 3
ADS#
NA#
A25:1
W/R#
WR#
LBA#
Idle
REFRESH#
Float
HOLD
HLDA
In Out
Valid 1 Valid 2
Valid 1 Valid 2 Valid 3
Intel386™ E X Em bed ded Microp ro cesso r
Datasheet 55
Figure 28. Refresh Cycle During HOLD/HL D A
A2493-02
D15:0
HOLD
CLK2
BHE#, BLE#
M/IO#, D/C# Floating
Floating
RD#
READY#
Ti Th Th Th Ti T1 T2 Ti Ti Th
HOLD
Acknowledge Cycle 1
Refresh
CLKOUT
Idle Idle Idle
Th
ADS#
NA#
REFRESH#
W/R#
WR#
LBA#
LOCK#
HOLD
Acknowledge
A25:1
HLDA
Floating
Due to refresh pending.
Floating Floating
Floating Floating
Floating
Floating
Floating
Floating
Floating
Floating
Valid 1
Intel386™ E X Embe dde d Micro pro cesso r
56 Datasheet
Figu re 29. L OC K # S ig nal Du ri ng Ad dress Pipel in in g
Figure 30. Interr upt Acknow ledge Cycl es
A2489-02
LOCK#
CLKOUT
Unlocked
Bus Cycle Locked
Bus Cycle Locked
Bus Cycle
BLE#, BHE#, A25:1
Unlocked
Bus Cycle
LOCK Deasserted
Address Asserted
READY#
A2490-03
CLK2
BHE#
BLE#, A25:19,
CAS2:0,A15:3, A1
M/IO#, D/C#, W/R#
LBA#
LOCK#
T2 T1 T2 Ti Ti Ti Ti T1 T2 Ti
Interrupt
Acknowledge
Cycle 1
(Internal)
Idle
(Four bus states) Idle
CLKOUT
RD#
A2
Ti
Previous
Cycle Interrupt
Acknowledge
Cycle 2
(Internal)
ADS#
READY#
WR#
