LMK040XX-REV3 EVALUATION BOARD OPERATING INSTRUCTIONS
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LMK04000 Family
Precision Clock Conditioner with Dual PLLs and Integrated VCO
Evaluation Board Operating Instructions for rev3 PCBs
2011-08-23
LMK04000BEVAL
LMK04000BEVAL-XO
LMK04031BEVAL
LMK04031BEVAL-XO
LMK04002BEVAL
LMK04033BEVAL
National Semiconductor Corporation
Interface Division
Precision Timing Devices
LMK040XX-REV3 EVALUATION BOARD OPERATING INSTRUCTIONS
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Table of Contents
TABLE OF CONTENTS ....................................................................................................................... 2
GENERAL DESCRIPTION ................................................................................................................... 4
Evaluation Board Kit Contents ................................................................................................................................... 4
Available Evaluation Boards ...................................................................................................................................... 4
Available LMK04000 Family NSIDs ......................................................................................................................... 5
QUICK START ................................................................................................................................... 6
Default CodeLoader modes for evaluation boards ..................................................................................................... 7
USING CODELOADER TO PROGRAM THE LMK040XXB ................................................................... 8
1. Start CodeLoader 4 Application ............................................................................................................................. 8
2. Select Device .......................................................................................................................................................... 8
3. Program/Load Device ............................................................................................................................................. 9
4. Restoring a Default Mode ...................................................................................................................................... 9
5. Visual Confirmation of Frequency Lock .............................................................................................................. 10
6. Enable Fout........................................................................................................................................................... 10
7. Enable Clock Outputs ........................................................................................................................................... 11
PLL LOOP FILTERS AND LOOP PARAMETERS ................................................................................. 12
PLL 1 Loop Filter ..................................................................................................................................................... 12
122.88 MHz VCXO option ................................................................................................... 12
12.288 MHz Crystal (-XO) option ........................................................................................ 12
PLL2 Loop Filter ...................................................................................................................................................... 13
122.88 MHz VCXO (Reference Input) ................................................................................. 13
12.288 MHz Crystal (-XO) option (Reference Input) .......................................................... 13
EVALUATION BOARD INPUTS/OUTPUTS ......................................................................................... 14
RECOMMENDED TEST EQUIPMENT ................................................................................................. 17
APPENDIX A: CODELOADER USAGE .............................................................................................. 18
Port Setup Tab .......................................................................................................................................................... 18
Clock Outputs Tab .................................................................................................................................................... 19
PLL1 Tab .................................................................................................................................................................. 20
PLL2 Tab .................................................................................................................................................................. 21
Bits/Pins Tab ............................................................................................................................................................ 22
Registers Tab ............................................................................................................................................................ 24
APPENDIX B: TYPICAL PHASE NOISE PERFORMANCE PLOTS ......................................................... 25
PLL1 ......................................................................................................................................................................... 25
Crystek 122.88 MHz VCXO................................................................................................. 25
Vectron 12.288 MHz Crystal ................................................................................................ 26
PLL2 ......................................................................................................................................................................... 27
Clock Outputs ........................................................................................................................................................... 28
Clock Output Measurement Technique ................................................................................ 28
LMK040x0B Phase Noise ........................................................................................................................................ 29
LMK040x1B Phase Noise ........................................................................................................................................ 30
LMK040x2B Phase Noise ........................................................................................................................................ 31
LMK040x3B Phase Noise ........................................................................................................................................ 32
APPENDIX C: SCHEMATICS ............................................................................................................ 33
Power ........................................................................................................................................................................ 33
Main ......................................................................................................................................................................... 34
Clock Outputs ........................................................................................................................................................... 35
APPENDIX D: BOARD LAYERS STACKUP ....................................................................................... 36
APPENDIX E: BILL OF MATERIALS ................................................................................................ 37
Common Bill of Materials for Evaluation Boards .................................................................................................... 37
LMK040XX-REV3 EVALUATION BOARD OPERATING INSTRUCTIONS
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Bill of Material Custom to LMK04000BEVAL ....................................................................................................... 40
Bill of Material Custom to LMK04000BEVAL-XO ................................................................................................ 40
Bill of Material Custom to LMK04031BEVAL ....................................................................................................... 41
Bill of Material Custom to LMK04031BEVAL-XO ................................................................................................ 41
Bill of Material Custom to LMK04002BEVAL ....................................................................................................... 42
Bill of Material Custom to LMK04033BEVAL ....................................................................................................... 42
APPENDIX F: BALUN INFORMATION ............................................................................................... 43
Typical Balun Frequency Response ......................................................................................................................... 43
APPENDIX G: VCXO/CRYSTAL CHANGES...................................................................................... 44
Changing from Crystal Resonator to VCXO ............................................................................................................ 44
Changing from VCXO to Crystal Resonator ............................................................................................................ 47
APPENDIX H: LMK04000 .............................................................................................................. 50
APPENDIX I: PROPERLY CONFIGURING LPT PORT ......................................................................... 53
LPT Driver Loading ................................................................................................................................................. 53
Correct LPT Port/Address ........................................................................................................................................ 53
Correct LPT Mode .................................................................................................................................................... 54
APPENDIX J: TROUBLESHOOTING INFORMATION ........................................................................... 55
1)Confirm Communications ............................................................................................................................. 55
2)Confirm PLL1 operation/locking .................................................................................................................. 55
3)Confirm PLL2 operation/locking .................................................................................................................. 56
LMK040XX-REV3 EVALUATION BOARD OPERATING INSTRUCTIONS
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General Description
The LMK040xx Evaluation Board simplifies evaluation of the LMK040xxB Precision Clock
Conditioner with Dual PLLs and Integrated VCO. Configuring and controlling the board is
accomplished using National Semiconductor’s CodeLoader software, which can be downloaded
from: http://www.national.com/timing/software/.
The CodeLoader software will run on a Windows 2000 or Windows XP PC. The CodeLoader
software is used to program the internal registers of the LMK040xxB device through a
MICROWIRETM interface.
Evaluation Board Kit Content s
The evaluation board kit contains…
An LMK040xx Evaluation board (one from Table 1).
LMK04000 Family quick start guide.
o Evaluation board instructions are downloadable from the product folder on
National’s website, www.national.com/.
CodeLoader uWire cable (LPT --> uWire).
A vailable Evaluatio n Boards
National Semiconductor has released a series of evaluation boards which allow the customer to
evaluate the different output types and VCO frequency ranges made available by the LMK04000
Family.
Note: It is possible to mount a VCXO on a –XO board or a Crystal on a non –XO board. See
Appendix G: VCXO/Crystal changes for more details.
Table 1. Avail able E val uation boards and configuration
Evaluation Board NSID VCXO Crystal (XTAL)
LMK04000BEVAL 122.88 MHz Crystek -
LMK04000BEVAL-XO - Vectron 12.288 MHz crystal
LMK04031BEVAL 122.88 MHz Crystek -
LMK04031BEVAL-XO - Vectron 12.288 MHz crystal
LMK04002BEVAL 122.88 MHz Crystek -
LMK04033BEVAL 122.88 MHz Crystek -
LMK040XX-REV3 EVALUATION BOARD OPERATING INSTRUCTIONS
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A vailable LMK04000 Family NSIDs
Please refer to the datasheet for the most up to date list of available devices in the LMK04000
Family.
Table 2. LMK040xxB Clock Output Configuration
Part Number CLKout0 CLKout1 CLKout2 CLKout3 CLKout4 VCO
Frequency
LMK04000BISQ LVPECL/
2VPECL
LVCMOS
(x2)
LVCMOS
(x2)
LVPECL/
2VPECL
LVPECL/
2VPECL
1185 to 1296
MHz
LMK04001BISQ LVPECL/
2VPECL
LVCMOS
(x2)
LVCMOS
(x2)
LVPECL/
2VPECL
LVPECL/
2VPECL
1430 to 1570
MHz
LMK04002BISQ LVPECL/
2VPECL
LVCMOS
(x2)
LVCMOS
(x2)
LVPECL/
2VPECL
LVPECL/
2VPECL
1566 to 1724
MHz
LMK04010BISQ LVPECL/
2VPECL
LVPECL/
2VPECL
LVPECL/
2VPECL
LVPECL/
2VPECL
LVPECL/
2VPECL
1185 to 1296
MHz
LMK04011BISQ LVPECL/
2VPECL
LVPECL/
2VPECL
LVPECL/
2VPECL
LVPECL/
2VPECL
LVPECL/
2VPECL
1430 to 1570
MHz
LMK04031BISQ LVDS LVPECL/
2VPECL
LVCMOS
(x2)
LVPECL/
2VPECL LVDS 1430 to 1570
MHz
LMK04033BISQ LVDS LVPECL/
2VPECL
LVCMOS
(x2)
LVPECL/
2VPECL LVDS 1840 to 2160
MHz
Note: LVPECL/2VPECL is software programmable.
LMK040XX-REV3 EVALUATION BOARD OPERATING INSTRUCTIONS
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Quick Start
Full evaluation board instructions with data are downloadable from the product folder of the
device at National Semiconductor’s website, www.national.com/.
1. Connect a voltage of 3.3 volts to either the Vcc SMA connector or the alternate connector.
2. Connect a reference clock from a signal generator or other source. Exact frequency
depends on programming. Default modes use a 122.88 MHz reference.
3. Connect the uWire header to a computer parallel port with the CodeLoader cable. A
USB communication option is available, search at www.national.com/ for:
USB2UWIRE-IFACE.
4. Program the device with CodeLoader. Ctrl-L must be pressed at least once to load all
registers once after CodeLoader is started or after restoring a Mode. CodeLoader is
available for download at www.national.com/timing/software/.
5. Measurements may be made at any clock output or Fout if enabled by programming.
Figure 1 - Quick Start Dia gr am
LMK040XX-REV3 EVALUATION BOARD OPERATING INSTRUCTIONS
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Default CodeLoader modes for evaluation boards
CodeLoader saves the state of the device when exiting the software. To ensure a common
starting point, the following modes listed in Table 3 may be restored by clicking “Mode” Æ
<Default Mode for evaluation board>.
After restoring a mode, be sure to press Ctrl-L to program the device. The default modes also
disable all outputs, so be sure to enable an output to make measurements.
Table 3 - Default Evaluation Board Modes
Evaluation Board NSID Default Mode
LMK04000BEVAL 122.88 MHz VCXO Default
LMK04000BEVAL-XO 12.288 MHz Crystal Default, or
12.288 MHz Crystal with Doubler Default
LMK04031BEVAL 122.88 MHz VCXO Default
LMK04031BEVAL-XO 12.288 MHz Crystal Default, or
12.288 MHz Crystal with Doubler Default
LMK04002BEVAL 122.88 MHz VCXO Default
LMK04033BEVAL 122.88 MHz VCXO Default
The next section outlines step-by-step procedures for using an LMK04031B evaluation board.
The process is the same for other evaluation boards except the part number is different.
LMK040XX-REV3 EVALUATION BOARD OPERATING INSTRUCTIONS
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Using CodeLoader to Program the LMK040xxB
The purpose of this section is to walk the user through using CodeLoader to make some
measurements with the LMK040xxB device. For more information on CodeLoader refer to
Appendix A: CodeLoader Usage or the CodeLoader 4 instructions located at
http://www.national.com/timing/software/.
Before proceeding, be sure to follow the Quick Start section above to ensure proper connections.
1. S tart CodeLoader 4 Application
Click “Start” Æ “Programs” Æ “CodeLoader 4” Æ “CodeLoader 4”
The CodeLoader 4 program is installed by default to the CodeLoader 4 application group.
2. Select Device
Click “Select Device” Æ “Clock Conditioners” Æ “LMK04031B”
Once started CodeLoader 4 will load the last
used device. To load a new device click
“Select Device” from the menu bar, then
select the subgroup and finally device to
load. For this example, the LMK04031B is
chosen. Selecting the device does cause the
device to be programmed.
Figure 2 – Selecting the LMK040 3 1B
LMK040XX-REV3 EVALUATION BOARD OPERATING INSTRUCTIONS
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3. Program/Load Device
Press “Ctrl – L”
Assuming the Port Settings are correct, it is
now possible to click “Keyboard Controls”
Æ “Load Device” from the menu to program
the device to the current state of the newly
loaded LMK04031B file. Ctrl-L is the
accelerator assigned to the Load Device
option and is very convenient.
Once the device has been loaded, by default CodeLoader will automatically program changed
registers, so it is not necessary to load the device again completely. It is possible to disable this
functionality by ensuring there is no checkmark by the “Mode” Æ “AutoReload with Changes.”
Since a default mode will be restored in the next step, this step isn’t really needed but included to
emphasize the importance of pressing “Ctrl-L” to load the device at least once after starting
CodeLoader, restoring a mode, or restoring a saved setup using the File menu.
See Appendix A: CodeLoader Usage or the CodeLoader 4 instructions located at
http://www.national.com/timing/software/ for more information on port setup. Appendix J:
Troubleshooting Information contains information on troubleshooting communications.
4. Restoring a Default Mode
Click “Mode” Æ “122.88 MHz VCXO Default”; then
Press “Ctrl – L”
Figure 4 – Setting the 122.88 MHz VCXO Default mode
For the purposes of this walkthrough a default mode will be loaded to ensure a common starting
point. This is important because when CodeLoader is closed, it remembers the last settings used
for a particular device. By loading the default mode a common starting point is ensured.
Loading a mode does not automatically program the device so it is necessary to press “Ctrl – L”
again to program the device.
Figure 3 - Loading the Devi ce
LMK040XX-REV3 EVALUATION BOARD OPERATING INSTRUCTIONS
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5. V isual Confirmation of Frequency Lock
After a device is selected and a default mode restored and loaded, the visual display on the board
should indicate a clock present at CLKin0 (LED D3 off) and that the PLL is locked (LED D1 on).
D1 will be on because the mode default sets PLL_MUX = PLL1/2 DLD Active High.
Figure 5 – Visual indic at ors of proper operation of eval uation board
6. Enable Fout
To measure the phase noise of the VCO,
1. Go to the Bits/Pins tab and enable the
“EN_Fout” bit.
2. Connect the Fout SMA on the left hand side of
the board to a spectrum analyzer or signal
source analyzer.
See Appendix B: Typical Phase Noise Performance
Plots for phase noise plots of the VCO.
Red LED off
LED D3 on if no signal
detected on CLKin0 port.
Green LED on
LED D1 on if locked when
PLL_MUX = PLL1/2 DLD
Active High. (mode default)
LMK040XX-REV3 EVALUATION BOARD OPERATING INSTRUCTIONS
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7. Enable Clock Output s
To measure phase noise at the clock outputs,
1. Click on the “Clock Outputs” tab,
2. Enable an output,
3. Then set the
a. CLKout MUX mode,
b. divide value, and
c. delay value.
Figure 6 - Setting Divide, Delay, CLKout _ MUX, Enabled for CLKout1 on "Clock Outpu ts" tab.
4. Connect the clock output SMAs to a spectrum analyzer or signal source analyzer.
a. For LVDS, a balun is recommended such as the ADT2-1T.
b. For LVPECL,
i. A balun can be used, or
ii. One side of the LVPECL signal can be terminated with a 50 ohm load and
the other side can be run to the test equipment single ended.
c. For LVCMOS,
i. Only one side of the LVCMOS signal can be turned
on by setting the CLKout_#a / CLKout_#b states in
the CLKout CMOS Options on the Bits/Pins tab.
ii. One side of the LVCMOS signal can be terminated
with a 50 ohm load and the other side can be run to
the test equipment single ended.
iii. A balun may be used. Ensure CLKout_#a and
CLKout_#b states are complementary, for example:
Non-inverted and Inverted.
5. The phase noise may be measured with a spectrum analyzer or signal source analyzer.
See Appendix B: Typical Phase Noise Performance Plots for phase noise plots of the clock
outputs.
National’s Clock Design Tool can be used to calculate divider values to achieve desired clock
output frequencies. See: http://www.national.com/timing/software/.
Figure 7 - Setting
LVCMOS modes.
LMK040XX-REV3 EVALUATION BOARD OPERATING INSTRUCTIONS
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PLL Loop Filters and Loop Parameters
In jitter cleaning applications that use a cascaded PLL architecture, the first PLL’s purpose is to
substitute the phase noise of a low noise oscillator (VCXO or crystal resonator) for the phase
noise of a “dirty” reference clock. The first PLL is typically configured with a narrow loop
bandwidth in order to minimize the impact of the reference clock phase noise. The reference
clock consequently serves only as a frequency reference rather than a phase reference.
The loop filters on the LMK040xx evaluation board are setup using the approach above. The
loop filter for PLL1 has been configured for a narrow loop bandwidth (< 100 Hz), while the loop
filter of PLL2 has been configured for a wide loop bandwidth (> 100 kHz). The specific loop
bandwidth values depend on the phase noise performance of the oscillator mounted on the board.
The following tables contain the parameters for PLL1 and PLL2 for each oscillator option.
National’s Clock Design Tool can be used to optimize PLL phase noise/jitter for given
specifications. See: http://www.national.com/timing/software/.
PLL 1 Loop Filter
Table 4. PLL1 Loop Filter Parameters for Crystek 122.88 MHz VCXO and 12.288 MHz Vectron Crystal
122.88 MHz VCXO option
Phase Margin 50º Kφ (Charge Pump) 100 uA
Loop Bandwidth 12 Hz Phase Detector Freq 1.024 MHz
VCO Gain 2.5 kHz/Volt
Reference Clock
Frequency 122.88 MHz Output Frequency 122.88 MHz (To PLL 2)
Loop Filter Components C1 = 100 nF C2 = 680 nF R2 = 39 k
12.288 MHz Crystal (-XO) option
Phase Margin 60º Kφ (Charge Pump) 100 uA
Loop Bandwidth 8 Hz Phase Detector Freq 1.024 MHz
VCO Gain 1.5 kHz/Volt
Reference Clock
Frequency 122.88 MHz Output Frequency 12.288 MHz (To PLL 2)
Loop Filter Components C1 = 330 nF C2 = 10 uF R2 = 3.9 k
Note: PLL Loop Bandwidth is a function of Kφ, Kvco, N as well as loop components. Changing
Kφ and N will change the loop bandwidth.
LMK040XX-REV3 EVALUATION BOARD OPERATING INSTRUCTIONS
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PLL2 Loop Filter
122.88 MHz VCXO (Reference Input)
LMK040x0B LMK040x1B LMK040x2B LMK040x3B Units
C1 Open
C2 12 nF
C3 0 nF
C4 0.01 nF
R2 1.8 k
R3 0.6 k
R4 0.2 k
Charge Pump
Current, Kφ 3.2 mA
Phase Detector
Frequency 61.44 MHz
Frequency 1228.8 1474.56 1720.32 1966.08 MHz
Kvco 8 9 13 19 MHz/V
N 20 24 28 32
Phase Margin 85.5 85.5 85.0 84.0 degrees
Loop Bandwidth 366 343 424 542 kHz
12.288 MHz Crystal (-XO) option (Reference Input)
LMK040x0B LMK040x1B LMK040x2B LMK040x3B Units
C1 Open
C2 6.8 nF
C3 0 nF
C4 0.01 nF
R2 2.7 k
R3 0.6 k
R4 0.2 k
Charge Pump
Current, Kφ 3.2 mA
Phase Detector
Frequency 12.288 MHz
Frequency 1228.8 1474.56 1720.32 1966.08 MHz
Kvco 8 9 13 19 MHz/V
N 100 120 140 160
Phase Margin 62 63 60 56 degrees
Loop Bandwidth 98 93 112 136 kHz
Note: PLL Loop Bandwidth is a function of Kφ, Kvco, N as well as loop components. Changing
Kφ and N will change the loop bandwidth.
LMK040XX-REV3 EVALUATION BOARD OPERATING INSTRUCTIONS
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Evaluation Board Inputs/Outputs
The following table contains descriptions of the various inputs and outputs for the evaluation
board.
Table 5. LMK040xx Evaluation Board I/O
Connector Name Input/Output Description
CLKout0 /
CLKout0*,
CLKout1 /
CLKout1*,
CLKout2 /
CLKout2*,
CLKout3 /
CLKout3*,
CLKout4 /
CLKout4*
Output
Populated connectors.
Differential clock output pairs. See Table 2 for format of
the output depending on part number. If an LVCMOS
output, each output can be independently configured (non-
inverted, inverted, tri-state, and LOW).
On the evaluation board, all clock outputs are AC-coupled
to allow safe testing with RF test equipment.
All LVPECL/2VPECL clock outputs are
terminated to GND with a 120 ohm resistor, one on
each output pin of the pair.
CLKout4 is configured with an on board balun. Part
number is Mini-circuits’ ADT2-1T. According to the
ADT2-1T datasheet the 3 dB frequency range is 0.4 to 450
MHz. See Appendix F: Balun Information for more detail.
Fout Output
Populated connector.
When enabled, buffered VCO output. AC-coupled. The
default configuration on the board contains a 3-dB
attenuator on the Fout signal.
Vcc Input
Populated connector.
DC power supply for the PCB. Removing R1, R2, or R3
allow for splitting the power to various devices on the
board. For example, the VCXO is powered from the
VccAUXPlane connected via R3.
Note: The LMK04000 Family contains internal voltage
regulators for the VCO, PLL and related circuitry. The
clock outputs do not have an internal regulator. A clean
power supply is required for best performance.
VccLDO Input
Unpopulated connector.
Vcc input for LDOs on bottom of PCB. Refer to
schematics for more information.
LMK040XX-REV3 EVALUATION BOARD OPERATING INSTRUCTIONS
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Connector Name Input/Output Description
CLKin0/CLKin0*,
CLKin1/CLKin1* Input
Populated connectors.
Reference clock inputs for PLL1. The default board
configuration is setup for a single-ended reference source
at CLKin0* (CLKin0 pin is AC-coupled to ground). The
mode of the clock input buffer is programmable in
CodeLoader on the Bits/Pins tab, and may be either bi-
polar junction mode or MOS mode.
The input level for the various modes is as in the datasheet:
AC Coupled Input Clock Voltage Levels
Input Mode Min Max Units
Differential Bipolar 0.25 2.0 Vpp
Differential MOS 0.25 2.0 Vpp
Single Ended Bipolar 0.5 3.1 Vpp
Single Ended MOS 0.5 3.1 Vpp
If a DC-coupled clock is used to drive either of the inputs,
the high voltage level must be at least 2 volts and the low
voltage no greater than 0.4 volts.
By default CLKin0 is the active input in either of the auto-
switching modes (CLKin0 non-revertive, CLKin0
revertive). When loss of CLKin0 is detected, the device
automatically switches to CLKin1 if an active reference
clock is attached. See datasheet for further explanation.
LOS0, LOS1 Output
Unpopulated connectors.
Loss-of-Signal indicator (when LOS_TYPE = Active
CMOS, default) for CLKin0/0* and CLKin1/1*. The
LEDs D5 and D3 are light red when no signal is detected
according to the datasheet specification for LOS pins.
Bits/Pins, LOS_TYPE = Active CMOS for default
operation.
OSCin/OSCin* Input
Populated connectors.
By altering the PCB an external VCXO may be attached to
the OSCin/OSCin* SMA connectors. Either a differential
or single-ended device may be used. If a single-end device
is used, OSCin* should be tied to GND through a capacitor
that matches the AC-coupling capacitor value used for the
OSCin pin. See datasheet for OSCin port signal
specifications.
LMK040XX-REV3 EVALUATION BOARD OPERATING INSTRUCTIONS
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Connector Name Input/Output Description
Vtune1 Output
Unpopulated connector.
Tuning voltage output from the loop filter for PLL1. If an
external VCXO is used, this tuning voltage should be
connected to the voltage control pin of the external VCXO.
Note: Resistor R38 must be populated with a zero ohm
resistor to control an off-board VCXO.
uWire Input/Output
Populated connector.
10-pin header programming interface for the board. Of
Most important are the CLKuWire, DATAuWire, and
LEuWire programming lines from this header. Each of
these signals, GEO, and SYNC* can be monitored through
test points on the board.
LD Output
Unpopulated connector.
The LD pin is attached to a multiplexer inside the device
and may be programmed with a variety of internal signals
for monitoring internal device functions and
troubleshooting. See datasheet for further explanation.
The lock detect signal is accessible through this pin.
LD_TP Output
Test point attached to the LD pin of the device. See LD
above for more information.
GOE Input
Unpopulated connector.
Access to GOE of device.
SYNC* Input
Unpopulated connector.
Access to SYNC* of device.
PTO Output
Unpopulated connector.
Vcc SMA located close to OSCin SMAs for powering
external oscillator boards.
LMK040XX-REV3 EVALUATION BOARD OPERATING INSTRUCTIONS
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Recommended Test Equipment
Power Supply
The Power Supply should be a low noise power supply.
Phase Noise / Spectrum Analyzer
For measuring phase noise an Agilent E5052A Signal Source Analyzer is recommended. An
Agilent E4445A PSA Spectrum Analyzer with the Phase Noise option is also usable although the
architecture of the E5052A is superior for phase noise measurements. At frequencies less than
100 MHz the local oscillator noise of the E4445A is too high and measurements will reflect the
E4445A’s internal local oscillator performance, not the device under test.
LMK040XX-REV3 EVALUATION BOARD OPERATING INSTRUCTIONS
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Appendix A: CodeLoader Usage
Code Loader is used to program the evaluation board with either an LPT port using the included
CodeLoader cable or with a USB port using the optional USB <--> uWire cable available from
http://store.national.com/. The part number is USB2UWIRE-IFACE.
Port Setup Tab
Figure 8 - Port Setup tab
On the Port Setup tab, the user may select the type of communication port (USB or Parallel) that
will be used to program the device on the evaluation board. If parallel port is selected, the user
should ensure that the correct port address is entered.
The Pin Configuration field is hardware dependent and normally SHOULD NOT be changed by
the user. Figure 8 shows the default settings.
LMK040XX-REV3 EVALUATION BOARD OPERATING INSTRUCTIONS
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Clock Output s Tab
Figure 9 - Clock Outputs ta b
The clock outputs tab allows the user to Enable/Disable individual clock outputs, select the clock
mode (Bypass/Divided/Delayed/Divided & Delayed), set the clock output delay value (if delay is
enabled), and the clock output divider value (2, 4, 6, …, 510).
This tab also allows the user to select the VCO Divider value (2, 3, …, 8). Note that the total
PLL2 N divider value is composed of both the VCO Divider value and the N value shown in the
blue box in the image, and is given by: N_TOTAL = VCO Divider * N.
Clicking on the blue box that contains R, PDF and N values takes the user to the PLL2 tab where
these values may be changed.
Clicking on the components in the box containing the Internal Loop Filter values allows the user
to change these component values.
The Reference Oscillator value field may be changed in either the Clock Outputs tab or the PLL2
tab. Note this value should match the value of the on-board VCXO or Crystal. When using the
EN_PLL2_REF2X = 1, then Reference Oscillator field should be twice the VCXO or Crystal
frequency.
LMK040XX-REV3 EVALUATION BOARD OPERATING INSTRUCTIONS
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PLL1 Tab
Figure 10 - PLL1 tab.
The PLL1 tab allows the user to change:
External VCXO (or Crystal oscillator) frequency. Note: This value must be entered in
both the PLL1 and PLL2 tabs.
PLL1 Phase detector frequency
PLL1 R-counter value
PLL1 N-counter value
CLKin (Reference) oscillator frequency
PLL1 Phase Detector polarity (for external VCXO tuning slope, click on the polarity
value)
PLL1 Charge pump gain (left click and right click on the charge pump current value)
PLL1 Charge pump state (click on the charge pump state value)
Note that the value entered in the VCO frequency field on the PLL1 tab must match the
Reference Oscillator frequency entered on the PLL2 tab and the OSCin_FREQ on the Bits/Pins
tab. Updating the PLL2 tab Reference Oscillator frequency will automatically update the value
of OSCin_FREQ on the Bits/Pins tab. The only time that the Reference Oscillator frequency of
PLL2 tab will be different from the VCO frequency of PLL1 is when the EN_PLL2_REF2X
mode is enabled.
LMK040XX-REV3 EVALUATION BOARD OPERATING INSTRUCTIONS
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PLL2 Tab
Figure 11 - PLL2 tab.
The PLL2 tab allows the user to change:
VCO frequency
PLL2 Phase detector frequency
PLL2 R-counter value
PLL2 N-counter value
The frequency of the external VCXO (or XTAL oscillator). Note: This value must be
entered in both the PLL1 and PLL2 tabs.
PLL2 Charge pump gain
PLL2 Charge pump state
Any changes made on this tab are reflected in the Clock Outputs tab. Note that the PLL2 Phase
Detector polarity is fixed and cannot be changed by the user. Also note that the VCO frequency
should conform to the specified frequency range for the device.
Note that the value entered in the VCO frequency field on the PLL1 tab must match the
Reference Oscillator frequency entered on the PLL2 tab and the OSCin_FREQ on the Bits/Pins
tab. Updating the PLL2 tab Reference Oscillator frequency will automatically update the value
of OSCin_FREQ on the Bits/Pins tab. The only time that the Reference Oscillator frequency of
PLL2 tab will be different from the VCO frequency of PLL1 is when the EN_PLL2_REF2X
mode is enabled.
LMK040XX-REV3 EVALUATION BOARD OPERATING INSTRUCTIONS
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Bit s/Pins Tab
Figure 12 - Bits/Pins tab.
The Bits/Pins tab allows the user to program bits directly. Many of which are not available on
other tabs. Refer to the datasheet for more detailed information. The bits available are:
Common Box
o RESET - Set the reset bit. This will reset the device. In a normal application it is
not necessary to program this bit clear since it is auto-clearing. However in the
CodeLoader software, RESET must be clicked again (cleared) to not cause a reset
every time R7 is programmed.
o POWERDOWN - Place the device in powerdown mode.
o EN_Fout – Enable the Fout port.
PLL Box
o PLL_MUX – Set the function of the LD pin.
o RC_DLD1_Start – Prevent PLL2 from locking until digital lock detect from
PLL1 is achieved.
o EN_PLL2_XTAL – Enables Crystal mode for PLL2. For use with Crystals as
opposed to a VCXO.
o EN_PLL2_REF2X – Doubles the reference frequency of PLL2. Note with this is
enabled, the PLL_R value is invalid. Program the Reference Oscillator on PLL2
Tab to be twice the VCO frequency on PLL1 tab. This adjustment must be done
manually.
LMK040XX-REV3 EVALUATION BOARD OPERATING INSTRUCTIONS
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CLKin Options Box
o CLKin_SEL – Sets manual or automatic switching modes for selecting a
reference oscillator for PLL1.
o LOS_TIMEOUT – The timeout value before a loss of signal on a clock input is
registered on the LOS pins.
o LOS_TYPE – Set the type of output for the LOS pins.
o CLKin0_BUFTYPE & CLKin1_BUFTYPE – Select the input buffer used for the
respective clock input.
PLL2_LF Box
o Set the integrated loop filter values for PLL2 including,
PLL2_R3_LF – R3 value
PLL2_R4_LF – R4 value
PLL2_C3_C4_LF – C3 and C4 value at the same time
o It is also possible to set these values by clicking on the loop filter values on the
Clock Outputs tab.
CLKout Options Box
o EN_CLKout_Global – A global enable for clocks, if unchecked no outputs will
be observed!
o EN_CLKout0 through EN_CLKout4 – Individual clock output enables. These
can also be set on the Clock Outputs tab.
o The number of options vary depending on the option of the LMK device selected.
CLKout#_PECL_LVL – Set the level of an LVPECL output to LVPECL
or 2VPECL. The 2VPECL a higher output level than LVPECL.
CLKout CMOS Options Box
o The presence of this box and the number of options on this tab depends upon the
option of the LMK device.
CLKout##_STATE – Set the state of the individual LVCMOS output.
VCO Control – FC Box
o OSCin_FREQ – Must be set to the reference frequency of PLL2 in MHz, which
should normally be the VCO frequency of PLL1. NOTE: It is important to
enter the correct frequency value in this field, as it is used by the internal
state machine of the LMK040xxB to execute its calibration routine for the
internal VCO. An incorrect value may result in an unlocked condition for the
synthesizer.
Entering a reference oscillator frequency on PLL2 tab will automatically
update this register with the frequency to the nearest MHz.
Program Pins Box
o GOE – Set high or low voltage on GOE pin. Checked is high voltage.
If GOE is low, then no clock outputs will be observed!
o SYNC* – Set high or low voltage on SYNC* pin. Checked is high voltage.
If SYNC* is low, then no clock outputs will be observed on divided clock
outputs!
o TRIGGER – Set high or low voltage on pin 10 of uWire header.
LMK040XX-REV3 EVALUATION BOARD OPERATING INSTRUCTIONS
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Registers Tab
The registers tab shows the value of each register. This is convenient for programming the
device to the desired settings, then recording the hex values for programming in your own
application.
By clicking in the “bit field” it is possible to manually change the value of registers by typing ‘1’
and ‘0.’