STL3N10F7 N-channel 100 V, 0.062 typ., 4 A STripFETTM VII DeepGATETM Power MOSFET in a PowerFLATTM 2x2 package Datasheet - production data Features Order code VDS RDS(on) max ID STL3N10F7 100 V 0.07 4A 1 2 3 * N-channel enhancement mode 6 1 * Low gate charge 5 2 4 3 * 100% avalanche rated PowerFLATTM 2x2 Applications * Switching applications Figure 1. Internal schematic diagram 2(D) 1(D) 3(G) D 6(D) Description This device utilizes the 7th generation of design rules of ST's proprietary STripFETTM technology, with a new gate structure. The resulting Power MOSFET exhibits the lowest RDS(on) in all packages. S 5(D) 4(S) Bottom view AM11269v1 Table 1. Device summary Order code Marking Packages Packaging STL3N10F7 ST3N PowerFLATTM 2x2 Tape and reel April 2014 This is information on a product in full production. DocID025948 Rev 2 1/13 www.st.com Contents STL3N10F7 Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) ............................ 6 3 Test circuits 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2/13 .............................................. 8 DocID025948 Rev 2 STL3N10F7 1 Electrical ratings Electrical ratings Table 2. Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage 100 V VGS Gate-source voltage 20 V ID(1) Drain current (continuous) at Tpcb = 25 C 4 A ID (1) Drain current (continuous) at Tpcb=100 C 2.5 A IDM(2) Drain current (pulsed) 16 A Total dissipation at Tpcb = 25 C 2.4 W PTOT (1) TJ Operating junction temperature C -55 to 150 Tstg storage temperature C 1. The value is rated according Rthj-pcb 2. Pulse width limited by safe operating area. Table 3. Thermal resistance Symbol Rthj-pcb (1) Parameter Thermal resistance junction-pcb Value Unit 52 C/W 1. When mounted on FR-4 board of 1inch, 2oz Cu, t < 10 sec DocID025948 Rev 2 3/13 13 Electrical characteristics 2 STL3N10F7 Electrical characteristics (TCASE=25 C unless otherwise specified) Table 4. On/off states Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage, VGS= 0 ID = 250 A Min. Typ. Max. 100 Unit V VDS = 100 V 1 A VDS = 100 V, TC= 125 C 100 A Gate body leakage current (VDS = 0) VGS = 20 V 100 nA VGS(th) Gate threshold voltage VDS= VGS, ID = 250 A 4.5 V RDS(on) Static drain-source onresistance VGS= 10 V, ID= 2 A 0.062 0.07 Min. Typ. Max. Unit - 408 - pF - 112 - pF - 10 - pF - 7.8 - nC - 3 - nC - 1.7 - nC Min. Typ. Max. Unit - 6.3 - ns - 3 - ns - 11 - ns - 4 - ns IDSS IGSS Zero gate voltage drain current (VGS = 0) 2.5 Table 5. Dynamic Symbol Parameter Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Qg Total gate charge Qgs Gate-source charge Qgd Gate-drain charge Test conditions VDS =25 V, f=1 MHz, VGS=0 VDD=50 V, ID = 4 A VGS =10 V (see Figure 14) Table 6. Switching times Symbol td(on) tr td(off) tf 4/13 Parameter Test conditions Turn-on delay time Rise time Turn-off delay time VDD=50 V, ID= 2 A, RG=4.7 , VGS= 10 V (see Figure 13) Fall time DocID025948 Rev 2 STL3N10F7 Electrical characteristics Table 7. Source drain diode Symbol Parameter Test conditions Min. Typ. Max. Unit Source-drain current - 4 A (1) Source-drain current (pulsed) - 16 A (2) Forward on voltage ISD= 2 A, VGS=0 - 1.1 V trr Reverse recovery time - 30 ns Qrr Reverse recovery charge - 24 nC IRRM Reverse recovery current ISD= 2 A, di/dt = 100 A/s, VDD= 80 V, Tj=150 C (see Figure 18) - 1.6 A ISD ISDM VSD 1. Pulse width limited by safe operating area. 2. Pulsed: pulse duration = 300 s, duty cycle 1.5 % DocID025948 Rev 2 5/13 13 Electrical characteristics 2.1 STL3N10F7 Electrical characteristics (curves) Figure 2. Safe operating area Figure 3. Thermal impedance GIPG230120140925SA ID (A) GIPG230120140958SA K =0.5 Operation in this area is Limited by max RDS(on) 0.2 10 0.1 10 -1 100s 0.05 0.02 1 1ms Tj=150C Tpcb=25C 0.1 10ms Sinlge pulse 0.01 0.1 1 VDS(V) 10 Figure 4. Output characteristics GIPG200120141028FSR ID (A) VGS= 10 V pcb 0.01 10 -2 Single pulse 10 -3 10 -5 10 -4 10 -3 10 -1 10 -2 10 0 tp(s) Figure 5. Transfer characteristics GIPG200120141040FSR ID (A) VDS= 9V 30 30 9V 8V 24 7V 18 25 20 15 12 6 0 0 2 4 6 8 6V 10 5V 5 Figure 6. Gate charge vs gate-source voltage GIPG200120141048FSR VGS (V) VDD= 50V ID= 4A 12 0 VDS(V) 2 6 4 8 10 VGS(V) Figure 7. Static drain-source on-resistance GIPG210120141012FSR RDS(on) (m) 62.4 VGS=10V 10 62 8 6 61.6 4 61.2 2 0 2 6/13 4 6 8 10 QG(nC) 60.8 0.5 DocID025948 Rev 2 1 1.5 2 2.5 ID(A) STL3N10F7 Electrical characteristics Figure 8. Capacitance variations Figure 9. Normalized V(BR)DSS vs temperature GIPG200120141330FSR C (pF) 500 GIPG210120141040FSR V(BR)DSS (norm) ID= 250A 1.04 Ciss 400 1.02 300 1.0 200 0.98 100 0 0 20 40 60 80 Coss Crss VDS(V) Figure 10. Normalized gate threshold voltage vs temperature GIPG210120141021FSR VGS(th) (norm) ID= 250A 0.96 -75 -25 25 75 125 TJ(C) Figure 11. Normalized on-resistance vs temperature GIPG210120141030FSR RDS(on) (norm) VGS= 10 V 1.1 1.7 1 1.3 0.9 0.8 0.9 0.7 0.6 -75 -25 25 75 125 TJ(C) 0.5 -75 -25 25 75 125 TJ(C) Figure 12. Source-drain diode forward characteristics GIPG210120141051FSR VSD (V) 1.2 TJ=-55C 1.0 TJ=25C 0.8 TJ=175C 0.6 0.4 0.5 1 1.5 2 2.5 ISD(A) DocID025948 Rev 2 7/13 13 Test circuits 3 STL3N10F7 Test circuits Figure 13. Switching times test circuit for resistive load Figure 14. Gate charge test circuit VDD 12V 47k 1k 100nF 3.3 F 2200 RL F IG=CONST VDD VGS 100 Vi=20V=VGMAX VD RG 2200 F D.U.T. D.U.T. VG 2.7k PW 47k 1k PW AM01468v1 Figure 15. Test circuit for inductive load switching and diode recovery times A A AM01469v1 Figure 16. Unclamped inductive load test circuit L A D G D.U.T. FAST DIODE B B VD L=100H S 3.3 F B 25 1000 F D VDD 2200 F 3.3 F VDD ID G RG S Vi D.U.T. Pw AM01470v1 AM01471v1 Figure 17. Unclamped inductive waveform Figure 18. Switching time waveform ton V(BR)DSS tdon VD toff tr tdoff tf 90% 90% IDM 10% ID VDD 10% 0 VDD VDS 90% VGS AM01472v1 8/13 0 DocID025948 Rev 2 10% AM01473v1 STL3N10F7 4 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. DocID025948 Rev 2 9/13 13 Package mechanical data STL3N10F7 Figure 19. Drawing dimension PowerFLATTM 2x2 8368575_REV_C 10/13 DocID025948 Rev 2 STL3N10F7 Package mechanical data Table 8. PowerFLATTM 2 x 2 mechanical data mm. Dim. Min. Typ. Max. A 0.70 0.75 0.80 A1 0.00 0.02 0.05 A3 0.20 b 0.25 0.30 0.35 D 1.90 2.00 2.10 E 1.90 2.00 2.10 D2 0.90 1.00 1.10 E2 0.80 0.90 1.00 e 0.55 0.65 0.75 K 0.15 0.25 0.35 K1 0.20 0.30 0.40 K2 0.25 0.35 0.45 L 0.20 0.25 0.30 L1 0.65 0.75 0.85 Figure 20. PowerFLATTM 2x2 recommended footprint (all dimensions are in mm) Footprint DocID025948 Rev 2 11/13 13 Revision history 5 STL3N10F7 Revision history Table 9. Document revision history 12/13 Date Revision Changes 18-Feb-2014 1 First release. 30-Apr-2014 2 Document status promoted from preliminary to production data DocID025948 Rev 2 STL3N10F7 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. 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