This is information on a product in full production.
April 2014 DocID025948 Rev 2 1/13
STL3N10F7
N-channel 100 V, 0.062 Ω typ., 4 A STripFET™ VII DeepGATE™
Power MOSFET in a PowerFLAT™ 2x2 package
Datasheet
-
production data
Figure 1. Internal schematic diagram
Features
•N-channel enhancement mode
•Low gate charge
•100% avalanche rated
Applications
•Switching applications
Description
This device utilizes the 7
th
generation of design
rules of ST’s proprietary STripFET™ technology,
with a new gate structure. The resulting Power
MOSFET exhibits the lowest R
DS(on)
in all
packages.
PowerF LAT™ 2x2
1
2
3
6
5
4
1
2
3
1(D) 2(D) 3(G)
6(D) 5(D) 4(S)
DS
AM11269v1
Bottom view
Order code V
DS
R
DS(on)
max I
D
STL3N10F7 100 V 0.07 Ω4 A
Table 1. Device summary
Order code Marking Packages Packaging
STL3N10F7 ST3N PowerFLAT™ 2x2 Tape and reel
www.st.com
Contents STL3N10F7
2/13 DocID025948 Rev 2
Contents
1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
DocID025948 Rev 2 3/13
STL3N10F7 Electrical ratings
13
1 Electrical ratings
Table 2. Absolute maximum ratings
Symbol Parameter Value Unit
V
DS
Drain-source voltage 100 V
V
GS
Gate-source voltage ± 20 V
I
D(1)
1. The value is rated according R
thj-pcb
Drain current (continuous) at Tpcb = 25 °C 4 A
ID (1) Drain current (continuous) at Tpcb=100 °C 2.5 A
IDM(2)
2. Pulse width limited by safe operating area.
Drain current (pulsed) 16 A
P
TOT(1)
Total dissipation at T
pcb
= 25 °C 2.4 W
T
J
Operating junction temperature
-55 to 150
°C
T
stg
storage temperature °C
Table 3. Thermal resistance
Symbol Parameter Value Unit
R
thj-pcb (1)
1. When mounted on FR-4 board of 1inch², 2oz Cu, t < 10 sec
Thermal resistance junction-pcb 52 °C/W
Ele ctrical characteristics STL3N10F7
4/13 DocID025948 Rev 2
2 Electrical characteristics
(T
CASE
=25 °C unless otherwise specified)
Table 4. On/off states
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
(BR)DSS
Drain-source breakdown
voltage, V
GS
= 0 I
D
= 250 μA100 V
I
DSS
Zero gate voltage drain
current (V
GS
= 0)
V
DS
= 100 V 1μA
V
DS
= 100 V, T
C
= 125 °C 100 μA
I
GSS
Gate body leakage current
(V
DS
= 0) V
GS
= ± 20 V
±
100 nA
V
GS(th)
Gate threshold voltage V
DS
= V
GS
, I
D
= 250 μA2.5 4.5 V
R
DS(on)
Static drain-source on-
resistance V
GS
= 10 V, I
D
= 2 A 0.062 0.07 Ω
Table 5. Dynamic
Symbol Parameter Test conditions Min. Typ. Max. Unit
C
iss
Input capacitance
V
DS
=25 V, f=1 MHz,
V
GS
=0
-408 - pF
C
oss
Output capacitance - 112 - pF
C
rss
Reverse transfer
capacitance -10 - pF
Q
g
Total gate charge V
DD
=50 V, I
D
= 4 A
V
GS
=10 V
(see Figure 14)
-7.8 - nC
Q
gs
Gate-source charge - 3 - nC
Q
gd
Gate-drain charge - 1.7 - nC
Table 6. Switching times
Symbol Parameter Test conditions Min. Typ. Max. Unit
t
d(on)
Turn-on delay time
V
DD
=50 V, I
D
= 2 A,
R
G
=4.7 Ω, V
GS
= 10 V
(see Figure 13)
-6.3 - ns
t
r
Rise time - 3 - ns
t
d(off)
Turn-off delay time - 11 - ns
t
f
Fall time - 4 - ns
DocID025948 Rev 2 5/13
STL3N 10F7 Electri cal chara ct er ist ics
13
Table 7. Source drain diode
Symbol Parameter Test conditions Min. Typ. Max. Unit
I
SD
Source-drain current - 4 A
I
SDM(1)
1. Pulse width limited by safe operating area.
Source-drain current (pulsed) - 16 A
V
SD(2)
2. Pulsed: pulse duration = 300 μs, duty cycle 1.5 %
Forward on voltage I
SD
= 2 A, V
GS
=0 - 1.1 V
t
rr
Reverse recovery time I
SD
= 2 A,
di/dt = 100 A/μs,
V
DD
= 80 V, Tj=150 °C
(see Figure 18)
-30 ns
Q
rr
Reverse recovery charge - 24 nC
I
RRM
Reverse recovery current - 1.6 A
Ele ctrical characteristics STL3N10F7
6/13 DocID025948 Rev 2
2.1 Electrical characterist ics (curves)
Figure 2. Safe operating area Figure 3. Thermal impedance
Figure 4. Output characteristics Figure 5. Transfer characteristics
Figure 6. Gate charge vs gate-source voltage Figure 7. Static drain-source on-resistance
I
D
10
1
0.1
0.01
0.1 1V
DS
(V)
10
(A)
Operation in this area is
Limited by max R
DS(on)
100μs
1ms
10ms
Tj=150°C
Tpcb=25°C
Sinlge
pulse
GIPG230120140925SA
Single pulse
δ=0.5
0.05
0.02
0.01
0.1
0.2
K
10 t
p
(s)
-4 10-3
10-2
10-1
10-5
10-3
10-2 10-1 100
pcb
GIPG230120140958SA
I
D
18
12
6
0
04V
DS
(V)
(A)
26
24
30
6 V
5 V
7 V
8 V
9 V
V
GS
= 10 V
8
GIPG200120141028FSR
I
D
15
10
5
04V
GS
(V)
(A)
26
20
25
30
V
DS
= 9V
108
GIPG200120141040FSR
V
GS
6
4
2
04Q
G
(nC)
(V)
26
8
10
12
V
DD
= 50V
I
D
= 4A
108
GIPG200120141048FSR
R
DS(on)
62
61.6
61.2
60.80.5 1.5 I
D
(A)
(mΩ)
12
62.4 V
GS
=10V
2.5
GIPG210120141012FSR
DocID025948 Rev 2 7/13
STL3N 10F7 Electri cal chara ct er ist ics
13
Figure 8. Capacitance variations Figure 9. Normalized V
(BR)DSS
vs temperatu re
Figure 10. Normalized gate threshold voltage vs
temperature Figure 11. Normalized on-resistance vs
temperature
Figure 12. Source -drain diode forward
characteristics
C
400
300
200
100
040 V
DS
(V)
(pF)
20
500
60
Ciss
Coss
Crss
80
0
GIPG200120141330FSR
V
(BR)DSS
1.0
0.98
0.96
-75 T
J
(°C)
(norm)
-25 75
25 125
1.02
1.04 I
D
= 250µA
GIPG210120141040FSR
V
GS(th)
0.8
0.7
0.6
-75 T
J
(°C)
(norm)
-25
1.1
75
25 125
0.9
1
I
D
= 250µA
GIPG210120141021FSR
R
DS(on)
1.3
0.9
0.5
-75 T
J
(°C)
(norm)
-25 75
25 125
1.7
V
GS
= 10 V
GIPG210120141030FSR
V
SD
0.5 1.5 I
SD
(A)
(V)
122.5
0.4
0.6
0.8
T
J
=-55°C
T
J
=175°C
T
J
=25°C
1.0
1.2
GIPG210120141051FSR
Test circuits STL3N10F7
8/13 DocID025948 Rev 2
3 Test circuits
Figure 13. Switching times test circuit for
resistive load Figure 14. Gate charge test circuit
Figure 15. Test circuit for inductive load
switching and diode recovery times Figure 16. Unclamped inductive load tes t circuit
Figure 17. Unclamped inductive waveform Figure 18. Switching time waveform
AM01468v1
VGS
PW
VD
RG
RL
D.U.T.
2200
μF
3.3
μFVDD
AM01469v1
VDD
47kΩ1kΩ
47kΩ
2.7kΩ
1kΩ
12V
Vi=20V=VGMAX
2200
μF
PW
IG=CONST
100Ω
100nF
D.U.T.
VG
AM01470v1
A
D
D.U.T.
S
B
G
25 Ω
AA
B
B
RG
G
FAST
DIODE
D
S
L=100μH
μF
3.3 1000
μFVDD
AM01471v1
Vi
Pw
VD
ID
D.U.T.
L
2200
μF
3.3
μFVDD
AM01472v1
V(BR)DSS
VDD
VDD
VD
IDM
ID
AM01473v1
VDS
ton
tdon tdoff
toff
tf
tr
90%
10%
10%
0
0
90%
90%
10%
VGS
DocID025948 Rev 2 9/13
STL3N10F7 Package mechanical data
13
4 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK
®
is an ST trademark.
Package mechanical data STL3N10F7
10/13 DocID025948 Rev 2
Figure 19. Drawing dimension PowerFLAT™ 2x2
8368575_REV_C
DocID025948 Rev 2 11/13
STL3N10F7 Package mechanical data
13
Figure 20. PowerFLAT™ 2x2 recommended footprint (all dimensions are in mm)
Table 8. PowerFLAT™ 2 x 2 mechanical data
Dim. mm.
Min. Typ. Max.
A 0.70 0.75 0.80
A1 0.00 0.02 0.05
A3 0.20
b 0.25 0.30 0.35
D 1.90 2.00 2.10
E 1.90 2.00 2.10
D2 0.90 1.00 1.10
E2 0.80 0.90 1.00
e 0.55 0.65 0.75
K 0.15 0.25 0.35
K1 0.20 0.30 0.40
K2 0.25 0.35 0.45
L 0.20 0.25 0.30
L1 0.65 0.75 0.85
Footprint
Revision history STL3N10F7
12/13 DocID025948 Rev 2
5 Revision history
Table 9. Document revision history
Date Revision Changes
18-Feb-2014 1First release.
30-Apr-2014 2 Document status promoted from preliminary to production data
DocID025948 Rev 2 13/13
STL3N10F7
13
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