1
DSC-6158/4
FEBRUARY 2009
IDT72T54242
IDT72T54252
IDT72T54262
2.5V QUAD/DUAL TeraSync™ DDR/SDR FIFO
x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS
32,768 x 10 x 4/16,384 x 20 x 2
65,536 x 10 x 4/32,768 x 20 x 2
131,072 x 10 x 4/65,536 x 20 x 2
©2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The TeraSync is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
FEATURES
••
••
•Choose from among the following memory organizations:
IDT72T54242 - 32,768 x 10 x 4/32,768 x 10 x 2
IDT72T54252 - 65,536 x 10 x 4/65,536 x 10 x 2
IDT72T54262 - 131,072 x 10 x 4/131,072 x 10 x 2
••
••
•User Selectable Quad / Dual Mode - Choose between two or
four independent FIFOs
••
••
•Quad Mode offers
- Eight discrete clock domain, (four write clocks & four read clocks)
- Four separate write ports, write data to four independent FIFOs
- 10-bit wide write ports
- Four separate read ports, read data from any of four independent FIFOs
- Independent set of status flags and control signals for each FIFO
••
••
•Dual Mode offers
- Four discrete clock domain, (two write clocks & two read clocks)
- Two separate write ports, write data to two independent FIFOs
- 10-bit/20-bit wide write ports
- Two separate read ports, read data from any of two independent FIFOs
- Independent set of status flags and control signals for each FIFO
- Bus-Matching on read and write port x10/x20
- Maximum depth of each FIFO is the same as in Quad Mode
FUNCTIONAL BLOCK DIAGRAMS
••
••
•Up to 200MHz operating frequency or 2Gbps throughput in SDR mode
••
••
•Up to 100MHz operating frequency or 2Gbps throughput in DDR mode
••
••
•Double Data Rate, DDR is selectable, providing up to 400Mbps
bandwidth per data pin
••
••
•User selectable Single or Double Data Rate modes on both the
write port(s) and read port(s)
••
••
•All I/Os are LVTTL/ HSTL/ eHSTL user selectable
••
••
•3.3V tolerant inputs in LVTTL mode
••
••
•ERCLK and EREN Echo outputs on all read ports
••
••
•Write enable WEN and Chip Se lect WCS input for each write port
••
••
•Re ad enable REN and Chip Select RCS input for each read port
••
••
•User Selectable IDT Standard mode (using EF and FF) or FWFT
mode (using IR and OR)
••
••
•Programmable Almost Empty and Almost Full flags per FIFO
••
••
•Dedicated Serial Port for flag offset programming
••
••
•Power Down pin minimizes power consumption
••
••
•2.5V Supply Voltage
••
••
•Available in a 324-pin PBGA, 1mm pitch, 19mm x 19mm
••
••
•IEEE 1149.1 compliant JTAG port provides boundary scan function
••
••
•Low Power, High Performance CMOS technology
••
••
•Industrial temperature range (-40°°
°°
°C to +85°°
°°
°C)
••
••
•Green parts available, see ordering information
32,768 x 10
65,536 x 10
131,072 x 10
32,768 x 10
65,536 x 10
131,072 x 10
32,768 x 10
65,536 x 10
131,072 x 10
32,768 x 10
65,536 x 10
131,072 x 10
WEN1
WCS1
WEN2
WCS2
WEN3
WCS3
WCLK1
WCLK2
WCLK3
D[19:10]
D[29:20]
D[39:30]
FIFO 1
FIFO 2
FIFO 3
FIFO 1
Data In
FIFO 2
Data In
FIFO 3
Data In
FF0/IR0
PAF0
FF1/IR1
PAF1
FF2/ IR2
PAF2
FF3/IR3
PAF3
Write Port
Flag Outputs
WEN0
WCS0
WCLK0
D[9:0]
EF0/OR0
PAE0
EF1/OR1
PAE1
EF2/OR2
PAE2
EF3/OR3
PAE3
Read Port
Flag Outputs
6158 drw01
Q[9:0]
x10
REN0
RCS0
RCLK0
OE0
FIFO 0
Quad Mode
FIFO 0
Data In
EREN0
ERCLK0
Q[19:10]
REN1
RCS1
RCLK1
OE1
EREN1
ERCLK1
Q[29:20]
REN2
RCS2
RCLK2
OE2
EREN2
ERCLK2
Q[39:30]
REN3
RCS3
RCLK3
OE3
EREN3
ERCLK3
FIFO 1
Data Out
FIFO 2
Data Out
FIFO 3
Data Out
FIFO 0
Data Out
x10
x10
x10
x10
x10
x10
x10
(See next page for Dual Mode)
2
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync™ DDR/SDR FIFO
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
FEBRUARY 11, 2009
32,768 x 10/16,384 x 20
65,536 x 10/32,768 x 20
131,072 x 10/65,536 x 20
WEN2
WCS2
WCLK2
D[39:20]
FIFO 2
FIFO 2
Data In Q[39:20]
REN2
RCS2
RCLK2
OE2
EREN2
ERCLK2
FIFO 2
Data Out
WEN0
WCS0
WCLK0
D[19:0]
x10 or
x20
REN0
RCS0
RCLK0
OE0
FIFO 0
Dual Mode
FIFO 0
Data In
EREN0
ERCLK0
FIFO 0
Data Out
x10 or
x20
Q[19:0]
FF0/IR0
PAF0
FF2/IR2
PAF2
Write Port
Flag Outputs
EF0/OR0
PAE0
EF2/OR2
PAE2
Read Port
Flag Outputs
6158 drw02
x10 or
x20
x10 or
x20
32,768 x 10/16,384 x 20
65,536 x 10/32,768 x 20
131,072 x 10/65,536 x 20
FUNCTIONAL BLOCK DIAGRAMS (CONTINUED)
3
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync™ DDR/SDR FIFO
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
FEBRUARY 11, 2009
Table of Contents
Features .........................................................................................................................................................................................................................1
Description ......................................................................................................................................................................................................................4
Pin Configuration .............................................................................................................................................................................................................6
Pin Descriptions...............................................................................................................................................................................................................7
Device Characteristics ................................................................................................................................................................................................... 11
DC Electrical Characteristics ..........................................................................................................................................................................................12
AC Electrical Characteristics...........................................................................................................................................................................................14
AC T est Conditions ........................................................................................................................................................................................................15
Functional Description ...................................................................................................................................................................................................17
Signal Descriptions ........................................................................................................................................................................................................ 23
JTAG Timing Specifications ............................................................................................................................................................................................29
List of Tables
Table 1 — Device Configuration ....................................................................................................................................................................................17
T able 2 — Default Programmable Flag Offsets................................................................................................................................................................17
Table 3 — Status Flags for IDT Standard mode .............................................................................................................................................................20
Table 4 — Status Flags for FWFT mode ........................................................................................................................................................................20
Table 5 — I/O V oltage Level Associations.......................................................................................................................................................................21
Table 6 — TSKEW Measurement ...................................................................................................................................................................................27
List of Figures
Figure 1. Quad/Dual Block Diagram ................................................................................................................................................................................5
Figure 2a. AC Test Load................................................................................................................................................................................................15
Figure 2b. Lumped Capacitive Load, Typical Derating ...................................................................................................................................................15
Figure 3. Programmable Flag Offset Programming Methods ........................................................................................................................................... 18
Figure 4. Offset Registers Serial Bit Sequence................................................................................................................................................................ 19
Figure 5. Bus-Matching in Dual mode ............................................................................................................................................................................22
Figure 6. Echo Read Clock and Data Output Relationship ..............................................................................................................................................27
Figure 7. Standard JT AG Timing ...................................................................................................................................................................................28
Figure 8. JT AG Architecture ........................................................................................................................................................................................... 29
Figure 9. T AP Controller State Diagram......................................................................................................................................................................... 30
Figure 10. Master Reset Timing..................................................................................................................................................................................... 33
Figure 1 1. Partial Reset Timing ......................................................................................................................................................................................34
Figure 12. Write Cycle and Full Flag Timing (Quad mode, IDT Standard mode, SDR to SDR) .......................................................................................35
Figure 13. Write Cycle and Full Flag Timing (Quad mode, IDT Standard mode, DDR to DDR).......................................................................................36
Figure 14. Write Cycle and Full Flag Timing (Dual mode, IDT Standard mode, DDR to SDR, x10 In to x20 Out)............................................................37
Figure 15. Write Cycle and Full Flag (Dual mode, IDT Standard mode, SDR to DDR, x20 In to x10 Out).......................................................................38
Figure 16. Write Cycle and Output Ready Timing (Quad mode, FWFT mode, SDR to SDR) ..........................................................................................39
Figure 17. Write Cycle and Output Ready Timing (Quad mode, FWFT mode, DDR to DDR).......................................................................................... 40
Figure 18. Read Cycle, Output Enable and Empty Flag Timing (Quad mode, IDT Standard mode, SDR to SDR)........................................................... 41
Figure 19. Read Cycle, Output Enable and Empty Flag Timing (Quad mode, IDT Standard mode, DDR to DDR) ..........................................................42
Figure 20. Read Cycle and Empty Flag Timing (Dual mode, IDT Standard mode, DDR to SDR, x20 In to x10 Out)....................................................... 43
Figure 21. Read Cycle and Empty Flag Timing (Dual mode, IDT Standard mode, SDR to DDR, x10 In to x20 Out)....................................................... 44
Figure 22. Read Timing and Output Ready Flag (Quad mode, FWFT mode, SDR to SDR) ...........................................................................................45
Figure 23. Read Timing and Output Ready Timing (Quad mode, FWFT mode, DDR to DDR)........................................................................................46
Figure 24. Read Cycle and Read Chip Select (Quad mode, IDT Standard mode, SDR to SDR).................................................................................... 47
Figure 25. Read Cycle and Read Chip Select Timing (Quad mode, FWFT mode, SDR to SDR).................................................................................... 48
Figure 26. Echo Read Clock and Read Enable Operation (Quad mode, IDT Standard mode, DDR to DDR) .................................................................49
Figure 27. Echo RCLK and Echo Read Enable Operation (Quad mode, FWFT mode, SDR to SDR).............................................................................50
Figure 28. Echo Read Clock and Read Enable Operation (Quad mode, IDT Standard mode, SDR to SDR) ..................................................................51
Figure 29. Loading of Programmable Flag Registers (IDT Standard and FWFT modes) ................................................................................................52
Figure 30. Reading of Programmable Flag Registers (IDT Standard and FWFT modes)................................................................................................52
Figure 32. Synchronous Programmable Almost-Empty Flag Timing (Quad mode, IDT Standard and FWFT mode, SDR to SDR) ...................................53
Figure 31. Synchronous Programmable Almost-Full Flag Timing (Quad mode, IDT Standard and FWFT mode, SDR to SDR).......................................53
Figure 33. Asynchronous Programmable Almost-Full Flag Timing (Quad mode, IDT Standard and FWFT mode, SDR to SDR)......................................54
Figure 34. Asynchronous Programmable Almost-Empty Flag T iming (Quad mode, IDT Standard and FWFT mode, SDR to SDR).................................. 54
Figure 35. Power Down Operation................................................................................................................................................................................55
4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync™ DDR/SDR FIFO
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
FEBRUARY 11, 2009
DESCRIPTION
The IDT72T54242/72T54252/72T54262 Quad/Dual TeraSync FIFO
devices are ideal for many applications where data stream convergence and
parallel buffering of multiple data paths are required. These applications may
include communication systems such as data bandwidth aggregation, data
acquisition systems and medical equipment, etc. The Quad/Dual FIFO allows
the user to select either two or four individual internal FIFOs for operation. Each
internal FIFO has its own discrete read and write clock, independent read and
write enables, and separate status flags. The density of each FIFO is fixed.
If Quad mode is selected, there will be a total of eight clock domains, four read
and four write clocks. Data can be written into any of the four write ports totally
independent of any other port, and can be read out of any of the four read ports
corresponding to their respective write port. Each port has its own control
enables and status flags and is 10 bits wide. The device functions as four
separate 10-bit wide FIFOs.
If Dual mode is selected, there will be a total of four clock domains, two read
and two write clocks. Data can be written into any of the two write ports totally
independent of any other port, and can be read out of any of the two read ports
corresponding to their respective write port. Each port has its own control
enables and status flags. All input and output ports have bus-matching
capabilities of x10 or x20 bits wide.
As typical with most IDT FIFOs, two types of data transfer are available, IDT
Standard mode and First Word Fall Through (FWFT) mode. This affects the
device operation and also the flag outputs. The device provides eight flag outputs
per input and output port. A dedicated Serial Clock is used for programming the
flag offsets. This clock is also used for reading the offset values. The serial read
and write operations are performed via the SCLK, FWFT/SI, SWEN, SREN,
and SDO pins. The flag offsets can also be programmed using the JTAG port.
If this option is selected, the SCLK, SWEN, and SREN pins must be disabled.
The Quad/Dual device offers a maximum throughput of 2Gbps per port, with
selectable SDR or DDR data transfer modes for the inputs and outputs. In SDR
mode, the input clock can operate up to 200MHz. Data will transition/latch on
the rising edge of the clock. In DDR mode, the input clock can operate up to 100
MHz, with data transitioning/latched on both rising and falling edges of the clock.
The advantage of DDR is that it can achieve the same throughput as SDR with
only half the number of bits, assuming the frequency is constant. For example,
a 4Gbps throughput in SDR is 100MHz x 40 bits. In DDR mode, it is 100MHz
x 20 bits, because two bits transition per clock cycle.
All Read ports provide the user with a dedicated Echo Read Enable, EREN
and Echo Read Clock, ERCLK output. These outputs aid in high speed
applications where synchronization of the input clock and data of receiving
device is critical. Otherwise known as “Source Synchronous Clocking,” the
echo outputs provide tighter synchronization of the data transmitted from the
FIFO and the read clock interfacing the FIFO outputs.
A Master Reset input is provided and all setup and configuration pins are
latched with respect to a Master Reset pulse. For example, the mode of
operation, bus-matching, and data rate are selected at Master Reset. A Partial
Reset is provided for each internal FIFO. When a Partial Reset is performed
on a FIFO the read and write pointers of that FIFO are reset to the first memory
location. The flag offset values, timing modes, and initial configurations are
retained.
The Quad/Dual device has the capability of operating its I/O at either 2.5V
LVTTL, 1.5V HSTL or 1.8V eHSTL levels. A Voltage Reference, Vref input
is provided for HSTL and eHSTL interfaces. The type of I/O is selected via the
IOSEL pin. The core supply voltage of the device, VCC is always 2.5V, however
the output pins have a separate supply, VDDQ which can be 2.5V, 1.8V, or 1.5V.
The inputs of this device are 3.3V tolerant when VDDQ is set to 2.5V. The device
also offers significant power savings, most notably achieved by the presence
of a Power Down input, PD.
A JTAG test port is provided. The Quad/Dual device has a fully functional
Boundary Scan feature, compliant with IEEE 1149.1 Standard Test Access Port
and Boundary Scan Architecture.
5
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync™ DDR/SDR FIFO
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
FEBRUARY 11, 2009
Figure 1. Quad/Dual Block Diagram
NOTES:
1. This block diagram only shows the architecture for FIFO 0. There are a total of four FIFOs inside this device all with the identical architecture.
2. *Denotes dedicated signal for each internal FIFO inside the device.
OE0*
INPUT
DEMUX
Programmable
Flag Control
SCLK
6158 drw03A
Read Control
Logic
RAM
ARRAY
8,192 x 40
16,384 x 40
32,768 x 40
D0 - D39 (x10, x20, or x40)
10
RDDR
REN0*
RSC0*
RCLK0*
Status Flag
Logic
PAE0*
EF0*
CEF
Echo Outputs ERCLK0*
EREN0*
HSTL I/O
Control IOSEL
OUTPUT
MUX
Q0 - Q39 (x10, x20, or x40)
IW[1:0]
Read Pointer
10
Write Control
Logic
WDDR
*WEN0
*WSC0
*WCLK0
Status Flag
Logic
*PAF0
*FF0
CFF
Write Pointer
JTAG Control
(Boundary Scan)
SWEN
SREN
SDI
SDO
FSEL[1:0]
Reset
Logic
MRS
PRS
TCK
TRST
TMS
TDI
TDO
OW[1:0]
PFM
6
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync™ DDR/SDR FIFO
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
FEBRUARY 11, 2009
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
WEN2
WCS3
GND
GND
VCC
VCC
VCC
D39 Q33
Q36
FF2PAF3GND Q35REN2RCS1
VDDQ
VCC VCC
VCC GND VDDQ
VDDQ VDDQ VDDQ
D0 D1
D6
D3
D13
WCLK0
WCLK1
D38
GND
GND
GND
GND
GND
GND
GND
GND
GND GND
GND
GND
GND
GND
GND
GND
GND
PRS0
PD
VCC
GND
VDDQ OE3
OE0
PRS3VREF MRS
D23
OE1OE2
FWFT/SI
Q9
Q12
Q15
12 34 56 78 9 10111213141516
A1 BALL PAD CORNER
GND
MD
D24
D27
D30
D33
D36
GND
VDDQ
WCLK2
WCLK3
D26
D29
D32
D35
D7
D11
D14
D16
D18
D20
D25
D22
D28
D31
D34
D37 Q30
Q18
EREN1
EREN2
Q21
Q24
Q27
TDI SREN
SCLK
D12
D15
D17
D19
D21
D4 D5 FSEL0
WDDR
D9 OW
FSEL1 VDDQ
IW GND
VCC TRST
GND TMS
TCK
GND
PFM VCC
IOSEL VDDQ
GND GND
VCC VDDQVDDQ VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
GND
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
D2
SWEN
Q6
D10
RDDR VCC
PRS1PRS2
D8
6158 drw03B
U
V
GND
GND
GND
VCC
VCC
Q38
RCLK1
EF3GNDRCS2RCLK2
RCLK3REN3
RCS0
PAE3RCS3
FF3REN1REN0
17 18
ERCLK0
ERCLK1
Q37
Q34
Q1
Q0
Q2
Q7
Q10
Q13
Q32
Q16
Q19
Q20
Q23
Q26
Q29
TDO
SDO
Q5
EREN0
EREN3
Q22
Q25
Q28
Q31
Q8
Q11
Q14
Q17
Q3
Q4
ERCLK2
ERCLK3
RCLK0
Q39
VCCVCC
VCC VDDQ
VCC GND
VCC VDDQ VDDQ
VDDQ
GNDGND
VCC GNDGND GND
GND GND VDDQ
GND
GNDGND
VCC GNDGND GND
GND GND VDDQ
GND
GND
GND
GND
GND GND
GND
VCC GND GND GND GND VDDQGND
GND
GND
VCC GND GND
GND VDDQ
GNDVCCVCC VDDQ
VCC
VCC GND VDDQ
VDDQ VDDQ
GNDGND
VCC
GNDGND
VCC
GNDGND
VCC
GNDGND
VCC
GND VDDQ
GND
GND VDDQ
GND
GND VDDQ
GND
GND VDDQ
GND
WEN3
WEN0WEN1
WCS0WCS1WCS2
GND PAE0EF0PAE1FF1PAE2
PAF0EF1NCEF2
FF0PAF1NCPAF2
PBGA (BB324-1, order code: BB)
TOP VIEW
PIN CONFIGURATION
NOTE:
1. NC = No Connection.
7
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync™ DDR/SDR FIFO
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
FEBRUARY 11, 2009
Symbol Name I/O Type Description
D[39:0] Data Input Bus HSTL-LVTTL These are the data inputs for the device. Data is written into the part via these inputs using the respective
INPUT write port clocks and enables. In Quad mode, these inputs provide four separate busses to the four
separate FIFOs. D[9:0] is FIFO[0], D[19:10] is FIFO[1], D[29:20] is FIFO[2], D[39:30] is FIFO[3].
In Dual mode, these inputs provide two separate busses to the two separate FIFOs. D[19:0] is FIFO[0],
D[39:20] is FIFO[2]. Any unused inputs should be tied to GND.
EF0/1/2/3, Empty Flag 0/1/2/3 HSTL-LVTTL These are the Empty Flags (IDT Standard mode) or Output Ready Flag (FWFT mode) corresponding
OR0/1/2/3 or Output Ready OUTPUT(1) to each of the four FIFOs on the read port. If Dual mode is selected EF1/OR1 and EF3/OR3 are
Flags 0/1/2/3 not used and can be left floating.
ERCLK0/1/2/3 Echo Read Clock HSTL-LVTTL These are the echo clock outputs corresponding to each of the four FIFOs on the read port. The
0/1/2/3 OUTPUT(1) echo read clock is guaranteed to transition after the slowest output data switching. If Dual mode is
selected ERCLK1 and ERCLK3 are not used and can be left floating
EREN0/1/2/3 Echo Read Enable HSTL-LVTTL These are the echo read enable outputs corresponding to each of the four FIFOs on the read port.
0/1/2/3 OUTPUT(1) The echo read enable is synchronous to the RCLK input and is active when a read operation has
occurred and a new word has been placed onto the data output bus. If Dual mode is selected EREN1
and EREN3 are not used and can be left floating.
FF0/1/2/3, Full Flags 0/1/2/3 or HSTL-LVTTL These are the Full Flags (IDT Standard mode) and Input Ready Flags (FWFT mode) corresponding
IR0/1/2/3 Input Ready Flags OUTPUT(1) to each of the four FIFOs on the read port. If Dual mode is selected FF1/IR1 and FF3/IR3 are not
0/1/2/3 used and can be left floating.
FSEL Flag Select HSTL-LVTTL Flag select default offset pins. During master reset, the FSEL pins are used to select one of four default
[1:0] INPUT PAE and PAF offsets. Both the PAE and the PAF offsets are programmed to the same value. Values
are: 00 = 7; 01 = 63; 10 = 127; 11 = 1023. The offset value selected is supplied to all internal FIFOs.
FWFT/SI First Word Fall HSTL-LVTTL During Master Reset, FWFT=1 selects First Word Fall Through mode, FWFT=0 selects IDT Standard
Through/ Serial INPUT mode. After Master Reset this pin is used for the Serial Data input for the programming of the PAE and
Input PAF flag's offset registers.
IOSEL I/O Select CMOS(2) This input determines whether the inputs will operate in LVTTL or HSTL/eHSTL mode. If IOSEL
INPUT pin is HIGH, then all inputs and outputs that are designated "LVTTL or HSTL" in this section will be
set to HSTL. If IOSEL is LOW then LVTTL is selected. This signal must be tied to either VCC or GND
for proper operation.
IW Input Width CMOS(2) If Dual mode is selected , this pin is used during master reset to select the input word width bus size
INPUT for the device. 0 = x10; 1 = x20. If Quad mode is selected the input word width will be x10 regardless
of IW. IW must be tied to VCC or GND and cannot be left floating.
MD Mode CMOS(2) This mode selection pin is used during master reset to select either Quad or Dual mode operation.
INPUT A HIGH on this pin selects Quad mode, a LOW selects Dual mode.
MRS Master Reset HSTL-LVTTL This input provides a full device reset. All set-up pins are latched based on a master reset operation.
INPUT Read and write pointers will be reset to the first location memory. All flag offsets are cleared and
reset to default values determined by FSEL[1:0].
OE0/1/2/3 Output Enable HSTL-LVTTL These are the output enables corresponding to each individual FIFO on the read port. All data outputs
0/1/2/3 INPUT will be placed into High Impedance if this pin is High. These inputs are asynchronous. If Dual mode
is selected OE1 and OE3 are not used and should be tied to VCC.
OW Output Width CMOS(2) If Dual mode is selected, this pin is used during master reset to select the output word width bus size
INPUT for the device. 0 = x10; 1 = x20. If Quad mode is selected the output word width will be x10 regardless
of OW. OW must be tied to VCC or GND and cannot be left floating.
PAE0/1/2/3 Programmable HSTL-LVTTL These are the programmable almost empty flags that can be used as an early indicator for the empty
Almost-Empty OUTPUT(1) boundary of each FIFO. The PAE flags can be set to one of four default offsets determined by the
Flags 0/1/2/3 state of FSEL0 and FSEL1 during master reset. The PAE offset value can also be written and read
from serially by either the JTAG port or the serial programming pins (SCLK, SI, SDO, SWEN, SREN).
This flag can operate in synchronous or asynchronous mode depending on the sate of the PFM pin
during master reset. If Dual mode is selected PAE1 and PAE3 are not used and can be left floating.
PAF0/1/2/3 Programmable HSTL-LVTTL These are the programmable almost full flags that can be used as an early indicator for the full
Almost-Full Flags OUTPUT(1) boundary of each FIFO. The PAF flags can be set to one of four default offsets determined by the
0/1/2/3 state of FSEL0 and FSEL1 during master reset. The PAF offset value can also be written and read
from serially by either the JTAG port or the serial programming pins (SCLK, SI, SDO, SWEN, SREN).
PIN DESCRIPTIONS
8
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync™ DDR/SDR FIFO
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
FEBRUARY 11, 2009
PAF0/1/2/3 Programmable HSTL-LVTTL This flag can operate in synchronous or asynchronous mode depending on the sate of the PFM pin
(Continued) Almost-Full Flags0-3 OUTPUT(1) during master reset. If Dual mode is selected PAF1 and PAF3 are not used and can be left floating.
PD Power Down HSTL-LVTTL This input provides considerable power saving in HSTL/eHSTL mode. If this pin is low, the input
INPUT level translators for all the data input pins, clocks and non-essential control pins are turned off.
When PD is brought high, power-up sequence timing will have to be adhered to before the inputs
will be recognized. It is essential that the user respect these conditions when powering down the
part and powering up the part, so as to not produce runt pulses or glitches on the clocks if the clocks
are free running. PD does not provide any power consumption savings when the inputs are
configured for LVTTL.
PFM Programmable CMOS(2) During master reset, a HIGH on PFM selects synchronous PAE/PAF flag timing, a Low during
Flag Mode INPUT master reset selects asynchronous PAE/PAF flag timing. This pin controls all PAE/PAF flag outputs.
PRS0/1/2/3 Partial Reset HSTL-LVTTL These are the partial reset inputs for each internal FIFO. The read, write, flag pointers, and output
INPUT registers will all be set to zero when partial reset is activated. During partial reset, the existing mode
(IDT or FWFT), input/output bus width and rate mode, and the programmable flag settings are all
retained. If Dual mode is selected, PRS1 and PRS3 are not used and should be tied to VCC.
Q[39:0] Data Output Bus HSTL-LVTTL These are the Data Outputs for the device. Data is read from the part via these outputs using the
OUTPUT(1) respective read port clocks and enables. In Quad mode, these outputs provide four separate busses
from the four separate FIFO's. Q[9:0] is FIFO[0], Q[19:10] is FIFO[1], Q[29:20] is FIFO[2], Q[39:30]
is FIFO[3]. In Dual mode these outputs provide two separate busses from the two separate FIFO's.
Q[19:0] is FIFO[0] and Q[39:20] is FIFO[2].
RCLK0/1/2/3 Read Clock 0/1/2/3 HSTL-LVTTL These are the clock inputs corresponding to each of the four FIFOs on the read port. If Dual mode
INPUT is selected then RCLK1 and RCLK3 are not used and should be tied to GND. In SDR mode data
will be accessed on the rising edge of RCLK when REN and RCS are LOW at the rising edge of RCLK.
In DDR mode data will be accessed on both rising and falling edge of RCLK when REN is LOW.
RCS0/1/2/3 Read Chip Select HSTL-LVTTL These are the read chip select inputs corresponding to each of the four FIFOs on the read port. This
INPUT pin provides synchronous control of the read port and high impedance control of the output data bus.
RCS is only sampled on the rising edge of RCLK. During master or partial reset this input is a don’t
care, if OE is LOW the data inputs will be in Low-Impedance regardless of the state of RCS. If Dual
mode is selected then RCS1 and RCS3 are not used and should be tied to VCC.
REN0/1/2/3 Read Enable HSTL-LVTTL These are the read enable inputs corresponding to each of the four FIFOs on the read port. In SDR,
INPUT when this signal (and RCS) are LOW data will be sent from the FIFO memory to the output bus on
every rising edge of RCLK. In DDR mode, data will be accessed on both rising and falling edges
of RCLK. Note in DDR mode the REN and RCS are only sampled on the rising edge of RCLK. New
data will always begin from the rising edge not the falling edge of RCLK. If Dual mode is selected
then REN1 and REN3 are not used and should be tied to VCC.
RDDR Read Port DDR CMOS(2) During master reset, this pin selects the output port to operate in DDR or SDR format. If RDDR is HIGH,
INPUT then a word is read on the rising and falling edge of the appropriate RCLK0, 1, 2 and 3 input. If RDDR
is LOW, then a word is read only on the rising edge of the appropriate RCLK0, 1, 2 and 3 inputs.
SCLK Serial Clock HSTL-LVTTL Serial clock for writing and reading the PAE and PAF offset registers. On the rising edge of each
INPUT SCLK, when SWEN is low, one bit of data is shifted into the PAE and PAF registers. On the rising edge
of each SCLK, when SREN is low, one bit of data is shifted out of the PAE and PAF offset registers.
The reading of the PAE and PAF registers is non-destructive. If programming of the PAE/PAF offset
registers are done via the JTAG port, this input must be tied to VCC.
SDO Serial Data LVTTL This output is used to read data from the programmable flag offset registers. It is used in conjunction
OUTPUT(1) with the SREN and SCLK signals.
SREN Serial Read Enable HSTL-LVTTL When SREN is brought LOW before the rising edge of SCLK, the contents of the PAE and PAF
INPUT offset registers are copied to a serial shift register. While SREN is maintained LOW, on each rising
edge of SCLK, one bit of data is shifted out of this serial shift register through the SDO output pin.
If programming of the PAE/PAF offset registers is done via the JTAG port, this input must be tied HIGH.
SWEN Serial Write Enable HSTL-LVTTL On each rising edge of SCLK when SWEN is LOW, data from the FWFT/SI pin is serially loaded
INPUT into the PAE and PAF registers. If programming of the PAE/PAF offset registers is done via the
JTAG port, this input must be tied HIGH.
Symbol Name I/O Type Description
PIN DESCRIPTIONS (CONTINUED)
9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync™ DDR/SDR FIFO
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
FEBRUARY 11, 2009
TCK(3) JTAG Clock HSTL-LVTTL Clock input for JTAG function. One of four terminals required by IEEE Standard 1149.1-1990. Test
INPUT operations of the device are synchronous to TCK. Data from TMS and TDI are sampled on the
rising edge of TCK and outputs change on the falling edge of TCK. If the JTAG function is not used
this signal needs to be tied to GND.
TDI(3) JTAG Test Data HSTL-LVTTL One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan
Input INPUT operation, test data serially loaded via the TDI on the rising edge of TCK to either the Instruction
Register, ID Register and Bypass Register. An internal pull-up resistor forces TDI HIGH if left
unconnected.
TDO(3) JTAG Test Data HSTL-LVTTL One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan
Output OUTPUT operation, test data serially loaded output via the TDO on the falling edge of TCK from either the
Instruction Register, ID Register and Bypass Register. This output is high impedance except
when shifting, while in SHIFT-DR and SHIFT-IR controller states.
TMS(3) JTAG Mode Select HSTL-LVTTL TMS is a serial input pin. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs
INPUT the device through its TAP controller states. An internal pull-up resistor forces TMS HIGH if left
unconnected.
TRST(3) JTAG Reset HSTL-LVTTL TRST is an asynchronous reset pin for the JTAG controller. The JTAG TAP controller does not
INPUT automatically reset upon power-up, thus it must be reset by either this signal or by setting TMS= HIGH
for five TCK cycles. If the TAP controller is not properly reset then the FIFO outputs will always be
in high-impedance. If the JTAG function is used but the user does not want to use TRST, then TRST
can be tied with MRS to ensure proper FIFO operation. If the JTAG function is not used then this signal
needs to be tied to GND. An internal pull-up resistor forces TRST HIGH if left unconnected.
WCLK0/1/2/3 Write Clock 0/1/2/3 HSTL-LVTTL These are the clock inputs corresponding to each of the four FIFOs on the write port. If Dual mode
INPUT is selected then WCLK1 and WCLK3 are not used and should be tied to GND. In SDR mode data
will be written on the rising edge of WCLK when WEN and WCS are LOW at the rising edge of WCLK.
In DDR mode data will be written on both rising and falling edge of WCLK when WEN and WCS are
LOW at the rising edge of WCLK.
WCS0/1/2/3 Write Chip Select HSTL-LVTTL These are the write chip select inputs corresponding to each of the four FIFOs on the write port. This
INPUT pin can be regarded as a second write enable input, enabling/disabling write operations. WCS is
only sampled on the rising edge of WCLK. If Dual mode is selected then WCS1 and WCS3 are not
used and should be tied to VCC.
WDDR Write Port DDR CMOS(2) During master reset, this pin selects the input port to operate in DDR or SDR format. If WDDR is HIGH,
INPUT then a word is written on the rising and falling edge of the appropriate WCLK0, 1, 2 and 3 input.
If WDDR is LOW, then a word is written only on the rising edge of the appropriate WCLK0, 1, 2 and
3 inputs.
WEN0/1/2/3 Write Enable 0/1/2/3 HSTL-LVTTL These are the write enable inputs corresponding to each of the four FIFOs on the write port. In SDR,
INPUT when this signal (and WCS) are LOW data on the databus will be written into the FIFO memory on
every rising edge of WCLK. In DDR mode, data will be written on both rising and falling edges of
WCLK. Note in DDR mode the WEN and WCS are only sampled on the rising edge of WCLK. New
data will always begin writing from the rising edge, not the falling edge of WCLK. If Dual mode is
selected then WEN1 and WEN3 are not used and should be tied to VCC.
VCC +2.5V Supply Power These are VCC core power supply pins and must all be connected to a +2.5V supply rail.
VDDQ Output Rail Voltage Power This pin should be tied to the desired voltage rail for providing to the output drivers. Nominally 1.5V
or 1.8V for HSTL, 2.5V for LVTTL.
GND Ground Pin Ground These ground pins are for the core device and must be connected to the GND rail.
Vref Reference voltage Power This is a Voltage Reference input and must be connected to a voltage level determined in the Voltage
Recommended DC Operating Conditions section. This provides the reference voltage when using
HSTL class inputs. If HSTL class inputs are not being used, this pin must be connected to GND.
Symbol Name I/O Type Description
PIN DESCRIPTIONS (CONTINUED)
NOTES:
1. All unused outputs may be left floating.
2 . All CMOS pins should remain unchanged. CMOS format means that the pin is intended to be tied directly to VCC or GND and these particular pins are not tested for VIH or VIL.
3. These pins are for the JTAG port. Please refer to pages 27-31 and Figures 7-9.
10
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync™ DDR/SDR FIFO
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
FEBRUARY 11, 2009
SET-UP, CONFIGURATION & RESET PINS
Regardless of the mode of operation, (Quad or Dual), the following inputs
must be always be used. These inputs must be set-up with respect to master
reset as they are latched during this time.
WDDR – Write Port DDR/SDR selection
RDDR – Read Port DDR/SDR selection
MD – Mode Selection
OW – Output width
IW – Input Width
FSEL[1:0] – Flag offset default values
IOSEL – I/O Level Selection
PFM – Programmable Flag Mode
FWFT/SI – First word Fall Through or IDT Standard mode
QUAD MODE
The following inputs/ outputs should be used when Mux mode is selected
by the user:
INPUTS:
WCLK0, WCLK1, WCLK2, WCLK3 – Four write port clocks
WEN0, WEN1, WEN2, WEN3 – Four write port enables
WCS0, WCS1, WCS2, WCS3 – Four write port chip selects
RCLK0, RCLK1, RCLK2, RCLK3 – Four read port clocks
REN0, REN1, REN2, REN3 – Four read port enables
RCS0, RCS1, RCS2, RCS3, – Four read port chip selects
OE0, OE1, OE2, OE3 – Four read port output enables
OUTPUTS:
ERCLK0, ERCLK1, ERCLK2, ERCLK3 – Four read port echo read clocks
EREN0, EREN1, EREN2, EREN3 – Four read port echo read enables
EF0/OR0, EF1/OR1, EF2/OR2, EF3/OR3 – Four read port Empty/Output
Ready Flags
FF0/IR0, FF1/IR1, FF2/IR2, FF3/IR3 – Four write port full/ input ready flags
PAE0, PAE1, PAE2, PAE3 – Four read port programmable almost empty flags
PAF0, PAF1, PAF2, PAF3 – Four write port programmable almost empty flags
SERIAL PORT
The following pins are used when user programming of the Programmable
Flag offsets is required:
SCLK – Serial Clock
SWEN – Serial Write Enable
SREN – Serial Read Enable
FWFT/SI – Serial Data In
SDO – Serial Data Out
DUAL MODE
The following inputs/ outputs should be used when Mux mode is selected
by the user:
INPUTS:
WCLK0, WCLK2 – Two write port clocks
WEN0, WEN2 – Two write port enables
WCS0, WCS2 – Two write port chip selects
RCLK0, RCLK2 – Two read port clocks
REN0, REN2 – Two read port enables
RCS0, RCS2 – Two read port chip selects
OE0, OE2 – Two read port output enables
OUTPUTS:
ERCLK0, ERCLK2 – Two read port echo read clock outputs
EREN0, EREN2 – Two read port echo read enable outputs
EF0/OR0, EF2/OR2 – Two read port empty/output ready flags
FF0/IR0, FF2/IR2 – Two write port Full/ Input Ready Flags
PAE0, PAE2 – Two read port programmable almost empty flags
PAF0, PAF2 – Two write port programmable almost full flags
QUAD/DUAL I/O USAGE SUMMARY
11
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync™ DDR/SDR FIFO
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
FEBRUARY 11, 2009
ABSOLUTE MAXIMUM RATINGS(1)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. Compliant with JEDEC JESD8-5. VCC terminal only.
Symbol Parameter Conditions Max. Unit
CIN(2,3) Input VIN = 0V 10(3) pF
Capacitance
COUT(1,2) Output VOUT = 0V 10 pF
Capacitance
CAPACITANCE (TA = +25°C, f = 1.0MHz)
NOTES:
1. With output deselected, (OE ≥ VIH).
2. Characterized values, not currently tested.
3. CIN for Vref is 20pF.
Symbol Parameter Min. Typ. Max. Unit
VCC Supply voltage relative to GND 2.375 2.5 2.625 V
VDDQ Output supply voltage ⎯ LVTTL 2.375 2.5 2.625 V
⎯ eHSTL 1 . 7 1 . 8 1 . 9 V
⎯ HSTL 1.4 1.5 1.6 V
VREF(1) Voltage reference input ⎯ eHSTL 0 . 8 0 . 9 1 . 0 V
⎯ HSTL 0.68 0.75 0.9 V
VIH Input high voltage ⎯ LVTTL 1.7 — 3.45 V
⎯ eHSTL VREF+0.2 — VDDQ+0.3 V
⎯ HSTL VREF+0.2 — VDDQ+0.3 V
VIL Input low voltage ⎯ LVTTL -0.3 — 0.7 V
⎯ eHSTL -0.3 — VREF-0.2 V
⎯ HSTL -0.3 — VREF-0.2 V
TAOperating temperature (Commercial) 0 — +70 °C
TAOperating temperature (Industrial) -40 — +85 °C
RECOMMENDED DC OPERATING CONDITIONS
NOTES:
1. VREF is only required for HSTL or eHSTL inputs. VREF should be tied LOW for LVTTL operation.
2. GND = Ground.
Symbol Rating Com'l & Ind'l Unit
VTERM Terminal Voltage –0.5 to +3.6(2) V
with respect to GND
TSTG Storage Temperature –55 to +125 °C
IOUT DC Output Current –50 to +50 mA
TJMaximum Junction Temperature +150 °C
12
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync™ DDR/SDR FIFO
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
FEBRUARY 11, 2009
DC ELECTRICAL CHARACTERISTICS
(Industrial: VCC = 2.5V ± 0.125V, T A = -40°C to +85°C)
Symbol Parameter Min. Max. Un it
ILI Input Leakage Current –10 +10 µA
ILO Output Leakage Current –10 +10 µA
ICC3(2,3) JTAG Input Leakage Current — -16 mA
VOH(1) Output Logic “1” Voltage, IOH = –8 mA @LVTTL VDDQ -0.4 — V
IOH = –8 mA @eHSTL VDDQ -0.4 — V
IOH = –8 mA @HSTL VDDQ -0.4 — V
VOL Output Logic “0” Voltage, IOL = 8 mA @LVTTL — 0 . 4 V
IOL = 8 mA @eHSTL — 0.4 V
IOL = 8 mA @HSTL — 0.4 V
ICC1(2,3,4) Active VCC Current (Quad mode) -- LVTTL — 250(7) mA
(See Note 7 for test conditions) -- eHSTL — 350(7) mA
-- HSTL — 3 5 0(7) mA
ICC2(2,3,4) Active VCC Current (Dual mode) -- LVTTL — 180(7) mA
(See Note 8 for test conditions) -- eHSTL — 295(7) mA
-- HSTL — 2 9 5(7) mA
IDDQ1(2,3,5) Active VDDQ Current (Quad mode) -- LVTTL — 50 mA
(See Note 7 for test conditions) -- eHSTL — 4 0 mA
-- HSTL — 40 mA
IDDQ2(2,3,5) Active VDDQ Current (Dual mode) -- LVTTL — 35 mA
(See Note 8 for test conditions) -- eHSTL — 2 0 mA
-- HSTL — 20 mA
ISB1(2,3,4) Standby VCC Current (Quad mode) -- LVTTL — 110(7) mA
(See Note 9 for test conditions) -- eHSTL — 240(7) mA
-- HSTL — 2 4 0(7) mA
ISB2(2,3,4) Standby VCC Current (Dual mode) -- LVTTL — 100(7) mA
(See Note 10 for test conditions) -- eHSTL — 185(7) mA
-- HSTL — 1 8 5(7) mA
ISB3(2,3,5) Standby VDDQ Current (Quad mode) -- LVTTL — 40 mA
(See Note 9 for test conditions) -- eHSTL — 3 5 mA
-- HSTL — 35 mA
ISB4(2,3,5) Standby VDDQ Current (Dual mode) -- LVTTL — 30 mA
(See Note 10 for test conditions) -- eHSTL — 1 5 mA
-- HSTL — 15 mA
IPD1(3,4) Power Down VCC Current (Quad mode) -- LVTTL — 15(7) mA
(See Note 11 for test conditions) -- eHSTL — 30(7) mA
-- HSTL — 30 (7) mA
IPD2(3,4) Power Down VCC Current (Dual mode) -- LVTTL — 15(7) mA
(See Note 12 for test conditions) -- eHSTL — 30(7) mA
-- HSTL — 30 (7) mA
IPD3(3,5) Power Down VDDQ Current (Quad mode) -- LVTTL — 0.5 mA
(See Note 11 for test conditions) -- eHSTL — 0.5 mA
-- HSTL — 0. 5 mA
IPD4(3,5) Power Down VDDQ Current (Dual mode) -- LVTTL — 0.2 mA
(See Note 12 for test conditions) -- eHSTL — 0.2 mA
-- HSTL — 0. 2 mA
NOTES:
1. Outputs are not 3.3V tolerant.
2. All WCLKs and RCLKs toggling at 20MHz. Data inputs toggling at 10MHz.
3. VCC = 2.5V, OE0-3 = HIGH.
4. Typical ICC1 calculation:for LVTTL I/O: ICC1 (Quad mode) = 11.25 x fs
ICC1 (Dual mode) = 7.74 x fs
for HSTL I/O: ICC1 (Quad mode) = 158 + (11.25 x fs)
ICC1 (Dual mode) = 115 + (7.74 x fs)
where fs = WCLK = RCLK frequency (in MHz) NOTES CONTINUED ON PAGE 13.
13
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync™ DDR/SDR FIFO
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
FEBRUARY 11, 2009
5. Typical IDDQ calculation: With data outputs in High-Impedance: IDDQ (Quad mode) = 0.8 x fs
IDDQ (Dual mode) = 0.3 x fs
With data outputs in Low-Impedance: IDDQ (Quad mode and Dual mode) = CL x VDDQ x fs x N
2000
where fs = WCLK = RCLK frequency (in MHz). CL = capacitance load (pF), N= Number of outputs switching.
6. Total Power consumed: PT = [(VCC x ICC) + (VDDQ x IDDQ)].
7. Maximum value tested wtih RCLK = WCLK = 20MHz at 85°C. Maximum value may differ depending on VCC and temperature.
8. WEN0-3 = REN0-3 = LOW, WCS0-3 = RCS0-3 = LOW, PD = HIGH.
9. WEN0,2 = REN0,2 = LOW, WCS0,2 = RCS0,2 = LOW, PD = HIGH.
10. WEN0-3 = REN0-3 = HIGH, WCS0-3 = RCS0-3 = HIGH, PD = HIGH.
11. WEN0,2 = REN0,2 = HIGH, WCS0,2 = RCS0,2 = HIGH, PD = HIGH.
12. WEN0-3 = REN0-3 = HIGH, WCS0-3 = RCS0-3 = HIGH, PD = LOW.
13. WEN0,2 = REN0,2 = HIGH, WCS0,2 = RCS0,2 = HIGH, PD = LOW.
14
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync™ DDR/SDR FIFO
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
FEBRUARY 11, 2009
AC ELECTRICAL CHARACTERISTICS(1)
(Commercial: VCC = 2.5V ± 0.15V, TA = 0°C to +70°C;Industrial: VCC = 2.5V ± 0.15V, TA = -40°C to +85°C; JEDEC JESD8-A compliant)
Commerical Com'l & Ind'l
IDT72T54242L5 IDT72T54242L6-7
IDT72T54252L5 IDT72T54252L6-7
IDT72T54262L5 IDT72T54262L6-7
Symbol Parameter Min. Max. Min. Max. Unit
fS1 Clock Cycle Frequency (WCLK & RCLK) SDR — 200 — 150 MHz
fS2 Clock Cycle Frequency (WCLK & RCLK) DDR — 100 — 75 MHz
tAData Access Time 0.6 3.6 0.6 3.8 ns
tCLK1 Clock Cycle Time SDR 5 — 6.7 — ns
tCLK2 Clock Cycle Time DDR 10 — 13 — ns
tCLKH1 Clock High Time SDR 2.3 — 2.8 — ns
tCLKH2 Clock High Time DDR 4.5 — 6.0 — ns
tCLKL1 Clock Low Time SDR 2.3 — 2.8 — ns
tCLKL2 Clock Low Time DDR 4.5 — 6.0 — ns
tDS Data Setup Time 1.5 — 2.0 — ns
tDH Data Hold Time 0.5 — 0.5 — ns
tENS Enable Setup Time 1.5 — 2.0 — ns
tENH Enable Hold Time 0.5 — 0.5 — ns
fCClock Cycle Frequency (SCLK) — 10 — 10 MHz
tASO Serial Output Data Access Time — 20 — 20 ns
tSCLK Serial Clock Cycle 100 — 100 — ns
tSCKH Serial Clock High 45 — 45 — ns
tSCKL Serial Clock Low 45 — 45 — ns
tSDS Serial Data In Setup 15 — 15 — n s
tSDH Serial Data In Hold 5 — 5 — n s
tSENS Serial Enable Setup 5 — 5 — ns
tSENH Serial Enable Hold 5 — 5 — n s
tRS(3) Reset Pulse Width 200 — 200 — ns
tRSS Reset Setup Time 15 — 15 — ns
tRSR Reset Recovery Time 10 — 10 — ns
tRSF Reset to Flag and Output Time — 12 — 15 ns
tOLZ (OE - Qn) Output Enable to Output in Low-Impedance 0.6 3.6 0.8 3.8 ns
tOHZ Output Enable to Output in High-Impedance 0.6 3.6 0 .8 3 .8 n s
tOE Output Enable to Data Output Valid 0 .6 3 .6 0 . 8 3 . 8 n s
tRCSLZ RCLK to Active from High-Impedance — 3.6 — 3.8 ns
tRCSHZ RCLK to High-Impedance — 3.6 — 3.8 ns
tPDLZ Power Down to Output Low-Impedance — 19.4 — 19.6 ns
tPDHZ Power Down to Output High-Impedance — 13.5 — 13.7 ns
tPDL Power Down LOW — 19.4 — 19.6 ns
tPDH Power Down HIGH 1 — 1 — µs
tWFF Write Clock to FF or IR — 3.6 — 3.8 ns
tREF Read Clock to EF or OR — 3.6 — 3.8 ns
tPAFS Write Clock to Synchronous Programmable Almost-Full Flag — 3.6 — 3.8 ns
tPAES Read Clock to Synchronous Programmable Almost-Empty Flag — 3.6 — 3.8 ns
tPAFA Write Clock to Asynchronous Programmable Almost-Full Flag — 10 — 12 ns
tPAEA Read Clock to Asynchronous Programmable Almost-Empty Flag — 10 — 12 ns
tERCLK RCLK to Echo RCLK Output — 4.0 — 4.3 ns
tCLKEN RCLK to Echo REN Output — 3.6 — 3.8 n s
tSKEW1 SKEW time between RCLK and WCLK for EF/OR and FF/IR for SDR inputs and outputs 4 — 5 — ns
tSKEW2 SKEW time between RCLK and WCLK for EF/OR and FF/IR in for DDR inputs and outputs 5 — 6 — ns
tSKEW3 SKEW time between RCLK and WCLK for PAE and PAF 5— 6—ns
NOTES:
1. With exception to clock cycle frequency, these parameters apply to both DDR and SDR modes of operation.
2. All AC timings apply to both IDT Standard mode and FWFT mode in both Quad and Dual mode.
3. Pulse width less than the minimum value is not allowed.
4. Values guaranteed by design, not currently tested.
5 . Industrial temperature range product for the 6-7ns speed grade is available as a standard device. All other speed grades available by special order.
15
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync™ DDR/SDR FIFO
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
FEBRUARY 11, 2009
AC TEST LOADS
Figure 2a. AC Test Load
6158 drw04
50Ω
V
DDQ
/2
I/O Z0 = 50Ω
10pF
Input Pulse Levels 0.25 to 1.25V
Input Rise/Fall Times 0.4ns
Input Timing Reference Levels 0.75V
Output Reference Levels 0.75V
HSTL
1.5V AC TEST CONDITIONS
Input Pulse Levels GND to 2.5V
Input Rise/Fall Times 1ns
Input Timing Reference Levels 1.25V
Output Reference Levels 1.25V
LVTTL
2.5V AC TEST CONDITIONS
NOTES:
1. VDDQ = 1.5V.
2. VREF = 0.75V.
NOTE:
1. For LVTTL, VCC = VDDQ = 2.5V.
Input Pulse Levels 0.4 to 1.4V
Input Rise/Fall Times 0.4ns
Input Timing Reference Levels 0.9V
Output Reference Levels 0.9V
EXTENDED HSTL
1.8V AC TEST CONDITIONS
NOTES:
1. VDDQ = 1.8V.
2. VREF = 0.9V.
Figure 2b. Lumped Capacitive Load, Typical Derating
6158 drw04a
6
5
4
3
2
1
20 30 50 80 100 200
Capacitance (pF)
∆t
CD
(Typical, ns)
16
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync™ DDR/SDR FIFO
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
FEBRUARY 11, 2009
OUTPUT ENABLE & DISABLE TIMING
V
IH
OE
V
IL
tOE & tOLZ
100mV
100mV
tOHZ
100mV
100mV
Single Output
Normally
LOW
Single Output
Normally
HIGH
V
OL
V
OH
VCC/2
6158 drw05
Output
Enable
Output
Disable
VCC/2
VCC/2
VCC/2
t
OLZ
Current data in output register
tOE
VCC/2
Output Bus VCC/2
tOHZ
READ CHIP SELECT ENABLE & DISABLE TIMING
NOTES:
1. REN is HIGH.
2. OE is LOW.
VIH
RCS
VIL
tENS
tENH
tRCSLZ
RCLK
VCC
2
VCC
2
100mV
100mV
tRCSHZ
100mV
100mV
Single Output
Normally
LOW
Single Output
Normally
HIGH
VOL
VOH
VCC
2
VCC
2
6158 drw06
t
OLZ
tRCSLZ
Output Bus Current data in output register
tOHZ
VCC
2
VCC
2
NOTES:
1. REN is HIGH.
2. RCS is LOW.
17
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync™ DDR/SDR FIFO
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
FEBRUARY 11, 2009
FUNCTIONAL DESCRIPTION
MASTER RESET & DEVICE CONFIGURATION
During Master Reset the device configuration and settings are determined,
this includes the following:
1. Quad or Dual mode
2. IDT Standard or First Word Fall Through (FWFT) flag timing mode
3. Single or Double Data Rates on both the Write and Read ports
4. Programmable flag mode, synchronous or asynchronous timing
5. Write and Read Port Bus Widths, x10 or x20 (in Dual mode only)
6. Default Offsets for the programmable flags, 7, 63, 127, or 1023
7. LVTTL or HSTL I/O selection
The state of the configuration inputs during master reset will determine which
of the above modes are selected. A master reset comprises of pulsing the MRS
input pin from high to low for a period of time (tRS) with the configuration inputs
held in their respective states. Table 1 summarizes the configuration modes
available during master reset. They are described as follows:
Quad or Dual mode. This mode is selected using the MD input. If during
master reset, MD is HIGH then Quad mode is selected, if MD is LOW then Dual
mode is selected. In Quad mode four independent FIFOs are available, while
in Dual mode two independent FIFOs are available.
IDT Standard or FWFT mode. The two available flag timing modes are
selected using the FWFT/SI input. If FWFT/SI is LOW during master reset then
IDT Standard mode is selected, if it is high then FWFT mode is selected. The
timing modes are described later in this section.
Single Data Rate (SDR) or Double Data Rate (DDR). The input/output
data rates are port selectable. This is a versatile feature that allows the user to
select either SDR or DDR on the write ports and/or read ports of all FIFOs using
the WDDR and RDDR inputs. If WDDR is LOW during master reset then the write
ports of all FIFOs will function in SDR mode; if it is high then the write ports will
be DDR mode. If RDDR is LOW during master reset then the read ports of all
FIFOs will function in SDR mode; if it is high then the read port will be DDR mode.
This feature is described in the Signal Descriptions section.
Programmable Almost Empty/Full Flags. These flags can operate in
either synchronous or asynchronous timing mode. If the programmable flag
input, PFM is HIGH during master reset then all programmable flags will operate
in a synchronous manner, meaning the PAE flags are double buffered and
updated based on the rising edge of its respective read clocks. The PAF flags
are also double buffered and updated based on the rising edge of its respective
write clocks. If it is LOW then all programmable flags will operate in an
asynchronous manner, meaning the PAE and PAF flags are not double buffered
and will update through the internal counter after a nominal delay. This feature
is described in the Signal Descriptions section.
Selectable Bus Width. In Dual mode, the bus width can be selected on
the read and write ports using the IW and OW inputs. If IW is LOW then the write
ports will be 10 bits wide, if IW is HIGH then the write ports will be 20 bits wide.
If OW is LOW then the read ports will be 10 bits wide, if OW is HIGH then the read
ports will be 20 bits wide. Note in Quad mode the inputs and outputs are always
10 bits wide regardless of the state of these pins. This feature is described in the
Signal Descriptions section.
Programmable Flag Offset Values. These offset values can be user
programmed or they can be set to one of four default values during a master
reset. For default programming, the state of the FSEL[1:0] inputs during master
reset will determine the value. Table 2, Default Programmable offsets lists the
four offset values and how to select them. For programming the offset values to
a specific number, use the serial programming signals (SCLK, SWEN, SREN,
FWFT/SI) to load the value into the offset register. You may also use the JTAG
port on this device to load the offset value. Keep in mind that you must disable
the serial programming signals if you plan to use the JTAG port for loading the
offset values. To disable the serial programming signals, tie SCLK, SWEN,
SREN, and FWFT/SI to VCC. A thorough explanation of the serial and JTAG
programming of the flag offset values is provided in the "Serial Write and Reading
of Offset Registers” section.
I/O Level Selection. The I/Os can be selected for either 2.5V LVTTL levels
or 1.5V HSTL / 1.8V eHSTL levels. The state of the IOSEL input will determine
which I/O level will be selected. If IOSEL is HIGH then the applicable I/Os will
be 1.5V HSTL or 1.8V eHSTL, depending on the voltage level applied to VDDQ
and VREF. For HSTL, VDDQ and VREF = 1.5V and for eHSTL VDDQ and VREF
= 1.8V. If IOSEL is LOW then the applicable I/Os will be 2.5V LVTTL. As noted
in the Pin Description section, IOSEL is a CMOS input and must be tied to either
VCC or GND for proper operation.
TABLE 1 — DEVICE CONFIGURATION
PINS VALUES CONFIGURATION
MD 0 Dual mode
1 Quad mode
FWFT/SI 0 IDT Standard mode
1 FWFT mode
WDDR 0 Single Data Rate write port
1 Double Data Rate write port
RDDR 0 Single Data Rate read port
1 Double Data Rate read port
PFM 0 Asynchronous operation of PAE and PAF outputs
1 Synchronous operation of PAE and PAF outputs
IW 0 Write port is 10 bits wide
1 Write port is 20 bits wide in dual mode, 10 bits wider
in Dual mode
OW 0 Read port is 10 bits wide
1 Read port is 20 bits wide in dual mode, 10 bits wider
in Dual mode
FSEL[1:0] 00 Programmable flag registers offset value = 7
01 Programmable flag registers offset value = 63
10 Programmable flag registers offset value = 127
11 Programmable flag registers offset value = 1023
IOSEL 0 All applicable I/Os (except CMOS) are LVTTL
1 Al l applicable I/Os (except CMOS) are HSTL/eHSTL
IDT72T54242
IDT72T54252
IDT72T54262
FSEL1 FSEL0 Offsets n,m
00 7
0163
1 0 127
1 1 1023
TABLE 2 — DEFAULT PROGRAMMABLE
FLAG OFFSETS
NOTES:
1. In default programming, the offset value selected applies to all internal FIFOs.
2. To program different offset values for each FIFO, serial programming must be used.
3 . n is the offset value for PAE, m is the offset value for PAF.
18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync™ DDR/SDR FIFO
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
FEBRUARY 11, 2009
SERIAL WRITING AND READING OF OFFSET REGISTERS
The offset registers can be loaded with a default value or they can be user
programmed with a specific value. One of four default values are loaded based
on the state of the FSEL[1:0] inputs. The flag offset values can be programmed
either through the dedicated serial programming port or the JTAG port. The
dedicated serial port can be used to load or read the contents of the offset
registers. The offset registers are programmed and read sequentially through
a series of shift registers. Each bit in the serial input will shift through the offset
registers and program each FIFOs offset registers.
The serial read and write operations are performed by the dedicated SCLK,
FWFT/SI, SWEN , SREN and SDO pins. The total number of bits required per
device are listed in Figure 3, Programmable Flag Offset Programming
Methods. These bits account for all four PAE/PAF offset registers in the device.
To write to the offset registers, set the serial write enable signal active (LOW),
and on each rising edge of SCLK one bit from the FWFT/SI pin is serially shifted
into the flag offset register chain. Once the complete number of bits has been
programmed into all four registers, the programming sequence is complete. The
programming sequence is listed in Figure 3. To read the values from the offset
registers, set the serial read enable active (LOW). Then on each rising edge
of SCLK, one bit is shifted out to the serial data output. The serial read enable
must be kept LOW throughout the entire read operation. To stop reading the offset
register, disable the serial read enable (HIGH). There is a setup time for reading
the offset registers, as the offset register data for each FIFO is temporarily stored
in a scan chain. When data has been completely read out of the offset registers,
any additional read operations to the offset register will result in zeros as the
output data.
Reading and writing the offset registers can also be accomplished using the
JTAG port. To write to the offset registers using JTAG, set the instructional register
to the offset write command (Hex Value = 0x0008). The JTAG port will load data
into each of the offset registers in a similar fashion as the serial programming
described above. To read the values from the offset registers, set the instructional
register to the offset read command (Hex Value = 0x0007). The TDO of the JTAG
port will output data in a similar fashion as the serial programming described
above.
The number of bits required to load the offset registers is dependent on the
size of the device selected and the width of the I/Os selected. Each offset register
requires 15 bits, 16 bits or 17 bits for the IDT72T54242/72T54252/72T54262
devices respectively. So a total of 120 bits, 128 bits or 136 bits will need to be
loaded into each offset register chain for the IDT72T54242/72T54252/72T54262
devices respectively. If Dual mode is selected, only two of the four offset register
will need to be programmed (PAE/PAF2, PAE/PAF0). Therefore, the total
number of bits required will be half of its Quad mode operation. See Figure 4,
Offset Register Serial Bit Sequence for a mapping of the serial bits to each offset
registers.
6158 drw07
0008 (Hex)
Serial ProgrammingJTAG Programming
Instruction Code
IDT Part Number
01
IDT72T54242
IDT72T54252
IDT72T54262
SWEN SREN
10
0007 (Hex) IDT72T54242
IDT72T54252
IDT72T54262
Quad Mode
120
128
136
120
128
136
Dual Mode
(4)
(IW/OW = x10)
60
64
68
60
64
68
Dual Mode
(IW/OW = x20)
56
60
64
56
60
64
PROGRAMMING INSTRUCTIONS:
JTAG Programming
1. Load JTAG Instruction code in "JTAG Timing Specifications" section.
2. Use rising edge of TCK to clock in the required bits from the TD2 input or to clock out from the TDO output pin.
Serial Programming
1. Set SWEN and SREN as shown above.
2. If reading, SREN LOW will clock data out of the SDO pin on every rising TCK edge. If writing, SWEN LOW will clock in data from the FWFT/SI pin.
NOTES:
1. The programming methods apply to both IDT Standard mode and FWFT mode.
2. The number of bits indicated are for all four PAE/PAF offset registers.
3. SWEN = 0, and SREN = 0 simultaneously are not allowed.
4. In Dual mode (IW/OW = x10), the total number of bits required will be half since only two FIFOs are active.
5. Parallel programming is not available.
Figure 3. Programmable Flag Offset Programming Methods
19
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync™ DDR/SDR FIFO
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
FEBRUARY 11, 2009
TIMING MODES: IDT STANDARD vs FIRST WORD FALL THROUGH
(FWFT) MODE
The IDT72T54242/72T54252/72T54262 support two different timing modes
of operation: IDT Standard mode and First Word Fall Through (FWFT) mode.
The selection of which mode will be used is determined during master reset, by
the state of the FWFT input.
During master reset, if the FWFT pin is LOW, then IDT Standard mode will
be selected. This mode uses the Empty Flag (EF) to indicate whether or not there
are any words present in the FIFO. It also uses the Full Flag (FF) to indicate
whether or not the FIFO has any free space for writing. In IDT Standard mode,
every word read from the FIFO, including the first, must be requested using the
Read Enable (REN), Read Chip Select (RCS), and RCLK.
If the FWFT pin is HIGH during master reset, then FWFT mode will be
selected. This mode uses Output Ready (OR) to indicate whether or not there
is valid data at the data outputs. It also uses Input Ready (IR) to indicate whether
or not the FIFO has any free space for writing. In the FWFT mode, the first word
written to an empty FIFO goes directly to output bus after three RCLK rising
edges. Applying REN = LOW is not necessary, although having RCS = 0 at the
previous rising RCLK is necessary to keep the output from being in high-
impedance. However, subsequent words must be accessed using Read
Enable (REN), Read Chip Select (RCS), and RCLK. Various signals in both
inputs and outputs operate differently depending on which timing mode is in effect.
The timing mode selected affects all internal FIFOs and are not programmed
individually.
IDT STANDARD MODE
In this mode, the status flags FF, PAF, PAE, and EF operate in the manner
outlined in Table 3, Status Flags for IDT Standard Mode. To write data into the
FIFO, Write Enable (WEN), and Write Chip Select (WCS) must be LOW. Data
presented to the DATA IN lines will be clocked into the FIFO on subsequent
transitions of the Write Clock (WCLK). After the first write is performed, the Empty
Flag (EF) will go HIGH. Subsequent writes will continue to fill up the FIFO. The
Programmable Almost-Empty flag (PAE) will go HIGH after n + 1 words have
been loaded into the FIFO, where "n" is the empty offset value. The default
settings for these values are listed in Table 2. This parameter is also user
programmable as described in the Serial Writing and Reading of Offset Registers
section.
Continuing to write data into the FIFO without performing read operations will
cause the Programmable Almost-Full flag (PAF) to go LOW. Again, if no reads
are performed, the PAF will go LOW after (32,768-m) writes for the IDT72T54242,
(65,536-m) writes for the IDT72T54252, and (131,072-m) writes for the
IDT72T54262. In x20 dual mode, PAF will go LOW after (16,384-m) writes for
the IDT72T54242, (32,768-m) writes for the IDT72T54252, and (65,536-m)
writes for the IDT72T54262. The offset “m” is the full offset value. The default
setting for these values are listed in Table 3, Status Flags for IDT Standard
Mode. This parameter is also user programmable. See the section on Serial
Writing and Reading of Offset Registers for details.
When the FIFO is full, the Full Flag (FF) will go LOW, inhibiting further write
operations. If no reads are performed after a reset, FF will go LOW after D writes
to the FIFO, where D = 32,768 writes for the IDT72T54242, 65,536 writes for
the IDT72T54252, and 131,072 writes for the IDT72T54262. In x20 dual mode,
FF will go LOW after 16,384 writes for the IDT72T54242, 32,768 writes for the
IDT72T54252, and 65,536 writes for the IDT72T54262.
If the FIFO is full, the first read operation will cause FF to go HIGH. Subsequent
read operations will cause PAF to go HIGH at the conditions described in Table
3, Status Flags for IDT Standard Mode. If further read operations occur without
write operations, PAE will go LOW when there are n words in the FIFO, where
n is the empty offset value. Continuing read operations will cause the FIFO to
become empty. When the last word has been read from the FIFO, the EF will
go LOW inhibiting further read operations. REN is ignored when the FIFO is
empty, but RCS will continue to determine whether or not the output is in high-
impedance.
When configured in IDT Standard mode, the EF and FF outputs are double
register-buffered outputs. IDT Standard mode is available when the device is
configured in either Single Data Rate or Double Data Rate mode. Relevant
timing diagrams for IDT Standard mode can be found in Figure 10, 11, 12, 13,
14, 15, 16, 17, 18 and 23.
6158 drw08
16 - 30
31 - 45
46 - 60
61 - 75
76 - 90
1 - 15
91 - 105
106 - 120
Serial Bits
IDT72T54252
Quad mode
IDT72T54262
Quad mode
IDT72T54242
Quad mode
IDT72T54242
Dual mode
IW/OW = x10
or
IDT72T54252
IW/OW = x20
IDT72T54252
Dual mode
IW/OW = x10
or
IDT72T54262
IW/OW = x20
IDT72T54242
Dual mode
IW/OW = x20
Offset
Register
17 - 32
33 - 48
49 - 64
65 - 80
81 - 96
1 - 16
97 - 112
113 - 128
18 - 34
35 - 51
52 - 68
69 - 85
86 - 102
1 - 17
103 - 119
120 - 136
⎯
1 - 14
15 - 28
⎯
⎯
⎯
29 - 42
43 - 56
⎯
1 - 15
16 - 30
⎯
⎯
⎯
31 - 45
46 - 60
⎯
1 - 16
17 - 32
⎯
⎯
⎯
33 - 48
49 - 64
PAE3(1)
PAF3(1)
PAE2
PAF2
PAE1(1)
PAF1(1)
PAE0
PAF0
IDT72T54262
Dual mode
IW/OW = x10
⎯
1 - 17
18 - 34
⎯
⎯
⎯
35 - 51
52 - 68
Figure 4. Offset Registers Serial Bit Sequence
NOTES:
1. These registers are not used in Dual mode. They are not programmed or read in the serial chain.
2. In all modes, the higher numbered bit is the MSB. For example, in the IDT72T54242 in Quad mode, the first bit is the LSB for PAE3.
20
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync™ DDR/SDR FIFO
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
FEBRUARY 11, 2009
FIRST WORD FALL THROUGH MODE (FWFT)
In this mode, the status flags OR, IR, PAE, and PAF operate in the manner
outlined in Table 4, Status Flags for FWFT Mode. To write data into to the FIFO,
WEN, and WCS must be LOW. Data presented to the DATA IN lines will be
clocked into the FIFO on subsequent transitions of WCLK. After the first write is
performed, the Output Ready (OR) flag will go LOW. Subsequent writes will
continue to fill up the FIFO. PAE will go HIGH after n + 2 words have been loaded
into the FIFO, where n is the empty offset value. The default setting for these
values are listed in Table 4, Status Flags for FWFT Mode. This parameter is
also user programmable as described in the Serial Writing and Reading of Offset
Registers section.
Continuing to write data into the FIFO without performing read operations will
cause the Programmable Almost-Full flag (PAF) to go LOW. Again, if no reads
are performed, the PAF will go LOW after (32,769-m) writes for the IDT72T54242,
(65,537-m) writes for the IDT72T54252, and (131,073-m) writes for the
IDT72T54262. In x20 dual mode, PAF will go LOW after (16,385-m) writes for
the IDT72T54242, (32,769-m) writes for the IDT72T54252, and (65,537-m)
writes for the IDT72T54262. The offset “m” is the full offset value. The default
setting for these values are listed in Table 4, Status Flags for FWFT Mode. This
parameter is also user programmable. See the section on serial writing and
reading of offset registers for details.
When the FIFO is full, the Input Ready (IR) will go LOW, inhibiting further write
operations. If no reads are performed after a reset, IR will go LOW after D writes
to the FIFO, where D = 32,769 writes for the IDT72T54242, 65,537 writes for
the IDT72T54252, and 131,073 writes for the IDT72T54262. In x20 dual mode,
FF will go LOW after 16,385 writes for the IDT72T54242, 32,769 writes for the
IDT72T54252, and 65,537 writes for the IDT72T54262.
If the FIFO is full, the first read operation will cause IR to go HIGH. Subsequent
read operations will cause PAF to go HIGH at the conditions described in Table
4, Status Flags for FWFT Mode. If further read operations occur without write
operations, PAE will go LOW when there are n words in the FIFO, where n is
the empty offset value. Continuing read operations will cause the FIFO to
become empty. When the last word has been read from the FIFO, the OR will
go HIGH inhibiting further read operations. REN is ignored when the FIFO is
empty, but RCS will continue to determine whether or not the output is in high-
impedance.
When configured in FWFT mode, the OR flag output is triple register-buffered
and the IR flag output is double register-buffered. Relevant timing diagrams for
FWFT mode can be found in Figure 19, 20, 21, 22 and 24.
6158 drw09
0
1 to n
16,384
FF PAF PAE EF
HHLH
HLHH
LLHH
IDT72T54242
Dual mode
IW/OW = x20
Number of
Words in
FIFO
IDT72T54242
Quad mode or Dual mode
IW/OW = x10
or
IDT72T54252
Dual mode IW/OW = x20
IDT72T54252
Quad mode or Dual mode
IW/OW = x10
or
IDT72T54262
Dual mode IW/OW = x20
IDT72T54262
Quad mode or Dual mode
IW/OW = x10
16,384 - (m) to 16,383
0
1 to n
32,768
32,768 - (m) to 32,767
0
1 to n
65,536
65,536 - (m) to 65,535
0
1 to n
131,072
131,072 - (m) to 131,071
HHLL
0
1 to n+1
16,385
IR PAF PAE OR
LHLL
LLHL
HLHL
IDT72T54242
Dual mode
IW/OW = x20
Number of
Words in
FIFO
IDT72T54242
Quad mode or Dual mode
IW/OW = x10
or
IDT72T54252
Dual mode IW/OW = x20
IDT72T54252
Quad mode or Dual mode
IW/OW = x10
or
IDT72T54262
Dual mode IW/OW = x20
IDT72T54262
Quad mode or Dual mode
IW/OW = x10
16,385 - (m) to 16,384
0
1 to n+1
32,769
32,769 - (m) to 32,768
0
1 to n+1
65,537
65,537 - (m) to 65,536
0
1 to n+1
131,073
131,073 - (m) to 131,072
LHLH
NOTE:
1. See Table 2 for values for n, m. Values n,m may be different for each FIFO.
NOTE:
1. See Table 2 for values for n, m. Values n,m may be different for each FIFO.
TABLE 3 — STATUS FLAGS FOR IDT STANDARD MODE
TABLE 4 — STATUS FLAGS FOR FWFT MODE
21
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync™ DDR/SDR FIFO
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
FEBRUARY 11, 2009
SELECTABLE MODES
This device is capable of operating in two different modes: Quad mode or Dual
mode. In the Quad mode there are four independent FIFOs available, with the
input and output bus widths set to 10 bits wide for each FIFO. A total of eight
independent clock inputs are available– four RCLKs and four WCLKs. Each
FIFO has independent read and write controls, output enable controls, as well
as individual status flags EF/OR, FF/IR, PAE, and PAF. Also available are echo
outputs ERCLK and EREN for each individual FIFO to aid high-speed operation
where synchronizing data is critical.
In the Dual mode there are two independent FIFOs available, with the input
and output bus widths each selectable between x10 or x20. Bus-matching is
available in this mode, allowing for more flexibility. A total of four independent
clock inputs are available, two RCLKs and two WCLKs. Each FIFO has
independent read and write controls– output enable controls, as well as
individual status flags EF/OR, FF/IR, PAE, and PAF. Also available are echo
outputs ERCLK and EREN for each individual FIFO to aid high-speed operation
where synchronizing data is critical.
HSTL/LVTTL I/O
The inputs and outputs of this device can be configured for either LVTTL or
HSTL/eHSTL operation. If the IOSEL pin is HIGH during master reset, then all
applicable LVTTL or HSTL signals will be configured for HSTL/eHSTL
operating voltage levels. To select between HSTL or eHSTL VREF must be
driven to 1.5V or 1.8V respectively. Typically a logic HIGH in HSTL would be
VREF + 0.2V and a logic LOW would be VREF – 0.2V.
If the IOSEL pin is LOW during master reset, then all applicable LVTTL or
HSTL signals will be configured for LVTTL operating voltage levels. In this
configuration VREF must be set to GND. Table 5 illustrates which pins are and
LVTTL/HSTL/eHSTL SELECT STATIC CMOS SIGNALS
Write Port Read Port JTAG Signal Pins Serial Clock Port Static Pins
D[39:0] Q[39:0] TCK FSEL[1:0] SCLK IOSEL
WCLK0/1/2/3 RCLK0/1/2/3 TRST PD SREN IW
WEN0/1/2/3 REN0/1/2/3 TMS MRS SWEN OW
WCS0/1/2/3 RCS0/1/2/3 TDI PRS0/1/2/3 FWFT/SI MD
FF/IR0/1/2/3 EF/OR0/1/2/3 TDO FWFT/SI SDO PFM
PAF0/1/2/3 OE0/1/2/3 RDDR
PAE0/1/2/3 WDDR
ERCLK0/1/2/3
EREN0/1/2/3
TABLE 5 — I/O VOLTAGE LEVEL ASSOCIATIONS
are not associated with this feature. Note that all “Static Pins” must be tied to VCC
or GND. These pins are LVTTL only and are purely device configuration pins.
Note the IOSEL pin should be tied HIGH or LOW and cannot toggle before and
after master reset.
BUS MATCHING
In the Dual mode operation, the write and read port have bus-matching
capability such that the input and output busses can each be either 10 bits or
20 bits wide. The bus width of both the input and output port is determined during
master reset using the input (IW) and output (OW) widths setup pins. The selected
port width is applied to both FIFO ports, such that both FIFOs will be configured
for either x10 or x20 bus widths. When writing or reading data from a FIFO the
number of memory locations available to be read will depend on the bus width
selected and the density of the device.
If the write/read ports are 10 bits wide, this provides the user with a FIFO depth
of 32,768 x 10 for the IDT72T54242, 65,536 x 10 for the IDT72T54252, or
131,072 x 10 for the IDT72T54262. If the write/read ports are 20 bits wide, this
provides the user with a FIFO depth of 16,384 x 20 for the IDT72T54242,
32,768 x 20 for the IDT72T54252, or 65,536 x 20 for the IDT72T54262. The
FIFO depths will always have a fixed density of 327,680 bits for the IDT72T54242,
655,360 bits for the IDT72T54252 and 1,310,072 bits for the IDT72T54262
regardless of bus-width configuration on the write/read port. When the device
is operating in double data rate, the word is twice as large as in single data rate
since one word consists of both the rising and falling edge of clock. Therefore
in DDR, the FIFO depths will be half of what it is mentioned above. For instance,
if the write/read port is 10 bits wide, the depth of each FIFO is 16,384 x 10 for
the IDT72T54242, 32,768 x 10 for the IDT72T54252, or 65,536 x 10 for the
IDT72T54262. See Figure 5, Bus-Matching in Dual mode for more information.
NOTE:
1. In Dual mode, not all available signals will be used. Signals with a designation of 1 and 3 are not used.
22
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync™ DDR/SDR FIFO
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
FEBRUARY 11, 2009
Figure 5. Bus-Matching in Dual mode
6158 drw10
A
Write to
FIFO 0 and FIFO 2
INPUT PORT BUS-WIDTH x20
OUTPUT PORT BUS-WIDTH x20
BCD
H
D39-D30 D29-D20 D19-D10 D9-D0
FIFO 0FIFO 0FIFO 2FIFO 2
ARead from
FIFO 0 and FIFO 2
BCD
D39-D30 D29-D20 D19-D10 D9-D0
FIFO 0FIFO 0FIFO 2FIFO 2
(a) x20 INPUT to x20 OUTPUT
A1st Read from
FIFO 0 and FIFO 2
C
D39-D30 D29-D20 D19-D10 D9-D0
INPUT PORT BUS-WIDTH x20
OUTPUT PORT BUS-WIDTH x10
B2nd Read from
FIFO 0 and FIFO 2
D
D39-D30 D29-D20 D19-D10 D9-D0
INPUT PORT BUS-WIDTH x10
OUTPUT PORT BUS-WIDTH x10
(b) x20 INPUT to x10 OUTPUT
A1st Write to
FIFO 0 and FIFO 2
B
D39-D30 D29-D20 D19-D10 D9-D0
C2nd Write to
FIFO 0 and FIFO 2
D
D39-D30 D29-D20 D19-D10 D9-D0
FIFO 0FIFO 0FIFO 2FIFO 2
(c) x10 INPUT to x10 OUTPUT
A1st Read from
FIFO 0 and FIFO 2
B
D39-D30 D29-D20 D19-D10 D9-D0
C2nd Read from
FIFO 0 and FIFO 2
D
D39-D30 D29-D20 D19-D10 D9-D0
FIFO 0FIFO 0FIFO 2FIFO 2
ARead from
FIFO 0 and FIFO 2
CBD
D39-D30 D29-D20 D19-D10 D9-D0
(d) x10 INPUT to x20 OUTPUT
INPUT PORT BUS-WIDTH x10
OUTPUT PORT BUS-WIDTH x20
IW OW
H
H
IW OW
L
L
IW OW
L
L
IW OW
H
FIFO 0FIFO 0FIFO 2FIFO 2
FIFO 0FIFO 0FIFO 2FIFO 2
FIFO 0FIFO 0FIFO 2FIFO 2
FIFO 0FIFO 0FIFO 2FIFO 2
FIFO 0FIFO 0FIFO 2FIFO 2
23
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync™ DDR/SDR FIFO
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
FEBRUARY 11, 2009
SIGNAL DESCRIPTIONS
INPUTS:
DATA INPUT BUS (D[39:0])
The data input busses are 10 bits wide in Quad mode and 20 or 10-bits wide
in Dual mode. In Quad mode, D[9:0] are data inputs for FIFO0, D[19:10] are
for FIFO1, D[29:20] are for FIFO2, and D[39:30] are for FIFO3. In Dual mode,
D[19:0] are data inputs for FIFO0 and D[39:20] are for FIFO2 for the 20-bit wide
data bus. D[9:0] are data inputs for FIFO0 and D[29:20] are data inputs for
FIFO2 for the 10-bit wide data bus.
MASTER RESET (MRS)
There is a single master reset available for all internal FIFOs in this device.
A master reset is initiated whenever the MRS input is taken to a LOW state. This
operation sets the internal read and write pointers of all FIFOs to the first location
in memory. The programmable almost empty flag will go LOW and the almost
full flags will go HIGH.
If FWFT/SI signal is LOW during master reset then IDT Standard mode is
selected. This mode utilizes the empty and full status flags from the EF/OR and
FF/IR dual-purpose pin. During master reset, all empty flags will be set to LOW
and all full flags will be set to HIGH.
If FWFT/SI signal is HIGH during master reset, then the First Word Fall
Through mode is selected. This mode utilizes the input read and output ready
status flags from the EF/OR and FF/IR dual-purpose pin. During master reset,
all input ready flags will be set to LOW and all output ready flags will be set to
HIGH.
All device configuration pins such as MD, OW, IW, WDDR, RDDR, IOSEL,
PFM, FSEL[1:0] and FWFT/SI need to be defined before the master reset cycle.
During a master reset the output registers are initialized to all zeros. If the output
enables are LOW during master reset, then the output bus will be LOW. If the
output enable(s) are HIGH during master reset, then the output bus will be in
high-impedance. RCS has no affect on the data outputs during master reset. If
the output width OW is configured to x10 in Dual mode, then the unused outputs
Q[19:10] and Q[39:30] will be in high-impedance. A master reset is required
after power up before a write operation to any FIFO can take place. Master reset
is an asynchronous signal and thus the read and write clocks can be free-
running or idle during master reset. See Figure 10, Master Reset Timing, for
the associated timing diagram.
PARTIAL RESET (PRS0/1/2/3)
A partial reset is a means by which the user can reset both the read and write
pointers of each individual FIFO inside the device without changing the FIFO's
configuration. There are four dedicated partial reset signals (two in Dual mode)
that each correspond to an individual FIFO. There are no restrictions as to when
partial reset can be performed in either operating modes.
During partial reset, the internal read and write pointers are set to the first
location in memory, PAE goes LOW and PAF goes HIGH. Whichever timing
mode was active at the time of Partial Reset will remain active after Partial Reset.
If IDT Standard Mode is active, then FF will go HIGH and EF will go LOW. If
the First Word Fall Through mode is active, then OR will go HIGH and IR will
go LOW.
Following Partial Reset, all values held in the offset registers remain
unchanged. The output registers are initialized to all zeros. All other
configurations set up during master reset remain unchanged. PRS is an
asynchronous signal. See Figure 11, Partial Reset Timing, for the associated
timing diagram.
FIRST WORD FALL THROUGH/SERIAL IN (FWFT/SI)
This is a dual purpose pin. During master reset, the state of the FWFT/SI input
determines whether the device will operate in IDT Standard mode or First Word
Fall Through (FWFT) mode.
If FWFT/SI is LOW before the falling edge of master reset, then IDT Standard
mode will be selected. This mode uses the Empty Flag (EF) to indicate whether
or not there are any words present in the FIFOs’ memory. It also uses the Full
Flag (FF) to indicate whether or not the FIFOs’ memory has any free space for
writing. In IDT Standard mode, every word read from the FIFOs, including the
first, must be requested using the Read Enable (REN), Read Chip Select (RCS)
and RCLK.
If FWFT/SI is HIGH before the falling edge of master reset, then FWFT mode
will be selected. This mode uses Output Ready (OR) to indicate whether or not
there is valid data in the output register. It also uses Input Ready (IR) to indicate
whether or not the FIFO's memory has any free space for writing. In other words,
they are the inverse of the empty and full flags. In the FWFT mode, the first word
written to an empty FIFO goes directly to data outputs after three RCLK rising
edges, provided that the first RCLK meets the tSKEW parameter. There may be
a one RCLK cycle delay if tSKEW is not met. REN and RCS do not need to be
enabled. Subsequent words must be accessed using the REN, RCS, and
RCLK.
The state of the FWFT/SI input must be kept at the present state for the minimum
of the reset recovery time (tRSR) after master reset. After this time, the FWFT/
SI acts as a serial input for loading PAE and PAF offsets into the programmable
offset registers. The serial input is used in conjunction with SCLK, SWEN, SREN,
and SDO to access the offset registers. Serial programming using the FWFT/
SI pin functions the same way in both IDT Standard and FWFT modes.
WRITE CLOCK (WCLK0/1/2/3)
There are a possible total of four write clocks (or two in Dual mode) available
in this device depending on the mode selected, each corresponding to the
individual FIFOs in memory. A write can be initiated on the rising (or falling) edge
of the WCLK input. If the write double data rate (WDDR) mode pin is tied HIGH,
data will be written on both the rising and falling edge of WCLK0/1/2/3, provided
that WEN0/1/2/3 and WCS0/1/2/3 are enabled on the rising edge of WCLK 0/
1/2/3. If WDDR is tied LOW, data will be written only on the rising edge of WCLK0/
1/2/3 provided that WEN0/1/2/3 and WCS 0/1/2/3 are enabled. Each write
clock is completely independent from the others.
Data setup and hold times must be met with respect to the LOW-to-HIGH (and
HIGH-to-LOW in DDR) transition of the write clock. It is permissible to stop the
write clocks, for asynchronous operations. Note that while the write clocks are
idle, the FF0/1/2/3 and PAF0/1/2/3 flags will not be updated unless the port is
operating in asynchronous timing mode (PFM=0). The write clocks can be
independent or coincident with one another. In Dual mode, the unused clocks
(WCLK1 and WCLK3) should be tied to GND.
WRITE ENABLE (WEN0/1/2/3)
There are a total of four write enables (or two in Dual mode) available in this
device depending on the mode selected, one for each individual FIFO. When
the write enable input is LOW on the rising edge of WCLK in single data rate mode,
data is loaded on the rising edge of every WCLK cycle, provided the device
is not full and the write chip select (WCS) is enabled. The setup and hold times
are referenced with respect to the rising edge of WCLK only. When the write
enable input is LOW on the rising edge of WCLK in double data rate, data is
loaded into any of the FIFOs on the rising and falling edge of every WCLK cycle,
provided the device is not full and the write chip select (WCS) is enabled on the
24
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync™ DDR/SDR FIFO
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
FEBRUARY 11, 2009
rising edge of WCLK. In this mode, the data setup and hold times are referenced
with respect to the rising and falling edge of WCLK. Note that WEN and WCS
are sampled only on the rising edge of WCLK in either data rates.
Data is stored in the FIFOs’ memory sequentially and independently of any
ongoing read operation. When the write enables or write chip selects are HIGH,
no new data is written into the corresponding FIFO on each WCLK cycle. Each
write enable operates independently of the others. In Dual mode, the unused
write enables (WEN1 and WEN3) should be tied to VCC.
WRITE CHIP SELECT (WCS0/1/2/3)
There are a total of four write chip selects (or two in Dual mode) available
in this device depending on the mode selected, one for each individual FIFO.
The write chip selects disables all data bus inputs if it is held HIGH. To perform
normal write operations, the write chip select must be enabled, (held LOW). The
four write chip selects are completely independent of one another. When the
write chip select is LOW on the rising edge of WCLK in single data rate mode,
data is loaded on the rising edge of every WCLK cycle, provided the device
is not full and the write enable (WEN) of the corresponding FIFO is LOW.
When the write chip select is LOW on the rising edge of WCLK in double data
rate mode, data is loaded into any of the FIFOs on the rising and falling edge
of every WCLK cycle, provided the device is not full and the write enable (WEN)
of the corresponding FIFO is LOW on the rising clock edge.
When the write chip select is HIGH on the rising edge of WCLK in single data
rate mode, the write port is disabled and no words are written into the FIFO
memory, on the rising edge of WCLK, even if WEN is LOW. If the write chip select
is HIGH on the rising edge of WCLK in double data rate mode, the write port
is disabled and no words are written into the FIFO memory on the rising or falling
edge of WCLK, even if WEN is LOW. Note that WCS is sampled on the rising
edge of WCLK only in either data rate. In Dual mode, the unused write chip
selects (WCS1 and WCS3) should be tied to VCC.
WRITE DOUBLE DATA RATE (WDDR)
When the write double data rate (WDDR) pin is HIGH, the write port will be
set to double data rate mode. In this mode, all write operations are based on
the rising and falling edge of the write clocks, provided that write enables and
write chip selects are LOW for the rising clock edges. In double data rate the write
enable signals are sampled with respect to the rising edge of write clock only,
and a word will be written to both the rising and falling edge of write clock
regardless of whether or not write enable is active on the falling edge of write
clock.
When WDDR is LOW, the write port will be set to single data rate mode. In
this mode, all write operations are based on only the rising edge of the write
clocks, provided that write enables and write chip selects are LOW during the
rising edge of write clock. This pin should be tied HIGH or LOW and cannot
toggle.
READ CLOCK (RCLK0/1/2/3)
There are a total of four read clocks (or two in Dual mode) available in this
device depending on the mode selected, each corresponding to the individual
FIFOs in memory. A read can be initiated on the rising (or falling) edge of the
RCLK input. If the read double data rate (RDDR) mode pin is tied HIGH, data
will be read on both the rising and falling edge of RCLK0/1/2/3, provided that
REN0/1/2/3 and RCS0/1/2/3 are enabled on the rising edge of RCLK0/1/2/
3. If RDDR is tied LOW, data will be read only on the rising edge of RCLK0/1/
2/3 provided that REN0/1/2/3 and RCS0/1/2/3 are enabled. Each read clock
is completely independent from the others.
There is an associated data access time (tA) for the data to be read out of the
FIFOs. It is permissible to stop the read clocks. Note that while the read clocks
are idle, the EF/0/1/2/3 and PAE0/1/2/3 flags will not be updated unless the part
is operating in asynchronous timing mode (PFM=0). The write and read clocks
can be independent or coincident. In Dual mode, the unused clocks (RCLK1
and RCLK3) should be tied to GND.
READ ENABLE (REN0/1/2/3)
There are a total of four read enables (or two in Dual mode) available in this
device depending on the mode selected, one for each individual FIFOs . When
the read enable input is LOW on the rising edge of RCLK in single data rate mode,
data will be read on the rising edge of every RCLK cycle, provided the device
is not empty and the read chip select (RCS) is enabled. The associated data
access time (tA) is referenced with respect to the rising edge of RCLK. When
the read enable input is LOW on the rising edge of WCLK in double data rate
mode, data will be read on the rising and falling edge of every RCLK cycle,
provided the device is not empty and RCS is enabled. In this mode, the data
access times are referenced with respect to the rising and falling edges of RCLK.
Note that REN, and RCS are sampled only on the rising edge of RCLK in either
data rate.
Data read from the FIFO's memory sequentially and independently of any
ongoing write operation. When the read enables or read chip selects are HIGH,
no new data is read on each RCLK cycle. Each read enable operates
independently of the others.
To prevent reading from an empty FIFO in the IDT Standard mode, the empty
flag of each FIFO will go LOW with respect to RCLK, when the total number of
words in the FIFO has been read, thus inhibiting further read operations. Upon
the completion of a valid write cycle, the empty flag will go HIGH with respect
to RCLK two cycles later, thus allowing another read to occur similarly, for FWFT
mode, the output ready flag of each FIFO will go HIGH with respect to RCLK
when the total number of words in the FIFO has been read out. In Dual mode,
the unused read enables (REN1 and REN3) should be tied to VCC.
READ CHIP SELECT (RCS0/1/2/3)
There are a total of four read chip selects (or two in Dual mode) available
in this device, each corresponding to an individual FIFO. The read chip select
inputs provide synchronous control of the read port. When the read chip select
is held LOW, the next rising edge of the corresponding RCLK will enable the
output bus. When the read chip select goes HIGH, the next rising edge of RCLK
will send the output bus into high-impedance and prevent that RCLK from
initiating a read, regardless of the state of REN. During a master or partial reset
the read chip select input has no effect on the output bus– output enable is the
only input that provides high-impedance control of the output bus. If output enable
is LOW, the data outputs will be active regardless of read chip select until the first
rising edge of RCLK after a reset is complete. Afterwards if read chip select is
HIGH the data outputs will go to high-impedance. Each read chip select is
completely independent of the others.
The read chip select inputs do not affect the updating of the flags. For example,
when the first word is written to any/all empty FIFOs, the empty flags will still go
from LOW to HIGH based on a rising edge of the RCLK, regardless of the state
of the read chip select inputs. Also, when operating the FIFO in FWFT mode
the first word written to any/all empty FIFOs will still be clocked through to the
output bus on the third rising edge of RCLK, regardless of the state of read chip
select inputs, assuming that the tSKEW parameter is met. For this reason the user
should pay extra attention to the read chip selects when a data word is written
to any/all empty FIFOs in FWFT mode. If the read chip select inputs are HIGH
when an empty FIFO is written into, the first word will fall through to the output
register but will not be available on the outputs because they are in high-
impedance. The user must enable read chip select on the rising edge of RCLK
while disabling REN to access this first word. In Dual mode, the unused read
25
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync™ DDR/SDR FIFO
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
FEBRUARY 11, 2009
chip selects (RCS1 and RCS3) should be tied to VCC. Refer to Figures 23 and
24, Read Cycle and Read Chip Select for the associated timing diagrams.
READ DOUBLE DATA RATE (RDDR)
When the read double data rate (RDDR) pin tied HIGH, the read port will be
set to double data rate mode. In this mode, all read operations are based on
the rising and falling edge of the read clocks, provided that read enables and
read chip selects are LOW. In double data rate the read enable signals are
sampled with respect to the rising edge of read clock only, and a word will be
read from both the rising and falling edge of read clock regardless of whether
or not read enable and read chip select are active on the falling edge of read
clock.
When RDDR is tied LOW, the read port will be set to single data rate mode.
In this mode, all read operations are based on only the rising edge of the read
clocks, provided that read enables and read chip selects are LOW during the
rising edge of read clock. This pin should be tied HIGH or LOW and cannot toggle
before or after master reset.
OUTPUT ENABLE (OE0/1/2/3)
There are total of four asynchronous output enables (two in Dual mode)
available in this device, each corresponding to an individual FIFO in memory.
When the output enable inputs are LOW, the output bus of each individual FIFO
becomes active and drives the data currently in the output register. When the
output enable inputs are HIGH, the output bus of each individual FIFO goes into
high-impedance. During master or partial reset the output enable is the only input
that can place the output data bus into high-impedance. During reset the read
chip select input has no effect on the output data bus. Each output enable input
is completely independent from the others. In Dual mode, the unused output
enables (OE1 and OE3) should be tied to VCC.
I/O SELECT (IOSEL)
The inputs and outputs of this device can be configured for either LVTTL or
HSTL/eHSTL operation. If the IOSEL pin is HIGH during master reset, then all
applicable LVTTL or HSTL signals will be configured for HSTL/eHSTL
operating voltage levels. To select between HSTL or eHSTL VREF must be
driven to 1.5V or 1.8V respectively. If the IOSEL pin is LOW during master reset,
then all applicable LVTTL or HSTL programmable pins will be configured for
LVTTL operating voltage levels. In this configuration VREF should be set to
GND. This pin should be tied HIGH or LOW and cannot toggle before or after
master reset. Please refer to table 5 for a list of LVTTL/HSTL/eHSTL program-
mable pins.
POWER DOWN (PD)
This device has a power down feature intended for reducing power
consumption for HSTL/eHSTL configured inputs when the device is idle for a
long period of time. By entering the power down state certain inputs can be
disabled, thereby significantly reducing the power consumption of the part. All
WEN and REN signals must be disabled for a minimum of four WCLK and RCLK
cycles before activating the power down signal. The power down signal is
asynchronous and needs to be held LOW throughout the desired power down
time. During power down, the following conditions for the inputs/outputs signals
are:
•All data in FIFO(s) memory are retained.
•All data inputs become inactive.
•All write and read pointers maintain their last value before power down.
•All enables, chip selects, and clock input pins become inactive.
•All data outputs become inactive and enter high-impedance state.
•All flag outputs will maintain their current states before power down.
•All programmable flag offsets maintain their values.
•All echo clocks and enables will become inactive and enter high-
impedance state.
•The serial programming and JTAG port will become inactive and enter
high-impedance state.
•All setup and configuration CMOS static inputs are not affected, as these
pins are tied to a known value and do not toggle during operation.
All internal counters, registers, and flags will remain unchanged and maintain
their current state prior to power down. Clock inputs can be continuous and free-
running during power down, but will have no affect on the part. However, it is
recommended that the clock inputs be low when the power down is active. To
exit power down state and resume normal operations, disable the power down
signal by bringing it HIGH. There must be a minimum of 1µs waiting period before
read and write operations can resume. The device will continue from where it
had stopped and no form of reset is required after exiting power down state. The
power down feature does not provide any power savings when the inputs are
configured for LVTTL operation. However, it will reduce the current for I/Os that
are not tied directly to VCC or GND. See Figure 35, Power Down Operation,
for the associated timing diagram.
SERIAL CLOCK (SCLK)
The serial clock is used to load and read data in the programmable offset
registers. Data from the serial input signal (FWFT/SI) can be loaded into the offset
registers on the rising edge of SCLK provided that the serial write enable
(SWEN) signal is LOW. Data can be read from the offset registers via the serial
data output (SDO) signal on the rising edge of SCLK provided that SREN is LOW.
The serial clock can operate at a maximum frequency of 10MHz.
SERIAL WRITE ENABLE (SWEN)
The serial write enable input is an enable used for serial programming of the
programmable offset registers. It is used in conjunction with the serial input
(FWFT/SI) and serial clock (SCLK) when programming the offset registers.
When the serial write enable is LOW, data at the serial input is loaded into the
offset register, one bit for each LOW-to-HIGH transition of SCLK. When serial
write enable is HIGH, the offset registers retain the previous settings and no
offsets are loaded. Serial write enable functions the same way in both Standard
IDT and FWFT modes. See Figure 29, Loading of Programmable Flag
Registers, for the timing diagram.
SERIAL READ ENABLE (SREN)
The serial read enable input is an enable used for reading the value of the
programmable offset registers. It is used in conjunction with the serial data output
(SDO) and serial clock (SCLK) when reading the offset registers. When the
serial read enable is LOW, data at the serial data output can be read from the
offset register, one bit for each LOW-to-HIGH transition of SCLK. When serial
read enable is HIGH, the reading of the offset registers will stop. Whenever serial
read enable (SREN) is activated (LOW) values in the offset registers are copied
directly into a serial scan out register. SREN must be kept LOW in order to read
the entire contents of the scan out register. If at any point SREN is toggled HIGH,
another copy function from the offset register to the serial scan out register will
occur the next time SREN is enabled (LOW). Serial read enable functions the
same way in both IDT Standard and FWFT modes. See Figure 30, Reading
of Programmable Flag Registers, for the timing diagram.
26
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync™ DDR/SDR FIFO
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
FEBRUARY 11, 2009
OUTPUTS:
DATA OUTPUT BUS (Q[39:0])
The data output busses are 10 bits wide in Quad mode and 20 or 10-bits wide
in Dual mode. In Quad mode, Q[9:0] are data outputs for FIFO0, Q[19:10] are
for FIFO1, Q[29:20] are for FIFO2, and Q[39:30] are for FIFO3. In Dual mode,
Q[19:0] are data outputs for FIFO0 and Q[39:20] are for FIFO2 for the 20-bit
wide data bus. Q[9:0] are data outputs for FIFO0 and Q[29:20] are data outputs
for FIFO2 for the 10-bit wide data bus.
EMPTY/OUTPUT READY FLAG (EF/0/1/2/3)
There are four empty/output ready flags (two in Dual mode) available in this
device, each corresponding to the individual FIFOs in memory. This is a dual-
purpose pin whose function is determined based on the state of the FWFT/SI
pin during master reset. In the IDT Standard mode, the empty flags are selected.
When an individual FIFO is empty, its empty flag will go LOW, inhibiting further
read operations from that FIFO. When the empty flag is HIGH, the individual
FIFO is not empty and valid read operations can be performed. See Figure 18,
Read Cycle, Output Enable and Empty Flag Timing, for the relevant timing
information. Also see Table 3, Status Flags for IDT Standard Mode for the truth
table of the empty flags.
In FWFT mode, the output ready flags are selected. Output ready flags (OR)
go LOW at the same time that the first word written to an empty FIFO appears
on the outputs, which is a minimum of two read clock cycles provided the RCLK
and WCLK meets the tSKEW parameter (See Table 6 - TSKEW Measurement).
OR stays LOW after the RCLK LOW-to- HIGH transitions that shifts the last word
from the FIFO memory to the outputs. OR goes HIGH when another read
operation is performed, indicating the last word was read. The previous data
stays at the outputs, further data reads are inhibited until OR goes LOW again
and a new word appears on the bus. See Figure 22, Read Timing and Output
Ready Flag , for the relevant timing information. Also see Table 4, Status Flags
for FWFT Mode for the truth table of the empty flags. To prevent reading in the
FWFT mode, the output ready flag of each FIFO will go HIGH with respect to
RCLK, when the total number of words has been read out of the FIFO, thus
inhibiting further read operations. Upon the completion of a valid write cycle, the
output ready flag will go LOW with respect to RCLK three cycles later, thus
indicating another read has occurred.
The empty/output ready flags are synchronous and updated on the rising
edge of RCLK. In IDT Standard mode, the flags are double register-buffered
outputs. In FWFT mode, the flags are triple register-buffered outputs. Each
empty flag operates independently of the others and always indicates the
respective FIFO’s status.
FULL/INPUT READY FLAG (FF/IR/0/1/2/3)
There are four full/input ready flags (two in Dual mode) available in this
device, each corresponding to the individual FIFOs in memory. This is a dual-
purpose pin whose function is determined based on the state of the FWFT/SI
pin during master reset. In the IDT Standard mode, the full flags are selected.
When an individual FIFO is full, its full flags will go LOW after the rising edge of
WCLK that wrote the last word, thus inhibiting further write operations to the FIFO.
When the full flag is HIGH, the individual FIFO is not full and valid write operations
can be performed. See Figure 11, Write Cycle and Full Flag Timing for the
associated timing diagram. Also see Table 4, Status Flags for FWFT Mode for
the truth table of the full flags.
In FWFT mode, the input ready flags are selected. Input ready flags go LOW
when there is adequate memory space in the FIFOs for writing in data. The input
ready flags go HIGH after the rising edge of WCLK that wrote the last word, when
there are no free spaces available for writing in data. See Figure 16, Write Cycle
and Output Ready Timing , for the associated timing information. Also see Table
4, Status Flags for FWFT Mode for the truth table of the full flags. The input ready
status not only measures the contents of the FIFOs memory, but also counts the
presence of a word in the output register. Thus, in FWFT mode, the total number
of writes necessary to make IR LOW is one greater than needed to assert FF
in IDT Standard mode.
FF/IR is synchronous and updated on the rising edge of WCLK. FF/IR are
double register-buffered outputs. Each flag operates independently of the
others. To prevent data overflow in the IDT Standard mode, the full flag of each
FIFO will go LOW with respect to WCLK, when the maximum number of words
has been written into the FIFO, thus inhibiting further write operations. Upon the
completion of a valid read cycle, the full flag will go HIGH with respect to WCLK
two cycles later, thus allowing another write to occur.
To prevent data overflow in the FWFT mode, the input ready flag of each FIFO
will go HIGH with respect to WCLK, when the maximum number of words has
been written into the FIFO, thus inhibiting further write operations. Upon the
completion of a valid read cycle, the input ready flag will go LOW with respect
to WCLK two cycles later, thus allowing another write to occur.
PROGRAMMABLE ALMOST EMPTY FLAG (PAE0/1/2/3)
There are four programmable almost empty flags (two in Dual mode)
available in this device, each corresponding to an individual FIFO in memory.
The programmable almost empty flag is an additional status flag that notifies the
user when the FIFO memory is near empty. The user may utilize this feature
as an early indicator as to when the FIFO will become empty. In IDT Standard
mode, PAE will go LOW when there are n words or less in the FIFO. In FWFT
mode, the PAE will go LOW when there are n-1 words or less in the FIFO. The
offset “n” is the empty offset value. The default setting for this value is stated in
Table 2. There are four internal FIFOs hence four PAE offset values, (n0, n1,
n2, and n3).
There are two timing modes available for the PAE flags, selectable by the state
of the Programmable Flag Mode (PFM) pin. If PFM is tied HIGH, then
synchronous timing mode is selected. If PFM is tied LOW, then asynchronous
timing mode is selected. In synchronous configuration, the PAE flag is updated
on the rising edge of RCLK. In asynchronous PAE configuration, the PAE flag
is asserted LOW on the LOW-to-HIGH transitions of the Read Clock (RCLK).
PAE is reset to HIGH on the LOW-to-HIGH transitions of the Write Clock (WCLK).
See Figures 31 and 33, Synchronous and Asynchronous Programmable
Almost-Empty Flag Timing, for the relevant timing information.
Each programmable almost empty flag operates independently of the others.
PROGRAMMABLE ALMOST FULL FLAG (PAF0/1/2/3)
There are four programmable almost full flags (two in Dual mode) available
in this device, each corresponding to the individual FIFOs in memory. The
programmable almost full flag is an additional status flag that notifies the user when
the FIFO memory is nearly full. The user may utilize this feature as an early
indicator as to when the FIFO will not be able to accept any more data and thus
prevent data from being dropped. In IDT Standard mode, if no reads are
performed after master reset, PAF will go LOW after (D-m) (D meaning the
density of the particular device) words are written to the FIFO. In FWFT mode,
PAF will go LOW after (D+1-m) words are written to the FIFO. The offset “m”
is the full offset value. The default setting for this value is stated in Table 2. There
are four internal FIFOs hence four PAF offset values, (m0, m1, m2, and m3).
There are two timing modes available for the PAF flags, selectable by the state
of the Programmable Flag Mode (PFM) pin. If PFM is tied HIGH, then
synchronous timing mode is selected. If PFM is tied LOW, then asynchronous
timing mode is selected. In synchronous configuration, the PAF flag is updated
on the rising edge of WCLK. In asynchronous PAF configuration, the PAF flag
27
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync™ DDR/SDR FIFO
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
FEBRUARY 11, 2009
6158 drw11
ERCLK
tAtD
Q
SLOWEST
(3)
RCLK
tERCLK
is asserted LOW on the LOW-to-HIGH transitions of the Write Clock (WCLK).
PAF is reset to HIGH on the LOW-to-HIGH transitions of the Read Clock (RCLK).
See Figure 31 and 33, Synchronous and Asynchronous Programmable
Almost-Full Flag Timing (IDT Standard and FWFT mode), for the relevant timing
information.
Each programmable almost full flag operates independently of the others.
ECHO READ CLOCK (ERCLK0/1/2/3)
There are four echo read clock outputs (two in Dual mode) available in this
device, each corresponding to their respective input read clocks in the FIFO.
The echo read clock is a free-running clock output, that will always follow the
RCLK input regardless of the read enables and read chip selects. The ERCLK
output follows the RCLK input with an associated delay. This delay provides the
user with a more effective read clock source when reading data from the output
bus. This is especially helpful at high speeds when variables within the device
may cause changes in the data access times. These variations in access time
may be caused by ambient temperature, supply voltage, or device characteristics.
Any variations effecting the data access time will also have a corresponding
effect on the echo read clock output produced by the FIFO, therefore the echo
read clock output level transitions should always be at the same position in time
relative to the data outputs. Note, that echo read clock is guaranteed by design
to be slower than the slowest data outputs. Refer to Figure 6, Echo Read Clock
and Data Output Relationship, Figures 25, 26, and 27 Echo Read Clock and
Read Enable Operation for timing information. Each echo read clock output
operate independently of the others and transitions with respect to the data
outputs of its FIFO.
Figure 6. Echo Read Clock and Data Output Relationship
NOTES:
1. REN is LOW.
2. tERCLK > tA, guaranteed by design.
3. Qslowest is the data output with the slowest access time, tA.
4. Time, tD is greater than zero, guaranteed by design.
TABLE 6 — TSKEW MEASUREMENT
Data Port Status Flags TSKEW Measurement Datasheet
Configuration Parameter
DDR Input EF/OR Negative Edge WCLK to tSKEW2
t o Positive Edge RCLK
DDR Output FF/IR Negative Edge RCLK to tSKEW2
Positive Edge WCLK
PAE Negative Edge WCLK to tSKEW3
Positive Edge RCLK
PAF Negative Edge RCLK to tSKEW3
Positive Edge WCLK
DDR Input EF/OR Negative Edge WCLK to tSKEW2
t o Positive Edge RCLK
SDR Output FF/IR Positive Edge RCLK to tSKEW1
Positive Edge WCLK
PAE Negative Edge WCLK to tSKEW3
Positive Edge RCLK
PAF Positive Edge RCLK to tSKEW3
Positive Edge WCLK
SDR Input EF/OR Positive Edge WCLK to tSKEW1
t o Positive Edge RCLK
DDR Output FF/IR Negative Edge RCLK to tSKEW2
Positive Edge WCLK
PAE Positive Edge WCLK to tSKEW3
Positive Edge RCLK
PAF Negative Edge RCLK to tSKEW3
Positive Edge WCLK
SDR Input EF/OR Positive Edge WCLK to tSKEW1
t o Positive Edge RCLK
SDR Output FF/IR Positive Edge RCLK to tSKEW1
Positive Edge WCLK
PAE Positive Edge WCLK to tSKEW3
Positive Edge RCLK
PAF Positive Edge RCLK to tSKEW3
Positive Edge WCLK
28
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync™ DDR/SDR FIFO
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
FEBRUARY 11, 2009
TDO
TDO
TDI/
TMS
TCK
TRST
t
DOH
Notes to diagram:
t1 =
t
TCKLOW
t2 =
t
TCKHIGH
t3 =
tRST
(reset pulse width)
t4 = tRSR (reset recovery)
6158 drw12
t3
t4
t1t2
t
TCK
t
DH
t
DS
t
DO
Figure 7. Standard JTAG Timing
Parameter Symbol Test
Conditions Min. Max. Units
JTAG Clock Input Period tTCK - 100 - ns
JTAG Clock HIGH tTCKHIGH -40-ns
JTAG Clock Low tTCKLOW -40-ns
JTAG Reset tRST -50-ns
JTAG Reset Recovery tRSR -50-ns
JTAG
AC ELECTRICAL CHARACTERISTICS
(vcc = 2.5V ± 5%; Tcase = 0°C to +85°C)
NOTE:
1. 50pf loading on external output signals.
SYSTEM INTERFACE PARAMETERS
IDT72T54242
IDT72T54252
IDT72T54262
Parameter Symbol Test Conditions Min. Max. Units
Data Output tDO(1) -20ns
Data Output Hold tDOH(1) 0-ns
Data Input tDS trise=3ns 10 - ns
tDH tfall=3ns 10 -
29
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync™ DDR/SDR FIFO
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
FEBRUARY 11, 2009
JTAG TIMING SPECIFICATIONS
(IEEE 1149.1 COMPLIANT)
The JTAG test port in this device is fully compliant with the IEEE Standard
Test Access Port (IEEE 1149.1) specifications. Five additional pins (TDI, TDO,
TMS, TCK and TRST) are provided to support the JTAG boundary scan
interface. Note that IDT provides appropriate Boundary Scan Description
Language program files for these devices.
The Standard JTAG interface consists of five basic elements:
•Test Access Port (TAP)
•TAP controller
•Instruction Register (IR)
•Data Register Port (DR)
•Bypass Register (BYR)
The following sections provide a brief description of each element. For a
complete description refer to the IEEE Standard Test Access Port Specification
(IEEE Std. 1149.1-1990).
The Figure below shows the standard Boundary-Scan Architecture
Figure 8. JTAG Architecture
TEST ACCESS PORT (TAP)
The TAP interface is a general-purpose port that provides access to the
internal JTAG state machine. It consists of four input ports (TCLK, TMS, TDI,
TRST) and one output port (TDO).
THE TAP CONTROLLER
The TAP controller is a synchronous finite state machine that responds to
TMS and TCLK signals to generate clock and control signals to the Instruction
and Data Registers for capture and updating of data passed through the TDI
serial input.
In Pad
In Pad
Incell
Incell
Core
Logic
Outcell
Outcell
Out Pad
Out Pad
All outputs
All inputs
Eg: Dins, Clks
(BSDL file
describes the
chain order)
ID
Bypass
Instruction
Register
TA P
TMS
TDI
TCK
TRST
Instruction
Select
Enable
TDO
6158 drw13
30
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync™ DDR/SDR FIFO
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
FEBRUARY 11, 2009
Refer to the IEEE Standard Test Access Port Specification (IEEE Std.
1149.1) for the full state diagram
All state transitions within the TAP controller occur at the rising edge of the
TCLK pulse. The TMS signal level (0 or 1) determines the state progression
that occurs on each TCLK rising edge. The TAP controller takes precedence
over the FIFO memory and must be reset after power up of the device. See
TRST description for more details on TAP controller reset.
Test-Logic-Reset All test logic is disabled in this controller state enabling the
normal operation of the IC. The TAP controller state machine is designed in such
a way that, no matter what the initial state of the controller is, the Test-Logic-Reset
state can be entered by holding TMS at high and pulsing TCK five times. This
is the reason why the Test Reset (TRST) pin is optional.
Run-Test-Idle In this controller state, the test logic in the IC is active only if
certain instructions are present. For example, if an instruction activates the self
test, then it will be executed when the controller enters this state. The test logic
in the IC is idles otherwise.
Select-DR-Scan This is a controller state where the decision to enter the
Data Path or the Select-IR-Scan state is made.
Select-IR-Scan This is a controller state where the decision to enter the
Instruction Path is made. The Controller can return to the Test-Logic-Reset state
other wise.
Figure 9. TAP Controller State Diagram
Test-Logic
Reset
Run-Test/
Idle
1
0
0
Select-
DR-Scan
Select-
IR-Scan
111
Capture-IR
0
Capture-DR
0
0
EXit1-DR
1
Pause-DR
0
Exit2-DR
1
Update-DR
1
Exit1-IR
1
Exit2-IR
1
Update-IR
1
10
1
1
1
6158 drw14
0
Shift-DR
0
0
0
Shift-IR
0
0
Pause-IR
0
1
Input is
TMS
0
0
1
NOTES:
1. Five consecutive TCK cycles with TMS = 1 will reset the TAP.
2. TAP controller does not automatically reset upon power-up. The user must provide a reset to the TAP controller (either by TRST or TMS).
3. TAP controller must be reset before normal FIFO operations can begin.
Capture-IR In this controller state, the shift register bank in the Instruction
Register parallel loads a pattern of fixed values on the rising edge of TCK. The
last two significant bits are always required to be “01”.
Shift-IR In this controller state, the instruction register gets connected
between TDI and TDO, and the captured pattern gets shifted on each rising edge
of TCK. The instruction available on the TDI pin is also shifted in to the instruction
register.
Exit1-IR This is a controller state where a decision to enter either the Pause-
IR state or Update-IR state is made.
Pause-IR This state is provided in order to allow the shifting of instruction
register to be temporarily halted.
Exit2-DR This is a controller state where a decision to enter either the Shift-
IR state or Update-IR state is made.
Update-IR In this controller state, the instruction in the instruction register is
latched in to the latch bank of the Instruction Register on every falling edge of
TCK. This instruction also becomes the current instruction once it is latched.
Capture-DR In this controller state, the data is parallel loaded in to the data
registers selected by the current instruction on the rising edge of TCK.
Shift-DR, Exit1-DR, Pause-DR, Exit2-DR and Update-DR These
controller states are similar to the Shift-IR, Exit1-IR, Pause-IR, Exit2-IR and
Update-IR states in the Instruction path.
31
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync™ DDR/SDR FIFO
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
FEBRUARY 11, 2009
THE INSTRUCTION REGISTER
The Instruction register allows an instruction to be shifted in serially into the
processor at the rising edge of TCLK.
The Instruction is used to select the test to be performed, or the test data
register to be accessed, or both. The instruction shifted into the register is latched
at the completion of the shifting process when the TAP controller is at Update-
IR state.
The instruction register must contain 4 bit instruction register-based cells
which can hold instruction data. These mandatory cells are located nearest the
serial outputs they are the least significant bits.
TEST DATA REGISTER
The Test Data register contains three test data registers: the Test Bypass
register, the Boundary Scan register and Device ID register.
These registers are connected in parallel between a common serial input
and a common serial data output.
The following sections provide a brief description of each element. For a
complete description, refer to the IEEE Standard Test Access Port Specification
(IEEE Std. 1149.1-1990).
Test Bypass Register
The register is used to allow test data to flow through the device from TDI
to TDO. It contains a single stage shift register for a minimum length in serial path.
When the bypass register is selected by an instruction, the shift register stage
is set to a logic zero on the rising edge of TCLK when the TAP controller is in
the Capture-DR state.
The operation of the bypass register should not have any effect on the
operation of the device in response to the BYPASS instruction.
The Boundary-Scan Register
The Boundary Scan Register allows serial data TDI be loaded in to or read
out of the processor input/output ports. The Boundary Scan Register is a part
of the IEEE 1149.1-1990 Standard JTAG Implementation.
The Device Identification Register
The Device Identification Register is a Read Only 32-bit register used to
specify the manufacturer, part number and version of the processor to be
determined through the TAP in response to the IDCODE instruction.
IDT JEDEC ID number is 0xB3. This translates to 0x33 when the parity is
dropped in the 11-bit Manufacturer ID field.
For the IDT72T54242/72T54252/72T54262, the Part Number field con-
tains the following values:
IDT72T54242/252/262 JTAG Device Identification Register
31(MSB) 28 27 12 11 1 0(LSB)
V ersion (4 bits) Part Number (16-bit) Manufacturer ID (1 1-bit)
0X0 00B3 (hex) 1
JTAG INSTRUCTION REGISTER
The Instruction register allows instruction to be serially input into the device
when the TAP controller is in the Shift-IR state. The instruction is decoded to
perform the following:
•Select test data registers that may operate while the instruction is
current. The other test data registers should not interfere with chip
operation and the selected data register.
•Define the serial test data register path that is used to shift data between
TDI and TDO during data register scanning.
The Instruction Register is a 4 bit field (i.e. IR3, IR2, IR1, IR0) to decode
16 different possible instructions. Instructions are decoded as follows.
Hex Instruction Function
Value
0000 EXTEST Test external pins
0001 SAMPLE/PRELOAD Select boundary scan register
0002 IDCODE Selects chip identification register
0003 CLAMP Fix the output chains to scan chain values
0004 HI-IMPEDANCE Puts all outputs in high-impedance state
0007 OFFSET READ Read PAE/PAF offset register values
0008 OFFSET WRITE Write PAE/PAF offset register values
000F BYPASS Select bypass register
Private Several combinations are private (for IDT
internal use). Do not use codes other than
those identified above.
JTAG Instruction Register Decoding
The following sections provide a brief description of each instruction. For
a complete description refer to the IEEE Standard Test Access Port Specification
(IEEE Std. 1149.1-1990).
EXTEST
The required EXTEST instruction places the IC into an external boundary-
test mode and selects the boundary-scan register to be connected between TDI
and TDO. During this instruction, the boundary-scan register is accessed to
drive test data off-chip via the boundary outputs and receive test data off-chip
via the boundary inputs. As such, the EXTEST instruction is the workhorse of
IEEE. Std 1149.1, providing for probe-less testing of solder-joint opens/shorts
and of logic cluster function.
SAMPLE/PRELOAD
The required SAMPLE/PRELOAD instruction allows the IC to remain in a
normal functional mode and selects the boundary-scan register to be connected
between TDI and TDO. During this instruction, the boundary-scan register can
be accessed via a date scan operation, to take a sample of the functional data
entering and leaving the IC. This instruction is also used to preload test data into
the boundary-scan register before loading an EXTEST instruction.
IDCODE
The optional IDCODE instruction allows the IC to remain in its functional mode
and selects the optional device identification register to be connected between
TDI and TDO. The device identification register is a 32-bit shift register containing
information regarding the IC manufacturer, device type, and version code.
Accessing the device identification register does not interfere with the operation
of the IC. Also, access to the device identification register should be immediately
available, via a TAP data-scan operation, after power-up of the IC or after the
TAP has been reset using the optional TRST pin or by otherwise moving to the
Test-Logic-Reset state.
Device Part# Field
IDT72T54242 4C5 (hex)
IDT72T54252 4C6 (hex)
IDT72T54262 4C7 (hex)
32
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync™ DDR/SDR FIFO
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
FEBRUARY 11, 2009
CLAMP
The optional CLAMP instruction sets the outputs of an IC to logic levels
determined by the contents of the boundary-scan register and selects the one-
bit bypass register to be connected between TDI and TDO. Before loading this
instruction, the contents of the boundary-scan register can be preset with the
SAMPLE/PRELOAD instruction. During this instruction, data can be shifted
through the bypass register from TDI to TDO without affecting the condition of
the outputs.
HIGH-IMPEDANCE
The optional High-Impedance instruction sets all outputs (including two-state
as well as three-state types) of an IC to a disabled (high-impedance) state and
selects the one-bit bypass register to be connected between TDI and TDO.
During this instruction, data can be shifted through the bypass register from TDI
to TDO without affecting the condition of the IC outputs.
OFFSET READ
This instruction is an alternative to serial reading the offset registers for the
PAE/PAF flags. When reading the offset registers through this instruction, the
dedicated serial programming signals must be disabled.
OFFSET WRITE
This instruction is an alternative to serial programming the offset registers for
the PAE/PAF flags. When writing the offset registers through this instruction, the
dedicated serial programming signals must be disabled.
BYPASS
The required BYPASS instruction allows the IC to remain in a normal
functional mode and selects the one-bit bypass register to be connected
between TDI and TDO. The BYPASS instruction allows serial data to be
transferred through the IC from TDI to TDO without affecting the operation of
the IC.
33
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync™ DDR/SDR FIFO
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
FEBRUARY 11, 2009
EF/OR(6)
0/1/2/3
tRSF
If FWFT = HIGH, OR = HIGH
If FWFT = LOW, EF = LOW
tRSF
PAF(6)
0/1/2/3
tRSF
tRSF
Q[39:0](7)
tRSF
OE = HIGH
OE = LOW
6158 drw15
OW(3),
IW(3)
FSEL[1:0](3)
PFM(3)
HIGH = Synchronous PAE/PAF Timing
LOW = Asynchronous PAE/PAF Timing
MD(3)
tRSS
HIGH = FWFT Mode
LOW = IDT Standard Mode
RDDR(3),
WDDR(3)
FWFT/SI(3)
IOSEL(3)
HIGH = Read/Write Double Data Rate
LOW = Read/Write Single Data Rate
HIGH = HSTL I/Os
LOW = LVTTL I/Os
tRSS
tRSS
tRSS
tRSS
tRSS
tRSS
FF/IR(6)
0/1/2/3
PAE(6)
0/1/2/3
HIGH = Quad mode
LOW = Dual mode
If FWFT = LOW, FF = HIGH
If FWFT = HIGH, IR = LOW
tRS
MRS
W
EN0/1/2/3(6)
REN0/1/2/3(6)
tRSS
SWEN,
SREN
tRSS
tRSR
tRSR
Figure 10 . Master Reset Timing
NOTES:
1. OE can be toggled during master reset. During master reset, the high-impedance control of the Qn data outputs are provided by OE only.
2. RCLK(s), WCLK(s) and SCLK(s) can be free running or idle.
3. The state of these pins are latched when the master reset pulse is LOW.
4. JTAG flag should not toggle during master reset.
5. RCS and WCS can be HIGH or LOW until the first rising edge of RCLK after master reset is complete.
6. If Dual mode is selected, only the signals designated with a "0" or "2" are used.
7. If Dual mode is selected, outputs Q[19:10] and Q[39:30] are not used if outputs are configured to x10.
34
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync™ DDR/SDR FIFO
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
FEBRUARY 11, 2009
EF/OR
PAF
tRSF
tRSF
Q[39:0]
(3)
tRSF
OE = HIGH
OE = LOW
6158 drw16
FF/IR
PAE
tRS
PRS
WEN
REN
tRSS
SWEN,
SREN
tRSS
tRSR
tRSR
tRSF If FWFT = HIGH, OR = HIGH
If FWFT = LOW, EF = LOW
tRSF If FWFT = LOW, EF = HIGH
If FWFT = HIGH, IR = LOW
Figure 11. Partial Reset Timing
NOTES:
1. This timing diagram shows the partial reset timing for a single FIFO. Each PRS is independent of the others.
2 . During partial reset the high-impedance control of the Qn data outputs are provided by OE only, RCS can be HIGH or LOW until the first rising edge of RCLK after master reset.
3. If Dual mode is selected, outputs Q[19:10] and Q[39:30] are not used if outputs are configured to x10.
35
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync™ DDR/SDR FIFO
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
FEBRUARY 11, 2009
Figure 12. Write Cycle and Full Flag Timing (Quad mode, IDT Standard mode, SDR to SDR)
NOTES:
1. The timing diagram shown is for FIFO0. FIFO1-3 exhibits the same behavior.
2. tSKEW1 is the minimum time between a rising RCLK0 edge and a rising WCLK0 edge to guarantee that FF0 will go HIGH (after one WCLK0 cycle plus tWFF). If the time between
the rising edge of the RCLK0 and the rising edge of the WCLK0 is less than tSKEW1, then the FF0 deassertion may be delayed one extra WCLK0 cycle. (See Table 6 - TSKEW
measurement).
3. OE0 = LOW, and WCS0 = LOW.
4. WCLK0 must be free running for FF0 to update.
5. MD IW OW WDDR RDDR FWFT/SI
1 D/C D/C 0 0 0
D[9:0]
WEN0
RCLK0
REN0
t
ENH
t
ENH
Q[9:0]
DATA READ NEXT DATA READ
t
SKEW1
(2)
6158 drw17
WCLK0
NO WRITE
1212
NO WRITE
t
WFF
t
A
t
ENS
t
ENS
(2)
t
DS
t
A
W
X
t
DH
t
CLK
t
CLKH
FF0
RCS0
t
ENS
t
RCSLZ
t
WFF
t
SKEW1
t
CLKL
W
X+1
t
WFF
t
WFF
t
DS
t
DH
36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync™ DDR/SDR FIFO
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
FEBRUARY 11, 2009
Figure 13. Write Cycle and Full Flag Timing (Quad mode, IDT Standard mode, DDR to DDR)
NOTES:
1. The timing diagram shown is for FIFO0. FIFO1-3 exhibits the same behavior.
2. tSKEW2 is the minimum time between a falling RCLK0 edge and a rising WCLK0 edge to guarantee that FF0 will go HIGH (after one WCLK0 cycle plus tWFF). If the time between the falling edge of the RCLK0 and the rising edge
of WCLK0 is less than tSKEW2, then FF0 deassertion may be delayed one extra WCLK0 cycle. (See Table 6 - TSKEW measurement).
3. OE0 = LOW, WCS0 = LOW, and RCS0 = LOW.
4. WCLK0 must be free running for FF0 to update.
5. MD IW OW WDDR RDDR FWFT/SI
1 D/C D/C 1 1 0
Word 0
Q[9:0]
6158 drw18
t
A
12
NO
WRITE
D[9:0]
RCLK0
WCLK0
WEN0
FF0
t
CLKL
t
CLKH
t
CLK
t
SKEW2
(2)
12
t
SKEW2
(2)
REN0
NO WRITE
Wx
t
DS
t
DS
t
DH
Wx+1
t
DH
Wx+2 Wx+3
t
WFF
t
WFF
t
WFF
t
WFF
t
ENH
t
ENS
t
ENH
t
ENS
t
A
Data in Output Register Word 1 Word 2
t
A
t
A
Word 3
37
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync™ DDR/SDR FIFO
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
FEBRUARY 11, 2009
Figure 14. Write Cycle and Full Flag Timing (Dual mode, IDT Standard mode, DDR to SDR, x10 In to x20 Out)
WCLK0
FF0
WEN0
RCS0
t
ENS
t
SKEW1(2)
Q[19:0]
RCLK0
t
ENH
t
ENS
12
t
WFF
D[9:0]
REN0
t
RCSLZ
t
A
t
DS
t
DS
t
DH
t
DH
t
WFF
t
SKEW1(2)
t
ENS
t
ENH
t
A
12
t
WFF
t
DS
t
DS
t
DH
t
DH
t
CLK
t
CLKH
t
CLKL
NO WRITE
NO WRITE
t
WFF
Word 0 Word 1
Wx Wx+1 Wx+2 Wx+3
6158 drw19
NOTES:
1. The timing diagram shown is for FIFO0. FIFO 2 exhibit the same behavior.
2. tSKEW1 is the minimum time between a rising RCLK0 edge and a rising WCLK0 edge to guarantee that FF0 will go HIGH (after one WCLK0 cycle plus tWFF). If the time between the rising edge of the RCLK0 and the rising edge
of the WCLK0 is less than tSKEW1, then the FF0 deassertion may be delayed one extra WCLK cycle. (See Table 6 - TSKEW measurement).
4. OE0 = LOW, and WCS0 = LOW.
5. WCLK0 must be free running for FF0 to update.
3. MD IW OW WDDR RDDR FWFT/SI
001100
38
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync™ DDR/SDR FIFO
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
FEBRUARY 11, 2009
Figure 15. Write Cycle and Full Flag (Dual mode, IDT Standard mode, SDR to DDR, x20 In to x10 Out)
WCLK0
FF0
WEN0
RCS0
t
ENS
Q[9:0]
RCLK0
t
ENH
t
ENS
12
t
WFF
D[19:0]
REN0
t
RCSLZ
t
A
t
DS
t
DH
t
ENS
t
ENH
t
A
12
t
DS
t
DS
t
DH
t
DH
t
CLK
NO WRITE
NO WRITE
t
WFF
Word 1 Word 3
Wx Wx+2 Wx+3
t
A
t
DS
t
DH
Wx+1
t
CLKH
t
CLKH
t
WFF
t
A
t
SKEW2(2)
t
WFF
t
ENS
t
RCSHZ
Word 0 Word 2
6158 drw20
t
SKEW2(2)
NOTES:
1. The timing diagram shown is for FIFO0. FIFO 2 exhibit the same behavior.
2. tSKEW2 is the minimum time between a falling RCLK0 edge and a rising WCLK0 edge to guarantee that FF0 will go HIGH (after one WCLK0 cycle plus tWFF). If the time between the falling edge of the RCLK0 and the rising edge
of WCLK0 is less than tSKEW2, then FF0 deassertion may be delayed one extra WCLK0 cycle. (See Table 6 - TSKEW measurement).
3. OE0 = LOW, WCS0 = LOW, and RCS0 = LOW.
4. WCLK0 must be free running for FF0 to update.
5. MD IW OW WDDR RDDR FWFT/SI
010010
39
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync™ DDR/SDR FIFO
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
FEBRUARY 11, 2009
Figure 16. Write Cycle and Output Ready Timing (Quad mode, FWFT mode, SDR to SDR)
NOTES:
1. The timing diagram shown is for FIFO0. FIFO1-3 exhibits the same behavior.
2. tSKEW1 is the minimum time between a rising WCLK0 edge and a rising RCLK0 edge to guarantee that OR0 will go LOW after two RCLK0 cycles plus tREF. If the time between the rising edge of WCLK0 and the rising edge of
RCLK0 is less than tSKEW1, then OR0 assertion may be delayed one extra RCLK0 cycle. (See Table 6 - TSKEW measurement).
3. tSKEW3 is the minimum time between a rising WCLK0 edge and a rising RCLK0 edge to guarantee that PAE0 will go HIGH after one RCLK0 cycle plus tPAES. If the time between the rising edge of WCLK0 and the rising edge of
RCLK0 is less than tSKEW3, then the PAE0 deassertion may be delayed one extra RCLK0 cycle. (See Table 6 - TSKEW measurement).
4. n0 = PAE0 offset, m0 = PAF0 offset and D = maximum FIFO depth.
5. OE0 = LOW, and WCS0 = LOW.
6. First data word latency = tSKEW1 + 2*TRCLK + tREF.
7 . WCLK0 must be free running for OR0 to update.
8. MD IW OW WDDR RDDR PFM FWFT/SI
1 D/C D/C 0 0 1 1
W[D-m0-1]
W[D-m0-2] W[D-1] WD
W[D-m0] W[D-m0+1]
tDS
tPAFS
tWFF
W[D-m0+2]
W1
tENH
6158 drw21
1
W1W2W4W[n0 +2] W[n0+3] W[n0+4]
WCLK0
WEN0
D[9:0]
RCLK0
tDHtDS
tSKEW1
(2)
REN0
Q
[9:0]
PAF0
PAE0
IR0
tDS
tSKEW3
(3)
tA
tREF
OR0
tPAES
PREVIOUS DATA IN OUTPUT REGISTER
W3
12312
tENS
RCS0
tRCSLZ
tENS
tENS
40
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync™ DDR/SDR FIFO
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
FEBRUARY 11, 2009
Figure 17. Write Cycle and Output Ready Timing (Quad mode, FWFT mode, DDR to DDR)
NOTES:
1. The timing diagram shown is for FIFO0. FIFO1-3 exhibits the same behavior.
2. tSKEW2 is the minimum time between a falling WCLK0 edge and a rising RCLK0 edge to guarantee that OR0 will go LOW after two RCLK0 cycle plus tREF. If the time between the falling edge of WCLK0 and the rising edge of RCLK0
is less than tSKEW2, then OR0 assertion may be delayed one extra RCLK0 cycle. (See Table 6 - TSKEW measurement).
3. OE0 = LOW, RCS0 = LOW, and WCS0 = LOW.
4. First data word latency = tSKEW2 + 2*TRCLK + tREF.
5 . WCLK0 must be free running for OR0 to update.
6. MD IW OW WDDR RDDR FWFT/SI
1 D/C D/C 1 1 1
WCLK0
WEN0
OR0
t
SKEW2(2)
Q[9:0]
RCLK0
D[9:0]
REN0
Previous Data In Output Register
6158 drw22
t
DS
t
DH
W1 W2
t
ENH
12 3
t
DS
t
DH
t
DS
t
DH
W3 W4
t
ENH
t
DS
t
DH
t
ENS
t
ENS
t
REF
t
REF
t
ENH
t
ENS
t
A
t
A
W1 W2
t
A
t
A
W3 W4
41
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync™ DDR/SDR FIFO
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
FEBRUARY 11, 2009
Figure 18. Read Cycle, Output Enable and Empty Flag Timing (Quad mode, IDT Standard mode, SDR to SDR)
NOTES:
1. The timing diagram shown is for FIFO0. FIFO1-3 exhibits the same behavior.
2. tSKEW1 is the minimum time between a rising WCLK0 edge and a rising RCLK0 edge to guarantee that EF0 will go HIGH (after one RCLK0 cycle plus tREF). If the time between
the rising edge of WCLK0 and the rising edge of RCLK0 is less than tSKEW1, then EF0 deassertion may be delayed one extra RCLK0 cycle. (See Table 6 - TSKEW measurement)..
3. First data word latency = tSKEW1 + 1*TRCLK + tREF.
4. RCS0 = LOW.
5. RCLK0 must be free running for EF0 to update.
6. MD IW OW WDDR RDDR FWFT/SI
1 D/C D/C 0 0 0
6158 drw23
D[9:0]
tDS tDH
WXWX+1
tDS tDH
NO OPERATION
RCLK0
REN0
EF0
tCLK
tCLKH tCLKL
tENH
tREF
tA
tOLZ
Q[9:0]
OE0
WCLK0
(2)
tSKEW1
WEN0
tENS
tENS tENH
12
t
OE
NO OPERATION
tENS tENH
tOHZ
WX-1
tREF
tENH
tENS
tAtA
tREF
tENS tENH
WCS0
tOE
tENS tENH
WX-1 WXWX+1
42
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync™ DDR/SDR FIFO
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
FEBRUARY 11, 2009
Figure 19. Read Cycle, Output Enable and Empty Flag Timing (Quad mode, IDT Standard mode, DDR to DDR)
NOTES:
1. The timing diagram shown is for FIFO0. FIFO1-3 exhibits the same behavior.
2. tSKEW2 is the minimum time between a falling WCLK0 edge and a rising RCLK0 edge to guarantee that EF0 will go HIGH (after one RCLK0 cycle plus tREF). If the time between the falling edge of WCLK0 and the rising edge of
RCLK0 is less than tSKEW2, then EF0 deassertion may be delayed one extra RCLK0 cycle. (See Table 6 - TSKEW measurement)
3. REN0 = LOW, and RCS0 = LOW.
4. First data word latency = tSKEW2 + 1*TRCLK + tREF.
5. RCLK0 must be free running for EF0 to update.
6. MD IW OW WDDR RDDR FWFT/SI
1 D/C D/C 1 1 0
t
OLZ
t
REF
t
REF
W
n
W
n
W
n+1
t
OHZ
t
OLZ
Q[9:0]
EF0
OE0
WCLK0
WEN0
D[9:0]
5198 drw24
W
n+1
t
DH
t
DS
t
DS
t
DH
t
ENS
t
ENH
t
REF
RCLK0
12
t
SKEW2
(2)
t
CLK
t
CLKH
t
CLKL
t
OE
t
A
WCS0
t
WCSS
t
WCSH
W
n
-
1
NO Read NO Read
W
n+2
W
n+2
t
A
t
A
t
A
43
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync™ DDR/SDR FIFO
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
FEBRUARY 11, 2009
Figure 20. Read Cycle and Empty Flag Timing (Dual mode, IDT Standard mode, DDR to SDR, x20 In to x10 Out)
RCLK0
EF0
WEN0
REN0
WCS0
t
ENS
t
SKEW2
(2)
D[19:0]
t
DS
W0 - W1
Q[9:0]
WCLK0
t
ENH
t
ENH
t
ENS
W2 - W3
t
DH
t
DS
t
DH
12
t
REF
t
ENS
t
A
t
A
t
A
t
A
W0 W1 W2 W3
t
REF
Previous Data in Ouput Register
6158 drw25
t
CLKH
t
CLKL
t
CLK
NOTES:
1. The timing diagram shown is for FIFO0. FIFO 2 exhibits the same behavior.
2. tSKEW2 is the minimum time between a falling WCLK0 edge and a rising RCLK0 edge to guarantee that EF0 will go HIGH (after one RCLK0 cycle plus tREF). If the time between the falling edge of WCLK0 and the rising edge of
RCLK0 is less than tSKEW2, then EF0 deassertion may be delayed one extra RCLK0 cycle. (See Table 6 - TSKEW measurement).
3. REN0 = LOW, and RCS0 = LOW.
4. First data word latency = tSKEW1 + 1*TRCLK + tREF.
5. RCLK0 must be free running for EF0 to update.
6. MD IW OW WDDR RDDR FWFT/SI
010100
44
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync™ DDR/SDR FIFO
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
FEBRUARY 11, 2009
Figure 21. Read Cycle and Empty Flag Timing (Dual mode, IDT Standard mode, SDR to DDR, x10 In to x20 Out)
NOTES:
1. The timing diagram shown is for FIFO0. FIFO 2 exhibits the same behavior.
2. tSKEW1 is the minimum time between a rising WCLK0 edge and a rising RCLK0 edge to guarantee that EF0 will go HIGH (after one RCLK0 cycle plus tREF). If the time between the rising edge of WCLK0 and the rising edge of
RCLK0 is less than tSKEW1, then EF0 deassertion may be delayed one extra RCLK0 cycle. (See Table 6 - TSKEW measurement).
3. OE0 = LOW, RCS0 = LOW, and WCS0 = LOW.
4. First data word latency = tSKEW1 + 1*TRCLK + tREF.
5. RCLK0 must be free running for EF0 to update.
6. MD IW OW WDDR RDDR FWFT/SI
001010
Q[19:0]
t
SKEW1
(2)
WCLK0
RCLK0
REN0
12
WEN0
t
REF
EF0
D[9:0]
6158 drw26
t
REF
t
REF
Last Word Last 20-bit Word
t
ENS
t
ENH
W0W1W2W3
t
ENH
t
ENS
W0-W1
t
A
t
A
t
A
t
A
t
DS
t
DH
t
DS
t
DH
t
DS
t
DH
t
DH
t
DS
t
CLK
t
CLKH
t
CLKL
Previous Data
t
ENH
NO Read
W2-W3
45
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync™ DDR/SDR FIFO
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
FEBRUARY 11, 2009
Figure 22. Read Timing and Output Ready Flag (Quad mode, FWFT mode, SDR to SDR)
NOTES:
1. The timing diagram shown is for FIFO0. FIFO1-3 exhibit the same behavior.
2. tSKEW1 is the minimum time between a rising WCLK0 edge and a rising RCLK0 edge to guarantee that OR0 will go LOW after two RCLK0 cycles plus tREF. If the time between the rising edge of WCLK0 and the rising edge of
RCLK0 is less than tSKEW1, then OR0 assertion may be delayed one extra RCLK0 cycle.
3. tSKEW3 is the minimum time between a rising WCLK0 edge and a rising RCLK0 edge to guarantee that PAE0 will go HIGH after one RCLK0 cycle plus tPAES. If the time between the rising edge of WCLK0 and the rising edge of
RCLK0 is less than tSKEW3, then the PAE0 deassertion may be delayed one extra RCLK0 cycle.
4. OE0 = LOW, and WCS = LOW.
5. n0 = PAE0 offset, m0 = PAF0 offset and D = maximum FIFO depth.
6. First data word latency = tSKEW1 + 2*TRCLK + tREF.
7. MD IW OW WDDR RDDR FWFT/SI PFM
1 D/C D/C 0 0 1 1
6158 drw27
tPAES
W[D-n0]W[D-n0-1]
tA
tREF
W[D-1] WD
tA
W[D-n0+1] W[D-n0+2]
tENS
1
WCLK0 12
WEN0
D[9:0]
RCLK0
tENS
REN0
Q[9:0]
PAF0
PAE0
IR0
OR0
W1W1W2W3Wm0+2 W[m0+3]
tOHZ
tSKEW1
tENH
tDS tDH
tOE tAtAtA
tPAFS
tWFF
tWFF
tENS
OE0
tSKEW3
WD
W[m0+4]
(2) (3)
tCLKH tCLKL
tCLK
46
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync™ DDR/SDR FIFO
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
FEBRUARY 11, 2009
Figure 23. Read Timing and Output Ready Timing (Quad mode, FWFT mode, DDR to DDR)
NOTES:
1. The timing diagram shown is for FIFO0. FIFO1-3 exhibit the same behavior.
2. tSKEW2 is the minimum time between a falling WCLK0 edge and a rising RCLK0 edge to guarantee that OR0 will go LOW after two RCLK0 cycles plus tREF. If the time between the falling edge of WCLK0 and the rising edge of
RCLK0 is less than tSKEW2, then OR0 assertion may be delayed one extra RCLK0 cycle. (See Table 6 - TSKEW measurement).
3. OE0 = LOW.
4. RCLK0 must be free running for OR0 to update.
5. MD IW OW WDDR RDDR FWFT/SI
1 D/C D/C 1 1 1
t
REF
OR0
t
REF
Q[9:0]
6158 drw28
RCLK0 12 3
REN0
t
ENS
t
A
W7
t
A
W8 W9
t
A
W10
t
A
W11
t
A
W12
t
A
t
A
W13
t
A
W14
t
A
W15
t
A
W16 W17
t
ENS
W11 W12 W13
t
HS
W14 W15 W16 W17 W18
WCLK0
WEN0
t
SKEW2
W10
t
DS
D[9:0] W19 W20 W21
t
WFF
IR0
t
CLK
t
CLKH
t
CLKL
47
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync™ DDR/SDR FIFO
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
FEBRUARY 11, 2009
Figure 24. Read Cycle and Read Chip Select (Quad mode, IDT Standard mode, SDR to SDR)
NOTES:
1. The timing diagram shown is for FIFO0. FIFO1-3 exhibit the same behavior.
2. tSKEW1 is the minimum time between a rising WCLK0 edge and a rising RCLK0 edge to guarantee that EF0 will go HIGH (after one RCLK0 cycle plus tREF). If the time between
the rising edge of WCLK0 and the rising edge of RCLK0 is less than tSKEW1, then EF0 deassertion may be delayed one extra RCLK0 cycle.
3. First data word latency = tSKEW1 + 1*TRCLK + tREF.
4. OE0 = LOW.
5. RCLK0 must be free running for EF0 to update.
6. MD IW OW WDDR RDDR FWFT/SI
1 D/C D/C 0 0 0
RCLK0
REN0
12
6158 drw29
RCS0
Q[9:0]
WCLK0
WEN0
D[9:0]
t
ENS
LAST DATA
D
x
t
ENS
t
ENS
EF0
t
A
t
REF
t
REF
t
RCSLZ
LAST DATA-1
t
RCSHZ
t
RCSLZ
t
A
t
RCSHZ
t
SKEW1
(2)
t
ENH
t
ENS
t
DH
t
DS
t
ENH
t
ENH
t
CLK
t
CLKH
t
CLKL
48
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync™ DDR/SDR FIFO
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
FEBRUARY 11, 2009
Figure 25. Read Cycle and Read Chip Select Timing (Quad mode, FWFT mode, SDR to SDR)
NOTES:
1. The timing diagram shown is for FIFO0. FIFO1-3 exhibit the same behavior.
2. tSKEW1 is the minimum time between a rising RCLK0 edge and a rising WCLK0 edge to guarantee that IR0 will go LOW after one WCLK0 cycle plus tWFF. If the time between the rising edge of RCLK0 and the rising edge of
WCLK0 is less than tSKEW1, then the IR0 assertion may be delayed one extra WCLK0 cycle.
3. tSKEW3 is the minimum time between a rising RCLK0 edge and a rising WCLK0 edge to guarantee that PAF0 will go HIGH after one WCLK0 cycle plus tPAFS. If the time between the rising edge of RCLK0 and the rising edge of
WCLK0 is less than tSKEW3, then the PAF0 deassertion may be delayed one extra WCLK0 cycle.
4. n0 = PAE0 Offset, m0 = PAF0 offset and D = maximum FIFO depth.
5. OE = LOW.
6. RCLK0 must be free running for EF0 to update.
7. MD IW OW WDDR RDDR PFM FWFT/SI
1 D/C D/C 0 0 1 1
WCLK0
12
WEN0
D[9:0]
RCLK0
REN0
Q[9:0]
PAF0
PAE0
IR0
OR0
W
1
W
2
W
3
W
m+2
W
[m+3]
t
RCSHZ
t
SKEW1
t
ENH
t
DS
t
DH
t
A
t
A
t
PAFS
t
WFF
t
WFF
t
ENS
RCS0
t
SKEW3
6158 drw30
t
PAES
W
[D-n]
W
[D-n-1]
t
A
W
[D-1]
W
D
t
A
W
[D-n+1]
W
[m+4]
W
[D-n+2]
(2) (3)
t
ENS
1
t
ENS
t
RCSLZ
t
ENS
t
REF
t
ENH
W
D
49
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync™ DDR/SDR FIFO
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
FEBRUARY 11, 2009
Figure 26. Echo Read Clock and Read Enable Operation (Quad mode, IDT Standard mode, DDR to DDR)
NOTES:
1. The timing diagram shown is for FIFO0. FIFO1-3 exhibit the same behavior.
2. The EREN0 output is LOW if RCS0 and REN0 are LOW on the rising RCLK0 edge provided that the FIFO is not empty. If the FIFO is empty, EREN0 will go HIGH to indicate that there is no new word available.
3. The EREN0 output is synchronous to RCLK0.
4. OE0 = LOW.
5. MD IW OW WDDR RDDR FWFT/SI
1 D/C D/C 1 1 0
RCLK0
REN0
EREN0
ERCLK0
EF0
RCS0
tENS
tREF
tERCLK
tENH
Q[9:0]
tENS
tENH
tCLKEN tCLKEN tCLKEN tCLKEN
tOLZ tA
tA
tCLKEN
tAtOLZ
tOLZ tA
tAtAtA
tA
WD-10 WD-9 WD-8 WD-6 WD-5 WD-4 WD-3 WD-2 Last Word WD
6158 drw29
tCLKEN
tA
WD-7 WD-6
tA
WD-1
tENS
NO Read NO Read
tENS
tENH
tENS
tENH
50
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync™ DDR/SDR FIFO
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
FEBRUARY 11, 2009
Figure 27. Echo RCLK and Echo Read Enable Operation (Quad mode, FWFT mode, SDR to SDR)
NOTE:
1. The timing diagram shown is for FIFO0. FIFO1-3 exhibit the same behavior.
2. The O/P Register is the internal output register. Its contents are available on the Qn output bus only when RCS0 and OE0 are both active, LOW, that is the bus is not in High-
Impedance state.
3. OE0 is LOW.
Cycle:
a&b. At this point the FIFO is empty, OR0 is HIGH.
RCS0 and REN0 are both disabled, the output bus is High-Impedance.
c. Word Wn+1 falls through to the output register, OR0 goes active, LOW.
RCS0 is HIGH, therefore the Qn outputs are High-Impedance. EREN0 goes LOW to indicate that a new word has been placed on the output register.
d. EREN0 goes HIGH, no new word has been placed on the output register on this cycle.
e. No Operation.
f. RCS0 is LOW on this cycle, therefore the Qn outputs go to Low-Impedance and the contents of the output register (Wn+1) are made available.
NOTE: In FWFT mode is important to take RCS0 active LOW at least one cycle ahead of REN0, this ensures the word (Wn+1) currently in the output register is made
available for at least one cycle.
g. REN0 goes active LOW, this reads out the second word, Wn+2.
EREN0 goes active LOW to indicate a new word has been placed into the output register.
h. Word Wn+3 is read out, EREN0 remains active, LOW indicating a new word has been read out.
NOTE: Wn+3 is the last word in the FIFO.
i. This is the next enabled read after the last word, Wn+3 has been read out. OR0 flag goes HIGH and EREN0 goes HIGH to indicate that there is no new word available.
4. OE0 is LOW, WDDR = LOW, and RDDR = LOW.
Q[9:0]
O/P
Reg.
t
A
t
REF
OR0
6158 drw32
t
RCSLZ
REN0
t
ENS
t
ENH
RCS0
t
ENS
RCLK0
abcdefghi
W
n+1
WCLK0
WEN0
D[9:0]
t
SKEW1
t
ENS
t
DS
t
ENH
W
n+2
W
n+3
ERCLK0
EREN0
t
CLKEN
t
CLKEN
t
CLKEN
t
CLKEN
W
n+1
W
n+2
W
n+3
t
A
t
REF
W
n+1
W
n+2
W
n+3
t
A
W
n
Last Word
t
A
t
A
t
DH
t
DH
t
DH
t
DS
t
DS
12
t
ERCLK
HIGH-Z
51
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync™ DDR/SDR FIFO
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
FEBRUARY 11, 2009
6158 drw33
RCLK0
REN0
t
ERCLK
ERCLK0
RCS0
t
ENS
EREN0
t
CLKEN
t
CLKEN
t
CLKEN
EF0
t
REF
Q[9:0]
t
OLZ
t
A
t
A
t
A
t
A
t
A
W
D-1
W
D Last Word
t
ENH
t
ENS
Figure 28. Echo Read Clock and Read Enable Operation (Quad mode, IDT Standard mode, SDR to SDR)
NOTES:
1. The timing diagram shown is for FIFO0. FIFO1-3 exhibit the same behavior.
2. The EREN0 output is LOW if RCS0 and REN0 are LOW on the rising RCLK0 edge provided that the FIFO is not empty. If the FIFO is empty, EREN0 will go HIGH to indicate that
there is no new word available.
3. The EREN0 output is synchronous to RCLK0.
4. OE0 = LOW.
5. MD IW OW WDDR RDDR FWFT/SI
1 D/C D/C 0 0 0
52
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync™ DDR/SDR FIFO
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
FEBRUARY 11, 2009
Figure 29. Loading of Programmable Flag Registers (IDT Standard and FWFT modes)
NOTES:
1. See Table 2 - Default Programming Flag Offsets for the values of x.
2. See Figure 4 - Offset Register Serial Bit Sequence for data sequence information.
t
SENH
t
SDH
SCLK
SWEN
SI
6158 drw34
EMPTY OFFSET 3 FULL OFFSET 3
BIT X
(1)
t
SENS
t
SDS
BIT X
(1)
BIT 1
t
SCLK
t
SCKH
t
SCKL
BIT 1
EMPTY OFFSET 0 FULL OFFSET 0
BIT X
(1)
BIT X
(1)
BIT 1BIT 1
Figure 30. Reading of Programmable Flag Registers (IDT Standard and FWFT modes)
NOTES:
1. See Table 2 - Default Programming Flag Offsets for the values of x.
2. See Figure 3 - Offset Register Serial Bit Sequence for data sequence information.
SCLK
SREN
SO
6158 drw35
BIT 0
EMPTY OFFSET 3 FULL OFFSET 3
BIT X
(1)
t
SENS
t
SOA
t
SEN
H
BIT X
(1)
t
ENH
t
SCLK
t
SCKH
t
SCKL
BIT 0
BIT 0
BIT X
(1)
BIT X
(1)
t
SOA
BIT 0
EMPTY OFFSET 0 FULL OFFSET 0
53
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync™ DDR/SDR FIFO
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
FEBRUARY 11, 2009
WCLK0
WEN0
PAF0
RCLK0
REN0
6158 drw36
1212
D-(m0+1) words
in FIFO
(2)
D - m0 words in FIFO
(2)
D - (m0 +1) words in FIFO
(2)
t
ENH
t
ENS
t
PAFS
t
ENS
t
ENH
t
CLKL
t
SKEW3
(4)
t
PAFS
t
CLKL
WCLK0
WEN0
PAE0
RCLK0 12 12
REN0
6158 drw37
n0 + 1 words in FIFO
(3)
,
n0 + 2 words in FIFO
(4)
t
ENS
t
SKEW3
(5)
t
ENH
t
PAES
n0 words in FIFO
(3)
,
n0 + 1 words in FIFO
(4)
t
PAES
n0 words in FIFO
(3)
,
n0 + 1 words in FIFO
(4)
t
ENS
t
ENH
t
CLKH
t
CLKL
NOTES:
1. The timing diagram shown is for FIFO0. FIFO1-3 exhibit the same behavior.
2. m0 = PAF0 offset .
2. D = maximum FIFO depth. For density of FIFO with bus-matching, refer to the bus-matching section on page 19.
4. tSKEW3 is the minimum time between a rising RCLK0 edge and a rising WCLK0 edge to guarantee that PAF0 will go HIGH (after one WCLK0 cycle plus tPAFS). If the time
between the rising edge of RCLK0 and the rising edge of WCLK0 is less than tSKEW2, then the PAF0 deassertion time may be delayed one extra WCLK0 cycle.
5. PAF0 is asserted and updated on the rising edge of WCLK0 only.
6. RCS0 = LOW, and WCS0 = LOW.
7. MD IW OW WDDR RDDR PFM
1 D/C D/C 0 0 1
Figure 31. Synchronous Programmable Almost-Full Flag Timing (Quad mode, IDT Standard and FWFT mode, SDR to SDR)
NOTES:
1. The timing diagram shown is for FIFO0. FIFO1-3 exhibit the same behavior.
2 . n0 = PAE0 offset.
3. For IDT Standard mode
4. For FWFT mode.
5.
tSKEW3 is the minimum time between a rising WCLK0 edge and a rising RCLK0 edge to guarantee that PAE
0
will go HIGH (after one RCLK0 cycle plus tPAES). If the time between
the rising edge of WCLK0 and the rising edge of RCLK0 is less than tSKEW3, then the PAE
0
deassertion may be delayed one extra RCLK0 cycle.
6. PAE0 is asserted and updated on the rising edge of RCLK0 only.
7. RCS0 = LOW, and WCS0 = LOW.
8. MD IW OW WDDR RDDR PFM
1 D/C D/C 0 0 1
Figure 32. Synchronous Programmable Almost-Empty Flag Timing (Quad mode, IDT Standard and FWFT mode, SDR to SDR)
54
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync™ DDR/SDR FIFO
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
FEBRUARY 11, 2009
WCLK0
WEN0
PAF0D - (m0 + 1) words
in FIFO
RCLK0
tPAFA
REN0
6158 drw38
D - m0 words
in FIFO
D - (m0 + 1) words in FIFO
tENS
tPAFA
tENH
tENS
tCLKLtCLKH
WCLK0
WEN0
PAE0
n0 words in FIFO
(3)
,
n0 + 1 words in FIFO
(4)
RCLK0
REN0
6158 drw39
t
PAEA
n0 + 1 words in FIFO
(3)
,
n 0+ 2 words in FIFO
(4)
t
PAEA
t
ENS
t
ENS
t
ENH
t
CLKL
t
CLKH
n0 words in FIFO
(3)
,
n0 + 1 words in FIFO
(4)
NOTES:
1. The timing diagram shown is for FIFO0. FIFO1-3 exhibit the same behavior.
2. m0 = PAF0 offset.
3. D = maximum FIFO depth. For density of FIFO with bus-matching, refer to the bus-matching section on page 19.
4. PAF0 is asserted to LOW on WCLK0 transition and reset to HIGH on RCLK0 transition.
5. RCS0 = LOW, and WCS0 = LOW.
6. MD IW OW WDDR RDDR PFM
1 D/C D/C 0 0 0
Figure 33. Asynchronous Programmable Almost-Full Flag Timing (Quad mode, IDT Standard and FWFT mode, SDR to SDR)
NOTES:
1. The timing diagram shown is for FIFO0. FIFO1-3 exhibit the same behavior.
2 . n0 = PAE0 offset.
3. For IDT Standard Mode.
4. For FWFT Mode.
5. PAE0 is asserted LOW on RCLK0 transition and reset to HIGH on WCLK0 transition.
6. RCS0 = LOW, and WCS0 = LOW.
7. MD IW OW WDDR RDDR PFM
1 D/C D/C 0 0 0
Figure 34. Asynchronous Programmable Almost-Empty Flag Timing (Quad mode, IDT Standard and FWFT mode, SDR to SDR)
55
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync™ DDR/SDR FIFO
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
FEBRUARY 11, 2009
Figure 35. Power Down Operation
6158 drw40
WCLK
WEN
D[39:0]
RCLK
REN
Q[39:0]
PD
ERCLK
EREN
t
DS
t
DH
t
DH
t
DH
t
DS
1234
(1)
t
A
t
A
t
A
t
ERCLK
t
EREN
t
DS
1ns
t
PDHZ(7)
t
PDLZ(2)
t
A
t
PDL
t
PDH(2)
t
PDH(2)
t
EREN
W
DH
W
DS
Hi-Z
Hi-Z
W
D4
W
D3
W
D2
W
D1
W
D10
W
D11
W
D12
W
D13
t
DS
Hi-Z
NOTES:
1 . All read and write operations must have ceased a minimum of 4 WCLK and 4 RCLK cycles before power down is asserted. REN and WEN must be held HIGH during this interval.
2. When the PD input becomes deasserted, there will be a 1µs waiting period before read and write operations can resume.
All input and output signals will also resume after this time period.
3. Setup and configuration static inputs are not affected during power down.
4. Serial programming and JTAG programming port are inactive during power down.
5. RCS = 0, WCS = 0 and OE = 0. These signals can toggle during and after power down.
6. All flags remain active and maintain their current states.
7. During power down, all outputs will be in high-impedance.
56
CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 408-360-1753
San Jose, CA 95138 fax: 408-284-2775 email: FIFOhelp@idt.com
www.idt.com
Plastic Ball Grid Array (PBGA, BB324-1)
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Low Power
6158 drw41
Commercial Only
Commercial and Industrial
L
XXXXX
Device Type
X
Power
XX
Speed
X
Package
X
Process /
Temperature
Range
BLANK
I
(1)
72T54242 32,768 x 10 x 4/32,768 x 10 x 2 ⎯ 2.5V Quad/Dual TeraSync
TM
DDR/SDR FIFO
72T54252 65,536 x 10 x 4/65,536 x 10 x 2 ⎯ 2.5V Quad/Dual TeraSync
TM
DDR/SDR FIFO
72T54262 131,072 x 10 x 4/131,072 x 10 x 2 ⎯ 2.5V Quad/Dual TeraSync
TM
DDR/SDR FIFO
Clock Cycle Time (t
CLK
)
Speed in Nanoseconds
BB
5
6-7
Green
G
X
ORDERING INFORMATION
NOTES:
1. Industrial temperature range product for the 6-7 speed grade is available as a standard device. All other speed grades available by special order.
2. Green parts available. For specific speeds contact your sales office.
DATASHEET DOCUMENT HISTORY
12/01/2003 pgs. 1, 6, 13, 27, and 30.
03/22/2005 pgs. 1, 4, 7, 12-15 and 56.
02/11/2009 pgs. 1 and 56.
