+30 V/±15 V Operation
128-Position Digital Potentiometer
AD7376
FEATURES
128 positions
10 kΩ, 50 kΩ, 100 kΩ
20 V to 30 V single-supply operation
±10 V to ±15 V dual-supply operation
3-wire SPI®-compatible serial interface
THD 0.006% typical
Programmable preset
Power shutdown: less than 1 µA
iCMOS™ process technology
APPLICATIONS
High voltage DAC
Programmable power supply
Programmable gain and offset adjustment
Programmable filters, delays
Actuator control
Audio volume control
Mechanical potentiometer replacement
FUNCTIONAL BLOCK DIAGRAM
VDD
A
W
B
VSS
SDI
CLK
CS
SDO
7 7
R
7-BIT
LATCH
7-BIT
SERIAL
REGISTER
Q
DCK
AD7376
01119-001
SHDN
SHDN
RS
GND
Figure 1.
GENERAL DESCRIPTION
The AD73761 is one of the few high voltage, high performance
digital potentiometers2 on the market. This device can be used
as a programmable resistor or resistor divider. The AD7376
performs the same electronic adjustment function as mechanical
potentiometers, variable resistors, and trimmers with enhanced
resolution, solid-state reliability, and programmability. With
digital rather than manual control, the AD7376 provides layout
flexibility and allows closed-loop dynamic controllability.
The AD7376 features sleep-mode programmability in shutdown
that can be used to program the preset before device activation,
thus providing an alternative to costly EEPROM solutions.
The AD7376 is available in 14-lead TSSOP and 16-lead wide
body SOIC packages in 10 kΩ, 50 kΩ, and 100 kΩ options. All
parts are guaranteed to operate over the −40°C to +85°C
extended industrial temperature range.
1 Patent number: 54952455.
2 The terms digital potentiometer and RDAC are used interchangeably.
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©1997–2011 Analog Devices, Inc. All rights reserved.
AD7376
Rev. D | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Electrical Characteristics—10 kΩ Version ................................ 3
Electrical Characteristics—50 kΩ, 100 kΩ Versions ............... 4
Timing Specifications .................................................................. 5
3-Wire Digital Interface ................................................................... 6
Absolute Maximum Ratings ............................................................ 7
ESD Caution .................................................................................. 7
Pin Configurations and Function Descriptions ........................... 8
Typical Performance Characteristics ............................................. 9
Theory of Operation ...................................................................... 12
Programming the Variable Resistor ......................................... 12
Programming the Potentiometer Divider ............................... 13
3-Wire Serial Bus Digital Interface .......................................... 13
Daisy-Chain Operation ............................................................. 14
ESD Protection ........................................................................... 14
Terminal Voltage Operating Range ......................................... 14
Power-Up and Power-Down Sequences .................................. 14
Layout and Power Supply Biasing ............................................ 15
Applications Information .............................................................. 16
High Voltage DAC ...................................................................... 16
Programmable Power Supply ................................................... 16
Audio Volume Control .............................................................. 17
Outline Dimensions ....................................................................... 18
Ordering Guide .......................................................................... 19
REVISION HISTORY
8/11—Rev. C to Rev. D
Changes to Output Logic Low Conditions, Table 1 ..................... 3
Changes to Output Logic Low Conditions, Table 2 ..................... 5
Changes to Figure 28 ...................................................................... 14
Updates Outline Dimensions ........................................................ 18
7/09—Rev. B to Rev. C
Changes to Features Section............................................................ 1
Updates Outline Dimensions ........................................................ 19
Changes to Ordering Guide .......................................................... 20
3/07—Rev. A to Rev. B
Updated Format .................................................................. Universal
Changes to Absolute Maximum Ratings ....................................... 7
Changes to ESD Protection Section ............................................. 14
Changes to Ordering Guide .......................................................... 19
11/05—Rev. 0 to Rev. A
Updated Format .................................................................. Universal
Deleted DIP Package .......................................................... Universal
Changes to Features ..........................................................................1
Separated Electrical Characteristics into Table 1 and Table 2 .....3
Separated Interface Timing into Table 3 ........................................5
Changes to Table 1 Through Table 3...............................................3
Added Table 4 ....................................................................................6
Added Figure 2...................................................................................6
Changes to Absolute Maximum Ratings Section ..........................7
Deleted Parametric Test Circuits Section .......................................7
Changes to Typical Performance Characteristics..........................9
Added Daisy-Chain Operation Section ...................................... 14
Added ESD Protection Section ..................................................... 14
Added Terminal Voltage Operating Range Section ................... 14
Added Power-Up and Power-Down Sequences Section ........... 14
Added Layout and Power Supply Biasing Section ..................... 15
Added Applications Section .......................................................... 16
Updated Outline Dimensions ....................................................... 18
Changes to Ordering Guide .......................................................... 19
10/97—Revision 0: Initial Version
AD7376
Rev. D | Page 3 of 20
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—10 kΩ VERSION
VDD/VSS = ±15 V ± 10%, VA = VDD, VB = VSS/0 V, −40°C < TA < +85°C, unless otherwise noted.
Table 1.
Parameter Symbol Conditions Min Typ 1 Max Unit
DC CHARACTERISTICS—
RHEOSTAT MODE
Resistor Differential Nonlinearity2 R-DNL RWB, VA = NC, VDD/VSS = ±15 V −1 ±0.5 +1 LSB
Resistor Nonlinearity2 R-INL RWB, VA = NC, VDD/VSS = ±15 V −1 ±0.5 +1 LSB
Nominal Resistor Tolerance ∆RAB TA = 25°C −30 +30 %
Resistance Temperature Coefficient3 (∆RAB/RAB)/∆T × 106 VAB = VDD, wiper = no connect −300 ppm/°C
Wiper Resistance RW VDD/VSS = ±15 V 120 200 Ω
VDD/VSS = ±5 V 260 Ω
DC CHARACTERISTICS—
POTENTIOMETER DIVIDER MODE
Integral Nonlinearity4 INL VDD/VSS = ±15 V −1 ±0.5 +1 LSB
Differential Nonlinearity4 DNL VDD/VSS = ±15 V −1 ±0.5 +1 LSB
Voltage Divider Temperature
Coefficient
(∆VW/VW)/∆T × 106 Code = 0x40 5 ppm/°C
Full-Scale Error VWFSE Code = 0x7F, VDD/VSS = ±15 V −3 −1.5 0 LSB
Zero-Scale Error VWZSE Code = 0x00, VDD/VSS = ±15 V 0 1.5 3 LSB
RESISTOR TERMINALS
Voltage Range5 VA, B, W VSS VDD V
Capacitance6 A, B CA, B f = 1 MHz, measured to GND,
code = 0x40
45 pF
Capacitance6 CW f = 1 MHz, measured to GND,
code = 0x40
60 pF
Shutdown Supply Current7 IA_SD VA = VDD, VB = 0 V, SHDN = 0 0.02 1 µA
Shutdown Wiper Resistance RW_SD VA = VDD, VB = 0 V, SHDN = 0, VDD = 15 V 170 400 Ω
Common-Mode Leakage ICM VA = VB = VW 1 nA
DIGITAL INPUTS AND OUTPUTS
Input Logic High VIH VDD = 5 V or 15 V 2.4 V
Input Logic Low VIL VDD = 5 V or 15 V 0.8 V
Output Logic High VOH RPull-Up = 2.2 kΩ to 5 V 4.9 V
Output Logic Low VOL IOL = 1.6 mA, VDD = 15 V 0.4 V
Input Current IIL VIN = 0 V or 5 V ±1 µA
Input Capacitance6 CIL 5 pF
POWER SUPPLIES
Power Supply Range VDD/VSS Dual-supply range ±4.5 ±16.5 V
Power Supply Range VDD Single-supply range, VSS = 0 4.5 33 V
Positive Supply Current IDD VIH = 5 V or VIL = 0 V, VDD/VSS = ±15 V 2 mA
VIH = 5 V or VIL = 0 V, VDD/VSS = ±5 V 12 25 µA
Negative Supply Current ISS VIH = 5 V or VIL = 0 V, VDD/VSS = ±15 V −0.1 mA
VIH = 5 V or VIL = 0 V, VDD/VSS = ±5 V −0.1 mA
Power Dissipation8 PDISS VIH = 5 V or VIL = 0 V, VDD/VSS = ±15 V 31.5 mW
Power Supply Rejection Ratio PSRR ΔVDD/ΔVSS = ±15 V ± 10% −0.2 ±0.05 +0.2 %/%
AD7376
Rev. D | Page 4 of 20
Parameter Symbol Conditions Min Typ 1 Max Unit
DYNAMIC CHARACTERISTICS6, 9,10
Bandwidth −3 dB BW Code = 0x40 470 kHz
Total Harmonic Distortion THDW VA = 1 V rms, VB = 0 V, f = 1 kHz 0.006 %
VW Settling Time tS VA = 10 V, VB = 0 V, ±1 LSB error band 4 µs
Resistor Noise Voltage
e
N_WB
R
WB
= 5 kΩ, f = 1 kHz
0.9
nV√Hz
1 Typical values represent average readings at 25°C, VDD = 15 V, and VSS = −15 V.
2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum and minimum resistance wiper positions. R-DNL
measures the relative step change from an ideal value measured between successive tap positions. Parts are guaranteed monotonic.
3 Pb-free parts have a 35 ppm/°C temperature coefficient (tempco).
4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider, similar to a voltage output digital-to-analog converter. VA = VDD and VB = 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
5 Resistor Terminals A, B, and W have no limitations on polarity with respect to each other.
6 Guaranteed by design and not subject to production test.
7 Measured at the A terminal. A terminal is open circuit in shutdown mode.
8 PDISS is calculated from (IDD × VDD) + abs(ISS × VSS). CMOS logic level inputs result in minimum power dissipation.
9 Bandwidth, noise, and settling times are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest
bandwidth. The highest R value results in the minimum overall power consumption.
10 All dynamic characteristics use VDD = 15 V and VSS = −15 V.
ELECTRICAL CHARACTERISTICS—50 kΩ, 100 kΩ VERSIONS
VDD/VSS = ±15 V ± 10% or ±5 V ± 10%, VA = VDD, VB = VSS/0 V, −40°C < TA < +85°C, unless otherwise noted.
Table 2.
Parameter Symbol Conditions Min Typ 1 Max Unit
DC CHARACTERISTICS—RHEOSTAT MODE
Resistor Differential Nonlinearity2 R-DNL RWB, VA = NC −1 ±0.5 +1 LSB
Resistor Nonlinearity2 R-INL RWB, VA = NC, RAB = 50 kΩ −1.5 ±0.5 +1.5 LSB
RWB, VA = NC, RAB = 100 kΩ −1 ±0.5 +1 LSB
Nominal Resistor Tolerance ∆RAB TA = 25°C −30 +30 %
Resistance Temperature Coefficient3 (∆RAB/RAB)/∆T × 106 VAB = VDD, wiper = no connect −300 ppm/°C
Wiper Resistance RW VDD/VSS = ±15 V 120 200 Ω
VDD/VSS = ±5 V 260 Ω
DC CHARACTERISTICS—
POTENTIOMETER DIVIDER MODE
Integral Nonlinearity4 INL −1 ±0.5 +1 LSB
Differential Nonlinearity4 DNL −1 ±0.5 +1 LSB
Voltage Divider Temperature
Coefficient
(∆VW/VW)/∆T × 106 Code = 0x40 5 ppm/°C
Full-Scale Error VWFSE Code = 0x7F −2 −0.5 0 LSB
Zero-Scale Error VWZSE Code = 0x00 0 0.5 1 LSB
RESISTOR TERMINALS
Voltage Range5 VA, B, W VSS VDD V
Capacitance6 A, B CA, B f = 1 MHz, measured to GND,
code = 0x40
45 pF
Capacitance
6
C
W
f = 1 MHz, measured to GND,
code = 0x40
60
pF
Shutdown Supply Current7 IA_SD VA = VDD, VB = 0 V, SHDN = 0 0.02 1 µA
Shutdown Wiper Resistance RW_SD VA = VDD, VB = 0 V, SHDN = 0, VDD = 15 V 170 400 Ω
Common-Mode Leakage ICM VA = VB = VW 1 nA
AD7376
Rev. D | Page 5 of 20
Parameter Symbol Conditions Min Typ 1 Max Unit
DIGITAL INPUTS AND OUTPUTS
Input Logic High VIH VDD = 5 V or 15 V 2.4 V
Input Logic Low VIL VDD = 5 V or 15 V 0.8 V
Output Logic High VOH RPull-Up = 2.2 kΩ to 5 V 4.9 V
Output Logic Low
V
OL
I
OL
= 1.6 mA, V
DD
= 15 V
0.4
V
Input Current IIL VIN = 0 V or 5 V ±1 µA
Input Capacitance6 CIL 5 pF
POWER SUPPLIES
Power Supply Range VDD/VSS Dual-supply range ±4.5 ±16.5 V
Power Supply Range VDD Single-supply range, VSS = 0 4.5 33 V
Positive Supply Current IDD VIH = 5 V or VIL = 0 V, VDD/VSS = ±15 V 2 mA
VIH = 5 V or VIL = 0 V, VDD/VSS = ±5 V 12 25 µA
Negative Supply Current ISS VIH = 5 V or VIL = 0 V, VDD/VSS = ±15 V −0.1 mA
V
IH
= 5 V or V
IL
= 0 V, V
DD
/V
SS
= ±5 V
−0.1
mA
Power Dissipation8 PDISS VIH = 5 V or VIL = 0 V, VDD/VSS = ±15 V 31.5 mW
Power Supply Rejection Ratio PSRR −0.25 ±0.1 +0.25 %/%
DYNAMIC CHARACTERISTICS6, 9, 10
Bandwidth −3 dB BW RAB = 50 kΩ, code = 0x40 90 kHz
RAB = 100 kΩ, code = 0x40 50 kHz
Total Harmonic Distortion THDW VA = 1 V rms, VB = 0 V, f = 1 kHz 0.002 %
VW Settling Time tS VA = 10 V, VB = 0 V, ±1 LSB error band 4 µs
Resistor Noise Voltage eN_WB RWB = 25 kΩ, f = 1 kHz 2 nV√Hz
1 Typical values represent average readings at 25°C, VDD = 15 V, and VSS = −15 V.
2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum and minimum resistance wiper positions. R-DNL
measures the relative step change from an ideal value measured between successive tap positions. Parts are guaranteed monotonic.
3 Pb-free parts have a 35 ppm/°C temperature coefficient.
4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider, similar to a voltage output digital-to-analog converter. VA = VDD and VB = 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
5 Resistor Terminals A, B, and W have no limitations on polarity with respect to each other.
6 Guaranteed by design and not subject to production test.
7 Measured at the A terminal. A terminal is open circuit in shutdown mode.
8 PDISS is calculated from (IDD × VDD) + abs(ISS × VSS). CMOS logic level inputs result in minimum power dissipation.
9 Bandwidth, noise, and settling times are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest
bandwidth. The highest R value results in the minimum overall power consumption.
10 All dynamic characteristics use VDD = 15 V and VSS = −15 V.
TIMING SPECIFICATIONS
Table 3.
Parameter Symbol Conditions Min Typ Max Unit
INTERFACE TIMING CHARACTERISTICS1, 2
Clock Frequency fCLK 4 MHz
Input Clock Pulse Width tCH, tCL Clock level high or low 120 ns
Data Setup Time
t
DS
30
ns
Data Hold Time tDH 20 ns
CLK to SDO Propagation Delay3 tPD RPull-Up = 2.2 kΩ, CL < 20 pF 10 100 ns
CS Setup Time tCSS 120 ns
CS High Pulse Width tCSW 150 ns
Reset Pulse Width tRS 120 ns
CLK Fall to CS Fall Hold Time tCSH0 10 ns
CLK Rise to CS Rise Hold Time tCSH 120 ns
CS Rise to Clock Rise Setup tCS1 120 ns
1 Guaranteed by design and not subject to production test.
2 See Figure 3 for the location of the measured values. All input control voltages are specified with tR = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
Switching characteristics are measured using VDD = 15 V and VSS = −15 V.
3 Propagation delay depends on value of VDD, RPull-Up, and CL.
AD7376
Rev. D | Page 6 of 20
3-WIRE DIGITAL INTERFACE
Table 4. AD7376 Serial Data-Word Format1
MSB LSB
D6 D5 D4 D3 D2 D1 D0
26 20
1 Data is loaded MSB first.
D6 D5 D4 D3 D2 D1 D0
1
SDI 0
1
CLK 0
1
CS 0
1
V
OUT
0
01119-002
RDAC REGISTER LO AD
Figure 2. AD7376 3-Wire Digital Interface Timing Diagram
(VA = VDD, VB = 0 V, VW = VOUT)
±1 LS B E RROR BAND
±1 LS B
t
S
t
CSW
t
CSH
t
CL
V
DD
V
OUT
0V
CS 0
1
t
CSH0
t
CSS
t
CH
0
1
1
0
1
SDI
(DATA I N)
SDO
(DATA OUT)
CLK
D
X
D
X
t
DS
t
DH
D'
X
D'
X
t
PD_MAX
t
CS1
01119-003
0
Figure 3. Detail Timing Diagram
AD7376
Rev. D | Page 7 of 20
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 5.
Parameter Rating
VDD to GND −0.3 V to +35 V
VSS to GND +0.3 V to −16.5 V
VDD to VSS −0.3 V to +35 V
VA, VB, VW to GND VSS to VDD
Maximum Current
IWB, IWA Pulsed ±20 mA
I
WB
Continuous (R
WB
≤ 6 kΩ, A open,
VDD/VSS = 30 V/0 V)1
±5 mA
IWA Continuous (RWA ≤ 6 kΩ, B open,
VDD/VSS = 30 V/0 V)1
±5 mA
Digital Input and Output Voltages to GND 0 V to VDD + 0.3 V
Operating Temperature Range −40°C to +85°C
Maximum Junction Temperature (T
JMAX
)
2
150°C
Storage Temperature Range −65°C to +150°C
Reflow Soldering
Peak Temperature 260°C
Time at Peak Temperature 20 sec to 40 sec
Package Power Dissipation
(T
JMAX
− T
A
)/θ
JA
Thermal Resistance θJA
16-Lead SOIC_W 120°C/W
14-Lead TSSOP 240°C/W
1 Maximum terminal current is bound by the maximum current handling of
the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.
2 Package power dissipation = (TJMAX – TA)/θJA.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
AD7376
Rev. D | Page 8 of 20
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
01119-004
A
1
B
2
V
SS 3
GND
4
W
14
NC
13
V
DD
12
SDO
11
CS
5
RS
6
CLK
7
SHDN
10
SDI
9
NC
8
NC = NO CONNECT
AD7376
TOP VIEW
(Not to Scale)
Figure 4. 14-Lead TSSOP Pin Configuration
01119-005
A
1
B
2
V
SS 3
GND
4
W
16
NC
15
V
DD
14
SDO
13
CS
5
SHDN
12
RS
6
SDI
11
CLK
7
NC
10
NC
8
NC
9
NC = NO CONNECT
AD7376
TOP VIEW
(Not to Scale)
Figure 5. 16-Lead SOIC_W Pin Configuration
Table 6.Pin Function Descriptions
Pin No.
14-Lead
TSSOP
16-Lead
SOL Mnemonic Description
1 1 A A Terminal. VSS ≤ VA ≤ VDD.
2 2 B B Terminal. VSS ≤ VB ≤ VDD.
3 3 VSS Negative Power Supply.
4 4 GND Digital Ground.
5 5 CS Chip Select Input, Active Low. When CS returns high, data is loaded into the wiper register.
6 6 RS Reset to Midscale.
7 7 CLK Serial Clock Input. Positive edge triggered.
8 8, 9, 10 NC No Connect. Let it float or ground.
9 11 SDI Serial Data Input (data loads MSB first).
10 12 SHDN Shutdown. A terminal open ended; W and B terminals shorted. Can be used as
programmable preset.1
11
13
SDO
Serial Data Output.
12 14 VDD Positive Power Supply.
13 15 NC No Connect. Let it float or ground.
14 16 W Wiper Terminal. VSS ≤ VW ≤ VDD.
1 Assert shutdown and program the device during power-up. Then, deassert the shutdown to achieve the desirable preset level.
AD7376
Rev. D | Page 9 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
–0.5
–0.4
–0.3
–0.2
–0.1
0.1
0.2
0.3
0.4
0.5
0
CODE ( Decimal)
012816 32 48 64 80 96 112
VDD = + 15V
VSS = –15V
–40°C
RHEOSTAT MODE INL (LSB)
+85°C
+25°C
01119-006
Figure 6. Resistance Step Position Nonlinearity Error vs. Code
CODE ( Decimal)
012816 32 48 64 80 96 112
–0.5
–0.4
–0.3
–0.2
–0.1
0.1
0.2
0.3
0.4
0.5
0
RHEOSTAT M ODE DNL (LSB)
VDD = + 15V
VSS = –15V
–40°C
+85°C
+25°C
01119-007
Figure 7. Relative Resistance Step Change from Ideal vs. Code
CODE ( Decimal)
012816 32 48 64 80 96 112
–0.5
–0.4
–0.3
–0.2
–0.1
0.1
0.2
0.3
0.4
0.5
0
POTENTIOMETER MODE INL (LSB)
V
DD
= +15V
V
SS
= –15V
–40°C
+85°C
+25°C
01119-008
Figure 8. Potentiometer Divider Nonlinearity Error vs. Code
CODE ( Decimal)
012816 32 48 64 80 96 112
–0.5
–0.4
–0.3
–0.2
–0.1
0.1
0.2
0.3
0.4
0.5
0
POTENTI O MET ER MODE DNL (LSB)
VDD = + 15V
VSS = –15V
–40°C
+85°C
+25°C
01119-009
Figure 9. Potentiometer Divider Differential Nonlinearity Error vs. Code
20
–4
–40
01119-010
TEMPERAT URE ( °C)
SUPPLY CURRENT ( µ A)
16
12
8
4
0
–20 020 40 60 80 100 120
I
DD
@ V
DD
/V
SS
= 30V/ 0V
I
DD
@ V
DD
/V
SS
= ±15V
I
SS
@ V
DD
/V
SS
= 30V/ 0V
I
SS
@ V
DD
/V
SS
= ±15V
Figure 10. Supply Current (IDD, ISS) vs. Temperature
0.5
–0.5
–40
01119-011
TEMPERAT URE ( ºC)
SHUT DOWN CURRE NT (µA)
–20 020 40 60 80 100 120
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
Figure 11. Shutdown Current vs. Temperature
AD7376
Rev. D | Page 10 of 20
–40
01119-012
TOTAL RESISTANCE, RAB (kΩ)
–20 020 40 60 80 100 120
120
100
80
60
40
20
0
TEMPERAT URE ( °C)
10kΩ
50kΩ
100kΩ VDD/VSS = ± 15V
Figure 12. Total Resistance vs. Temperature
350
0
–40
01119-013
TEMPERAT URE ( °C)
WIPER RESISTANCE R
W
(Ω)
–20 020 40 60 80 100 120
300
250
200
150
100
50
R
W
@ V
DD
/V
SS
= ±15V
R
W
@ V
DD
/V
SS
= ±5V
Figure 13. Wiper Contact Resistance vs. Temperature
10kΩ
50kΩ
100kΩ
VDD/VSS = ± 15V
01119-014
120
–40
–20
0
20
40
60
80
100
POTENTIOMETER MODE TEMPCO (ppm/°C)
CODE ( Decimal)
012816 32 48 64 80 96 112
Figure 14. (ΔRWB/RWB)/ΔT Rheostat Mode Tempco
V
DD
/V
SS
= ±15V
10kΩ
50kΩ
100kΩ
01119-015
CODE ( Decimal)
012816 32 48 64 80 96 112
120
–40
–20
0
20
40
60
80
100
RHEOSTAT MODE TEMPCO (ppm/°C)
Figure 15. (ΔVWB/VWB)/ΔT Potentiometer Mode Tempco
0
–601k 1M
01119-016
10k 100k
–6
–12
–18
–24
–30
–36
–42
–48
–54
(dB)
(Hz)
0x40
0x20
0x10
0x08
0x04
0x02
0x01
Figure 16. 10 kΩ Gain vs. Frequency vs. Code
0
–601k 1M
01119-017
10k 100k
–6
–12
–18
–24
–30
–36
–42
–48
–54
(dB)
(Hz)
0x40
0x20
0x10
0x08
0x04
0x02
0x01
Figure 17. 50 kΩ Gain vs. Frequency vs. Code
AD7376
Rev. D | Page 11 of 20
0
–60
1k 1M
01119-018
10k 100k
–6
–12
–18
–24
–30
–36
–42
–48
–54
(dB)
(Hz)
0x40
0x20
0x10
0x08
0x04
0x02
0x01
Figure 18. 100 kΩ Gain vs. Frequency vs. Code
01119-019
CH1 5V CH2 5V M2µs A CH1 4.20V
2
1
T 50%
Figure 19. Midscale to Midscale − 1 Transition Glitch
80
0
100 1M
01119-020
FREQUENCY (Hz)
PSRR (–dB)
1k 10k 100k
60
40
20
CODE = 40
H
, V
A
= V
DD
, V
B
= V
SS
–PSRR @ V
DD
/V
SS
= ±15V
DC ± 10% p-p AC
+PSRR @ V
DD
/V
SS
= ±15V
DC ± 10% p-p AC
–PSRR @ V
DD
/V
SS
= ±5V
DC ± 10% p-p AC
+PSRR @ V
DD
/V
SS
= ±5V
DC ± 10% p-p AC
Figure 20. Power Supply Rejection vs. Frequency
0.1
0.0001
10
01119-021
FREQUENCY (Hz)
THD + N (%)
100k100 1k 10k
0.001
0.01
10kΩ
50kΩ
100kΩ
V
DD
/V
SS
= ±15V
CODE = MIDSCALE
V
IN
= 1Vrms
Figure 21. Total Harmonic Distortion Plus Noise vs. Frequency
1
0.001
0.001
01119-022
AMPLITUDE (V)
THD + N (%)
100.01 0.1 1
0.01
0.1
V
DD
/V
SS
= ±15V
CODE = MIDSCALE
f
IN
= 1kHz
10kΩ
50kΩ
100kΩ
Figure 22. Total Harmonic Distortion Plus Noise vs. Amplitude
6
0
2
4
THEORETIC
A
L I
WB_MAX
(mA)
CODE (Decimal)
012816 32 48 64 80 96 112
01119-023
1
3
5
V
DD
/V
SS
= 30V/0V
V
A
= V
DD
V
B
= 0V
R
AB
= 50kΩ
R
AB
= 100kΩ
R
AB
= 10kΩ
Figure 23. Theoretical Maximum Current vs. Code
AD7376
Rev. D | Page 12 of 20
THEORY OF OPERATION
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation
The part operates in rheostat mode when only two terminals
are used as a variable resistor. The unused terminal can be left
floating or tied to the W terminal as shown in Figure 24.
A
W
B
A
W
B
A
W
B
01119-024
Figure 24. Rheostat Mode Configuration
The nominal resistance between Terminals A and B, RAB, is
available in 10 kΩ, 50 kΩ, and 100 kΩ with ±30% tolerance and
has 128 tap points accessed by the wiper terminal. The 7-bit
data in the RDAC latch is decoded to select one of the 128
possible settings. Figure 25 shows a simplified RDAC structure.
R
S
R
S
R
S
R
S
0x01
0x7F
0x00
A
W
B
SW
B
01119-025
D6
D5
D4
D3
D2
D1
D0
RDAC
LATCH
AND
DECODER
SW
A
R
S
= R
NOMINAL
/128
SHDN
Figure 25. AD7376 Equivalent RDAC Circuit
The general equation determining the digitally programmed
output resistance between the W and the B terminals is
W
AB
WB RR
D
DR 128
)( (1)
where:
D is the decimal equivalent of the binary code loaded in the
7-bit RDAC register from 0 to 127.
RAB is the end-to-end resistance.
RW is the wiper resistance contributed by the on resistance of
the internal switch.
The AD7376 wiper switches are designed with the transmission
gate CMOS topology, and the gate voltage is derived from the
VDD. Each switch’s on resistance, RW, is a function of VDD and
temperature (see Figure 13).
Contrary to the temperature coefficient of RAB, the temperature
coefficient of the wiper resistance is significantly higher because
the wiper resistance doubles with every 100° increase. As a result,
the user must take into consideration the contribution of RW on
the desirable resistance. On the other hand, each switch’s on
resistance is insensitive to the tap point potential and remains
relatively flat at 120 Ω typical at a VDD of 15 V and a
temperature of 25°C.
Assuming that a 10 kΩ part is used, the wiper’s first connection
starts at the B terminal for programming code 0x00, where SWB
is closed. The minimum resistance between Terminals W and B
is therefore 120 Ω in general. The second connection is the first
tap point, which corresponds to 198 Ω (RWB = 1/128 × RAB + RW
= 78 Ω + 120 Ω) for programming code 0x01, and so on.
Each LSB data value increase moves the wiper up the resistor
ladder until the last tap point is reached at 10,042 Ω (RAB – 1 LSB +
RW). Regardless of which settings the part is operating with, care
should be taken to limit the current conducted between any A
and B, W and A, or W and B terminals to a maximum dc
current of 5 mA and a maximum pulse current of 20 mA.
Otherwise, degradation or possible destruction of the internal
switch contact can occur.
Similar to the mechanical potentiometer, the resistance of the
RDAC between the W and A terminals also produces a digitally
controlled complementary resistance, RWA .
When these terminals are used, the B terminal can be opened.
Setting the resistance value for RWA starts at a maximum value
of resistance and decreases as the data loaded into the latch
increases in value. The general equation for this operation is
W
ABWA RR
D
DR
128
128
)( (2)
AD7376
Rev. D | Page 13 of 20
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates a voltage divider at
Wiper W to Terminal B and Wiper W to Terminal A that is
proportional to the input voltage at Terminal A to Terminal B.
Unlike the polarity of VDD to GND, which must be positive,
voltage across Terminal A to Terminal B, Wiper W to Terminal A,
and Wiper W to Terminal B can be at either polarity.
A
V
I
W
B
V
O
01119-026
Figure 26. Potentiometer Mode Configuration
If ignoring the effect of the wiper resistance for the purpose of
approximation, connecting the Terminal A to 30 V and the
Terminal B to ground produces an output voltage at the Wiper W
to Terminal B ranging from 0 V to 1 LSB less than 30 V. Each
LSB of voltage is equal to the voltage applied across Terminals A
and B divided by the 128 positions of the potentiometer divider.
The general equation defining the output voltage at VW with
respect to ground for any valid input voltage applied to
Terminals A and B is
A
WV
D
DV 128
)( =
(3)
A more accurate calculation that includes the effect of wiper
resistance, VW, is
B
AB
WA
A
AB
WB
WV
R
DR
V
R
DR
DV )(
)(
)( +=
(4)
Operation of the digital potentiometer in the divider mode
results in a more accurate operation over temperature. Unlike
when in rheostat mode, the output voltage in divider mode is
primarily dependent on the ratio, not the absolute values, of the
internal resistors RWA and RWB. Therefore, the temperature drift
reduces to 5 ppm/°C.
3-WIRE SERIAL BUS DIGITAL INTERFACE
The AD7376 contains a 3-wire digital interface (CS, CLK, and
SDI). The 7-bit serial word must be loaded MSB first. The
format of the word is shown in Figure 2. The positive edge-
sensitive CLK input requires clean transitions to avoid clocking
incorrect data into the serial input register. Standard logic
families work well. When CS is low, the clock loads data into the
serial register upon each positive clock edge.
The data setup and hold times in Table 3 determine the valid
timing requirements. The AD7376 uses a 7-bit serial input data
register word that is transferred to the internal RDAC register
when the CS line returns to logic high. Extra MSB bits are
ignored.
The AD7376 powers up at a random setting. However, the
midscale preset or any desirable preset can be achieved by
manipulating RS or SHDN with an extra I/O.
When the reset (RS) pin is asserted, the wiper resets to the
midscale value. Midscale reset can be achieved dynamically or
during power-up if an extra I/O is used.
When the SHDN pin is asserted, the AD7376 opens SWA to let
the Terminal A float and to short Wiper W to Terminal B. The
AD7376 consumes negligible power during the shutdown mode
and resumes the previous setting once the SHDN pin is released.
On the other hand, the AD7376 can be programmed with any
settings during shutdown. With an extra programmable I/O
asserting shutdown during power-up, this unique feature allows
the AD7376 with programmable preset at any desirable level.
Table 7 shows the logic truth table for all operations.
Table 7. Input Logic Control Truth Table1
CLK CS RS SHDN Register Activity
L L H H Enables SR, enables SDO pin.
P L H H Shifts one bit in from the SDI pin. The
seventh previously entered bit is
shifted out of the SDO pin.
X P H H Loads SR data into 7-bit RDAC latch.
X H H H No operation.
X
X
L
H
Sets 7-bit RDAC latch to midscale,
wiper centered, and SDO latch cleared.
X H P H Latches 7-bit RDAC latch to 0x40.
X H H L Opens circuits resistor of Terminal A,
connects Wiper W to Terminal B,
turns off SDO output transistor.
1 P = positive edge, X = don’t care, and SR = shift register.
AD7376
Rev. D | Page 14 of 20
DAISY-CHAIN OPERATION
01119-027
CS
SDI SERIAL
REGISTER D
CK
Q
RS
SHDN
SDO
RS
CLK
Figure 27. Detailed SDO Output Schematic of the AD7376
Figure 27 shows the details of the serial data output pin (SDO).
SDO shifts out the SDI content in the previous frame; therefore,
it can be used for daisy-chaining multiple devices. The SDO pin
contains an open-drain N-Channel MOSFET and requires a
pull-up resistor if the SDO function is used.
Users need to tie the SDO pin of one package to the SDI pin of
the next package. For example, in Figure 28, if two AD7376s are
daisy-chained, a total of 14 bits of data are required for each
operation. The first set of seven bits goes to U2; the second set
of seven bits goes to U1. CS should be kept low until all 14 bits
are clocked into their respective serial registers. Then CS is
pulled high to complete the operation.
When daisy-chaining multiple devices, users may need to
increase the clock period because the pull-up resistor and the
capacitive loading at the SDO to SDI interface may induce a
time delay to subsequent devices.
AD7376
SDOSDI
CLKCS
AD7376
SDO
SDI
CLK
CS
µC
5V
R
PU
2.2kΩ
MOSI
SSSCLK
01119-028
U1 U2
Figure 28. Daisy-Chain Configuration
ESD PROTECTION
All digital inputs are protected with a series input resistor and
an ESD structure shown in Figure 29. These structures apply to
digital input pins CS, CLK, SDI, RS, and SHDN.
INPUT
340Ω
LOGIC
PINS
V
DD
GND
01119-029
Figure 29. Equivalent ESD Protection Circuit
All analog terminals are also protected by ESD protection
diodes, as shown in Figure 30.
V
SS
V
DD
A
W
B
01119-030
Figure 30. Equivalent ESD Protection Analog Pins
TERMINAL VOLTAGE OPERATING RANGE
The AD7376 VDD and VSS power supplies define the boundary
conditions for proper 3-terminal digital potentiometer oper-
ation. Applied signals present on Terminals A, B, and W that
are more positive than VDD or more negative than VSS will be
clamped by the internal forward-biased diodes (see Figure 30).
POWER-UP AND POWER-DOWN SEQUENCES
Because of the ESD protection diodes that limit the voltage
compliance at Terminals A, B, and W (see Figure 30), it is
important to power VDD/VSS before applying voltage to
Terminals A, B, and W. Otherwise, the diodes are forward
biased such that VDD/VSS are powered unintentionally and affect
the system. Similarly, VDD/VSS should be powered down last.
The ideal power-up sequence is in the following order: GND,
VDD, VSS, digital inputs, and VA/VB/VW. The order of powering
VA, VB, VW, and the digital inputs is not important, as long as
they are powered after VDD/VSS.
AD7376
Rev. D | Page 15 of 20
LAYOUT AND POWER SUPPLY BIASING
It is a good practice to employ a compact, minimum lead-length
layout design. The leads to the input should be as direct as
possible, with a minimum conductor length. Ground paths
should have low resistance and low inductance.
Similarly, it is also good practice to bypass the power supplies
with quality capacitors. Low ESR (equivalent series resistance)
1 μF to 10 μF tantalum or electrolytic capacitors should be
applied at the supplies to minimize transient disturbances and
filter low frequency ripple. Figure 31 illustrates the basic supply
bypassing configuration for the AD7376.
The ground pin of the AD7376 is a digital ground reference. To
minimize the digital ground bounce, the AD7376 digital ground
terminal should be joined remotely to the analog ground (see
Figure 31).
V
DD
V
DD
V
SS
V
SS
GND
C3
AD7376
C4
C1
+
+C2
10µF
10µF 0.1µF
0.1µF
01119-031
Figure 31. Power Supply Bypassing
AD7376
Rev. D | Page 16 of 20
APPLICATIONS INFORMATION
HIGH VOLTAGE DAC
The AD7376 can be configured as a high voltage DAC as high
as 30 V. The circuit is shown in Figure 32. The output is
1
2
1V2.1
128
)( R
RD
DVO (5)
Where D is the decimal code from 0 to 127.
AD7376
U2
AD8512
V+
V–
AD8512
V
OUT
V
DD
U1B
V
DD
R
BIAS
ADR512
D1
R2
R1
B
100kΩ
0
1119-032
U1A
Figure 32. High Voltage DAC
PROGRAMMABLE POWER SUPPLY
With a boost regulator such as ADP1611, AD7376 can be used
as the variable resistor at the regulator’s FB pin to provide the
programmable power supply (see Figure 33). The output is
2
128
1V23.1 R
R
D
V
AB
O (6)
Note that the AD7376’s VDD is derived from the output. Initially
L1 acts as a short, and VDD is one diode voltage drop below +5 V.
The output slowly establishes to the final value.
The AD7376 shutdown sleep-mode programming can be used
to program a desirable preset level at power-up.
AD7376
ADP1611
1.23V
C
C
150pF
R
C
220kΩ
C
OUT
10µF
V
OUT
D1
L1
4.7µF
IN
GND
SS
FB
RT SW
COMP
U2
C1
0.1µF
V
DD
R1
100kΩ
A
W
B
C
IN
10µF
5V
R2
8.5kΩC
SS
22nF
01119-033
U1
SD
Figure 33. Programmable Power Supply
AD7376
Rev. D | Page 17 of 20
AUDIO VOLUME CONTROL
Because of its good THD performance and high voltage
capability, the AD7376 can be used for digital volume control. If
AD7376 is used directly as an audio attenuator or gain amplifier,
a large step change in the volume level at any arbitrary time can
lead to an abrupt discontinuity of the audio signal, causing an
audible zipper noise. To prevent this, a zero-crossing window
detector can be inserted to the CS line to delay the device
update until the audio signal crosses the window. Since the
input signal can operate on top of any dc levels rather than
absolute zero volt level, zero-crossing, in this case, means the
signal is ac-coupled and the dc offset level is the signal zero
reference point.
The configuration to reduce zipper noise and the result of using
this configuration are shown in Figure 35 and Figure 34,
respectively. The input is ac-coupled by C1 and attenuated
down before feeding into the window comparator formed by
U2, U3, and U4B. U6 is used to establish the signal zero
reference. The upper limit of the comparator is set above its
offset and, therefore, the output pulses high whenever the input
falls between 2.502 V and 2.497 V (or 0.005 V window) in this
example. This output is AND’ed with the chip select signal such
that the AD7376 updates whenever the signal crosses the
window. To avoid constant update of the device, the chip select
signal should be programmed as two pulses, rather than the one
shown in Figure 2.
In Figure 34, the lower trace shows that the volume level
changes from a quarter scale to full scale when a signal change
occurs near the zero-crossing window.
The AD7376 shutdown sleep-mode programming feature can
be used to mute the device at power-up by holding SHDN low
and programming zero scale.
01119-035
CHANNEL 1
FRE Q = 20. 25kHz
1.03V p-p
1
2
NOTES
1. THE L OW E R TRACE S HOW S THAT THE VOL UME LEVEL
CHANGE S FROM QUART E R S CALE TO FULL SCALE, WITH THE
CHANGE OCCURRING NEAR THE ZERO-CRO S S ING WI NDOW.
Figure 34. Input (Trace 1) and Output (Trace 2) of the Circuit in Figure 35
V
DD
V
SS
CS
CLK
SDI
V+
V–
AD7376
100kΩ
+15V
–15V
C3
0.1µF
C2
0.1µF
A
B
W
GND
SDI
CLK
U1
+15V
–15V
V
OUT
U5
01119-034
CS
V+
V+
V–
V–
ADCM371
ADCM371
+5V
+5V
U3
U2
R1
100kΩ
R2
200Ω
+5V
V
IN
U4A
U4B
16
2
4
5
7408
7408
V+
V–
AD8541
+5V
U6
R3
100Ω
R4
90kΩ
R5
10kΩ
C1
1µF
Figure 35. Audio Volume Control with Zipper Noise Reduction
AD7376
Rev. D | Page 18 of 20
OUTLINE DIMENSIONS
COM P LIANT T O JEDE C S TANDARDS M O-153-AB- 1
061908-A
8°
0°
4.50
4.40
4.30
14 8
7
1
6.40
BSC
PI N 1
5.10
5.00
4.90
0.65 BS C
0.15
0.05 0.30
0.19
1.20
MAX
1.05
1.00
0.80 0.20
0.09 0.75
0.60
0.45
COPLANARITY
0.10
SEATING
PLANE
Figure 36. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-013-AA
10.50 (0.4134)
10.10 (0.3976)
0.30 (0.0118)
0.10 (0.0039)
2.65 (0.1043)
2.35 (0.0925)
10.65 (0.4193)
10.00 (0.3937)
7.60 (0.2992)
7.40 (0.2913)
0.75 (0.0295)
0.25 (0.0098)
45°
1.27 (0.0500)
0.40 (0.0157)
COPLANARITY
0.10 0.33 (0.0130)
0.20 (0.0079)
0.51 (0.0201)
0.31 (0.0122)
SEATING
PLANE
8°
0°
16 9
8
1
1.27 (0.0500)
BSC
03-27-2007-B
Figure 37. 16-Lead Standard Small Outline Package [SOIC_W]
Wide Body
(RW-16)
Dimensions shown in millimeters and (inches)
AD7376
Rev. D | Page 19 of 20
ORDERING GUIDE
Model
1
kΩ
Temperature Range
Package Description
2, 3
Package Option
Ordering Quantity
AD7376ARUZ10 10 −40°C to +85°C 14-Lead TSSOP RU-14 96
AD7376ARUZ10-R7 10 −40°C to +85°C 14-Lead TSSOP RU-14 1,000
AD7376ARWZ10 10 −40°C to +85°C 16-Lead SOIC_W RW-16 47
AD7376ARWZ10-RL 10 −40°C to +85°C 16-Lead SOIC_W RW-16 1,000
AD7376ARUZ50-REEL7 50 −40°C to +85°C 14-Lead TSSOP RU-14 1,000
AD7376ARUZ50 50 −40°C to +85°C 14-Lead TSSOP RU-14 96
AD7376ARWZ50 50 −40°C to +85°C 16-Lead SOIC_W RW-16 47
AD7376ARUZ100 100 −40°C to +85°C 14-Lead TSSOP RU-14 96
AD7376ARUZ100-R7 100 −40°C to +85°C 14-Lead TSSOP RU-14 1,000
AD7376ARWZ100 100 −40°C to +85°C 16-Lead SOIC_W RW-16 47
EVAL-AD7376EBZ 10 1
1 Z = RoHS Compliant Part.
2 In SOIC RW-16 package top marking: line 1 shows AD7376; line 2 shows the branding information, where A10 = 10 kΩ, A50 = 50 kΩ, and A100 = 100 kΩ; line 3 shows a
“#” top marking with the date code in YYWW; and line 4 shows the lot number.
3 In TSSOP-14 package top marking: line 1 shows 7376; line 2 shows the branding information, where A10 = 10 kΩ, A50 = 50 kΩ, and A100 = 100 kΩ; line 3 shows a “#”
top marking with the date code in YWW; back side shows the lot number.
AD7376
Rev. D | Page 20 of 20
NOTES
©1997–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D01119-0-8/11(D)
