M95320 M95320-W M95320-R M95640 M95640-W M95640-R 32 Kbit and 64 Kbit Serial SPI bus EEPROMs with high speed clock Feature summary Compatible with SPI Bus Serial Interface (Positive Clock SPI Modes) Single Supply Voltage: - 4.5 to 5.5V for M95320 and M95640 - 2.5 to 5.5V for M95320-W and M95320-W - 1.8 to 5.5V for M95320-R and M95640-R 10MHz, 5MHz or 2MHz clock rates 5ms or 10ms Write Time Status Register Hardware Protection of the Status Register Byte and Page Write (up to 32 Bytes) Self-Timed Programming Cycle Adjustable Size Read-Only EEPROM Area Enhanced ESD Protection More than 1 million Write cycles More than 40-Year Data Retention Packages - ECOPACK(R) (RoHS compliant) July 2006 SO8 (MN) 150 mil width TSSOP8 (DW) 169 mil width MLP8 (MB) 2x3 mm Rev 6 1/44 www.st.com 1 Contents M95320, M95640, M95320-x, M95640-x Contents 1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 Serial Data Output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.0.2 Serial Data Input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.0.3 Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.0.4 Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.0.5 Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.0.6 Write Protect (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Connecting to the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1 4 2.0.1 SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1 Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1.1 4.2 4.1.2 Operating supply voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1.3 Internal device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1.4 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Active Power and Standby Power modes . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.2.1 Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.3 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.4 Data protection and protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2/44 6.1 Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.2 Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.3 Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.3.1 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.3.2 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.3.3 BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.3.4 SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 M95320, M95640, M95320-x, M95640-x 7 Contents 6.4 Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.5 Read from Memory Array (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.6 Write to Memory Array (WRITE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Power-up and delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.1 Power-up state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.2 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 9 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 10 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 11 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3/44 List of tables M95320, M95640, M95320-x, M95640-x List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. 4/44 Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Write-Protected block size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Address range bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Operating conditions (M95320 and M95640) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Operating conditions (M95320-W and M95640-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Operating conditions (M95320-R and M95640-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 DC characteristics (M95320 and M95640, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . 27 DC characteristics (M95320 and M95640, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . 27 DC characteristics (M95320-W and M95640-W, device grade 6). . . . . . . . . . . . . . . . . . . . 28 DC characteristics (M95320-W and M95640-W, device grade 3). . . . . . . . . . . . . . . . . . . . 28 DC characteristics (M95320-R and M95640-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 AC characteristics (M95320 and M95640, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . 30 AC characteristics (M95320 and M95640, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . 31 AC characteristics (M95320-W and M95640-W, device grade 6). . . . . . . . . . . . . . . . . . . . 32 AC characteristics (M95320-W and M95640-W, device grade 3). . . . . . . . . . . . . . . . . . . . 33 AC characteristics (M95320-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 AC characteristics (M95640-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 SO8N - 8 lead Plastic Small Outline, 150 mils body width, package mechanical data . . . 38 TSSOP8 - 8 lead Thin Shrink Small Outline, package mechanical data . . . . . . . . . . . . . . 39 MLP8 - 8-lead Ultra thin Fine pitch Dual Flat No Lead, package mechanical data. . . . . . . 40 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 M95320, M95640, M95320-x, M95640-x List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 8 pin package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Write Enable (WREN) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Write Disable (WRDI) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Read Status Register (RDSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Write Status Register (WRSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Read from Memory Array (READ) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Byte Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Page Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Serial Input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 SO8N - 8 lead Plastic Small Outline, 150 mils body width, package outline . . . . . . . . . . . 38 TSSOP8 - 8 lead Thin Shrink Small Outline, package outline . . . . . . . . . . . . . . . . . . . . . . 39 MLP8 - 8-lead Ultra thin Fine pitch Dual Flat No Lead, package outline . . . . . . . . . . . . . . 40 5/44 Summary description 1 M95320, M95640, M95320-x, M95640-x Summary description These electrically erasable programmable memory (EEPROM) devices are accessed by a high speed SPI-compatible bus. The M95320, M95320-W and M95320-R are 32Kbit devices organized as 4096 x 8 bits. The M95640, M95640-W and M95640-R are 64Kbit devices organized as 8192 x 8 bits. The device is accessed by a simple serial interface that is SPI-compatible. The bus signals are C, D and Q, as shown in Table 1 and Figure 1. The device is selected when Chip Select (S) is taken Low. Communications with the device can be interrupted using Hold (HOLD). In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. ECOPACK(R) packages are Lead-free and RoHS compliant. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 1. Logic diagram VCC D Q C S M95xxx W HOLD VSS AI01789C Figure 2. 8 pin package connections M95xxx S Q W VSS 1 2 3 4 8 7 6 5 VCC HOLD C D AI01790D 1. See Package mechanical section for package dimensions and how to identify pin-1. 6/44 M95320, M95640, M95320-x, M95640-x Table 1. Summary description Signal names C Serial Clock D Serial data Input Q Serial data Output S Chip Select W Write Protect HOLD Hold VCC Supply Voltage VSS Ground 7/44 Signal description 2 M95320, M95640, M95320-x, M95640-x Signal description During all operations, VCC must be held stable and within the specified valid range: VCC(min) to VCC(max). All of the input and output signals must be held High or Low (according to voltages of VIH, VOH, VIL or VOL, as specified in Table 13 to Table 17). These signals are described next. 2.0.1 Serial Data Output (Q) This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C). 2.0.2 Serial Data Input (D) This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be written. Values are latched on the rising edge of Serial Clock (C). 2.0.3 Serial Clock (C) This input signal provides the timing of the serial interface. Instructions, addresses, or data present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on Serial Data Output (Q) changes after the falling edge of Serial Clock (C). 2.0.4 Chip Select (S) When this input signal is High, the device is deselected and Serial Data Output (Q) is at high impedance. Unless an internal Write cycle is in progress, the device will be in the Standby Power mode. Driving Chip Select (S) Low selects the device, placing it in the Active Power mode. After Power-up, a falling edge on Chip Select (S) is required prior to the start of any instruction. 2.0.5 Hold (HOLD) The Hold (HOLD) signal is used to pause any serial communications with the device without deselecting the device. During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data Input (D) and Serial Clock (C) are Don't Care. To start the Hold condition, the device must be selected, with Chip Select (S) driven Low. 2.0.6 Write Protect (W) The main purpose of this input signal is to freeze the size of the area of memory that is protected against Write instructions (as specified by the values in the BP1 and BP0 bits of the Status Register). This pin must be driven either High or Low, and must be stable during all write operations. 8/44 M95320, M95640, M95320-x, M95640-x 3 Connecting to the SPI bus Connecting to the SPI bus These devices are fully compatible with the SPI protocol. All instructions, addresses and input data bytes are shifted in to the device, most significant bit first. The Serial Data Input (D) is sampled on the first rising edge of the Serial Clock (C) after Chip Select (S) goes Low. All output data bytes are shifted out of the device, most significant bit first. The Serial Data Output (Q) is latched on the first falling edge of the Serial Clock (C) after the instruction (such as the Read from Memory Array and Read Status Register instructions) have been clocked into the device. Figure 3 shows three devices, connected to an MCU, on a SPI bus. Only one device is selected at a time, so only one device drives the Serial Data Output (Q) line at a time, all the others being high impedance. Figure 3. Bus master and memory devices on the SPI bus VSS VCC R(2) SDO SPI Interface with (CPOL, CPHA) = (0, 0) or (1, 1) SDI SCK VCC C Q D SPI Bus Master SPI Memory Device R(2) CS3 CS2 VCC C Q D VSS C Q D VCC VSS VSS SPI Memory R(2) Device R(2) SPI Memory Device CS1 S W HOLD S W HOLD S W HOLD AI12836 1. The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate. 2. These pull-up resistors, R, ensure that the memory devices are not selected if the Bus Master leaves the S line in the highimpedance state. As the Bus Master may enter a state where all inputs/outputs are in high impedance at the same time (e.g.: when the Bus Master is reset), the clock line (C) must be connected to an external pull-down resistor so that, when all inputs/outputs become high impedance, S is pulled High while C is pulled Low (thus ensuring that S and C do not become High at the same time, and so, that the tSHCH requirement is met). 9/44 Connecting to the SPI bus 3.1 M95320, M95640, M95320-x, M95640-x SPI modes These devices can be driven by a microcontroller with its SPI peripheral running in either of the two following modes: CPOL=0, CPHA=0 CPOL=1, CPHA=1 For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data is available from the falling edge of Serial Clock (C). The difference between the two modes, as shown in Figure 4, is the clock polarity when the bus master is in Stand-by mode and not transferring data: C remains at 0 for (CPOL=0, CPHA=0) C remains at 1 for (CPOL=1, CPHA=1) Figure 4. SPI modes supported CPOL CPHA 0 0 C 1 1 C D Q MSB MSB AI01438B 10/44 M95320, M95640, M95320-x, M95640-x 4 Operating features 4.1 Supply voltage (VCC) 4.1.1 Operating supply voltage VCC Operating features Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied (see Table 8.). In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually of the order of 10nF to 100nF) close to the VCC/VSS package pins. This voltage must remain stable and valid until the end of the transmission of the instruction and, for a Write instruction, until the completion of the internal write cycle (tW). 4.1.2 Power-up conditions When the power supply is turned on, VCC rises from VSS to VCC. During this time, the Chip Select (S) is not allowed to float but must follow the VCC voltage, therefore the S line should be connected to VCC via a suitable pull-up resistor. In addition, the Chip Select (S) input offers a built-in safety feature, as the S input is edge sensitive as well as level sensitive: after Power-up, the device does not become selected until a falling edge has first been detected on Chip Select (S). This ensures that Chip Select (S) must have been High, prior to going Low to start the first operation. The VCC rise time must not be faster than 1V/s. 4.1.3 Internal device Reset In order to prevent inadvertent Write operations during Power-up, a Power On Reset (POR) circuit is included. At Power-up (continuous rise of VCC), the device will not respond to any instruction until VCC has reached the Power On Reset threshold voltage (this threshold is lower than the minimum VCC operating voltage defined in Tables XX). When VCC has passed the POR threshold, the device is reset and in the following state: Standby Power mode deselected (at next Power-up, a falling edge is required on Chip Select (S) before any instructions can be started). not in the Hold Condition Status Register state: the Write Enable Latch (WEL) is reset to 0 Write In Progress (WIP) is reset to 0. The SRWD, BP1 and BP0 bits of the Status Register are in the same state as when the power was last removed (they are nonvolatile bits). 11/44 Operating features 4.1.4 M95320, M95640, M95320-x, M95640-x Power-down At Power-down (continuous decrease of VCC), as soon as VCC drops from the normal operating voltage to below the Power On Reset threshold voltage, the device stops responding to any instruction sent to it. During Power-down, the device must be deselected and in Standby Power mode (that is there should be no internal Write cycle in progress). Chip Select (S) should be allowed to follow the voltage applied on VCC. 4.2 Active Power and Standby Power modes When Chip Select (S) is Low, the device is selected, and in the Active Power mode. The device consumes ICC, as specified in Table 13 to Table 17. When Chip Select (S) is High, the device is deselected. If an Erase/Write cycle is not currently in progress, the device then goes in to the Standby Power mode, and the device consumption drops to ICC1. 4.2.1 Hold condition The Hold (HOLD) signal is used to pause any serial communications with the device without resetting the clocking sequence. During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data Input (D) and Serial Clock (C) are Don't Care. To enter the Hold condition, the device must be selected, with Chip Select (S) Low. Normally, the device is kept selected, for the whole duration of the Hold condition. Deselecting the device while it is in the Hold condition, has the effect of resetting the state of the device, and this mechanism can be used if it is required to reset any processes that had been in progress. The Hold condition starts when the Hold (HOLD) signal is driven Low at the same time as Serial Clock (C) already being Low (as shown in Figure 5). The Hold condition ends when the Hold (HOLD) signal is driven High at the same time as Serial Clock (C) already being Low. Figure 5 also shows what happens if the rising and falling edges are not timed to coincide with Serial Clock (C) being Low. Figure 5. Hold condition activation C HOLD Hold Condition Hold Condition AI02029D 12/44 M95320, M95640, M95320-x, M95640-x 4.3 Operating features Status Register Figure 6 shows the position of the Status Register in the control logic of the device. The Status Register contains a number of status and control bits that can be read or set (as appropriate) by specific instructions. See Section 6.3: Read Status Register (RDSR) for a detailed description of the Status Register bits. 4.4 Data protection and protocol control Non-volatile memory devices can be used in environments that are particularly noisy, and within applications that could experience problems if memory bytes are corrupted. Consequently, the device features the following data protection mechanisms: Write and Write Status Register instructions are checked that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution. All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state by the following events: - Power-up - Write Disable (WRDI) instruction completion - Write Status Register (WRSR) instruction completion - Write (WRITE) instruction completion The Block Protect (BP1, BP0) bits allow part of the memory to be configured as readonly. This is the Software Protected Mode (SPM). The Write Protect (W) signal allows the Block Protect (BP1, BP0) bits to be protected. This is the Hardware Protected Mode (HPM). For any instruction to be accepted, and executed, Chip Select (S) must be driven High after the rising edge of Serial Clock (C) for the last bit of the instruction, and before the next rising edge of Serial Clock (C). Two points need to be noted in the previous sentence: The `last bit of the instruction' can be the eighth bit of the instruction code, or the eighth bit of a data byte, depending on the instruction (except for Read Status Register (RDSR) and Read (READ) instructions). The `next rising edge of Serial Clock (C)' might (or might not) be the next bus transaction for some other device on the SPI bus. Table 2. Write-Protected block size Status Register Bits Array Addresses Protected Protected Block M95640, M95640-W, M95640-R, M95640-S M95320, M95320-W, M95320-R, M95320-S none none none 1 Upper quarter 1800h - 1FFFh 0C00h - 0FFFh 1 0 Upper half 1000h - 1FFFh 0800h - 0FFFh 1 1 Whole memory 0000h - 1FFFh 0000h - 0FFFh BP1 BP0 0 0 0 13/44 Memory organization 5 M95320, M95640, M95320-x, M95640-x Memory organization The memory is organized as shown in Figure 6. Figure 6. Block diagram HOLD W High Voltage Generator Control Logic S C D I/O Shift Register Q Address Register and Counter Data Register Size of the Read only EEPROM area Y Decoder Status Register 1 Page X Decoder AI01272C 14/44 M95320, M95640, M95320-x, M95640-x 6 Instructions Instructions Each instruction starts with a single-byte code, as summarized in Table 3. If an invalid instruction is sent (one not contained in <Blue>Table 3.), the device automatically deselects itself. Table 3. Instruction set Instruction 6.1 Description Instruction Format WREN Write Enable 0000 0110 WRDI Write Disable 0000 0100 RDSR Read Status Register 0000 0101 WRSR Write Status Register 0000 0001 READ Read from Memory Array 0000 0011 WRITE Write to Memory Array 0000 0010 Write Enable (WREN) The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction. The only way to do this is to send a Write Enable instruction to the device. As shown in Figure 7, to send this instruction to the device, Chip Select (S) is driven Low, and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then enters a wait state. It waits for a the device to be deselected, by Chip Select (S) being driven High. Figure 7. Write Enable (WREN) sequence S 0 1 2 3 4 5 6 7 C Instruction D High Impedance Q AI02281E 15/44 Instructions 6.2 M95320, M95640, M95320-x, M95640-x Write Disable (WRDI) One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction to the device. As shown in Figure 8, to send this instruction to the device, Chip Select (S) is driven Low, and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then enters a wait state. It waits for a the device to be deselected, by Chip Select (S) being driven High. The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events: Power-up WRDI instruction execution WRSR instruction completion WRITE instruction completion. Figure 8. Write Disable (WRDI) sequence S 0 1 2 3 4 5 6 7 C Instruction D High Impedance Q AI03750D 16/44 M95320, M95640, M95320-x, M95640-x 6.3 Instructions Read Status Register (RDSR) The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status Register may be read at any time, even while a Write or Write Status Register cycle is in progress. When one of these cycles is in progress, it is recommended to check the Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible to read the Status Register continuously, as shown in Figure 9. The Status Register format is shown in Table 4 and the status and control bits of the Status Register are as follows: 6.3.1 WIP bit The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write Status Register cycle. When set to 1, such a cycle is in progress, when reset to 0 no such cycle is in progress. 6.3.2 WEL bit The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write or Write Status Register instruction is accepted. 6.3.3 BP1, BP0 bits The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against Write instructions. These bits are written with the Write Status Register (WRSR) instruction. When one or both of the Block Protect (BP1, BP0) bits is set to 1, the relevant memory area (as defined in Table 4) becomes protected against Write (WRITE) instructions. The Block Protect (BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set. 6.3.4 SRWD bit The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W) signal allow the device to be put in the Hardware Protected mode (when the Status Register Write Disable (SRWD) bit is set to 1, and Write Protect (W) is driven Low). In this mode, the non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for execution. Table 4. Status Register format b7 SRWD b0 0 0 0 BP1 BP0 WEL WIP Status Register Write Protect Block Protect Bits Write Enable Latch Bit Write In Progress Bit 17/44 Instructions M95320, M95640, M95320-x, M95640-x Figure 9. Read Status Register (RDSR) sequence S 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 C Instruction D Status Register Out Status Register Out High Impedance Q 7 6 5 4 3 MSB 2 1 0 7 6 5 4 3 2 1 0 7 MSB AI02031E 6.4 Write Status Register (WRSR) The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded and executed, the device sets the Write Enable Latch (WEL). The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) Low, followed by the instruction code and the data byte on Serial Data Input (D). The instruction sequence is shown in Figure 10. The Write Status Register (WRSR) instruction has no effect on b6, b5, b4, b1 and b0 of the Status Register. b6, b5 and b4 are always read as 0. Chip Select (S) must be driven High after the rising edge of Serial Clock (C) that latches in the eighth bit of the data byte, and before the next rising edge of Serial Clock (C). Otherwise, the Write Status Register (WRSR) instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed Write Status Register cycle (whose duration is tW) is initiated. While the Write Status Register cycle is in progress, the Status Register may still be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed. When the cycle is completed, the Write Enable Latch (WEL) is reset. The Write Status Register (WRSR) instruction allows the user to change the values of the Block Protect (BP1, BP0) bits, to define the size of the area that is to be treated as readonly, as defined in Table 4. The Write Status Register (WRSR) instruction also allows the user to set or reset the Status Register Write Disable (SRWD) bit in accordance with the Write Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W) signal allow the device to be put in the Hardware Protected Mode (HPM). The Write Status Register (WRSR) instruction is not executed once the Hardware Protected Mode (HPM) is entered. The contents of the Status Register Write Disable (SRWD) and Block Protect (BP1, BP0) bits are frozen at their current values from just before the start of the execution of Write Status Register (WRSR) instruction. The new, updated, values take effect at the moment of completion of the execution of Write Status Register (WRSR) instruction. 18/44 M95320, M95640, M95320-x, M95640-x Table 5. Instructions Protection modes Memory Content W SRWD Signal Bit 1 0 0 0 1 1 0 1 Mode Write Protection of the Status Register Protected Area(1) Unprotected Area(1) Status Register is Writable Software (if the WREN instruction Protected has set the WEL bit) Write Protected (SPM) The values in the BP1 and BP0 bits can be changed Ready to accept Write instructions Status Register is Hardware Hardware write protected Protected The values in the BP1 and Write Protected (HPM) BP0 bits cannot be changed Ready to accept Write instructions 1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 2. The protection features of the device are summarized in Table 2. When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial delivery state), it is possible to write to the Status Register provided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless of the whether Write Protect (W) is driven High or Low. When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two cases need to be considered, depending on the state of Write Protect (W): If Write Protect (W) is driven High, it is possible to write to the Status Register provided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction. If Write Protect (W) is driven Low, it is not possible to write to the Status Register even if the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction. (Attempts to write to the Status Register are rejected, and are not accepted for execution). As a consequence, all the data bytes in the memory area that are software protected (SPM) by the Block Protect (BP1, BP0) bits of the Status Register, are also hardware protected against data modification. Regardless of the order of the two events, the Hardware Protected Mode (HPM) can be entered: by setting the Status Register Write Disable (SRWD) bit after driving Write Protect (W) Low or by driving Write Protect (W) Low after setting the Status Register Write Disable (SRWD) bit. The only way to exit the Hardware Protected Mode (HPM) once entered is to pull Write Protect (W) High. If Write Protect (W) is permanently tied High, the Hardware Protected Mode (HPM) can never be activated, and only the Software Protected Mode (SPM), using the Block Protect (BP1, BP0) bits of the Status Register, can be used. 19/44 Instructions M95320, M95640, M95320-x, M95640-x Address range bits(1) Table 6. Device 32 Kbit Devices 64 Kbit Devices Address Bits A12-A0 A11-A0 1. b15 to b13 are Don't Care on the 64 Kbit devices. b15 to b12 are Don't Care on the 32 Kbit devices. Figure 10. Write Status Register (WRSR) sequence S 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 C Instruction Status Register In 7 D High Impedance 6 5 4 3 2 1 0 MSB Q AI02282D 20/44 M95320, M95640, M95320-x, M95640-x 6.5 Instructions Read from Memory Array (READ) As shown in Figure 11, to send this instruction to the device, Chip Select (S) is first driven Low. The bits of the instruction byte and address bytes are then shifted in, on Serial Data Input (D). The address is loaded into an internal address register, and the byte of data at that address is shifted out, on Serial Data Output (Q). If Chip Select (S) continues to be driven Low, the internal address register is automatically incremented, and the byte of data at the new address is shifted out. When the highest address is reached, the address counter rolls over to zero, allowing the Read cycle to be continued indefinitely. The whole memory can, therefore, be read with a single READ instruction. The Read cycle is terminated by driving Chip Select (S) High. The rising edge of the Chip Select (S) signal can occur at any time during the cycle. The first byte addressed can be any byte within any page. The instruction is not accepted, and is not executed, if a Write cycle is currently in progress. Figure 11. Read from Memory Array (READ) sequence S 0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31 C Instruction 16-Bit Address 15 14 13 D 3 2 1 0 MSB Data Out 1 High Impedance Q 7 6 5 4 3 2 Data Out 2 1 0 7 MSB AI01793D 1. Depending on the memory size, as shown in Table 6, the most significant address bits are Don't Care. 21/44 Instructions 6.6 M95320, M95640, M95320-x, M95640-x Write to Memory Array (WRITE) As shown in Figure 12, to send this instruction to the device, Chip Select (S) is first driven Low. The bits of the instruction byte, address byte, and at least one data byte are then shifted in, on Serial Data Input (D). The instruction is terminated by driving Chip Select (S) High at a byte boundary of the input data. In the case of Figure 12, this occurs after the eighth bit of the data byte has been latched in, indicating that the instruction is being used to write a single byte. The self-timed Write cycle starts, and continues for a period tWC (as specified in Table 18 to Table 22), at the end of which the Write in Progress (WIP) bit is reset to 0. If, though, Chip Select (S) continues to be driven Low, as shown in Figure 13, the next byte of input data is shifted in, so that more than a single byte, starting from the given address towards the end of the same page, can be written in a single internal Write cycle. Each time a new data byte is shifted in, the least significant bits of the internal address counter are incremented. If the number of data bytes sent to the device exceeds the page boundary, the internal address counter rolls over to the beginning of the page, and the previous data there are overwritten with the incoming data. (The page size of these devices is 32 bytes). The instruction is not accepted, and is not executed, under the following conditions: if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable instruction just before) if a Write cycle is already in progress if the device has not been deselected, by Chip Select (S) being driven High, at a byte boundary (after the eighth bit, b0, of the last data byte that has been latched in) if the addressed page is in the region protected by the Block Protect (BP1 and BP0) bits. Figure 12. Byte Write (WRITE) sequence S 0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31 C Instruction 16-Bit Address 15 14 13 D 3 2 Data Byte 1 0 7 6 5 4 3 2 1 0 High Impedance Q AI01795D 1. Depending on the memory size, as shown in Table 6, the most significant address bits are Don't Care. 22/44 M95320, M95640, M95320-x, M95640-x Instructions Figure 13. Page Write (WRITE) sequence S 0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31 C Instruction 16-Bit Address 15 14 13 D 3 2 Data Byte 1 1 0 7 6 5 4 3 2 0 1 S 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 C Data Byte 2 D 7 6 5 4 3 2 Data Byte 3 1 0 7 6 5 4 3 2 Data Byte N 1 0 6 5 4 3 2 1 0 AI01796D 1. Depending on the memory size, as shown in Table 6, the most significant address bits are Don't Care. 23/44 Power-up and delivery state 7 Power-up and delivery state 7.1 Power-up state M95320, M95640, M95320-x, M95640-x After Power-up, the device is in the following state: Standby Power mode deselected (after Power-up, a falling edge is required on Chip Select (S) before any instructions can be started). not in the Hold Condition the Write Enable Latch (WEL) is reset to 0 Write In Progress (WIP) is reset to 0 The SRWD, BP1 and BP0 bits of the Status Register are unchanged from the previous power-down (they are non-volatile bits). 7.2 Initial delivery state The device is delivered with the memory array set at all 1s (FFh). The Status Register Write Disable (SRWD) and Block Protect (BP1 and BP0) bits are initialized to 0. 24/44 M95320, M95640, M95320-x, M95640-x 8 Maximum rating Maximum rating Stressing the device outside the ratings listed in Table 7 may cause permanent damage to the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the Operating sections of this specification, is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 7. Absolute maximum ratings Symbol TSTG TA TLEAD Parameter Min. Max. Unit Storage Temperature -65 150 C Ambient operating temperature -40 130 C Lead Temperature during Soldering See note (1) C VO Output Voltage -0.50 VCC+0.6 V VI Input Voltage -0.50 6.5 V VCC Supply Voltage -0.50 6.5 V VESD Electrostatic Discharge Voltage (Human Body model)(2) -4000 4000 V 1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the ST ECOPACK(R) 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU 2. AEC-Q100-002 (compliant with JEDEC Std JESD22-A114A, C1=100pF, R1=1500, R2=500) 25/44 DC and AC parameters 9 M95320, M95640, M95320-x, M95640-x DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC Characteristic tables that follow are derived from tests performed under the Measurement Conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. Table 8. Operating conditions (M95320 and M95640) Symbol VCC TA Table 9. Parameter Min. Max. Unit Supply Voltage 4.5 5.5 V Ambient Operating Temperature (Device Grade 6) -40 85 C Ambient Operating Temperature (Device Grade 3) -40 125 C Operating conditions (M95320-W and M95640-W) Symbol VCC TA Table 10. Parameter Min. Max. Unit Supply Voltage 2.5 5.5 V Ambient Operating Temperature (Device Grade 6) -40 85 C Ambient Operating Temperature (Device Grade 3) -40 125 C Min.(1) Max. (1) Unit Supply Voltage 1.8 5.5 V Ambient Operating Temperature -40 85 C Operating conditions (M95320-R and M95640-R) Symbol VCC TA Parameter 1. This product is under development. For more information, please contact your nearest ST sales office. Table 11. AC measurement conditions(1) Symbol CL Parameter Min. Typ. Load Capacitance 30 Input Rise and Fall Times Unit pF 50 ns Input Pulse Voltages 0.2VCC to 0.8VCC V Input and Output Timing Reference Voltages 0.3VCC to 0.7VCC V 1. Output Hi-Z is defined as the point where data out is no longer driven. Figure 14. AC measurement I/O waveform Input Levels 0.8VCC 0.2VCC Input and Output Timing Reference Levels 0.7VCC 0.3VCC AI00825B 26/44 Max. M95320, M95640, M95320-x, M95640-x Table 12. Symbol COUT CIN DC and AC parameters Capacitance(1) Parameter Test Condition Max. Unit VOUT = 0V 8 pF Input Capacitance (D) VIN = 0V 8 pF Input Capacitance (other pins) VIN = 0V 6 pF Output Capacitance (Q) Min. 1. Sampled only, not 100% tested, at TA=25C and a frequency of 5MHz. Table 13. DC characteristics (M95320 and M95640, device grade 6) Symbol Parameter Test Condition ILI Input Leakage Current ILO Min. Max. Unit VIN = VSS or VCC 2 A Output Leakage Current S = VCC, VOUT = VSS or VCC 2 A ICC Supply Current C = 0.1VCC/0.9VCC at 10MHz, VCC = 5V, Q = open 5 mA ICC1 Supply Current (Standby) S = VCC, VCC = 5V, VIN = VSS or VCC 2 A VIL Input Low Voltage -0.45 0.3VCC V VIH Input High Voltage 0.7VCC VCC+1 V VOL(1) Output Low Voltage IOL = 2 mA, VCC = 5V 0.4 V VOH(1) Output High Voltage IOH = -2 mA, VCC = 5V 0.8VCC V 1. For all 5V range devices, the device meets the output requirements for both TTL and CMOS standards. Table 14. Symbol DC characteristics (M95320 and M95640, device grade 3) Parameter Test Condition Min. Max. Unit VIN = VSS or VCC 2 A ILI Input Leakage Current ILO Output Leakage Current S = VCC, VOUT = VSS or VCC 2 A ICC Supply Current C = 0.1VCC/0.9VCC at 5MHz, VCC = 5V, Q = open 4 mA ICC1 Supply Current (Standby) S = VCC, VCC = 5V, VIN = VSS or VCC 5 A VIL Input Low Voltage -0.45 0.3 VCC V VIH Input High Voltage 0.7 VCC VCC+1 V VOL(1) Output Low Voltage IOL = 2mA, VCC = 5V 0.4 V VOH(1) Output High Voltage IOH = -2mA, VCC = 5V 0.8 VCC V 1. For all 5V range devices, the device meets the output requirements for both TTL and CMOS standards. 27/44 DC and AC parameters Table 15. Symbol DC characteristics (M95320-W and M95640-W, device grade 6) Parameter Test Condition Min. Max. Unit VIN = VSS or VCC 2 A ILI Input Leakage Current ILO Output Leakage Current S = VCC, VOUT = VSS or VCC 2 A ICC Supply Current C = 0.1VCC/0.9VCC at 5MHz, VCC = 2.5V, Q = open 3 mA ICC1 Supply Current (Standby) S = VCC, VCC = 2.5V VIN = VSS or VCC 1 A VIL Input Low Voltage -0.45 0.3VCC V VIH Input High Voltage 0.7VCC VCC+1 V VOL Output Low Voltage IOL = 1.5mA, VCC = 2.5V or IOL = 2mA, VCC = 5.5V 0.4 V VOH Output High Voltage IOH = -0.4mA, VCC = 2.5V or IOH = -2mA, VCC = 5.5V Table 16. Symbol 28/44 M95320, M95640, M95320-x, M95640-x 0.8VCC V DC characteristics (M95320-W and M95640-W, device grade 3) Parameter Test Condition Min. Max. Unit VIN = VSS or VCC 2 A ILI Input Leakage Current ILO Output Leakage Current S = VCC, VOUT = VSS or VCC 2 A ICC Supply Current C = 0.1VCC/0.9VCC at 5MHz, VCC = 2.5V, Q = open 3 mA ICC1 Supply Current (Standby) S = VCC, VCC = 2.5V, VIN = VSS or VCC 2 A VIL Input Low Voltage 0.3VCC V VIH Input High Voltage 0.7VCC VCC+1 V VOL Output Low Voltage IOL = 1.5mA, VCC = 2.5V VOH Output High Voltage IOH = -0.4mA, VCC = 2.5V -0.45 0.4 0.8VCC V V M95320, M95640, M95320-x, M95640-x Table 17. Symbol DC and AC parameters DC characteristics (M95320-R and M95640-R) Parameter Max.(1) Unit VIN = VSS or VCC 1 A S = VCC, VOUT = VSS or VCC 1 A C = 0.1VCC/0.9VCC at max clock frequency, 1.8V < VCC = 2.5V, Q = open 3 mA S = VCC, VIN = VSS or VCC, 1.8V < VCC = 2.5V 1 A 0.3 VCC V 0.7 VCC VCC+1 V Test Condition ILI Input Leakage Current ILO Output Leakage Current ICC Supply Current ICC1 Supply Current (Standby) VIL Input Low Voltage VIH Input High Voltage VOL Output Low Voltage IOL = 0.15 mA, VCC = 1.8 V VOH Output High Voltage IOH = -0.1 mA, VCC = 1.8 V Min.(1) -0.45 0.3 0.8 VCC V V 1. This product is under qualification. For more information, please contact your nearest ST sales office. 29/44 DC and AC parameters Table 18. M95320, M95640, M95320-x, M95640-x AC characteristics (M95320 and M95640, device grade 6) Test conditions specified in Table 11 and Table 8 Symbol Alt. fC fSCK Clock Frequency tSLCH tCSS1 S Active Setup Time 15 ns tSHCH tCSS2 S Not Active Setup Time 15 ns tSHSL tCS S Deselect Time 40 ns tCHSH tCSH S Active Hold Time 25 ns S Not Active Hold Time 15 ns tCHSL Parameter Max. Unit D.C. 10 MHz tCH(1) tCLH Clock High Time 40 ns tCL(1) tCLL Clock Low Time 40 ns tCLCH(2) tRC Clock Rise Time 1 s (2) tFC Clock Fall Time 1 s tCHCL tDVCH tDSU Data In Setup Time 15 ns tCHDX tDH Data In Hold Time 15 ns tHHCH Clock Low Hold Time after HOLD not Active 15 ns tHLCH Clock Low Hold Time after HOLD Active 20 ns tCLHL Clock Low Set-up Time before HOLD Active 0 ns tCLHH Clock Low Set-up Time before HOLD not Active 0 ns tSHQZ(2) tDIS tCLQV tV tCLQX tHO Output Hold Time tQLQH(2) tRO Output Rise Time 20 ns tQHQL(2) tFO Output Fall Time 20 ns tHHQV tLZ HOLD High to Output Valid 25 ns tHLQZ(2) tHZ HOLD Low to Output High-Z 25 ns tW tWC Write Time 5 ms Output Disable Time 25 ns Clock Low to Output Valid 25 ns 1. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max). 2. Value guaranteed by characterization, not 100% tested in production. 30/44 Min. 0 ns M95320, M95640, M95320-x, M95640-x Table 19. DC and AC parameters AC characteristics (M95320 and M95640, device grade 3) Test conditions specified in Table 11 and Table 8 Symbol Alt. fC fSCK Clock Frequency tSLCH tCSS1 S Active Setup Time 90 ns tSHCH tCSS2 S Not Active Setup Time 90 ns tSHSL tCS S Deselect Time 100 ns tCHSH tCSH S Active Hold Time 90 ns S Not Active Hold Time 90 ns tCHSL Parameter Min. Max. Unit D.C. 5 MHz tCH(1) tCLH Clock High Time 90 ns tCL(1) 90 ns tCLL Clock Low Time tCLCH (2) tRC Clock Rise Time 1 s tCHCL (2) tFC Clock Fall Time 1 s tDVCH tDSU Data In Setup Time 20 ns tCHDX tDH Data In Hold Time 30 ns tHHCH Clock Low Hold Time after HOLD not Active 70 ns tHLCH Clock Low Hold Time after HOLD Active 40 ns tCLHL Clock Low Set-up Time before HOLD Active 0 ns tCLHH Clock Low Set-up Time before HOLD not Active 0 ns tSHQZ(2) tDIS tCLQV tV tCLQX tHO Output Hold Time tQLQH(2) tRO Output Rise Time 50 ns tQHQL(2) tFO Output Fall Time 50 ns tHHQV tLZ HOLD High to Output Valid 50 ns tHLQZ(2) tHZ HOLD Low to Output High-Z 100 ns tW tWC Write Time 5 ms Output Disable Time 100 ns Clock Low to Output Valid 60 ns 0 ns 1. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max). 2. Value guaranteed by characterization, not 100% tested in production. 31/44 DC and AC parameters Table 20. M95320, M95640, M95320-x, M95640-x AC characteristics (M95320-W and M95640-W, device grade 6) Test conditions specified in Table 11 and Table 9 Symbol Alt. fSCK fC Parameter Clock Frequency Current Product Version(1) New Product Version(2) Min. Max. Min. Max. D.C. D.C. 10 5 Unit MHz tSLCH tCSS1 S Active Setup Time 90 30 ns tSHCH tCSS2 S Not Active Setup Time 90 30 ns tSHSL tCS S Deselect Time 100 40 ns tCHSH tCSH S Active Hold Time 90 30 ns S Not Active Hold Time 90 30 ns tCHSL tCH(3) tCLH Clock High Time 90 42 ns tCL(3) tCLL Clock Low Time 90 40 ns tCLCH(4) tRC Clock Rise Time 1 2 s (4) tFC Clock Fall Time 1 2 s tCHCL tDVCH tDSU Data In Setup Time 20 10 ns tCHDX tDH Data In Hold Time 30 10 ns tHHCH Clock Low Hold Time after HOLD not Active 70 30 ns tHLCH Clock Low Hold Time after HOLD Active 40 30 ns tCLHL Clock Low Set-up Time before HOLD Active 0 0 ns tCLHH Clock Low Set-up Time before HOLD not Active 0 0 ns tSHQZ(4) tDIS tCLQV tV tCLQX Output Disable Time 100 40 ns Clock Low to Output Valid 60 40 ns tHO Output Hold Time tQLQH (4) 0 0 ns tRO Output Rise Time 50 40 ns tQHQL (4) tFO Output Fall Time 50 40 ns tHHQV tLZ HOLD High to Output Valid 50 40 ns tHLQZ(4) tHZ HOLD Low to Output High-Z 100 40 ns tW tWC Write Time 5 5 ms 1. Current product version is identified by Process Identification letter `V''. 2. New product version is identified by Process Identification letter `P'. Please contact your nearest ST sales office for details (PCN MPG-NVM/05/1315 and PCN MPG-NVM/05/1191) 3. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max). 4. Value guaranteed by characterization, not 100% tested in production. 32/44 M95320, M95640, M95320-x, M95640-x Table 21. DC and AC parameters AC characteristics (M95320-W and M95640-W, device grade 3) Test conditions specified in Table 11 and Table 9 Symbol Alt. fC fSCK Clock Frequency tSLCH tCSS1 S Active Setup Time 90 ns tSHCH tCSS2 S Not Active Setup Time 90 ns tSHSL tCS S Deselect Time 100 ns tCHSH tCSH S Active Hold Time 90 ns S Not Active Hold Time 90 ns tCHSL Parameter Min. Max. Unit D.C. 5 MHz tCH(1) tCLH Clock High Time 90 ns tCL(1) 90 ns tCLL Clock Low Time tCLCH (2) tRC Clock Rise Time 1 s tCHCL (2) tFC Clock Fall Time 1 s tDVCH tDSU Data In Setup Time 20 ns tCHDX tDH Data In Hold Time 30 ns tHHCH Clock Low Hold Time after HOLD not Active 70 ns tHLCH Clock Low Hold Time after HOLD Active 40 ns tCLHL Clock Low Set-up Time before HOLD Active 0 ns tCLHH Clock Low Set-up Time before HOLD not Active 0 ns tSHQZ (2) tDIS tCLQV tV tCLQX Output Disable Time 100 ns Clock Low to Output Valid 60 ns tHO Output Hold Time tQLQH (2) 0 ns tRO Output Rise Time 50 ns tQHQL (2) tFO Output Fall Time 50 ns tHHQV tLZ HOLD High to Output Valid 50 ns tHLQZ(2) tHZ HOLD Low to Output High-Z 100 ns tW tWC Write Time 5 ms 1. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max). 2. Value guaranteed by characterization, not 100% tested in production. 33/44 DC and AC parameters Table 22. M95320, M95640, M95320-x, M95640-x AC characteristics (M95320-R) Test conditions specified in Table 11 and Table 10 Symbol Alt. fC fSCK Clock Frequency tSLCH tCSS1 S Active Setup Time 60 ns tSHCH tCSS2 S Not Active Setup Time 60 ns tSHSL tCS S Deselect Time 90 ns tCHSH tCSH S Active Hold Time 60 ns S Not Active Hold Time 60 ns tCHSL Parameter Min. Max. Unit D.C. 5 MHz tCH(1) tCLH Clock High Time 90 ns tCL(1) 90 ns tCLL Clock Low Time tCLCH (2) tRC Clock Rise Time 2 s tCHCL (2) tFC Clock Fall Time 2 s tDVCH tDSU Data In Setup Time 20 ns tCHDX tDH Data In Hold Time 20 ns tHHCH Clock Low Hold Time after HOLD not Active 60 ns tHLCH Clock Low Hold Time after HOLD Active 60 ns tCLHL Clock Low Set-up Time before HOLD Active 0 0 tCLHH Clock Low Set-up Time before HOLD not Active 0 0 tSHQZ(2) tDIS tCLQV tV tCLQX tHO Output Hold Time tQLQH(2) tRO Output Rise Time 80 ns tQHQL(2) tFO Output Fall Time 80 ns tHHQV tLZ HOLD High to Output Valid 80 ns tHLQZ(2) tHZ HOLD Low to Output High-Z 80 ns tW tWC Write Time 10 ms Output Disable Time 80 ns Clock Low to Output Valid 80 ns 0 1. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max). 2. Value guaranteed by characterization, not 100% tested in production. 34/44 ns M95320, M95640, M95320-x, M95640-x Table 23. DC and AC parameters AC characteristics (M95640-R) Test conditions specified in Table 11 and Table 9 Symbol Alt. fC fSCK tSLCH Min. Max. Unit Clock Frequency D.C. 2 MHz tCSS1 S Active Setup Time 150 ns tSHCH tCSS2 S Not Active Setup Time 150 ns tSHSL tCS S Deselect Time 200 ns tCHSH tCSH S Active Hold Time 150 ns S Not Active Hold Time 150 ns tCHSL Parameter tCH(1) tCLH Clock High Time 200 ns tCL(3) tCLL Clock Low Time 200 ns tCLCH(2) tRC Clock Rise Time 2 s (4) tFC Clock Fall Time 2 s tCHCL tDVCH tDSU Data In Setup Time 50 ns tCHDX tDH Data In Hold Time 50 ns tHHCH Clock Low Hold Time after HOLD not Active 150 ns tHLCH Clock Low Hold Time after HOLD Active 150 ns tCLHL Clock Low Set-up Time before HOLD Active 0 0 tCLHH Clock Low Set-up Time before HOLD not Active 0 0 tSHQZ(4) tDIS tCLQV tV tCLQX Output Disable Time 200 ns Clock Low to Output Valid 200 ns tHO Output Hold Time (4) tRO Output Rise Time 200 ns tQHQL(4) tFO Output Fall Time 200 ns tHHQV tLZ HOLD High to Output Valid 200 ns tHLQZ(4) tHZ HOLD Low to Output High-Z 200 ns tW tWC Write Time 10 ms tQLQH 0 ns 1. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max). 2. Value guaranteed by characterization, not 100% tested in production. 35/44 DC and AC parameters M95320, M95640, M95320-x, M95640-x Figure 15. Serial Input timing tSHSL S tCHSL tSLCH tCHSH tSHCH C tDVCH tCHCL tCHDX LSB IN MSB IN D Q tCLCH High Impedance AI01447C Figure 16. Hold timing S tHLCH tCLHL tHHCH C tCLHH tHLQZ tHHQV Q D HOLD AI01448B 36/44 M95320, M95640, M95320-x, M95640-x DC and AC parameters Figure 17. Output timing S tCH C tCLQV tCLQX tCLQV tCL tSHQZ tCLQX LSB OUT Q tQLQH tQHQL D ADDR. LSB IN AI01449e 37/44 Package mechanical 10 M95320, M95640, M95320-x, M95640-x Package mechanical Figure 18. SO8N - 8 lead Plastic Small Outline, 150 mils body width, package outline h x 45 A2 A c ccc b e 0.25 mm GAUGE PLANE D k 8 E1 E 1 L A1 L1 SO-A 1. Drawing is not to scale. Table 24. SO8N - 8 lead Plastic Small Outline, 150 mils body width, package mechanical data millimeters inches Symbol Typ Min A Typ Min 1.75 Max 0.069 A1 0.10 A2 1.25 b 0.28 0.48 0.011 0.019 c 0.17 0.23 0.007 0.009 ccc 0.25 0.004 0.010 0.049 0.10 0.004 D 4.90 4.80 5.00 0.193 0.189 0.197 E 6.00 5.80 6.20 0.236 0.228 0.244 E1 3.90 3.80 4.00 0.154 0.150 0.157 e 1.27 - - 0.050 - - h 0.25 0.50 0.010 0.020 k 0 8 0 8 L 0.40 1.27 0.016 0.050 L1 38/44 Max 1.04 0.041 M95320, M95640, M95320-x, M95640-x Package mechanical Figure 19. TSSOP8 - 8 lead Thin Shrink Small Outline, package outline D 8 5 c E1 1 E 4 A1 A L A2 L1 CP b e TSSOP8AM 1. Drawing is not to scale. Table 25. TSSOP8 - 8 lead Thin Shrink Small Outline, package mechanical data millimeters inches Symbol Typ. Min. A Max. Min. 1.200 A1 0.050 0.150 0.800 1.050 b 0.190 c 0.090 A2 Typ. 1.000 CP Max. 0.0472 0.0020 0.0059 0.0315 0.0413 0.300 0.0075 0.0118 0.200 0.0035 0.0079 0.0394 0.100 0.0039 D 3.000 2.900 3.100 0.1181 0.1142 0.1220 e 0.650 - - 0.0256 - - E 6.400 6.200 6.600 0.2520 0.2441 0.2598 E1 4.400 4.300 4.500 0.1732 0.1693 0.1772 L 0.600 0.450 0.750 0.0236 0.0177 0.0295 L1 1.000 0 8 0.0394 0 8 39/44 Package mechanical M95320, M95640, M95320-x, M95640-x Figure 20. MLP8 - 8-lead Ultra thin Fine pitch Dual Flat No Lead, package outline e D b L1 L3 E E2 L A D2 ddd A1 UFDFPN-01 1. Drawing is not to scale. Table 26. MLP8 - 8-lead Ultra thin Fine pitch Dual Flat No Lead, package mechanical data millimeters inches Symbol A Typ Min Max Typ Min Max 0.55 0.50 0.60 0.022 0.020 0.024 0.00 0.05 0.000 0.002 0.20 0.30 0.008 0.012 0.061 0.065 A1 b 0.25 D 2.00 D2 0.079 1.55 ddd E 1.65 0.05 3.00 E2 0.002 0.118 0.15 0.25 0.006 0.010 e 0.50 - - 0.020 - - L 0.45 0.40 0.50 0.018 0.016 0.020 L1 40/44 0.010 0.15 0.006 L3 0.30 0.012 N 8 8 M95320, M95640, M95320-x, M95640-x 11 Part numbering Part numbering Table 27. Ordering information scheme Example: M95640 - W MN 6 T P /B Device Type M95 = SPI serial access EEPROM Device Function 640 = 64 Kbit (8192 x 8) 320 = 32 Kbit (4096 x 8) Operating Voltage blank = VCC = 4.5 to 5.5V W = VCC = 2.5 to 5.5V R = VCC = 1.8 to 5.5V Package MN = SO8 (150 mil width) DW = TSSOP8 (169 mil width) MB = MLP8 (2x3 mm) Device Grade 6 = Industrial temperature range, -40 to 85 C. Device tested with standard test flow 3 = Device tested with High Reliability Certified Flow(1)Automotive temperature range (-40 to 125 C) Option blank = Standard Packing T = Tape and Reel Packing Plating Technology blank = Standard SnPb plating P or G = ECOPACK (RoHS compliant) Process letter(2) /B = DP26% Rsst /P = DP26% Chartered 1. ST strongly recommends the use of the Automotive Grade devices for use in an automotive environment. The High Reliability Certified Flow (HRCF) is described in the quality note QNEE9801. Please ask your nearest ST sales office for a copy. 2. The Process letter only concerns Grade-3 devices. For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST Sales Office. The category of second-Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. 41/44 Revision history 12 Revision history Table 28. 42/44 M95320, M95640, M95320-x, M95640-x Document revision history Date Revision Changes 13-Jul-2000 1.2 Human Body Model meets JEDEC std (Table 2). Minor adjustments on pp 1,11,15. New clause on p7. Addition of TSSOP8 package on pp 1, 2, Ordering Info, Mechanical Data 16-Mar-2001 1.3 Test condition added ILI and ILO, and specification of tDLDH and tDHDL removed. tCLCH, tCHCL, tDLDH and tDHDL changed to 50ns for the -V range. "-V" Voltage range changed to "2.7V to 3.6V" throughout. Maximum lead soldering time and temperature conditions updated. Instruction sequence illustrations updated. "Bus Master and Memory Devices on the SPI bus" illustration updated. Package Mechanical data updated 19-Jul-2001 1.4 M95160 and M95080 devices removed to their own data sheet 06-Dec-2001 1.5 Endurance increased to 1M write/erase cycles Instruction sequence illustrations updated 18-Dec-2001 2.0 Document reformatted using the new template. No parameters changed. 08-Feb-2002 2.1 Announcement made of planned upgrade to 10MHz clock for the 5V, -40 to 85C, range. Endurance set to 100K write/erase cycles 18-Dec-2002 2.2 10MHz, 5MHz, 2MHz clock; 5ms, 10ms Write Time; 100K, 1M erase/write cycles distinguished on front page, and in the DC and AC Characteristics tables 26-Mar-2003 2.3 Process indentification letter corrected in footnote to AC Characteristics table for temp. range 3 26-Jun-2003 2.4 -S voltage range upgraded by removing it and inserting -R voltage range in its place 15-Oct-2003 3.0 Table of contents, and Pb-free options added. VIL(min) improved to -0.45V 21-Nov-2003 3.1 VI(min) and VO(min) corrected (improved) to -0.45V 28-Jan-2004 4.0 TSSOP8 connections added to DIP and SO connections M95320, M95640, M95320-x, M95640-x Table 28. Date 24-May-2005 07-Jul-2006 Revision history Document revision history (continued) Revision Changes 5.0 M95320-S and M95640-S root part numbers (1.65 to 5.5V Supply) and related characteristics added. 20MHz Clock rate added.TSSOP14 package removed and MLP8 package added. Description of Power On Reset: VCC Lock-Out Write Protect updated. Product List summary table added. Absolute Maximum Ratings for VIO(min) and VCC(min) improved. Soldering temperature information clarified for RoHS compliant devices. Device Grade 3 clarified, with reference to HRCF and automotive environments. AEC-Q100-002 compliance. tCHHL(min) and tCHHH(min) is tCH for products under "S" process. tHHQX corrected to tHHQV. Figure 16: Hold timing updated. 6 Document converted to new ST template. Packages are ECOPACK(R) compliant. PDIP package removed. SO8N package specifications updated (see Table 24 and Figure 18). M95640-S and M95320-S part numbers removed (DC and AC parameters updated accordingly). How to identify previous, current and new products by the Process identification letter Table removed. Figure 4: SPI modes supported updated and Note 2 added. First three paragraphs of Section 4: Operating features replaced by Section 4.1: Supply voltage (VCC). TA added to Table 7: Absolute maximum ratings. ICC and ICC1 updated in Table 13, Table 14, Table 15 and Table 17. VOL and VOH updated in Table 15. ICC updated in Table 16. Data in Table 17 is no longer preliminary. tCH updated in Table 20. Table 23: AC characteristics (M95640-R) added. Timing line of tSHQZ modified in Figure 17: Output timing. Process letter added to Table 27: Ordering information scheme, Note 2 removed. Note 2 removed from Figure 2. 43/44 M95320, M95640, M95320-x, M95640-x Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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