July 2006 Rev 6 1/44
1
M95320 M95320-W M95320-R
M95640 M95640-W M95640-R
32 Kbit and 64 Kbit Serial SPI bus EEPROMs
with high speed clock
Feature summary
■Compatible with SPI Bus Serial Interface
(Positive Clock SPI Modes)
■Single Supply Voltage:
– 4.5 to 5.5V for M95320 and M95640
– 2.5 to 5.5V for M95320-W and M95320-W
– 1.8 to 5.5V for M95320-R and M95640-R
■10MHz, 5MHz or 2MHz clock rates
■5ms or 10ms Write Time
■Status Register
■Hardware Protection of the Status Register
■Byte and Page Write (up to 32 Bytes)
■Self-Timed Programming Cycle
■Adjustable Size Read-Only EEPROM Area
■Enhanced ESD Protection
■More than 1 million Write cycles
■More than 40-Year Data Retention
■Packages
– ECOPACK® (RoHS compliant)
SO8 (MN)
150 mil width
TSSOP8 (DW)
169 mil width
MLP8 (MB)
2x3 mm
www.st.com
Contents M95320, M95640, M95320-x, M95640-x
2/44
Contents
1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.0.1 Serial Data Output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.0.2 Serial Data Input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.0.3 Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.0.4 Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.0.5 Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.0.6 Write Protect (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 Connecting to the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1 SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4 Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1 Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1.1 Operating supply voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
4.1.2 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1.3 Internal device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1.4 Po wer-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2 Active Power and Standby Power modes . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2.1 Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.4 Data protection and protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.1 Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.2 Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.3 Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.3.1 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.3.2 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.3.3 BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.3.4 SR WD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
M95320, M95640, M95320-x, M95640-x Contents
3/44
6.4 Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.5 Read from Memory Array (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.6 Write to Memory Array (WRITE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7 Power-up and delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.1 Power-up state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.2 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
8 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
9 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
10 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
11 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
List of tables M95320, M95640, M95320-x, M95640-x
4/44
List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2. Write-Protected block size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 3. Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 4. Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 5. Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 6. Address range bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 7. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 8. Operating conditions (M95320 and M95640) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 9. Operating conditions (M95320-W and M95640-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 10. Operating conditions (M95320-R and M95640-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 11. AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 12. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 13. DC characteristics (M95320 and M95640, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 14. DC characteristics (M95320 and M95640, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 15. DC characteristics (M95320-W and M95640-W, device grade 6). . . . . . . . . . . . . . . . . . . . 28
Table 16. DC characteristics (M95320-W and M95640-W, device grade 3). . . . . . . . . . . . . . . . . . . . 28
Table 17. DC characteristics (M95320-R and M95640-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 18. AC characteristics (M95320 and M95640, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 19. AC characteristics (M95320 and M95640, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 20. AC characteristics (M95320-W and M95640-W, device grade 6). . . . . . . . . . . . . . . . . . . . 32
Table 21. AC characteristics (M95320-W and M95640-W, device grade 3). . . . . . . . . . . . . . . . . . . . 33
Table 22. AC characteristics (M95320-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 23. AC characteristics (M95640-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 24. SO8N – 8 lead Plastic Small Outline, 150 mils body width, package mechanical data . . . 38
Table 25. TSSOP8 – 8 lead Thin Shrink Small Outline, package mechanical data . . . . . . . . . . . . . . 39
Table 26. MLP8 - 8-lead Ultra thin Fine pitch Dual Flat No Lead, package mechanical data. . . . . . . 40
Table 27. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 28. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
M95320, M95640, M95320-x, M95640-x List of figures
5/44
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. 8 pin package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Bus master and memory devices on the SPI bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 4. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0
Figure 5. Hold condition activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 6. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 7. Write Enable (WREN) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 8. Write Disable (WRDI) sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 9. Read Status Register (RDSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 10. Write Status Register (WRSR) sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 11. Read from Memory Array (READ) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 12. Byte Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2
Figure 13. Page Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 14. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 15. Serial Input timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 16. Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 17. Output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 18. SO8N – 8 lead Plastic Small Outline, 15 0 mils body wid th, pack age out line . . . . . . . . . . . 38
Figure 19. TSSOP8 – 8 lead Thin Shrink Small Outline, package outline. . . . . . . . . . . . . . . . . . . . . . 39
Figure 20. MLP8 - 8-lead Ultra thin Fine pitch Dual Flat No Lead, package outline . . . . . . . . . . . . . . 40
Summary description M95320, M95640, M95320-x, M95640-x
6/44
1 Summary description
These electrically erasable programmable memory (EEPROM) devices are accessed by a
high speed SPI-compatible bus.
The M95320, M 95320-W and M95320- R are 32Kbit de vices organiz ed as 409 6 x 8 bits. The
M95640, M95640-W and M95640-R are 64Kbit devices organized as 8192 x 8 bits.
The device is accessed by a simple serial interface that is SPI-compatible. The bus signals
are C, D and Q, as shown in Table 1 an d Figure 1.
The device is selected when Chip Select (S) is taken Lo w. Communications with the device
can be interrupted using Hold (HOLD).
In order to meet environmental requirements , ST offers these devices in ECOPACK®
packages.
ECOPACK® packages are Lead-fr ee and RoHS compliant.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
Figure 1. Logic diagram
Figure 2. 8 pin packag e connections
1. See Package mechanical section for package dimensions and how to identify pin-1.
AI01789C
S
VCC
M95xxx
HOLD
VSS
W
Q
C
D
DVSS C
HOLDQ
SV
CC
W
AI01790D
M95xxx
1
2
3
4
8
7
6
5
M95320, M95640, M95320-x, M95640-x Summary description
7/44
Table 1. Signal names
C Serial Clock
D Serial data Input
Q Serial data Output
SChip Select
WWrite Protect
HOLD Hold
VCC Supply Voltage
VSS Ground
Signal description M95320, M95640, M95320-x, M95640-x
8/44
2 Signal description
During all operations, VCC must be held stab le and within the specified valid range:
VCC(min) to VCC(max).
All of the input and output signals must be held High or Low (according to voltages of VIH,
VOH, VIL or VOL, as specified in Table 13 to Table 17). These signals are described next .
2.0.1 Serial Data Output (Q)
This output signal is used to tr ansf er data serially out of the de vice . Data is shifted out on the
falling edge of Serial Clock (C).
2.0.2 Serial Data Input (D)
This input signal is used to transfer data serially into the device. It receives instructions,
addresses , and the data t o be written. Values are latched on the rising edge of Serial Clock
(C).
2.0.3 Serial Clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data
present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on
Serial Data Output (Q) changes after the falling edge of Serial Clock (C).
2.0.4 Chip Select (S)
When this input signal is High, the de vice is deselected and Serial Data Output (Q) is at high
impedance. Unless an internal Write cycle is in progress, the device will be in the Standby
Power mode. Driving Chip Select (S) Low selects the device, placing it in the Active Power
mode.
After Power-up, a falling edge on Chip Select (S) is required prior to the start of any
instruction.
2.0.5 Hold (HOLD)
The Hold (HOLD) signal is used to pause any se rial communications with the de vice without
deselecting the device.
During the Hold condition, the Serial Data Outp ut (Q) is high impe da nc e, and Serial Data
Input (D) and Serial Clock (C) are Don’t Care.
To start the Hold condition, the device must be selected, with Chip Select (S) driven Low.
2.0.6 Write Protect (W)
The main purpose of th is inp ut sig nal is to freeze the size of the area of mem ory that is
protected against Write instructions (as specified by the values in the BP1 and BP0 bits of
the Status Register).
This pin must be driven either High or Low, and must be stable during all write operations.
M95320, M95640, M95320-x, M95640-x Connecting to the SPI bus
9/44
3 Connecting to the SPI bus
These devices are fully compatible with the SPI protocol.
All instructions, addresse s and inp ut dat a bytes are shifted in to the device, most significant
bit first. The Serial Data Input (D) is sampled on the first rising edge of the Serial Clock (C)
after Chip Select (S) goes Low.
All output data bytes are shifted out of the device , most significant bit first. The Serial Data
Output (Q) is latched on the first falling edge of the Serial Clock (C) after the instruction
(such as the Read from Memory Array and Read Status Register instructio ns) have been
clocked into the device.
Figure 3 shows three devices, connected to an MCU, on a SPI bus. Only one device is
selected at a time , so only o ne de vice driv es the Serial Data Output (Q) line at a time , all the
others being high impedance.
Figure 3. Bus master and memory devices on the SPI bus
1. The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.
2. These pull-up resistors, R, ensure that the memory devices are not selected if the Bus Master leaves the S line in the high-
impedance state. As the Bus Master may enter a state where all inputs/outputs are in high impedance at the same time
(e.g.: when the Bus Master is reset), the clock line (C) must be connected to an external pull-down resistor so that, when all
inputs/outputs become high impedance, S is pulled High while C is pulled Low (thus ensuring that S and C do not become
High at the same time, and so, that the tSHCH requirement is met).
AI12836
SPI Bus Master
SPI Memory
Device
SDO
SDI
SCK
CQD
S
SPI Memory
Device
CQD
S
SPI Memory
Device
CQD
S
CS3 CS2 CS1
SPI Interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
WHOLD WHOLD WHOLD
R(2) R(2) R(2)
VCC
VCC VCC VCC
VSS
VSS VSS VSS
R(2)
Connecting to the SPI bus M95320, M95640, M95320-x, M95640-x
10/44
3.1 SPI modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of
the two follo wing modes:
●CPOL=0, CPHA=0
●CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from th e falling edge of Serial Clock (C).
The difference between t he two modes , a s shown in Figure 4, is the clock polarity when the
bus master is in Stand-by mode and not transferring data:
●C remains at 0 for (CPOL=0, CPHA=0)
●C remains at 1 for (CPOL=1, CPHA=1)
Figure 4. SPI modes supported
AI01438B
C
MSB
CPHA
D
0
1
CPOL
0
1
Q
C
MSB
M95320, M95640, M95320-x, M95640-x Operating features
11/44
4 Operating features
4.1 Supply voltage (VCC)
4.1.1 Operating supply voltage VCC
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage
within the specified [VCC(min), VCC(max)] range must be applied (see Table 8.). In order to
secure a stable DC supply voltage, it is recommended to decouple the VCC line with a
suitable capacitor (usually of the order of 10nF to 100nF) close to the VCC/VSS package
pins.
This v oltage m ust remain st ab le and v a lid until the end of the tr an smission of the instruction
and, for a Write instruction, until the completi on of the internal write cycle (tW).
4.1.2 Power-up conditions
When the power supply is turned on, VCC rises from VSS to VCC. During this time, the Chip
Select (S) is not allowed to float but must follo w the V CC voltage, ther efore the S line should
be connecte d to VCC via a suitable pull-up resistor.
In addition, the Chip Select (S) input offers a built-in safety feat ur e, as the S input is edge
sensitive as well as level sensitive: after Power-up, the device does not become selected
until a falling edge has first been detected on Chip Select (S). This ensures that Chip Select
(S) must have been High, pr io r to goin g Low to start the first operation.
The VCC rise time must not be faster than 1V/µs.
4.1.3 Internal device Reset
In order to prevent inadvertent Write operations during Power -u p, a Power On Reset (POR)
circuit is included. At Power-up (continuous rise of VCC), the device will not respond to any
instruction until V CC has reached the Power On Reset threshold voltage (this threshold is
lower than the minimum VCC operating v oltage defined in Tables XX).
When VCC has passed the POR threshold, the device is reset and in the following state:
●Standby Power mode
●deselected (at next Power-up, a falling edge is required on Chip Select (S) before any
instructions can be started).
●not in the Hold Condition
Status Register state:
●the Write Enable Latch (WEL) is reset to 0
●Write In Progress (WIP) is reset to 0. The SRWD, BP1 and BP0 bits of the Status
Register are in the same state as when the power was last removed (they are non-
volatile bits).
Operating features M95320, M95640, M95320-x, M95640-x
12/44
4.1.4 Power-down
At Power-down (continuous decrease of VCC), as soon as VCC drops from the normal
operating volt age to below the Power On Reset threshold voltage, the device stops
responding to any instruction sent to it.
During Power-down, the device must be deselected and in Standby Power mode (that is
there should be no internal Write cycle in progress). Chip Select (S) should be allowed to
follow the voltage applied on VCC.
4.2 Active Power and Standby Power modes
When Chip Select (S) is Low, the device is selected, and in the Active Power mode. The
device consumes ICC, as specified in Table 13 to Table 17.
When Chip Select (S) is High, the device is deselected. If an Erase/Write cycle is not
currently in progress, the device then goes in to the Standby Power mode, and the device
consumption drops to ICC1.
4.2.1 Hold condition
The Hold (HOLD) signal is used to pause any se rial communications with the de vice without
resetting the clocking sequence.
During the Hold condition, the Serial Data Outp ut (Q) is high impe da nc e, and Serial Data
Input (D) and Serial Clock (C) are Don’t Care.
To enter the Hold condition, the device must be selected, with Chip Select (S) Low.
Normally, the device is kept selected, for the whole duration of the Hold condition.
Deselecting the de vice while it is in th e Hold condition, has the e ff ect of resetting the state of
the device, and this mechanism can b e used if it is required to reset an y pr ocesses that h ad
been in progress.
The Hold condition starts when the Hold (HOLD) signal is driven Low at the same time as
Serial Clock (C) already being Low (as shown in Figure 5).
The Hold condition ends when the Hold (HOLD) signal is driven High at the same time as
Serial Clock (C) already being Low.
Figure 5 also shows what happens if the rising and falling edges are not timed to coincide
with Serial Clock (C) being Low.
Figure 5. Hold condition activat ion
AI02029D
HOLD
C
Hold
Condition Hold
Condition
M95320, M95640, M95320-x, M95640-x Operating features
13/44
4.3 Status Register
Figure 6 shows the position of the Status Register in the control logic of the device. The
Status Register conta ins a number of status and control bits that can be read or set (as
appropriate) by specific instructions. See Section 6.3: Read Status Register (RDSR) for a
detailed description of the Status Register bits.
4.4 Data protection and protocol control
Non-volatile memory devices can be us ed in environments that are particularly noisy, and
within applications that coul d experience problems if memory bytes are corrupted.
Consequently, the device features the following dat a protection mechanisms:
●Write and Write Status Register instruction s ar e checked that they consist of a number
of clock pulses that is a multiple of eight, before they are accepted f or execution.
●All instructions that modify data m ust be preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch (WEL) bit. This bit is re turned to its re set state
by the following events:
–Power-up
– Write Disable (WRDI) instruction completion
– Write Status Register (WRSR) instruction completion
– Write (WRITE) instruction completion
●The Block Protect (BP1, BP0) bits allow part of the memory to be configured as read-
only. This is the Software Protected Mode (SPM).
●The Write Protect (W) signal allows the Block Protect (BP1, BP0) bits to be protected.
This is the Hardware Protecte d Mo d e (HPM ) .
F o r a n y inst ruction to be ac cept ed, and execut ed, Chip Se lect (S ) m ust be d riv e n High after
the rising edge of Serial Cloc k (C) f or the last bit of the inst ruction, and bef ore t he ne xt rising
edge of Serial Clock (C).
Two points need to be noted i n the previous sentence:
●The ‘last bit of the instruction’ can be the eighth bit of the instruction code, or t he eighth
bit of a data byte, depending on the instruction (except for Read Status Register
(RDSR) and Read (READ) instructions).
●The ‘next rising edge of Serial Clock (C)’ might (or might not) be the next bus
transaction for some other device on the SPI bus.
Table 2. Write-Protected block size
Status Register Bits
Protected Block
Array Addresses Protected
BP1 BP0 M95640, M95640-W,
M95640-R, M95640-S M95320, M95320-W,
M95320-R, M95320-S
0 0 none none none
0 1 Upper quarter 1800h - 1FFFh 0C00h - 0FFFh
1 0 Upper half 1000h - 1FFFh 0800h - 0FFFh
1 1 Whole memory 0000h - 1FFFh 0000h - 0FFFh
Memory organization M95320, M95640, M95320-x, M95640-x
14/44
5 Memory organization
The memory is organized as shown in Figure 6.
Figure 6. Block diagram
AI01272C
HOLD
S
WControl Logic High Voltage
Generator
I/O Shift Register
Address Register
and Counter Data
Register
1 Page
X Decoder
Y Decoder
C
D
Q
Size of the
Read only
EEPROM
area
Status
Register
M95320, M95640, M95320-x, M95640-x Instructions
15/44
6 Instructions
Each instruction starts with a single-byte code, as summarized in Table 3.
If an invalid instruction is sent (one not contained in <Blue>Table 3.), the device
automatically deselects itself.
6.1 Write Enable (WREN)
The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction.
The only way to do this is to send a Write Enable instruction to the device.
As shown in Figure 7, to send this instruction to the device, Chip Select (S) is driven Low,
and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then
enters a w ait state. I t waits f or a the de vice to be deselecte d, by Ch ip Select (S) being driv en
High.
Figure 7. Write Enable (WREN) seq uence
Table 3. Instruction set
Instruction Description Instruct ion Format
WREN Write Enable 0000 0110
WRDI Write Disable 0000 0100
RDSR Read Status Register 0000 0101
WRSR Write Status Register 0000 0001
READ Read from Memory Array 0000 0011
WRITE Write to Memory Array 0000 0010
C
D
AI02281E
S
Q
21 34567
High Impedance
0
Instruction
Instructions M95320, M95640, M95320-x, M95640-x
16/44
6.2 Write Disable (WRDI)
One way of resetting the Write Enab le Lat ch (WEL) bit is to send a Write Disab le inst ruction
to the device.
As shown in Figure 8, to send this instruction to the device, Chip Select (S) is driven Low,
and the bits of the instruction byte are shifted in, on Serial Data Input (D).
The de vice then enters a wait state . It w aits f or a the device to be deselected, by Chip Select
(S) being driven High.
The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events:
●Power-up
●WRDI instruction execution
●WRSR instruction completion
●WRITE instruction completion.
Figure 8. Write Disable (WRDI) seque nce
C
D
AI03750D
S
Q
21 34567
High Impedance
0
Instruction
M95320, M95640, M95320-x, M95640-x Instructions
17/44
6.3 Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows the Status Register to be read. The
Status Register may be read at any time, even while a Write or Write Status Register cycle
is in progress. When one of these cycles is in progress, it is recommended to check the
Write In Progress (WIP) bit before sending a new instruction to the de vice. It is also possib le
to read the Status Register continuously, as shown in Figure 9.
The Status Register format is shown in Table 4 and the status and control bits of the Status
Register are as follows:
6.3.1 WIP bit
The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write
Status Register cycle. When set to 1, such a cycle is in progress, when reset to 0 no such
cycle is in progress.
6.3.2 WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enab le Latch.
When set to 1 the inte rnal Write Enable Latch is set, when set to 0 t he internal Write Enable
Latch is reset and no Write or Write Status Register instruction is accepted.
6.3.3 BP1, BP0 bits
The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be
software protected against Write instructions. These bits are written with th e Write Status
Register (WRSR) instruction. When one or both of the Block Protect (BP1, BP0) bits is set to
1, the relevant memory area (as defined in Table 4) becomes protected against Write
(WRITE) instructions. The Block Protect (BP1, BP0) bits can be written provided that the
Hardware Protected mode has not been set.
6.3.4 SRWD bit
The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write
Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W)
signal allow the device to be put in the Hardware Protected mode (when the Status Register
Write Disable (SRWD) bit is set to 1, and Write Prot ect ( W ) is driv en Lo w). In this mode, the
non-volatile bits of th e Status Register (SRWD, BP1, BP0) become read-only bits and the
Write Status Register (WRSR) instruction is no longer accepted for execution.
Table 4. Status Register format
b7 b0
SRWD 0 0 0 BP1 BP0 WEL WIP
Status Register Write Protect
Block Protect Bits
Write Enable Latch Bit
Write In Progress Bit
Instructions M95320, M95640, M95320-x, M95640-x
18/44
Figure 9. Read Status Register (RDSR) sequence
6.4 Write Status Register (WRSR)
The Write Status Register (WRSR) instruction allows new values to be written to the Status
Register. Before it can be accepted, a Write Enable (WREN) instruction must previously
have been executed. After the Write Enable (WREN) instruction has been decoded and
executed, the device sets the Write Enable Latch (WEL).
The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) Low,
followed by the instruction code and the data byte on Serial Data Input (D).
The instruction sequence is shown in Figure 10.
The Write Status Register (WRSR) instruction has no effect on b6, b5, b4, b1 and b0 of the
Status Register. b6, b5 and b4 are always read as 0.
Chip Select (S) must be driven High after the rising edge of Serial Clock (C) that latches in
the eighth bit of the dat a byte , and bef ore the next rising edge of Serial Cloc k (C). Otherwise,
the Write Status Register (WRSR) instruction is not executed. As soon as Chip Select (S) is
driven High, the self-timed Write Status Register cycle (whose duration is tW) is initiated.
While the Write Status Register cycle is in progress, the Status Register ma y still be read to
check the value of the Write In Progress (WIP) b it. The Write In Progress (WIP) bit is 1
during the self-timed Write Status Register cycle, and is 0 when it is completed. When the
cycle is completed, the Write Enable Latch (WEL) is reset.
The Write Status Register (WRSR) instruction allo ws the user to change the values of the
Block Protect (BP1, BP0) bits, to define the size of the area that is to be treated as read-
only, as defined in Table 4.
The Write Status Register (WRSR) instruction also allows the user to set or reset the Status
Register Write Disable (SRWD) bit in accordance with the Write Protect (W) signal. The
Status Register Write Disable (SRWD) bit and Write Protect (W) signal allow the device to
be put in the Hardware Protected Mode (HPM). The Write Status Register (WRSR)
instruction is not executed once the Hardware Protected Mode (HPM) is entered.
The contents of the Status Register Write Disable (SRWD) and Block Protect (BP1, BP0)
bits are frozen at their current values from just before the start of the execution of Write
Status Register (WRSR) instruction. The new, updated, values take effect at the moment of
completion of the execution of Write Status Register (WRSR) instruction.
C
D
S
21 3456789101112131415
Instruction
0
AI02031E
Q76543210
Status Register Out
High Impedance
MSB
76543210
Status Register Out
MSB
7
M95320, M95640, M95320-x, M95640-x Instructions
19/44
The protection features of the device are summarized in Table 2.
When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial
delivery state), it is possible to write to the Status Register provided that the Write Enable
Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless
of the whether Write Protect (W) is driven High or Low.
When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two
cases need to be considered, depending on the state of Write Protect (W):
●If Write Protect (W) is driven High, it is possib le t o write to the Status Register p rov ided
that the Write Enable Latch (WEL) bit has previously been set by a Write Enable
(WREN) instruction.
●If Write Protect (W) is driven Low, it is not possible to write to the Status Register even
if the Write Enable Lat ch (WEL) bi t has previously been set by a Write Enab le (WREN)
instruction. (Attempts to write to the Status Register are reject ed, and ar e not accepte d
for execution). As a consequence, all the data bytes in the memory area that are
software protected (SPM) by the Block Protect (BP1, BP0) bits of the Status Register,
are also hardware protected against data modificati on.
Regardless of the order of the two events, the Hardware Protected Mode (HPM) can be
entered:
●by setting the Status Register Write Disable (SRWD) bit after driving Write Protect (W)
Low
●or by driving Write Protect (W) Low after setting the Status Register Write Disable
(SRWD) bit.
The only way to exit the Hardware Protected Mode (HPM) once entered is to pull Write
Protect (W) High.
If Write Protect (W) is permanently tied High, the Hardware Protected Mode (HPM) ca n
never be activated, and only the Software Protected Mode (SPM), using the Block Protect
(BP1, BP0) bits of the Stat us Register, can be used.
Table 5. Protection modes
W
Signal SRWD
Bit Mode Write Protection of the
Status Register
Memory Content
Protected Area(1)
1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 2.
Unprotected
Area(1)
10
Software
Protected
(SPM)
Status Regi ster is Writab le
(if the WREN instruction
has set the WEL bit)
The values in the BP1 and
BP0 bits can be changed
Write Protected Ready to accept
Write instr uction s
00
11
01
Hardware
Protected
(HPM)
Status Register is
Hardware write protected
The values in the BP1 and
BP0 bits cannot be
changed
Write Protected Ready to accept
Write instr uction s
Instructions M95320, M95640, M95320-x, M95640-x
20/44
Figure 10. Write Status Register (W RSR) sequence
Table 6. Address range bits(1)
1. b15 to b13 are Don’t Care on the 64 Kbit devices.
b15 to b12 are Don’t Care on the 32 Kbit devices.
Dev i c e 32 Kbit Devices 64 Kbit Devices
Address Bits A12-A0 A11-A0
C
D
AI02282D
S
Q
21 3456789101112131415
High Impedance
Instruction Status
Register In
0
765432 0
1
MSB
M95320, M95640, M95320-x, M95640-x Instructions
21/44
6.5 Read from Memory Array (READ)
As shown in Figure 11, to send this instruction to the device, Chip Select (S) is first driven
Low. The bits of the instruction byte and address bytes are then shifted in, on Serial Data
Input (D). The address is loaded into an internal address register, and the byte of data at
that address is shifted out, on Serial Data Output (Q).
If Chip Select (S) continues to be driven Low, the internal address register is automatically
incremented, and the byte of data at the new address is shifted out.
When the highest add ress is reached, the address counter rolls ov er to zero, allowing the
Read cycle to be continued indefinitely. The whole memory can, therefore, be read with a
single READ instruction.
The Read cycle is terminated by driving Chip Select (S) High. The rising edge of the Chip
Select (S) signal can occur at any time during the cycle.
The first byte addressed can be any byte within any page.
The instruction is not accepted, and is n ot executed, if a Write cycle is currently in progress.
Figure 11. Read from Memory Array (READ) sequence
1. Depending on the memory size, as shown in Table 6, the most significant address bits are Don’t Care.
C
D
AI01793D
S
Q
15
21 345678910 2021222324252627
1413 3210
28 29 30
76543 1 7
0
High Impedance Data Out 1
Instruction 16-Bit Address
0
MSB
MSB
2
31
Data Out 2
Instructions M95320, M95640, M95320-x, M95640-x
22/44
6.6 Write to Memory Array (WRITE)
As shown in Figure 12, to send this instruction to the device, Chip Select (S) is first driven
Low. The bits of the instruction byte, address byte, and at least one data byt e are then
shifted in, on Serial Data Input (D).
The instruction is terminated by driving Chip Select (S) High at a b y t e boun da ry of the input
data. In the case of Figure 12, this occurs after the eighth bit of the data byte has been
latched in, indicating that the instruction is being used to wr ite a sin gle byte. The self-timed
Write cycle starts, and continues for a period tWC (as specified in Table 18 to Table 22), at
the end of which the Write in Progress (WIP) bit is reset to 0.
If, though, Chip Select (S) continues to be driven Low, as shown in Figure 13, the next byte
of input data is shifted in, so that more than a single byte, starting from the given address
towards the end of the same page, can be written in a single internal Write cycle.
Each time a new data byte is shifted in, the least significant bits of the internal address
counter are incremented. If the number of data bytes sent to the device exceeds the page
boundary, the internal address counter rolls over to the beginning of the page, and the
previous data there ar e ov er written wit h the incomi ng d ata. (The p age size of these devices
is 32 bytes).
The instruction is not accepted, and is not executed, under the following conditions:
●if the Write Enable Latch (WEL) bit ha s no t been set to 1 (by executing a Write Enable
instruction just before)
●if a Write cycle is already in progress
●if the device has not been deselected, by Chip Select (S) being driven High, at a byte
boundary (after the eighth bit, b0, of the last data byte that has been latched in)
●if the addressed page is in t he region protected by the Block Protect (BP1 and BP0)
bits.
Figure 12. Byte Write (WRITE) sequence
1. Depending on the memory size, as shown in Table 6, the most significant address bits are Don’t Care.
C
D
AI01795D
S
Q
15
21 345678910 2021222324252627
1413 3210
28 29 30
High Impedance
Instruction 16-Bit Address
0
765432 0
1
Data Byte
31
M95320, M95640, M95320-x, M95640-x Instructions
23/44
Figure 13. Page Write (WRITE) sequence
1. Depending on the memory size, as shown in Table 6, the most significant address bits are Don’t Care.
C
D
AI01796D
S
3433 35 36 37 38 39 40 41 42 44 45 46 4732
C
D
S
15
21 345678910 2021222324252627
1413 3210
28 29 30
Instruction 16-Bit Address
0
765432 0
1
Data Byte 1
31
43
765432 0
1
Data Byte 2
765432 0
1
Data Byte 3
65432 0
1
Data Byte N
Power-up and delivery state M95320, M95640, M95320-x, M95640-x
24/44
7 Power-up and delivery state
7.1 Power-up state
After Power -up, the device is in the following state:
●Standby Power mode
●deselected (after Power-up, a falling edge is required on Chip Select (S) before any
instructions can be started).
●not in the Hold Condition
●the Write Enab le Latch (WEL) is reset to 0
●Write In Progress (WIP) is reset to 0
The SRWD, BP1 and BP0 bits of the Status Register are unchanged from the previous
power-down (they are non-volatile bits).
7.2 Initial delivery state
The device is delivered with the memory array set at all 1s (FFh). The Status Reg ister Write
Disable (SRWD) and Block Protect (BP1 and BP0) bits are initialized to 0.
M95320, M95640, M95320-x, M95640-x Maximum rating
25/44
8 Maximum rating
Stressing the device outside the ratings listed in Table 7 may cause permanent damage to
the device. These are stress ra tings only, and operation of the device at these, or any other
conditions outside those indicated in the Operating sections of this specification, is not
implied. Exposure to Absolute Maximum Rating conditions for exten ded periods may affect
device reliability. Refer also to the STMicroelectronics SURE Program and other relevant
quality documents.
Table 7. Absolute maximum ratings
Symbol Parameter Min. Max. Unit
TSTG Storage Temperature –65 150 °C
TAAmbient operating temperature –40 130 °C
TLEAD Lead Temperature during Soldering See note (1)
1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the ST ECOPACK®
7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS)
2002/95/EU
°C
VOOutput Voltage –0.50 VCC+0.6 V
VIInput Voltage –0.50 6.5 V
VCC Supply Voltage –0.50 6.5 V
VESD Electrostatic Discharge Voltage (Human Body
model)(2)
2. AEC-Q100-002 (compliant with JEDEC Std JESD22-A114A, C1=100pF, R1=1500Ω, R2=500Ω)
–4000 4000 V
DC and AC parameters M95320, M95640, M95320-x, M95640-x
26/44
9 DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC Characteristic tables that
follow are derived from tests performed under the Measurement Conditions summarized in
the relevant tables. Designers should check that the operating conditions in their circuit
match the measurem ent conditions when relying on the quoted parameters.
Figure 14. AC measurement I/O waveform
Table 8. Operating conditions (M95320 and M95640)
Symbol Parameter Min. Max. Unit
VCC Supply Voltage 4.5 5.5 V
TAAmbient Operating Temperatu re (Device Grade 6) –40 85 °C
Ambient Operating Temperature (Device Grade 3) –40 125 °C
Table 9. Operating conditions (M95320-W and M95640-W)
Symbol Parameter Min. Max. Unit
VCC Supply Voltage 2.5 5.5 V
TAAmbient Operating Temperature (Device Grade 6) –40 85 °C
Ambient Operating Temperature (Device Grade 3) –40 125 °C
Table 10. Operating conditions (M95320-R and M95640-R)
Symbol Parameter Min.(1)
1. This product is under development. For more information, please contact your nearest ST sales office.
Max. (1) Unit
VCC Supply Voltage 1.8 5.5 V
TAAmbient Operating Temperatu r e –40 85 °C
Table 11. AC measurement con ditions(1)
1. Output Hi-Z is defined as the point where data out is no longer driven.
Symbol Parameter Min. Typ. Max. Unit
CLLoad Capacitance 30 pF
Input Rise and Fall Times 50 ns
Input Pulse Voltages 0.2VCC to 0.8VCC V
Input and Output Timing Reference Voltages 0.3VCC to 0.7VCC V
AI00825B
0.8VCC
0.2VCC
0.7VCC
0.3VCC
Input and Output
Timing Reference Levels
Input Levels
M95320, M95640, M95320-x, M95640-x DC and AC parameters
27/44
Table 12. Capacitance(1)
1. Sampled only, not 100% tested, at TA=25°C and a frequency of 5MHz.
Symbol Parameter Test Condition Min.Max.Unit
COUT Output Capacitance (Q) VOUT = 0V 8 pF
CIN Input Capacitance (D) VIN = 0V 8 pF
Input Capacitance (other pins) VIN = 0V 6 pF
Table 13. DC characteristics (M95320 and M95640, device grade 6)
Symbol Parameter Test Condition Min. Max. Unit
ILI Input Leakage Current VIN = VSS or VCC ± 2 µA
ILO Output Leakage
Current S = VCC, VOUT = VSS or VCC ± 2 µA
ICC Supply Current C=0.1V
CC/0.9VCC at 10MHz,
VCC = 5V, Q = open 5mA
ICC1 Supply Current
(Standby) S = VCC, VCC = 5V,
VIN = VSS or VCC 2µA
VIL Input Low Voltage –0.45 0.3VCC V
VIH Input High Voltage 0.7VCC VCC+1 V
VOL(1)
1. For all 5V range devices, the device meets the output requirements for both TTL and CMOS standards.
Output Low Voltage IOL = 2 mA, VCC = 5V 0.4 V
VOH(1) Output High Voltage IOH = –2 mA, VCC = 5V 0.8VCC V
Table 14. DC characteristics (M95320 and M95640, device grade 3)
Symbol Parameter Test Condition Min. Max. Unit
ILI Input Leakage Current VIN = VSS or VCC ± 2 µA
ILO Output Leakage Current S = VCC, VOUT = VSS or VCC ± 2 µA
ICC Supply Current C = 0.1VCC/0.9VCC at 5MHz,
VCC = 5V, Q = open 4mA
ICC1 Supply Current
(Standby) S = VCC, VCC = 5V,
VIN = VSS or VCC 5µA
VIL Input Low Voltage –0.45 0.3 VCC V
VIH Input High Voltage 0.7 VCC VCC+1 V
VOL(1)
1. For all 5V range devices, the device meets the output requirements for both TTL and CMOS standards.
Output Low Voltage IOL = 2mA, VCC = 5V 0.4 V
VOH(1) Output High Voltage IOH = –2mA, VCC = 5V 0.8 VCC V
DC and AC parameters M95320, M95640, M95320-x, M95640-x
28/44
Table 15. DC characteristics (M95320-W and M95640-W, device grade 6)
Symbol Parameter Test Condition Min. Max. Unit
ILI Input Leakage Current VIN = VSS or VCC ± 2 µA
ILO Output Leakage Current S = VCC, VOUT = VSS or VCC ± 2 µA
ICC Supply Current C = 0.1VCC/0.9VCC at 5MHz,
VCC = 2 .5V, Q = o pen 3mA
ICC1 Supply Current
(Standby) S = VCC, VCC = 2.5V
VIN = VSS or VCC 1µA
VIL Input Low Voltage –0.45 0.3VCC V
VIH Input High Voltage 0.7VCC VCC+1 V
VOL Output Low Voltage IOL = 1.5mA, VCC = 2.5V or
IOL = 2mA, VCC = 5.5V 0.4 V
VOH Output High Voltage IOH = –0.4mA, VCC = 2.5V or
IOH = –2mA, VCC = 5.5V 0.8VCC V
Table 16. DC characteristics (M95320-W and M95640-W, device grade 3)
Symbol Parameter Test Condition Min. Max. Unit
ILI Input Leakage Current VIN = VSS or VCC ± 2 µA
ILO Output Leakage Current S = VCC, VOUT = VSS or VCC ± 2 µA
ICC Supply Current C = 0.1VCC/0.9VCC at 5MHz,
VCC = 2.5V, Q = open 3mA
ICC1 Supply Current (Standby) S = VCC, VCC = 2.5V, VIN = V SS or VCC 2µA
VIL Input Low Voltage –0.45 0.3VCC V
VIH Input High Voltage 0.7VCC VCC+1 V
VOL Output Low Voltage IOL = 1.5mA, VCC = 2.5V 0.4 V
VOH Output High Voltage IOH = –0.4mA, VCC = 2.5V 0.8V CC V
M95320, M95640, M95320-x, M95640-x DC and AC parameters
29/44
Table 17. DC characteristics (M95320-R and M95640-R)
Symbol Parameter Test Condition Min.(1)
1. This product is under qualification. For more information, please contact your nearest ST sales office.
Max.(1) Unit
ILI Input Leakage Current VIN = VSS or VCC ± 1 µA
ILO Output Leakage Current S = VCC, VOUT = VSS or VCC ± 1 µA
ICC Supply Current C = 0.1VCC/0.9VCC at max clock
frequency, 1.8V < VCC =2.5V,
Q = open 3mA
ICC1 Supply Current (Standby) S = VCC, VIN = VSS or VCC,
1.8V < VCC =2.5V 1µA
VIL Input Lo w Voltage –0.45 0.3 VCC V
VIH Input High Voltage 0.7 VCC VCC+1 V
VOL Output Low Voltage IOL = 0.15 mA, VCC = 1.8 V 0.3 V
VOH Output High Voltage IOH = –0.1 mA, VCC = 1.8V 0.8V
CC V
DC and AC parameters M95320, M95640, M95320-x, M95640-x
30/44
Table 18. AC charac teristics (M95320 and M95640, device grade 6)
Test condition s sp ec ified in Table 11 and Table 8
Symbol Alt. Parameter Min. Max. Unit
fCfSCK Clock Frequency D.C. 10 MHz
tSLCH tCSS1 S Activ e Setup Time 15 ns
tSHCH tCSS2 S Not Active Setup Time 15 ns
tSHSL tCS S Deselect Time 40 ns
tCHSH tCSH S Active Hold Time 25 ns
tCHSL S Not Active Hold Time 15 ns
tCH(1)
1. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max).
tCLH Clock High Time 40 ns
tCL(1) tCLL Clock Low Time 40 ns
tCLCH(2)
2. Value guaranteed by characterization, not 100% tested in production.
tRC Clock Rise Time 1 µs
tCHCL(2) tFC Clock Fall Time 1 µs
tDVCH tDSU Data In Setup Time 15 ns
tCHDX tDH Data In Hold Time 15 ns
tHHCH Clock Low Hold Time after HOLD not Activ e 15 ns
tHLCH Clock Low Hold Time after HOLD Active 20 ns
tCLHL Clock Low Set-up Time before HOLD Active 0 ns
tCLHH Clock Low Set-up Time before HOLD not Active 0 ns
tSHQZ(2) tDIS Output Disable Time 25 ns
tCLQV tVClock Low to Output Valid 25 ns
tCLQX tHO Output Hold Time 0 ns
tQLQH(2) tRO Output Rise Time 20 ns
tQHQL(2) tFO Output Fall Time 20 ns
tHHQV tLZ HOLD High to Output Valid 25 ns
tHLQZ(2) tHZ HOLD Low to Output High-Z 25 ns
tWtWC Write Time 5 ms
M95320, M95640, M95320-x, M95640-x DC and AC parameters
31/44
Table 19. AC charac teristics (M95320 and M95640, device grade 3)
Test conditions specified in Table 11 and Table 8
Symbol Alt. Parameter Min. Max. Unit
fCfSCK Clock Frequency D.C. 5 MHz
tSLCH tCSS1 S Active Setup Time 90 ns
tSHCH tCSS2 S Not Active Setup Time 90 ns
tSHSL tCS S Deselect Time 100 ns
tCHSH tCSH S Active Hold Time 90 ns
tCHSL S Not Active Hold Time 90 ns
tCH(1)
1. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max).
tCLH Clock High Time 90 ns
tCL(1) tCLL Clock Low Time 90 ns
tCLCH(2)
2. Value guaranteed by characterization, not 100% tested in production.
tRC Clock Rise Time 1 µs
tCHCL(2) tFC Clock Fall Time 1 µs
tDVCH tDSU Data In Setup Time 20 ns
tCHDX tDH Data In Hold Time 30 ns
tHHCH Clock Low Hold Time after HOLD not Active 70 ns
tHLCH Clock Low Hold Time after HOLD Active 40 ns
tCLHL Clock Low Set-up Time before HOLD Active 0 ns
tCLHH Clock Low Set-up Time before HOLD not Active 0 ns
tSHQZ(2) tDIS Output Disable Time 100 ns
tCLQV tVClock Low to Output Valid 60 ns
tCLQX tHO Output Hold Time 0 ns
tQLQH(2) tRO Output Rise Time 50 ns
tQHQL(2) tFO Output Fall Time 50 ns
tHHQV tLZ HOLD High to Output Valid 50 ns
tHLQZ(2) tHZ HOLD Low to Output High-Z 100 ns
tWtWC Write Time 5 ms
DC and AC parameters M95320, M95640, M95320-x, M95640-x
32/44
Table 20. AC characteristics (M95320-W and M95640-W, device grade 6)
Test conditions specified in Table 11 and Table 9
Symbol Alt. Parameter
Current
Product
Version(1)
1. Current product version is identified by Process Identification letter ‘V’’.
New Product
Version(2)
2. New product version is identified by Process Identification letter ‘P’. Please contact your nearest ST sales
office for details (PCN MPG-NVM/05/1315 and PCN MPG-NVM/05/1191)
Unit
Min. Max. Min. Max.
fCfSCK Clock Frequency D.C . 5 D.C. 10 MHz
tSLCH tCSS1 S Active Setup Time 90 30 ns
tSHCH tCSS2 S Not Active Setup Time 90 30 ns
tSHSL tCS S Deselect Time 100 40 ns
tCHSH tCSH S Active Hold Time 90 30 ns
tCHSL S Not Activ e Hold Time 90 30 ns
tCH(3)
3. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max).
tCLH Clock High Time 90 42 ns
tCL(3) tCLL Cloc k Low Time 90 40 ns
tCLCH(4)
4. Value guaranteed by characterization, not 100% tested in production.
tRC Clock Rise Time 1 2 µs
tCHCL(4) tFC Clock Fall Time 1 2 µs
tDVCH tDSU Da ta In Setup Time 20 10 ns
tCHDX tDH Data In Hold Time 30 10 ns
tHHCH Clock Low Hold Time after HOLD not Active 70 30 ns
tHLCH Clock Low Hold Time after HOLD Active 40 30 ns
tCLHL Clock Low Set-up Time before HOLD Active 0 0 ns
tCLHH Clock Low Set-up Time bef ore HOLD not
Active 00 ns
tSHQZ(4) tDIS Output Disable Time 100 40 ns
tCLQV tVClock Low to Output Valid 60 40 ns
tCLQX tHO Output Hold Time 0 0 ns
tQLQH(4) tRO Output Rise Time 50 40 ns
tQHQL(4) tFO Output Fall Time 50 40 ns
tHHQV tLZ HOLD High to Output Valid 50 40 ns
tHLQZ(4) tHZ HOLD Low to Output High-Z 100 40 ns
tWtWC Write Time 5 5 ms
M95320, M95640, M95320-x, M95640-x DC and AC parameters
33/44
Table 21. AC characteristics (M95320-W and M95640-W, device grade 3)
Test conditions specified in Table 11 and Table 9
Symbol Alt. Parameter Min. Max. Unit
fCfSCK Clock Frequency D.C. 5 MHz
tSLCH tCSS1 S Active Setup Time 90 ns
tSHCH tCSS2 S Not Active Setup Time 90 ns
tSHSL tCS S Deselect Time 100 ns
tCHSH tCSH S Active Hold Time 90 ns
tCHSL S Not Active Hold Time 90 ns
tCH(1)
1. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max).
tCLH Clock High Time 90 ns
tCL(1) tCLL Clock Low Time 90 ns
tCLCH(2)
2. Value guaranteed by characterization, not 100% tested in production.
tRC Clock Rise Time 1 µs
tCHCL(2) tFC Clock Fall Time 1 µs
tDVCH tDSU Data In Setup Time 20 ns
tCHDX tDH Data In Hold Time 30 ns
tHHCH Clock Low Hold Time after HOLD not Activ e 70 ns
tHLCH Clock Low Hold Time after HOLD Active 40 ns
tCLHL Clock Low Set-up Time before HOLD Active 0 ns
tCLHH Clock Low Set-up Time before HOLD not Active 0 ns
tSHQZ(2) tDIS Output Disable Time 100 ns
tCLQV tVClock Low to Output Valid 60 ns
tCLQX tHO Output Hold Time 0 ns
tQLQH(2) tRO Output Rise Time 50 ns
tQHQL(2) tFO Output Fall Time 50 ns
tHHQV tLZ HOLD High to Output Valid 50 ns
tHLQZ(2) tHZ HOLD Low to Output High-Z 100 ns
tWtWC Write Time 5 ms
DC and AC parameters M95320, M95640, M95320-x, M95640-x
34/44
Table 22. AC characteristics (M95320-R)
Test conditions specified in Table 11 and Table 10
Symbol Alt. Parameter Min. Max. Unit
fCfSCK Clock Frequency D.C. 5 MHz
tSLCH tCSS1 S Active Setup Time 60 ns
tSHCH tCSS2 S Not Active Setup Time 60 ns
tSHSL tCS S Deselect Time 90 ns
tCHSH tCSH S Active Hold Time 60 ns
tCHSL S Not Active Hold Time 60 ns
tCH(1)
1. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max).
tCLH Clock High Time 90 ns
tCL(1) tCLL Cloc k Low Time 90 ns
tCLCH(2)
2. Value guaranteed by characterization, not 100% tested in production.
tRC Clock Rise Time 2 µs
tCHCL(2) tFC Clock Fall Time 2 µs
tDVCH tDSU Data In Setup Time 20 ns
tCHDX tDH Data In Hold Time 20 ns
tHHCH Clock Low Hold Time after HOLD not Active 60 ns
tHLCH Clock Low Hold Time after HOLD Active 60 ns
tCLHL Clock Low Set-up Time before HOLD Activ e 0 0
tCLHH Clock Low Set-up Time before HOLD not
Active 00
tSHQZ(2) tDIS Output Disable Time 80 ns
tCLQV tVClock Low to Output Valid 80 ns
tCLQX tHO Output Hold Time 0 ns
tQLQH(2) tRO Output Rise Time 80 ns
tQHQL(2) tFO Output Fall Time 80 ns
tHHQV tLZ HOLD High to Output Valid 80 ns
tHLQZ(2) tHZ HOLD Low to Output High-Z 80 ns
tWtWC Write Time 10 ms
M95320, M95640, M95320-x, M95640-x DC and AC parameters
35/44
Table 23. AC characteristics (M95640-R)
Test conditions specified in Table 11 and Table 9
Symbol Alt. Parameter Min. Max. Unit
fCfSCK Clock Frequency D.C . 2 MHz
tSLCH tCSS1 S Active Setup Time 150 ns
tSHCH tCSS2 S Not Active Setup Time 150 ns
tSHSL tCS S Deselect Time 200 ns
tCHSH tCSH S Active Hold Time 150 ns
tCHSL S Not Active Hold Time 150 ns
tCH(1)
1. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max).
tCLH Clock High Time 200 ns
tCL(3) tCLL Clock Low Time 200 ns
tCLCH(2)
2. Value guaranteed by characterization, not 100% tested in production.
tRC Clock Rise Time 2 µs
tCHCL(4) tFC Clock Fall Time 2 µs
tDVCH tDSU Da ta In Setup Time 50 ns
tCHDX tDH Data In Hold Time 50 ns
tHHCH Clock Low Hold Time after HOLD not Active 150 ns
tHLCH Clock Low Hold Time after HOLD Active 150 ns
tCLHL Clock Low Set-up Time bef ore HOLD Active 0 0
tCLHH Clock Low Set-up Time bef ore HOLD not Active 0 0
tSHQZ(4) tDIS Output Disable Time 200 ns
tCLQV tVCloc k Low to Output Valid 200 ns
tCLQX tHO Output Hold Time 0 ns
tQLQH(4) tRO Output Rise Time 200 ns
tQHQL(4) tFO Output Fall Time 200 ns
tHHQV tLZ HOLD High to Output Valid 200 ns
tHLQZ(4) tHZ HOLD Low to Output High-Z 200 ns
tWtWC Write Time 10 ms
DC and AC parameters M95320, M95640, M95320-x, M95640-x
36/44
Figure 15. Serial Input timing
Figure 16. Hold timing
C
D
AI01447C
S
MSB IN
Q
tDVCH
High Impedance
LSB IN
tSLCH
tCHDX
tCHCL
tCLCH
tSHCH
tSHSL
tCHSHtCHSL
C
Q
AI01448B
S
D
HOLD
tCLHL
tHLCH
tHHCH
tCLHH
tHHQVtHLQZ
M95320, M95640, M95320-x, M95640-x DC and AC parameters
37/44
Figure 17. Output timing
C
Q
AI01449e
S
LSB OUT
DADDR.
LSB IN
tSHQZ
tCH
tCL
tQLQH
tQHQL
tCLQX
tCLQV
tCLQX
tCLQV
Package mechanical M95320, M95640, M95320-x, M95640-x
38/44
10 Package mechanical
Figure 18. SO8N – 8 lead Plastic Small Outline, 150 mils bod y width, pac ka ge outline
1. Drawing is not to scale.
Table 24. SO8N – 8 lead Plastic Small Outline, 150 mils body width, package
mechanical data
Symbol millimeters inches
Typ Min Max Typ Min Max
A1.750.069
A1 0.10 0.25 0.004 0.010
A2 1.25 0.049
b 0.28 0.48 0.011 0.019
c 0.17 0.23 0.007 0.009
ccc 0.10 0.004
D 4.90 4.80 5.00 0.193 0.189 0.197
E 6.00 5.80 6.20 0.236 0.228 0.244
E1 3.90 3.80 4.00 0.154 0.150 0.157
e1.27– –0.050– –
h 0.25 0.50 0.010 0.020
k0°8°0°8°
L 0.40 1.27 0.016 0.050
L1 1.04 0.041
SO-A
E1
8
ccc
be
A
D
c
1E
h x 45˚
A2
k
0.25 mm
L
L1
A1
GAUGE PLANE
M95320, M95640, M95320-x, M95640-x Package mechanical
39/44
Figure 19. TSSOP8 – 8 l ead Thin Shrink Small Outl ine, package outline
1. Drawing is not to scale.
Table 25. TSSOP8 – 8 lead Thin Shrink Small Outline, package mechanical data
Symbol millimeters inches
Typ. Min. Max. Typ. Min. Max.
A 1.200 0.0472
A1 0.050 0.150 0.0020 0.0059
A2 1.000 0.800 1.050 0.0394 0.0315 0.0413
b 0.190 0.300 0.0075 0.0118
c 0.090 0.200 0.0035 0.0079
CP 0.100 0.0039
D 3.000 2.900 3.100 0.1181 0.1142 0.1220
e 0.650 – – 0.0256 – –
E 6.400 6.200 6.600 0.2520 0.2441 0.2598
E1 4.400 4.300 4.500 0.1732 0.1693 0.1772
L 0.600 0.450 0.750 0.0236 0.0177 0.0295
L1 1.000 0.0394
α0° 8° 0° 8°
TSSOP8AM
1
8
CP
c
L
EE1
D
A2A
α
eb
4
5
A1
L1
Package mechanical M95320, M95640, M95320-x, M95640-x
40/44
Figure 20. MLP8 - 8-lead Ultra thin Fine pitch Dual Flat No Lead, package outline
1. Drawing is not to scale.
Table 26. MLP8 - 8-lead Ultra thin Fine pitch Dual Flat No Lead, package
mechanical data
Symbol millimeters inches
Typ Min Max Typ Min Max
A 0.55 0.50 0.60 0.022 0.020 0.024
A1 0.00 0.05 0.000 0.002
b 0.25 0.20 0.30 0.010 0.008 0.012
D2.00 0.079
D2 1.55 1.65 0.061 0.065
ddd 0.05 0.002
E3.00 0.118
E2 0.15 0.25 0.006 0.010
e0.50– –0.020– –
L 0.45 0.40 0.50 0.018 0.016 0.020
L1 0.15 0.006
L3 0.30 0.012
N8 8
D
E
UFDFPN-01
A
A1 ddd
L1
eb
D2
L
E2
L3
M95320, M95640, M95320-x, M95640-x Part numbering
41/44
11 Part numbering
F o r a list of availab le opt ions (spee d, package, etc.) or for further information on any aspect
of this device, please contact your nea rest ST Sales Office.
The category of second-Level Inte rconnect is mark ed on the package and on the inner box
label, in compliance with JEDEC Standar d JESD97. The maximum ratings related to
soldering conditions are also marked on the inner box label.
Table 27. Ordering information scheme
Example: M95640 – W MN 6 T P /B
Device Type
M95 = SPI serial access EEPROM
Device Function
640 = 64 Kbit (8192 x 8)
320 = 32 Kbit (4096 x 8)
Operating Voltage
blank = V CC = 4.5 to 5.5V
W = VCC = 2.5 to 5.5V
R = VCC = 1.8 to 5.5V
Package
MN = SO8 (150 mil width)
DW = TSSOP8 (169 mil width)
MB = MLP8 (2x3 mm)
Device Grade
6 = Industrial temperature range, –40 to 85 °C.
Device tested with standard test flow
3 = Device tested with High Reliability Certified Flow(1)Automotive
temperature range (–40 to 125 °C)
1. ST strongly recommends the use of the Automotive Grade devices for use in an automotive environment.
The High Reliability Certified Flow (HRCF) is described in the quality note QNEE9801. Please ask your
nearest ST sales office for a copy.
Option
blank = Standard Packing
T = Tape and Reel Packing
Plating Technology
blank = Standard SnPb plating
P or G = ECOPA CK (RoHS compliant)
Process letter(2)
2. The Process letter only concerns Grade-3 device s.
/B = DP26% Rsst
/P = DP26% Chartered
Revision history M95320, M95640, M95320-x, M95640-x
42/44
12 Revision history
Table 28. Doc ument revisi on history
Date Revision Changes
13-Jul-2000 1.2 Human Body Model meets JEDEC std (Table 2). Minor adjustments on pp
1,11,15. New clause on p7. Addition of TSSOP8 package on pp 1, 2,
Ordering Info, Mechanical Data
16-Mar-2001 1.3
Test condition added ILI and ILO, and specification of tDLDH and tDHDL
removed.
tCLCH, tCHCL, tDLDH and tDHDL changed to 50ns for the -V range.
“-V” Voltage range changed to “2.7V to 3.6V” throughout.
Maximum lead soldering time and temperature conditions updated.
Instruction sequence illustrations updated.
“Bus Master and Memory Devices on the SPI bus” illustration updated.
Package Mechanical data updated
19-Jul-2001 1.4 M95160 and M95080 devices remo ved to their own data sheet
06-Dec-2001 1.5 Endurance increased to 1M write/erase cycles
Instruction sequence illustrations updated
18-Dec-2001 2.0 Document reformatted using the new template. No parameters changed.
08-Feb-2002 2.1 Ann ouncement made of planned upgrade to 10MHz clock for the 5V, –40
to 85°C, range.
Endurance set to 100K write/erase cycles
18-Dec-2002 2.2 10MHz, 5MHz, 2MHz clock; 5ms, 10ms Write Time; 100K, 1M erase/write
cycles distinguished on front page, and in the DC and AC Characteristics
tables
26-Mar-2003 2.3 Process indentification letter corrected in footnote to AC Characteri stics
table for temp. range 3
26-Jun-2003 2.4 -S voltage range upgraded by removing it and inserting -R voltage range
in its place
15-Oct-2003 3.0 Table of contents, and Pb-free options added. VIL(min) improved to -0.45V
21-Nov-2003 3.1 VI(min) and VO(min) corrected (improved) to -0.45V
28-Jan-2004 4.0 TSSOP8 connections added to DIP and SO connections
M95320, M95640, M95320-x, M95 640-x Revision hist ory
43/44
24-May-2005 5.0
M95320-S and M95640-S root part numbers (1.65 to 5.5V Supply) and
related characteristics added.
20MHz Clock rate added.TSSOP14 package removed and MLP8 package
added.
Description of Power On Reset: VCC Lock-Out Write Protect updated.
Product List summary table added. Absolute Maximum Ratings for
VIO(min) and VCC(min) improved. Soldering temperature information
clarified for RoHS compliant devices. Device Grade 3 clarified, with
reference to HRCF and automotive environments. AEC-Q100-002
compliance. tCHHL(min) and tCHHH(min) is tCH for products under “S”
process. tHHQX corrected to tHHQV.
Figure 16: Hold timing updated.
07-Jul-2006 6
Document converted to new ST template.
Packages are ECOPACK® compliant. PDIP package removed.
SO8N package specifications updated (see Table 24 and Figure 18).
M95640-S and M95320-S part numbers remov ed (DC and A C parameters
updated accordingly).
How to identify previous, current and new products by the Process
identification letter Table removed.
Figure 4 : SPI modes supported updated and Note 2 added. First three
paragraphs of Section 4: Operating features replaced by Section 4.1:
Supply voltage (VCC).
TA added to Table 7: Absolute maximum ratings. ICC and ICC1 updated in
Table 13, Table 14, Table 15 and Table 17. VOL and VOH updated in
Table 15. ICC updated in Table 16. Data in Table 17 is no longer
preliminary.
tCH updated in Table 20. Table 23: AC characteristics (M95640-R) added.
Timing line of tSHQZ modified in Figure 17: Output timing.
Process letter added to Table 27: Ordering information scheme, Note 2
removed. Note 2 removed from Figure 2.
Table 28. Document revision history (continued)
Date Revision Changes
M95320, M95640, M95320-x, M95 640-x
44/44
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