TLE 8718 SA Smart 18-Channel Lowside Switch with Micro Second Bus Data Sheet Rev. 1.1, 2012-07-31 Automotive Power TLE 8718 SA Table of Contents Table of Contents 1 1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Device Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 3.1 3.2 3.3 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 4.1 4.2 4.3 4.4 4.5 General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test coverage (TC) in series production . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 11 11 13 14 14 5 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Stages OUT1 and OUT3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Stages OUT2 and OUT4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Stages OUT5...OUT8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Stages OUT9 and OUT10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Stages OUT11...OUT14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Stages OUT15 and OUT16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Stages OUT17 and OUT18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Diagram MSC to OUTn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel connection of PS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 15 15 17 19 21 23 26 28 30 30 6 6.1 6.2 6.3 6.4 Device Self Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Short Circuit Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Over Temperature Shut Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Battery Voltage Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 32 32 32 33 7 Supervisory (DIS5_10, DELAYIN, DELAYOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8 8.1 8.2 8.3 8.4 8.5 8.6 Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Diagnostic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Encoding of Diagnostic Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . State Diagram of the Device Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset of the Diagnostic Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 36 39 40 41 41 42 9 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 Supply, VDD Monitoring, Reset and ABE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General functions of VDD Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD Undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD Overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ABE Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Testing of VDD Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Testing procedure of VDD Monitoring in the application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 43 44 44 45 46 46 46 47 Data Sheet 2 Rev. 1.1, 2012-07-31 TLE 8718 SA Table of Contents 10 Device Logic Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 11 11.1 11.1.1 11.1.2 11.1.3 11.1.4 11.2 11.3 11.4 11.5 Micro Second Channel MSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Downstream Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage Level Diagrams of low voltage differential pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Downstream Supervisory Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Upstream Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Clock Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 53 54 54 54 55 57 58 58 59 12 Control of the device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1.1 WR_OUT1516 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1.2 WR_RST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1.3 WR_START . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1.4 RD_CONFIG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1.5 RD_DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.1 CONREG1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.2 CONREG2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.3 CONREG3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.4 CONREG4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.5 OUT1516 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.6 OUTREG_EVEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.7 OUTREG_ODD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.8 DIAREG1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.9 DIAREG2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.10 DIAREG3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.11 DIAREG4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.12 DIAREG5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.13 DIAREG6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.14 DIAREG7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.15 IDENTREG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.16 TESTREG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.17 SEL_THRES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.18 FUSE_SC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 62 63 64 64 66 66 67 67 67 68 68 69 70 70 71 71 72 72 73 74 75 76 77 77 78 13 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 14 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 15 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Data Sheet 3 Rev. 1.1, 2012-07-31 Smart 18-Channel Lowside Switch with Micro Second Bus speedFLEX 1 TLE8718SA Overview Features * * * * * * * * * * * * * Operating Conditions -40...150C Over Temperature Warning ESD Capability 2/4KV HBM on-/off board Pins Short Circuit Protected for VBAT = 36V Active Zener Clamping at typically 55V Open Load, Short to Ground, Short Circuit Diagnosis (2 bit/OUT) Output control, diagnostics and initialisation via high speed serial communication: Micro Second Channel [MSC] all Pins protected against 36V Over-Voltage and Under-Voltage Monitoring Two Output Channels operating during low supply voltage possible Programmable Short circuit behavior: switch off or current limitation Green Product (RoHS compliant) AEC Qualified PG-DSO-36 Application * Automotive Engine Management Applications * Driver IC for inductive and ohmic actuators, such as Injectors, Solenoids, Relays, Lambda Heater. Table 1 Output Stage Overview and Product Summary Output Maximum current RON_max at Tj = 150C without clamping OUT1, OUT3 8A 200m OUT2, OUT4 3A 350m OUT5...OUT8 2.2A 720m OUT9...OUT10 2.2A 470m OUT11...OUT14 2.2A 720m OUT15, OUT16 0.6A 2400m OUT17, OUT18 0.6A 2400m Operating Voltage VDD_RES VDD_POR VDD VDS (AZ) 2.5V (defined behavior of the device) Active Zener Voltage 3...3.5V (OUT15,16 delayed switch-off) 4.5...5.5V (operating range) 50...60V Type Package Marking TLE8718SA PG-DSO-36 TLE8718SA Data Sheet 4 Rev. 1.1, 2012-07-31 TLE 8718 SA Overview 1.1 Device Description All stages are controlled by MSC interface. The MSC interface can be single ended or low voltage differential type. Serial transmission of the error code (diagnostic) via MSC interface (upstream channel). All power stages (PS) are protected against short circuit to battery voltage (SCB). All PS (OUT1...18) are equipped with switch off mode and current control mode in case of SCB (configurable). Diagnosis of open load (OL), short-circuit to ground (SCG), short-circuit to battery voltage (SCB) and over temperature (DOT) individually for each PS. The fault conditions SCB, SCG, OL and DOT are not stored until an integrated filtering time has expired. If, at one output, several errors occur in a sequence, always the last detected error is stored (after filtering time). All fault conditions are encoded in two bits per stage and stored in the corresponding MSC interface registers. Additionally there is one common diagnostic bit for fault occurrence (FAILURE_FLAG) at any output and one common diagnostic bit (COTW) for diagnosis over temperature (DOT). The diagnostic registers can be read via MSC interface. During the start-bit of a read out cycle the corresponding diagnostic register is cleared, nevertheless the status of the diagnostic register before the start-bit is send. Pull-down Diagnostic currents and Open Load OL can be switched off by configuration for OUT11...18; (CONREG3 and OUT1516). Each stage (OUT1...14, 17, 18) is controlled with a separate bit of the data frame (downstream channel). The control bit is non inverting, i.e. if a control bit is `1' the corresponding stage is off. Stages are disabled - i.e. switched off and switching on disabled if VDD is too low (VDD undervoltage or power on reset) or VDD too high (VDD overvoltage). The same applies when the MSC monitoring detects an error, micro controller reset is active (i.e. external signal on pin RST = low or external signal on Pin ABE is logical low level). All outputs are designed with internal zener diodes for applications with inductive loads. OUT1 and OUT3 are designed for normal operation with 4A and extended current of 8A for maximum of 200 seconds each vehicle driving cycle. OUT5...OUT10 are disabled by active low level on pins DIS5_10 (with short delay). OUT9 and OUT10 are designed for actuators with higher clamping energy. OUT15 and OUT16 can be forced OFF with the higher thresholds of DELAYIN (VDELAYIN_RES15_16_L and VDELAYIN_RES15_16_H) (see Figure 8). OUT15 and OUT16 can be configured to delayed reset behavior, in this case, the switching-off algorithm is delayed by internal filtering time (exception: power on reset (POR), RES15_16 and valid command frame to switch off stages is not delayed). Parallel connection of stages (OUT1...14, 17, 18) is possible as the control bits that switch on and off these stages are all transmitted in the same data frame. OUT15 and OUT16 are only allowed to be connected to each other and not to other stages (see Chapter 5.10). DELAYOUT is pulled active low to switch off external components by the lower thresholds of DELAYIN (VDELAYIN_L and VDELAYIN_H), ABE or VDD monitoring. Data Sheet 5 Rev. 1.1, 2012-07-31 TLE 8718 SA Overview tDIAG_OL & MUX n=1...10 tDIAG_SCB OFF/ON RD_DATA WR_RST OL n=1...4, 15...18 & OUTn_SCB SCB S Flip R Flop 1 tOUTn_OVSD tOUTn_OVSON SVBATT RES15_16 STATUS_SVBATT OUTn tDELAYIN_GLITCH_x Higher thresholds of DELAYIN DELAYIN_FIL RES15_16_STATUS 1 R 1 S Reset 0" V OUTn_B IAS OUTn_DIA1/2 OUTn_DIA1/2 MUX n=5...14 EXT_SCB n=11...18 OUTn_DIAC Reset OUTn Control Flipflop "Off" & & "On, no delay " OUTn_SCB OUTn_CONTROL OUTn_DIAC OUTn_DELAY "On, restart timeout " 1 & & "Keep State , restart timeout" tDELRES Discard 1 & Restart n=15, 16 DIS5_10 tDIS5_10 DIS5_10_STATUS n=5...10 TOUTn _OTSD MSC downstream D OUTPUT_STBY 1 R OUTn Control Flipflop OUTREG n=1...14, 17, 18 1 POR tPOR tRST RST MSC_MON (timeout) tMSC_MON ABE_IMPACT 1 STAUS_UV STATUS_OV & MUX See Block Diagramm V DD Monitoring" ABE_STATUS tFIL_OFF_DEL READ_DIAREG6 VDD<V DD_POR D DIAREG POR_FLAG 6.2 R ABE 1 & DELAYOUT DELAYIN_CONFx DELAYIN_FIL DELAYIN Lower thresholds Figure 1 Data Sheet tDELAYIN_GLITCH_x tDELAYIN_x 1 DELAYIN _STATUS Output _Stages _Function _Overview.vsd Output stages, functional schematic 6 Rev. 1.1, 2012-07-31 TLE 8718 SA Block Diagram 2 Block Diagram Logic VDD Power SIP SIN OUT1 8A/55V SI FCLN FCL Micro Second Channel FCLP OUT2 3A/55V OUT3 8A/55V OUT4 3A/55V OUT5 2.2A/55V OUT6 2.2A/55V SSY OUT7 2.2A/55V OUT8 SDO 2.2A/55V OUT9 2.2A/55V DIS5_10 OUT10 Enable 2.2A/55V OUT11 DELAYOUT 2.2A/55V DELAYIN/OUT DELAYIN OUT12 2.2A/55V OUT13 2.2A/55V OUT14 2.2A/55V OUT15 0.6A/55V RST SVBATT ABE OUT16 Reset 0.6A/55V OUT17 Battery Voltage Monitoring 0.6A/55V OUT18 0.6A/55V VDD Monitoring GNDABE PGND Slug Block_Diagram.vsd Figure 2 Data Sheet Block Diagram 7 Rev. 1.1, 2012-07-31 TLE 8718 SA Pin Configuration 3 Pin Configuration 3.1 Pin Assignment PGND (Slug) OUT1 OUT1 OUT5 OUT9 OUT13 OUT17 DELAYIN DELAYOUT DIS5_10 SVBATT ABE GNDABE VDD OUT15 OUT11 OUT7 OUT3 OUT3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 OUT2 OUT6 OUT10 OUT14 OUT18 FCL FCLN FCLP SI SIN SIP SSY SDO RST OUT16 OUT12 OUT8 OUT4 Pin_Config.vsd Figure 3 Data Sheet Pin Assignment 8 Rev. 1.1, 2012-07-31 TLE 8718 SA Pin Configuration 3.2 Pin Pin Definitions and Functions Symbol 1) Function 1, 2 OUT1 36 OUT2 17, 18 OUT32) 19 OUT4 3 OUT5 35 OUT6 16 OUT7 20 OUT8 4 OUT9 34 OUT10 15 OUT11 21 OUT12 5 OUT13 33 OUT14 14 OUT15 22 OUT16 6 OUT17 32 OUT18 9 DIS5_10 Disable pin for OUT5...OUT10 (low level disables OUT5...OUT10 after filtering time (tDIS5_10) has expired). The thresholds are defined in Chapter 7 (active low, internal pull-up) 7 DELAYIN DELAYIN input (internal pull-down, active low): Disable pin for DELAYOUT after the configurable filtering time (tDELAYIN) has expired and Reset pin for OUT15 and OUT16. The thresholds are defined in Chapter 7. 8 DELAYOUT Open drain output generating active low level if DELAYIN is low level (below VDELAYIN_L) and tDELYAIN has expired, input ABE disables stages or VDD monitoring has detected a supply voltage failure. See Chapter 7. 11 ABE Bidirectional pin (active low). Indicates VDD overvoltage and undervoltage condition by pulling ABE-pin low. If forced to low from externally all stages are turned off. 12 GNDABE Sense ground. Reference ground for VDD monitoring only. Connect this pin to ground. 13 VDD Supply voltage 5V 24 SDO MSC interface. Upstream data, open drain output 25 SSY MSC interface. Chip select and synchronization strobe. Drain Connection of Power stage. Short circuit proof Individually protected against overtemperature diagnostic functions control via MSC Clamping of the output voltage by zener diodes 26 SIP MSC interface. Downstream data positive for differential interface 27 SIN MSC interface. Downstream data negative for differential interface 28 SI MSC interface optional downstream data input for single ended interface 29 FCLP MSC interface. Clock positive for differential interface 30 FCLN MSC interface. Clock negative for differential interface 31 FCL MSC interface optional clock input for single ended interface Data Sheet 9 Rev. 1.1, 2012-07-31 TLE 8718 SA Pin Configuration Pin Symbol Function 23 RST Reset input (active low, internal pull-up). Shuts down all stages regardless of their input signals. Clears the fault registers and resets the MSC interface registers (partially). 10 SVBATT Sense Battery Voltage Monitoring Pin. Connect to VBAT. Used to activate factory test mode. See Chapter 6.4. Slug PGND Power Ground. Internally used as PGND. Analogue circuits except VDD-monitoring refer to PGND. Connect to Ground. 1) Pin1 and Pin2 have to be connected together without any parasitic resistor 2) Pin17 and Pin18 have to be connected together without any parasitic resistor in between. 3.3 Abbreviations Table 2 Abbreviations ABE "ABschaltung Endstufen" (switch off output stages) C Command bit CD Command data bit DC Dont care bit DOT Diagnosis overtemperature LVDS Low voltage differential signal MSC Micro Second Channel NCB Number of bits of the active phase of a command frame NDB Number of bits of the active phase of a data frame OL Open Load (diagnostic stage information) OTSD Over Temperature Shut Down (threshold to shut down stages for device self protection) OTW Over Temperature Warning (diagnostic information) POR Power On Reset, including filter time tPOR PS Power Stage(s) RST ReSeT input pin SCB Short Circuit to Battery (diagnostic stage information) SCG Short Circuit to Ground (diagnostic stage information) SSY Select / SYnc signal for MSC communication SB Selection bit TC Test coverage UD Upstream data bit Data Sheet 10 Rev. 1.1, 2012-07-31 TLE 8718 SA General Product Characteristics 4 General Product Characteristics 4.1 Test coverage (TC) in series production In the standard production flow not all parameters can be covered due to technical or economic reasons. Therefore the following test coverage classes are defined: A) Parameter test (parameter is measured in production test) B) Go/NoGo test (parameter within specified range is guaranteed by Go/NoGo-test in production) C) Specified by design (covered by lab tests, not considered within the standard production flow) The given supply voltage range is only valid as long as the related function is active. (e.g. the power stages are shut off if VBAT > 28V. In that case, no function is available to be tested at VBAT = 40V). 4.2 Absolute Maximum Ratings The integrated circuit will not be damaged if maximum ratings are reached. Every maximum rating is allowed to be reached at the same time, as long as no other maximum rating is exceeded. But see Item Note: Unless otherwise indicated all voltages are referred to PGND (all PGND and GNDABE are externally connected to each other) Positive current flows into the pin. Table 3 Maximum Ratings Tj = -40C to +150C, all voltages with respect to PGND, positive current flowing into pin, unless otherwise specified Pos. Parameter Symbol Values min. max. Unit TC Conditions Supply and Power Pins 4.2.1 Supply Voltage Range pin VDD, static VDD_MR -0.3 36 V C - 4.2.2 Battery Voltage stages output pins via load VBAT_MR -1 40 V C - 4.2.3 Total current over the PGND IPGND_MR dVGND_MR -38 38 A C - -0.3 0.3 V C - 4.2.5 Output Stages static voltage OUTn (n=1...18) VOUTn_MR -0.3 50 V C OUTn OFF 4.2.6 Short Circuit to VBAT (single event) VBAT_SC -0.3 36 V C OUTn (n=1...18), Figure 4 VSIP_MR, VSIN_MR, -0.3 VSI_MR, VFCLP_MR, VFCLN_MR, VFCL_MR, VSSY_MR, VDIS5_10_MR, VRST_MR VABE_MR -0.3 VDELAYOUT_MR, -0.3 VSDO_MR 36 V C - 36 V C - 36 V C - 4.2.4 Ground Voltage Offset maximum permissible offset between GNDABE and the PGND Interface and Logic 4.2.7 Logic Input Pins SIP, SIN, SI, FCLP, FCLN, FCL, SSY, DIS5_10, RST 4.2.8 Bidirectional Pin ABE 4.2.9 Output Pins DELAYOUT, SDO Data Sheet 11 Rev. 1.1, 2012-07-31 TLE 8718 SA General Product Characteristics Table 3 Maximum Ratings Tj = -40C to +150C, all voltages with respect to PGND, positive current flowing into pin, unless otherwise specified Pos. Parameter Symbol Values min. 4.2.10 Input Pins DELAYIN, SVBATT 4.2.11 Current into Pin SIP, SIN, SI, FCLP, FCLN, FCL, SSY, DIS5_10, RST, DELAYIN, SVBATT, SDO 4.2.12 Current into Pin DELAYOUT, ABE Unit TC Conditions max. VDELAYIN_MR, -0.3 VSVBATT_MR ISIP_MR, ISIN_MR, ISI_MR, -10 IFCLP_MR, IFCLN_MR, IFCL_MR, ISSY_MR, IDIS5_10_MR, IRST_MR, IDELAYIN_MR, ISVBATT_MR, ISDO_MR IDELAYOUT_MR, IABE_MR -10 40 V C - 10 mA C 1) 15 mA C 1) Tj TSTG -40 150 C C - -55 150 C C - Temperatures 4.2.13 Junction Temperature 4.2.14 Storage Temperature 1) Other maximum ratings (like Item 4.2.7 to Item 4.2.10 or Item 4.2.13) are not allowed to be exceeded. Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as "outside" normal operating range. Protection functions are not designed for continuous or repetitive operation. 5H 80m 0...5H 10m LBAT RHarness LHarness 20m RECU OUTn RBAT VBAT PGND Short_Circuit_test_setup.vsd Figure 4 Data Sheet Short Circuit test set-up 12 Rev. 1.1, 2012-07-31 TLE 8718 SA General Product Characteristics 4.3 Thermal Resistance Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go to www.jedec.org. Table 4 Thermal Resistance Tj = -40C to +150C, all voltages with respect to PGND, positive current flowing into pin, unless otherwise specified Pos. 4.3.1 Parameter Symbol Junction to Case Values RthJC RthJA Unit TC Conditions min. typ. max. - - 2 K/W C 1) Junction to Ambient - 25 - K/W C see Figure 5 1) 1) Power dissipation Pv=3W distributed statically and homogeneously over all power stages. Resistive Load. 4.3.2 Dimensions : 76.2 x 114.3 x 1.6 mm; Material: FR4 Thermal Vias: diameter = 0.3 mm; plating 25 m; 56 pcs. Metalization accodring : JEDEC 2s2p (JESD 51-7) + (JESD 51-5) 1.6 mm 70m modeled (traces) 35m, 90% metalization 35m, 90% metalization 70m, 5% metalization Thermal_Setup .vsd Figure 5 Data Sheet Thermal simulation - PCB setup 13 Rev. 1.1, 2012-07-31 TLE 8718 SA General Product Characteristics 4.4 ESD Of the various ESD models, the integrated circuit meets at least the "human body model" according to the requirements of the EIA/JESD22-A114-F. During manufacturing process, ESD pulses according to "charged device model" (EIA/JESD22-C101-D) may be exposed to each pin. ESD Specification Details in the following Table. Table 5 ESD Susceptibility Tj = -40C to +150C, all voltages with respect to PGND, positive current flowing into pin, unless otherwise specified Pos. Parameter Symbol Values Unit TC Conditions min. typ. max. Standard Requirements for all Pins 4.4.1 Electro Static Discharge Voltage "Human-Body-Model - HBM" VESD1 -2 - 2 kV C All Pins 4.4.2 Electro Static Discharge Voltage "Charged-Device-Model - CDM" VESD2 -500 - 500 V C All Pins Pins with Extended Requirements 4.4.3 Electro Static Discharge Voltage "Human-Body-Model - HBM" VESD3 -6 - 6 kV C OUT1...14 vs. PGND 4.4.4 Electro Static Discharge Voltage "Human-Body-Model - HBM" VESD4 -4 - 4 kV C OUT15...18 vs. PGND 4.5 Operating Range Table 6 Operating Range Tj = -40C to +150C, all voltages with respect to PGND, positive current flowing into pin, unless otherwise specified Pos. Parameter Symbol Values Unit TC Conditions V C - 13.5 V C - 0 A C 1) min. max. 4.5 5.5 Supply, Battery Voltage 4.5.1 Supply Voltage Range 4.5.2 Battery Voltage 4.5.3 Nominal Total PGND Current VDD VBAT(typ) IPGND(typ) -12 1) Total PGND current influences e.g. the RON-measurement of the Power Stages or voltage thresholds of the input buffers because of common PGND bond wires. As basis for definition of the RON or the voltage thresholds, the defined PGND current is used. Data Sheet 14 Rev. 1.1, 2012-07-31 TLE 8718 SA Power Stages 5 Power Stages 5.1 Functional Description The following general description is valid for the channel groups OUT1,3, OUT2,4, OUT5...8, OUT9,10, OUT11...14, OUT17,18. The specific function of the channel group OUT15,16 is described in Chapter 5.7. The reset input of the OUTn-control flip-flop is active high and dominant, delivering a logic low level at the output of the OUTn-control flip-flop.Only in failure-free condition, output can be switched on by MSC downstream. Disabling inputs DIS5_10 and DELAYIN have different input characteristics and delay (tDELAYIN >> tDIS5_10). For details concerning DIS5_10, DELAYIN and DELAYOUT see Chapter 7 and Figure 1. 5.2 Power Stages OUT1 and OUT3 Table 7 Electrical Characteristics Power Stages OUT1 and OUT3 n = 1 and 3, all channels ON or OFF, nominal load conditions, 4.5V < VDD < 5.5V, 4.5V < VBAT < 40V, all voltages with respect to PGND, positive current flowing into pin. Tj = -40C to +150C, unless otherwise specified Pos. Parameter Symbol Values Unit TC Conditions min. typ. max. IOUTn IOUTn_ex tOUTn_ec - - 4 A C - - 8 A C max 800h - - 60 h C VBAT14V, RL0.88 IOUTn_max 8 - 12.5 A A Ron-40_n Ron+25_n Ron+150_n Ron_n - - 120 m C - - 148 m C - - 200 m A - - 210 m C Ron-40_n Ron+25_n Ron+150_n Ron_n - - 156 m C - - 193 m C - - 260 m A - - 273 m C 5.2.13 Switch on delay tdon_n - - 15 s C 5.2.14 Switch off delay tdoff_n - - 15 s C 5.2.15 Difference of switch on and off delay tdif_n=tdon_n-tdoff_n tdif_n -8 - 8 s C 5.2.16 Switch on slew rates son_n 0.5 1 2.5 V/s C Load Current 5.2.1 Continuous Load Current 5.2.2 Extended Load Current 5.2.3 Extended current time, Accumulated operating time 5.2.4 Maximum current, (short circuit limited current / switch off threshold) ON-Resistance without clamping 1) 5.2.5 On Resistance Tj=-40C 5.2.6 On Resistance Tj=25C 5.2.7 On Resistance Tj=150C 5.2.8 On Resistance Tj150C ON-Resistance with clamping 5.2.9 IOUTn=4A IOUTn=4A IOUTn=4A IOUTn<8A 2) On Resistance Tj=-40C 5.2.10 On Resistance Tj=25C 5.2.11 On Resistance Tj=150C 5.2.12 On Resistance Tj150C IOUTn=4A IOUTn=4A IOUTn=4A IOUTn<8A Delay times, Slew rates (see Figure 6) Data Sheet 15 RLoad=5.9, VBAT=14V RLoad=5.9, VBAT=14V RLoad=5.9, VBAT=14V RLoad=5.9, VBAT=14V Rev. 1.1, 2012-07-31 TLE 8718 SA Power Stages Table 7 Electrical Characteristics Power Stages OUT1 and OUT3 n = 1 and 3, all channels ON or OFF, nominal load conditions, 4.5V < VDD < 5.5V, 4.5V < VBAT < 40V, all voltages with respect to PGND, positive current flowing into pin. Tj = -40C to +150C, unless otherwise specified Pos. Parameter Symbol Values Unit TC Conditions min. typ. max. soff_n 0.5 1 2.5 V/s C RLoad=5.9, VBAT=14V 5.2.18 Leakage current of the Output Stage Il_OUTn - - 5 A C 5.2.19 Leakage current of the Output Stage Il_OUTn - - 10 A C 5.2.20 Leakage current of the Output Stage Il_OUTn - - 30 A A VOUTn=14V, VDD=0V, Tj=60C VOUTn=28V, VDD=0V, Tj=60C VOUTn<28V, VDD=0V, Tj=150C VCL_n VCL_n 50 - 60 V C 50 - 60 V A 5.2.23 Standard operating range, max. 1000Mio ECL_OUTn cycles - - 25 mJ C 5.2.24 Jump Start, max. 0.01Mio cycles ECL_OUTn - - 27 mJ C 5.2.25 Load Dump, max. 10 pulses ECL_OUTn - - 90 mJ C 5.2.26 Load Dump, max. 10 pulses ECL_OUTn - - 26 mJ C - - A C - - A C - - A C 5.2.17 Switch off slew rates Leakage current Clamping voltage 5.2.21 Clamping voltage 5.2.22 Clamping voltage IOUTn=3A IOUTn=0.2A Clamping energy 3) Tj(0)=125C, IOUTn(0)<2.8A Tj(0)=85C, IOUTn(0)<5.6A Tj(0)=35C, IOUTn(0)<8A Tj(0)=150C, IOUTn(0)<8A Reverse current through OUTn IR_S_OUTn -3 5.2.28 Without supply voltage, possibly Leakage IR_Soff_OUTn -3 5.2.27 In operation mode, static, no destruction Tj=150C,VDD=5V VDD<1V Current out of neighbor channels. 10ms after the reverse current disappears leakage current criteria are kept. IR_S_OUTn 5.2.29 In operation mode, No unwanted switching of channels; No unwanted Reset, No unwanted change of Voltage Monitoring Thresholds; No unwanted communication errors or register changes beside diagnostic registers. Possibly unwanted diagnostic entries. Possibly Leakage Current out of neighbor channels. -1.5 Tj=150C, VDD=5V 1) Item 5.2.5 to Item 5.2.8 has to be considered for applications with resistive load or inductive load with external freewheeling. 2) Item 5.2.9 to Item 5.2.12 has to be considered for applications where clamping occurs. 3) Clamping energy, Linear decreasing current, fcl<67Hz. Data Sheet 16 Rev. 1.1, 2012-07-31 TLE 8718 SA Power Stages 5.3 Power Stages OUT2 and OUT4 Table 8 Electrical Characteristics Power Stages OUT2 and OUT4 n = 2 and 4, all channels ON or OFF, nominal load conditions, 4.5V < VDD < 5.5V, 4.5V < VBAT < 40V, all voltages with respect to PGND, positive current flowing into pin., Tj = -40C to +150C, unless otherwise specified Pos. Parameter Symbol Values Unit TC Conditions min. typ. max. IOUTn tOUTn_ec - - 3 A C - - 100 h C IOUTn_max 3 - 6 A A Ron-40_n Ron+25_n Ron_n - - 210 m C - - 259 m C - - 350 m A Ron-40_n Ron+25_n Ron_n - - 273 m C - - 337 m C - - 455 m A 5.3.10 Switch on delay tdon_n - - 15 s C 5.3.11 Switch off delay tdoff_n - - 15 s C 5.3.12 Difference of switch on and off delay tdif_n=tdon_n-tdoff_n tdif_n -5 - 5 s C 5.3.13 Switch on slew rates son_n 1.1 2.5 5.8 V/s C 5.3.14 Switch off slew rates soff_n 1.1 2.5 5.8 V/s C 5.3.15 Leakage current of the Output Stage Il_OUTn - - 5 A C 5.3.16 Leakage current of the Output Stage Il_OUTn - - 10 A C 5.3.17 Leakage current of the Output Stage Il_OUTn - - 30 A A VCL_n VCL_n 50 - 60 V C 50 - 60 V A Load Current 5.3.1 Continuous Load Current 5.3.2 Extended Current time Accumulated Operating time 5.3.3 Maximum Current, (short circuit limited current / switch off threshold) VBAT14V, RL1.98 ON-Resistance without clamping 1) 5.3.4 On Resistance Tj=-40C 5.3.5 On Resistance Tj=25C 5.3.6 On Resistance Tj150C ON-Resistance with clamping IOUTn=3A IOUTn=3A IOUTn=3A 2) 5.3.7 On Resistance Tj=-40C 5.3.8 On Resistance Tj=25C 5.3.9 On Resistance Tj150C IOUTn=3A IOUTn=3A IOUTn=3A Delay times, Slew rates (see Figure 6) RLoad=5.9, VBAT=14V RLoad=5.9, VBAT=14V RLoad=5.9, VBAT=14V RLoad=5.9, VBAT=14V RLoad=5.9, VBAT=14V Leakage current VOUTn=14V, VDD=0V, Tj=60C VOUTn=28V, VDD=0V, Tj=60C VOUTn<28V, VDD=0V, Tj=150C Clamping voltage 5.3.18 Clamping voltage 5.3.19 Clamping voltage Data Sheet 17 IOUTn=3A IOUTn=0.2A Rev. 1.1, 2012-07-31 TLE 8718 SA Power Stages Table 8 Electrical Characteristics Power Stages OUT2 and OUT4 n = 2 and 4, all channels ON or OFF, nominal load conditions, 4.5V < VDD < 5.5V, 4.5V < VBAT < 40V, all voltages with respect to PGND, positive current flowing into pin., Tj = -40C to +150C, unless otherwise specified Pos. Parameter Symbol Values Unit TC Conditions min. typ. max. 5.3.20 Standard operating range, max. 1000Mio ECL_OUTn cycles - - 22 mJ C 5.3.21 Jump Start, max. 0.01Mio cycles ECL_OUTn - - 18 mJ C 5.3.22 Load Dump, max. 10 pulses ECL_OUTn - - 76 mJ C 5.3.23 Load Dump, max. 10 pulses ECL_OUTn - - 19 mJ C - - A C - - A C - - A C Clamping energy 3) Tj(0)=125C, IOUTn(0)<1.05A Tj(0)=85C, IOUTn(0)<2.1A Tj(0)=35C, IOUTn(0)<3A Tj(0)=150C, IOUTn(0)<3A Reverse current through OUTn IR_S_OUTn -3 5.3.25 Without supply voltage, possibly Leakage IR_Soff_OUTn -3 5.3.24 In operation mode, static, no destruction Tj=150C,VDD=5V VDD<1V Current out of neighbor channels. 10ms after the reverse current disappears leakage current criteria are kept. 5.3.26 In operation mode, No unwanted IR_S_OUTn switching of channels; No unwanted Reset, No unwanted change of Voltage Monitoring Thresholds; No unwanted communication errors or register changes beside diagnostic registers. Possibly unwanted diagnostic entries. Possibly Leakage Current out of neighbor channels. -1.1 Tj=150C, VDD=5V 1) Item 5.3.4 to Item 5.3.6 has to be considered for applications with resistive load or inductive load with external freewheeling. 2) Item 5.3.7 to Item 5.3.9 has to be considered for applications where clamping occurs. 3) Clamping energy, Linear decreasing current, fcl<67Hz. Data Sheet 18 Rev. 1.1, 2012-07-31 TLE 8718 SA Power Stages 5.4 Power Stages OUT5...OUT8 Table 9 Electrical Characteristics Power Stages OUT5...OUT8 n = 5...8, all channels ON or OFF, nominal load conditions, 4.5V < VDD < 5.5V, 4.5V < VBAT < 40V, all voltages with respect to PGND, positive current flowing into pin., Tj = -40C to +150C, unless otherwise specified Pos. Parameter Symbol Values Unit TC Conditions min. typ. max. IOUTn tOUTn_ec - - 2.2 A C - - - 100 h C VBAT14V, RL2.78 IOUTn_max 2.2 - 4 A A - Ron-40_n Ron+25_n Ron_n - - 432 m C - - 533 m C - - 720 m A IOUTn=2.2A IOUTn=2.2A IOUTn=2.2A Load Current 5.4.1 Continuous Load Current 5.4.2 Extended current time, Accumulated operating time 5.4.3 Maximum current, (short circuit limited current / switch off threshold) ON-Resistance 5.4.4 On-resistance Tj=-40C 5.4.5 On-resistance Tj=25C 5.4.6 On-resistance Tj150C Delay times, Slew rates (see Figure 6) 5.4.7 Switch on delay tdon_n - - 10 s C 5.4.8 Switch off delay tdoff_n - - 10 s C Difference of switch on and off delay tdif_n -5 - 5 s C 5.4.10 Switch on slew rates Son_n 1.5 3.1 7.5 V/s C 5.4.11 Switch off slew rates Soff_n 1.5 3.1 7.5 V/s C 5.4.12 Leakage current of the Output Stage Il_OUTn - - 5 A C 5.4.13 Leakage current of the Output Stage Il_OUTn - - 10 A C 5.4.14 Leakage current of the Output Stage Il_OUTn - - 20 A A VCL_n VCL_n VCL_dif_n 50 - 60 V C 50 - 60 V A -3 - 3 V A ECL_OUTn - - 7.5 mJ C 5.4.9 tdif_n=tdon_n-tdoff_n RLoad=7.68, VBAT=14V RLoad=7.68, VBAT=14V RLoad=7.68, VBAT=14V RLoad=7.68, VBAT=14V RLoad=7.68, VBAT=14V Leakage current VOUTn=14V, VDD=0V, Tj=60C VOUTn=28V, VDD=0V, Tj=60C VOUTn<28V, VDD=0V, Tj=150C Clamping voltage 5.4.15 Clamping voltage 5.4.16 Clamping voltage 5.4.17 Clamping voltage, difference between outputs. OUTn with identical inductive loads IOUTn=2.2A IOUTn=0.2A IOUTn=0.2A Clamping energy 1) 5.4.18 Standard operating range, max. 18Mio cycles Data Sheet 19 Tj(0)=35C, IOUTn(0)<1.8A Rev. 1.1, 2012-07-31 TLE 8718 SA Power Stages Table 9 Electrical Characteristics Power Stages OUT5...OUT8 n = 5...8, all channels ON or OFF, nominal load conditions, 4.5V < VDD < 5.5V, 4.5V < VBAT < 40V, all voltages with respect to PGND, positive current flowing into pin., Tj = -40C to +150C, unless otherwise specified Pos. Parameter Symbol Values min. typ. max. Unit TC Conditions 5.4.19 Standard operating range, max. 648Mio cycles ECL_OUTn - - 4 mJ C 5.4.20 Standard operating range, max. 96Mio cycles ECL_OUTn - - 3 mJ C 5.4.21 Standard operating range, max. 4Mio cycles ECL_OUTn - - 3 mJ C 5.4.22 Generator defect, max. 0.5Mio cycles, or Item 5.4.23 ECL_OUTn - - 9 mJ C 5.4.23 Generator defect, max. 0.5Mio cycles ECL_OUTn - - 5 mJ C 5.4.24 Jump start, max. 0.021Mio cycles, or Item 5.4.25 ECL_OUTn - - 17.5 mJ C 5.4.25 Jump start, max. 0.021Mio cycles ECL_OUTn - - 10 mJ C 5.4.26 Load dump, max. 10 pulses, or Item 5.4.27 ECL_OUTn - - 35 mJ C 5.4.27 Load dump, max. 10 pulses ECL_OUTn - - 20 mJ C 5.4.28 Load dump, max. 10 pulses, or Item 5.4.29 ECL_OUTn - - 21 mJ C 5.4.29 Load dump, max. 10 pulses ECL_OUTn - - 18 mJ C - - A C - - A C - - A C Tj(0)=125C, IOUTn(0)<1.4A Tj(0)=140C, IOUTn(0)<1A Tj(0)=150C, IOUTn(0)<1A Tj(0)=35C, IOUTn(0)<2A Tj(0)=145C, IOUTn(0)<1.5A Tj(0)=35C, IOUTn(0)<3A2) Tj(0)=85C, IOUTn(0)<2.3A2) Tj(0)=85C, IOUTn(0)<2.1A Tj(0)=145C, IOUTn(0)<2.1A Tj(0)=85C, IOUTn(0)<3.3A2) Tj(0)=145C, IOUTn(0)<2.4A2) Reverse current through OUTn IR_S_OUTn -2.2 5.4.31 Without supply voltage, possibly Leakage IR_Soff_OUTn -2.2 5.4.30 In operation mode, static, no destruction Tj=150C,VDD=5V VDD<1V Current out of neighbor channels. 10ms after the reverse current disappears leakage current criteria are kept. 5.4.32 In operation mode, No unwanted IR_S_OUTn switching of channels; No unwanted Reset, No unwanted change of Voltage Monitoring Thresholds; No unwanted communication errors or register changes beside diagnostic registers. Possibly unwanted diagnostic entries. Possibly Leakage Current out of neighbor channels. -1 Tj=150C, VDD=5V 1) Clamping energy, Linear decreasing current, fcl<67Hz. 2) PS might switch off to limit the current before reaching the given IOUTn due to reaching IOUTn_max. Data Sheet 20 Rev. 1.1, 2012-07-31 TLE 8718 SA Power Stages 5.5 Power Stages OUT9 and OUT10 Table 10 Electrical Characteristics Power Stages OUT9 and OUT10 n = 9 and 10, all channels ON or OFF, nominal load conditions, 4.5V < VDD < 5.5V, 4.5V < VBAT < 40V, all voltages with respect to PGND, positive current flowing into pin., Tj = -40C to +150C, unless otherwise specified Pos. Parameter Symbol Values Unit TC Conditions min. typ. max. IOUTn tOUTn_ec - - 2.2 A C - - - 100 h C VBAT14V, RL2.78 IOUTn_max 2.2 - 4 A A - Ron-40_n Ron+25_n Ron_n - - 282 m C - - 348 m C - - 470 m A IOUTn=2.2A IOUTn=2.2A IOUTn=2.2A Load Current 5.5.1 Continuous Load Current 5.5.2 Extended current time, Accumulated operating time 5.5.3 Maximum current, (short circuit limited current / switch off threshold) ON-Resistance 5.5.4 On-resistance Tj=-40C 5.5.5 On-resistance Tj=25C 5.5.6 On-resistance Tj150C Delay times, Slew rates (see Figure 6) 5.5.7 Switch on delay tdon_n - - 10 s C 5.5.8 Switch off delay tdoff_n - - 10 s C Difference of switch on and off delay tdif_n -5 - 5 s C 5.5.10 Switch on slew rates Son_n 1.5 3.1 7.5 V/s C 5.5.11 Switch off slew rates Soff_n 1.5 3.1 7.5 V/s C 5.5.12 Leakage current of the Output Stage Il_OUTn - - 5 A C 5.5.13 Leakage current of the Output Stage Il_OUTn - - 10 A C 5.5.14 Leakage current of the Output Stage Il_OUTn - - 20 A A VCL_n VCL_n VCL_dif_n 50 - 60 V C 50 - 60 V A -3 - 3 V A ECL_OUTn - - 25 mJ C 5.5.9 tdif_n=tdon_n-tdoff_n RLoad=7.68, VBAT=14V RLoad=7.68, VBAT=14V RLoad=7.68, VBAT=14V RLoad=7.68, VBAT=14V RLoad=7.68, VBAT=14V Leakage current VOUTn=14V, VDD=0V, Tj=60C VOUTn=28V, VDD=0V, Tj=60C VOUTn<28V, VDD=0V, Tj=150C Clamping voltage 5.5.15 Clamping voltage 5.5.16 Clamping voltage 5.5.17 Clamping voltage, difference between outputs. OUTn with identical inductive loads IOUTn=2.2A IOUTn=0.2A IOUTn=0.2A Clamping energy 1) 5.5.18 Standard operating range, max. 18Mio cycles Data Sheet 21 Tj(0)=35C, IOUTn(0)<1.5A Rev. 1.1, 2012-07-31 TLE 8718 SA Power Stages Table 10 Electrical Characteristics Power Stages OUT9 and OUT10 n = 9 and 10, all channels ON or OFF, nominal load conditions, 4.5V < VDD < 5.5V, 4.5V < VBAT < 40V, all voltages with respect to PGND, positive current flowing into pin., Tj = -40C to +150C, unless otherwise specified Pos. Parameter Symbol Values min. typ. max. Unit TC Conditions 5.5.19 Standard operating range, max. 648Mio cycles ECL_OUTn - - 18 mJ C 5.5.20 Standard operating range, max. 96Mio cycles ECL_OUTn - - 15 mJ C 5.5.21 Standard operating range, max. 4Mio cycles ECL_OUTn - - 15 mJ C 5.5.22 Generator defect, max. 0.5Mio cycles; or Item 5.5.23 ECL_OUTn - - 28 mJ C 5.5.23 Generator defect, max. 0.5Mio cycles ECL_OUTn - - 16 mJ C 5.5.24 Jump start, max. 0.021Mio cycles, or Item 5.5.25 ECL_OUTn - - 50 mJ C 5.5.25 Jump start, max. 0.021Mio cycles ECL_OUTn - - 30 mJ C 5.5.26 Load dump, max. 10 pulses, or Item 5.5.27 ECL_OUTn - - 120 mJ C 5.5.27 Load dump, max. 10 pulses ECL_OUTn - - 55 mJ C 5.5.28 Load dump, max. 10 pulses, or Item 5.5.29 ECL_OUTn - - 80 mJ C 5.5.29 Load dump, max. 10 pulses ECL_OUTn - - 51 mJ C - - A C - - A C - - A C Tj(0)=125C, IOUTn(0)<1.2A Tj(0)=140C, IOUTn(0)<1A Tj(0)=150C, IOUTn(0)<1A Tj(0)=35C, IOUTn(0)<1.6A Tj(0)=145C, IOUTn(0)<1.1A Tj(0)=35C, IOUTn(0)<2.2A Tj(0)=85C, IOUTn(0)<1.8A Tj(0)=35C, IOUTn(0)<2.4A2) Tj(0)=145C, IOUTn(0)<1.8A Tj(0)=35C, IOUTn(0)<3.5A2) Tj(0)=145C, IOUTn(0)<2A Reverse current through OUTn IR_S_OUTn -2.2 5.5.31 Without supply voltage, possibly Leakage IR_Soff_OUTn -2.2 5.5.30 In operation mode, static, no destruction Tj=150C,VDD=5V VDD<1V Current out of neighbor channels. 10ms after the reverse current disappears leakage current criteria are kept. 5.5.32 In operation mode, No unwanted IR_S_OUTn switching of channels; No unwanted Reset, No unwanted change of Voltage Monitoring Thresholds; No unwanted communication errors or register changes beside diagnostic registers. Possibly unwanted diagnostic entries. Possibly Leakage Current out of neighbor channels. -1 Tj=150C, VDD=5V 1) Clamping energy, Linear decreasing current, fcl<67Hz. 2) PS might switch off to limit the current before reaching the given IOUTn due to reaching IOUTn_max. Data Sheet 22 Rev. 1.1, 2012-07-31 TLE 8718 SA Power Stages 5.6 Power Stages OUT11...OUT14 Table 11 Electrical Characteristics Power Stages OUT11...OUT14 n = 11...14, all channels ON or OFF, nominal load conditions, 4.5V < VDD < 5.5V, 4.5V < VBAT < 40V, all voltages with respect to PGND, positive current flowing into pin., Tj = -40C to +150C, unless otherwise specified Pos. Parameter Symbol Values Unit TC Conditions min. typ. max. IOUTn tOUTn_ec - - 2.2 A C - - - 100 h C VBAT14V, RL2.78 IOUTn_max 2.2 - 4 A A - Ron-40_n Ron+25_n Ron_n - - 432 m C - - 533 m C - - 720 m A IOUTn=2.2A IOUTn=2.2A IOUTn=2.2A Load Current 5.6.1 Continuous Load Current 5.6.2 Extended current time, Accumulated operating time 5.6.3 Maximum current, (short circuit limited current / switch off threshold) ON-Resistance 5.6.4 On-resistance Tj=-40C 5.6.5 On-resistance Tj=25C 5.6.6 On-resistance Tj150C Delay times, Slew rates (see Figure 6) 5.6.7 Switch on delay tdon_n - - 10 s C RLoad=7.68, VBAT=14V 5.6.8 Switch off delay tdoff_n - - 10 s C RLoad=7.68, VBAT=14V 5.6.9 Difference of switch on and off delay tdif_n=tdon_n-tdoff_n tdif_n -5 - 5 s C 5.6.10 Switch on slew rates son_n 1.5 3.1 7.5 V/s C 5.6.11 Switch off slew rates soff_n 1.5 3.1 7.5 V/s C RLoad=7.68, VBAT=14V RLoad=7.68, VBAT=14V RLoad=7.68, VBAT=14V 5.6.12 Leakage current of the Output Stage Il_OUTn - - 5 A C 5.6.13 Leakage current of the Output Stage Il_OUTn - - 20 A C Leakage current VOUTn=14V, VDD=0V, Tj=60C VOUTn=14V, VDD=5V (diagnosis current off, CONREG3), Tj=60C 5.6.14 Leakage current of the Output Stage Il_OUTn - - 10 A C 5.6.15 Leakage current of the Output Stage Il_OUTn - - 25 A C VOUTn=28V, VDD=0V, Tj=60C VOUTn=28V, VDD=5V (diagnosis current off, CONREG3), Tj=60C 5.6.16 Leakage current of the Output Stage Data Sheet Il_OUTn 23 - - 20 A A VOUTn<28V, VDD=0V, Tj=150C Rev. 1.1, 2012-07-31 TLE 8718 SA Power Stages Table 11 Electrical Characteristics Power Stages OUT11...OUT14 n = 11...14, all channels ON or OFF, nominal load conditions, 4.5V < VDD < 5.5V, 4.5V < VBAT < 40V, all voltages with respect to PGND, positive current flowing into pin., Tj = -40C to +150C, unless otherwise specified Pos. Parameter Symbol 5.6.17 Leakage current of the Output Stage Il_OUTn Values min. typ. max. - - 35 Unit TC Conditions A A VOUTn<28V, VDD=5V (diagnosis current off, CONREG3), Tj=150C Clamping voltage VCL_n VCL_n 50 - 60 V C 50 - 60 V A 5.6.20 Standard operating range, max. 18Mio cycles ECL_OUTn - - 18 mJ C 5.6.21 Standard operating range, max. 520Mio cycles ECL_OUTn - - 9 mJ C 5.6.22 Standard operating range, max. 120Mio cycles ECL_OUTn - - 7 mJ C 5.6.23 Standard operating range, max. 13Mio cycles ECL_OUTn - - 7 mJ C 5.6.24 Generator defect, max. 0.25Mio cycles or ECL_OUTn Item 5.6.25 - - 23 mJ C 5.6.25 Generator defect, max. 0.25Mio cycles ECL_OUTn - - 11 mJ C 5.6.26 Jump start, max. 0.02Mio cycles, or Item 5.6.27 ECL_OUTn - - 35 mJ C 5.6.27 Jump start, max. 0.02Mio cycles ECL_OUTn - - 17 mJ C 5.6.28 Load dump, max. 10 pulses, or Item 5.6.29 ECL_OUTn - - 50 mJ C 5.6.29 Load dump, max. 10 pulses ECL_OUTn - - 30 mJ C 5.6.30 Load dump, max. 10 pulses, or Item 5.6.31 ECL_OUTn - - 33 mJ C 5.6.31 Load dump, max. 10 pulses ECL_OUTn - - 18 mJ C 5.6.18 Clamping voltage 5.6.19 Clamping voltage Clamping energy Data Sheet IOUTn=2.2A IOUTn=0.2A 1) 24 Tj(0)=35C, IOUTn(0)<1.5A Tj(0)=125C, IOUTn(0)<1.2A Tj(0)=140C, IOUTn(0)<1A Tj(0)=150C, IOUTn(0)<1A Tj(0)=35C, IOUTn(0)<1.6A Tj(0)=145C, IOUTn(0)<1.1A Tj(0)=35C, IOUTn(0)<2.2A Tj(0)=85C, IOUTn(0)<1.8A Tj(0)=35C, IOUTn(0)<2.32) Tj(0)=145C, IOUTn(0)<1.3A Tj(0)=35C, IOUTn(0)<3.5A2) Tj(0)=145C, IOUTn(0)<2A Rev. 1.1, 2012-07-31 TLE 8718 SA Power Stages Table 11 Electrical Characteristics Power Stages OUT11...OUT14 n = 11...14, all channels ON or OFF, nominal load conditions, 4.5V < VDD < 5.5V, 4.5V < VBAT < 40V, all voltages with respect to PGND, positive current flowing into pin., Tj = -40C to +150C, unless otherwise specified Pos. Parameter Symbol Values min. Unit TC Conditions typ. max. Reverse current through OUTn IR_S_OUTn -2.2 5.6.33 Without supply voltage, possibly Leakage IR_Soff_OUTn -2.2 5.6.32 In operation mode, static, no destruction - - A C - - A C - - A C Tj=150C,VDD=5V VDD<1V Current out of neighbor channels. 10ms after the reverse current disappears leakage current criteria are kept. IR_S_OUTn 5.6.34 In operation mode, No unwanted switching of channels; No unwanted Reset, No unwanted change of Voltage Monitoring Thresholds; No unwanted communication errors or register changes beside diagnostic registers. Possibly unwanted diagnostic entries. Possibly Leakage Current out of neighbor channels. -1 Tj=150C, VDD=5V 1) Clamping energy, Linear decreasing current, fcl<50Hz 2) PS might switch off to limit the current before reaching the given IOUTn due to reaching IOUTn_max. Data Sheet 25 Rev. 1.1, 2012-07-31 TLE 8718 SA Power Stages 5.7 Power Stages OUT15 and OUT16 Table 12 Electrical Characteristics Power Stages OUT15 and OUT16 n = 15 and 16, all channels ON or OFF, nominal load conditions, 4.5V < VDD < 5.5V, 4.5V < VBAT < 40V, all voltages with respect to PGND, positive current flowing into pin., Tj = -40C to +150C, unless otherwise specified Pos. Parameter Symbol Values Unit TC Conditions min. typ. max. IOUTn tOUTn_ec - - 0.6 A C - - - 100 h C VBAT14V, RL6.93 IOUTn_max 0.6 - 1.5 A C - Load Current 5.7.1 Continuous Load Current 5.7.2 Extended current time, Accumulated operating time. 5.7.3 Maximum current (short circuit limited current / switch off threshold). ON-Resistance 5.7.4 On-resistance Tj=-40C Ron-40_n - - 1440 m C 3.5V<VDD<5.5V, IOUTn=0.6A 5.7.5 On-resistance Tj=25C Ron+25_n - - 1780 m C 3.5V<VDD<5.5V, IOUTn=0.6A 5.7.6 On-resistance Tj150C Ron_n - - 2400 m A 3.5V<VDD<5.5V, IOUTn=0.6A RLoad=28.7, VBAT=14V RLoad=28.7, VBAT=14V RLoad=28.7, VBAT=14V RLoad=28.7, VBAT=14V RLoad=28.7, VBAT=14V Delay times, Slew rates (see Figure 6) 5.7.7 Switch on delay tdon_n - - 15 s C 5.7.8 Switch off delay tdoff_n - - 15 s C Difference of switch on and off delay tdif_n -5 - 5 s C 5.7.10 Switch on slew rates son_n 1.5 3.1 7.5 V/s C 5.7.11 Switch off slew rates soff_n 1.5 3.1 7.5 V/s C 5.7.12 Leakage current of the Output Stage Il_OUTn - - 5 A C 5.7.13 Leakage current of the Output Stage Il_OUTn - - 15 A C 5.7.14 Leakage current of the Output Stage Il_OUTn - - 35 A A 5.7.9 tdif_n=tdon_n-tdoff_n Leakage current VOUTn=14V, VDD=0V, Tj=60C VOUTn=28V, VDD=0V, Tj=60C VOUTn<28V, VDD=5V (diagnosis current off, OUT1516), Tj=150C Clamping voltage 5.7.15 Clamping voltage 5.7.16 Clamping voltage Data Sheet VCL_n VCL_n 26 50 - 60 V C 50 - 60 V A IOUTn=0.6A IOUTn=0.2A Rev. 1.1, 2012-07-31 TLE 8718 SA Power Stages Table 12 Electrical Characteristics Power Stages OUT15 and OUT16 n = 15 and 16, all channels ON or OFF, nominal load conditions, 4.5V < VDD < 5.5V, 4.5V < VBAT < 40V, all voltages with respect to PGND, positive current flowing into pin., Tj = -40C to +150C, unless otherwise specified Pos. Parameter Clamping energy Symbol Values min. typ. max. Unit TC Conditions 1) 5.7.17 Standard operating range, max. 1.1Mio cycles ECL_OUTn - - 9 mJ C 5.7.18 Standard operating range, max. 40Mio cycles ECL_OUTn - - 6.5 mJ C 5.7.19 Standard operating range, max. 9Mio cycles ECL_OUTn - - 6.5 mJ C 5.7.20 Standard operating range, max. 1Mio cycles ECL_OUTn - - 6.5 mJ C 5.7.21 Generator defect, max. 0.02Mio cycles, or ECL_OUTn Item 5.7.22 - - 11 mJ C 5.7.22 Generator defect, max. 0.02Mio cycles ECL_OUTn - - 8 mJ C 5.7.23 Jump start, max. 0.001Mio cycles, or Item 5.7.24 ECL_OUTn - - 25 mJ C 5.7.24 Jump start, max. 0.001Mio cycles ECL_OUTn - - 17 mJ C 5.7.25 Load dump, max. 10 pulses, or Item 5.7.26 ECL_OUTn - - 50 mJ C 5.7.26 Load dump, max. 10 pulses ECL_OUTn - - 30 mJ C 5.7.27 Load dump, max. 10 pulses, or Item 5.7.28 ECL_OUTn - - 34 mJ C 5.7.28 Load dump, max. 10 pulses ECL_OUTn - - 18 mJ C - - A C - - A C - - A C Tj(0)=35C, IOUTn(0)<0.45A Tj(0)=125C, IOUTn(0)<0.3A Tj(0)=140C, IOUTn(0)<0.3A Tj(0)=150C, IOUTn(0)<0.3A Tj(0)=35C, IOUTn(0)<0.5A Tj(0)=145C, IOUTn(0)<0.35A Tj(0)=35C, IOUTn(0)<0.75A2) Tj(0)=85C, IOUTn(0)<0.5A Tj(0)=35C, IOUTn(0)<0.8A2) Tj(0)=145C, IOUTn(0)<0.4A Tj(0)=35C, IOUTn(0)<1A2) Tj(0)=145C, IOUTn(0)<0.6A Reverse current through OUTn IR_S_OUTn -0.6 5.7.30 Without supply voltage, possibly Leakage IR_Soff_OUTn -0.6 5.7.29 In operation mode, static, no destruction Tj=150C,VDD=5V VDD<1V Current out of neighbor channels. 10ms after the reverse current disappears leakage current criteria are kept. IR_S_OUTn 5.7.31 In operation mode, No unwanted switching of channels; No unwanted Reset, No unwanted change of Voltage Monitoring Thresholds; No unwanted communication errors or register changes beside diagnostic registers. Possibly unwanted diagnostic entries. Possibly Leakage Current out of neighbor channels. -0.2 Tj=150C, VDD=5V 1) Clamping energy, Linear decreasing current, fcl<50Hz 2) PS might switch off to limit the current before reaching the given IOUTn due to reaching IOUTn_max. Data Sheet 27 Rev. 1.1, 2012-07-31 TLE 8718 SA Power Stages 5.8 Power Stages OUT17 and OUT18 Table 13 Electrical Characteristics Power Stages OUT17 and OUT18 n = 17 and 18, all channels ON or OFF, nominal load conditions, 4.5V < VDD < 5.5V, 4.5V < VBAT < 40V, all voltages with respect to PGND, positive current flowing into pin., Tj = -40C to +150C, unless otherwise specified Pos. Parameter Symbol Values Unit TC Conditions min. typ. max. IOUTn tOUTn_ec - - 0.6 A C - - - 100 h C VBAT14V, RL6.93 IOUTn_max 0.6 - 1.5 A C - Ron-40_n Ron+25_n Ron_n - - 780 m C - - 962 m C - - 1300 m A IOUTn=0.6A IOUTn=0.6A IOUTn=0.6A Load Current 5.8.1 Continuous Load Current 5.8.2 Extended current time, Accumulated operating time. 5.8.3 Maximum current (short circuit limited current / switch off threshold). ON-Resistance 5.8.4 On-resistance Tj=-40C 5.8.5 On-resistance Tj=25C 5.8.6 On-resistance Tj150C Delay times, Slew rates (see Figure 6) 5.8.7 Switch on delay tdon_n - - 10 s C 5.8.8 Switch off delay tdoff_n - - 10 s C Difference of switch on and off delay tdif_n -5 - 5 s C 5.8.10 Switch on slew rates son_n 1.5 3.1 7.5 V/s C 5.8.11 Switch off slew rates soff_n 1.5 3.1 7.5 V/s C 5.8.12 Leakage current of the Output Stage Il_OUTn - - 5 A C 5.8.13 Leakage current of the Output Stage Il_OUTn - - 15 A C 5.8.14 Leakage current of the Output Stage Il_OUTn - - 35 A A 5.8.9 tdif_n=tdon_n-tdoff_n RLoad=28.7, VBAT=14V RLoad=28.7, VBAT=14V RLoad=28.7, VBAT=14V RLoad=28.7, VBAT=14V RLoad=28.7, VBAT=14V Leakage current VOUTn=14V, VDD=0V, Tj=60C VOUTn=28V, VDD=0V, Tj=60C VOUTn<28V, VDD=5V (diagnosis current off, CONREG3), Tj=150C Clamping voltage 5.8.15 Clamping voltage 5.8.16 Clamping voltage Data Sheet VCL_n VCL_n 28 50 - 60 V C 50 - 60 V A IOUTn=0.6A IOUTn=0.2A Rev. 1.1, 2012-07-31 TLE 8718 SA Power Stages Table 13 Electrical Characteristics Power Stages OUT17 and OUT18 n = 17 and 18, all channels ON or OFF, nominal load conditions, 4.5V < VDD < 5.5V, 4.5V < VBAT < 40V, all voltages with respect to PGND, positive current flowing into pin., Tj = -40C to +150C, unless otherwise specified Pos. Parameter Clamping energy Symbol Values min. typ. max. Unit TC Conditions 1) 5.8.17 Standard operating range, max. 1.1Mio cycles ECL_OUTn - - 9 mJ C 5.8.18 Standard operating range, max. 40Mio cycles ECL_OUTn - - 6.5 mJ C 5.8.19 Standard operating range, max. 9Mio cycles ECL_OUTn - - 6.5 mJ C 5.8.20 Standard operating range, max. 1Mio cycles ECL_OUTn - - 6.5 mJ C 5.8.21 Generator defect, max. 0.02Mio cycles, or ECL_OUTn Item 5.8.22 - - 11 mJ C 5.8.22 Generator defect, max. 0.02Mio cycles ECL_OUTn - - 8 mJ C 5.8.23 Jump start, max. 0.001Mio cycles, or Item 5.8.24 ECL_OUTn - - 25 mJ C 5.8.24 Jump start, max. 0.001Mio cycles ECL_OUTn - - 17 mJ C 5.8.25 Load dump, max. 10 pulses, or Item 5.8.26 ECL_OUTn - - 50 mJ C 5.8.26 Load dump, max. 10 pulses ECL_OUTn - - 30 mJ C 5.8.27 Load dump, max. 10 pulses, or Item 5.8.28 ECL_OUTn - - 34 mJ C 5.8.28 Load dump, max. 10 pulses ECL_OUTn - - 18 mJ C - - A C - - A C - - A C Tj(0)=35C, IOUTn(0)<0.45A Tj(0)=125C, IOUTn(0)<0.3A Tj(0)=140C, IOUTn(0)<0.3A Tj(0)=150C, IOUTn(0)<0.3A Tj(0)=35C, IOUTn(0)<0.5A Tj(0)=145C, IOUTn(0)<0.35A Tj(0)=35C, IOUTn(0)<0.75A2) Tj(0)=85C, IOUTn(0)<0.5A Tj(0)=35C, IOUTn(0)<0.8A2) Tj(0)=145C, IOUTn(0)<0.4A Tj(0)=35C, IOUTn(0)<1A2) Tj(0)=145C, IOUTn(0)<0.6A Reverse current through OUTn IR_S_OUTn -0.6 5.8.30 Without supply voltage, possibly Leakage IR_Soff_OUTn -0.6 5.8.29 In operation mode, static, no destruction Tj=150C,VDD=5V VDD<1V Current out of neighbor channels. 10ms after the reverse current disappears leakage current criteria are kept. IR_S_OUTn 5.8.31 In operation mode, No unwanted switching of channels; No unwanted Reset, No unwanted change of Voltage Monitoring Thresholds; No unwanted communication errors or register changes beside diagnostic registers. Possibly unwanted diagnostic entries. Possibly Leakage Current out of neighbor channels. -0.2 Tj=150C, VDD=5V 1) Clamping energy, Linear decreasing current, fcl<50Hz 2) PS might switch off to limit the current before reaching the given IOUTn due to reaching IOUTn_max. Data Sheet 29 Rev. 1.1, 2012-07-31 TLE 8718 SA Power Stages 5.9 Timing Diagram MSC to OUTn Command Frame OUTn ON OUTn OFF VOUTn VBAT 0.8VBAT t son s off t dif = t don - t doff 0.2VBAT Drawing8_Timing_MSC_to_OUTn.vsd Figure 6 t don t son t doff t soff t Timing diagram MSC to OUTn (not tested, overview only) The timing starts with the end of the data frame. 5.10 Parallel connection of PS All stages are switched on and off simultaneously as all data of the downstream frame becomes valid at the same time. The micro controller has to ensure that the stages which are connected in parallel have always the same state (on or off) and same configuration regarding current limitation (OUTn_SCB). Exceptions are OUT15 and OUT16 which are controlled by command. Therefor these two stages can only be connected in parallel with each other. The application has to take into account that all maximum ratings are observed (e.g. in case of short circuit the ground current and the power dissipation has to be taken into account). The Junction Temperature of the power stages which are switched in parallel has to be equal. No parasitic resistors between the parallel connected output channels are considered in Table 14. If channels are connected in parallel, they must be connected in parallel for the whole lifetime (no switching between "parallel connection" and "non parallel connection" allowed during lifetime for a single device). Maximum current: The maximum value of the maximum current IOUTpar_max(max) of the parallel connected stages is the sum of the corresponding maximum current values IOUTn_max(max). The minimum value of maximum current IOUTn_max(min) is shown in Table 14. ON-Resistance: The maximum ON-Resistance at 150C of a parallel connection Ron_par = 1 / (1 / Ron_n) and the corresponding condition IOUTpar_max(min) can be seen in Table 14. Clamping Energy: Only equivalent operating points could be added. The conditions (Tj(0), IOUTn(0)) for parallel connected stages are the same as for a single stage. The clamping energy of parallel connected stages is ECL_par(max) = Clamping_energy_factor x ECL_OUTn(max) and shown in Table 15. The performance during parallel connection of channels is specified by design and not subject to the production test. Only the combinations defined in Table 14 and Table 15 are supported for parallel connection. Data Sheet 30 Rev. 1.1, 2012-07-31 TLE 8718 SA Power Stages Table 14 Parallel connection, definition of Maximum Current and ON Resistance1) OUT OUT OUT OUT OUT OUT OUT 1, 3 2, 4 5...8 9, 10 11...14 15,16 17,18 OUT OUT OUT OUT OUT OUT OUT 1, 3 2, 4 5...8 9, 10 11...14 15,16 17,18 Maximum current for 2 stages [A]2) ON Resistance for 2 stages [m] OUT1, 3 13.6 6.6 6.7 4.7 6.7 - - 1053) 131 163 145 163 - - OUT2, 4 6.6 5.1 4.1 3.8 4.1 - - 131 175 236 201 236 - - OUT5...8 6.7 4.1 3.7 3.1 3.7 - - 163 236 360 284 360 - - OUT9, 10 5 3.8 3.1 3.7 3.1 - - 145 201 284 235 284 - - OUT11...14 6.7 4.1 3.7 3.1 3.7 - - 163 236 360 284 360 - - OUT15...16 - - - - - 1 - - - - - - 1200 - OUT17...18 - - - - - - 1 - - - - - - 650 Maximum current for 3 stages [A] OUT5...8 2) ON Resistance for 3 stages [m] - - 5.2 - - - - - - 240 - - - - OUT11...14 - - - - 5.2 - - - - - - 240 - - Maximum current for 4 stages [A] OUT5...8 2) ON Resistance for 4 stages [m] - - 6.5 - - - - - - 180 - - - - OUT11...14 - - - - 6.5 - - - - - - 180 - - 1) The performance during parallel connection of the channels is specified by design and not subject to production test. 2) The defined current could be forced, without running into overcurrent shutdown. Nevertheless the metal lines on the PCB must be designed for IOUTn_max (max). 3) The defined ON Resistance is valid for operation without clamping (resistive load or inductive load with external freewheeling). Table 15 Parallel connection, definition of Clamping_energy_factor1) OUT 5...8 OUT 9, 10 OUT 11...14 OUT 15,16 OUT 17,18 Clamping_energy_factor for 2 stages 2) 2) 2) 0.6 3) 2) 3) 0.6 OUT15...16 - - - 0.6 - OUT17...18 - - - - 0.6 OUT5...8 0.6 OUT9, 10 OUT11...14 Clamping_energy_factor for 3 stages OUT5...8 0.45 OUT11...14 - - - - - - 0.45 - - Clamping_energy_factor for 4 stages OUT5...8 0.4 OUT11...14 - - - - - - 0.4 - - 1) The performance during parallel connection of the channels is specified by design and not subject to production test. 2) The clamping energy of parallel connected stages is the same as clamping energy of a single OUT5...8 stage. 3) The clamping energy of parallel connected stages is the same as clamping energy of a single OUT11...14 stage. Data Sheet 31 Rev. 1.1, 2012-07-31 TLE 8718 SA Device Self Protection 6 Device Self Protection 6.1 Short Circuit Protection All PS are short circuit protected - see Chapter 4.2. In case of a short circuit to battery voltage the output current is limited by internal current control (OUT1...18). After a delay time (tDIAG_SCB) the output is turned off, if its configured in MSC register CONREG1, 2, OUT1516 to switch off (OUT1-18). 6.2 Over Temperature Shut Down If critical overtemperature (overtemperature shut down threshold TOUTn_OTSD) is detected in one stage the stage is switched off to protect the circuit against damage, see logic diagram, state D (Chapter 8.3). All self protection circuits (Short Circuit to Battery and Over Temperature Shut Down) are functional in undervoltage and overvoltage condition from VDD_POR up to VDD_MR. Registration of short circuit to battery (SCB) and overtemperature (DOT) in the diagnostic registers during undervoltage or overvoltage condition is not guaranteed. But the stage is switched off as defined in configuration register. 6.3 Battery Voltage Monitoring The Battery Voltage Monitoring allows the detection of Over Voltage Conditions. In case of Over Voltage VSVBATT_OVSD, the monitoring shuts down the Power Stages after a delay time tOUT_OVSD. The Battery Voltage Monitoring acts as an Enable of the Output Stages and does not clear the control bits. This functions supports the reduction of clamping energy to be dissipated in the power stage in case of over voltage conditions, such as Load Dumps. ISVBATT max ISVBATT_PDh min max ISVBATT_PD min t VSVBATT VSVBATT_OVSD max min min VSVBATT_HYS 18V 3V t OUT1...18 tOUT_OVSD tOUT_OVSON OFF" ON" t VBATT_Mon.svg Figure 7 Data Sheet Battery Voltage Monitoring 32 Rev. 1.1, 2012-07-31 TLE 8718 SA Device Self Protection 6.4 Electrical Characteristics Table 16 Self Protections 4.5V < VDD < 5.5V, 4.5V < VBAT < 40V, all voltages with respect to PGND, positive current flowing into pin., Tj = -40C to +150C, unless otherwise specified Pos. Parameter Symbol Values min. Unit TC Conditions typ. max. Self Protection 6.4.1 6.4.2 Self protection temperature threshold TOUTn_OTSD TOUTn_ - Junction temperature of OUTn OTW+0 (n=1...18)1) Self protection temperature hysteresis, OUTn (n=1...18) TOUTn_ TOUTn_ K C - - OTW+30 - 10 - K C 29 - 35 V B 0.25 - 1 V C 1 - 20 A C 3V<VSVBATT<18V OTSDHYS SVBATT Pin (Battery Voltage Monitoring Pin) 6.4.3 SVBATT Pin Voltage, Battery Overvoltage Shut Down Threshold VSVBATT_ 6.4.4 SVBATT Pin Voltage, Battery Overvoltage Shut Down Hysteresis VSVBATT_ 6.4.5 SVBATT Pin internal pull down current ISVBATT_PD 6.4.6 SVBATT Pin internal pull down current ISVBATT_PDh 20 - 80 A C 2) 6.4.7 SVBATT Pin internal pull down current ISVBATT_PD 1 - 500 A C 18V<VSVBATT<40V 6.4.8 Filter time before Output Stages shut tOUT_OVSD down in case of VSVBATT_OVSD is exceeded 5 - 20 s B - 6.4.9 Filter time before Output Stages switch on again tOUT_OVSON 60 - 135 s B - VSVBATT_TM - - -2 V B 3) 6.4.10 Factory test mode activation OVSD HYS 1) See Chapter 8, Item 8.5.6 Diagnosis, Overtemperature warning diagnosis threshold. 2) VSVBATT=VSVBATT_OVSD during voltage increase, respectively VSVBATT=VSVBATT_OVSD-VSVBATT_HYS during voltage decrease. See Figure 7. 3) Not intended to be used in application. Factory test mode entry condition violates Absolute Maximum Rating Item 4.2.10. Data Sheet 33 Rev. 1.1, 2012-07-31 TLE 8718 SA Supervisory (DIS5_10, DELAYIN, DELAYOUT) 7 Supervisory (DIS5_10, DELAYIN, DELAYOUT) Table 17 DIS5_10, DELAYIN, DELAYOUT 4.5V < VDD < 5.5V, 4.5V < VBAT < 40V, all voltages with respect to PGND, positive current flowing into pin., Tj = -40C to +150C, unless otherwise specified Pos. Parameter Symbol Values Unit TC Conditions min. typ. max. VDIS5_10_L VDIS5_10_H VDIS5_10_HYS IDIS5_10 IDIS5_10 IDIS5_10 IDIS5_10 -0.3 - 1 V B - 2 - 36 V B - 0.1 - 0.5 V C - -100 - 5 A C -0.2V<VDIS5_10< VDD -400 - - A C -0.3V<VDIS5_10 - - 100 A C -100 - -20 A A VDD<VDIS5_10< 36V 0V<VDIS5_10< VDD - tDIS5_10 60 - 135 s C - - 0.16*VDD V B - 36 V B - Pin DIS5_10 7.0.1 DIS5_10 input low level 7.0.2 DIS5_10 input high level 7.0.3 DIS5_10 input hysteresis 7.0.4 DIS5_10 input current 7.0.5 DIS5_10 input current 7.0.6 DIS5_10 Input current 7.0.7 DIS5_10 pull-up current 1.5V 7.0.8 Filtering time before switching OUTn, high- or low-pulses on DIS5_10, n=5...10 Pin DELAYIN for DELAYOUT function (lower threshold) 7.0.9 DELAYIN input low level for DELAYOUT VDELAYIN_L -0.3 7.0.10 DELAYIN input high level for DELAYOUT VDELAYIN_H 0.24*VDD - 7.0.11 DELAYIN input hysteresis for DELAYOUT VDELAYIN_HYS 0.02 - 0.1 V C - 7.0.12 DELAYIN input pull-down resistor RDELAYIN - 312 k A 1V<VDELAYIN<40V 7.0.13 DELAYIN input current IDELAYIN -400 tDELAYIN_GLITC 7.5 - 20 A C -0.3V<VDELAYIN <1V - 24 ms C CONREG3.6='1' - 135 s C CONREG3.6='0' 7.0.14 Rising edge long filter time before switching DELAYOUT or RES15_16 168 H_long tDELAYIN_GLITC 60 7.0.15 Rising edge short filter time before switching DELAYOUT or H_short RES15_16 DELAYIN - Filtering time before switching DELAYOUT low 7.0.16 Long delay for tDELAYIN_x, default tDELAYIN_L 800 - 1600 ms C CONREG4.0='1', CONREG4.1='1' 7.0.17 Medium long delay for tDELAYIN_x tDELAYIN_ML 400 - 800 ms C CONREG4.0='1', CONREG4.1='0' 7.0.18 Medium short delay for tDELAYIN_x tDELAYIN_MS 200 - 400 ms C CONREG4.0='0', CONREG4.1='1' 7.0.19 Short delay for tDELAYIN_x tDELAYIN_S 100 - 200 ms C CONREG4.0='0', CONREG4.1='0' Data Sheet 34 Rev. 1.1, 2012-07-31 TLE 8718 SA Supervisory (DIS5_10, DELAYIN, DELAYOUT) Table 17 DIS5_10, DELAYIN, DELAYOUT 4.5V < VDD < 5.5V, 4.5V < VBAT < 40V, all voltages with respect to PGND, positive current flowing into pin., Tj = -40C to +150C, unless otherwise specified Pos. Parameter Symbol Values min. Unit TC Conditions typ. max. Pin DELAYIN for RES15_16 function (higher threshold) 7.0.20 DELAYIN input low level for RES15_16 7.0.21 DELAYIN input high level for RES15_16 7.0.22 DELAYIN input hysteresis for RES15_16 VDELAYIN_RES -0.3 - 0.44*VDD V B - 36 V B - - 0.1 V C - - - 0.7 V A - - 1 V A VDD=2.5V, IDELAYOUT<2mA 2.5V<VDD<36V, IDELAYOUT<6.5mA - - mA C - V A no load 15_16_L VDELAYIN_RES 0.52*VDD - 15_16_H VDELAYIN_RES 0.02 15_16_HYS Pin DELAYOUT 7.0.23 DELAYOUT output low voltage VDELAYOUT_O UTL 7.0.24 DELAYOUT output low voltage VDELAYOUT_O UTL 7.0.25 Maximum current (short circuit limited current)1) IDELAYOUT_ma 15 7.0.26 DELAYOUT passive output high voltage VDELAYOUT_O UTH 7.0.27 DELAYOUT pull-up current IDELAYOUT_INL -50 - -4 A A 0V<VDELAYOUT< VDD- 1.5V, 2) 7.0.28 DELAYOUT input current IDELAYOUT_INH -10 - 10 A C VDD<VDELAYOUT< 36V x VDD - 1.5 VDD - 1) Integrated protection functions are designed to prevent IC destruction under fault conditions. Fault conditions are considered as "outside" normal operating range. Protection functions are not designed for continuous or repetitive operation. Application must take care, that current into this pin does not exceed 15mA. 2) DELAYOUT as Output is not active tDELAYIN_GLITCH_x depending on CONREG3.Bit6 tDELAYIN_x depending on CONREG4.Bit0 and Bit1 DELAYIN [V] 0.52*V DD 0.44*V DD VDELAYIN_RES15_16_H VDELAYIN_RES15_16_L 0.24*V DD 0.16*V DD VDELAYIN_H VDELAYIN_L t DELAYOUT < tDELAYIN_GLITCH_x t RES15_16 tDELAYIN_GLITCH_x OUT15...16 OFF tDELAYIN_x t DELAYIN_x tDELAYIN_GLITCH_x * OUT15...16 controlable via OUT1516 t tDELAYIN_GLITCH_x tDELAYIN_GLITCH_x tDELAYIN_GLITCH_x * tDELAYIN_GLITCH_x Interlock _DELAYIN .vsd * Filter for DELAYOUT is independend from RES 15_16. Thats why they may not switch synchronously. Figure 8 Data Sheet Timing DELAYIN 35 Rev. 1.1, 2012-07-31 TLE 8718 SA Diagnosis 8 Diagnosis 8.1 Diagnostic Functions All PS have fault diagnostic functions: * * * * short circuit to battery: (SCB) can be detected if stages are turned on short circuit to ground: (SCG) can be detected if stages are turned off open load: (OL) can be detected if stages are turned off Diagnosis overtemperature: (DOT) is set if Overtemperature Warning OTW occurs in ON-state or Overtemperature Shutdown OTSD occurs in any state SCB is recognized if the output current reaches IOUTn_max when the stage is switched on. If, after the filtering time (tDIAG_SCB) has expired, the failure is still present, it is stored in the diagnostic register (DIAREG1...5). This may be caused by a short circuit to battery voltage (VBAT up to VBAT_SC) or by a load with too low impedance (e.g. load switched on under cold conditions). In addition to this, there is the extended SCB behavior available, when CONREG3.EXT_SCB="1". In this case VOUTn is checked in addition to IOUTn and the diagnosis register SCB is only set, if IOUTn_max and VOL is reached for longer than tDIAG_SCB. This feature is available for OUT5...14 only and shown in Figure 9. A SCB condition is stored in the diagnosis register. It turns off the output dependent on configuration register (CONREG1, CONREG2, OUT1516). The output can be turned on again even if the SCB bit in the diagnosis registers have not been cleared yet (e.g. by polling the registers). Turning on the outputs won't clear the SCB bit. The output current IOUTn may overshoot before the current limiter reacts and limits the output current to IOUTn_max. However, this overshoot (which depends on the external load) will not damage the device. Data Sheet 36 Rev. 1.1, 2012-07-31 TLE 8718 SA Diagnosis CONREG3.EXT_SCB=0 CONREG1/2/OUT1516.OUTn_SCB=1 CONREG1/2/OUT1516.OUTn_SCB=0 Here is the diagnositc entry set Here is the diagnositc entry set IOUTn I OUTn_max Thermal toggling possible ~ ~ I OUTn IOUTn_max t DIAG_SCB tDIAG _SCB t t CONREG3.EXT_SCB=1 CONREG1/2/OUT1516.OUTn_SCB=1 CONREG1/2/OUT1516.OUTn_SCB=0 Here is the diagnositc entry set Here is the diagnositc entry set IOUTn I OUTn_max Thermal toggling possible ~ ~ I OUTn IOUTn_max t DIAG_SCB t DIAG_SCB VOUTn_OL Filter is startet when IOUTn and VOUTn has exeeded their limits t t VOUTn ~ ~ VOUTn Example 1 V OUTn_OL t IOUTn IOUTn_max tDIAG _SCB VOUTn VOUTn_OL Thermal toggling possible ~ ~ I OUTn_max t Here is the diagnositc entry set Filter is startet when IOUTn and VOUTn has exeeded their limits tDIAG _SCB t t VOUTn Example 2 V OUTn_OL ~ ~ I OUTn Here is the diagnositc entry set t I OUTn_max IOUTn_max t VOUTn VOUTn_OL t VOUTn Example 3 V OUTn_OL t current over -shoot and voltage behavior dependending on external load condition Figure 9 ~ ~ IOUTn If OT is not reached, there is no diagnostic entry ~ ~ I OUTn t Diagnostic entry accures because of OT t SCB_extended_Diagnostic.vsd SCB Diagnosis function Depending on the configuration of the stage (CONREG1, 2, OUT1516) the stage is switched off or remains functional in current limited mode with fault entry in the diagnostic register. The OTSD threshold (TOUTn_OTSD) has a hysteresis and switches off the channel (see Chapter 6); The OTW (TOUTn_OTW) threshold has no hysteresis and is diagnosis only. The stage is not switched off by OTW. Only if temperature rises above shutdown threshold (TOUTn_OTSD) the stage is disabled for device self protection. After this, the stage wont be enabled again until temperature falls below Self protection temperature hysteresis (TOUTn_OTSDHYS) (see Chapter 6). Data Sheet 37 Rev. 1.1, 2012-07-31 TLE 8718 SA Diagnosis Over Temperature Warning [TOTW ], Over Temperature Shut Down [TOTSD ], Over Temperature Shut Down Hysteresis [TOTSD_HYS], for OUT1...18 TJ TOTW Ref. 1 ON" 0 & 0 0 t OTW 0 DOT >=1 0 0 Ref. 2 OUTn OFF" TOTW + 10K = TOTSD Case 1: TOTSD-HYS > TOTW Case 2: TOTSD-HYS < TOTW TJ TOTSD TOTSD TOTSD-HYS TOTW TOTW TOTSD-HYS DOT set" tOTW DOT set" OUTn ON" OUTn ON" t Figure 10 tOTW TOTW_TOTSD_TOTSDHYST.vsd t Temperature Thresholds (see also Chapter 6) OL or SCG is recognized using two thresholds (VOUTn_SCG and VOUTn_OL) and a bias voltage source with current limit for each output. For OUT11...OUT18 it is possible by configuration to switch off the internal diagnostic pull-down current source. In this case diagnosis of OL is deactivated, no entry of OL into diagnostic register, even if VOUTn_SCG < VOUTn < VOUTn_OL. Diagnosis of SCG remains functional. See Chapter 8.3 for specified values of diagnostic currents and threshold voltages. The fault conditions SCB, SCG, OL and DOT will not be stored until an integrated filtering time (tDIAG_SCB, tDIAG_SCG, tDIAG_OL, tDIAG_OTW) has expired. If at one output, several errors occur in a sequence, the newest detected error is stored to the diagnosis register (after filtering time). Data Sheet 38 Rev. 1.1, 2012-07-31 TLE 8718 SA Diagnosis I OUTn I OUTn_DIA _P(max) Diagnostic pull-down current and Open Load OL on OL SCG O.K. 600A IOUTn_DIA_P(min) 220A 0 VOUTn_BIAS IOUTn_DIA _N(max) VBAT VOUTn VBAT VOUTn -100A IOUTn _DIA _N(min) -300A VOUTn_SCG I OUTn I l_OUTn (max) VOUTn_OL Diagnostic pull -down current and Open Load OL off SCG O.K. 20...35A 0 VOUTn_BIAS IOUTn_DIA _N(max) -100A Output stage is switched off for this measurement IOUTn _DIA _N(min) Drawing6_SCG _and_OL_Diagnosis _Function.vsd -300A VOUTn_SCG Figure 11 SCG and OL diagnosis function (not tested, overview only) 8.2 Encoding of Diagnostic Information All fault conditions are encoded in two bits per stage and are stored in the corresponding registers (DIAREG1...5). Additionally there is one central diagnostic overtemperature bit (COTW) (this bit is set to `0' if DOT occurred at any stage). The common failure bit (DIAREG6, bit FAILURE_FLAG) is set to `0' if SCB, SCG, OL or DOT is detected on any output stage (OUT1...18). Only if all the stage diagnostic bits are `1', the FAILURE_FLAG bit is `1'. The diagnosis registers can be read via MSC. When a valid MSC read command (RD_DATA) is detected, the selected diagnosis register information is moved to a shift register for transmission (MSC upstream). At the same time the selected diagnosis register is cleared. Table 18 Encoding of diagnosis information Encoding of the diagnosis bits of the device OUTn_DIA2 OUTn_DIA1 description 1 1 Power stage ok 1 0 Short circuit to battery (SBC) or diagnostic overtemperature (DOT) 0 1 Open load (OL) 0 0 Short circuit to ground (SCG) Data Sheet 39 Rev. 1.1, 2012-07-31 TLE 8718 SA Diagnosis State Diagram of the Device Diagnosis SCG Fault entry 11 (no fault) SCG OTW no Fault entry 10 (DOT) OTSD Fault entry 10 (DOT) below TO UTn_OTSDHYS and Control=ON SCB Fault entry 10 (SCB) Configuration: switch OFF on SCB OTSD Fault entry 10 (DOT) OTW tOUTn_OTW SC B RD_DATA WR_RST Control=OFF no OTW SCB n=1..4, 15..18 and 5..14 if EXT_SCB=0 tDIAG_SCB State C OFF forced by short circuit Control = On OUTn = Off OUTn MAX Control = On OUTn = On V t DIAG_SCG Fault entry 00 (SCG) an d b elow TOU Tn_OTS D HY S if OTS D was reached befo re Fault entry 10 (DOT) ON current internally limited to n =5 .. no SCG OTSD Control=OFF no Control = Off OUTn = Off State B Configuration: current limit on SCB OFF Control= ON O 14 if EUT >VO U T XT _S _ C B=1O L State A Fault entry 01 (OL) tOUTn_OTW TW RD_DATA WR_RST O RD_DATA WR_RST OL no OL OL tDIAG_OL Fault entry 11 (no fault) OTW Fault entry 11 (no fault) S CB & 8.3 OTW State D Overtemperature self protection OFF Control = x OUTn = Off below TOUTn _OTSDHYS and Control=OFF Drawing7_State _Diagram .vsd Figure 12 State diagram of the device diagnosis (not tested, overview only) Outputs are switched inactive if VDD is out of range or RST respectively ABE is externally pulled low. After a reset the stages start in state A (OFF state). If a stage is getting overheated above the overtemperature shutdown threshold (TOUTn_OTSD, Item 6.4.1) it is entering state D (switched off for self protection) independent from its current state. Leaving this state is only possible if temperature falls below Self Protection Temperature Hysteresis (TOUTn_OTSDHYS, Item 6.4.2). Data Sheet 40 Rev. 1.1, 2012-07-31 TLE 8718 SA Diagnosis 8.4 Reset of the Diagnostic Information The diagnostic registers are set to its reset value individually at readout by their RD_DATA command, or all together by WR_RST command, POR or RST. At the same time, the filters tDIAG_SCB, tDIAG_SCG, tDIAG_OL are re-set. The filter tDIAG_OTW is not re-set. In the case a stage is shut off because of SCB, by readout of the diagnostic information via RD_DATA instruction the DIAREGx entry is cleared and output is activated again. Because SCB could only be detected when the stage is switched on, the output is activated and shut off again after the shutoff delay, if SCB condition is still existent. Some register bits are not cleared by read-out or reset, see tables in Chapter 12.2. 8.5 Electrical Characteristics Table 19 Diagnosis 4.5V < VDD < 5.5V, 4.5V < VBAT < 40V, all voltages with respect to PGND, positive current flowing into pin., Tj = -40C to +150C, unless otherwise specified Pos. Parameter Symbol Values min. typ. Unit TC Conditions max. Diagnosis filter time, delay time fault condition to switch off, OUTn (n=1...18) 8.5.1 8.5.2 8.5.3 8.5.4 8.5.5 tDIAG_OTW tDIAG_SCB Short to Ground tDIAG_SCG Open Load tDIAG_OL Diagnosis Fault entry delay, delay tDIAG_DELAY Overtemperature Warning 15 - 30 s C - Short to Battery Voltage 60 - 135 s B - 60 - 135 s B - 60 - 135 s B - 0 - 5 s C - time after diagnosis filter time has expired until fault entry is stored in corresponding diagnostic register 8.5.6 Overtemperature warning diagnosis threshold TOUTn_OTW 150 - 190 C C - 8.5.7 Short circuit to ground diagnosis threshold VOUTn_SCG 0.6*VDD -0.2 - 0.6*VDD +0.2 V B - 8.5.8 Open load diagnosis threshold stage disabled VOUTn_OL VDD-0.2 - VDD+0.3 V B 1) 8.5.9 Diagnostic bias voltage stage disabled VOUTn_BIAS 0.7*VDD - 0.7*VDD +0.2 V A 1) VOUTn=14V VOUTn_OL< VOUTn<VBAT VOUTn=0V 0V<VOUTn <VOUTn_SCG Diagnostic current of OUTn 8.5.10 Diagnostic pull down current 8.5.11 Diagnostic pull down current 8.5.12 Diagnostic pull up current 8.5.13 Diagnostic pull up current Data Sheet -0.2 1) IOUTn_DIA_P 270 IOUTn_DIA_P 220 - 550 A A - 550 A C IOUTn_DIA_N -300 IOUTn_DIA_N -300 - -100 A A - -100 A C 41 Rev. 1.1, 2012-07-31 TLE 8718 SA Diagnosis Table 19 Diagnosis 4.5V < VDD < 5.5V, 4.5V < VBAT < 40V, all voltages with respect to PGND, positive current flowing into pin., Tj = -40C to +150C, unless otherwise specified Pos. Parameter Symbol Values Unit TC Conditions min. typ. max. VREVCUR -0.3 - -0.03 V C - tREVCUR 26 - 60 s C - Reverse Current Detection OUTn (n=1...18) 8.5.14 Reverse Current detection voltage 8.5.15 Reverse Current filter time 1) OUTn_DIAC='1' 8.6 Timing OUTn = OFF AE OUT-Voltage decreases slowly OL SCG t DIAG_OL t DIAG_SCG DIAG 11 OK 01 OL RD_DATAx 00 SCG 11 OK RD_DATAx 01 OL 11 OK t DIAG_OL OUTn = OFF AE OUT-Voltage decreases fast OL SCG t DIAG_OL RD_DATAx t DIAG_SCG DIAG 11 OK 00 SCG 11 OK RD_DATAx 01 OL 11 OK t DIAG_OL OUTn = ON to OFF AE OUT-Voltage increases fast ON OFF OL t DIAG_OL SCG t DIAG_SCG DIAG 11 OK OUTn = ON to OFF AE OUT-Voltage increases slow ON OFF OL t DIAG_OL SCG DIAG t DIAG_SCG 11 OK 01 OL t Diagnosis _entry _timing.vsd Figure 13 Data Sheet Timing and logic entry of diagnosis information to diagnosis register 42 Rev. 1.1, 2012-07-31 TLE 8718 SA Supply, VDD Monitoring, Reset and ABE 9 Supply, VDD Monitoring, Reset and ABE 9.1 General functions of VDD Monitoring VDD -Monitoring is measured with reference to GNDABE. Power On Reset (POR) is measured with reference to PGND. The state of VDD monitoring is stored in DIAREG7 and can be read out via MSC. VDD monitoring detects supply voltage outside the specified range. It disables stages but does not reset registers CONREGx, DIAREGx In case of VDD failure, the stages must be switched off according CONREG4.ABE_IMPACT -setting, even if Pin ABE is high level because of external short circuit to VDD or VBAT (up to VBAT_SC). 36V VDD_MR_max 5.25...5.5V ** VDD_THH 4.2...4.4V ** VDD_THL 3...3.5V VDD_POR max 2.5V VDD_RES tPOR tPOR tFIL_ON ABE power on reset, switched OFF tFIL _OFF tFIL _ON tFIL _OFF tFIL _ON t FIL_ON tABE or t FIL_OFF_DEL Depending on ABE_IMPACT Change of ABE caused by external event high low Outputs on off OUT16* OUT15* on off tFIL_OFF tDELRES Behavior up to VDD_RES undefied Outputs remain OFF if bit MON_LATCH is '1' OUT16, OUT16 are switched OFF after tDELRES or by MSC COMMAND t Drawing20_VDD_monitoring_function .vsd *: configured to delayed reset behaviour **: refered to GNDABE Figure 14 VDD monitoring function (not tested, overview only) Figure 14 explanation: In the "shaded" area of "Outputs", the output channels may be switches ON or OFF by MSC DATA-Frame. In shaded area of "OUT15, OUT16" the output channels may be switched or remain ON or OFF dependent on the register settings OUT1516. OUT15 and OUT16 cant be switched on during over-, undervoltage, ABE, MSC_MON or RST. Switching off is possible (see Figure 1). POR (VDD < VDD_POR) switches off all stages without delay. Data Sheet 43 Rev. 1.1, 2012-07-31 TLE 8718 SA Supply, VDD Monitoring, Reset and ABE 9.2 VDD Undervoltage If the VDD voltage is lower than the supply voltage supervisory lower threshold (VDD_THL), all output stages are shut off after a filtering time (tFIL_OFF) and active low signal is generated at the bi-directional pin ABE. The only exception is OUT15 and OUT16, if configured to delayed reset behavior. These outputs then remain functional in undervoltage condition, until * * * * filtering time (tDELRES) has expired, or stage is switched off by MSC command or VDD falls below the power-on-reset threshold (VDD_POR) or RES15_16 gets active. OUT15 or OUT16 cannot be switched on by MSC command in undervoltage condition. At the transition from undervoltage to normal voltage the signal at Pin ABE goes high after a filtering time (tFIL_ON) has expired. Output registers are cleared to "1" (output stages remain off until switched on again via MSC data frame). During undervoltage condition no new fault conditions are written to diagnosis registers, the content is frozen. However, data and configuration registers still can be accessed (read and write) using MSC commands. If VDD falls below the power-on-reset supply voltage (VDD_POR) all stages are shut off and ABE is switched active low. When VDD is rising above the power-on-reset supply voltage threshold (VDD_POR) a power-on-reset is internally generated (tPOR), setting all registers to its default state (all stages switched off, all registers cleared to default). 9.3 VDD Overvoltage If the VDD voltage is higher than the supply voltage supervisory upper threshold (VDD_THH), all output stages are shut off after a filtering time (tFIL_OFF) and active low signal is generated at the bi-directional Pin ABE. The only exception is OUT15 and OUT16, if configured to delayed reset behavior. These outputs then remain functional in overvoltage condition, until * * * filtering time (tDELRES) has expired or stage is switched off by MSC command or RES15_16 gets active. OUT15 or OUT16 cannot be switched on by MSC command in overvoltage condition. The behavior of the ABE level and output stages on the return of VDD from overvoltage to the correct range is configured in CONREG4, bit MON_LATCH). - 1: ABE is latched and outputs remain off after overvoltage, tDELRES continues to expire and switches off OUT15 and OUT16. Return to normal operation is only possible with power-on reset or by changing this bit via MSC command to "0". - 0: ABE is inactive after VDD returned to normal operating voltage and filtering time has expired. At the transition from overvoltage to normal condition, output registers are cleared to "1" (output stages remain off until switched on again via MSC). During overvoltage condition no new fault conditions are written to diagnosis registers, the content is frozen. However, data and configuration registers still can be accessed (read and write) using MSC commands. Data Sheet 44 Rev. 1.1, 2012-07-31 TLE 8718 SA Supply, VDD Monitoring, Reset and ABE Thresholds not defined MSC functional within specified values B) A) MSC disable not defined not defined not defined not defined 0V VDD_MR_min not defined -0.3V B) V DD_RES Stages follow MSC 2.5V A) V DD_POR All OFF 3... 3.5V MSC function not defined V DD_THL ABE output active low 4.2... 4.4V* Output stages ABE output inactive (ABE high) V DD_min ABE output active low 4.5V not defined V DD_THH VDD Monitoring no logic misfunction (no unwanted switching of stages...) 5.25... 5.5V* full compliance to specified values V DD_max no damage 5.5V Reset logic internal reset V DD_MR_max no damage 36V Device overall not defined VDD not defined 9.4 A) Switching OUT1...14, 17, 18 OFF after tFIL_OFF B) Switching OUT15, 16 OFF after tFIL _OFF or tDELRES if configured to delayed reset behavior via OUT 1516 * Refered to GNDABE Figure 15 Data Sheet Drawing18_Supply _Range .vsd Operating Supply Range 45 Rev. 1.1, 2012-07-31 TLE 8718 SA Supply, VDD Monitoring, Reset and ABE 9.5 ABE Pin ABE is functional as input and output. During a low on pin ABE (pulled low by the internal open drain device or forced low by an external source), the output registers are cleared to `1' switching off outputs OUT1...OUT14, OUT17, OUT18. Behavior of OUT15 and OUT16 depends on configuration register settings. Programmable filter times apply. See Figure 1 and Figure 16 for details. 9.6 Testing of VDD Monitoring RST STATUS_OV Power On Reset VDD Under voltage = L" + - 1 0 + 1 STATUS_UV Over voltage = L" VDD DIAREG6 bit #3 ABE_STATUS Hysteresis tFIL_ON tFIL_OFF tFIL_ON tFIL_OFF ABE tABE Set dominant 1 & S Q R PGND Internal reference GNDABE CONREG4 bit #7 Power On Reset H" = switches OFF OUTn tFIL_OFF_DEL & MUX 0 (MON_LATCH) 1 CONREG4. ABE_IMPACT GNDABE 1 1 bit #6 CONREG 4 0 Test overvoltage threshold Test undervoltage threshold 1 x default, normal operation Figure 16 #5 0 0 1 bit #7 #6 #5 DIAREG7 Drawing19_VDD_monitoring.vsd Block Diagram of VDD Monitoring The stages are switched off if under- or overvoltage is detected in any case OUT15,16 might be delayed, dependent on register OUT1516. 9.7 Testing procedure of VDD Monitoring in the application Testing upper threshold in application (VDD is 5V): By writing xxxxx00xb into CONREG4, the overvoltage threshold is reduced to VTEST_THH. In DIAREG7 bit 5 and 7 have to be LOW then. After writing xxxxx1x0b to CONREG4, bit 5 and 7 in DIAREG7 must be HIGH again. Testing lower threshold in application (VDD is 5V): By writing xxxxx01xb into CONREG4, the undervoltage threshold is increased to VTEST_THL. In DIAREG7 bit 6 and 7 have to be LOW then. After writing xxxxx1xxb to CONREG4, bit 6 and 7 in DIAREG7 must be HIGH again. Data Sheet 46 Rev. 1.1, 2012-07-31 TLE 8718 SA Supply, VDD Monitoring, Reset and ABE 9.8 Electrical Characteristics Table 20 Power Supply, POR, VDD Monitoring, ABE and RST 4.5V < VDD < 5.5V, 4.5V < VBAT < 40V, all voltages with respect to PGND, positive current flowing into pin., Tj = -40C to +150C, unless otherwise specified Pos. Parameter Symbol Values Unit TC Conditions min. typ. max. Power Supply 9.8.1 Operational Supply Current IVDD - 18 25 mA C 4.5V<VDD<5.5V, All channels ON or OFF, nominal load conditions 9.8.2 Overvoltage Supply Current IVDD_0V - - 50 mA C 5.5V<VDD<36V, no damage Power ON Reset 9.8.3 Reset Circuit Functional, Internal reset active for VDD_RES<VDD<VDD_POR All stages switched inactive and internal registers are cleared. VDD_RES - - 2.5 V B - 9.8.4 Power On Reset Threshold VDD_POR Below this threshold the device is in reset state, all registers are cleared. Device starts operation (VDD monitoring forces stages off) after tPOR, when VDD is rising above this threshold. 3 - 3.5 V B - 9.8.5 Power On Reset Extension Time 180 - 360 s C - tPOR VDD Monitoring 9.8.6 Undervoltage threshold, ABE turns VDD_THL active low and stages are turned off when VDD is below this threshold 4.1 - 4.4 V B 1) 9.8.7 Overvoltage threshold, ABE turns VDD_THH active low and stages are turned off when VDD is above this threshold 5.25 - 5.5 V B 1) 60 - 135 s C - tFIL_OFF_DEL 30 Filtering time with delay before switching off if ABE is configured to delayed switching of stages by CONREG4, switching OFF because of VDD Monitoring or falling edge of ABE is de-bounced 2) - 80 ms C - 9.8.8 Filtering time before switching off, VDD is rising above VDD_THH or falling below VDD_THL all outputs except tFIL_OFF OUT15, OUT16 if configured to delayed reset 9.8.9 Data Sheet 47 Rev. 1.1, 2012-07-31 TLE 8718 SA Supply, VDD Monitoring, Reset and ABE Table 20 Power Supply, POR, VDD Monitoring, ABE and RST 4.5V < VDD < 5.5V, 4.5V < VBAT < 40V, all voltages with respect to PGND, positive current flowing into pin., Tj = -40C to +150C, unless otherwise specified Pos. Parameter Symbol 9.8.10 Delayed Reset for OUT15 and tDELRES OUT16, if configuration bits are set to delayed reset Values Unit TC Conditions min. typ. max. 400 - 800 ms C - 9.8.11 Filtering time before switching on, returning to VDD_THL<VDD<VDD_THH tFIL_ON 60 - 135 s C - 9.8.12 Test VDD monitoring undervoltage, VDD monitoring test active VTEST_THL 5.15 - 5.6 V B 1) 9.8.13 Test VDD monitoring overvoltage, VDD monitoring test active VTEST_THH 4.1 - 4.5 V B 1) VABE_INL VABE_INH VABE_INHYS IABE_INL -0.3 - 0.3*VDD V B - 36 B - ABE as Input 9.8.14 ABE input low level 9.8.15 ABE input high level 9.8.16 ABE input hysteresis 9.8.17 ABE input current IABE 9.8.19 ABE input current IABE_INH 9.8.20 ABE pulse width, ABE requires min. tABE 9.8.18 ABE input current 0.7*VDD - V 0.2 - 1 V C - -100 - -20 A A -0.2V<VABE<VDD- 1.5V3) -400 - - A C -0.3V<VABE3) -5 - 5 A A VDD<VABE<36V 0.5 - 3.5 s C low level pulse width ABE as Output 9.8.21 ABE output low voltage VABE_OUTL - - 1 V A 2.5V<VDD<VDD_THL, IABE<6.5mA 9.8.22 ABE output low voltage VABE_OUTL - - 1 V A 9.8.23 ABE output low voltage VABE_OUTL - - 0.7 V A VDD_THH<VDD<36V, IABE<7mA VDD=2.5V, IABE<2mA 9.8.24 Maximum current (short circuit limited current)4) IABE_max 15 - - mA C 9.8.25 ABE passive output high voltage VABE_OUTH VDD-1.5 VDD - V A Data Sheet 48 no load Rev. 1.1, 2012-07-31 TLE 8718 SA Supply, VDD Monitoring, Reset and ABE Table 20 Power Supply, POR, VDD Monitoring, ABE and RST 4.5V < VDD < 5.5V, 4.5V < VBAT < 40V, all voltages with respect to PGND, positive current flowing into pin., Tj = -40C to +150C, unless otherwise specified Pos. Parameter Symbol Values Unit TC Conditions min. typ. max. -0.3 - 1 V B 2 - 36 V B 0.1 - 0.5 V C -120 - 20 A C Pin RST 9.8.26 RST input low level 9.8.27 RST input high level 9.8.28 RST input hysteresis 9.8.29 RST input current 9.8.30 RST input current 9.8.31 RST input current 9.8.32 RST pull-up current 9.8.33 Reset pulse width, RST requires min. low level pulse width VRST_L VRST_H VRST_HYS IRST IRST IRST IRST tRST -0.2V<VRST<VDD -10 - 1000 A C VDD<VRST<36V -400 - - A C -0.3V<VRST -50 - -10 A A 0V<VRST<VDD-1.5V 3.5 s C 0.5 1) Referred to GNDABE 2) In case of undervoltage of VDD, specification is not fulfilled: e.g. proper operation of protection functions is not guaranteed (OUT= 1...14,17,18). 3) ABE as Output is not active 4) Integrated protection functions are designed to prevent IC destruction under fault conditions. Fault conditions are considered as "outside" normal operating range. Protection functions are not designed for continuous or repetitive operation. Application must take care, that current into this pin does not exceed 15mA. Data Sheet 49 Rev. 1.1, 2012-07-31 TLE 8718 SA Device Logic Behavior 10 Device Logic Behavior Table 21 Device Logic Behavior 15, 16 OUT1516 delay timer MSC timeout counter ABE output DELAYOUT output SDO output - - data entry - ON/OFF depending on OUTREG - - restart - - - RD_CONFIG - read out - - - - - - - - send data RD_DATA read - out & reset 1) 1) 1) 1) - - - - send data reset - 1) 1) 1) 1) - - - - - WR_CONREGx - data entry - - - - - - - - - WR_OUT1516 - - - data entry - ON/OFF restart depending on 3) OUT1516 3) - - - - MON_TEST x data entry x x x x - - x x - DIS5_10 data entry - - - - disable - - - - - - lower thresholds of DELAYIN4) data entry - - - - - - - - pulled - low higher thresholds of DELAYIN5) data entry - - reset - reset - - - - RST reset reset reset reset disable 7) disable 6) - restart pulled pulled disable 8) low low ABE_STATUS data entry - reset reset disable 7) disable 6) - - - reset disable 7) disable 6) - - pulled pulled - low low disable disable - - - 1...4, 11...14, 17, 18 5...10 Dataframe DIAREG OUT1516 Others OUTREG Output Stages CONREG Registers MSC Communication WR_RST 2) Input pins 6) 6) - - - Internally detected error cases STATUS_UV, STATUS_OV data entry - reset 6) STATUS_SVBATT data entry - - POR reset reset reset reset disable restart restart 9) pulled pulled disable 8) low low SCB data entry - - - disable (defined in CONREGx and OUT1516) - - - - - OL data entry - - - - - - - - - - SCG data entry - - - - - - - - - - Data Sheet 50 Rev. 1.1, 2012-07-31 TLE 8718 SA Device Logic Behavior Table 21 Device Logic Behavior Registers Output Stages Others OTW data entry - - - - - - - - - - OTSD 10) - - - disable disable - - - - - REVCUR_FLAG data entry - - - - - - - - - - expired - - - - - Timeout counter expired MSC timeout counter data entry - reset reset disable7) disable 6) - OUT1516 delay timer - - - reset - disable 6)11) expired - 6) 11) - 1) Outputs which have been switched off by SCB are switched on until SCB is detected again 2) Only DIAREG1...5 are reset, DIAREG6 and DIAREG7 remain unchanged 3) Switching on respectively restarting delay timer only in failure free condition 4) Thresholds VDELAYIN_L and VDELAYIN_H 5) Thresholds VDELAYIN_RES15_16_L and VDELAYIN_RES15_16_H 6) OUT1516 reset and stages are disabled after delay time (OUT15, OUT16 may be configured to long delay) 7) OUTREG reset and stages are disabled because control register is reset 8) communication stopped 9) before tMSC_mon a data frame must be received, otherwise DIAREG6 must be read out to clear MSC_MON failure bit. 10) OTW still active in OTSD, no new diagnostic entry when changing from OTW to OTSD 11) Only if this timer has expired and failure occurs Description: - : no influence x : influence possible, refer to corresponding chapter in this specification Data Sheet 51 Rev. 1.1, 2012-07-31 TLE 8718 SA Micro Second Channel MSC 11 Micro Second Channel MSC Bidirectional micro second channel (MSC) is used for communication with micro controller. Via MSC, the micro controller controls the outputs and logic of the stage device including the diagnosis and monitoring module. Diagnosis data is requested by micro controller via downstream and returned by the device via MSC upstream channel. The MSC is a serial interface which is especially optimized to connect peripheral devices via serial link to micro controller. The serial communication link is built up by a fast synchronous downstream channel from micro controller to the stage device and an asynchronous upstream channel (referenced to downstream clock). The downstream interface can be "low voltage differential" (FCLN, FCLP, SIN, SIP) or "single ended" (FCL, SI, SSY). Multiple "power devices" with MSC on downstream are possible. Downstream device is selected by SSY. The MSC logic is supplied with VDD and referenced to PGND. If supply voltage of the device is below VDD_THL, downstream communication is possible with reduced FCL clock frequency only. Power on reset (VDD<VDD_POR) disables the MSC interface. TLE 8718SA Micro controller SSY MSC interface FCL Shift register 32 Bit FCLP FCLN Select / sync input Single ended Clock input Differential Downstream SI SIP SIN Asynchronous / synchronous receive buffer SDO Single ended Downstream data Differential Serial data output Drawing9_MSC_Interface .vsd Figure 17 Data Sheet MSC Interface (not tested, overview only) 52 Rev. 1.1, 2012-07-31 TLE 8718 SA Micro Second Channel MSC 11.1 Downstream Communication Downstream frames are synchronous serial frames with clock and data line. The physical interface for downstream communication can be "low voltage differential" or "single ended" type. Both interface types are using individual pins (FCL and SI or FCLN, FCLP, SIN and SIP) and common pins (SSY and SO). To select the interface, FLCN has to be connected either to PGND (for single ended type) or to a voltage within the defined input voltage range (for low voltage differential type) (see Item 11.5.7). The unused pins are connected to PGND (FCLN, FCLP, FCL, SIP, SIN) or to VDD (SI). Differential inputs for downstream data are SIP and SIN; the differential input signal SIP - SIN is the same logical signal as SI. The clock pins are FCLP and FCLN, the differential clock FCLP - FCLN is the same logical signal as FCL. There is one input for select/sync at SSY, and one output for upstream data at SDO. The stage device is always the slave in this communication link. The SSY signal enables receiver circuits automatically during a downstream frame transmission. Two types of downstream frames are defined: * * Command frames (selection bit ="1") Data frames (selection bit ="0") The device MSC uses non inverting polarity for SI and FCL: SI changes its state with the rising edge of FCL and is sampled with the falling edge; a logic `1' is a `high level' on SI, and a logic `0' is a `low level' on SI. Data at SI is latched by device on the falling edge of FCL. The SSY input is active low during the active phases of command or data frames. An active enable signal validates the SI input signal. Outside the active phase (SSY line is at high level) data at SI is ignored. By this way it is possible to drive multiple "power devices" with shared FCL and SI lines and individual SSY signal. Command frames and data frames may be sent in any sequence (with a passive phase of at least 2 FCL-cycles after each frame). Table 22 Execution of commands Event on MSC downstream upstream busy upstream idle valid read command frame ignored executed valid write command frame executed executed valid data frame accepted accepted invalid command frame ignored ignored invalid data frame ignored ignored The serial clock FCL is active (toggling) continuously ("FCL continuous mode") even when no command frame or data frame is transmitted. It is used to generate the upstream clock. The clock period of FCL is defined as tFCL, maximum downstream clock rate is fFCLmax. The active phase of a downstream frame starts with the falling edge of the signal on SSY and ends with the rising edge. SSY changes its state with the rising edge of clock FCL. After a power-on-reset or RST returns to logical high level for device normal operation, the MSC interface is fully functional after a maximum of 8 clock pulses on FCL respectively FCLP and FCLN. Data Sheet 53 Rev. 1.1, 2012-07-31 TLE 8718 SA Micro Second Channel MSC 11.1.1 Voltage Level Diagrams of low voltage differential pins This figure shows SIP and SIN function but is also valid for FCLP and FCLN VSIN, VSIP [V] Not defined VSIN(max), VSIP(max) SIP VSIx_low(min) VSIx_low(max) VSIx_high(min) VSIx_high(max) SIN VSIN(min), VSIP(min) Not defined t [s] Logic function 1 0 1 t [s] VSIN, VSIP [V] VSIN(max), VSIP(max) VSINx_off(max) SIP SIN VSINx_off(min) VSIN(min), VSIP(min) t [s] Logic function 1 0 1 1 0 1 1 0 1 1 0 1 X X X X X X t [s] Drawing10_Voltage _level_diagram.vsd Figure 18 Voltage level diagram 11.1.2 Downstream Supervisory Functions A command- or data frame is interpreted as valid, if it has the correct number of clock pulses (a frame has a length of 17 clock pulses). Clock pulses are counted at the falling edge of the signal. There is no parity check. If device receives no valid data frame for t > tMSC_mon, the device will switch off the output stages (exception: OUT15 or OUT16 if configured to delayed reset behavior and set the bit MSC_MON in DIAREG6 to `0'. 11.1.3 Command Frame A command frame always starts with a high level bit (command selection bit). The number of bits of the active phase of a command frame NCB is fixed to 17. A command is executed only if the number of the command bits is equal to NCB = 17. The length of the command frame's passive phase tCPP must be a minimum of 2 * tFCL (2 clock pulses). Alternatively the passive phase can consist in tCPP = tFCL (1 clock pulse) followed by a frame of wrong length (4...8 bits, with or without SSY active low) and a second tCPP = tFCL (1 clock pulse). Data Sheet 54 Rev. 1.1, 2012-07-31 TLE 8718 SA Micro Second Channel MSC Command frame passive phase active phase shift sample tFCL FCL SI invalid 1 command bits C0 ... C4 command data bits CD0 ... CD7 don 't care invalid selection bit (1=command) SSY tCPP active Drawing11_MSC_command_frame.vsd Figure 19 MSC command frame Content of a command frame (LSB transmitted first) Table 23 Command frame Bit # Description 0 (first bit) = `1': command selection bit 1...5 Command [C0...C4] 6...13 Data for the command [CD0...CD7] 14...16 don't care 3 bits The least significant (LSB) bit of a command is transmitted first. 11.1.4 Data Frame A data frame always starts with a low level bit (data selection bit). The number of the bits of the active phase of a data frame NDB is fixed to 17 bit. A data frame is accepted if the actual length is the expected length NDB. MSC Monitoring tMSC_mon is re-triggered by any data frame with correct length (no other error detection mechanism is implemented). The length of the data frame's passive phase tDPP must be a minimum of 2 * tFCL (2 clock pulses). Alternatively the passive phase can consist in tDPP = tFCL (1 clock pulse) followed by a frame of wrong length (4...8 bits, with or without SSY active low) and a second tDPP = tFCL (1 clock pulse). Data Sheet 55 Rev. 1.1, 2012-07-31 TLE 8718 SA Micro Second Channel MSC data frame passive phase active phase shift sample tFCL FCL SI invalid 0 invalid OUTREG data bits 1 ... 16 selection bit (0=data) SSY tDPP active Drawing12_MSC_data_frame.vsd Figure 20 MSC data frame There is no parity bit in the data frame. Table 24 Data frame OUTREG Bit Description 0 (first bit) = `0': data selection bit (R-A 1.5.3) 1 OUT1 stage data1) 2 OUT3 stage data1) 3 OUT5 stage data1) 4 OUT7 stage data1) 5 OUT9 stage data1) 6 OUT11 stage data1) 7 OUT13 stage data1) 8 OUT17 stage data1) 9 OUT2 stage data1) 10 OUT4 stage data1) 11 OUT6 stage data1) 12 OUT8 stage data1) 13 OUT10 stage data1) 14 OUT12 stage data1) 15 OUT14 stage data1) 16 OUT18 stage data1) 1) The control bit is non inverting, i.e. if a control bit is `1' the corresponding stage is off. The stages OUT15 and OUT16 are accessed by command frame (WR_OUT1516) due to their optional special functions (delayed reset behavior on ABE, RST, ...). The data is stored in register OUTREG. Data Sheet 56 Rev. 1.1, 2012-07-31 TLE 8718 SA Micro Second Channel MSC 11.2 Upstream Communication The serial data output [SDO] is the synchronous serial data signal of the upstream channel. The polarity for [SDO] is `non inverting polarity`- i.e. a low level bit at [SDO] is stored in the micro controller as a logic `0`, and a high level bit at [SDO] is stored in the micro controller as a logic `1`. TLE8718SA Micro controller SO FCL Downstream Channel SI FCL Divider Divider SI Upstream Channel SDO Shift Control Drawing13_MSC upstream communication .vsd Figure 21 MSC upstream communication (not tested, overview only, Single Ended) The serial data output (SDO) is single-ended. The frequency for SDO is derived from FCL (or FCLN/FCLP) by an internal divider and can be configured via MSC. Read request for 1 register Read request for 2 registers read requests are ignored during a running upstream write requests and data frames are executed , SSY During tMSC_RSP all requested registers are copied into a shadow register from where they are upstreamed via SDO. 8 bit data field tMSC_RSP tMSC_RSP Requested diagnostic registers are deleted after they are copied to the shadow register. fSDO SO Start UD0 UD7 Stop Stop Stop UD1 UD2 UD3 UD4 UD5 UD6 Parity bit bit bit bit LSB MSB Start UD0 UD7 Stop Stop Stop Start UD0 UD7 Stop Stop Stop UD1 UD2 UD3 UD4 UD5 UD6 Parity UD1 UD2 UD3 UD4 UD5 UD6 Parity bit bit bit bit LSB bit bit bit bit LSB MSB MSB 13 bit upstream data frame 13 bit upstream data frame 13 bit upstream data frame Drawing14_MSC upstream frame .vsd Figure 22 MSC upstream frame Table 25 Upstream frame Bit description 0 start bit, always `0' 1-8 upstream data bits UD0...7 9 parity bit (The parity bit is set in order to achieve an even number of `1' in Bits UD0...7+Parity) 10, 11, 12 stop bits, always `1' Transmission of the registers via upstream starts within tMSC_RSP after read command has been received. If a read command is received the device will ignore further read commands until the upstream data transfer is finished. A new read command is accepted if the rising edge SSY arrives after the last stop bit has been sent. Write commands or data frames are executed independently of ongoing read requests. If the write command is changing the register which is in transmission, the old register content will be sent (see Figure 22). Data Sheet 57 Rev. 1.1, 2012-07-31 TLE 8718 SA Micro Second Channel MSC 11.3 Timing Characteristics 1/fFCL FCL t setup t hold SI // tswitch t SSYsetup tSSYhold // SSY t MSC_RSP SDO Drawing16_MSC_timing.vsd Figure 23 MSC timing The downstream clock within the device is always running; each upstream data frame (i.e. each answer to a READ command) is synchronized with this clock. The upstream response time tMSC_RSP describes the time between end of read command (rising edge of SSY) to beginning of up-stream communication (falling edge of start bit). 11.4 Internal Clock Signal The MSC interface is synchronously clocked by the external MSC clock signal (FCL or FCLN/FCLP). If this clock signal is missing the communication is halted. All other functions of the circuit are available independently of an external MSC clock signal FCL or FCLN/FCLP. The internal clock source is used for: * * * * * * Diagnosis filtering Self protection Reset extension MSC data stream supervisory Delayed reset behavior of OUT15 and OUT16 Delayed disabling inputs (DIS5_10, DELAYIN) The internal clock signal is generated independently from MSC clock (FCL or FCLN/FCLP). The internal oscillator is functional in undervoltage VDD_THL above VDD_POR. By this way it is guaranteed that in undervoltage condition or during micro controller reset the diagnostic filters (e.g. stage shut off on SCB) and the delayed reset of OUT15 and OUT16 are functional. Data Sheet 58 Rev. 1.1, 2012-07-31 TLE 8718 SA Micro Second Channel MSC 11.5 Electrical Characteristics Table 26 Micro Second Channel 4.5V < VDD < 5.5V, 4.5V < VBAT < 40V, all voltages with respect to PGND, positive current flowing into pin., Tj = -40C to +150C, unless otherwise specified Pos. Parameter Symbol Values Unit TC Conditions min. typ. max. fINT 0.7 - 1.1 MHz C - VSSY_low VSSY_high VSSY_hys CSSY ISSY -0.3 - 0.8 V B - 1.6 - 36 V B - 0.1 - 0.5 V C - - - 10 pF C - -100 - -10 A A 0V<VSSY<2V VFCLP, VFCLN VFCLx_high 0.8 - 1.6 V C - 25 - 125 mV C - 11.5.9 Differential input low detection level, VFCLx_low=VFCLP-VFCLN VFCLx_low -125 - -25 mV C - 11.5.10 Input voltage offset, VFCLx_off=0.5*(VFCLP+VFCLN) VFCLx_off 1.05 - 1.4 V C - - - 8 pF C - Internal Clock 11.5.1 Frequency of internal clock Pin SSY 11.5.2 Input comparator low level 11.5.3 Input comparator high level 11.5.4 Input comparator hysteresis 11.5.5 Input capacitance 11.5.6 Input current Internal pull up current source to VDD Pins FCLP, FCLN 11.5.7 Input voltage range 11.5.8 Differential input high detection level, VFCLx_high=VFCLP-VFCLN 11.5.11 Differential capacitance between; FCLP CFCLx and FCLN 11.5.12 FCLP Input pull up current; FCLP: internal pull up current source; IFCLP -25 - -3 A A 0V<VFCLP<2V 11.5.13 FCLN Input pull down current; FCLN: internal pull down current source IFCLN 6 - 50 A A 1V<VFCLN<VDD - 0.4 V B - - 36 V B - Single ended/Differential selection 11.5.14 FCLN low level for MSC "single ended selection" 11.5.15 FCLN high level for MSC "low voltage differential selection" VFCLN_sel_l -0.3 ow VFCLN_sel_h 0.8 igh Pin FCL 11.5.16 FCL input low voltage 11.5.17 FCL input high voltage 11.5.18 FCL input hysteresis 11.5.19 FCL Input current. Internal pull down current source to PGND; VFCL_low VFCL_high VFCL_hys IFCL -0.3 - 0.8 V B - 1.6 - 36 V B - 0.1 - 0.5 V C - 10 - 100 A A 1V<VFCL<VDD fFCLx 4 - 23 MHz B Clock Frequency 11.5.20 FCLP, FCLN frequency VDD_POR<VDD< 5.5V Data Sheet 59 Rev. 1.1, 2012-07-31 TLE 8718 SA Micro Second Channel MSC Table 26 Micro Second Channel 4.5V < VDD < 5.5V, 4.5V < VBAT < 40V, all voltages with respect to PGND, positive current flowing into pin., Tj = -40C to +150C, unless otherwise specified Pos. Parameter 11.5.21 FCL frequency Symbol fFCL Values min. typ. max. 4 - 12.5 Unit TC Conditions MHz B VDD_POR<VDD< 5.5V Pins SIP, SIN VSIP, VSIN 0.8 VSIx_high 25 - 1.6 V C - - 125 mV C - 11.5.24 Differential input low detection level, VSIx_low=VSIP-VSIN VSIx_low -125 - -25 mV C - 11.5.25 Input voltage offset, VSIx_Off=0.5*(VSIP+VSIN) VSIx_Off 1.05 - 1.4 V C - 11.5.26 Differential capacitance between SIP and SIN CSIx - - 8 pF C - -25 - -3 A A 0V<VSIP<2V 6 - 50 A A 1V<VSIN<VDD -0.3 - 0.8 V B - 1.6 - 36 V B - 0.1 - 0.5 V C - -100 - -10 A A 0V<VSI<2V 11.5.22 Input voltage range 11.5.23 Differential input high detection level, VSIx_high=VSIP-VNSI 11.5.27 Input pull up current; SIP: internal pull up ISIP current source 11.5.28 Input pull down current; SIN: internal pull down current source to PGND ISIN Pin SI VSI_low 11.5.30 SI input high voltage VSI_high 11.5.31 SI input hysteresis VSI_hys 11.5.32 SI Input current; Internal pull up current ISI source to VDD 11.5.29 SI input low voltage Pin SDO 11.5.33 SDO output low level 11.5.34 SDO passive output high voltage VSDO_low; VSDO_low - - 0.8 V C - - 0.4 V A ISDO<4mA; ISDO<1mA VSDO_high VDD - VDD - V C no load 1.5 11.5.35 Maximum current (short circuit limited current)1) ISDO_max 15 - - mA C - 11.5.36 SDO pull-up current source ISDO_high -50 - -10 A A 0V<VSDO<2V, 11.5.37 SDO (high level = inactive) pin capacity CSDO 11.5.38 SDO frequency; maximum upstream frequency with external pull-up Data Sheet fSDO 2) - - 10 pF C 550 - - kHz C measured with bias voltage of 1V 1k and CL=50pF 60 Rev. 1.1, 2012-07-31 TLE 8718 SA Micro Second Channel MSC Table 26 Micro Second Channel 4.5V < VDD < 5.5V, 4.5V < VBAT < 40V, all voltages with respect to PGND, positive current flowing into pin., Tj = -40C to +150C, unless otherwise specified Pos. Parameter Symbol Values Unit TC Conditions min. typ. max. thold tsetup tswitch tFCLlow tFCLhigh tSSYsetup tSSYhold tMSC_mon tMSC_RSP 10 - - ns C - 10 - - ns C - - - 3 ns C - 13 - - ns C - 13 - - ns C - 5 - - ns C - 17 - - ns C - 60 - 135 s B - - - 100 s C fFCL or fFCLx=4MHz 11.5.48 Required idle time after command tCPP - 2/fFCL (2 clock pulses) - s C - 11.5.49 Required idle time after data frame tDPP 2/fFCL - (2 clock pulses) - s C - Timing Characteristics 3) 11.5.39 Data hold time 11.5.40 Data Setup time 11.5.41 Switching time 11.5.42 FCL low time 11.5.43 FCL high time 11.5.44 SSY setup time 11.5.45 SSY hold time 11.5.46 MSC data timeout monitoring 11.5.47 MSC upstream response time; upstream divider independent (CONREG4_FCL_CONFx) 1) Integrated protection functions are designed to prevent IC destruction under fault conditions. Fault conditions are considered as "outside" normal operating range. Protection functions are not designed for continuous or repetitive operation. Application must take care, that current into this pin does not exceed 15mA. 2) SDO as Output is not active 3) See Figure 19, Figure 20 and Figure 23. Data Sheet 61 Rev. 1.1, 2012-07-31 TLE 8718 SA Control of the device 12 Control of the device 12.1 Commands Table 27 Command Overview Command SB C0...4 CD0...7 DC Description - 1 00000 xxxx xxxx xxx Invalid command WR_CONREG1 1 10000 CD0...7 xxx Configuration of switch off or current control by SCB for OUT1...8 WR_CONREG2 1 01000 CD0...7 xxx Configuration of switch off or current control by SCB for OUT9...14, 17, 18 - 1 11000 xxxx xxxx xxx Invalid command WR_CONREG3 1 00100 CD0...7 xxx Configuration of diagnostic pull-down current and Open Load OL of OUT11...14, 17, 18, DELAYIN_FIL and EXT_SCB - 1 10100 xxxx xxxx xxx Invalid command - 1 01100 xxxx xxxx xxx Invalid command WR_OUT1516 1 11100 CD0...7 xxx Configuration of OUT 15, 16, switch off or current control by SCB for OUT15, 16, configuration of diagnostic pull-down current and Open Load OL. Special behavior (time delay) WR_RST 1 00010 xxxx xxxx xxx Soft reset via MSC (clear diagnostic registers) - 1 10010 xxxx xxxx xxx Invalid command - 1 01010 xxxx xxxx xxx Invalid command WR_START 1 11010 xxxx xxxx xxx Enable OUT1...14, OUT17 and OUT18 - 1 00110 xxxx xxxx xxx Invalid command WR_CONREG4 1 10110 CD0...7 xxx Configuration of DELAYIN delay, upstream frequency divider and VDD monitoring WR_TESTREG 1 01110 CD0...7 xxx For factory tests only. Do not use this command. - 1 11110 xxxx xxxx xxx Invalid command RD_CONFIG 1 00001 CD0...7 xxx Request content of configuration registers CONREG1...4, OUT1516, TESTREG - 1 10001 xxxx xxxx xxx Invalid command - 1 01001 xxxx xxxx xxx Invalid command RD_DATA 1 11001 CD0...7 xxx Request content of diagnostic registers DIAREG1...7 and IDENTREG - 1 00101 xxxx xxxx xxx Invalid command - 1 10101 xxxx xxxx xxx Invalid command - 1 01101 xxxx xxxx xxx Invalid command - 1 11101 xxxx xxxx xxx Invalid command - 1 00011 xxxx xxxx xxx Invalid command - 1 10011 xxxx xxxx xxx Invalid command WR_FUSE_SC 1 01011 CD0...7 xxx Active during factory test mode only. For factory tests only. Do not use this command. - 1 11011 xxxx xxxx xxx Invalid command Data Sheet 62 Rev. 1.1, 2012-07-31 TLE 8718 SA Control of the device Table 27 Command Overview Command SB C0...4 CD0...7 DC Description WR_SEL_THRES 1 00111 CD0...7 xxx Active during factory test mode only. For factory tests only. Do not use this command. - 1 10111 xxxx xxxx xxx Invalid command - 1 01111 xxxx xxxx xxx Invalid command - 1 11111 xxxx xxxx xxx Invalid command 12.1.1 WR_OUT1516 Table 28 Command WR_OUT1516 SB C CD0 1 OUT15_C OUT15_ ONTROL DELAY 11100 COMMAND- or DATA Frame (correct length ) CD1 DATA CD2 CD3 CD4 OUT15_ DIAC OUT15_ SCB OUT16_C OUT16_ ONTROL DELAY DATA POR DATA CMD* CD5 DATA CD6 CD7 DC OUT16_ DIAC OUT16_ SCB xxx CMD* DATA CMD* DATA DATA CMD does not re-trigger tMSC_MON tMSC _MON timer is not re-triggered tMSC_MON tMSC _MON timer is re-triggered in-time POR, RST or read DIAREG 6 re-sets DIAREG6.MSC_MON DIAREG6. MSC_MON OUT15 or 16 (standard switch-off) *: CMD WR_OUT1516 *: CMD .CD0 or.CD4 = ON WR_OUT1516 not valid because DIAREG6.MSC_MON .CD0 or.CD4 = ON valid not set *: CMD WR_OUT1516 .CD0 or.CD4 = ON valid OFF ON tDELRES OUT15 or 16 (delayed switch-off) OFF ON WR_OUT1516 _after _POR .vsd Figure 24 Data Sheet OUT1516 after Power ON (POR) and in dependency of tMSC_MON 63 Rev. 1.1, 2012-07-31 TLE 8718 SA Control of the device The MSC timeout counter is started from its initial state when POR and RST are released. The diagnosis flag DIAREG6.MSC_MON is initially set to `1'. Every valid data frame resets and restarts the MSC timeout counter as long as it has not expired. Hence data frames should be sent in intervals shorter than tMSC_mon. If no valid data frame is received within tMSC_mon, the MSC timeout counter will expire, clear the DIAREG6.MSC_MON flag and switch off the output stages. An exception may be OUT15/16 which are switched off after tDELRES if they are configured to delayed reset behavior. All other functions are not influenced by the MSC timeout, e.g. MSC upstream data transfer is not halted. Once the MSC timeout counter has expired a data frame will neither restart the timeout counter nor set the diagnosis flag nor turn on any output. In order to enable the output stages again after an MSC timeout the following steps are necessary: 1) DIAREG6 must be read to set the DIAREG6.MSC_MON bit and restart the MSC timeout counter. 2) Subsequent data frames or WR_OUT1516 commands are needed to switch on the outputs again. Command frames other than RD_DATA for DIAREG6 will neither influence the MSC timeout counter nor the DIAREG6.MSC_MON flag. The WR_OUT1516 output is a `high'-strobe after the command has been received. (See Figure 1) The tDELRES time-out counter generates a `low' pulse of tDELRES after the `Restart' input has been activated by `high' pulse. A `high' pulse on input `Discard' makes the timer expire without waiting for tDELRES, the output then is `high'level (failure will reset OUTn control register). The inputs of the OUTn-control flip-flop are active high and `R' is dominant, output is non inverting. OUT15 and OUT16 can be configured individually to delayed reset, only one timer (tDELRES) is needed as both outputs are accessed in the same command frame and no independent restart is possible. The functions are: * * * * switch OFF switch ON, no delay switch ON, restart timeout counter for delayed reset behavior keep state, restart timeout counter for delayed reset behavior 12.1.2 WR_RST Table 29 Command WR_RST SB C0...4 CD0...7 DC 1 00010 xxxx xxxx xxx The command triggers a soft reset via MSC. Diagnostic registers are cleared. If WR_RST command arrives during an up-stream burst, then all diagnostic registers are cleared. The incoming frame is sent with the uncleared content of the DIAREG and the rest of the frames are send with the cleared content. 12.1.3 WR_START Table 30 Command WR_START SB C0...4 CD0...7 DC 1 11010 xxxx xxxx xxx Data Sheet 64 Rev. 1.1, 2012-07-31 TLE 8718 SA Control of the device The command clears the bit OUTPUT_STBY = '0'. With OUTPUT_STBY ='1' the output registers OUTREG of OUT1...14, 17, 18 are reset. Control of OUT15 and 16 is still possible by register OUT1516. The OUTPUT_STBY bit is set by power-on-reset or by active low signal on pin RST. OUTPUT_STBY activated COMMAND- or DATA Frame (correct length ) DATA* CMD** DATA DATA DATA DATA DATA CMD** DATA DATA DATA CMD** DATA POR or RST CMD does not re-trigger tMSC _MON tMSC _MON timer is not re-triggered t MSC_MON tMSC _MON timer is re-triggered in-time POR or RST re -sets DIAREG6.MSC_MON DIAREG6. MSC_MON ** CMD WR_START re-sets DIAREG 6. OUTPUT_STBY DIAREG6. OUTPUT_STBY * DATA does not influence OUTn until WR_START has been send OUT1...14, 17, 18 ON or OFF dependent on content of DATA OFF OFF OUTPUT_STBY de-activated COMMAND- or DATA Frame (correct length ) DATA* CMD** DATA DATA DATA DATA CMD*** POR or RST CMD does not re-trigger tMSC _MON tMSC _MON timer is not re-triggered t MSC_MON tMSC _MON timer is re-triggered in-time *** CMD Read DIAREG 6 re-sets DIAREG 6. MSC_MON DIAREG6. MSC_MON ** CMD WR_START re-sets DIAREG 6. OUTPUT_STBY DIAREG6. OUTPUT_STBY ** CMD WR_START has no influence * DATA does not influence OUTn until WR_START has been send OUT1...14, 17, 18 OFF ON or OFF dependent on content of DATA OFF WR_START_OUTPUT_DTB.vsd Figure 25 Data Sheet Impact of WR_START to OUTPUT_STBY 65 Rev. 1.1, 2012-07-31 TLE 8718 SA Control of the device 12.1.4 RD_CONFIG Table 31 Command RD_CONFIG Register SB C0...4 CD0...7 DC CONREG1 1 xxxx xxx1 xxx 00001 CONREG2 xxxx xx1x CONREG3 xxxx x1xx CONREG4 xxxx 1xxx OUT1516 xxx1 xxxx not implemented xx1x xxxx OUTREG_EVEN x1xx xxxx OUTREG_ODD 1xxx xxxx The RD_CONFIG command requests the device to transmit configuration register content via MSC upstream. With the command data bit CD(0...7), it is masked which registers are to be transmitted. If more than one register is requested the transmission is made from CD7 down to CD0 (upstream transmission of CONREG1 first, CONREG2 second and so on). The request for a not implemented register is ignored. 12.1.5 RD_DATA Table 32 Command RD_DATA Register SB C0...4 CD0...7 DC DIAREG1 1 xxxx xxx1 xxx 11001 DIAREG2 xxxx xx1x DIAREG3 xxxx x1xx DIAREG4 xxxx 1xxx DIAREG5 xxx1 xxxx DIAREG6 xx1x xxxx DIAREG7 x1xx xxxx IDENTREG 1xxx xxxx The RD_DATA command requests the device to transmit diagnostic register content via MSC upstream. With the command data bit CD(0...7), it is masked which registers are to be transmitted. If more than one register is requested the transmission is made from CD7 down to CD0 (upstream transmission of DIAREG1 first, IDENTREG last). The Register which is sent on RD_DATA is deleted at the beginning of the transmission. Data Sheet 66 Rev. 1.1, 2012-07-31 TLE 8718 SA Control of the device 12.2 Registers 12.2.1 CONREG1 Table 33 CONREG1 Reset sources: RST, power-on-reset Controller read access: RD_CONFIG = '1 00001xxxx xxx1 xxx' Controller write access: WR_CONREG1 = '1 10000 CD0...CD7 xxx' UD/CD Name Description Reset value 0 OUT1_SCB 1 1 OUT2_SCB `1`: OUTn is switched off in case of SCB `0`: OUTn current limited mode in case of SCB 2 OUT3_SCB 1 3 OUT4_SCB 1 4 OUT5_SCB 1 5 OUT6_SCB 1 6 OUT7_SCB 1 7 OUT8_SCB 1 12.2.2 CONREG2 Table 34 CONREG2 1 Reset sources: RST, power-on-reset Controller read access: RD_CONFIG = '1 00001 xxxx xx1x xxx' Controller write access: WR_CONREG2 = '1 01000 CD0...CD7 xxx' UD/CD Name Description Reset value 0 OUT9_SCB 1 1 OUT10_SCB `1`: OUTn is switched off in case of SCB `0`: OUTn current limited mode in case of SCB 2 OUT11_SCB 1 3 OUT12_SCB 1 4 OUT13_SCB 1 5 OUT14_SCB 1 6 OUT17_SCB 1 7 OUT18_SCB 1 Data Sheet 67 1 Rev. 1.1, 2012-07-31 TLE 8718 SA Control of the device 12.2.3 CONREG3 Table 35 CONREG3 Reset sources: RST, power-on-reset Controller read access: RD_CONFIG = '1 00001 xxxx x1xx xxx' Controller write access: WR_CONREG3 = '1 00100 CD0...CD7 xxx' UD/CD Name Description Reset value 0 OUT11_DIAC 0 1 OUT12_DIAC `1`: OUTn diagnostic pull-down current and Open Load OL on `0`: OUTn diagnostic pull-down current and Open Load OL off 2 OUT13_DIAC 0 3 OUT14_DIAC 0 4 OUT17_DIAC 0 5 OUT18_DIAC 0 6 DELAYIN_FIL `1`: Long filter time for tDELAYIN_GLITCH_long selected `0`: Short filter time for tDELAYIN_GLITCH_short selected 7 EXT_SCB `1`: Extended SCB behavior of OUT5...OUT14 active (IOUTn and VOUTn 0 are taken into account) `0`: Default SCB behavior (only IOUTn is taken into account) 12.2.4 CONREG4 Table 36 CONREG4 0 1 Reset sources: RST, power-on-reset Controller read access: RD_CONFIG = '1 00001 xxxx 1xxx xxx' Controller write access: WR_CONREG4 = '1 10110 CD0...CD7 xxx' UD/CD Name Description Reset value 0 DELAYIN_CONF0 See table below: configuration of DELAYIN delay 1 1 DELAYIN_CONF1 See table below: configuration of DELAYIN delay 1 2 FCL_CONF0 See table below: divider settings for upstream frequency 1 3 FCL_CONF1 See table below: divider settings for upstream frequency 0 1) 4 ABE_IMPACT 1: ABE and VDD monitoring disables all Outputs with short delay 1 0: ABE and VDD monitoring disables all Outputs with long delay 5 MON_TEST `1`: VDD monitoring test inactive `0`: VDD monitoring test active 1 6 MON_THRES `1`: Test undervoltage threshold `0`: Test overvoltage threshold 1 7 MON_LATCH `1`: Overvoltage failure will be latched. Normal operation after reset, POR or by setting this bit to `0' `0`: Device returns to normal operation after overvoltage 1 1)In case of undervoltage of VDD, specification is not fulfilled: e.g. protection functions might not work. (OUT= 1...14,17,18) Data Sheet 68 Rev. 1.1, 2012-07-31 TLE 8718 SA Control of the device Table 37 CONREG4, DELAYIN configuration Configuration of tDELAYIN_x delay DELAYIN_CONF1 DELAYIN_CONF0 Description 1 1 Long delay tDELAYIN_L, see Item 7.0.16 0 1 Medium long delay tDELAYIN_ML, see Item 7.0.17 1 0 Medium short delay tDELAYIN_MS, see Item 7.0.18 0 0 Short delay tDELAYIN_S, see Item 7.0.19 CONREG4, Upstream divider configuration1) Table 38 Configuration of upstream clock divider FCL_CONF1 FCL_CONF0 Description 1 0 Upstream clock is fFCL/128 0 1 Upstream clock is fFCL/64 0 0 Upstream clock is fFCL/32 1 1 Upstream clock is fFCL/16 1) Take care that Item 11.5.38 fSDO is not exceeded. 12.2.5 OUT1516 Table 39 OUT1516 Reset sources: RST, power-on-reset, ABE, over-/undervoltage, OUT1516 timeout 1), MSC_MON, RES15_16 Controller read access: RD_CONFIG = '1 00001 xxx1 xxxx xxx' Controller write access: WR_ OUT1516 = '1 11100 CD0...CD7 xxx' UD/CD Name Description Reset value 0 OUT15_CONTROL See table "Output stage switching" below 12) 1 OUT15_DELAY See table "Output stage switching" below 12) 2 OUT15_DIAC `1`:OUT15 diagnostic pull-down current and Open Load OL on `0`:OUT15 diagnostic pull-down current and Open Load OL off 0 3 OUT15_ SCB `1`: OUT15 is switched off in case of SCB `0`: OUT15 current limited mode in case of SCB 1 4 OUT16_CONTROL See table "Output stage switching" below 12) 5 OUT16_DELAY See table "Output stage switching" below 12) 6 OUT16_DIAC `1`:OUT16 diagnostic pull-down current and Open Load OL on `0`:OUT16 diagnostic pull-down current and Open Load OL off 0 7 OUT16_ SCB `1`: OUT16 is switched off in case of SCB `0`: OUT16 current limited mode in case of SCB 1 1) Timeout tdelres only resets the register if another failure (RST, ABE, over-/undervoltage, MSC-timeout) is still present. POR and the filtered RES15_16 resets the register immediately. 2) After POR has occurred or RES15_16 is released OUT15, OUT16 starts in OFF- state. OUTn_DELAY, OUTn_CONTROL reset Values remain ='1' Data Sheet 69 Rev. 1.1, 2012-07-31 TLE 8718 SA Control of the device Table 40 OUT1516, Delay configuration Output stage switching OUTn_DELAY OUTn_CONTROL Description 1 1 keep state, restart timeout counter for delayed reset behavior 0 1 switch OFF 1 0 switch ON, restart timeout counter for delayed reset behavior 0 0 switch ON, no delay 12.2.6 OUTREG_EVEN Table 41 OUTREG_EVEN Reset sources: RST, power-on-reset, ABE, over-/undervoltage, MSC_MON, OUTPUT_STBY Controller read access: RD_CONFIG = '1 00001 x1xx xxxx xxx' Controller write access: Data Frame = '0 x UD0 x UD1 x UD2 x UD3 x UD4 x UD5 x UD6 x UD7' UD Name Description Reset value 0 OUT2 0 1 OUT4 `1`: OUTREG of OUTn is set to "ON"1) `0`: OUTREG of OUTn is set to "OFF" 2 OUT6 0 3 OUT8 0 4 OUT10 0 5 OUT12 0 6 OUT14 0 7 OUT18 0 0 1) OUTREG_EVEN contains the inverted status of what is programmed via a data frame into OUTREG. 12.2.7 OUTREG_ODD Table 42 OUTREG_ODD Reset sources: RST, power-on-reset, ABE, over-/undervoltage, MSC_MON, OUTPUT_STBY Controller read access: RD_CONFIG = '1 00001 1xxx xxxx xxx' Controller write access: Data Frame = '0 UD0 x UD1 x UD2 x UD3 x UD4 x UD5 x UD6 x UD7 x' UD Name Description Reset value 1) 0 OUT1 1 OUT3 `1`: OUTREG of OUTn is set to "ON" `0`: OUTREG of OUTn is set 0 to "OFF" 0 2 OUT5 0 3 OUT7 0 4 OUT9 0 5 OUT11 0 6 OUT13 0 7 OUT17 0 1) OUTREG_ODD contains the inverted status of what is programmed via a data frame into OUTREG. Data Sheet 70 Rev. 1.1, 2012-07-31 TLE 8718 SA Control of the device 12.2.8 DIAREG1 Table 43 DIAREG1 Reset sources: RST, power-on-reset, WR_RST, RD_DATA = '1 11001 xxxx xxx1 xxx' Controller read access: RD_DATA = '1 11001 xxxx xxx1 xxx' Controller write access: UD Name Description Reset value 0 OUT1_DIA1 See Table 44 1 1 OUT1_DIA2 1 2 OUT2_DIA1 1 3 OUT2_DIA2 1 4 OUT3_DIA1 1 5 OUT3_DIA2 1 6 OUT4_DIA1 1 7 OUT4_DIA2 1 Table 44 Encoding of diagnosis information Encoding of the diagnosis bits of the device OUTn_DIA2 OUTn_DIA1 description 1 1 Power stage ok 1 0 Short circuit to battery (SCB) or diagnostic overtemperature (DOT) 0 1 Open load (OL)1) 0 0 Short circuit to ground (SCG) 1) OL only available when OUTn_DIAC='1' 12.2.9 DIAREG2 Table 45 DIAREG2 Reset sources: RST, power-on-reset, WR_RST, RD_DATA = '1 11001 xxxx xx1x xxx' Controller read access: RD_DATA = '1 11001 xxxx xx1x xxx' Controller write access: UD Name Description Reset value 0 OUT5_DIA1 See Table 44 1 1 OUT5_DIA2 1 2 OUT6_DIA1 1 3 OUT6_DIA2 1 4 OUT7_DIA1 1 5 OUT7_DIA2 1 6 OUT8_DIA1 1 7 OUT8_DIA2 1 Data Sheet 71 Rev. 1.1, 2012-07-31 TLE 8718 SA Control of the device 12.2.10 DIAREG3 Table 46 DIAREG3 Reset sources: RST, power-on-reset, WR_RST, RD_DATA = '1 11001 xxxx x1xx xxx' Controller read access: RD_DATA = '1 11001 xxxx x1xx xxx' Controller write access: UD Name Description Reset value 0 OUT9_DIA1 See Table 44 1 1 OUT9_DIA2 1 2 OUT10_ DIA1 1 3 OUT10_ DIA2 1 4 OUT11_ DIA1 1 5 OUT11_ DIA2 1 6 OUT12_ DIA1 1 7 OUT12_ DIA2 1 12.2.11 DIAREG4 Table 47 DIAREG4 Reset sources: RST, power-on-reset, WR_RST, RD_DATA = '1 11001 xxxx 1xxx xxx' Controller read access: RD_DATA = '1 11001 xxxx 1xxx xxx' Controller write access: UD Name Description Reset value 0 OUT13_DIA1 See Table 44 1 1 OUT13_DIA2 1 2 OUT14_DIA1 1 3 OUT14_DIA2 1 4 OUT15_DIA1 1 5 OUT15_DIA2 1 6 OUT16_DIA1 1 7 OUT16_DIA2 1 Data Sheet 72 Rev. 1.1, 2012-07-31 TLE 8718 SA Control of the device 12.2.12 DIAREG5 Table 48 DIAREG5 Reset sources: RST, power-on-reset, WR_RST, RD_DATA = '1 11001 xxx1 xxxx xxx' Controller read access: RD_DATA = '1 11001 xxx1 xxxx xxx' Controller write access: UD Name Description Reset value 0 OUT17_DIA1 See Table 44 1 1 OUT17_DIA2 1 2 OUT18_DIA1 1 3 OUT18_DIA2 4 REVCUR_FLAG `1`:Common Reverse Current Flag OUT1...18, no reverse current 1 `0`:Common Reverse Current Flag OUT1...18, Reverse current any stage for longer than tREVCUR 5 OUT15_STATUS `0`: OUT15 is ON1) `1`: OUT15 is OFF 02) 6 OUT16_STATUS `0`: OUT16 is ON1) `1`: OUT16 is OFF 02) 7 RES15_16_STATUS `0`: DELAYIN > VRES15_16_H for longer than tDELAYIN_GLITCH_x `1`: DELAYIN < VRES15_16_L 1 12) 1) '1'=OFF: Channel is currently either in OFF-state (State A, C or D, see Figure 12), during falling edge or in clamping `0`=ON: Channel is currently either in ON-state (State B, see Figure 12), during rising edge or in current limitation. 2) Register data is asynchronously written and not latched by the device (status). Data Sheet 73 Rev. 1.1, 2012-07-31 TLE 8718 SA Control of the device 12.2.13 DIAREG6 Table 49 DIAREG6 Reset sources: RST, power-on-reset Controller read access: RD_DATA = '1 11001 xx1x xxxx xxx' Controller write access: UD Name Description Reset value 0 OUTPUT_STBY `1`: Outputs (1...14, 17, 18) disabled until command WR_START. `0`: Output stages active, following MSC register data Bit can be set = `0' by command WR_START only (see Chapter 12.1.3, Figure 25) 1 1 MSC_MON `1`: No MSC monitoring timeout detected `0`: Timeout: MSC monitoring has detected a transmission failure and power stages are switched off (see Chapter 5.1,Table 21, Chapter 11.1.2, Item 11.5.46) By activating the MSC communication this bit is not reset, only readout of DIAREG6 or power-on-reset (POR) or RST will enable output stages after MSC_MON has detected a failure. 1 2 POR_FLAG `1`: Power-on-reset (POR) has happened. Bit is set by power-onreset only `0`: No POR since last readout. Bit is reset after RST or readout RST and RD_DATA = `0'; POR = `1' 3 ABE_STATUS `1`: ABE inactive `0`: ABE active low disabling output stages 01) 4 FAILURE_FLAG `1`: Common failure flag OUT1...18, no failure `0`: Common failure flag OUT1...18, any stage 11) 5 COTW 1 `1`: Overtemperature flag OUT1...18, no DOT `0`: Overtemperature flag OUT1...18, DOT any stage This bit is latched, remaining '0' after DOT disappears until register is reset by RST, POR or RD_DATA. 6 DIS5_10_STATUS `1`: DIS5_10 > VDIS5_10_H for longer than tDIS5_10 `0`: DIS5_10 < VDIS5_10_L for longer than tDIS5_10 01) 7 DELAYIN_STATUS `1`: DELAYIN > VDELAYIN_H for longer than tDELAYIN_GLITCH_x `0`: DELAYIN < VDELAYIN_L for longer than tDELAYIN_x 01) 1) Register data is asynchronously written and not latched by the device (status). Data Sheet 74 Rev. 1.1, 2012-07-31 TLE 8718 SA Control of the device 12.2.14 DIAREG7 Table 50 DIAREG7 Reset sources: Controller read access: RD_DATA = '1 11001 x1xx xxxx xxx' Controller write access: UD Name 0 Description Reset value not implemented 1 1 1 2 1 3 STATUS_SVBATT `1`: No overvoltage detected by SVBATT monitoring `0`: Overvoltage detected by SVBATT monitoring 11) 4 TEST_ACTIVE Device is currently `1': in normal operation `0': factory test mode is active 11) 5 STATUS_OV `1`: No overvoltage detected by VDD monitoring OV detection may be configured to be latched. `0`: Overvoltage detected by VDD monitoring 11)2) 6 STATUS_UV `1`: No under voltage detected by VDD monitoring `0`: Under voltage detected by VDD monitoring 01) 7 MON_TEST `1`: VDD monitoring test inactive `0`: VDD monitoring test active 11)3) 1) Register data is asynchronously written and not latched by the device (status). 2) Dependent on CONREG4, bit 7 setting, see Figure 16. 3) Same as CONREG4, bit 5 Data Sheet 75 Rev. 1.1, 2012-07-31 TLE 8718 SA Control of the device 12.2.15 IDENTREG Table 51 IDENTREG Reset sources: Controller read access: RD_DATA = ' 1 11001 1xxx xxxx xxx' Controller write access: UD Name Description Software revision 0 SW_REV0 1 SW_REV1 A-step: SW_REV1 SW_REV0 0 0 B-step: 0 1 C-step: 1 0 D-step: 1 1 CHIP_REV2 CHIP_REV1 CHIP_REV0 Chip Revision 2 CHIP_REV0 3 CHIP_REV1 A-step: 0 0 0 4 CHIP_REV2 B-step: 0 0 1 C-step: 0 1 0 D-step 0 1 1 E-step: 1 0 0 IDENT2 IDENT1 IDENT0 1 0 0 Chip identifier 5 IDENT0 6 IDENT1 7 IDENT2 TLE8718SA: CHIP_REV is increased for "major" design changes. SW_REV is increased for "minor" changes within each CHIP_REV separately. Data Sheet 76 Rev. 1.1, 2012-07-31 TLE 8718 SA Control of the device 12.2.16 TESTREG For factory tests only. Do not use this command. . Table 52 TESTREG Reset Sources: RST, power-on-reset Controller read access: Controller write access: WR_TESTREG = '1 01110 CD0...CD7 xxx' CD Name Description Reset value 0 TEST1 reserved for factory test mode 1 1 TEST2 1 2 TEST3 1 3 TEST4 1 4 TEST5 1 5 TEST6 1 6 TEST7 1 7 TEST8 1 To enter in the test mode, a negative voltage on SVBATT (see Item 6.4.10) has to be applied together with a WR_TESTREG. To leave the test mode, a RST or POR has to be performed. 12.2.17 SEL_THRES Table 53 SEL_THRES Reset Sources: RST, power-on-reset Controller read access: Controller write access: WR_SEL_THRESH = '1 00111 CD0...CD7 xxx' CD Name Description Reset value 0 SEL_TRESH0 active only during factory test mode 1 1 SEL_TRESH1 1 2 SEL_TRESH2 1 3 SEL_TRESH3 1 4 SEL_TRESH4 1 5 SEL_TRESH5 1 6 SEL_TRESH6 1 7 SEL_TRESH7 1 Data Sheet 77 Rev. 1.1, 2012-07-31 TLE 8718 SA Control of the device 12.2.18 FUSE_SC Table 54 FUSE_SC Reset Sources: RST, power-on-reset Controller read access: Controller write access: WR_FUSE_SC = '1 01011 CD0...CD7 xxx' CD Name Description Reset value 0 FUSE_SC0 active only during factory test mode 0 1 FUSE_SC1 0 2 FUSE_SC2 0 3 FUSE_SC3 0 4 FUSE_SC4 0 5 FUSE_SC5 0 6 FUSE_SC6 0 7 FUSE_SC7 0 Data Sheet 78 Rev. 1.1, 2012-07-31 TLE 8718 SA Application Information 13 Application Information V BAT Reverse Polarity Protection Supply 5V V BAT 47F 100 nF 47nF *5 PCBConnector LLOAD Logic 4.7nF *3 100 RLOAD OUT1 SIN 8A/55V from micro controller *2 5V 3A/55V FCLP from micro controller 100 FCLN from micro controller FCL *2 OUT4 OUT5 4.7nF *3 OUT6 4.7nF *3 OUT7 4.7nF *3 OUT8 4.7nF *3 OUT9 4.7nF *3 OUT10 4.7nF *3 OUT11 4.7nF *3 OUT12 4.7nF *3 OUT13 4.7nF *3 OUT14 4.7nF *3 OUT15 4.7nF *3 OUT16 4.7nF *3 OUT17 4.7nF *3 OUT18 4.7nF *3 2.2A/55V 2.2A/55V 5k 2.2A/55V SDO to micro controller 2.2A/55V DIS5_10 2.2A/55V Enable 2.2A/55V to micro controller 3k *1 DELAYIN/OUT DELAYIN 47nF *5 3.3 or 5V 5k DELAYOUT 2.2A/55V 2.2A/55V 2.2A/55V to micro controller 2.2A/55V RST from micro controller 10k *1 0.6A/55V Reset to micro controller SVBATT Battery Voltage Monitoring ABE VDD Monitoring 5V 5k to micro controller 4.7nF *3 3A/55V 3.3 or 5V from micro controller 4.7nF *3 OUT3 8A/55V SSY from micro controller 4.7nF *3 OUT2 SI Micro Second Channel 220F Power SIP from micro controller 100nF VDD 0.6A/55V 0.6A/55V 0.6A/55V 4.7nF *3 GNDABE PGND PCBConnector Slug Very good GND connection ; no bouncing due to load trancients . *1 - all trace length at pin typ 50mm *2 - connected together without parasitic resistor inbetween *3 - capacitor located close to the connector *5 - capacitor located close to the IC Figure 26 ApplDiagr .vsd Max. 0.3V parasitic R parasitic R GND EXTERNAL COMPONENTS. Ceramic 4,7nF : TDK, Typ C1608 X7R2A472K Ceramic 47nF : TDK, Typ C1005 X7R1C473K Ceramic 100 nF : TDK, Typ C1608 X7R1H104K Electrolytic 220F : Nippon Chemi -Con, Typ MVH50VC220 MTPK14 Or similar types to achieve the needed ESD -performance Application Diagram (LVDS configuration) Note: This is a very simplified example of an application circuit. The function must be verified in the real application. Note: The information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device. Data Sheet 79 Rev. 1.1, 2012-07-31 TLE 8718 SA Package Outlines 14 Package Outlines Figure 27 PG-DSO-36 Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). For further information on alternative packages, please visit our website: http://www.infineon.com/packages. Data Sheet 80 Dimensions in mm Rev. 1.1, 2012-07-31 TLE 8718 SA Revision History 15 Revision History Revision Date Changes 1) V1.0 2011-04-21 Datasheet created. n V1.1 2012-07-31 IDENTREG in Table 51 changed from "101x xxxx" to "100x xxxx". y Temperature Profile Table removed from Chapter 4.5 n 1) Functional Change Data Sheet 81 Rev. 1.1, 2012-07-31 Edition 2012-07-31 Published by Infineon Technologies AG 81726 Munich, Germany (c) 2012 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.