Automotive Power
Data Sheet
Rev. 1.1, 2012-07-31
TLE 8718 SA
Smart 18-Channel Lowside Switch with Micro Second Bus
Data Sheet 2 Rev. 1.1, 2012-07-31
TLE 8718 SA
Table of Contents
1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1 Device Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4 General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1 Test coverage (TC) in series production . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.3 Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.4 ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.5 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5 Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.2 Power Stages OUT1 and OUT3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.3 Power Stages OUT2 and OUT4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.4 Power Stages OUT5...OUT8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.5 Power Stages OUT9 and OUT10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.6 Power Stages OUT11...OUT14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.7 Power Stages OUT15 and OUT16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.8 Power Stages OUT17 and OUT18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.9 Timing Diagram MSC to OUTn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.10 Parallel connection of PS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6 Device Self Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.1 Short Circuit Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.2 Over Temperature Shut Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.3 Battery Voltage Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7 Supervisory (DIS5_10, DELAYIN, DELAYOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8 Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
8.1 Diagnostic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
8.2 Encoding of Diagnostic Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8.3 State Diagram of the Device Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8.4 Reset of the Diagnostic Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8.5 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8.6 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
9 Supply, VDD Monitoring, Reset and ABE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9.1 General functions of VDD Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9.2 VDD Undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
9.3 VDD Overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
9.4 Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.5 ABE Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.6 Testing of VDD Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.7 Testing procedure of VDD Monitoring in the application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.8 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table of Contents
TLE 8718 SA
Table of Contents
Data Sheet 3 Rev. 1.1, 2012-07-31
10 Device Logic Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
11 Micro Second Channel MSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
11.1 Downstream Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
11.1.1 Voltage Level Diagrams of low voltage differential pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
11.1.2 Downstream Supervisory Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
11.1.3 Command Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
11.1.4 Data Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
11.2 Upstream Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
11.3 Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
11.4 Internal Clock Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
11.5 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
12 Control of the device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
12.1 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
12.1.1 WR_OUT1516 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
12.1.2 WR_RST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
12.1.3 WR_START . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
12.1.4 RD_CONFIG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
12.1.5 RD_DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
12.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
12.2.1 CONREG1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
12.2.2 CONREG2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
12.2.3 CONREG3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
12.2.4 CONREG4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
12.2.5 OUT1516 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
12.2.6 OUTREG_EVEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
12.2.7 OUTREG_ODD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
12.2.8 DIAREG1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
12.2.9 DIAREG2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
12.2.10 DIAREG3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
12.2.11 DIAREG4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
12.2.12 DIAREG5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
12.2.13 DIAREG6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
12.2.14 DIAREG7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
12.2.15 IDENTREG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
12.2.16 TESTREG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
12.2.17 SEL_THRES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
12.2.18 FUSE_SC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
13 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
14 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
15 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
PG-DSO-36
Type Package Marking
TLE8718SA PG-DSO-36 TLE8718SA
Data Sheet 4 Rev. 1.1, 2012-07-31
Smart 18-Channel Lowside Switch with Micro Second Bus
speedFLEX
TLE8718SA
1Overview
Features
• Operating Conditions -40...150°C
• Over Temperature Warning
• ESD Capability 2/4KV HBM on-/off board Pins
• Short Circuit Protected for VBAT = 36V
• Active Zener Clamping at typically 55V
• Open Load, Short to Ground, Short Circuit Diagnosis (2 bit/OUT)
• Output control, diagnostics and initialisation via high speed
serial communication: Micro Second Channel [MSC]
• all Pins protected against ≤36V
• Over-Voltage and Under-Voltage Monitoring
• Two Output Channels operating during low supply voltage possible
• Programmable Short circuit behavior: switch off or current limitation
• Green Product (RoHS compliant)
• AEC Qualified
Application
• Automotive Engine Management Applications
• Driver IC for inductive and ohmic actuators, such as Injectors, Solenoids, Relays, Lambda Heater.
Table 1 Output Stage Overview and Product Summary
Output Maximum current RON_max at Tj = 150°C without clamping
OUT1, OUT3 8A 200mΩ
OUT2, OUT4 3A 350mΩ
OUT5...OUT8 2.2A 720mΩ
OUT9...OUT10 2.2A 470mΩ
OUT11...OUT14 2.2A 720mΩ
OUT15, OUT16 0.6A 2400mΩ
OUT17, OUT18 0.6A 2400mΩ
Operating Voltage VDD_RES 2.5V (defined behavior of the device)
VDD_POR 3...3.5V (OUT15,16 delayed switch-off)
VDD 4.5...5.5V (operating range)
Active Zener Voltage VDS (AZ) 50...60V
TLE 8718 SA
Overview
Data Sheet 5 Rev. 1.1, 2012-07-31
1.1 Device Description
All stages are controlled by MSC interface. The MSC interface can be single ended or low voltage differential type.
Serial transmission of the error code (diagnostic) via MSC interface (upstream channel).
All power stages (PS) are protected against short circuit to battery voltage (SCB). All PS (OUT1...18) are equipped
with switch off mode and current control mode in case of SCB (configurable).
Diagnosis of open load (OL), short-circuit to ground (SCG), short-circuit to battery voltage (SCB) and over
temperature (DOT) individually for each PS.
The fault conditions SCB, SCG, OL and DOT are not stored until an integrated filtering time has expired. If, at one
output, several errors occur in a sequence, always the last detected error is stored (after filtering time). All fault
conditions are encoded in two bits per stage and stored in the corresponding MSC interface registers. Additionally
there is one common diagnostic bit for fault occurrence (FAILURE_FLAG) at any output and one common
diagnostic bit (COTW) for diagnosis over temperature (DOT). The diagnostic registers can be read via MSC
interface. During the start-bit of a read out cycle the corresponding diagnostic register is cleared, nevertheless the
status of the diagnostic register before the start-bit is send. Pull-down Diagnostic currents and Open Load OL can
be switched off by configuration for OUT11...18; (CONREG3 and OUT1516).
Each stage (OUT1...14, 17, 18) is controlled with a separate bit of the data frame (downstream channel). The
control bit is non inverting, i.e. if a control bit is ‘1’ the corresponding stage is off. Stages are disabled – i.e. switched
off and switching on disabled if VDD is too low (VDD undervoltage or power on reset) or VDD too high (VDD
overvoltage). The same applies when the MSC monitoring detects an error, micro controller reset is active (i.e.
external signal on pin RST = low or external signal on Pin ABE is logical low level).
All outputs are designed with internal zener diodes for applications with inductive loads.
OUT1 and OUT3 are designed for normal operation with 4A and extended current of 8A for maximum of 200
seconds each vehicle driving cycle.
OUT5...OUT10 are disabled by active low level on pins DIS5_10 (with short delay).
OUT9 and OUT10 are designed for actuators with higher clamping energy.
OUT15 and OUT16 can be forced OFF with the higher thresholds of DELAYIN (VDELAYIN_RES15_16_L and
VDELAYIN_RES15_16_H) (see Figure 8). OUT15 and OUT16 can be configured to delayed reset behavior, in this case,
the switching-off algorithm is delayed by internal filtering time (exception: power on reset (POR), RES15_16 and
valid command frame to switch off stages is not delayed).
Parallel connection of stages (OUT1...14, 17, 18) is possible as the control bits that switch on and off these stages
are all transmitted in the same data frame. OUT15 and OUT16 are only allowed to be connected to each other
and not to other stages (see Chapter 5.10).
DELAYOUT is pulled active low to switch off external components by the lower thresholds of DELAYIN (VDELAYIN_L
and VDELAYIN_H), ABE or VDD monitoring.
Data Sheet 6 Rev. 1.1, 2012-07-31
TLE 8718 SA
Overview
Figure 1 Output stages, functional schematic
&
n=15, 16
"Off"
"On, no delay "
"On, restart timeout "
"Keep State , restart
timeout“
DIS5_10
STAUS_UV
STATUS_OV
t
DIS5_10
T
OUTn _OTSD
MSC_MON
(timeout)
OUTn
ABE_STATUS
RST
V
DD
<V
DD_POR
t
DIAG_SCB
SCB
OUTn_SCB
n=5...10
OUTn_DIAC
n=11...18
D
R
MSC downstream OUTn
Control
Flipflop
OUTREG
≥1
DELAYIN
Lower thr esholds
DELAYOUT
DELAYIN_CONFx
DELAYIN_FIL
OUTPUT_STBY
ABE_IMPACT
t
POR
t
DELRES
Discard
Restart
n=1...14, 17, 18
Output _Stages _Function _Overview.vsd
t
FIL_ OFF _DE L
MUX
SVBATT
t
MSC_MON
EXT_SCB
MUX
OL
RES15_16
Higher thresholds
of DELAYIN
&
n=5...14
n=1…4, 15…18
MUX
OUTn_DIA1/2
t
DIAG_OL
„0"
n=1…10
See „Block Diagramm V
DD
Monitoring“
t
RST
DELAYIN_FIL
OUTn_DIA1/2
t
DELAYIN_GLITCH_x
≥1
≥1
&
&
≥1
≥1
R
S
OUTn
Control
Flipflop
&
&
t
OUTn_OVSD
t
OUTn_OVSON
t
DELAYIN_GLITCH_x
t
DELAYIN_x
V
OUTn_BIAS
&
Reset
≥1
OUTn_CONTROL
OUTn_DELAY
OUTn_SCB
OUTn_DIAC
S
R
Flip
Flop
RD_DATA
OFF/ON
≥1
WR_RST
≥1
ABE
&
&
Reset
STATUS_SVBATT
DIS5_10_STATUS
DELAYIN _STATUS
RES 15_ 16_STATUS
D
R
POR
POR_FLAG
DIAREG
6.2
≥1
READ_DIAREG6
≥1
TLE 8718 SA
Block Diagram
Data Sheet 7 Rev. 1.1, 2012-07-31
2 Block Diagram
Figure 2 Block Diagram
SIN
SIP
FCLP
FCLN
SSY
SDO
OUT1
Micro Second Channel
Reset
VDD
Monitoring
PowerLogic
8A/55V
GNDABE
ABE
RST
DIS5_10
SI
FCL
Enable
SVBATT
Block_Diagram.vsd
DELAYIN
DELAYOUT
Slug
OUT2
3A/55V
OUT3
8A/55V
OUT4
3A/55V
OUT5
2.2A/55V
OUT6
2.2A/55V
OUT7
2.2A/55V
OUT8
2.2A/55V
OUT9
2.2A/55V
OUT10
2.2A/55V
OUT11
2.2A/55V
OUT12
2.2A/55V
OUT13
2.2A/55V
OUT14
2.2A/55V
OUT15
0.6A/55V
OUT16
0.6A/55V
OUT17
0.6A/55V
OUT18
0.6A/55V
DELA YI N/ O UT
Battery
Voltage
Monitoring
PGND
VDD
Data Sheet 8 Rev. 1.1, 2012-07-31
TLE 8718 SA
Pin Configuration
3 Pin Configuration
3.1 Pin Assignment
Figure 3 Pin Assignment
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
OUT1
OUT5
OUT9
SVBATT
ABE
GNDABE
VDD
OUT15
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
OUT2
OUT6
OUT14
OUT18
FCL
FCLN
FCLP
SI
SIP
SSY
SDO
RST
OUT16
OUT12
OUT8
OUT4
OUT10
OUT1
OUT13
OUT17
DELAYIN
DELAYOUT
DIS5_10
SIN
PGND
(Slug)
OUT11
OUT7
OUT3
OUT3
Pin_ Config.vsd
TLE 8718 SA
Pin Configuration
Data Sheet 9 Rev. 1.1, 2012-07-31
3.2 Pin Definitions and Functions
Pin Symbol Function
1, 2 OUT11) Drain Connection of Power stage.
Short circuit proof
Individually protected against overtemperature
diagnostic functions
control via MSC
Clamping of the output voltage by zener diodes
36 OUT2
17, 18 OUT32)
19 OUT4
3OUT5
35 OUT6
16 OUT7
20 OUT8
4OUT9
34 OUT10
15 OUT11
21 OUT12
5OUT13
33 OUT14
14 OUT15
22 OUT16
6OUT17
32 OUT18
9 DIS5_10 Disable pin for OUT5...OUT10 (low level disables OUT5...OUT10 after filtering time
(tDIS5_10) has expired). The thresholds are defined in Chapter 7 (active low, internal
pull-up)
7 DELAYIN DELAYIN input (internal pull-down, active low): Disable pin for DELAYOUT after the
configurable filtering time (tDELAYIN) has expired and Reset pin for OUT15 and OUT16.
The thresholds are defined in Chapter 7.
8 DELAYOUT Open drain output generating active low level if DELAYIN is low level (below
VDELAYIN_L) and tDELYAIN has expired, input ABE disables stages or VDD monitoring has
detected a supply voltage failure. See Chapter 7.
11 ABE Bidirectional pin (active low).
Indicates VDD overvoltage and undervoltage condition by pulling ABE-pin low.
If forced to low from externally all stages are turned off.
12 GNDABE Sense ground. Reference ground for VDD monitoring only. Connect this pin to ground.
13 VDD Supply voltage 5V
24 SDO MSC interface. Upstream data, open drain output
25 SSY MSC interface. Chip select and synchronization strobe.
26 SIP MSC interface. Downstream data positive for differential interface
27 SIN MSC interface. Downstream data negative for differential interface
28 SI MSC interface optional downstream data input for single ended interface
29 FCLP MSC interface. Clock positive for differential interface
30 FCLN MSC interface. Clock negative for differential interface
31 FCL MSC interface optional clock input for single ended interface
Data Sheet 10 Rev. 1.1, 2012-07-31
TLE 8718 SA
Pin Configuration
3.3 Abbreviations
23 RST Reset input (active low, internal pull-up). Shuts down all stages regardless of their
input signals. Clears the fault registers and resets the MSC interface registers
(partially).
10 SVBATT Sense Battery Voltage Monitoring Pin. Connect to VBAT. Used to activate factory test
mode. See Chapter 6.4.
Slug PGND Power Ground. Internally used as PGND. Analogue circuits except VDD-monitoring
refer to PGND. Connect to Ground.
1) Pin1 and Pin2 have to be connected together without any parasitic resistor
2) Pin17 and Pin18 have to be connected together without any parasitic resistor in between.
Table 2 Abbreviations
ABE “ABschaltung Endstufen” (switch off output stages)
C Command bit
CD Command data bit
DC Don´t care bit
DOT Diagnosis overtemperature
LVDS Low voltage differential signal
MSC Micro Second Channel
NCB Number of bits of the active phase of a command frame
NDB Number of bits of the active phase of a data frame
OL Open Load (diagnostic stage information)
OTSD Over Temperature Shut Down (threshold to shut down stages for device self
protection)
OTW Over Temperature Warning (diagnostic information)
POR Power On Reset, including filter time tPOR
PS Power Stage(s)
RST ReSeT input pin
SCB Short Circuit to Battery (diagnostic stage information)
SCG Short Circuit to Ground (diagnostic stage information)
SSY Select / SYnc signal for MSC communication
SB Selection bit
TC Test coverage
UD Upstream data bit
Pin Symbol Function
TLE 8718 SA
General Product Characteristics
Data Sheet 11 Rev. 1.1, 2012-07-31
4 General Product Characteristics
4.1 Test coverage (TC) in series production
In the standard production flow not all parameters can be covered due to technical or economic reasons. Therefore
the following test coverage classes are defined:
A) Parameter test (parameter is measured in production test)
B) Go/NoGo test (parameter within specified range is guaranteed by Go/NoGo-test in production)
C) Specified by design (covered by lab tests, not considered within the standard production flow)
The given supply voltage range is only valid as long as the related function is active. (e.g. the power stages are
shut off if VBAT > 28V. In that case, no function is available to be tested at VBAT = 40V).
4.2 Absolute Maximum Ratings
The integrated circuit will not be damaged if maximum ratings are reached. Every maximum rating is allowed to
be reached at the same time, as long as no other maximum rating is exceeded. But see Item Note:
Unless otherwise indicated all voltages are referred to PGND (all PGND and GNDABE are externally connected
to each other) Positive current flows into the pin.
Table 3 Maximum Ratings
Tj = -40°C to +150°C, all voltages with respect to PGND, positive current flowing into pin, unless otherwise
specified
Pos. Parameter Symbol Values Unit TC Conditions
min. max.
Supply and Power Pins
4.2.1 Supply Voltage Range
pin VDD, static
VDD_MR -0.3 36 V C –
4.2.2 Battery Voltage
stages output pins via load
VBAT_MR -1 40 V C –
4.2.3 Total current over the PGND IPGND_MR -38 38 A C –
4.2.4 Ground Voltage Offset
maximum permissible offset
between GNDABE and the PGND
dVGND_MR -0.3 0.3 V C –
4.2.5 Output Stages
static voltage OUTn (n=1...18)
VOUTn_MR -0.3 50 V C OUTn OFF
4.2.6 Short Circuit to VBAT
(single event)
VBAT_SC -0.3 36 V C OUTn (n=1...18),
Figure 4
Interface and Logic
4.2.7 Logic Input Pins
SIP, SIN, SI,
FCLP, FCLN, FCL,
SSY, DIS5_10, RST
VSIP_MR, VSIN_MR,
VSI_MR, VFCLP_MR,
VFCLN_MR, VFCL_MR,
VSSY_MR, VDIS5_10_MR,
VRST_MR
-0.3 36 V C –
4.2.8 Bidirectional Pin ABE VABE_MR -0.3 36 V C –
4.2.9 Output Pins
DELAYOUT, SDO
VDELAYOUT_MR,
VSDO_MR
-0.3 36 V C –
Data Sheet 12 Rev. 1.1, 2012-07-31
TLE 8718 SA
General Product Characteristics
Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are
not designed for continuous or repetitive operation.
Figure 4 Short Circuit test set-up
4.2.10 Input Pins
DELAYIN, SVBATT
VDELAYIN_MR,
VSVBATT_MR
-0.3 40 V C –
4.2.11 Current into Pin
SIP, SIN, SI,
FCLP, FCLN, FCL,
SSY, DIS5_10, RST,
DELAYIN, SVBATT, SDO
ISIP_MR, ISIN_MR, ISI_MR,
IFCLP_MR, IFCLN_MR,
IFCL_MR, ISSY_MR,
IDIS5_10_MR, IRST_MR,
IDELAYIN_MR,
ISVBATT_MR, ISDO_MR
-10 10 mA C 1)
4.2.12 Current into Pin DELAYOUT, ABE IDELAYOUT_MR, IABE_MR -10 15 mA C 1)
Temperatures
4.2.13 Junction Temperature Tj -40 150 °CC–
4.2.14 Storage Temperature TSTG -55 150 °CC–
1) Other maximum ratings (like Item 4.2.7 to Item 4.2.10 or Item 4.2.13) are not allowed to be exceeded.
Table 3 Maximum Ratings
Tj = -40°C to +150°C, all voltages with respect to PGND, positive current flowing into pin, unless otherwise
specified
Pos. Parameter Symbol Values Unit TC Conditions
min. max.
PGND
OUTn
R
ECU
L
Harness
R
Harness
V
BAT
Short _Ci rcui t_test _ setup .vsd
R
BAT
L
BAT
5µH 20mΩ80mΩ
10mΩ
0...5µH
TLE 8718 SA
General Product Characteristics
Data Sheet 13 Rev. 1.1, 2012-07-31
4.3 Thermal Resistance
Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go
to www.jedec.org.
Figure 5 Thermal simulation - PCB setup
Table 4 Thermal Resistance
Tj = -40°C to +150°C, all voltages with respect to PGND, positive current flowing into pin, unless otherwise
specified
Pos. Parameter Symbol Values Unit TC Conditions
min. typ. max.
4.3.1 Junction to Case RthJC –– 2K/WC
1)
1) Power dissipation Pv=3W distributed statically and homogeneously over all power stages. Resistive Load.
4.3.2 Junction to Ambient RthJA –25–K/WCsee Figure 5 1)
70µm modeled (traces)
35µm, 90% metalization
35µm, 90% metalization
1.6 mm
70µm, 5% metalization
Dimensions: 76.2 x 114.3 x 1.6 mm³; Material: FR4
Thermal Vias: diameter = 0.3 mm; plating 25 µm; 56 pcs.
Metalization accodring : JEDEC 2s2p (JESD 51-7) + (JESD 51-5)
Thermal_Setup .vsd
Data Sheet 14 Rev. 1.1, 2012-07-31
TLE 8718 SA
General Product Characteristics
4.4 ESD
Of the various ESD models, the integrated circuit meets at least the “human body model” according to the
requirements of the EIA/JESD22-A114-F. During manufacturing process, ESD pulses according to "charged
device model" (EIA/JESD22-C101-D) may be exposed to each pin. ESD Specification Details in the following
Table.
4.5 Operating Range
Table 5 ESD Susceptibility
Tj = -40°C to +150°C, all voltages with respect to PGND, positive current flowing into pin, unless otherwise
specified
Pos. Parameter Symbol Values Unit TC Conditions
min. typ. max.
Standard Requirements for all Pins
4.4.1 Electro Static Discharge Voltage
“Human-Body-Model – HBM”
VESD1 -2 – 2 kV C All Pins
4.4.2 Electro Static Discharge Voltage
“Charged-Device-Model – CDM”
VESD2 -500 – 500 V C All Pins
Pins with Extended Requirements
4.4.3 Electro Static Discharge Voltage
“Human-Body-Model – HBM”
VESD3 -6 – 6 kV C OUT1…14
vs. PGND
4.4.4 Electro Static Discharge Voltage
“Human-Body-Model – HBM”
VESD4 -4 – 4 kV C OUT15…18
vs. PGND
Table 6 Operating Range
Tj = -40°C to +150°C, all voltages with respect to PGND, positive current flowing into pin, unless otherwise
specified
Pos. Parameter Symbol Values Unit TC Conditions
min. max.
Supply, Battery Voltage
4.5.1 Supply Voltage Range VDD 4.5 5.5 V C –
4.5.2 Battery Voltage VBAT(typ) 13.5 V C –
4.5.3 Nominal Total PGND Current IPGND(typ) -12 0 A C 1)
1) Total PGND current influences e.g. the RON-measurement of the Power Stages or voltage thresholds of the input buffers
because of common PGND bond wires. As basis for definition of the RON or the voltage thresholds, the defined PGND
current is used.
TLE 8718 SA
Power Stages
Data Sheet 15 Rev. 1.1, 2012-07-31
5 Power Stages
5.1 Functional Description
The following general description is valid for the channel groups OUT1,3, OUT2,4, OUT5...8, OUT9,10,
OUT11...14, OUT17,18. The specific function of the channel group OUT15,16 is described in Chapter 5.7.
The reset input of the OUTn-control flip-flop is active high and dominant, delivering a logic low level at the output
of the OUTn-control flip-flop.Only in failure-free condition, output can be switched on by MSC downstream.
Disabling inputs DIS5_10 and DELAYIN have different input characteristics and delay (tDELAYIN >> tDIS5_10). For
details concerning DIS5_10, DELAYIN and DELAYOUT see Chapter 7 and Figure 1.
5.2 Power Stages OUT1 and OUT3
Table 7 Electrical Characteristics Power Stages OUT1 and OUT3
n = 1 and 3, all channels ON or OFF, nominal load conditions, 4.5V < VDD < 5.5V, 4.5V < VBAT < 40V, all voltages
with respect to PGND, positive current flowing into pin. Tj = -40°C to +150°C, unless otherwise specified
Pos. Parameter Symbol Values Unit TC Conditions
min. typ. max.
Load Current
5.2.1 Continuous Load Current IOUTn ––4AC
5.2.2 Extended Load Current IOUTn_ex – – 8 A C max 800h
5.2.3 Extended current time,
Accumulated operating time
tOUTn_ec ––60hCV
BAT≤14V,
RL≥0.88Ω
5.2.4 Maximum current, (short circuit limited
current / switch off threshold)
IOUTn_max 8–12.5AA
ON-Resistance without clamping 1)
5.2.5 On Resistance Tj=-40°C Ron-40_n ––120mΩCIOUTn=4A
5.2.6 On Resistance Tj=25°C Ron+25_n ––148mΩCIOUTn=4A
5.2.7 On Resistance Tj=150°C Ron+150_n ––200mΩAIOUTn=4A
5.2.8 On Resistance Tj≤150°C Ron_n ––210mΩCIOUTn<8A
ON-Resistance with clamping 2)
5.2.9 On Resistance Tj=-40°C Ron-40_n ––156mΩCIOUTn=4A
5.2.10 On Resistance Tj=25°C Ron+25_n ––193mΩCIOUTn=4A
5.2.11 On Resistance Tj=150°C Ron+150_n – – 260 mΩAIOUTn=4A
5.2.12 On Resistance Tj≤150°C Ron_n ––273mΩCIOUTn<8A
Delay times, Slew rates (see Figure 6)
5.2.13 Switch on delay tdon_n ––15µsCRLoad=5.9Ω,
VBAT=14V
5.2.14 Switch off delay tdoff_n ––15µsCRLoad=5.9Ω,
VBAT=14V
5.2.15 Difference of switch on and off delay
tdif_n=tdon_n-tdoff_n
tdif_n -8 – 8 µs C RLoad=5.9Ω,
VBAT=14V
5.2.16 Switch on slew rates son_n 0.5 1 2.5 V/µs C RLoad=5.9Ω,
VBAT=14V
Data Sheet 16 Rev. 1.1, 2012-07-31
TLE 8718 SA
Power Stages
5.2.17 Switch off slew rates soff_n 0.5 1 2.5 V/µs C RLoad=5.9Ω,
VBAT=14V
Leakage current
5.2.18 Leakage current of the Output Stage Il_OUTn ––5µACVOUTn=14V,
VDD=0V, Tj=60°C
5.2.19 Leakage current of the Output Stage Il_OUTn ––10µACVOUTn=28V,
VDD=0V, Tj=60°C
5.2.20 Leakage current of the Output Stage Il_OUTn ––30µAAVOUTn<28V,
VDD=0V,
Tj=150°C
Clamping voltage
5.2.21 Clamping voltage VCL_n 50 – 60 V C IOUTn=3A
5.2.22 Clamping voltage VCL_n 50 – 60 V A IOUTn=0.2A
Clamping energy 3)
5.2.23 Standard operating range, max. 1000Mio
cycles
ECL_OUTn ––25mJCTj(0)=125°C,
IOUTn(0)<2.8A
5.2.24 Jump Start, max. 0.01Mio cycles ECL_OUTn ––27mJCTj(0)=85°C,
IOUTn(0)<5.6A
5.2.25 Load Dump, max. 10 pulses ECL_OUTn ––90mJCTj(0)=35°C,
IOUTn(0)<8A
5.2.26 Load Dump, max. 10 pulses ECL_OUTn ––26mJCTj(0)=150°C,
IOUTn(0)<8A
Reverse current through OUTn
5.2.27 In operation mode, static, no destruction IR_S_OUTn -3 – – A C Tj=150°C,VDD=5V
5.2.28 Without supply voltage, possibly Leakage
Current out of neighbor channels.
10ms after the reverse current disappears
leakage current criteria are kept.
IR_Soff_OUTn -3 – – A C VDD<1V
5.2.29 In operation mode, No unwanted
switching of channels; No unwanted
Reset, No unwanted change of Voltage
Monitoring Thresholds; No unwanted
communication errors or register changes
beside diagnostic registers.
Possibly unwanted diagnostic entries.
Possibly Leakage Current out of neighbor
channels.
IR_S_OUTn -1.5 – – A C Tj=150°C,
VDD=5V
1) Item 5.2.5 to Item 5.2.8 has to be considered for applications with resistive load or inductive load with external
freewheeling.
2) Item 5.2.9 to Item 5.2.12 has to be considered for applications where clamping occurs.
3) Clamping energy, Linear decreasing current, fcl<67Hz.
Table 7 Electrical Characteristics Power Stages OUT1 and OUT3
n = 1 and 3, all channels ON or OFF, nominal load conditions, 4.5V < VDD < 5.5V, 4.5V < VBAT < 40V, all voltages
with respect to PGND, positive current flowing into pin. Tj = -40°C to +150°C, unless otherwise specified
Pos. Parameter Symbol Values Unit TC Conditions
min. typ. max.
TLE 8718 SA
Power Stages
Data Sheet 17 Rev. 1.1, 2012-07-31
5.3 Power Stages OUT2 and OUT4
Table 8 Electrical Characteristics Power Stages OUT2 and OUT4
n = 2 and 4, all channels ON or OFF, nominal load conditions, 4.5V < VDD < 5.5V, 4.5V < VBAT < 40V, all voltages
with respect to PGND, positive current flowing into pin., Tj = -40°C to +150°C, unless otherwise specified
Pos. Parameter Symbol Values Unit TC Conditions
min. typ. max.
Load Current
5.3.1 Continuous Load Current IOUTn ––3AC
5.3.2 Extended Current time
Accumulated Operating time
tOUTn_ec ––100hCV
BAT≤14V,
RL≥1.98Ω
5.3.3 Maximum Current, (short circuit limited
current / switch off threshold)
IOUTn_max 3–6AA
ON-Resistance without clamping 1)
5.3.4 On Resistance Tj=-40°C Ron-40_n ––210mΩCIOUTn=3A
5.3.5 On Resistance Tj=25°C Ron+25_n ––259mΩCIOUTn=3A
5.3.6 On Resistance Tj≤150°C Ron_n ––350mΩAIOUTn=3A
ON-Resistance with clamping 2)
5.3.7 On Resistance Tj=-40°C Ron-40_n ––273mΩCIOUTn=3A
5.3.8 On Resistance Tj=25°C Ron+25_n ––337mΩCIOUTn=3A
5.3.9 On Resistance Tj≤150°C Ron_n ––455mΩAIOUTn=3A
Delay times, Slew rates (see Figure 6)
5.3.10 Switch on delay tdon_n ––15µsCRLoad=5.9Ω,
VBAT=14V
5.3.11 Switch off delay tdoff_n ––15µsCRLoad=5.9Ω,
VBAT=14V
5.3.12 Difference of switch on and off delay
tdif_n=tdon_n-tdoff_n
tdif_n -5 – 5 µs C RLoad=5.9Ω,
VBAT=14V
5.3.13 Switch on slew rates son_n 1.1 2.5 5.8 V/µs C RLoad=5.9Ω,
VBAT=14V
5.3.14 Switch off slew rates soff_n 1.1 2.5 5.8 V/µs C RLoad=5.9Ω,
VBAT=14V
Leakage current
5.3.15 Leakage current of the Output Stage Il_OUTn ––5µACVOUTn=14V,
VDD=0V, Tj=60°C
5.3.16 Leakage current of the Output Stage Il_OUTn ––10µACVOUTn=28V,
VDD=0V, Tj=60°C
5.3.17 Leakage current of the Output Stage Il_OUTn ––30µAAVOUTn<28V,
VDD=0V,
Tj=150°C
Clamping voltage
5.3.18 Clamping voltage VCL_n 50 – 60 V C IOUTn=3A
5.3.19 Clamping voltage VCL_n 50 – 60 V A IOUTn=0.2A
Data Sheet 18 Rev. 1.1, 2012-07-31
TLE 8718 SA
Power Stages
Clamping energy 3)
5.3.20 Standard operating range, max. 1000Mio
cycles
ECL_OUTn ––22mJCTj(0)=125°C,
IOUTn(0)<1.05A
5.3.21 Jump Start, max. 0.01Mio cycles ECL_OUTn ––18mJCTj(0)=85°C,
IOUTn(0)<2.1A
5.3.22 Load Dump, max. 10 pulses ECL_OUTn ––76mJCTj(0)=35°C,
IOUTn(0)<3A
5.3.23 Load Dump, max. 10 pulses ECL_OUTn ––19mJCTj(0)=150°C,
IOUTn(0)<3A
Reverse current through OUTn
5.3.24 In operation mode, static, no destruction IR_S_OUTn -3 – – A C Tj=150°C,VDD=5V
5.3.25 Without supply voltage, possibly Leakage
Current out of neighbor channels.
10ms after the reverse current disappears
leakage current criteria are kept.
IR_Soff_OUTn -3 – – A C VDD<1V
5.3.26 In operation mode, No unwanted
switching of channels; No unwanted
Reset, No unwanted change of Voltage
Monitoring Thresholds; No unwanted
communication errors or register changes
beside diagnostic registers.
Possibly unwanted diagnostic entries.
Possibly Leakage Current out of neighbor
channels.
IR_S_OUTn -1.1 – – A C Tj=150°C,
VDD=5V
1) Item 5.3.4 to Item 5.3.6 has to be considered for applications with resistive load or inductive load with external
freewheeling.
2) Item 5.3.7 to Item 5.3.9 has to be considered for applications where clamping occurs.
3) Clamping energy, Linear decreasing current, fcl<67Hz.
Table 8 Electrical Characteristics Power Stages OUT2 and OUT4
n = 2 and 4, all channels ON or OFF, nominal load conditions, 4.5V < VDD < 5.5V, 4.5V < VBAT < 40V, all voltages
with respect to PGND, positive current flowing into pin., Tj = -40°C to +150°C, unless otherwise specified
Pos. Parameter Symbol Values Unit TC Conditions
min. typ. max.
TLE 8718 SA
Power Stages
Data Sheet 19 Rev. 1.1, 2012-07-31
5.4 Power Stages OUT5...OUT8
Table 9 Electrical Characteristics Power Stages OUT5...OUT8
n = 5...8, all channels ON or OFF, nominal load conditions, 4.5V < VDD < 5.5V, 4.5V < VBAT < 40V, all voltages with
respect to PGND, positive current flowing into pin., Tj = -40°C to +150°C, unless otherwise specified
Pos. Parameter Symbol Values Unit TC Conditions
min. typ. max.
Load Current
5.4.1 Continuous Load Current IOUTn ––2.2AC–
5.4.2 Extended current time,
Accumulated operating time
tOUTn_ec ––100hCV
BAT≤14V,
RL≥2.78Ω
5.4.3 Maximum current, (short circuit limited
current / switch off threshold)
IOUTn_max 2.2 – 4 A A –
ON-Resistance
5.4.4 On-resistance Tj=-40°C Ron-40_n ––432mΩCIOUTn=2.2A
5.4.5 On-resistance Tj=25°C Ron+25_n ––533mΩCIOUTn=2.2A
5.4.6 On-resistance Tj≤150°C Ron_n ––720mΩAIOUTn=2.2A
Delay times, Slew rates (see Figure 6)
5.4.7 Switch on delay tdon_n ––10µsCRLoad=7.68Ω,
VBAT=14V
5.4.8 Switch off delay tdoff_n ––10µsCRLoad=7.68Ω,
VBAT=14V
5.4.9 Difference of switch on and off delay
tdif_n=tdon_n-tdoff_n
tdif_n -5 – 5 µs C RLoad=7.68Ω,
VBAT=14V
5.4.10 Switch on slew rates Son_n 1.5 3.1 7.5 V/µs C RLoad=7.68Ω,
VBAT=14V
5.4.11 Switch off slew rates Soff_n 1.5 3.1 7.5 V/µs C RLoad=7.68Ω,
VBAT=14V
Leakage current
5.4.12 Leakage current of the Output Stage Il_OUTn ––5µACVOUTn=14V,
VDD=0V, Tj=60°C
5.4.13 Leakage current of the Output Stage Il_OUTn ––10µACVOUTn=28V,
VDD=0V, Tj=60°C
5.4.14 Leakage current of the Output Stage Il_OUTn ––20µAAVOUTn<28V,
VDD=0V,
Tj=150°C
Clamping voltage
5.4.15 Clamping voltage VCL_n 50 – 60 V C IOUTn=2.2A
5.4.16 Clamping voltage VCL_n 50 – 60 V A IOUTn=0.2A
5.4.17 Clamping voltage, difference between
outputs. OUTn with identical inductive
loads
VCL_dif_n -3 – 3 V A IOUTn=0.2A
Clamping energy 1)
5.4.18 Standard operating range, max. 18Mio
cycles
ECL_OUTn ––7.5mJCTj(0)=35°C,
IOUTn(0)<1.8A
Data Sheet 20 Rev. 1.1, 2012-07-31
TLE 8718 SA
Power Stages
5.4.19 Standard operating range, max. 648Mio
cycles
ECL_OUTn ––4mJCTj(0)=125°C,
IOUTn(0)<1.4A
5.4.20 Standard operating range, max. 96Mio
cycles
ECL_OUTn ––3mJCTj(0)=140°C,
IOUTn(0)<1A
5.4.21 Standard operating range, max. 4Mio
cycles
ECL_OUTn ––3mJCTj(0)=150°C,
IOUTn(0)<1A
5.4.22 Generator defect, max. 0.5Mio cycles, or
Item 5.4.23
ECL_OUTn ––9mJCTj(0)=35°C,
IOUTn(0)<2A
5.4.23 Generator defect, max. 0.5Mio cycles ECL_OUTn ––5mJCTj(0)=145°C,
IOUTn(0)<1.5A
5.4.24 Jump start, max. 0.021Mio cycles, or
Item 5.4.25
ECL_OUTn ––17.5mJCTj(0)=35°C,
IOUTn(0)<3A2)
5.4.25 Jump start, max. 0.021Mio cycles ECL_OUTn ––10mJCTj(0)=85°C,
IOUTn(0)<2.3A2)
5.4.26 Load dump, max. 10 pulses, or
Item 5.4.27
ECL_OUTn ––35mJCTj(0)=85°C,
IOUTn(0)<2.1A
5.4.27 Load dump, max. 10 pulses ECL_OUTn ––20mJCTj(0)=145°C,
IOUTn(0)<2.1A
5.4.28 Load dump, max. 10 pulses, or
Item 5.4.29
ECL_OUTn ––21mJCTj(0)=85°C,
IOUTn(0)<3.3A2)
5.4.29 Load dump, max. 10 pulses ECL_OUTn ––18mJCTj(0)=145°C,
IOUTn(0)<2.4A2)
Reverse current through OUTn
5.4.30 In operation mode, static, no destruction IR_S_OUTn -2.2 – – A C Tj=150°C,VDD=5V
5.4.31 Without supply voltage, possibly Leakage
Current out of neighbor channels.
10ms after the reverse current disappears
leakage current criteria are kept.
IR_Soff_OUTn -2.2 – – A C VDD<1V
5.4.32 In operation mode, No unwanted
switching of channels; No unwanted
Reset, No unwanted change of Voltage
Monitoring Thresholds; No unwanted
communication errors or register changes
beside diagnostic registers.
Possibly unwanted diagnostic entries.
Possibly Leakage Current out of neighbor
channels.
IR_S_OUTn -1 – – A C Tj=150°C,
VDD=5V
1) Clamping energy, Linear decreasing current, fcl<67Hz.
2) PS might switch off to limit the current before reaching the given IOUTn due to reaching IOUTn_max.
Table 9 Electrical Characteristics Power Stages OUT5...OUT8
n = 5...8, all channels ON or OFF, nominal load conditions, 4.5V < VDD < 5.5V, 4.5V < VBAT < 40V, all voltages with
respect to PGND, positive current flowing into pin., Tj = -40°C to +150°C, unless otherwise specified
Pos. Parameter Symbol Values Unit TC Conditions
min. typ. max.
TLE 8718 SA
Power Stages
Data Sheet 21 Rev. 1.1, 2012-07-31
5.5 Power Stages OUT9 and OUT10
Table 10 Electrical Characteristics Power Stages OUT9 and OUT10
n = 9 and 10, all channels ON or OFF, nominal load conditions, 4.5V < VDD < 5.5V, 4.5V < VBAT < 40V, all voltages
with respect to PGND, positive current flowing into pin., Tj = -40°C to +150°C, unless otherwise specified
Pos. Parameter Symbol Values Unit TC Conditions
min. typ. max.
Load Current
5.5.1 Continuous Load Current IOUTn ––2.2AC–
5.5.2 Extended current time,
Accumulated operating time
tOUTn_ec ––100hCV
BAT≤14V,
RL≥2.78Ω
5.5.3 Maximum current, (short circuit limited
current / switch off threshold)
IOUTn_max 2.2 – 4 A A –
ON-Resistance
5.5.4 On-resistance Tj=-40°C Ron-40_n ––282mΩCIOUTn=2.2A
5.5.5 On-resistance Tj=25°C Ron+25_n ––348mΩCIOUTn=2.2A
5.5.6 On-resistance Tj≤150°C Ron_n ––470mΩAIOUTn=2.2A
Delay times, Slew rates (see Figure 6)
5.5.7 Switch on delay tdon_n ––10µsCRLoad=7.68Ω,
VBAT=14V
5.5.8 Switch off delay tdoff_n ––10µsCRLoad=7.68Ω,
VBAT=14V
5.5.9 Difference of switch on and off delay
tdif_n=tdon_n-tdoff_n
tdif_n -5 – 5 µs C RLoad=7.68Ω,
VBAT=14V
5.5.10 Switch on slew rates Son_n 1.5 3.1 7.5 V/µs C RLoad=7.68Ω,
VBAT=14V
5.5.11 Switch off slew rates Soff_n 1.5 3.1 7.5 V/µs C RLoad=7.68Ω,
VBAT=14V
Leakage current
5.5.12 Leakage current of the Output Stage Il_OUTn ––5µACVOUTn=14V,
VDD=0V, Tj=60°C
5.5.13 Leakage current of the Output Stage Il_OUTn ––10µACVOUTn=28V,
VDD=0V, Tj=60°C
5.5.14 Leakage current of the Output Stage Il_OUTn ––20µAAVOUTn<28V,
VDD=0V,
Tj=150°C
Clamping voltage
5.5.15 Clamping voltage VCL_n 50 – 60 V C IOUTn=2.2A
5.5.16 Clamping voltage VCL_n 50 – 60 V A IOUTn=0.2A
5.5.17 Clamping voltage, difference between
outputs. OUTn with identical inductive
loads
VCL_dif_n -3 – 3 V A IOUTn=0.2A
Clamping energy 1)
5.5.18 Standard operating range, max. 18Mio
cycles
ECL_OUTn ––25mJCTj(0)=35°C,
IOUTn(0)<1.5A
Data Sheet 22 Rev. 1.1, 2012-07-31
TLE 8718 SA
Power Stages
5.5.19 Standard operating range, max. 648Mio
cycles
ECL_OUTn ––18mJCTj(0)=125°C,
IOUTn(0)<1.2A
5.5.20 Standard operating range, max. 96Mio
cycles
ECL_OUTn ––15mJCTj(0)=140°C,
IOUTn(0)<1A
5.5.21 Standard operating range, max. 4Mio
cycles
ECL_OUTn ––15mJCTj(0)=150°C,
IOUTn(0)<1A
5.5.22 Generator defect, max. 0.5Mio cycles; or
Item 5.5.23
ECL_OUTn ––28mJCTj(0)=35°C,
IOUTn(0)<1.6A
5.5.23 Generator defect, max. 0.5Mio cycles ECL_OUTn ––16mJCTj(0)=145°C,
IOUTn(0)<1.1A
5.5.24 Jump start, max. 0.021Mio cycles, or
Item 5.5.25
ECL_OUTn ––50mJCTj(0)=35°C,
IOUTn(0)<2.2A
5.5.25 Jump start, max. 0.021Mio cycles ECL_OUTn ––30mJCTj(0)=85°C,
IOUTn(0)<1.8A
5.5.26 Load dump, max. 10 pulses, or
Item 5.5.27
ECL_OUTn ––120mJCTj(0)=35°C,
IOUTn(0)<2.4A2)
5.5.27 Load dump, max. 10 pulses ECL_OUTn ––55mJCTj(0)=145°C,
IOUTn(0)<1.8A
5.5.28 Load dump, max. 10 pulses, or
Item 5.5.29
ECL_OUTn ––80mJCTj(0)=35°C,
IOUTn(0)<3.5A2)
5.5.29 Load dump, max. 10 pulses ECL_OUTn ––51mJCTj(0)=145°C,
IOUTn(0)<2A
Reverse current through OUTn
5.5.30 In operation mode, static, no destruction IR_S_OUTn -2.2 – – A C Tj=150°C,VDD=5V
5.5.31 Without supply voltage, possibly Leakage
Current out of neighbor channels.
10ms after the reverse current disappears
leakage current criteria are kept.
IR_Soff_OUTn -2.2 – – A C VDD<1V
5.5.32 In operation mode, No unwanted
switching of channels; No unwanted
Reset, No unwanted change of Voltage
Monitoring Thresholds; No unwanted
communication errors or register changes
beside diagnostic registers.
Possibly unwanted diagnostic entries.
Possibly Leakage Current out of neighbor
channels.
IR_S_OUTn -1 – – A C Tj=150°C,
VDD=5V
1) Clamping energy, Linear decreasing current, fcl<67Hz.
2) PS might switch off to limit the current before reaching the given IOUTn due to reaching IOUTn_max.
Table 10 Electrical Characteristics Power Stages OUT9 and OUT10
n = 9 and 10, all channels ON or OFF, nominal load conditions, 4.5V < VDD < 5.5V, 4.5V < VBAT < 40V, all voltages
with respect to PGND, positive current flowing into pin., Tj = -40°C to +150°C, unless otherwise specified
Pos. Parameter Symbol Values Unit TC Conditions
min. typ. max.
TLE 8718 SA
Power Stages
Data Sheet 23 Rev. 1.1, 2012-07-31
5.6 Power Stages OUT11...OUT14
Table 11 Electrical Characteristics Power Stages OUT11...OUT14
n = 11...14, all channels ON or OFF, nominal load conditions, 4.5V < VDD < 5.5V, 4.5V < VBAT < 40V, all voltages
with respect to PGND, positive current flowing into pin., Tj = -40°C to +150°C, unless otherwise specified
Pos. Parameter Symbol Values Unit TC Conditions
min. typ. max.
Load Current
5.6.1 Continuous Load Current IOUTn ––2.2AC–
5.6.2 Extended current time,
Accumulated operating time
tOUTn_ec ––100hCV
BAT≤14V,
RL≥2.78Ω
5.6.3 Maximum current, (short circuit limited
current / switch off threshold)
IOUTn_max 2.2 – 4 A A –
ON-Resistance
5.6.4 On-resistance Tj=-40°C Ron-40_n ––432mΩCIOUTn=2.2A
5.6.5 On-resistance Tj=25°C Ron+25_n ––533mΩCIOUTn=2.2A
5.6.6 On-resistance Tj≤150°C Ron_n ––720mΩAIOUTn=2.2A
Delay times, Slew rates (see Figure 6)
5.6.7 Switch on delay tdon_n ––10µsCRLoad=7.68Ω,
VBAT=14V
5.6.8 Switch off delay tdoff_n ––10µsCRLoad=7.68Ω,
VBAT=14V
5.6.9 Difference of switch on and off delay
tdif_n=tdon_n-tdoff_n
tdif_n -5 – 5 µs C RLoad=7.68Ω,
VBAT=14V
5.6.10 Switch on slew rates son_n 1.5 3.1 7.5 V/µs C RLoad=7.68Ω,
VBAT=14V
5.6.11 Switch off slew rates soff_n 1.5 3.1 7.5 V/µs C RLoad=7.68Ω,
VBAT=14V
Leakage current
5.6.12 Leakage current of the Output Stage Il_OUTn ––5µACVOUTn=14V,
VDD=0V, Tj=60°C
5.6.13 Leakage current of the Output Stage Il_OUTn ––20µACVOUTn=14V,
VDD=5V
(diagnosis current
off, CONREG3),
Tj=60°C
5.6.14 Leakage current of the Output Stage Il_OUTn ––10µACVOUTn=28V,
VDD=0V, Tj=60°C
5.6.15 Leakage current of the Output Stage Il_OUTn ––25µACVOUTn=28V,
VDD=5V
(diagnosis current
off, CONREG3),
Tj=60°C
5.6.16 Leakage current of the Output Stage Il_OUTn ––20µAAVOUTn<28V,
VDD=0V,
Tj=150°C
Data Sheet 24 Rev. 1.1, 2012-07-31
TLE 8718 SA
Power Stages
5.6.17 Leakage current of the Output Stage Il_OUTn ––35µAAVOUTn<28V,
VDD=5V
(diagnosis current
off, CONREG3),
Tj=150°C
Clamping voltage
5.6.18 Clamping voltage VCL_n 50 – 60 V C IOUTn=2.2A
5.6.19 Clamping voltage VCL_n 50 – 60 V A IOUTn=0.2A
Clamping energy 1)
5.6.20 Standard operating range, max. 18Mio
cycles
ECL_OUTn ––18mJCTj(0)=35°C,
IOUTn(0)<1.5A
5.6.21 Standard operating range, max. 520Mio
cycles
ECL_OUTn ––9mJCTj(0)=125°C,
IOUTn(0)<1.2A
5.6.22 Standard operating range, max. 120Mio
cycles
ECL_OUTn ––7mJCTj(0)=140°C,
IOUTn(0)<1A
5.6.23 Standard operating range, max. 13Mio
cycles
ECL_OUTn ––7mJCTj(0)=150°C,
IOUTn(0)<1A
5.6.24 Generator defect, max. 0.25Mio cycles or
Item 5.6.25
ECL_OUTn ––23mJCTj(0)=35°C,
IOUTn(0)<1.6A
5.6.25 Generator defect, max. 0.25Mio cycles ECL_OUTn ––11mJCTj(0)=145°C,
IOUTn(0)<1.1A
5.6.26 Jump start, max. 0.02Mio cycles, or
Item 5.6.27
ECL_OUTn ––35mJCTj(0)=35°C,
IOUTn(0)<2.2A
5.6.27 Jump start, max. 0.02Mio cycles ECL_OUTn ––17mJCTj(0)=85°C,
IOUTn(0)<1.8A
5.6.28 Load dump, max. 10 pulses, or
Item 5.6.29
ECL_OUTn ––50mJCTj(0)=35°C,
IOUTn(0)<2.32)
5.6.29 Load dump, max. 10 pulses ECL_OUTn ––30mJCTj(0)=145°C,
IOUTn(0)<1.3A
5.6.30 Load dump, max. 10 pulses, or
Item 5.6.31
ECL_OUTn ––33mJCTj(0)=35°C,
IOUTn(0)<3.5A2)
5.6.31 Load dump, max. 10 pulses ECL_OUTn ––18mJCTj(0)=145°C,
IOUTn(0)<2A
Table 11 Electrical Characteristics Power Stages OUT11...OUT14
n = 11...14, all channels ON or OFF, nominal load conditions, 4.5V < VDD < 5.5V, 4.5V < VBAT < 40V, all voltages
with respect to PGND, positive current flowing into pin., Tj = -40°C to +150°C, unless otherwise specified
Pos. Parameter Symbol Values Unit TC Conditions
min. typ. max.
TLE 8718 SA
Power Stages
Data Sheet 25 Rev. 1.1, 2012-07-31
Reverse current through OUTn
5.6.32 In operation mode, static, no destruction IR_S_OUTn -2.2 – – A C Tj=150°C,VDD=5V
5.6.33 Without supply voltage, possibly Leakage
Current out of neighbor channels.
10ms after the reverse current disappears
leakage current criteria are kept.
IR_Soff_OUTn -2.2 – – A C VDD<1V
5.6.34 In operation mode, No unwanted
switching of channels; No unwanted
Reset, No unwanted change of Voltage
Monitoring Thresholds; No unwanted
communication errors or register changes
beside diagnostic registers.
Possibly unwanted diagnostic entries.
Possibly Leakage Current out of neighbor
channels.
IR_S_OUTn -1 – – A C Tj=150°C,
VDD=5V
1) Clamping energy, Linear decreasing current, fcl<50Hz
2) PS might switch off to limit the current before reaching the given IOUTn due to reaching IOUTn_max.
Table 11 Electrical Characteristics Power Stages OUT11...OUT14
n = 11...14, all channels ON or OFF, nominal load conditions, 4.5V < VDD < 5.5V, 4.5V < VBAT < 40V, all voltages
with respect to PGND, positive current flowing into pin., Tj = -40°C to +150°C, unless otherwise specified
Pos. Parameter Symbol Values Unit TC Conditions
min. typ. max.
Data Sheet 26 Rev. 1.1, 2012-07-31
TLE 8718 SA
Power Stages
5.7 Power Stages OUT15 and OUT16
Table 12 Electrical Characteristics Power Stages OUT15 and OUT16
n = 15 and 16, all channels ON or OFF, nominal load conditions, 4.5V < VDD < 5.5V, 4.5V < VBAT < 40V, all voltages
with respect to PGND, positive current flowing into pin., Tj = -40°C to +150°C, unless otherwise specified
Pos. Parameter Symbol Values Unit TC Conditions
min. typ. max.
Load Current
5.7.1 Continuous Load Current IOUTn ––0.6AC–
5.7.2 Extended current time, Accumulated
operating time.
tOUTn_ec ––100hCV
BAT≤14V,
RL≥6.93Ω
5.7.3 Maximum current (short circuit limited
current / switch off threshold).
IOUTn_max 0.6 – 1.5 A C –
ON-Resistance
5.7.4 On-resistance Tj=-40°C Ron-40_n – – 1440 mΩC3.5V<VDD<5.5V,
IOUTn=0.6A
5.7.5 On-resistance Tj=25°C Ron+25_n – – 1780 mΩC3.5V<VDD<5.5V,
IOUTn=0.6A
5.7.6 On-resistance Tj≤150°C Ron_n – – 2400 mΩA3.5V<VDD<5.5V,
IOUTn=0.6A
Delay times, Slew rates (see Figure 6)
5.7.7 Switch on delay tdon_n ––15µsCRLoad=28.7Ω,
VBAT=14V
5.7.8 Switch off delay tdoff_n ––15µsCRLoad=28.7Ω,
VBAT=14V
5.7.9 Difference of switch on and off delay
tdif_n=tdon_n-tdoff_n
tdif_n -5 – 5 µs C RLoad=28.7Ω,
VBAT=14V
5.7.10 Switch on slew rates son_n 1.5 3.1 7.5 V/µs C RLoad=28.7Ω,
VBAT=14V
5.7.11 Switch off slew rates soff_n 1.5 3.1 7.5 V/µs C RLoad=28.7Ω,
VBAT=14V
Leakage current
5.7.12 Leakage current of the Output Stage Il_OUTn ––5µACVOUTn=14V,
VDD=0V, Tj=60°C
5.7.13 Leakage current of the Output Stage Il_OUTn ––15µACVOUTn=28V,
VDD=0V, Tj=60°C
5.7.14 Leakage current of the Output Stage Il_OUTn ––35µAAVOUTn<28V,
VDD=5V
(diagnosis current
off, OUT1516),
Tj=150°C
Clamping voltage
5.7.15 Clamping voltage VCL_n 50 – 60 V C IOUTn=0.6A
5.7.16 Clamping voltage VCL_n 50 – 60 V A IOUTn=0.2A
TLE 8718 SA
Power Stages
Data Sheet 27 Rev. 1.1, 2012-07-31
Clamping energy 1)
5.7.17 Standard operating range, max. 1.1Mio
cycles
ECL_OUTn ––9mJCTj(0)=35°C,
IOUTn(0)<0.45A
5.7.18 Standard operating range, max. 40Mio
cycles
ECL_OUTn ––6.5mJCTj(0)=125°C,
IOUTn(0)<0.3A
5.7.19 Standard operating range, max. 9Mio
cycles
ECL_OUTn ––6.5mJCTj(0)=140°C,
IOUTn(0)<0.3A
5.7.20 Standard operating range, max. 1Mio
cycles
ECL_OUTn ––6.5mJCTj(0)=150°C,
IOUTn(0)<0.3A
5.7.21 Generator defect, max. 0.02Mio cycles, or
Item 5.7.22
ECL_OUTn ––11mJCTj(0)=35°C,
IOUTn(0)<0.5A
5.7.22 Generator defect, max. 0.02Mio cycles ECL_OUTn ––8mJCTj(0)=145°C,
IOUTn(0)<0.35A
5.7.23 Jump start, max. 0.001Mio cycles, or
Item 5.7.24
ECL_OUTn ––25mJCTj(0)=35°C,
IOUTn(0)<0.75A2)
5.7.24 Jump start, max. 0.001Mio cycles ECL_OUTn ––17mJCTj(0)=85°C,
IOUTn(0)<0.5A
5.7.25 Load dump, max. 10 pulses, or
Item 5.7.26
ECL_OUTn ––50mJCTj(0)=35°C,
IOUTn(0)<0.8A2)
5.7.26 Load dump, max. 10 pulses ECL_OUTn ––30mJCTj(0)=145°C,
IOUTn(0)<0.4A
5.7.27 Load dump, max. 10 pulses, or
Item 5.7.28
ECL_OUTn ––34mJCTj(0)=35°C,
IOUTn(0)<1A2)
5.7.28 Load dump, max. 10 pulses ECL_OUTn ––18mJCTj(0)=145°C,
IOUTn(0)<0.6A
Reverse current through OUTn
5.7.29 In operation mode, static, no destruction IR_S_OUTn -0.6 – – A C Tj=150°C,VDD=5V
5.7.30 Without supply voltage, possibly Leakage
Current out of neighbor channels.
10ms after the reverse current disappears
leakage current criteria are kept.
IR_Soff_OUTn -0.6 – – A C VDD<1V
5.7.31 In operation mode, No unwanted
switching of channels; No unwanted
Reset, No unwanted change of Voltage
Monitoring Thresholds; No unwanted
communication errors or register changes
beside diagnostic registers.
Possibly unwanted diagnostic entries.
Possibly Leakage Current out of neighbor
channels.
IR_S_OUTn -0.2 – – A C Tj=150°C,
VDD=5V
1) Clamping energy, Linear decreasing current, fcl<50Hz
2) PS might switch off to limit the current before reaching the given IOUTn due to reaching IOUTn_max.
Table 12 Electrical Characteristics Power Stages OUT15 and OUT16
n = 15 and 16, all channels ON or OFF, nominal load conditions, 4.5V < VDD < 5.5V, 4.5V < VBAT < 40V, all voltages
with respect to PGND, positive current flowing into pin., Tj = -40°C to +150°C, unless otherwise specified
Pos. Parameter Symbol Values Unit TC Conditions
min. typ. max.
Data Sheet 28 Rev. 1.1, 2012-07-31
TLE 8718 SA
Power Stages
5.8 Power Stages OUT17 and OUT18
Table 13 Electrical Characteristics Power Stages OUT17 and OUT18
n = 17 and 18, all channels ON or OFF, nominal load conditions, 4.5V < VDD < 5.5V, 4.5V < VBAT < 40V, all voltages
with respect to PGND, positive current flowing into pin., Tj = -40°C to +150°C, unless otherwise specified
Pos. Parameter Symbol Values Unit TC Conditions
min. typ. max.
Load Current
5.8.1 Continuous Load Current IOUTn ––0.6AC–
5.8.2 Extended current time, Accumulated
operating time.
tOUTn_ec ––100hCV
BAT≤14V,
RL≥6.93Ω
5.8.3 Maximum current (short circuit limited
current / switch off threshold).
IOUTn_max 0.6 – 1.5 A C –
ON-Resistance
5.8.4 On-resistance Tj=-40°C Ron-40_n ––780mΩCIOUTn=0.6A
5.8.5 On-resistance Tj=25°C Ron+25_n ––962mΩCIOUTn=0.6A
5.8.6 On-resistance Tj≤150°C Ron_n – – 1300 mΩAIOUTn=0.6A
Delay times, Slew rates (see Figure 6)
5.8.7 Switch on delay tdon_n ––10µsCRLoad=28.7Ω,
VBAT=14V
5.8.8 Switch off delay tdoff_n ––10µsCRLoad=28.7Ω,
VBAT=14V
5.8.9 Difference of switch on and off delay
tdif_n=tdon_n-tdoff_n
tdif_n -5 – 5 µs C RLoad=28.7Ω,
VBAT=14V
5.8.10 Switch on slew rates son_n 1.5 3.1 7.5 V/µs C RLoad=28.7Ω,
VBAT=14V
5.8.11 Switch off slew rates soff_n 1.5 3.1 7.5 V/µs C RLoad=28.7Ω,
VBAT=14V
Leakage current
5.8.12 Leakage current of the Output Stage Il_OUTn ––5µACVOUTn=14V,
VDD=0V, Tj=60°C
5.8.13 Leakage current of the Output Stage Il_OUTn ––15µACVOUTn=28V,
VDD=0V, Tj=60°C
5.8.14 Leakage current of the Output Stage Il_OUTn ––35µAAVOUTn<28V,
VDD=5V
(diagnosis current
off, CONREG3),
Tj=150°C
Clamping voltage
5.8.15 Clamping voltage VCL_n 50 – 60 V C IOUTn=0.6A
5.8.16 Clamping voltage VCL_n 50 – 60 V A IOUTn=0.2A
TLE 8718 SA
Power Stages
Data Sheet 29 Rev. 1.1, 2012-07-31
Clamping energy 1)
5.8.17 Standard operating range, max. 1.1Mio
cycles
ECL_OUTn ––9mJCTj(0)=35°C,
IOUTn(0)<0.45A
5.8.18 Standard operating range, max. 40Mio
cycles
ECL_OUTn ––6.5mJCTj(0)=125°C,
IOUTn(0)<0.3A
5.8.19 Standard operating range, max. 9Mio
cycles
ECL_OUTn ––6.5mJCTj(0)=140°C,
IOUTn(0)<0.3A
5.8.20 Standard operating range, max. 1Mio
cycles
ECL_OUTn ––6.5mJCTj(0)=150°C,
IOUTn(0)<0.3A
5.8.21 Generator defect, max. 0.02Mio cycles, or
Item 5.8.22
ECL_OUTn ––11mJCTj(0)=35°C,
IOUTn(0)<0.5A
5.8.22 Generator defect, max. 0.02Mio cycles ECL_OUTn ––8mJCTj(0)=145°C,
IOUTn(0)<0.35A
5.8.23 Jump start, max. 0.001Mio cycles, or
Item 5.8.24
ECL_OUTn ––25mJCTj(0)=35°C,
IOUTn(0)<0.75A2)
5.8.24 Jump start, max. 0.001Mio cycles ECL_OUTn ––17mJCTj(0)=85°C,
IOUTn(0)<0.5A
5.8.25 Load dump, max. 10 pulses, or
Item 5.8.26
ECL_OUTn ––50mJCTj(0)=35°C,
IOUTn(0)<0.8A2)
5.8.26 Load dump, max. 10 pulses ECL_OUTn ––30mJCTj(0)=145°C,
IOUTn(0)<0.4A
5.8.27 Load dump, max. 10 pulses, or
Item 5.8.28
ECL_OUTn ––34mJCTj(0)=35°C,
IOUTn(0)<1A2)
5.8.28 Load dump, max. 10 pulses ECL_OUTn ––18mJCTj(0)=145°C,
IOUTn(0)<0.6A
Reverse current through OUTn
5.8.29 In operation mode, static, no destruction IR_S_OUTn -0.6 – – A C Tj=150°C,VDD=5V
5.8.30 Without supply voltage, possibly Leakage
Current out of neighbor channels.
10ms after the reverse current disappears
leakage current criteria are kept.
IR_Soff_OUTn -0.6 – – A C VDD<1V
5.8.31 In operation mode, No unwanted
switching of channels; No unwanted
Reset, No unwanted change of Voltage
Monitoring Thresholds; No unwanted
communication errors or register changes
beside diagnostic registers.
Possibly unwanted diagnostic entries.
Possibly Leakage Current out of neighbor
channels.
IR_S_OUTn -0.2 – – A C Tj=150°C,
VDD=5V
1) Clamping energy, Linear decreasing current, fcl<50Hz
2) PS might switch off to limit the current before reaching the given IOUTn due to reaching IOUTn_max.
Table 13 Electrical Characteristics Power Stages OUT17 and OUT18
n = 17 and 18, all channels ON or OFF, nominal load conditions, 4.5V < VDD < 5.5V, 4.5V < VBAT < 40V, all voltages
with respect to PGND, positive current flowing into pin., Tj = -40°C to +150°C, unless otherwise specified
Pos. Parameter Symbol Values Unit TC Conditions
min. typ. max.
Data Sheet 30 Rev. 1.1, 2012-07-31
TLE 8718 SA
Power Stages
5.9 Timing Diagram MSC to OUTn
Figure 6 Timing diagram MSC to OUTn (not tested, overview only)
The timing starts with the end of the data frame.
5.10 Parallel connection of PS
All stages are switched on and off simultaneously as all data of the downstream frame becomes valid at the same
time. The micro controller has to ensure that the stages which are connected in parallel have always the same
state (on or off) and same configuration regarding current limitation (OUTn_SCB). Exceptions are OUT15 and
OUT16 which are controlled by command. Therefor these two stages can only be connected in parallel with each
other.
The application has to take into account that all maximum ratings are observed (e.g. in case of short circuit the
ground current and the power dissipation has to be taken into account).
The Junction Temperature of the power stages which are switched in parallel has to be equal. No parasitic
resistors between the parallel connected output channels are considered in Table 14. If channels are connected
in parallel, they must be connected in parallel for the whole lifetime (no switching between “parallel connection”
and “non parallel connection” allowed during lifetime for a single device).
Maximum current:
The maximum value of the maximum current IOUTpar_max(max) of the parallel connected stages is the sum of the
corresponding maximum current values IOUTn_max(max). The minimum value of maximum current IOUTn_max(min) is
shown in Table 14.
ON-Resistance:
The maximum ON-Resistance at 150°C of a parallel connection Ron_par = 1 / Σ (1 / Ron_n) and the corresponding
condition IOUTpar_max(min) can be seen in Table 14.
Clamping Energy:
Only equivalent operating points could be added. The conditions (Tj(0), IOUTn(0)) for parallel connected stages are
the same as for a single stage. The clamping energy of parallel connected stages is
ECL_par(max) = Clamping_energy_factor × Σ ECL_OUTn(max) and shown in Table 15.
The performance during parallel connection of channels is specified by design and not subject to the production
test. Only the combinations defined in Table 14 and Table 15 are supported for parallel connection.
s
off
s
on
t
don
t
son
t
doff
t
soff
t
t
0.8VBAT
0.2VBAT
Drawing8_ Timing_M SC_to_ OUTn.vsd
Command Frame
VBAT
VOUTn
OUTn ON OUTn OFF
t
dif
= t
don
-t
doff
TLE 8718 SA
Power Stages
Data Sheet 31 Rev. 1.1, 2012-07-31
Table 14 Parallel connection, definition of Maximum Current and ON Resistance1)
OUT
1, 3
OUT
2, 4
OUT
5...8
OUT
9, 10
OUT
11...14
OUT
15,16
OUT
17,18
OUT
1, 3
OUT
2, 4
OUT
5...8
OUT
9, 10
OUT
11...14
OUT
15,16
OUT
17,18
Maximum current for 2 stages [A]2) ON Resistance for 2 stages [mΩ]
OUT1, 3 13.6 6.6 6.7 4.7 6.7 – – 1053) 131 163 145 163 – –
OUT2, 4 6.6 5.1 4.1 3.8 4.1 – – 131 175 236 201 236 – –
OUT5...8 6.7 4.1 3.7 3.1 3.7 – – 163 236 360 284 360 – –
OUT9, 10 5 3.8 3.1 3.7 3.1 – – 145 201 284 235 284 – –
OUT11...14 6.7 4.1 3.7 3.1 3.7 – – 163 236 360 284 360 – –
OUT15…16––––– 1 – ––––– 1200–
OUT17…18––––– – 1 ––––– – 650
Maximum current for 3 stages [A]2) ON Resistance for 3 stages [mΩ]
OUT5...8––5.2–– – – ––240–– – –
OUT11...14––––5.2– – ––––240– –
Maximum current for 4 stages [A]2) ON Resistance for 4 stages [mΩ]
OUT5...8––6.5–– – – ––180–– – –
OUT11...14––––6.5– – ––––180– –
1) The performance during parallel connection of the channels is specified by design and not subject to production test.
2) The defined current could be forced, without running into overcurrent shutdown. Nevertheless the metal lines on the PCB
must be designed for ΣIOUTn_max (max).
3) The defined ON Resistance is valid for operation without clamping (resistive load or inductive load with external
freewheeling).
Table 15 Parallel connection, definition of Clamping_energy_factor1)
1) The performance during parallel connection of the channels is specified by design and not subject to production test.
OUT
5...8
OUT
9, 10
OUT
11...14
OUT
15,16
OUT
17,18
Clamping_energy_factor for 2 stages
OUT5...8 0.6 2) 2)
OUT9, 10 2)
2) The clamping energy of parallel connected stages is the same as clamping energy of a single OUT5...8 stage.
0.6 3)
OUT11...14 2) 3)
3) The clamping energy of parallel connected stages is the same as clamping energy of a single OUT11...14 stage.
0.6
OUT15…16 – – – 0.6 –
OUT17…18––––0.6
Clamping_energy_factor for 3 stages
OUT5...8 0.45 – – – –
OUT11...14 – – 0.45 – –
Clamping_energy_factor for 4 stages
OUT5...8 0.4 – – – –
OUT11...14––0.4––
Data Sheet 32 Rev. 1.1, 2012-07-31
TLE 8718 SA
Device Self Protection
6 Device Self Protection
6.1 Short Circuit Protection
All PS are short circuit protected - see Chapter 4.2.
In case of a short circuit to battery voltage the output current is limited by internal current control (OUT1...18).
After a delay time (tDIAG_SCB) the output is turned off, if it´s configured in MSC register CONREG1, 2, OUT1516 to
switch off (OUT1-18).
6.2 Over Temperature Shut Down
If critical overtemperature (overtemperature shut down threshold TOUTn_OTSD) is detected in one stage the stage is
switched off to protect the circuit against damage, see logic diagram, state D (Chapter 8.3).
All self protection circuits (Short Circuit to Battery and Over Temperature Shut Down) are functional in
undervoltage and overvoltage condition from VDD_POR up to VDD_MR.
Registration of short circuit to battery (SCB) and overtemperature (DOT) in the diagnostic registers during
undervoltage or overvoltage condition is not guaranteed. But the stage is switched off as defined in configuration
register.
6.3 Battery Voltage Monitoring
The Battery Voltage Monitoring allows the detection of Over Voltage Conditions. In case of Over Voltage
VSVBATT_OVSD, the monitoring shuts down the Power Stages after a delay time tOUT_OVSD. The Battery Voltage
Monitoring acts as an Enable of the Output Stages and does not clear the control bits.
This functions supports the reduction of clamping energy to be dissipated in the power stage in case of over
voltage conditions, such as Load Dumps.
Figure 7 Battery Voltage Monitoring
VSVBATT
VSVBATT_OVSD
OUT1...18
„ON“
VBATT_Mon.svg
t
t
OUT_OVSD
VSVBATT_HYS
tOUT_OVSON
„OFF“
3V
18V
ISVBATT_PD
ISVBATT_PDh
t
t
I
SVBATT
min
max
min
max
min min
max
TLE 8718 SA
Device Self Protection
Data Sheet 33 Rev. 1.1, 2012-07-31
6.4 Electrical Characteristics
Table 16 Self Protections
4.5V < VDD < 5.5V, 4.5V < VBAT < 40V, all voltages with respect to PGND, positive current flowing into pin.,
Tj = -40°C to +150°C, unless otherwise specified
Pos. Parameter Symbol Values Unit TC Conditions
min. typ. max.
Self Protection
6.4.1 Self protection temperature threshold
Junction temperature of OUTn
(n=1...18)1)
1) See Chapter 8, Item 8.5.6 Diagnosis, Overtemperature warning diagnosis threshold.
TOUTn_OTSD TOUTn_
OTW+0
–TOUTn_
OTW+30
KC–
6.4.2 Self protection temperature
hysteresis, OUTn (n=1...18)
TOUTn_
OTSDHYS
–10– KC–
SVBATT Pin (Battery Voltage Monitoring Pin)
6.4.3 SVBATT Pin Voltage, Battery
Overvoltage Shut Down Threshold
VSVBATT_
OVSD
29 – 35 V B
6.4.4 SVBATT Pin Voltage, Battery
Overvoltage Shut Down Hysteresis
VSVBATT_
HYS
0.25 – 1 V C
6.4.5 SVBATT Pin internal pull down
current
ISVBATT_PD 1–20µAC3V<VSVBATT<18V
6.4.6 SVBATT Pin internal pull down
current
ISVBATT_PDh 20 – 80 µA C 2)
2) VSVBATT=VSVBATT_OVSD during voltage increase, respectively VSVBATT=VSVBATT_OVSD-VSVBATT_HYS during voltage
decrease. See Figure 7.
6.4.7 SVBATT Pin internal pull down
current
ISVBATT_PD 1 – 500 µA C 18V<VSVBATT<40V
6.4.8 Filter time before Output Stages shut
down in case of VSVBATT_OVSD is
exceeded
tOUT_OVSD 5–20µsB–
6.4.9 Filter time before Output Stages
switch on again
tOUT_OVSON 60 – 135 µs B –
6.4.10 Factory test mode activation VSVBATT_TM ––-2VB
3)
3) Not intended to be used in application. Factory test mode entry condition violates Absolute Maximum Rating Item 4.2.10.
Data Sheet 34 Rev. 1.1, 2012-07-31
TLE 8718 SA
Supervisory (DIS5_10, DELAYIN, DELAYOUT)
7 Supervisory (DIS5_10, DELAYIN, DELAYOUT)
Table 17 DIS5_10, DELAYIN, DELAYOUT
4.5V < VDD < 5.5V, 4.5V < VBAT < 40V, all voltages with respect to PGND, positive current flowing into pin.,
Tj = -40°C to +150°C, unless otherwise specified
Pos. Parameter Symbol Values Unit TC Conditions
min. typ. max.
Pin DIS5_10
7.0.1 DIS5_10 input low level VDIS5_10_L -0.3 – 1 V B –
7.0.2 DIS5_10 input high level VDIS5_10_H 2–36VB–
7.0.3 DIS5_10 input hysteresis VDIS5_10_HYS 0.1 – 0.5 V C –
7.0.4 DIS5_10 input current IDIS5_10 -100 – 5 µA C -0.2V<VDIS5_10< VDD
7.0.5 DIS5_10 input current IDIS5_10 -400 – – µA C -0.3V<VDIS5_10
7.0.6 DIS5_10 Input current IDIS5_10 ––100µACVDD<VDIS5_10< 36V
7.0.7 DIS5_10 pull-up current IDIS5_10 -100 – -20 µA A 0V<VDIS5_10< VDD –
1.5V
7.0.8 Filtering time before switching
OUTn, high- or low-pulses on
DIS5_10, n=5...10
tDIS5_10 60 – 135 µs C –
Pin DELAYIN for DELAYOUT function (lower threshold)
7.0.9 DELAYIN input low level for
DELAYOUT
VDELAYIN_L -0.3 – 0.16*VDD VB–
7.0.10 DELAYIN input high level for
DELAYOUT
VDELAYIN_H 0.24*VDD –36 VB–
7.0.11 DELAYIN input hysteresis for
DELAYOUT
VDELAYIN_HYS 0.02 – 0.1 V C –
7.0.12 DELAYIN input pull-down
resistor
RDELAYIN 168 – 312 kΩA1V<VDELAYIN<40V
7.0.13 DELAYIN input current IDELAYIN -400 – 20 µA C -0.3V<VDELAYIN <1V
7.0.14 Rising edge long filter time
before switching DELAYOUT or
RES15_16
tDELAYIN_GLITC
H_long
7.5 – 24 ms C CONREG3.6=’1’
7.0.15 Rising edge short filter time
before switching DELAYOUT or
RES15_16
tDELAYIN_GLITC
H_short
60 – 135 µs C CONREG3.6=’0’
DELAYIN - Filtering time before switching DELAYOUT low
7.0.16 Long delay for tDELAYIN_x, default tDELAYIN_L 800 – 1600 ms C CONREG4.0=’1’,
CONREG4.1=’1’
7.0.17 Medium long delay for tDELAYIN_x tDELAYIN_ML 400 – 800 ms C CONREG4.0=’1’,
CONREG4.1=’0’
7.0.18 Medium short delay for
tDELAYIN_x
tDELAYIN_MS 200 – 400 ms C CONREG4.0=’0’,
CONREG4.1=’1’
7.0.19 Short delay for tDELAYIN_x tDELAYIN_S 100 – 200 ms C CONREG4.0=’0’,
CONREG4.1=’0’
TLE 8718 SA
Supervisory (DIS5_10, DELAYIN, DELAYOUT)
Data Sheet 35 Rev. 1.1, 2012-07-31
Figure 8 Timing DELAYIN
Pin DELAYIN for RES15_16 function (higher threshold)
7.0.20 DELAYIN input low level for
RES15_16
VDELAYIN_RES
15_16_L
-0.3 – 0.44*VDD VB–
7.0.21 DELAYIN input high level for
RES15_16
VDELAYIN_RES
15_16_H
0.52*VDD –36 VB–
7.0.22 DELAYIN input hysteresis for
RES15_16
VDELAYIN_RES
15_16_HYS
0.02 – 0.1 V C –
Pin DELAYOUT
7.0.23 DELAYOUT output low voltage VDELAYOUT_O
UTL
––0.7VAVDD=2.5V,
IDELAYOUT<2mA
7.0.24 DELAYOUT output low voltage VDELAYOUT_O
UTL
––1VA2.5V<VDD<36V,
IDELAYOUT<6.5mA
7.0.25 Maximum current (short circuit
limited current)1)
IDELAYOUT_ma
x
15 – – mA C –
7.0.26 DELAYOUT passive output
high voltage
VDELAYOUT_O
UTH
VDD - 1.5 VDD – V A no load
7.0.27 DELAYOUT pull-up current IDELAYOUT_INL -50 – -4 µA A 0V<VDELAYOUT< VDD–
1.5V, 2)
7.0.28 DELAYOUT input current IDELAYOUT_INH -10 – 10 µA C VDD<VDELAYOUT< 36V
1) Integrated protection functions are designed to prevent IC destruction under fault conditions. Fault conditions are
considered as “outside” normal operating range. Protection functions are not designed for continuous or repetitive
operation. Application must take care, that current into this pin does not exceed 15mA.
2) DELAYOUT as Output is not active
Table 17 DIS5_10, DELAYIN, DELAYOUT
4.5V < VDD < 5.5V, 4.5V < VBAT < 40V, all voltages with respect to PGND, positive current flowing into pin.,
Tj = -40°C to +150°C, unless otherwise specified
Pos. Parameter Symbol Values Unit TC Conditions
min. typ. max.
V
DELAYIN_RES15_16_H
DELAYIN
DELAYOUT
[V]
t
DELAYIN_GLITCH_x
t
DELAYIN_x
t
DELAYIN_GLITCH_x
*
t
DELAYIN_x
RES15_16
t
t
t
Inter lock _DELAYIN .vsd
V
DELAYIN_RES15_16_L
V
DELAYIN_H
V
DELAYIN_L
< t
DELAYIN_GLITCH_x
t
DELAYIN_GLITCH_x
t
DELAYIN_GLITCH_x
*
OUT15...16 controlable
via OUT1516
OUT15...16 OFF
t
DELAYIN_GLITCH_x
depending on CONREG3.Bit6
t
DELAYIN_x
depending on CONREG4.Bit0 and Bit1
t
DELAYIN_GLITCH_x
t
DELAYIN_GLITCH_x
0.16*V
DD
0.24*V
DD
0.52 *V
DD
0.44 *V
DD
* Filter for DELAYOUT is independend from RES 15_16. That´s why they may not switch synchronously.
Data Sheet 36 Rev. 1.1, 2012-07-31
TLE 8718 SA
Diagnosis
8 Diagnosis
8.1 Diagnostic Functions
All PS have fault diagnostic functions:
• short circuit to battery: (SCB) can be detected if stages are turned on
• short circuit to ground: (SCG) can be detected if stages are turned off
• open load: (OL) can be detected if stages are turned off
• Diagnosis overtemperature: (DOT) is set if Overtemperature Warning OTW occurs in ON-state or
Overtemperature Shutdown OTSD occurs in any state
SCB is recognized if the output current reaches IOUTn_max when the stage is switched on. If, after the filtering time
(tDIAG_SCB) has expired, the failure is still present, it is stored in the diagnostic register (DIAREG1...5). This may be
caused by a short circuit to battery voltage (VBAT up to VBAT_SC) or by a load with too low impedance (e.g. load
switched on under cold conditions).
In addition to this, there is the extended SCB behavior available, when CONREG3.EXT_SCB=”1”. In this case
VOUTn is checked in addition to IOUTn and the diagnosis register SCB is only set, if IOUTn_max and VOL is reached for
longer than tDIAG_SCB. This feature is available for OUT5...14 only and shown in Figure 9.
A SCB condition is stored in the diagnosis register. It turns off the output dependent on configuration register
(CONREG1, CONREG2, OUT1516). The output can be turned on again even if the SCB bit in the diagnosis
registers have not been cleared yet (e.g. by polling the registers). Turning on the outputs won't clear the SCB bit.
The output current IOUTn may overshoot before the current limiter reacts and limits the output current to IOUTn_max.
However, this overshoot (which depends on the external load) will not damage the device.
TLE 8718 SA
Diagnosis
Data Sheet 37 Rev. 1.1, 2012-07-31
Figure 9 SCB Diagnosis function
Depending on the configuration of the stage (CONREG1, 2, OUT1516) the stage is switched off or remains
functional in current limited mode with fault entry in the diagnostic register.
The OTSD threshold (TOUTn_OTSD) has a hysteresis and switches off the channel (see Chapter 6); The OTW
(TOUTn_OTW) threshold has no hysteresis and is diagnosis only. The stage is not switched off by OTW. Only if
temperature rises above shutdown threshold (TOUTn_OTSD) the stage is disabled for device self protection. After this,
the stage won´t be enabled again until temperature falls below Self protection temperature hysteresis
(TOUTn_OTSDHYS) (see Chapter 6).
Example 2
Example 1
SCB_extended_Diagnostic.vsd
current over -shoot and voltage behavior dependending on external load condition
t
I
OUTn_max
I
OUTn
CONREG3.EXT_SCB=0
t
DIAG_SCB
CONREG1/2/OUT1516.OUTn_SCB=1
Here is the
diagnositc entry set
t
I
OUTn_max
I
OUTn
t
DIAG _SCB
Here is the
diagnositc entry set
~
~
Thermal toggling
possible
t
I
OUTn_max
I
OUTn
t
V
OUTn
t
DIAG_SCB
V
OUTn_OL
Here is the
diagnositc entry set
t
I
OUTn_max
I
OUTn
t
V
OUTn
t
DIAG_SCB
V
OUTn_OL
Here is the
diagnositc entry set
~
~
Thermal toggling
possible
~
~
Filter is startet when
IOUTn and VOUTn has
exeeded their limits
t
I
OUTn_max
I
OUTn
t
V
OUTn
t
DIAG _SCB
V
OUTn_OL
Here is the
diagnositc entry set
t
I
OUTn_max
I
OUTn
t
V
OUTn
t
DIAG _SCB
V
OUTn_OL
Here is the
diagnositc entry set
~
~
Thermal toggling
possible
~
~
Filter is startet when
IOUTn and VOUTn has
exeeded their limits
CONREG1/2/OUT1516.OUTn_SCB=0
CONREG3.EXT_SCB=1
Example 3
t
I
OUTn_max
I
OUTn
V
OUTn
V
OUTn_OL
t
I
OUTn_max
I
OUTn
V
OUTn
V
OUTn_OL
Diagnostic entry accures
because of OT
~
~
~
~
tt
If OT is not reached, there is
no diagnostic entry
CONREG1/2/OUT1516.OUTn_SCB=1 CONREG1/2/OUT1516.OUTn_SCB=0
Data Sheet 38 Rev. 1.1, 2012-07-31
TLE 8718 SA
Diagnosis
Figure 10 Temperature Thresholds (see also Chapter 6)
OL or SCG is recognized using two thresholds (VOUTn_SCG and VOUTn_OL) and a bias voltage source with current
limit for each output.
For OUT11...OUT18 it is possible by configuration to switch off the internal diagnostic pull-down current source.
In this case diagnosis of OL is deactivated, no entry of OL into diagnostic register, even if VOUTn_SCG < VOUTn <
VOUTn_OL. Diagnosis of SCG remains functional.
See Chapter 8.3 for specified values of diagnostic currents and threshold voltages.
The fault conditions SCB, SCG, OL and DOT will not be stored until an integrated filtering time (tDIAG_SCB, tDIAG_SCG,
tDIAG_OL, tDIAG_OTW) has expired. If at one output, several errors occur in a sequence, the newest detected error is
stored to the diagnosis register (after filtering time).
Over Temperature Warning [TOTW],
Over Temperature Shut Down [TOTSD],
Over Temperature Shut Down Hysteresis [TOTSD_HYS],
for OUT1...18
TOTW_TOTSD_TOTSDHYST.vsd
TJ
TOTSD
TOTSD-HYS
TOTW
Case 1: TOTSD-HYS > TOTW Case 2: TOTSD-HYS < TOTW
tOTW
DOT
„set“
OUTn
„ON“
TOTSD
TOTSD-HYS
TOTW
tOTW
tt
Ref.
1
TJ
Ref.
2
>=1
0
0
0
TOTW
TOTW + 10K = TOTSD
DOT
&
0
0
0
„ON“
tOTW
OUTn „OFF“
DOT
„set“
OUTn
„ON“
TLE 8718 SA
Diagnosis
Data Sheet 39 Rev. 1.1, 2012-07-31
Figure 11 SCG and OL diagnosis function (not tested, overview only)
8.2 Encoding of Diagnostic Information
All fault conditions are encoded in two bits per stage and are stored in the corresponding registers (DIAREG1...5).
Additionally there is one central diagnostic overtemperature bit (COTW) (this bit is set to ‘0’ if DOT occurred at any
stage).
The common failure bit (DIAREG6, bit FAILURE_FLAG) is set to ‘0’ if SCB, SCG, OL or DOT is detected on any
output stage (OUT1...18). Only if all the stage diagnostic bits are ‘1’, the FAILURE_FLAG bit is ‘1’.
The diagnosis registers can be read via MSC.
When a valid MSC read command (RD_DATA) is detected, the selected diagnosis register information is moved
to a shift register for transmission (MSC upstream). At the same time the selected diagnosis register is cleared.
Table 18 Encoding of diagnosis information
Encoding of the diagnosis bits of the device
OUTn_DIA2 OUTn_DIA1 description
1 1 Power stage ok
1 0 Short circuit to battery (SBC) or diagnostic overtemperature
(DOT)
0 1 Open load (OL)
0 0 Short circuit to ground (SCG)
IOUTn
0
IOUTn_DIA_N(min)
VBAT
VOUTn_BIAS VOUTn
O.K.OL
SCG
IOUTn_DIA _P(max)
IOUTn_DIA_N(max)
IOUTn_DIA_P(min)
Output stage is switched off for this measurement
VOUTn_OL
VOUTn_SCG
600µA
220µA
-100µA
-300µA
IOUTn
0
IOUTn_DIA_N(min)
VBAT VOUTn
O.K.
SCG
IOUTn_DIA_N(max)
Il_OUTn(max)
Dr awing6 _SCG _and _ OL _Diagnosis _ Function .vsd
VOUTn_SCG
20...35µA
-100µA
-300µA
Diagnostic pull-down current and Open Load OL on
Diagnostic pull -down current and Open Load OL off
VOUTn_BIAS
Data Sheet 40 Rev. 1.1, 2012-07-31
TLE 8718 SA
Diagnosis
8.3 State Diagram of the Device Diagnosis
Figure 12 State diagram of the device diagnosis (not tested, overview only)
Outputs are switched inactive if VDD is out of range or RST respectively ABE is externally pulled low. After a reset
the stages start in state A (OFF state). If a stage is getting overheated above the overtemperature shutdown
threshold (TOUTn_OTSD, Item 6.4.1) it is entering state D (switched off for self protection) independent from its
current state. Leaving this state is only possible if temperature falls below Self Protection Temperature Hysteresis
(TOUTn_OTSDHYS, Item 6.4.2).
SCB
n=1.. 4, 15 ..18
and 5..14 if
EXT_SCB=0
State B
ON
current internally limited to
OUTn MAX
Control = On
OUTn = On
State C
OFF forced
by sho rt circuit
Control = On
OUTn = Off
State D
Overtemperature
self protection OFF
Control = x
OUTn = Off
State A
OFF
Control = Off
OUTn = Off
OL
no OL
SCG
SCG
no SCG
OTSD
no OTW
SCB
no SCB
Control=OFF
an d b elo w T
OUTn_OTSDHY S
if
OTSD was reached before
Configuration:
switch OFF on SCB
below T
OUTn_OTSDHYS
and Control=ON
below T
OUTn _OTSDHYS
and Control=OFF
Control=ON
OTW
OTSD
OTSD
Drawing7 _State _Diagram .vsd
no
OTW
OTW
OTW
Configuration:
current limit on SCB
SCB&V
OUT
>V
OUT_OL
n=5..14 if EXT_SCB=1
Fault entry
11 (no fault)
Fault entry
01 (OL)
Fault entry
11 (no fault)
Fault entry
10 (DOT)
Fault entry
10 (DOT)
Fault entry
10 (DOT)
Fault entry
10 (SCB)
t
DIAG_OL
t
DIAG_SCG
t
DIAG_SCB
t
OUTn_OTW
t
OUTn_OTW
OL
Control=OFF
RD_DATA
WR_RST
Fault entry
11 (no fault)
RD_DATA
WR_RST
OTW
Fault entry
10 (DOT)
Fault entry
00 (SCG)
RD_DATA
WR_RST
TLE 8718 SA
Diagnosis
Data Sheet 41 Rev. 1.1, 2012-07-31
8.4 Reset of the Diagnostic Information
The diagnostic registers are set to its reset value individually at readout by their RD_DATA command, or all
together by WR_RST command, POR or RST.
At the same time, the filters tDIAG_SCB, tDIAG_SCG, tDIAG_OL are re-set. The filter tDIAG_OTW is not re-set.
In the case a stage is shut off because of SCB, by readout of the diagnostic information via RD_DATA instruction
the DIAREGx entry is cleared and output is activated again. Because SCB could only be detected when the stage
is switched on, the output is activated and shut off again after the shutoff delay, if SCB condition is still existent.
Some register bits are not cleared by read-out or reset, see tables in Chapter 12.2.
8.5 Electrical Characteristics
Table 19 Diagnosis
4.5V < VDD < 5.5V, 4.5V < VBAT < 40V, all voltages with respect to PGND, positive current flowing into pin.,
Tj = -40°C to +150°C, unless otherwise specified
Pos. Parameter Symbol Values Unit TC Conditions
min. typ. max.
Diagnosis filter time, delay time fault condition to switch off, OUTn (n=1...18)
8.5.1 Overtemperature Warning tDIAG_OTW 15 – 30 µs C –
8.5.2 Short to Battery Voltage tDIAG_SCB 60 – 135 µs B –
8.5.3 Short to Ground tDIAG_SCG 60 – 135 µs B –
8.5.4 Open Load tDIAG_OL 60 – 135 µs B –
8.5.5 Diagnosis Fault entry delay, delay
time after diagnosis filter time has
expired until fault entry is stored in
corresponding diagnostic register
tDIAG_DELAY 0–5µsC–
8.5.6 Overtemperature warning
diagnosis threshold
TOUTn_OTW 150 – 190 °C C –
8.5.7 Short circuit to ground diagnosis
threshold
VOUTn_SCG 0.6*VDD
-0.2
–0.6*
VDD
+0.2
VB–
8.5.8 Open load diagnosis threshold
stage disabled
VOUTn_OL VDD-0.2 – VDD+0.3 V B 1)
8.5.9 Diagnostic bias voltage stage
disabled
VOUTn_BIAS 0.7*VDD
-0.2
–0.7*VDD
+0.2
VA
1)
Diagnostic current of OUTn 1)
8.5.10 Diagnostic pull down current IOUTn_DIA_P 270 – 550 µA A VOUTn=14V
8.5.11 Diagnostic pull down current IOUTn_DIA_P 220 – 550 µA C VOUTn_OL<
VOUTn<VBAT
8.5.12 Diagnostic pull up current IOUTn_DIA_N -300 – -100 µA A VOUTn=0V
8.5.13 Diagnostic pull up current IOUTn_DIA_N -300 – -100 µA C 0V<VOUTn
<VOUTn_SCG
Data Sheet 42 Rev. 1.1, 2012-07-31
TLE 8718 SA
Diagnosis
8.6 Timing
Figure 13 Timing and logic entry of diagnosis information to diagnosis register
Reverse Current Detection OUTn (n=1...18)
8.5.14 Reverse Current detection
voltage
VREVCUR -0.3 – -0.03 V C –
8.5.15 Reverse Current filter time tREVCUR 26 – 60 µs C –
1) OUTn_DIAC=’1’
Table 19 Diagnosis
4.5V < VDD < 5.5V, 4.5V < VBAT < 40V, all voltages with respect to PGND, positive current flowing into pin.,
Tj = -40°C to +150°C, unless otherwise specified
Pos. Parameter Symbol Values Unit TC Conditions
min. typ. max.
OL
SCG t
DIAG_OL
t
DIAG_SCG
DIAG 11 OK 01 OL 00 SCG
RD_DATAx
t
DIAG_OL
11 OK 01 OL
RD_DATAx
11 OK
OL
SCG t
DIAG_OL
t
DIAG_SCG
DIAG 11 OK 00 SCG
RD_DATAx
t
DIAG_OL
11 OK 01 OL
RD_DATAx
11 OK
OUTn = OFF Æ OUT-Voltage decreases slowly
OUTn = OFF Æ OUT-Voltage decreases fast
OUTn = ON to OFF Æ OUT-Voltage increases fast
OL
SCG
t
DIAG_OL
t
DIAG_SCG
DIAG 11 OK
ON OFF
OUTn = ON to OFF Æ OUT-Voltage increases slow
OL
SCG
t
DIAG_OL
t
DIAG_SCG
DIAG 11 OK
ON OFF
01 OL
t
Diagnosis _entr y _tim ing.vsd
TLE 8718 SA
Supply, VDD Monitoring, Reset and ABE
Data Sheet 43 Rev. 1.1, 2012-07-31
9 Supply, VDD Monitoring, Reset and ABE
9.1 General functions of VDD Monitoring
VDD -Monitoring is measured with reference to GNDABE. Power On Reset (POR) is measured with reference to
PGND.
The state of VDD monitoring is stored in DIAREG7 and can be read out via MSC.
VDD monitoring detects supply voltage outside the specified range. It disables stages but does not reset registers
CONREGx, DIAREGx
In case of VDD failure, the stages must be switched off according CONREG4.ABE_IMPACT -setting, even if Pin
ABE is high level because of external short circuit to VDD or VBAT (up to VBAT_SC).
Figure 14 VDD monitoring function (not tested, overview only)
Figure 14 explanation: In the “shaded” area of “Outputs”, the output channels may be switches ON or OFF by
MSC DATA-Frame. In shaded area of “OUT15, OUT16” the output channels may be switched or remain ON or
OFF dependent on the register settings OUT1516.
OUT15 and OUT16 can´t be switched on during over-, undervoltage, ABE, MSC_MON or RST. Switching off is
possible (see Figure 1).
POR (VDD < VDD_POR) switches off all stages without delay.
high
low
Outputs
OUT16*
OUT15*
*: configured to delayed reset behaviour
**: refered to GNDABE
ABE
on
off
on
off
t
power on reset,
switched OFF
Outputs remain OFF if
bit MON_LATCH is '1'
OUT16, OUT16 are switched
OFF after tDELRES or by
MSC COMMAND
t
FIL_ON
t
FIL
_OFF
t
FIL _ON
t
FIL _OFF
t
POR
t
FIL_ON
t
FIL_OFF
t
ABE
or t
FIL_OFF_DEL
Depending on
ABE_IMPACT
t
DELRES
t
FIL _ON
Change of ABE
caused by
external event
Drawing20_VDD_monitor ing _ functi on .vsd
36V
5.25 ... 5.5V **
4. 2... 4.4V **
3...3.5V V
DD_POR
V
DD_THH
V
DD_THL
V
DD_MR_max
max 2.5V V
DD_RES
Behavior up to
V
DD_RES
undefied
t
POR
Data Sheet 44 Rev. 1.1, 2012-07-31
TLE 8718 SA
Supply, VDD Monitoring, Reset and ABE
9.2 VDD Undervoltage
If the VDD voltage is lower than the supply voltage supervisory lower threshold (VDD_THL), all output stages are shut
off after a filtering time (tFIL_OFF) and active low signal is generated at the bi-directional pin ABE.
The only exception is OUT15 and OUT16, if configured to delayed reset behavior. These outputs then remain
functional in undervoltage condition, until
• filtering time (tDELRES) has expired, or
• stage is switched off by MSC command or
•VDD falls below the power-on-reset threshold (VDD_POR) or
• RES15_16 gets active.
OUT15 or OUT16 cannot be switched on by MSC command in undervoltage condition.
At the transition from undervoltage to normal voltage the signal at Pin ABE goes high after a filtering time (tFIL_ON)
has expired. Output registers are cleared to “1” (output stages remain off until switched on again via MSC data
frame). During undervoltage condition no new fault conditions are written to diagnosis registers, the content is
frozen. However, data and configuration registers still can be accessed (read and write) using MSC commands.
If VDD falls below the power-on-reset supply voltage (VDD_POR) all stages are shut off and ABE is switched active
low.
When VDD is rising above the power-on-reset supply voltage threshold (VDD_POR) a power-on-reset is internally
generated (tPOR), setting all registers to its default state (all stages switched off, all registers cleared to default).
9.3 VDD Overvoltage
If the VDD voltage is higher than the supply voltage supervisory upper threshold (VDD_THH), all output stages are
shut off after a filtering time (tFIL_OFF) and active low signal is generated at the bi-directional Pin ABE.
The only exception is OUT15 and OUT16, if configured to delayed reset behavior. These outputs then remain
functional in overvoltage condition, until
• filtering time (tDELRES) has expired or
• stage is switched off by MSC command or
• RES15_16 gets active.
OUT15 or OUT16 cannot be switched on by MSC command in overvoltage condition.
The behavior of the ABE level and output stages on the return of VDD from overvoltage to the correct range is
configured in CONREG4, bit MON_LATCH).
– 1: ABE is latched and outputs remain off after overvoltage, tDELRES continues to expire and switches off
OUT15 and OUT16. Return to normal operation is only possible with power-on reset or by changing this bit
via MSC command to “0”.
– 0: ABE is inactive after VDD returned to normal operating voltage and filtering time has expired.
At the transition from overvoltage to normal condition, output registers are cleared to “1” (output stages remain off
until switched on again via MSC). During overvoltage condition no new fault conditions are written to diagnosis
registers, the content is frozen. However, data and configuration registers still can be accessed (read and write)
using MSC commands.
TLE 8718 SA
Supply, VDD Monitoring, Reset and ABE
Data Sheet 45 Rev. 1.1, 2012-07-31
9.4 Thresholds
Figure 15 Operating Supply Range
Device
overall
V
DD
Monitoring
Output
stages
MSC
function
0V
V
DD
Reset
logic
Drawing18 _Supply _Range .vsd
A) Switching OUT1...14, 17, 18 OFF after t
FIL_OFF
B) Switching OUT15, 16 OFF after t
FIL _O FF
or t
DELRES
if configured to delayed reset behavior via OUT1516
* Refered to GNDABE
V
DD_MR_max
V
DD_max
V
DD_THH
V
DD_min
V
DD_THL
V
DD_POR
V
DD_RES
V
DD_MR_min
36V
5.5 V
5.25 ... 5.5 V*
4. 2... 4.4 V*
4.5 V
3... 3. 5V
2.5 V
-0 .3V
not
defined
no damage
full compliance to
specified values
no damage
not
defined
not
defined
not defined internal
reset
no logic misfunction
(no unwanted switching of stages…)
not
defined
not defined ABE output inactive
(ABE high)
ABE output
active low
ABE
output active low
not
defined
not defined
not
defined
not defined Stages follow MSC
A)
B)
All
OFF
MSC
disable MSC functional within specified values
A)
B)
Data Sheet 46 Rev. 1.1, 2012-07-31
TLE 8718 SA
Supply, VDD Monitoring, Reset and ABE
9.5 ABE Pin
ABE is functional as input and output.
During a low on pin ABE (pulled low by the internal open drain device or forced low by an external source), the
output registers are cleared to ‘1’ switching off outputs OUT1…OUT14, OUT17, OUT18. Behavior of OUT15 and
OUT16 depends on configuration register settings. Programmable filter times apply. See Figure 1 and Figure 16
for details.
9.6 Testing of VDD Monitoring
Figure 16 Block Diagram of VDD Monitoring
The stages are switched off if under- or overvoltage is detected in any case OUT15,16 might be delayed,
dependent on register OUT1516.
9.7 Testing procedure of VDD Monitoring in the application
Testing upper threshold in application (VDD is 5V):
By writing xxxxx00xb into CONREG4, the overvoltage threshold is reduced to VTEST_THH. In DIAREG7 bit 5 and 7
have to be LOW then. After writing xxxxx1x0b to CONREG4, bit 5 and 7 in DIAREG7 must be HIGH again.
Testing lower threshold in application (VDD is 5V):
By writing xxxxx01xb into CONREG4, the undervoltage threshold is increased to VTEST_THL. In DIAREG7 bit 6 and
7 have to be LOW then. After writing xxxxx1xxb to CONREG4, bit 6 and 7 in DIAREG7 must be HIGH again.
+
-
S Q
R
Set dominant
Internal
reference
VDD
&
Power On
Reset
ABE
V
DD
PGND
1
&
bit #7 #6 #5
DIAREG7
Hyster-
esis
Under
voltage
= „L“
Over
voltage
= „L“
CONREG 4 bit #6 #5
Test overvoltage threshold
Test undervoltage threshold
default, normal operation
CONREG4
bit #7
(MON_LATCH)
1
DIAREG6
bit #3
GNDABE
+
-
„H“ = swi tches OFF
OUTn
0
0
1
0
1
x
t
FIL_ON
t
FIL_OFF
t
FIL_ON
t
FIL_OFF
t
ABE
CONREG4.
ABE_ IMPACT
t
FIL_OFF_DEL
MUX
Drawing19 _VDD_monitoring .vsd
ABE_STATUS
STATUS_UV
STATUS_OV
GNDABE
1
0
1
0
≥1
≥1
Power On
Reset
RST
TLE 8718 SA
Supply, VDD Monitoring, Reset and ABE
Data Sheet 47 Rev. 1.1, 2012-07-31
9.8 Electrical Characteristics
Table 20 Power Supply, POR, VDD Monitoring, ABE and RST
4.5V < VDD < 5.5V, 4.5V < VBAT < 40V, all voltages with respect to PGND, positive current flowing into pin.,
Tj = -40°C to +150°C, unless otherwise specified
Pos. Parameter Symbol Values Unit TC Conditions
min. typ. max.
Power Supply
9.8.1 Operational Supply Current IVDD –1825mAC4.5V<VDD<5.5V,
All channels ON or
OFF, nominal load
conditions
9.8.2 Overvoltage Supply Current IVDD_0V ––50mAC5.5V<VDD<36V,
no damage
Power ON Reset
9.8.3 Reset Circuit Functional, Internal
reset active for
VDD_RES<VDD<VDD_POR
All stages switched inactive and
internal registers are cleared.
VDD_RES ––2.5VB–
9.8.4 Power On Reset Threshold
Below this threshold the device is in
reset state, all registers are cleared.
Device starts operation (VDD
monitoring forces stages off) after
tPOR, when VDD is rising above this
threshold.
VDD_POR 3–3.5VB–
9.8.5 Power On Reset Extension Time tPOR 180 – 360 µs C –
VDD Monitoring
9.8.6 Undervoltage threshold, ABE turns
active low and stages are turned off
when VDD is below this threshold
VDD_THL 4.1 – 4.4 V B 1)
9.8.7 Overvoltage threshold, ABE turns
active low and stages are turned off
when VDD is above this threshold
VDD_THH 5.25 – 5.5 V B 1)
9.8.8 Filtering time before switching off,
VDD is rising above VDD_THH or falling
below VDD_THL all outputs except
OUT15, OUT16 if configured to
delayed reset
tFIL_OFF 60 – 135 µs C –
9.8.9 Filtering time with delay before
switching off if ABE is configured to
delayed switching of stages by
CONREG4, switching OFF
because of VDD Monitoring or
falling edge of ABE is de-bounced 2)
tFIL_OFF_DEL 30 – 80 ms C –
Data Sheet 48 Rev. 1.1, 2012-07-31
TLE 8718 SA
Supply, VDD Monitoring, Reset and ABE
9.8.10 Delayed Reset for OUT15 and
OUT16, if configuration bits are set
to delayed reset
tDELRES 400 – 800 ms C –
9.8.11 Filtering time before switching on,
returning to VDD_THL<VDD<VDD_THH
tFIL_ON 60 – 135 µs C –
9.8.12 Test VDD monitoring undervoltage,
VDD monitoring test active
VTEST_THL 5.15 – 5.6 V B 1)
9.8.13 Test VDD monitoring overvoltage,
VDD monitoring test active
VTEST_THH 4.1 – 4.5 V B 1)
ABE as Input
9.8.14 ABE input low level VABE_INL -0.3 – 0.3*VDD VB–
9.8.15 ABE input high level VABE_INH 0.7*VDD –36 VB–
9.8.16 ABE input hysteresis VABE_INHYS 0.2 – 1 V C –
9.8.17 ABE input current IABE_INL -100 – -20 µA A -0.2V<VABE<VDD–
1.5V3)
9.8.18 ABE input current IABE -400 – – µA C -0.3V<VABE3)
9.8.19 ABE input current IABE_INH -5 – 5 µA A VDD<VABE<36V
9.8.20 ABE pulse width, ABE requires min.
low level pulse width
tABE 0.5 – 3.5 µs C
ABE as Output
9.8.21 ABE output low voltage VABE_OUTL ––1VA2.5V<VDD<VDD_THL,
IABE<6.5mA
9.8.22 ABE output low voltage VABE_OUTL ––1VAVDD_THH<VDD<36V,
IABE<7mA
9.8.23 ABE output low voltage VABE_OUTL ––0.7VAVDD=2.5V,
IABE<2mA
9.8.24 Maximum current (short circuit
limited current)4)
IABE_max 15 – – mA C
9.8.25 ABE passive output high voltage VABE_OUTH VDD–1.5 VDD – V A no load
Table 20 Power Supply, POR, VDD Monitoring, ABE and RST
4.5V < VDD < 5.5V, 4.5V < VBAT < 40V, all voltages with respect to PGND, positive current flowing into pin.,
Tj = -40°C to +150°C, unless otherwise specified
Pos. Parameter Symbol Values Unit TC Conditions
min. typ. max.
TLE 8718 SA
Supply, VDD Monitoring, Reset and ABE
Data Sheet 49 Rev. 1.1, 2012-07-31
Pin RST
9.8.26 RST input low level VRST_L -0.3 – 1 V B
9.8.27 RST input high level VRST_H 2–36VB
9.8.28 RST input hysteresis VRST_HYS 0.1 – 0.5 V C
9.8.29 RST input current IRST -120 – 20 µA C -0.2V<VRST<VDD
9.8.30 RST input current IRST -10 – 1000 µA C VDD<VRST<36V
9.8.31 RST input current IRST -400 – – µA C -0.3V<VRST
9.8.32 RST pull-up current IRST -50 – -10 µA A 0V<VRST<VDD–1.5V
9.8.33 Reset pulse width, RST requires
min. low level pulse width
tRST 0.5 3.5 µs C
1) Referred to GNDABE
2) In case of undervoltage of VDD, specification is not fulfilled: e.g. proper operation of protection functions is not guaranteed
(OUT= 1...14,17,18).
3) ABE as Output is not active
4) Integrated protection functions are designed to prevent IC destruction under fault conditions. Fault conditions are
considered as “outside” normal operating range. Protection functions are not designed for continuous or repetitive
operation. Application must take care, that current into this pin does not exceed 15mA.
Table 20 Power Supply, POR, VDD Monitoring, ABE and RST
4.5V < VDD < 5.5V, 4.5V < VBAT < 40V, all voltages with respect to PGND, positive current flowing into pin.,
Tj = -40°C to +150°C, unless otherwise specified
Pos. Parameter Symbol Values Unit TC Conditions
min. typ. max.
Data Sheet 50 Rev. 1.1, 2012-07-31
TLE 8718 SA
Device Logic Behavior
10 Device Logic Behavior
Table 21 Device Logic Behavior
Registers Output Stages Others
DIAREG
CONREG
OUTREG
OUT1516
1...4,
11...14,
17, 18
5...10
15, 16
OUT1516
delay timer
MSC timeout
counter
ABE output
DELAYOUT
output
SDO output
MSC Communication
Dataframe – – data
entry
– ON/OFF
depending on
OUTREG
– – restart–––
RD_CONFIG – read
out
––– – – – ––send
data
RD_DATA read
out &
reset
–1) 1) 1) 1) – – ––send
data
WR_RST reset
2) –1) 1) 1) 1) – – –––
WR_CONREGx – data
entry
––– – – – –––
WR_OUT1516 – – – data
entry
– ON/OFF
depending on
OUT1516 3)
restart
3)
– –––
MON_TEST x data
entry
xxx x – – xx–
Input pins
DIS5_10 data
entry
–––– disable– – – –––
lower thresholds of
DELAYIN4)
data
entry
–––– – – – –pulled
low
–
higher thresholds of
DELAYIN5) data
entry
– – reset – reset – – – – –
RST reset reset reset reset
6) disable 7) disable 6) – restart pulled
low
pulled
low
disable
8)
ABE_STATUS data
entry
–resetreset
6) disable 7) disable 6) – – –––
Internally detected error cases
STATUS_UV,
STATUS_OV
data
entry
–resetreset
6) disable 7) disable 6) ––pulled
low
pulled
low
–
STATUS_SVBATT data
entry
disable disable – – – – –
POR reset reset reset reset disable restart restart
9) pulled
low
pulled
low
disable
8)
SCB data
entry
–––disable (defined in CONREGx
and OUT1516)
– – –––
OL data
entry
–––– – – – –––
SCG data
entry
–––– – – – –––
TLE 8718 SA
Device Logic Behavior
Data Sheet 51 Rev. 1.1, 2012-07-31
OTW data
entry
–––– – – – –––
OTSD 10) –––disable disable – – –––
REVCUR_FLAG data
entry
–––– – – – –––
Timeout counter expired
MSC timeout
counter
data
entry
–resetreset
6) disable7) disable 6) – expired–––
OUT1516 delay
timer
–––reset
11) – disable 6)11) expired– –––
1) Outputs which have been switched off by SCB are switched on until SCB is detected again
2) Only DIAREG1...5 are reset, DIAREG6 and DIAREG7 remain unchanged
3) Switching on respectively restarting delay timer only in failure free condition
4) Thresholds VDELAYIN_L and VDELAYIN_H
5) Thresholds VDELAYIN_RES15_16_L and VDELAYIN_RES15_16_H
6) OUT1516 reset and stages are disabled after delay time (OUT15, OUT16 may be configured to long delay)
7) OUTREG reset and stages are disabled because control register is reset
8) communication stopped
9) before tMSC_mon a data frame must be received, otherwise DIAREG6 must be read out to clear MSC_MON failure bit.
10) OTW still active in OTSD, no new diagnostic entry when changing from OTW to OTSD
11) Only if this timer has expired and failure occurs
Description:
– : no influence
x : influence possible, refer to corresponding chapter in this specification
Table 21 Device Logic Behavior
Registers Output Stages Others
Data Sheet 52 Rev. 1.1, 2012-07-31
TLE 8718 SA
Micro Second Channel MSC
11 Micro Second Channel MSC
Bidirectional micro second channel (MSC) is used for communication with micro controller.
Via MSC, the micro controller controls the outputs and logic of the stage device including the diagnosis and
monitoring module. Diagnosis data is requested by micro controller via downstream and returned by the device
via MSC upstream channel.
The MSC is a serial interface which is especially optimized to connect peripheral devices via serial link to micro
controller. The serial communication link is built up by a fast synchronous downstream channel from micro
controller to the stage device and an asynchronous upstream channel (referenced to downstream clock). The
downstream interface can be “low voltage differential” (FCLN, FCLP, SIN, SIP) or “single ended” (FCL, SI, SSY).
Multiple “power devices” with MSC on downstream are possible. Downstream device is selected by SSY.
The MSC logic is supplied with VDD and referenced to PGND.
If supply voltage of the device is below VDD_THL, downstream communication is possible with reduced FCL clock
frequency only. Power on reset (VDD<VDD_POR) disables the MSC interface.
Figure 17 MSC Interface (not tested, overview only)
MSC interface
Asynchronous/
synchronous
receive buffer
Micro controller TLE8718SA
Downstream
Shift register
32 Bit
Select / sync input
Clock
input
Serial data
output
FCL
FCLP
FCLN
Downstream
data
Drawing 9_MSC_Interface .vsd
SI
SIP
SIN
Differential
Single
ended
Differential
Single
ended
SSY
SDO
TLE 8718 SA
Micro Second Channel MSC
Data Sheet 53 Rev. 1.1, 2012-07-31
11.1 Downstream Communication
Downstream frames are synchronous serial frames with clock and data line.
The physical interface for downstream communication can be “low voltage differential” or “single ended” type. Both
interface types are using individual pins (FCL and SI or FCLN, FCLP, SIN and SIP) and common pins (SSY and
SO). To select the interface, FLCN has to be connected either to PGND (for single ended type) or to a voltage
within the defined input voltage range (for low voltage differential type) (see Item 11.5.7). The unused pins are
connected to PGND (FCLN, FCLP, FCL, SIP, SIN) or to VDD (SI).
Differential inputs for downstream data are SIP and SIN; the differential input signal SIP – SIN is the same logical
signal as SI. The clock pins are FCLP and FCLN, the differential clock FCLP – FCLN is the same logical signal as
FCL.
There is one input for select/sync at SSY, and one output for upstream data at SDO. The stage device is always
the slave in this communication link.
The SSY signal enables receiver circuits automatically during a downstream frame transmission.
Two types of downstream frames are defined:
• Command frames (selection bit =“1”)
• Data frames (selection bit =“0”)
The device MSC uses non inverting polarity for SI and FCL: SI changes its state with the rising edge of FCL and
is sampled with the falling edge; a logic ‘1’ is a ‘high level’ on SI, and a logic ‘0’ is a ‘low level’ on SI. Data at SI is
latched by device on the falling edge of FCL.
The SSY input is active low during the active phases of command or data frames. An active enable signal validates
the SI input signal. Outside the active phase (SSY line is at high level) data at SI is ignored.
By this way it is possible to drive multiple “power devices” with shared FCL and SI lines and individual SSY signal.
Command frames and data frames may be sent in any sequence (with a passive phase of at least 2 FCL-cycles
after each frame).
The serial clock FCL is active (toggling) continuously (“FCL continuous mode”) even when no command frame or
data frame is transmitted. It is used to generate the upstream clock.
The clock period of FCL is defined as tFCL, maximum downstream clock rate is fFCLmax.
The active phase of a downstream frame starts with the falling edge of the signal on SSY and ends with the rising
edge. SSY changes its state with the rising edge of clock FCL.
After a power-on-reset or RST returns to logical high level for device normal operation, the MSC interface is fully
functional after a maximum of 8 clock pulses on FCL respectively FCLP and FCLN.
Table 22 Execution of commands
Event on MSC downstream upstream busy upstream idle
valid read command frame ignored executed
valid write command frame executed executed
valid data frame accepted accepted
invalid command frame ignored ignored
invalid data frame ignored ignored
Data Sheet 54 Rev. 1.1, 2012-07-31
TLE 8718 SA
Micro Second Channel MSC
11.1.1 Voltage Level Diagrams of low voltage differential pins
Figure 18 Voltage level diagram
11.1.2 Downstream Supervisory Functions
A command- or data frame is interpreted as valid, if it has the correct number of clock pulses (a frame has a length
of 17 clock pulses). Clock pulses are counted at the falling edge of the signal.
There is no parity check.
If device receives no valid data frame for t > tMSC_mon, the device will switch off the output stages (exception: OUT15
or OUT16 if configured to delayed reset behavior and set the bit MSC_MON in DIAREG6 to ‘0’.
11.1.3 Command Frame
A command frame always starts with a high level bit (command selection bit). The number of bits of the active
phase of a command frame NCB is fixed to 17. A command is executed only if the number of the command bits
is equal to NCB = 17.
The length of the command frame’s passive phase tCPP must be a minimum of 2 * tFCL (2 clock pulses).
Alternatively the passive phase can consist in tCPP = tFCL (1 clock pulse) followed by a frame of wrong length (4...8
bits, with or without SSY active low) and a second tCPP = tFCL (1 clock pulse).
Drawing10_Voltage _level_diagram. vsd
This figure shows SIP and SIN function but is also valid for FCLP and FCLN
SIP
SIN
V
SIN(min)
, V
SIP(min)
V
SIN(max)
, V
SIP(max)
Not defined
Not defined
V
SIx_low(min)
V
SIx_low(max)
Logic function
101
V
SIN(min)
, V
SIP(min)
V
SIN(max)
, V
SIP(max)
V
SINx _off(max )
V
SINx_off(min)
SIP
SIN
101 101 101 101 XXX XXX
t [s]
V
SIN
, V
SIP
[V]
t [s]
t [s]
t [s]
V
SIN
, V
SIP
[V]
Logic function
V
SIx_high(min)
V
SIx_high(max)
TLE 8718 SA
Micro Second Channel MSC
Data Sheet 55 Rev. 1.1, 2012-07-31
Figure 19 MSC command frame
Content of a command frame (LSB transmitted first)
The least significant (LSB) bit of a command is transmitted first.
11.1.4 Data Frame
A data frame always starts with a low level bit (data selection bit). The number of the bits of the active phase of a
data frame NDB is fixed to 17 bit.
A data frame is accepted if the actual length is the expected length NDB.
MSC Monitoring tMSC_mon is re-triggered by any data frame with correct length (no other error detection mechanism
is implemented).
The length of the data frame’s passive phase tDPP must be a minimum of 2 * tFCL (2 clock pulses).
Alternatively the passive phase can consist in tDPP = tFCL (1 clock pulse) followed by a frame of wrong length (4...8
bits, with or without SSY active low) and a second tDPP = tFCL (1 clock pulse).
Table 23 Command frame
Bit # Description
0 (first bit) = ‘1’: command selection bit
1...5 Command [C0...C4]
6...13 Data for the command [CD0...CD7]
14...16 don’t care 3 bits
1
invalid command bits
C0 ... C4 command data bits
CD0 ... CD7 invalid
shift sample t
FCL
SSY
SI
FCL
active
selection bit (1=command)
active phase
Command frame
passive
phase
t
CPP
don 't
care
Drawing11_MSC_ command_frame.vsd
Data Sheet 56 Rev. 1.1, 2012-07-31
TLE 8718 SA
Micro Second Channel MSC
Figure 20 MSC data frame
There is no parity bit in the data frame.
The stages OUT15 and OUT16 are accessed by command frame (WR_OUT1516) due to their optional special
functions (delayed reset behavior on ABE, RST, ...).
The data is stored in register OUTREG.
Table 24 Data frame
OUTREG Bit Description
0 (first bit) = ‘0’: data selection bit (R-A 1.5.3)
1 OUT1 stage data1)
1) The control bit is non inverting, i.e. if a control bit is ‘1’ the corresponding stage is off.
2 OUT3 stage data1)
3 OUT5 stage data1)
4 OUT7 stage data1)
5 OUT9 stage data1)
6 OUT11 stage data1)
7 OUT13 stage data1)
8 OUT17 stage data1)
9 OUT2 stage data1)
10 OUT4 stage data1)
11 OUT6 stage data1)
12 OUT8 stage data1)
13 OUT10 stage data1)
14 OUT12 stage data1)
15 OUT14 stage data1)
16 OUT18 stage data1)
0
invalid OUTREG data bits 1 ... 16 invalid
shift sample t
FCL
SSY
SI
FCL
active
selection bit (0=data)
active phase
data frame
t
DPP
Drawing12_MSC_data_frame.vsd
passive
phase
TLE 8718 SA
Micro Second Channel MSC
Data Sheet 57 Rev. 1.1, 2012-07-31
11.2 Upstream Communication
The serial data output [SDO] is the synchronous serial data signal of the upstream channel.
The polarity for [SDO] is ‘non inverting polarity‘– i.e. a low level bit at [SDO] is stored in the micro controller as a
logic ‘0‘, and a high level bit at [SDO] is stored in the micro controller as a logic ‘1‘.
Figure 21 MSC upstream communication (not tested, overview only, Single Ended)
The serial data output (SDO) is single-ended.
The frequency for SDO is derived from FCL (or FCLN/FCLP) by an internal divider and can be configured via MSC.
Figure 22 MSC upstream frame
Transmission of the registers via upstream starts within tMSC_RSP after read command has been received. If a read
command is received the device will ignore further read commands until the upstream data transfer is finished. A
new read command is accepted if the rising edge SSY arrives after the last stop bit has been sent. Write
commands or data frames are executed independently of ongoing read requests. If the write command is changing
the register which is in transmission, the old register content will be sent (see Figure 22).
Table 25 Upstream frame
Bit description
0 start bit, always ‘0’
1-8 upstream data bits UD0...7
9 parity bit (The parity bit is set in order to achieve an even number of ‘1’ in Bits
UD0...7+Parity)
10, 11, 12 stop bits, always ‘1’
Downstream
Channel
Divider
Upstream
Channel
Divider
Shift
Control
TLE8718SA
SO
FCL
SDOSI
Micro controller
FCL
SI
Drawing13 _ MSC upstream communication .vsd
Drawing14 _M SC upstream frame . vsd
SSY
SO
f
SDO
8 bit data field
t
MSC_RSP
Read request for 1 register
read requests are ignored during a running upstream ,
write requests and data frames are executed
t
MSC_RSP
13 bit upstream data frame
Start
bit
UD0
LSB UD1 UD2 UD3 UD4 UD5 UD6 UD7
MSBParityStop
bit
Stop
bit
Stop
bit
Start
bit
UD0
LSB UD1 UD2 UD3 UD4 UD5 UD6 UD7
MSBParity Stop
bit
Stop
bit
Stop
bit
13 bit upstream data frame
Read request for 2 registers
13 bit upstream data frame
Start
bit
UD0
LSB UD1 UD2 UD3 UD4 UD5 UD6 UD7
MSBParity Stop
bit
Stop
bit
Stop
bit
During tMSC_RSP all requested registers are copied into a shadow register from where
they are upstreamed via SDO.
Requested diagnostic registers are deleted after they are copied to the shadow register.
Data Sheet 58 Rev. 1.1, 2012-07-31
TLE 8718 SA
Micro Second Channel MSC
11.3 Timing Characteristics
Figure 23 MSC timing
The downstream clock within the device is always running; each upstream data frame (i.e. each answer to a READ
command) is synchronized with this clock.
The upstream response time tMSC_RSP describes the time between end of read command (rising edge of SSY) to
beginning of up-stream communication (falling edge of start bit).
11.4 Internal Clock Signal
The MSC interface is synchronously clocked by the external MSC clock signal (FCL or FCLN/FCLP). If this clock
signal is missing the communication is halted.
All other functions of the circuit are available independently of an external MSC clock signal FCL or FCLN/FCLP.
The internal clock source is used for:
• Diagnosis filtering
• Self protection
• Reset extension
• MSC data stream supervisory
• Delayed reset behavior of OUT15 and OUT16
• Delayed disabling inputs (DIS5_10, DELAYIN)
The internal clock signal is generated independently from MSC clock (FCL or FCLN/FCLP).
The internal oscillator is functional in undervoltage VDD_THL above VDD_POR. By this way it is guaranteed that in
undervoltage condition or during micro controller reset the diagnostic filters (e.g. stage shut off on SCB) and the
delayed reset of OUT15 and OUT16 are functional.
SSY
FCL
SI
t
switch
t
setup
t
hold
t
SSYhold
1/f
FCL
t
SSYsetup
SDO
//
//
t
MSC_RSP
Drawing16 _MSC_timing.vsd
TLE 8718 SA
Micro Second Channel MSC
Data Sheet 59 Rev. 1.1, 2012-07-31
11.5 Electrical Characteristics
Table 26 Micro Second Channel
4.5V < VDD < 5.5V, 4.5V < VBAT < 40V, all voltages with respect to PGND, positive current flowing into pin.,
Tj = -40°C to +150°C, unless otherwise specified
Pos. Parameter Symbol Values Unit TC Conditions
min. typ. max.
Internal Clock
11.5.1 Frequency of internal clock fINT 0.7 – 1.1 MHz C -
Pin SSY
11.5.2 Input comparator low level VSSY_low -0.3 – 0.8 V B –
11.5.3 Input comparator high level VSSY_high 1.6 – 36 V B –
11.5.4 Input comparator hysteresis VSSY_hys 0.1 – 0.5 V C –
11.5.5 Input capacitance CSSY – – 10 pF C –
11.5.6 Input current
Internal pull up current source to VDD
ISSY -100 – -10 µA A 0V<VSSY<2V
Pins FCLP, FCLN
11.5.7 Input voltage range VFCLP,
VFCLN
0.8 – 1.6 V C –
11.5.8 Differential input high detection level,
VFCLx_high=VFCLP–VFCLN
VFCLx_high 25 – 125 mV C –
11.5.9 Differential input low detection level,
VFCLx_low=VFCLP–VFCLN
VFCLx_low -125 – -25 mV C –
11.5.10 Input voltage offset,
VFCLx_off=0.5*(VFCLP+VFCLN)
VFCLx_off 1.05 – 1.4 V C –
11.5.11 Differential capacitance between; FCLP
and FCLN
CFCLx ––8pFC–
11.5.12 FCLP Input pull up current; FCLP:
internal pull up current source;
IFCLP -25 – -3 µA A 0V<VFCLP<2V
11.5.13 FCLN Input pull down current; FCLN:
internal pull down current source
IFCLN 6–50µAA1V<VFCLN<VDD
Single ended/Differential selection
11.5.14 FCLN low level for MSC “single ended
selection”
VFCLN_sel_l
ow
-0.3 – 0.4 V B –
11.5.15 FCLN high level for MSC “low voltage
differential selection”
VFCLN_sel_h
igh
0.8 – 36 V B –
Pin FCL
11.5.16 FCL input low voltage VFCL_low -0.3 – 0.8 V B –
11.5.17 FCL input high voltage VFCL_high 1.6 – 36 V B –
11.5.18 FCL input hysteresis VFCL_hys 0.1 – 0.5 V C –
11.5.19 FCL Input current. Internal pull down
current source to PGND;
IFCL 10 – 100 µA A 1V<VFCL<VDD
Clock Frequency
11.5.20 FCLP, FCLN frequency fFCLx 4–23MHzBVDD_POR<VDD<
5.5V
Data Sheet 60 Rev. 1.1, 2012-07-31
TLE 8718 SA
Micro Second Channel MSC
11.5.21 FCL frequency fFCL 4–12.5MHzBVDD_POR<VDD<
5.5V
Pins SIP, SIN
11.5.22 Input voltage range VSIP, VSIN 0.8 – 1.6 V C –
11.5.23 Differential input high detection level,
VSIx_high=VSIP–VNSI
VSIx_high 25 – 125 mV C –
11.5.24 Differential input low detection level,
VSIx_low=VSIP–VSIN
VSIx_low -125 – -25 mV C –
11.5.25 Input voltage offset,
VSIx_Off=0.5*(VSIP+VSIN)
VSIx_Off 1.05 – 1.4 V C –
11.5.26 Differential capacitance between SIP
and SIN
CSIx ––8pFC–
11.5.27 Input pull up current; SIP: internal pull up
current source
ISIP -25 – -3 µA A 0V<VSIP<2V
11.5.28 Input pull down current; SIN: internal pull
down current source to PGND
ISIN 6–50µAA1V<VSIN<VDD
Pin SI
11.5.29 SI input low voltage VSI_low -0.3 – 0.8 V B –
11.5.30 SI input high voltage VSI_high 1.6 – 36 V B –
11.5.31 SI input hysteresis VSI_hys 0.1 – 0.5 V C –
11.5.32 SI Input current; Internal pull up current
source to VDD
ISI -100 – -10 µA A 0V<VSI<2V
Pin SDO
11.5.33 SDO output low level VSDO_low;
VSDO_low
––0.8VCISDO<4mA;
––0.4VA
ISDO<1mA
11.5.34 SDO passive output high voltage VSDO_high VDD –
1.5
VDD –VCno load
11.5.35 Maximum current (short circuit limited
current)1)
ISDO_max 15 –– mAC–
11.5.36 SDO pull-up current source ISDO_high -50 – -10 µA A 0V<VSDO<2V,
2)
11.5.37 SDO (high level = inactive) pin capacity CSDO – – 10 pF C measured with
bias voltage of
1V
11.5.38 SDO frequency; maximum upstream
frequency with external pull-up
fSDO 550 – – kHz C 1kΩ and
CL=50pF
Table 26 Micro Second Channel
4.5V < VDD < 5.5V, 4.5V < VBAT < 40V, all voltages with respect to PGND, positive current flowing into pin.,
Tj = -40°C to +150°C, unless otherwise specified
Pos. Parameter Symbol Values Unit TC Conditions
min. typ. max.
TLE 8718 SA
Micro Second Channel MSC
Data Sheet 61 Rev. 1.1, 2012-07-31
Timing Characteristics 3)
11.5.39 Data hold time thold 10 – – ns C –
11.5.40 Data Setup time tsetup 10 – – ns C –
11.5.41 Switching time tswitch ––3nsC–
11.5.42 FCL low time tFCLlow 13 – – ns C –
11.5.43 FCL high time tFCLhigh 13 – – ns C –
11.5.44 SSY setup time tSSYsetup 5––nsC–
11.5.45 SSY hold time tSSYhold 17 – – ns C –
11.5.46 MSC data timeout monitoring tMSC_mon 60 – 135 µs B –
11.5.47 MSC upstream response time; up-
stream divider independent
(CONREG4_FCL_CONFx)
tMSC_RSP ––100µsCfFCL or
fFCLx=4MHz
11.5.48 Required idle time after command tCPP 2/fFCL
(2 clock
pulses)
–– s C–
11.5.49 Required idle time after data frame tDPP 2/fFCL
(2 clock
pulses)
–– s C–
1) Integrated protection functions are designed to prevent IC destruction under fault conditions. Fault conditions are
considered as “outside” normal operating range. Protection functions are not designed for continuous or repetitive
operation. Application must take care, that current into this pin does not exceed 15mA.
2) SDO as Output is not active
3) See Figure 19, Figure 20 and Figure 23.
Table 26 Micro Second Channel
4.5V < VDD < 5.5V, 4.5V < VBAT < 40V, all voltages with respect to PGND, positive current flowing into pin.,
Tj = -40°C to +150°C, unless otherwise specified
Pos. Parameter Symbol Values Unit TC Conditions
min. typ. max.
Data Sheet 62 Rev. 1.1, 2012-07-31
TLE 8718 SA
Control of the device
12 Control of the device
12.1 Commands
Table 27 Command Overview
Command SB C0...4 CD0...7 DC Description
– 1 00000 xxxx xxxx xxx Invalid command
WR_CONREG1 1 10000 CD0...7 xxx Configuration of switch off or current control by SCB for
OUT1...8
WR_CONREG2 1 01000 CD0...7 xxx Configuration of switch off or current control by SCB for
OUT9...14, 17, 18
– 1 11000 xxxx xxxx xxx Invalid command
WR_CONREG3 1 00100 CD0...7 xxx Configuration of diagnostic pull-down current and Open
Load OL of OUT11...14, 17, 18, DELAYIN_FIL and
EXT_SCB
– 1 10100 xxxx xxxx xxx Invalid command
– 1 01100 xxxx xxxx xxx Invalid command
WR_OUT1516 1 11100 CD0...7 xxx Configuration of OUT 15, 16, switch off or current control by
SCB for OUT15, 16, configuration of diagnostic pull-down
current and Open Load OL. Special behavior (time delay)
WR_RST 1 00010 xxxx xxxx xxx Soft reset via MSC (clear diagnostic registers)
– 1 10010 xxxx xxxx xxx Invalid command
– 1 01010 xxxx xxxx xxx Invalid command
WR_START 1 11010 xxxx xxxx xxx Enable OUT1...14, OUT17 and OUT18
– 1 00110 xxxx xxxx xxx Invalid command
WR_CONREG4 1 10110 CD0...7 xxx Configuration of DELAYIN delay, upstream frequency
divider and VDD monitoring
WR_TESTREG 1 01110 CD0...7 xxx For factory tests only. Do not use this command.
– 1 11110 xxxx xxxx xxx Invalid command
RD_CONFIG 1 00001 CD0...7 xxx Request content of configuration registers CONREG1...4,
OUT1516, TESTREG
– 1 10001 xxxx xxxx xxx Invalid command
– 1 01001 xxxx xxxx xxx Invalid command
RD_DATA 1 11001 CD0...7 xxx Request content of diagnostic registers DIAREG1...7 and
IDENTREG
– 1 00101 xxxx xxxx xxx Invalid command
– 1 10101 xxxx xxxx xxx Invalid command
– 1 01101 xxxx xxxx xxx Invalid command
– 1 11101 xxxx xxxx xxx Invalid command
– 1 00011 xxxx xxxx xxx Invalid command
– 1 10011 xxxx xxxx xxx Invalid command
WR_FUSE_SC 1 01011 CD0...7 xxx Active during factory test mode only. For factory tests only.
Do not use this command.
– 1 11011 xxxx xxxx xxx Invalid command
TLE 8718 SA
Control of the device
Data Sheet 63 Rev. 1.1, 2012-07-31
12.1.1 WR_OUT1516
Figure 24 OUT1516 after Power ON (POR) and in dependency of tMSC_MON
WR_SEL_THRES 1 00111 CD0...7 xxx Active during factory test mode only. For factory tests only.
Do not use this command.
– 1 10111 xxxx xxxx xxx Invalid command
– 1 01111 xxxx xxxx xxx Invalid command
– 1 11111 xxxx xxxx xxx Invalid command
Table 28 Command WR_OUT1516
SB C CD0 CD1 CD2 CD3 CD4 CD5 CD6 CD7 DC
1 11100 OUT15_C
ONTROL
OUT15_
DELAY
OUT15_
DIAC
OUT15_
SCB
OUT16_C
ONTROL
OUT16_
DELAY
OUT16_
DIAC
OUT16_
SCB
xxx
Table 27 Command Overview
Command SB C0...4 CD0...7 DC Description
WR_OUT1516 _after _POR .vsd
COMMAND- or
DATA Frame
(correct length )
POR
DATA
t
MSC _MON
timer is re-triggered
in-time
t
MSC _MON
timer is
not re -triggered
t
MSC_MON
DATA CMD*
*: CMD WR_OUT1516
.CD0 or.CD4 = ON
valid
OUT15 or 16
(standard switch-off)
OUT15 or 16
(delayed switch-off)
DATA DATA
t
DELRES
DIAREG6.
MSC_MON
POR, RST or
read DIAREG 6 re-sets
DIAREG6.MSC_MON
CMD* DATA CMD*
*: CMD W R_OUT1516
.CD0 or.CD4 = ON
not valid because
DIAREG 6.MSC_MON
not set
*: CMD
WR_OUT1516
.CD0 or.CD4 = ON
valid
OFF ON
OFF ON
DATA DATA
CMD does not
re-trigger
t
MSC_MON
Data Sheet 64 Rev. 1.1, 2012-07-31
TLE 8718 SA
Control of the device
The MSC timeout counter is started from its initial state when POR and RST are released. The diagnosis flag
DIAREG6.MSC_MON is initially set to ‘1’. Every valid data frame resets and restarts the MSC timeout counter as
long as it has not expired. Hence data frames should be sent in intervals shorter than tMSC_mon.
If no valid data frame is received within tMSC_mon, the MSC timeout counter will expire, clear the
DIAREG6.MSC_MON flag and switch off the output stages. An exception may be OUT15/16 which are switched
off after tDELRES if they are configured to delayed reset behavior. All other functions are not influenced by the MSC
timeout, e.g. MSC upstream data transfer is not halted.
Once the MSC timeout counter has expired a data frame will neither restart the timeout counter nor set the
diagnosis flag nor turn on any output. In order to enable the output stages again after an MSC timeout the following
steps are necessary:
1) DIAREG6 must be read to set the DIAREG6.MSC_MON bit and restart the MSC timeout counter.
2) Subsequent data frames or WR_OUT1516 commands are needed to switch on the outputs again.
Command frames other than RD_DATA for DIAREG6 will neither influence the MSC timeout counter nor the
DIAREG6.MSC_MON flag.
The WR_OUT1516 output is a ‘high’-strobe after the command has been received. (See Figure 1)
The tDELRES time-out counter generates a ‘low’ pulse of tDELRES after the ‘Restart’ input has been activated by ‘high’
pulse. A ‘high’ pulse on input ‘Discard’ makes the timer expire without waiting for tDELRES, the output then is ‘high’-
level (failure will reset OUTn control register).
The inputs of the OUTn-control flip-flop are active high and ‘R’ is dominant, output is non inverting.
OUT15 and OUT16 can be configured individually to delayed reset, only one timer (tDELRES) is needed as both
outputs are accessed in the same command frame and no independent restart is possible.
The functions are:
•switch OFF
• switch ON, no delay
• switch ON, restart timeout counter for delayed reset behavior
• keep state, restart timeout counter for delayed reset behavior
12.1.2 WR_RST
The command triggers a soft reset via MSC. Diagnostic registers are cleared.
If WR_RST command arrives during an up-stream burst, then all diagnostic registers are cleared. The incoming
frame is sent with the uncleared content of the DIAREG and the rest of the frames are send with the cleared
content.
12.1.3 WR_START
Table 29 Command WR_RST
SB C0...4 CD0...7 DC
1 00010 xxxx xxxx xxx
Table 30 Command WR_START
SB C0...4 CD0...7 DC
1 11010 xxxx xxxx xxx
TLE 8718 SA
Control of the device
Data Sheet 65 Rev. 1.1, 2012-07-31
The command clears the bit OUTPUT_STBY = ’0’. With OUTPUT_STBY =’1’ the output registers OUTREG of
OUT1...14, 17, 18 are reset. Control of OUT15 and 16 is still possible by register OUT1516. The OUTPUT_STBY
bit is set by power-on-reset or by active low signal on pin RST.
Figure 25 Impact of WR_START to OUTPUT_STBY
WR_START_OUTPUT_DTB.vsd
COMMAND- or
DATA Frame
(correct length )
POR or RST
DATA*
t
MSC _MON
tim er is re-triggered
in-time
t
MSC _MON
timer is
not re-triggered
t
MSC_MON
CMD** DATA DATA
DIAREG6.
MSC_MON
*** CMD
Read DIAREG 6 re-sets
DIAREG6.MSC_MON
DATA DATA
DATA DATA CMD***
DIAREG6.
OUTPUT_STBY
** CMD WR_START
re-sets DIAREG6.
OUTPUT_STBY
OFF
ON or OFF
dependent on
content of DATA
* DATA does not influence
OUTn until
WR_START has been send
OFF
OUT1...14, 17, 18
COMMAND- or
DATA Frame
(correct length )
POR or RST
DATA*
t
MSC _MON
tim er is re-triggered
in-time
t
MSC _MON
timer is
not re-triggered
t
MSC_MON
CMD** DATA DATA
DIAREG6.
MSC_MON
POR or RST re -sets
DIAREG6.MSC_MON
DATA DATA DATA
DATA DATA CMD**
DIAREG6.
OUTPUT_STBY
** CMD WR_START
re-sets DIAREG6.
OUTPUT_STBY
OFF
ON or OFF
dependent on
content of DATA
* DATA does not influence
OUTn until
WR_START has been send
OFF
OUT1...14, 17, 18
OUTPUT_STBY activated
OUTPUT_STBY de-activated
CMD**
** CMD WR_START
has no influence
CMD does not
re-tr igger
t
MSC _MON
CMD does not
re-tr igger
t
MSC _MON
Data Sheet 66 Rev. 1.1, 2012-07-31
TLE 8718 SA
Control of the device
12.1.4 RD_CONFIG
The RD_CONFIG command requests the device to transmit configuration register content via MSC upstream.
With the command data bit CD(0...7), it is masked which registers are to be transmitted.
If more than one register is requested the transmission is made from CD7 down to CD0 (upstream transmission
of CONREG1 first, CONREG2 second and so on). The request for a not implemented register is ignored.
12.1.5 RD_DATA
The RD_DATA command requests the device to transmit diagnostic register content via MSC upstream. With the
command data bit CD(0...7), it is masked which registers are to be transmitted.
If more than one register is requested the transmission is made from CD7 down to CD0 (upstream transmission
of DIAREG1 first, IDENTREG last).
The Register which is sent on RD_DATA is deleted at the beginning of the transmission.
Table 31 Command RD_CONFIG
Register SB C0...4 CD0...7 DC
CONREG1 1 00001 xxxx xxx1 xxx
CONREG2 xxxx xx1x
CONREG3 xxxx x1xx
CONREG4 xxxx 1xxx
OUT1516 xxx1 xxxx
not implemented xx1x xxxx
OUTREG_EVEN x1xx xxxx
OUTREG_ODD 1xxx xxxx
Table 32 Command RD_DATA
Register SB C0...4 CD0...7 DC
DIAREG1 1 11001 xxxx xxx1 xxx
DIAREG2 xxxx xx1x
DIAREG3 xxxx x1xx
DIAREG4 xxxx 1xxx
DIAREG5 xxx1 xxxx
DIAREG6 xx1x xxxx
DIAREG7 x1xx xxxx
IDENTREG 1xxx xxxx
TLE 8718 SA
Control of the device
Data Sheet 67 Rev. 1.1, 2012-07-31
12.2 Registers
12.2.1 CONREG1
12.2.2 CONREG2
Table 33 CONREG1
Reset sources: RST, power-on-reset
Controller read access: RD_CONFIG = ’1 00001xxxx xxx1 xxx’
Controller write access: WR_CONREG1 = ’1 10000 CD0...CD7 xxx’
UD/CD Name Description Reset value
0 OUT1_SCB ‘1‘: OUTn is switched off in case of SCB
‘0‘: OUTn current limited mode in case of SCB
1
1OUT2_SCB 1
2OUT3_SCB 1
3OUT4_SCB 1
4OUT5_SCB 1
5OUT6_SCB 1
6OUT7_SCB 1
7OUT8_SCB 1
Table 34 CONREG2
Reset sources: RST, power-on-reset
Controller read access: RD_CONFIG = ’1 00001 xxxx xx1x xxx’
Controller write access: WR_CONREG2 = ’1 01000 CD0...CD7 xxx’
UD/CD Name Description Reset value
0 OUT9_SCB ‘1‘: OUTn is switched off in case of SCB
‘0‘: OUTn current limited mode in case of SCB
1
1 OUT10_SCB 1
2 OUT11_SCB 1
3 OUT12_SCB 1
4 OUT13_SCB 1
5 OUT14_SCB 1
6 OUT17_SCB 1
7 OUT18_SCB 1
Data Sheet 68 Rev. 1.1, 2012-07-31
TLE 8718 SA
Control of the device
12.2.3 CONREG3
12.2.4 CONREG4
Table 35 CONREG3
Reset sources: RST, power-on-reset
Controller read access: RD_CONFIG = ’1 00001 xxxx x1xx xxx’
Controller write access: WR_CONREG3 = ’1 00100 CD0...CD7 xxx’
UD/CD Name Description Reset value
0 OUT11_DIAC ‘1‘: OUTn diagnostic pull-down current and Open Load OL on
‘0‘: OUTn diagnostic pull-down current and Open Load OL off
0
1 OUT12_DIAC 0
2 OUT13_DIAC 0
3 OUT14_DIAC 0
4 OUT17_DIAC 0
5 OUT18_DIAC 0
6 DELAYIN_FIL ‘1‘: Long filter time for tDELAYIN_GLITCH_long selected
‘0‘: Short filter time for tDELAYIN_GLITCH_short selected
1
7 EXT_SCB ‘1‘: Extended SCB behavior of OUT5...OUT14 active (IOUTn and VOUTn
are taken into account)
‘0‘: Default SCB behavior (only IOUTn is taken into account)
0
Table 36 CONREG4
Reset sources: RST, power-on-reset
Controller read access: RD_CONFIG = ’1 00001 xxxx 1xxx xxx’
Controller write access: WR_CONREG4 = ’1 10110 CD0...CD7 xxx’
UD/CD Name Description Reset value
0 DELAYIN_CONF0 See table below: configuration of DELAYIN delay 1
1 DELAYIN_CONF1 See table below: configuration of DELAYIN delay 1
2 FCL_CONF0 See table below: divider settings for upstream frequency 1
3 FCL_CONF1 See table below: divider settings for upstream frequency 0
4 ABE_IMPACT1)
1)In case of undervoltage of VDD, specification is not fulfilled: e.g. protection functions might not work. (OUT= 1...14,17,18)
1: ABE and VDD monitoring disables all Outputs with short delay
0: ABE and VDD monitoring disables all Outputs with long delay
1
5 MON_TEST ‘1‘: VDD monitoring test inactive
‘0‘: VDD monitoring test active
1
6 MON_THRES ‘1‘: Test undervoltage threshold
‘0‘: Test overvoltage threshold
1
7 MON_LATCH ‘1‘: Overvoltage failure will be latched. Normal operation after
reset, POR or by setting this bit to ‘0’
‘0‘: Device returns to normal operation after overvoltage
1
TLE 8718 SA
Control of the device
Data Sheet 69 Rev. 1.1, 2012-07-31
12.2.5 OUT1516
Table 37 CONREG4, DELAYIN configuration
Configuration of tDELAYIN_x delay
DELAYIN_CONF1 DELAYIN_CONF0 Description
1 1 Long delay tDELAYIN_L, see Item 7.0.16
0 1 Medium long delay tDELAYIN_ML, see Item 7.0.17
1 0 Medium short delay tDELAYIN_MS, see Item 7.0.18
0 0 Short delay tDELAYIN_S, see Item 7.0.19
Table 38 CONREG4, Upstream divider configuration1)
1) Take care that Item 11.5.38 fSDO is not exceeded.
Configuration of upstream clock divider
FCL_CONF1 FCL_CONF0 Description
1 0 Upstream clock is fFCL/128
0 1 Upstream clock is fFCL/64
0 0 Upstream clock is fFCL/32
1 1 Upstream clock is fFCL/16
Table 39 OUT1516
Reset sources: RST, power-on-reset, ABE, over-/undervoltage, OUT1516 timeout 1), MSC_MON, RES15_16
1) Timeout tdelres only resets the register if another failure (RST, ABE, over-/undervoltage, MSC-timeout) is still present. POR
and the filtered RES15_16 resets the register immediately.
Controller read access: RD_CONFIG = ’1 00001 xxx1 xxxx xxx’
Controller write access: WR_ OUT1516 = ’1 11100 CD0...CD7 xxx’
UD/CD Name Description Reset value
0 OUT15_CONTROL See table “Output stage switching” below 12)
2) After POR has occurred or RES15_16 is released OUT15, OUT16 starts in OFF- state. OUTn_DELAY, OUTn_CONTROL
reset Values remain =’1’
1 OUT15_DELAY See table “Output stage switching” below 12)
2 OUT15_DIAC ‘1‘:OUT15 diagnostic pull-down current and Open Load OL on
‘0‘:OUT15 diagnostic pull-down current and Open Load OL off
0
3 OUT15_ SCB ‘1‘: OUT15 is switched off in case of SCB
‘0‘: OUT15 current limited mode in case of SCB
1
4 OUT16_CONTROL See table “Output stage switching” below 12)
5 OUT16_DELAY See table “Output stage switching” below 12)
6 OUT16_DIAC ‘1‘:OUT16 diagnostic pull-down current and Open Load OL on
‘0‘:OUT16 diagnostic pull-down current and Open Load OL off
0
7 OUT16_ SCB ‘1‘: OUT16 is switched off in case of SCB
‘0‘: OUT16 current limited mode in case of SCB
1
Data Sheet 70 Rev. 1.1, 2012-07-31
TLE 8718 SA
Control of the device
12.2.6 OUTREG_EVEN
12.2.7 OUTREG_ODD
Table 40 OUT1516, Delay configuration
Output stage switching
OUTn_DELAY OUTn_CONTROL Description
1 1 keep state, restart timeout counter for delayed reset behavior
0 1 switch OFF
1 0 switch ON, restart timeout counter for delayed reset behavior
0 0 switch ON, no delay
Table 41 OUTREG_EVEN
Reset sources: RST, power-on-reset, ABE, over-/undervoltage, MSC_MON, OUTPUT_STBY
Controller read access: RD_CONFIG = ’1 00001 x1xx xxxx xxx’
Controller write access: Data Frame = ’0 x UD0 x UD1 x UD2 x UD3 x UD4 x UD5 x UD6 x UD7’
UD Name Description Reset value
0 OUT2 ‘1‘: OUTREG of OUTn is set to “ON”1)
‘0‘: OUTREG of OUTn is set to “OFF”
1) OUTREG_EVEN contains the inverted status of what is programmed via a data frame into OUTREG.
0
1OUT4 0
2OUT6 0
3OUT8 0
4OUT10 0
5OUT12 0
6OUT14 0
7OUT18 0
Table 42 OUTREG_ODD
Reset sources: RST, power-on-reset, ABE, over-/undervoltage, MSC_MON, OUTPUT_STBY
Controller read access: RD_CONFIG = ’1 00001 1xxx xxxx xxx’
Controller write access: Data Frame = ’0 UD0 x UD1 x UD2 x UD3 x UD4 x UD5 x UD6 x UD7 x’
UD Name Description Reset value
0 OUT1 ‘1‘: OUTREG of OUTn is set to “ON”1)‘0‘: OUTREG of OUTn is set
to “OFF”
1) OUTREG_ODD contains the inverted status of what is programmed via a data frame into OUTREG.
0
1OUT3 0
2OUT5 0
3OUT7 0
4OUT9 0
5OUT11 0
6OUT13 0
7OUT17 0
TLE 8718 SA
Control of the device
Data Sheet 71 Rev. 1.1, 2012-07-31
12.2.8 DIAREG1
12.2.9 DIAREG2
Table 43 DIAREG1
Reset sources: RST, power-on-reset, WR_RST, RD_DATA = ’1 11001 xxxx xxx1 xxx’
Controller read access: RD_DATA = ’1 11001 xxxx xxx1 xxx’
Controller write access: -
UD Name Description Reset value
0 OUT1_DIA1 See Table 44 1
1 OUT1_DIA2 1
2 OUT2_DIA1 1
3 OUT2_DIA2 1
4 OUT3_DIA1 1
5 OUT3_DIA2 1
6 OUT4_DIA1 1
7 OUT4_DIA2 1
Table 44 Encoding of diagnosis information
Encoding of the diagnosis bits of the device
OUTn_DIA2 OUTn_DIA1 description
1 1 Power stage ok
1 0 Short circuit to battery (SCB) or diagnostic overtemperature (DOT)
0 1 Open load (OL)1)
1) OL only available when OUTn_DIAC=’1’
0 0 Short circuit to ground (SCG)
Table 45 DIAREG2
Reset sources: RST, power-on-reset, WR_RST, RD_DATA = ’1 11001 xxxx xx1x xxx’
Controller read access: RD_DATA = ’1 11001 xxxx xx1x xxx’
Controller write access: -
UD Name Description Reset value
0 OUT5_DIA1 See Table 44 1
1 OUT5_DIA2 1
2 OUT6_DIA1 1
3 OUT6_DIA2 1
4 OUT7_DIA1 1
5 OUT7_DIA2 1
6 OUT8_DIA1 1
7 OUT8_DIA2 1
Data Sheet 72 Rev. 1.1, 2012-07-31
TLE 8718 SA
Control of the device
12.2.10 DIAREG3
12.2.11 DIAREG4
Table 46 DIAREG3
Reset sources: RST, power-on-reset, WR_RST, RD_DATA = ’1 11001 xxxx x1xx xxx’
Controller read access: RD_DATA = ’1 11001 xxxx x1xx xxx’
Controller write access: -
UD Name Description Reset value
0 OUT9_DIA1 See Table 44 1
1 OUT9_DIA2 1
2 OUT10_ DIA1 1
3 OUT10_ DIA2 1
4 OUT11_ DIA1 1
5 OUT11_ DIA2 1
6 OUT12_ DIA1 1
7 OUT12_ DIA2 1
Table 47 DIAREG4
Reset sources: RST, power-on-reset, WR_RST, RD_DATA = ’1 11001 xxxx 1xxx xxx’
Controller read access: RD_DATA = ’1 11001 xxxx 1xxx xxx’
Controller write access: -
UD Name Description Reset value
0 OUT13_DIA1 See Table 44 1
1 OUT13_DIA2 1
2 OUT14_DIA1 1
3 OUT14_DIA2 1
4 OUT15_DIA1 1
5 OUT15_DIA2 1
6 OUT16_DIA1 1
7 OUT16_DIA2 1
TLE 8718 SA
Control of the device
Data Sheet 73 Rev. 1.1, 2012-07-31
12.2.12 DIAREG5
Table 48 DIAREG5
Reset sources: RST, power-on-reset, WR_RST, RD_DATA = ’1 11001 xxx1 xxxx xxx’
Controller read access: RD_DATA = ’1 11001 xxx1 xxxx xxx’
Controller write access: -
UD Name Description Reset value
0 OUT17_DIA1 See Table 44 1
1 OUT17_DIA2 1
2 OUT18_DIA1 1
3 OUT18_DIA2 1
4 REVCUR_FLAG ‘1‘:Common Reverse Current Flag OUT1...18, no reverse current
‘0‘:Common Reverse Current Flag OUT1...18, Reverse current any
stage for longer than tREVCUR
1
5 OUT15_STATUS ‘0‘: OUT15 is ON1)
‘1‘: OUT15 is OFF
1) ’1’=OFF: Channel is currently either in OFF-state (State A, C or D, see Figure 12), during falling edge or in clamping
‘0‘=ON: Channel is currently either in ON-state (State B, see Figure 12), during rising edge or in current limitation.
02)
2) Register data is asynchronously written and not latched by the device (status).
6 OUT16_STATUS ‘0‘: OUT16 is ON1)
‘1‘: OUT16 is OFF
02)
7 RES15_16_STATUS ‘0‘: DELAYIN > VRES15_16_H for longer than tDELAYIN_GLITCH_x
‘1‘: DELAYIN < VRES15_16_L
12)
Data Sheet 74 Rev. 1.1, 2012-07-31
TLE 8718 SA
Control of the device
12.2.13 DIAREG6
Table 49 DIAREG6
Reset sources: RST, power-on-reset
Controller read access: RD_DATA = ’1 11001 xx1x xxxx xxx’
Controller write access: -
UD Name Description Reset value
0 OUTPUT_STBY ‘1‘: Outputs (1...14, 17, 18) disabled until command WR_START.
‘0‘: Output stages active, following MSC register data
Bit can be set = ‘0’ by command WR_START only
(see Chapter 12.1.3, Figure 25)
1
1 MSC_MON ‘1‘: No MSC monitoring timeout detected
‘0‘: Timeout: MSC monitoring has detected a transmission failure
and power stages are switched off (see Chapter 5.1,Table 21,
Chapter 11.1.2, Item 11.5.46)
By activating the MSC communication this bit is not reset, only
readout of DIAREG6 or power-on-reset (POR) or RST will enable
output stages after MSC_MON has detected a failure.
1
2 POR_FLAG ‘1‘: Power-on-reset (POR) has happened. Bit is set by power-on-
reset only
‘0‘: No POR since last readout. Bit is reset after RST or readout
RST and
RD_DATA =
‘0’;
POR = ‘1’
3 ABE_STATUS ‘1‘: ABE inactive
‘0‘: ABE active low disabling output stages
01)
1) Register data is asynchronously written and not latched by the device (status).
4 FAILURE_FLAG ‘1‘: Common failure flag OUT1...18, no failure
‘0‘: Common failure flag OUT1...18, any stage
11)
5 COTW ‘1‘: Overtemperature flag OUT1...18, no DOT
‘0‘: Overtemperature flag OUT1...18, DOT any stage
This bit is latched, remaining ’0’ after DOT disappears until register
is reset by RST, POR or RD_DATA.
1
6 DIS5_10_STATUS ‘1‘: DIS5_10 > VDIS5_10_H for longer than tDIS5_10
‘0‘: DIS5_10 < VDIS5_10_L for longer than tDIS5_10
01)
7 DELAYIN_STATUS ‘1‘: DELAYIN > VDELAYIN_H for longer than tDELAYIN_GLITCH_x
‘0‘: DELAYIN < VDELAYIN_L for longer than tDELAYIN_x
01)
TLE 8718 SA
Control of the device
Data Sheet 75 Rev. 1.1, 2012-07-31
12.2.14 DIAREG7
Table 50 DIAREG7
Reset sources: -
Controller read access: RD_DATA = ’1 11001 x1xx xxxx xxx’
Controller write access: -
UD Name Description Reset value
0 not implemented 1
1 1
2 1
3 STATUS_SVBATT ‘1‘: No overvoltage detected by SVBATT monitoring
‘0‘: Overvoltage detected by SVBATT monitoring
11)
4 TEST_ACTIVE Device is currently
‘1’: in normal operation
‘0’: factory test mode is active
11)
1) Register data is asynchronously written and not latched by the device (status).
5 STATUS_OV ‘1‘: No overvoltage detected by VDD monitoring
OV detection may be configured to be latched.
‘0‘: Overvoltage detected by VDD monitoring
11)2)
2) Dependent on CONREG4, bit 7 setting, see Figure 16.
6 STATUS_UV ‘1‘: No under voltage detected by VDD monitoring
‘0‘: Under voltage detected by VDD monitoring
01)
7 MON_TEST ‘1‘: VDD monitoring test inactive
‘0‘: VDD monitoring test active
11)3)
3) Same as CONREG4, bit 5
Data Sheet 76 Rev. 1.1, 2012-07-31
TLE 8718 SA
Control of the device
12.2.15 IDENTREG
CHIP_REV is increased for “major” design changes. SW_REV is increased for “minor” changes within each
CHIP_REV separately.
Table 51 IDENTREG
Reset sources: -
Controller read access: RD_DATA = ’ 1 11001 1xxx xxxx xxx’
Controller write access: -
UD Name Description
Software revision
0 SW_REV0 SW_REV1 SW_REV0
1 SW_REV1 A-step: 0 0
B-step: 0 1
C-step: 1 0
D-step: 1 1
Chip Revision
2 CHIP_REV0 CHIP_REV2 CHIP_REV1 CHIP_REV0
3 CHIP_REV1 A-step: 0 0 0
4 CHIP_REV2 B-step: 0 0 1
C-step: 0 1 0
D-step 0 1 1
E-step: 1 0 0
Chip identifier
5 IDENT0 IDENT2 IDENT1 IDENT0
6 IDENT1 TLE8718SA: 1 0 0
7IDENT2
TLE 8718 SA
Control of the device
Data Sheet 77 Rev. 1.1, 2012-07-31
12.2.16 TESTREG
For factory tests only. Do not use this command.
.
To enter in the test mode, a negative voltage on SVBATT (see Item 6.4.10) has to be applied together with a
WR_TESTREG. To leave the test mode, a RST or POR has to be performed.
12.2.17 SEL_THRES
Table 52 TESTREG
Reset Sources: RST, power-on-reset
Controller read access: -
Controller write access: WR_TESTREG = ’1 01110 CD0...CD7 xxx’
CD Name Description Reset value
0 TEST1 reserved for factory test mode 1
1 TEST2 1
2 TEST3 1
3 TEST4 1
4 TEST5 1
5 TEST6 1
6 TEST7 1
7 TEST8 1
Table 53 SEL_THRES
Reset Sources: RST, power-on-reset
Controller read access: -
Controller write access: WR_SEL_THRESH = ’1 00111 CD0...CD7 xxx’
CD Name Description Reset value
0 SEL_TRESH0 active only during factory test mode 1
1 SEL_TRESH1 1
2 SEL_TRESH2 1
3 SEL_TRESH3 1
4 SEL_TRESH4 1
5 SEL_TRESH5 1
6 SEL_TRESH6 1
7 SEL_TRESH7 1
Data Sheet 78 Rev. 1.1, 2012-07-31
TLE 8718 SA
Control of the device
12.2.18 FUSE_SC
Table 54 FUSE_SC
Reset Sources: RST, power-on-reset
Controller read access: -
Controller write access: WR_FUSE_SC = ’1 01011 CD0...CD7 xxx’
CD Name Description Reset value
0 FUSE_SC0 active only during factory test mode 0
1 FUSE_SC1 0
2 FUSE_SC2 0
3 FUSE_SC3 0
4 FUSE_SC4 0
5 FUSE_SC5 0
6 FUSE_SC6 0
7 FUSE_SC7 0
TLE 8718 SA
Application Information
Data Sheet 79 Rev. 1.1, 2012-07-31
13 Application Information
Figure 26 Application Diagram (LVDS configuration)
Note: This is a very simplified example of an application circuit. The function must be verified in the real application.
Note: The information is given as a hint for the implementation of the device only and shall not be regarded as a
description or warranty of a certain functionality, condition or quality of the device.
SIN
SIP
FCLP
FCLN
SSY
SDO
OUT1
Micro Second Channel
Reset
VDD
Monitoring
PowerLogic
8A/55V
GNDABE
ABE
RST
DIS5_10
SI
FCL
Enable
SVBATT
ApplDiagr .vsd
DELAYIN
DELAYOUT
*1 - all trace length at pin typ 50mm
*2 – connected together without parasitic resistor inbetween
*3 - capacitor located close to the connector
*5 - capacitor located close to the IC
Very good GND -
connection ; no bouncing
due to load trancients .
3kΩ *1
47nF
*5
EXTERNAL COMPONENTS.
Ceramic 4,7nF : TDK, Typ C1608 X7R2A472K
Cer amic 47 nF : TDK, Typ C1005 X 7R1C473 K
Ceramic 100 nF : TDK, Typ C1608 X 7R1H104 K
Electrolytic 220 µF : Nippon Chemi -Con, Typ MVH50VC220 MTPK14
Or similar types to achieve the needed ESD -performance
Slug
PCB-
Connector
PCB-
Connector
3.3 or 5V
GND
Max. ± 0.3V
V
BAT
V
BAT
L
LOAD
R
LOAD
parasitic R
from micro controller
5kΩ
from micro controller
OUT2
3A/55V
OUT3
8A/55V
OUT4
3A/55V
OUT5
2. 2A/ 55 V
OUT6
2. 2A/ 55 V
OUT7
2. 2A/ 55 V
OUT8
2. 2A/ 55 V
OUT9
2. 2A/ 55 V
OUT10
2. 2A/ 55 V
OUT11
2. 2A/ 55 V
OUT12
2. 2A/ 55 V
OUT13
2. 2A/ 55 V
OUT14
2. 2A/ 55 V
OUT15
0. 6A/ 55 V
OUT16
0. 6A/ 55 V
OUT17
0. 6A/ 55 V
OUT18
0. 6A/ 55 V
3.3 or 5V
5kΩ
DELAYIN/OUT
5V
5kΩ
10kΩ *1
Battery
Voltage
Monitoring
47nF
*5
PGND
VDD
47µF 100 nF
Supply
5V
4.7nF
*3
100nF
220µF
parasitic R
4.7nF *3
Reverse
Polarity
Protection
100 Ω
100 Ω
5V
4.7nF *3
4.7nF *3
4.7nF *3
4.7nF *3
4.7nF *3
4.7nF *3
4.7nF *3
4.7nF *3
4.7nF *3
4.7nF *3
4.7nF *3
4.7nF *3
4.7nF *3
4.7nF *3
4.7nF *3
4.7nF *3
4.7nF *3
*2
*2
from micro controller
from micro controller
from micro controller
to micro controller
to micro controller
from micro controller
to micro controller
to micro controller
from micro controller
to micro controller
Data Sheet 80 Rev. 1.1, 2012-07-31
TLE 8718 SA
Package Outlines
14 Package Outlines
Figure 27 PG-DSO-36
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant with
government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e
Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
For further information on alternative packages, please visit our website:
http://www.infineon.com/packages.Dimensions in mm
Edition 2012-07-31
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2012 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
