MD1665-D2048-1F-P - SANDISK

SY58604U

3.2Gbps Precision, LVPECL Buffer with

Internal Termination and Fail Safe Input

Precision Edge is a registered trademark of Micrel, Inc.

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com

April 2008

M9999-041508-C

hbwhelp@micrel.com or (408) 955-1690

General Description

The SY58604U is a 2.5/3.3V, high-speed, fully

differential LVPECL buffer optimized to provide less

than 10pspp total jitter. The SY58604U can process

clock signals as fast as 2.5GHz or data patterns up to

3.2Gbps.

The differential input includes Micrel’s unique, 3-pin

input termination architecture that interfaces to LVPECL,

LVDS or CML differential signals, (AC- or DC-coupled)

as small as 100mV (200mVpp) without any level-shifting

or termination resistor networks in the signal path. For

AC-coupled input interface applications, an integrated

voltage reference (VREF-AC) is provided to bias the VT pin.

The output is 800mV LVPECL, with extremely fast

rise/fall times guaranteed to be less than 110ps.

The SY58604U operates from a 2.5V ±5% supply or

3.3V ±10% supply and is guaranteed over the full

industrial temperature range (–40°C to +85°C). For

applications that require CML or LVDS outputs, consider

the SY58603U and the SY58605U, buffers with 400mV

and 325mV output swings respectively. The SY58604U

is part of Micrel’s high-speed, Precision Edge® product

line.

Datasheets and support documentation can be found on

Micrel’s web site at: www.micrel.com.

Functional Block Diagram

Precision Edge®

Features

∑ Precision 800mV LVPECL buffer

∑ Guaranteed AC performance over temperature and

voltage:

– DC-to > 3.2Gbps throughput

– <350ps typical propagation delay (IN-to-Q)

– <110ps rise/fall times

∑ Fail Safe Input

– Prevents output from oscillating when input is

invalid

∑ Ultra-low jitter design

– <1psRMS cycle-to-cycle jitter

– <10psPP total jitter

– <1psRMS random jitter

– <10psPP deterministic jitter

∑ High-speed LVPECL output

∑ 2.5V ±5% or 3.3V ±10% power supply operation

∑ Industrial temperature range: –40°C to +85°C

∑ Available in 8-pin (2mm x 2mm) DFN package

Applications

∑ All SONET clock and data distribution

∑ Fibre Channel clock and data distribution

∑ Gigabit Ethernet clock and data distribution

∑ Backplane distribution

Markets

∑ Storage

∑ ATE

∑ Test and measurement

∑ Enterprise networking equipment

∑ High-end servers

∑ Access

∑ Metro area network equipment

Micrel, Inc.

SY58604U

April 2008

M9999-041508-C

hbwhelp@micrel.com or (408) 955-1690

Ordering Information(1)

Part Number

Package

Type

Operating

Range

Package Marking

Lead

Finish

SY58604UMG

DFN-8

Industrial

604 with Pb-Free

bar-line indicator

NiPdAu

Pb-Free

SY58604UMGTR(2)

DFN-8

Industrial

604 with Pb-Free

bar-line indicator

NiPdAu

Pb-Free

Notes:

1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only.

2. Tape and Reel.

Pin Configuration

8-Pin DFN

Pin Description

Pin Number

Pin Name

Pin Function

1, 4

IN, /IN

Differential Input: This input pair is the differential signal input to the device. Input

accepts DC-Coupled differential signals as small as 100mV (200mVpp). Each pin of

this pair internally terminates with 50_ to the VT pin. If the input swing falls below a

certain threshold (typical 30mV), the Fail Safe Input (FSI) feature will guarantee a

stable output by latching the output to its last valid state. See “Input Interface

Applications” subsection for more details.

Input Termination Center-Tap: Each input terminates to this pin. The VT pin

provides a center-tap for each input (IN, /IN) to a termination network for maximum

interface flexibility. See “Input Interface Applications” subsection.

VREF-AC

Reference Voltage: This output biases to VCC–1.2V. It is used for AC-coupling inputs

IN and /IN. Connect VREF-AC directly to the VT pin. Bypass with 0.01µF low ESR

capacitor to VCC. Maximum sink/source current is ±1.5mA. See “Input Interface

Applications” subsection for more details.

GND,

Exposed pad

Ground: Exposed pad must be connected to a ground plane that is the same

potential as the ground pin.

6, 7

/Q, Q

LVPECL Differential Output Pair: Differential buffered output copy of the input

signal. The output swing is typically 800mV. See “LVPECL Output Termination”

subsection.

VCC

Positive Power Supply: Bypass with 0.1µF//0.01µF low ESR capacitors as close to

the VCC pin as possible.

Micrel, Inc.

SY58604U

April 2008

M9999-041508-C

hbwhelp@micrel.com or (408) 955-1690

Absolute Maximum Ratings(1)

Supply Voltage (VCC) ................................. –0.5V to +4.0V

Input Voltage (VIN) ............................... –0.5V to VCC+0.5V

LVPECL Output Current (IOUT)

Continuous......................................................... 50mA

Surge................................................................ 100mA

Current (VT)

Source or sink on VT pin ............................... ±100mA

Input Current

Source or sink Current on (IN, /IN) ................. ±50mA

Current (VREF)

Source or sink current on VREF-AC(4) ............. ±1.5mA

Maximum Operating Junction Temperature............125°C

Lead Temperature (soldering, 20sec.) ....................260°C

Storage Temperature (Ts) ......................–65°C to +150°C

Operating Ratings(2)

Supply Voltage (VIN) .......................... +2.375V to +3.60V

Ambient Temperature (TA) ..................... –40°C to +85°C

Package Thermal Resistance(3)

DFN

Still-air (qJA) .............................................. 93°C/W

Junction-to-board (YJB)............................ 56°C/W

DC Electrical Characteristics(5)

TA = –40°C to +85°C, unless otherwise stated.

Symbol

Parameter

Condition

Min

Typ

Max

Units

VCC

Power Supply Voltage Range

2.375

3.0

2.5

3.3

2.625

3.6

ICC

Power Supply Current

No load, max. VCC

RDIFF_IN

Differential Input Resistance

(IN-to-/IN)

100

110

Ω

VIH

Input HIGH Voltage

(IN, /IN)

IN, /IN, Note 7

VCC–1.6

VCC

VIL

Input LOW Voltage

(IN, /IN)

IN, /IN

VIH–0.1

VIN

Input Voltage Swing

(IN, /IN)

see Figure 3a, Note 6

0.1

1.7

VDIFF_IN

Differential Input Voltage Swing

(|IN - /IN|)

see Figure 3b

0.2

VIN_FSI

Input Voltage Threshold that

Triggers FSI

100

VREF-AC

Output Reference Voltage

VCC–1.3

VCC–1.2

VCC–1.1

VT_IN

Voltage from Input to VT

1.28

Notes:

1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not

implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions

for extended periods may affect device reliability.

2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.

3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the device's most negative potential on the PCB. YJB and qJA

values are determined for a 4-layer board in still-air number, unless otherwise stated.

4. Due to the limited drive capability, use for input of the same package only.

5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.

6. VIN (max) is specified when VT is floating.

7. VIH (min) not lower than 1.2V.

Micrel, Inc.

SY58604U

April 2008

M9999-041508-C

hbwhelp@micrel.com or (408) 955-1690

LVPECL Outputs DC Electrical Characteristics(5)

VCC = +2.5V ±5% or +3.3V ±10%, RL = 50Ω to VCC-2V; TA = –40°C to +85°C, unless otherwise stated.

Symbol

Parameter

Condition

Min

Typ

Max

Units

VOH

Output HIGH Voltage

VCC-1.145

VCC -0.895

VOL

Output LOW Voltage

VCC-1.945

VCC-1.695

VOUT

Output Voltage Swing

See Figure 3a

550

800

950

VDIFF_OUT

Differential Output Voltage Swing

See Figure 3b

1100

1600

Micrel, Inc.

SY58604U

April 2008

M9999-041508-C

hbwhelp@micrel.com or (408) 955-1690

AC Electrical Characteristics

VCC = +2.5V ±5% or +3.3V ±10%, RL = 50Ω to VCC-2V, Input tr/tf: <300ps; TA = –40°C to +85°C, unless otherwise

stated.

Symbol

Parameter

Condition

Min

Typ

Max

Units

NRZ Data

3.2

4.25

Gbps

fMAX

Maximum Frequency

VOUT > 400mV Clock

2.5

GHz

VIN: 100mV-200mV

180

320

450

tPD

Propagation Delay IN-to-Q

VIN: 200mV-800mV

150

230

350

tSkew

Part-to-Part Skew

Note 7

135

Data Random Jitter

Note 8

psRMS

Deterministic Jitter

Note 9

psPP

Clock Cycle-to-Cycle Jitter

Note 10

psRMS

tJitter

Total Jitter

Note 11

psPP

tr, tf

Output Rise/Fall Times

(20% to 80%)

At full output swing.

110

Duty Cycle

Differential I/O

Notes:

7. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and no skew at the edges at the

respective inputs.

8. Random jitter is measured with a K28.7 pattern, measured at ≤ fMAX.

9. Deterministic jitter is measured at 2.5Gbps with both K28.5 and 223–1 PRBS pattern.

10. Cycle-to-cycle jitter definition: the variation period between adjacent cycles over a random sample of adjacent cycle pairs. tJITTER_CC = Tn –Tn+1,

where T is the time between rising edges of the output signal.

11. Total jitter definition: with an ideal clock input frequency of ≤ fMAX (device), no more than one output edge in 1012 output edges will deviate by

more than the specified peak-to-peak jitter value.

Micrel, Inc.

SY58604U

April 2008

M9999-041508-C

hbwhelp@micrel.com or (408) 955-1690

Functional Description

Fail-Safe Input (FSI)

The input includes a special failsafe circuit to sense

the amplitude of the input signal and to latch the

outputs when there is no input signal present, or

when the amplitude of the input signal drops

sufficiently below 100mVPK (200mVPP), typically

30mVPK. Maximum frequency of SY58604U is limited

by the FSI function.

Input Clock Failure Case

If the input clock fails to a floating, static, or extremely

low signal swing, then the FSI function will eliminate a

metastable condition and guarantee a stable output.

No ringing and no undetermined state will occur at the

output under these conditions.

Note that the FSI function will not prevent duty cycle

distortion in case of a slowly deteriorating (but still

toggling) input signal. Due to the FSI function, the

propagation delay will depend on rise and fall time of

the input signal and on its amplitude. Refer to “Typical

Characteristics” for detailed information.

Timing Diagrams

Figure 1a. Propagation Delay

Figure 1b. Fail Safe Feature

Micrel, Inc.

SY58604U

April 2008

M9999-041508-C

hbwhelp@micrel.com or (408) 955-1690

Typical Characteristics

VCC = 3.3V, GND = 0V, VIN = 100mV, RL = 50Ω to VCC-2V, TA = 25°C, unless otherwise stated.

Micrel, Inc.

SY58604U

April 2008

M9999-041508-C

hbwhelp@micrel.com or (408) 955-1690

Functional Characteristics

VCC = 3.3V, GND = 0V, VIN = 400mV, Data Pattern: 223-1, RL = 50Ω to VCC-2V, TA = 25°C, unless otherwise stated.

Micrel, Inc.

SY58604U

April 2008

M9999-041508-C

hbwhelp@micrel.com or (408) 955-1690

Functional Characteristics (continued)

VCC = 3.3V, GND = 0V, VIN = 400mV, RL = 50Ω to VCC-2V, TA = 25°C, unless otherwise stated.

Micrel, Inc.

SY58604U

April 2008

M9999-041508-C

hbwhelp@micrel.com or (408) 955-1690

Input and Output Stage

Figure 2a. Simplified Differential Input Buffer Figure 2b. Simplified LVPECL Output Buffer

Single-Ended and Differential Swings

Figure 3a. Single-Ended Voltage Swing Figure 3b. Differential Voltage Swing

Micrel, Inc.

SY58604U

April 2008

M9999-041508-C

hbwhelp@micrel.com or (408) 955-1690

Input Interface Applications

Figure 4a. CML Interface

(DC-Coupled)

Option: May connect VT to VCC

Figure 4b. CML Interface

(AC-Coupled)

Figure 4c. LVPECL Interface

(DC-Coupled)

Figure 4d. LVPECL Interface

(AC-Coupled)

Figure 4e. LVDS Interface

Micrel, Inc.

SY58604U

April 2008

M9999-041508-C

hbwhelp@micrel.com or (408) 955-1690

LVPECL Output Termination

LVPECL outputs have very low output impedance

(open emitter), and small signal swing which results in

low EMI. LVPECL is ideal for driving 50Ω-and-100Ω-

controlled impedance transmission lines. There are

several techniques in terminating the LVPECL output,

as shown in Figure 5a and 5b.

Figure 5a. Parallel Termination-Thevenin Equivalent

Figure 5b. Three-Resistor “Y-Termination”