FPGA Configuration Memory - Application Notes - Atmel Corporation - Datasheet.Live

1

Industry-standar d 2-wire Protocol “Bit-banged” C

Routines for the AVR® Microcontroller/ISP Code

for the AT17CXXX FPGA Configuration Memories

Features

•C Routines for Serial Interface

•Example Circuit for AVR Programming

FPGA Configuration Memories

•No Interrupts

•User Programmable Speed

•Supports Entire AVR® Family

•Supports AT17CXXX and AT24CXXX

Families of EEPROM Devices

Introduction

This ap plication note descri bes how t o

In-System Program (ISP) an Atmel

FPGA Configuration m emory (Configu-

rator) using an Atmel AVR®

Microcon tro ller an d ho w to “b it-ba ng” th e

industry-standard 2 -wire protocol that is

needed to program the Configurator

using port pins on an AT90S8515 AVR

Microcontroller. The AT17C series of

Configurators, ranges in density from

64K bits to 2M bits.

Users should be familiar with

the AT90S8515 and AT17 Series

datasheets and the application

note titled, “Programming Specification

for Atmel’s Configuration Memory

EEPROMS AT17C65/128/256/512/

010/020” . This ap plicati on note i s writte n

specifically for the 1M bit device, but can

be easily modified for other AT17 series

family members. C routin es to read and

write data are included. The code

can easily be recompiled for all AVR

controllers with SRAM.

Theory of Operation

The industry-standard 2-wire protocol

bus is a two-wire synchronous serial

interface consisting of one data (SDA)

and one clock (SCL) line. The industry-

standard 2-wire protocol bus is a multi-

master bus where one or more devices,

capable of taking control of the bus, can

be connected. When there is only one

master connected to the bus, the result-

ing code is much simpler because

handling of bus contentions and inter

master access (a master accessing

another master) is not necessary. Only

master devices can drive both the SCL

and SDA lines while a slave device is

only allowed to issue data on the SDA

line.

Software Description

The generic industry-standard 2-wire

protocol routines listed below were

compiled without optimization using

IAR’s C Compiler Version 1.30A

(http://www.iar.se). These routines

implement a single master, industry-

standard 2-wire protocol implementation

and are available for download from

http://www.atmel.com/atmel/prod-

ucts/prod185.htm. The AT90S8515 used

to perform the master function is clocked

by an exte rnal 7.3728 MH z crystal. The

routine Bit Delay is executed in 15 clock

cycles or a 2.03 µ s period and pr ovides

the quarter period bit timing necessary to

meet the 3.3V timing specifications

found i n the abov e referenc ed Config u-

rator programming application note.

This code uses PORTB of the

AT90S8515. On power-up PORTB is

initialized to all inputs with the internal

pull-ups turned off, the external pull-ups

pull the S DA and S CL lines high a nd the

C Routines for

the

Microcontroller/

AT17CXXX

ISP Code

Application

Note

Rev. 1298A–0 4/2 0/9 9

AT17CXXX

2

PORTB output latch bits SCL and SDA are initialized to

zero. Routine WriteSDA and WriteSCL toggle their

respective data direction register bit depending on the

value of parameter “state”. When state is a “1” the port pin

is configured as input (external pull-ups pull high). When

state is a “0” the port pin is configured as an output and the

latch drives the pin low. Table 1 li sts the generic industry-

standard 2-wire protocol routines and the amount o f code

space consumed by each. WriteSDA and WriteSCL are

very simple routines that could be incorporated into their

respective calling routines to further reduce code size.

Table 1 lists the number of clock cycles consumed while

implementing the function. Compiler option s were set to

default, i.e. no AVR specific optimizations.

General Calling Sequence for the Industry-

standard 2-wire Protocol Routines

Write

SendStartBit() // start

SendByte(byte,msbfirst) // send address MSB first

SendByte(byte,lsbfirst) // send data byte to that

address LSB first

SendStop() // stop

Read

SendStartBit() // start

SendByte(byte,msbfirst) // send address MSB first

byte = GetByte(lastbyte) // read byte from that

address … last byte

= 1 for the last byte

in a serial stream

SendStop() // stop

The routines SendStartBit, SendByte, and GetByte all

leave the SCL signal low on exit, allowing the next routine

to write data to SDA. (The industry-standard 2- wire proto-

col allows changes on SDA only when SCL is low;

otherwise the industry-standard 2-wire protocol device will

interpret a start or stop condition). SendByte returns a flag

indicating a successful write to the industry-standard 2-wire

protocol slave, 0 x 01 signals that the slave did not

acknowledge the transfer and th at something is wr ong on

the indus try-standar d 2 -wire proto col bus or with the slav e.

WritePage and Pr ogra mResetPo lari ty use thi s flag for data

polling. Figure 1 shows industry-standard 2-wire protocol

start and stop bit conditions.

Figure 1. Industry-standard 2-wire Protocol Start

andStopBits

The AT17C010 device is programmed/verified on a

128-byte page boundary. Dur ing normal FPGA configur a-

tion operati ons, the read of t he device s tarts at addres s 0

and co ntinues until the F PGA has completed read ing its

configuration. The routines WritePage and ReadPage write

and read 128-byte pages from the configuration memory

and use the generic industry-standard 2-wire protocol

routines to perform this function. WritePage and ReadPage

are both called with the page address to write/read to and a

pointer to a 128-byte page buffer. At the end of a page

write the data polling methodology is used to determine

the end of the internal page programming cycle. Program-

ResetPolarity and VerifyResetPolarity write and read data

from memory locations 0 x 20000 – 0 x 20003 in effect

setting and verifying the RESET/OE polarity.

Table 1. Size and Execution Time for Indus try- standard

2-wire Protocol Routines

Routine Clocks Bytes

SendStartBit 138 24

SendByte 1050 - 1054 74

SendStopBit 110 18

BitDelay 15 18

SetSCLHigh 33 40

WriteSCL 12 - 13 12

WriteSDA 12 - 13 12

GetByte 1089 - 1090 68

Table 2. Code Size and Execution Time for

Page Read/Write

Routines Cycles Bytes

WritePage 287872 152

ReadPage 145901 122

ProgramResetPolarity 156104 102

VerifyResetPolarity 157269 90

SCL

SDA

SCL

SDA

START

CONDITION STOP

CONDITION

AT17CXXX

3

PORTB on the AT90S8515 is us ed to communicate with

the FP GA Configur ation Me mory. Bit ass ignment s are as

follows:

// PB0 = SDA

// PB1 = SCL

// PB2 = SER_EN – used to put AT17C010 in serial

programming mode

The routine Init.c initializes the AT90S8515 peripherals.

Routines Timer0.c and Timer1.c are general-purpose time

out routines. Main is used to call WritePage, ReadPage,

Program Reset Po larity , and Veri fyReset Pola rity and s erves

to illustrate proper calling conventions for those routines.

Init.c

Main.c

Timer0.c

Timer1.c

Modifications and Optimizations

Impact on Changing Cr ystal Frequency

If the user decides to c hange oscillator frequencies then

the following routines would have to be modified:

BitDelay

ProgramResetPolarity

SetSCLHigh

WritePage

BitDelay uses NOP’s to effect a quarter b us period delay .

Add or subtract NOP’s to increase or dec rea se the delay .

In the r outin es Prog ramRe setPo larity an d Writ ePage ti mer

1 is used to time- out after 20 milliseconds , the program-

ming operation should have completed by then. Timer 0 is

used in Set SCLHigh to time out after 35 microseconds . If

the SCL line is not high by then, then something is wrong

on the bus.

Impact on Changing PAGE_SIZE

PAGE_SIZE is defined in at17c.h and initially set to 128 to

support the AT17C512/010/020 devices. PAGE_SIZE can

be changed to support other configuration memories or

other generic industry-standard 2-wire protocol devices.

Routines effected are:

Main

ReadPage

WritePage

© Atmel Corporation 1999.

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