A8589 Wide Input Voltage, 2.4MHz, 2.5A Asynchronous Buck Regulator With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output FEATURES AND BENEFITS * * * * * * * * * * * * Automotive AEC-Q100 qualified Withstands surge voltages up to 40V Operates as low as 3.4VIN (typ) with VIN decreasing Utilizes pulse frequency modulation (PFM) to draw only tens of microamperes from VIN while maintaining keep-alive VOUT PWM/PFMn mode control input pin Delivers up to 2.5A of output current with integrated 110m high voltage MOSFET SLEEPn input pin commands ultra-low current shutdownmode Adjustable output voltage with 1.0% accuracy from 0C to 85C, 1.5% from -40C to 150C Programmable switching frequency: 250kHz to 2.4MHz Synchronization capability: applying a clock input to the PWM/PFMn input pin will increase the PWM frequency Active low, power-on reset (NPOR) open-drain output Maximized duty cycle for low dropout Continued on the next page... Designed to provide the power supply requirements of next generation car audio and infotainment systems, the A8589 provides all the control and protection circuitry to produce a high current regulator with 1.0% output voltage accuracy. The A8589 employs pulse frequency modulation (PFM) to draw less than 50A from 12VIN while supplying 3.3V/40A. After startup, the A8589 operates down to at least 3.6VIN (VIN falling). Features of the A8589 include a PWM/PFMn mode control input to enable PWM (logic high) or PFM (logic low). If the PWM/PFMn input is driven by an external clock signal higher than the base frequency (fOSC) the PWM frequency synchronizes to the incoming clock frequency. The SLEEPn input pin commands an ultra-low current shutdown mode requiring less than 5A for internal circuitry and 10A (max) for MOSFET leakage at 16VIN, 85C. The A8589 has external compensation to accommodate a wide range of frequencies and external components, and provides a power-on reset (NPOR) signal validated by the output voltage. Continued on the next page... Package: 16-pin TSSOP with exposed thermal pad (suffix LP) APPLICATIONS: * Automotive: Instrument clusters Audio Systems * Home Audio Not to scale VIN 1 VIN 2 VIN CIN 5 GND 13 GND CP DESCRIPTION U1 A8589 9 COMP 3 SS 8 FSET 12 VREG RZ CSS RFSET 15 SW 14 SW BOOT BIAS FB Navigation HVAC LO CBOOT D1 VOUT CO 16 11 10 RFB1 CVREG CZ RFB2 CFB EN 4 Mode 6 SLEEP PWM/PFM POK 7 Typical Application Diagram A8589-DS, Rev. 2 POK A8589 Wide Input Voltage, 2.4MHz, 2.5A Asynchronous Buck Regulator With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output FEATURES AND BENEFITS (CONTINUED) * Pre-bias startup capable, VOUT will not cause a reset * External compensation for maximum flexibility * Stable with ceramic or electrolytic output capacitors * Excellent set of protection features to satisfy the most demanding applications * Overvoltage, pulse-by-pulse current limit, hiccup mode short circuit, and thermal protection * Robust FMEA, with pin open/short and component faults * Thermally enhanced, surface mount package DESCRIPTION (CONTINUED) Extensive protection features of the A8589 include pulse-by-pulse current limit, hiccup mode short circuit protection, open/short asynchronous diode protection, BOOT open/short voltage protection, VIN undervoltage lockout, VOUT overvoltage protection and thermal shutdown. The A8589 is supplied in a low profile 16-pin TSSOP package with exposed power pad (suffix LP). It is lead (Pb) free, with 100% matte-tin leadframe plating. Selection Guide Part Number Operating Ambient Temperature Range TA, (C) Packing A8589KLPTR-T -40 to 125 4000 pieces per 13-in. reel Contact Allegro(R) for additional packing options. Table of Contents Specifications 3 Functional Block Diagram 4 Pin-out Diagram and Terminal List 5 Electrical Characteristics 6 Characteristic Performance 10 Functional Description 12 Overview 12 Reference Voltage 12 PWM Switching Frequency 12 SLEEPn Input 12 PWM/PFMn Input and PWM Synchronization 13 BIAS Input Functionality, Ratings, and Connections13 Transconductance Error Amplifier 14 Slope Compensation 14 Current Sense Amplifier 14 Power MOSFETs 14 BOOT Regulator 14 Pulse Width Modulation (PWM) Mode 14 Low-IQ Pulse Frequency Modulation (PFM) Mode 15 Maximized Duty Cycle Control 15 Reduced Current (Low-IP) PWM Mode 17 Soft Start (Startup) and Inrush Current Control 17 Pre-Biased Startup 18 Not Power-On Reset (NPOR) Output 18 Protection Features 18 Undervoltage Lockout (UVLO) 18 Pulse-by-Pulse Overcurrent Protection (OCP) 18 Overcurrent Protection (OCP) and Hiccup Mode20 BOOT Capacitor Protection 20 Asynchronous Diode Protection 21 Output Overvoltage Protection (OVP) 21 Pin-to-Ground and Pin-to-Pin Short Protections 21 Thermal Shutdown (TSD) 21 Application Information 25 Design and Component Selection 25 Setting the Output Voltage (VOUT) 25 PWM Base Switching Frequency (fOSC, RFSET) 25 Output Inductor (LO) 26 Output Capacitors 27 LowIQPFM Output Voltage Ripple Calculation 28 Input Capacitors 28 Asynchronous Diode (D1) 29 Bootstrap Capacitor 29 Soft Start and Hiccup Mode Timing (CSS) 30 Compensation Components (RZ, CZ, and CP) 30 A Generalized Tuning Procedure 32 Power Dissipation and Thermal Calculations 35 PCB Component Placement and Routing 36 Typical Applications Schematics 38 Package Outline Drawing 39 Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 2 A8589 Wide Input Voltage, 2.4MHz, 2.5A Asynchronous Buck Regulator With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output SPECIFICATIONS Absolute Maximum Ratings* Characteristic Symbol Notes Rating Unit -0.3 to 40 V -0.3 to VIN + 0.3 V -1.0 to VIN + 3 V Continuous VSW-0.3 to VSW + 5.5 V BOOT OV Fault Condition VSW-0.3 to VSW + 7.0 V VIN, SLEEPn, SS Pin Voltage SW Pin Voltage VSW BOOT Pin Voltage VBOOT BIAS Pin Voltage VBIAS Continuous (minimum limit is a function of temperature) t < 50 ns Continuous -0.3 to 5.5 BIAS OV Fault Condition -0.3 to 6 All Other Pins Voltage V -0.3 to 5.5 V -40 to 125 C Operating Ambient Temperature TA Maximum Junction Temperature TJ(max) 150 C Tstg -55 to 150 C Storage Temperature K temperature range *Operation at levels beyond the ratings listed in this table may cause permanent damage to the device. The Absolute Maximum ratings are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the Electrical Characteristics table is not implied. Exposure to Absolute Maximum-rated conditions for extended periods may affect device reliability. Thermal Characteristics may require derating at maximum conditions, see application information Characteristic Package Thermal Resistance Symbol RJA Test Conditions* On 4-layer PCB based on JEDEC standard Value Unit 34 C/W *Additional thermal information available on the Allegro website. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 3 Wide Input Voltage, 2.4MHz, 2.5A Asynchronous Buck Regulator With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output A8589 VIN BIAS VREG - - 3.8V 3.4V LDO OFF V BIAS > LDOOUT + 50 mV + BOOT REG 5.0V UVLO B OOT OFF 1.205 V BG - DELAY 103s 2.90V Digital POR + 2V, 4.1V VPWMOFFS 400 mV BOOT OFF P WM P WM + SE s leep P WM fSYNC DELAY PWM/PFMn minOff 750mA P FM - GCSA S Q R Q 110 m Q fSW Current Comp VREG PFM Controller 2048 IFB Error Amplifier s leep P WM SW 10 BOOT > 4.1V DIODEOK FB < 0.8 V FB BOOT + Low IP P WM CLK FB < 0.4V f OSC FB < 0.2V FSET BOOT FAULT 2x ISENSE fSYNC>1.2 x fOSC F F/2 F/4 OC 250 mA EN B OOT RE G Q VREG SLEEPn REGOV + 5.75V V BIAS rising LDO CLAMP OCL V REF 800 mV COMP s leep P WM + s leep P WM - Soft Start Offset 400 mV 20A SS 5A FB < 700 mV (PFM) FB > 880 mV (PWM) OCL DIODEOK BOOT FAULT REGOV UVLO POR TSD FAULT LOGIC (See Fault Table) s leep P WM HIC SET HICCUP LOGIC HICCUP 1 k 2 k HIC RST PULL DOWN BOOT OFF NPOR DELAY FB <700 mV (PFM ) FB >880 mV (PWM) FB <740 mV (PWM ) 7.5ms Functional Block Diagram Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 4 Wide Input Voltage, 2.4MHz, 2.5A Asynchronous Buck Regulator With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output A8589 Pin-out Diagram and Terminal List VIN 1 16 BOOT VIN 2 15 SW SS 3 14 SW SLEEPn 4 GND 5 PWM/PFMn 6 NPOR 7 FSET 8 PAD 13 GND 12 VREG 11 BIAS 10 FB 9 COMP Package LP, 16-Pin TSSOP Pin-out Diagram Terminal List Table Name Number 11 BIAS Bias input, supplies internal circuitry. 16 BOOT High-side gate drive boost input. This pin supplies the drive for the high-side N-channel MOSFET. Connect a 47nF ceramic capacitor from BOOT to SW. 9 COMP Output of the error amplifier and compensation node for the current mode control loop. Connect a series RC network from this pin to GND for loop compensation. See the Design and Component Selection section of this datasheet for further details. 10 FB Feedback (negative) input to the error amplifier. Connect a resistor divider from the regulator output, VOUT, to this pin to program the output voltage. 8 FSET Frequency setting pin. A resistor, RFSET, from this pin to GND sets the base PWM switching frequency (fOSC). See the Design and Component Selection section for information on determining the value of RFSET. 5, 13 GND Ground pins. 7 NPOR Active low, power-on reset output signal. This pin is an open drain output that transitions from low to high impedance after the output has maintained regulation for tD(NPOR). - PAD Exposed pad of the package providing enhanced thermal dissipation. This pad must be connected to the ground plane(s) of the PCB with at least 6 vias, directly in the pad land. 6 Function Sets operating output mode (fSW). Setting this pin low forces Low-IQ PFM mode (fSW set by load). Setting this pin high PWM/PFMn forces PWM mode switching at the the base frequency (fOSC), set by RFSET. Applying an external clock input to this pin forces synchronization of PWM to the clock input rate (fSYNC), at a rate higher than fOSC. SLEEPn low overrides this pin. Setting this pin low forces sleep mode (very low current shutdown mode: VOUT = 0V). This pin must be set high to enable the A8589. If the application does not require a sleep mode, then this pin can be tied directly to VIN. Do not float this pin. 4 SLEEPn 3 SS Soft start and hiccup pin. Connect a capacitor, CSS, from this pin to GND to set soft start mode duration. The capacitor also determines the hiccup period during overcurrent. 14, 15 SW The source of the high-side N-channel MOSFET. The external free-wheeling diode (D1) and output inductor (LO) should be connected to this pin. Both D1 and LO should be placed close to this pin and connected with relatively wide traces. 1, 2 VIN Power input for the control circuits and the drain of the high-side N-channel MOSFET. Connect this pin to a power supply providing from 4.0 to 35V. A high quality ceramic capacitor should be placed and grounded very close to this pin. 12 VREG Internal voltage regulator bypass capacitor pin. Connect a 1F ceramic capacitor from this pin to ground and place it very close to the A8589. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 5 Wide Input Voltage, 2.4MHz, 2.5A Asynchronous Buck Regulator With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output A8589 ELECTRICAL CHARACTERISTICS: valid at 4.0V VIN 35V, -40C TA = TJ 150C; unless otherwise specified Characteristic Symbol Test Conditions Min. Typ. Max. Unit Input Voltage Input Voltage Range1 VIN 4.0 - 35 V VIN rising 3.6 3.8 4.0 V VIN UVLO Stop VINUV(OFF) VIN falling 3.2 3.4 3.6 V VIN UVLO Hysteresis VINUV(HYS) - 400 - mV VIN UVLO Start VINUV(ON) Input Supply Current Sleep Mode Input Supply Current2,6 PWM Mode Input Supply Current2 Low-IQ PFM Input Supply Current2,3 VSLEEPn 0.5V, TJ = 85C, VIN =16 V - 5 15 A VSLEEPn 0.5 V, TJ = 85C, VIN = 35 V - 7 25 A IIN(PWM) VBIAS > 3.2V, IOUT = 0 mA - 2.5 5.0 mA ILO_IQ(0) VIN = 12 V, VOUT = 3.3V, VPWMPFMn 0.8 V, IOUT= 40 A, TA =25C, components selected per table3 - - 50 A ILO_IQ(1) VIN = 12 V, VOUT = 5.0V, VPWMPFMn 0.8 V, IOUT= 200 A, TA = 25C, components selected per table3 - - 250 A ILO_IQ(2) VIN = 12 V, VOUT = 6.5V, VPWMPFMn 0.8 V, IOUT= 1mA, TA = 25C, components selected per table3 - - 750 A IIN(SLEEP) Voltage Regulation Feedback Voltage Accuracy4 Low-IQ PFM Mode Output Voltage Setting Range1,3 PWM Output Voltage Setting Range3 Output Dropout Voltage3 VFB VOUT(LO_IQ) VOUT VOUT(SAT) Low-IQ PFM Mode Ripple Voltage3 VOUT(LO_IQ) Low-IQ PFM Mode Peak Current Threshold IPEAK(LO_IQ) Low-IQ PFM Mode DC Load Current3 IOUT(LO_IQ) 0C < TJ < 85C, VIN 4.1 V, VFB = VCOMP 792 800 808 mV -40C < TJ < 150C, VIN 4.1V, VFB = VCOMP 788 800 812 mV 3.0V < VBIAS < 5.5V and ILO_IQ specifications satisfied 3.3 - 6.5 V VBIAS = GND, PWM only, no PFM mode 0.8 - 10 V TA = 85C, DCRLO 75m, VIN = 3.6 V, IOUT=1A, fSW = 425 kHz 3.27 3.3 - V TA = 85C, DCRLO 75m, VIN = 5.3 V, IOUT=1A, fSW = 425 kHz 4.95 5.0 - V TA = 85C, DCRLO 50m, VIN = 3.75 V, IOUT=1A, fSW = 2 MHz 3.25 3.3 - V TA = 85C, DCRLO 50m, VIN = 5.5 V, IOUT=1A, fSW = 2 MHz 4.89 5.0 - V 8 V < VIN < 12 V, components selected per table3 - 30 65 mVPP fSW < 750 kHz - 750 - mAPEAK fSW > 750 kHz - 850 - mAPEAK 400 550 700 mA Maximum load to maintain VOUT(LO_IQ), components selected per table 3 Continued on the next page... Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 6 Wide Input Voltage, 2.4MHz, 2.5A Asynchronous Buck Regulator With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output A8589 ELECTRICAL CHARACTERISTICS (continued): valid at 4.0V VIN 35V, -40C TA = TJ 150C; unless otherwise specified Characteristic Symbol Test Conditions Min. Typ. Max. Unit -38 - -16 nA - 65 - dB Error Amplifier Feedback Input Bias Current2 Open Loop Voltage Gain IFB AVOL 400 mV < VFB 550 750 950 A/V 0 V < VFB < 400 mV 275 375 475 A/V VCOMP = 1.2 V - 75 - A FAULT = 1 or HICCUP = 1 - 1 - K PWMOFFS VCOMP level required for 0% duty cycle - 400 - mV - 95 135 ns - 95 130 ns Transconductance gm Output Current IEA COMP Pull-Down Resistance VCOMP = 1.2 V RCOMP Pulse Width Modulation (PWM) PWM Ramp Offset Minimum Controllable PWM On-Time tON(MIN)PWM Minimum Switch Off-Time tOFF(MIN)PWM COMP to SW Current Gain gmPOWER Slope Compensation3 SE 12V < VIN < 16V, IOUT = 1 A, VBOOT - VSW = 4.5 V - 2.85 - A/V fOSC = 2.44 MHz 2.1 3.0 3.9 A/s fOSC = 1.00 MHz 0.60 0.91 1.2 A/s fOSC = 252 kHz 0.14 0.20 0.26 A/s MOSFET Parameters1 High-Side MOSFET On-Resistance5 High-Side MOSFET Leakage2,6 SW Node Slew Rate3 Low-Side MOSFET RDS(on)HS Ilkg(HS) SRSW On-Resistance5 RDS(on)LS TJ =25C, VBOOT - VSW = 4.5 V, IDS = 0.4 A - 110 125 m TJ =150C, VBOOT - VSW = 4.5 V, IDS = 0.4 A - 190 215 m TJ < 85C, VSLEEPn 0.5 V, VSW = 0 V, VIN=16V - - 10 A TJ 150C, VSLEEPn 0.5V, VSW = 0 V, VIN=16V - 60 150 A 12V < VIN < 16V - 0.72 - V/ns TJ = 25C, VIN 6V, IDS = 0.1A - - 10 RFSET = 8.06 k, VPWM/PFMn= high 2.20 2.44 2.70 MHz RFSET = 23.7 k, VPWM/PFMn= high 0.90 1.00 1.10 MHz RFSET = 102 k, VPWM/PFMn= high - 252 - kHz PWM Switching Frequency Base PWM Switching Frequency fOSC PWM Synchronization Timing Synchronization Frequency Range fSYNC(MULT) 1.2 x fOSC(typ) - 1.5 x fOSC(typ) - Synchronized PWM Frequency fSYNC(PWM) - - 2.9 MHz Synchronization Input Duty Cycle DSYNC - - 80 % Synchronization Input Pulse Width twSYNC 200 - - ns Synchronization Input Rise Time3 trSYNC - 10 15 ns tfSYNC - 10 15 ns Synchronization Input Fall Time3 Continued on the next page... Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 7 A8589 Wide Input Voltage, 2.4MHz, 2.5A Asynchronous Buck Regulator With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output ELECTRICAL CHARACTERISTICS (continued): valid at 4.0V VIN 35V, -40C TA = TJ 150C; unless otherwise specified Characteristic Symbol Test Conditions Min. Typ. Max. Unit PWM/PFMn Pin Input Thresholds PWM/PFMn High Threshold VPWMPFMn(H) PWM/PFMn Low Threshold VPWMPFMn(L) PWM/PFMn Hysteresis VPWMPFMnhys PWM/PFMn Input Resistance Low-IQ PFM Transition Delay 3.0V < VBIAS < 3.6 V, VPWMPFMn rising - - 2.0 V 4.5 V < VBIAS < 5.5 V, VPWMPFMn rising - - 2.6 V 3.0 V < VBIAS < 3.6 V, VPWMPFMn falling 0.8 - - V 4.5 V < VBIAS < 5.5 V, VPWMPFMn falling 1.2 - - V 3.0 V < VBIAS < 3.6 V, VPWMPFM(H) - VPWMPFM(L) - 200 - mV 4.5 V < VBIAS < 5.5 V, VPWMPFM(H) - VPWMPFM(L) - 400 - mV RPWMPFMn tD(LO_IQ) 120 200 280 k PWM/PFMn = low, VSS > HIC/PFMEN, NPOR=high - 2048 - counts fOSC < 1.5 MHz - 435 - ns PFM Mode Timing Constant PFM Off-Time tOFF(PFM) Maximum PFM On-Time tON(PFM)MAX fOSC > 1.5 MHz - 275 - ns - 4.1 - s 1.3 2.1 V SLEEPn Pin Input Thresholds SLEEPn High Threshold VSLEEP(H) VSLEEPn rising - SLEEPn Low Threshold VSLEEP(L) VSLEEPn falling 0.5 1.2 - V SLEEPn Delay tD(SLEEP) VSLEEPn transitioning low 55 103 150 s - 500 - nA - 3.05 - V 3.2 - 5.5 V 1.7 2.0 2.2 V SLEEPn Input Bias Current ISLEEPBIAS VSLEEPn = 5 V VREG Pin Output VREG Output Voltage VVREG VBIAS = 0 V BIAS Pin Input BIAS Input Voltage Range VBIAS BOOT Regulator BOOT Voltage Enable Threshold VBOOT(EN) BOOT Voltage Enable Hysteresis VBOOT(HYS) - 200 - mV BOOT Voltage Low-Side Switch Disable Threshold VBOOTLS(DIS) VBOOT rising - 4.1 - V - 200 275 mV - 2.3 - V VBOOT rising Soft Start Pin FAULT, HICCUP Reset Voltage Hiccup OCP (and Low IQ PFM Counter Enable) Threshold VSSRST VSS falling due to RSS(FLT) HIC/PFMEN VSS rising Maximum Charge Voltage VSS(MAX) - VVREG - - Startup (Source) Current ISSSU HICCUP = FAULT = 0 -30 -20 -10 A Hiccup (Sink) Current ISSHIC HICCUP = 1 2.4 5 10 A Pull-Down Resistance RSS(FLT) - 2 - k FAULT = 1 or VSLEEPn = low Continued on the next page... Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 8 A8589 Wide Input Voltage, 2.4MHz, 2.5A Asynchronous Buck Regulator With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output ELECTRICAL CHARACTERISTICS (continued): valid at 4.0V VIN 35V, -40C TA = TJ 150C; unless otherwise specified Characteristic Symbol Test Conditions Min. Typ. Max. Unit Soft Start Pin (continued) Soft Start Frequency Foldback Soft Start Delay Time3 Soft Start Output Ramp Time3 fSW(SS) 0 V < VFB < 200 mV - fOSC / 4 - - 200 mV < VFB < 400 mV - fOSC / 2 - - 400 mV < VFB - fOSC - - tD(SS) CSS = 22 nF - 440 - s tSS CSS = 22 nF - 880 - s VSS > 2.3 V and OCL = 1 - 120 - counts Hiccup Modes Hiccup, OCP Count OCPLIM Hiccup, BOOT Undervoltage (Shorted) Count BOOTUV - 120 - counts Hiccup, BOOT Overvoltage (Open) Count BOOTOV - 7 - counts 3.6 4.1 4.6 A 2.3 3.1 3.9 A 860 880 902 mV - -10 - mV 715 740 765 mV - 10 - mV 665 700 735 mV Overcurrent Protection (OCP) PWM Pulse-by-Pulse Limit ILIM(TONMIN) tON = tON(MIN)PWM ILIM(TONMAX) tON = (1/fSW) - tOFF(MIN)PWM, no PWM synchronization Output Voltage Protection (OVP) VOUT Overvoltage PWM Threshold VOUT(OV)PWM VFB rising, PWM mode VOUT Overvoltage Hysteresis VOUT(OV)HYS VFB falling, relative to VOUT(OV)PWM VOUT Undervoltage PWM Threshold VOUT(UV)PWM VFB falling, PWM mode VOUT Undervoltage Hysteresis VOUT(UV)HYS VFB rising, relative to VOUT(UV)PWM VOUT Undervoltage PFM Threshold VOUT(UV)PFM VFB falling, Low-IQ PFM mode Power-On Reset (NPOR) Output NPOR Rising Delay tD(NPOR) VFB rising only 5 7.5 10 ms NPOR Low Output Voltage VNPOR(L) INPOR = 5 mA - 185 400 mV -1 - 1 A 155 170 185 C - 20 - C NPOR Leakage Current2 INPOR(LKG) VNPOR = 5.5 V Thermal Protection Thermal Shutdown Rising Threshold3 Thermal Shutdown Hysteresis3 TSD TSDHYS PWM stops immediately and COMP and SS are pulled low 1Thermally limited depending on input voltage, output voltage, duty cycle, regulator load currents, PCB layout, and airflow. current is defined as coming out of the node or pin, positive current is defined as going into the node or pin. 3Ensured by design and characterization, not production tested. 4Performance at the 0C and 85C ranges ensured by design and characterization, not production tested. 5Performance at 25C ensured by design and characterization, not production tested. 6Performance at 85C ensured by design and characterization, not production tested. 2Negative Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 9 Wide Input Voltage, 2.4MHz, 2.5A Asynchronous Buck Regulator With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output A8589 CHARACTERISTIC PERFORMANCE Reference Voltage versus Temperature Switching Frequency versus Temperature 808 3.50 806 fOSC = 2.44 MHz 3.00 fOSC = 1.00 MHz 2.50 802 fOSC (MHz) V VREF (mV) 804 800 798 2.00 1.50 796 1.00 794 792 0.50 -50 -25 0 25 50 75 100 125 150 -50 -25 0 Temperature (C) 3.9 950 3.8 900 3.7 START, VINUV(ON) STOP, VINUV(OFF) 3.6 3.5 3.4 3.3 125 150 850 VOUT(OV)PWM VOUT(UV)PWM 800 VOUT(UV)PFM 750 700 650 -50 -25 0 25 50 75 Temperature (C) 100 125 150 -50 Pulse-by-Pulse Current Limit at t ON(MIN)PWM (ILIM(TONMIN)) versus Temperature 4.50 -25 0 25 50 75 Temperature (C) 100 125 150 Error Amplifier Transconductance versus Temperature 900 4.40 800 4.30 700 Transconductane (A/V) ILIM(TONMIN) (A) 100 VOUT Overvoltage and Undervoltage Thresholds versus Temperature VOUT OV and UV Thresholds (V) VIN UVLO Thresholds (V) VIN UVLO Start and Stop Thresholds versus Temperature 25 50 75 Temperature (C) 4.20 4.10 4.00 3.90 3.80 V VFB>400 mV FB>400 mV V VFB<400mV FB<400 mV 600 500 400 300 200 3.70 -50 -25 0 25 50 75 Temperature (C) 100 125 150 100 -50 -25 0 25 50 75 Temperature (C) 100 125 Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 150 10 Wide Input Voltage, 2.4MHz, 2.5A Asynchronous Buck Regulator With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output A8589 PWM/PFMn High and Low Voltage Thresholds versus Temperature, VBIAS = 5.0 V PWM/PFMn High and Low Voltage Thresholds versus Temperature, VBIAS = 3.3 V 2.3 1.60 VPWMPFMn(H) 1.50 1.45 1.40 1.35 1.30 1.25 2.0 1.9 1.8 1.7 1.15 1.6 -50 -25 0 25 50 75 Temperature (C) 100 125 -50 150 -25 0 25 50 75 100 125 150 Temperature (C) SLEEPn High and Low Voltage Thresholds versus Temperature SS Start and Hiccup Currents versus Temperature 1.60 25.0 VSLEEP(H) VSLEEP(L) 1.40 Startup, ISSSU Hiccup, ISSHIC 20.0 1.20 Current (A) SLEEPn Thresholds (V) VPWMPFMn(L) 2.1 1.20 1.00 0.80 15.0 10.0 5.0 0.60 -50 -25 0 25 50 75 100 125 0 150 -50 Temperature (C) NPOR Low Output Voltage at 5 mA versus Temperature 400 -25 0 25 50 75 Temperature (C) 100 125 150 NPOR Time Delay versus Temperature 8.00 7.90 350 7.80 300 7.70 250 tD(NPOR) (ms) V NPOR (mV) VPWMPFMn(H) 2.2 VPWMPFMn(L) PWM/PFMn Thresholds (V) PWM/PFMn Thresholds (V) 1.55 200 150 7.60 7.50 7.40 7.30 100 7.20 50 7.10 7.00 0 -50 -25 0 25 50 75 Temperature (C) 100 125 150 -50 -25 0 25 50 75 Temperature (C) 100 125 150 Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 11 A8589 Wide Input Voltage, 2.4MHz, 2.5A Asynchronous Buck Regulator With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output FUNCTIONAL DESCRIPTION Overview The A8589 is an asynchronous, current mode, buck regulator that incorporates all the control and protection circuitry necessary to provide the power supply requirements of car audio and infotainment systems. The A8589 has three modes of operation. First, the A8589 can deliver up to 2.5A in pulse width modulation (PWM) mode. Second, in Low-IQ pulse frequency modulation (PFM) mode, the A8589 will draw only tens of microamperes from VIN while maintaining VOUT (at no load). Under most conditions, Low-IQ PFM mode is typically capable of supporting up to 550mA. Third, with the SLEEPn pin low, the A8589 will enter an ultralow current shutdown (sleep) mode where VOUT = 0V and the total current drawn from VIN will typically be less than 10A. The PWM/PFMn input pin is used to select either PWM or Low-IQ PFM mode. In PFM mode the A8589 is able to supply a relatively high amount of current (typically 550mA). This allows enough current for a microcontroller or DSP to fully power-up. After power-up, to obtain the full current capability of the A8589, the microcontroller or DSP must change the PWM/PFMn input from a logic low to a logic high to force PWM mode. This will provide full current to the remainder of the system. The A8589 was designed to support up to 2.5A. However, the exact amount of current it will supply, before possible thermal shutdown, depends heavily on: duty cycle, ambient temperature, airflow, PCB layout, and PCB construction. Figure 1 shows calculated current ratings versus ambient temperature for VIN= 12V, and VOUT = 3.3V and 5.0V, at both fSW = 425kHz and fSW = 2MHz. This analysis assumed a 4-layer PCB constructed according to the JEDEC standard (vielding a thermal resistance of 34C/W), with no nearby heat sources, and no airflow. Reference Voltage The A8589 incorporates an internal reference that allows output voltages (VOUT) as low as 0.8V. The accuracy of the internal reference is 1.0% from 0C to 85C and 1.5% from -40C to 150C. The output voltage is programmed by connecting a resistor divider from VOUT to the FB pin of the A8589, as shown in the Typical Applications schematics. PWM Switching Frequency The PWM switching frequency of the A8589 is adjustable from 250kHz to 2.4MHz and has an accuracy of about 10% across the operating temperature range. During startup, the PWM switching frequency changes from 25% to 50% and finally to 100% of fOSC, as VOUT rises from 0V to the regulation voltage. The startup switching frequency is discussed in more detail in the section describing soft start, below. If the regulator output is shorted to ground, VFB 0V, the PWM frequency will be 25% of fOSC. In this case, the extra low switching frequency allows extra off-time between SW pulses. The extra off-time allows the output inductor current to decay back to 0A before the next SW pulse occurs. This prevents the inductor current from climbing to a value that could damage the A8589 or the output inductor. SLEEPn Input VIN = 12 V, VOUT = 5 V, fSW = 2 MHz VIN = 12 V, VOUT = 5 V, fSW = 425 kHz VIN = 12 V, VOUT = 3.3 V, fSW = 2 MHz VIN = 12 V, VOUT = 3.3 V, fSW = 425 kHz Figure 1: A8589 Typical Current Derating The A8589 has a SLEEPn logic level input pin. To get the A8589 to operate, the SLEEPn pin must be a logic high (>2.1V). The SLEEPn pin is rated to 40V, allowing the SLEEPn pin to be connected directly to VIN if there is no suitable logic signal available to wake up the A8589. When SLEEPn transitions low, the A8589 waits approximately 103s before shutting down. This delay provides plenty of filtering to prevent the A8589 from prematurely entering sleep mode because of any small glitch coupling onto the PCB trace or SLEEPnpin. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 12 Wide Input Voltage, 2.4MHz, 2.5A Asynchronous Buck Regulator With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output A8589 PWM/PFMn Input and PWM Synchronization The PWM/PFMn pin provides two major functions. It is a control input that sets the operating mode, and also an optional clock input for setting PWM frequency. If PWM/PFMn is a logic high, the A8589 operates in PWM mode. If PWM/PFMn is a logic low, the A8589 operates in LowIQPFM (keep alive) mode. When PWM/PFMn transitions from logic high to logic low, the A8589 checks for VSS>2.3V and NPOR at logic high. If these two conditions are satisfied, then the A8589 will wait 2048 internal clock cycles and then enter LowIQPFM mode. This delay provides plenty of filtering to prevent the regulator from prematurely entering PFM mode because of any small glitch coupling onto the PCB trace or PWM/PFMnpin. Also, note that the SLEEPn pin must be a logic high or the PWM/PFMn input has no effect. The interaction between the SLEEPn pin and PWM/PFMn pin is summarized in Table 1. If an external clock is applied to the PWM/PFMn pin, the A8589 synchronizes its PWM frequency to the external clock. The external clock may be used to increase the A8589 base PWM frequency (fOSC) set by RFSET. Synchronization operates from 1.2x fOSC(typ) to 1.5x fOSC(typ). The external clock pulses must satisfy the pulse width, duty cycle, and rise/fall time requirements shown in the Electrical Characteristics table in this datasheet. Table 1: A8589 Modes of Operation Pin Inputs Operating Mode SLEEPn PWM/PFMn Name Description Low Don't care Sleep VOUT = 0 V High High fSW = fOSC PWM High fSW = PWM/PFMn clock in VOUT = OK and IOUT 2.5A Enter LowIQPFM after 2048 cycles, if VSS > 2.3V (typ) and NPOR = high High High Low LowIQPFM High Low LowIPPWM fSW is VOUT dependent BIAS Input Functionality, Ratings, and Connections When the A8589 is powering up, it operates from an internal LDO regulator, directly from VIN. However, VIN can be a relatively high voltage and an LDO is very inefficient and generates extra heat. To improve efficiency, especially in LowIQPFM mode, a BIAS pin is utilized. For most applications, the BIAS pin should be connected directly to the output of the regulator, VOUT. When VOUT rises to an adequate level (approximately 3.1V), the A8589 will shut down the inefficient LDO and begin running its control circuitry directly from the output of the regulator. This makes the A8589 much more efficient and cooler. The BIAS pin is designed to operate in the range from 3.2to5.5V. If the output of the regulator is in this range then VOUT should be routed directly to the BIAS pin. However, if the output of the regulator is above 5.6V then a very small LDO, capable of at least 5mA, must be used to reduce the voltage to either 3.3V or 5.0V before routing it to the BIAS pin. Operating with an external LDO will reduce the efficiency in LowIQPFMmode. The BIAS pin may be driven by an external power supply. For startup, there are no sequencing requirements between VIN and BIAS. However, for shutdown, VIN should be removed before BIAS. If BIAS is removed before VIN it will cause the A8589 to reset. The reset will cause the A8589 to terminate PWM switching and VOUT will decay. Also, NPOR, VSS, and VCOMP will be pulled low. Ideally, the SLEEPn pin should be used to set the mode of the A8589 before VIN and/or BIAS are turned on or off. If the BIAS pin is grounded, the A8589 will simply operate continuously from VIN. However, during PFM mode, the input current will increase and the PFM efficiency will be significantly reduced. 400 mV Fault, ILIM at 50% Error Amplifier SS Pin VOUT = OK and IOUT 550mA (typ) + + VREF 800 mV - COMP Pin FB Pin Figure 2: The A8589 Error Amplifier Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 13 A8589 Wide Input Voltage, 2.4MHz, 2.5A Asynchronous Buck Regulator With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output Transconductance Error Amplifier Power MOSFETs The transconductance error amplifier primary function is to control the regulator output voltage. The error amplifier is shown in Figure 2. Here, it is shown as a three-terminal input device with two positive and one negative input. The negative input is simply connected to the FB pin and is used to sense the feedback voltage for regulation. The two positive inputs are used for soft start and steady-state regulation. The error amplifier performs an analog OR selection between its two positive inputs. The error amplifier regulates to either the soft start pin voltage (minus 400 mV) or the A8589 internal reference, VREF, whichever is lower. The A8589 includes a 40V, 110m high-side N-channel MOSFET, capable of delivering at least 2.5A. The A8589 also includes a 10, low-side MOSFET to help ensure the BOOT capacitor is always charged. The typical RDS(on) increase versus temperature is shown in Figure 3. If a fault occurs or the regulator is disabled (SLEEPn = low), the COMP pin is pulled to GND via approximately 1k and PWM switching is inhibited. Slope Compensation The A8589 incorporates internal slope compensation (SE) to allow PWM duty cycles above 50% for a wide range of input/output voltages and inductor values. The slope compensation signal is added to the sum of the current sense amplifier output and the PWM ramp offset. As shown in the Electrical Characteristics table, the amount of slope compensation scales with the base switching frequency set by RFSET (fOSC). The amount of slope compensation does not change when the regulator is synchronized to an external clock. The value of the output inductor should be chosen such that SE is from 0.5x to 1x the falling slope of the inductor current (SF). Current Sense Amplifier The A8589 incorporates a high-bandwidth current sense amplifier to monitor the current in the high-side MOSFET. This current signal is used by both the PWM and PFM control circuitry to regulate the peak current. The current signal is also used by the protection circuitry to prevent damage to the A8589. The A8589 contains a regulator to charge the boot capacitor. The voltage across the BOOT capacitor is typically 5.0V. If the BOOT capacitor is missing, the A8589 detects a boot overvoltage. Similarly, if the BOOT capacitor is shorted the A8589 detects a boot undervoltage. Also, the BOOT regulator has a current limit to protect itself during a short circuit condition. The details of how each type of boot fault is handled by the A8589 are shown in Figures 13 and 14 and summarized in Table 2. Pulse Width Modulation (PWM) Mode The A8589 utilizes fixed-frequency, peak current mode control to provide excellent load and line regulation, fast transient response, and ease of compensation. A high-speed comparator and control logic, capable of typical pulse widths of 95ns, are included in the A8589. The inverting input of the PWM comparator is connected to the output of the error amplifier. The non-inverting input is connected to the sum of the current sense signal, the slope compensation, and a DC offset voltage (VPWMOFFS, 400mV (typ) ). At the beginning of each PWM cycle, the CLK signal sets the PWM flip flop and the high-side MOSFET is turned on. When the summation of the DC offset, slope compensation, and current sense signal rises above the error amplifier voltage, the PWM flip flop is reset and the high-side MOSFET is turned off. Normalized RDS(on) To stabilize the regulator, a series RC compensation network (RZ and CZ) must be connected from the error amplifier output (the COMP pin) to GND, as shown in the Typical Applications schematics. In most instances an additional, relatively low value, capacitor (CP) should be connected in parallel with the RZ-CZ components to reduce the loop gain at very high frequencies. However, if the CP capacitor is too large, the phase margin of the regulator may be reduced. Calculating RZ, CZ, and CP is covered in detail in the Component Selection section of thisdatasheet. BOOT Regulator Temperature (C) Figure 3: Typical MOSFET RDS(on) versus Temperature Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 14 Wide Input Voltage, 2.4MHz, 2.5A Asynchronous Buck Regulator With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output A8589 The PWM flip flop is reset-dominant, so the error amplifier may override the CLK signal in certain situations. For example, at very light loads or extremely high input voltages the error amplifier reduces (temporarily) output voltage below the 400mV DC offset and the PWM flip flop will ignore one or more of the incoming CLK pulses. The high-side MOSFET will not turn on, and the regulator will skip pulses to maintain output voltage regulation. In PWM mode all of the A8589 fault detection circuits are active. See Figure 13 for a timing diagram showing how faults are handled when in PWM mode. Also, the Protection Features section of this datasheet provides a detailed description of each fault and Table 2 presents a summary. ing frequency. Utilizing the extended duty cycle technique, the A8589 can achieve typical drop out duty cycles of greater than 95% in 2MHz designs. Low-IQ Pulse Frequency Modulation (PFM) Mode The A8589 enters LowIQPFM mode after 2048 internal clock cycles, if SLEEPn is high, VSS > HIC/PFMEN (2.3V (typ)), and NPOR is high. In Low-IQ PFM mode, the regulator operates with a switching frequency, fSW, that depends on the load condition. Maximized Duty Cycle Control In Low-IQ PFM mode, a comparator monitors the voltage at the FB pin. If VFB is above about 800mV, the A8589 remains in coast mode and draws extremely low current from the input supply. Most fixed frequency PWM controllers have limited maximum duty cycle. This is due to the off-time required to keep the BOOT capacitor charged in order to drive the high-side N-channel MOSFET. This limitation becomes significant in high-frequency, lowinput voltage regulators. It may cause the output voltage to drop out of regulation during stop/start profiles in automotive designs. If the voltage at the FB pin drops below about 800mV, the A8589 will fully power-up, delay approximately 2.5s while it wakes up, and then turn on the high-side MOSFET. VOUT will rise at a rate dependent on the input voltage, inductor value, output capacitance, and load. The high-side MOSFET will be turned off when either: The A8589 employs a technique that helps extend the maximum duty cycle during drop out conditions. Without this technique the typical maximum duty cycle would be 74% at 2MHz switch- * current in the high-side MOSFET reaches IPEAK(LO_IQ), or * the high-side MOSFET has been on for tON(PFM)MAX. After the high-side MOSFET is turned off, the A8589 will again VOUT 3.3 V VOUT 3.3 V 18.5 s tOFF(PFM) = 435 ns VSW VSW IPEAK(LO_IQ) IIPEAK(LO_IQ) PEAK(LO_IQ) IL Figure 4. Low-IQ PFM Mode Operation at VIN = 12V, VOUT = 3.3V, and IOUT = 66mA. SW turns on only once every 18.5s to regulate VOUT IL Figure 5. Low-IQ PFM Mode Operation at VIN = 12V, VOUT = 3.3V, and IOUT = 330mA. SW turns on only twice every 5s to regulate VOUT Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 15 Wide Input Voltage, 2.4MHz, 2.5A Asynchronous Buck Regulator With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output A8589 VOUT B D Overall Waveforms C A E IOUT VPWM/PFMn VOUT VOUT B C A IOUT IOUT VPWM/PFMn VPWM/PFMn Time A: Transition from PWM to PFM at 250 mA Time B: Load steps from 250 mA to 0 A in Low-IQ PFM mode VOUT Time C: Load steps from 0 A to 100 mA and back to 0 A in Low-IQ PFM mode VOUT D IOUT E IOUT VPWM/PFMn Time D: Load steps from 0 A to 250 mA in Low-IQ PFM mode VPWM/PFMn Time E: Transition from Low-IQ PFM to PWM mode at 250 mA Figure 6: Transitions between PWM Mode and Low-IQ PFM Mode, and Load Transient Responses; using circuit in typical application schematic B (VIN = 12V, VOUT = 5V, fSW = 425kHz) Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 16 A8589 Wide Input Voltage, 2.4MHz, 2.5A Asynchronous Buck Regulator With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output delay approximately tOFF(PFM) and either: (high precision comparators, timers, and counters). * turn on the MOSFET again, if VFB < 800mV, or * return to the Low-IQ PFM mode Figures 4 and 5 demonstrate Low-IQ PFM mode operation for a light load (66mA) and a heavy load (330mA), respectively. There are several faults that cause a transition from Low-IQ PFM to Low-IP PWM mode: a missing asynchronous diode, an open or shorted boot capacitor, VOUT shorted to ground, or SW shorted to ground. See Figure 14 for a timing diagram showing operation when the A8589 transitions from Low-IQPFM mode to Low-IP PWM mode. In Low-IQ PFM mode the average current drawn from the input supply depends primarily on both the load, and how often the A8589 must fully power-up to maintain regulation. In Low-IQ PFM mode the following faults are detected: a missing asynchronous diode, an open or shorted boot capacitor, VOUT shorted to ground, and SW shorted to ground. As described in the next section, if any of these faults occur the A8589 will transition from Low-IQ PFM mode to Low-IP PWM mode, with operation at 50% of the current limit of the PWM switching mode. See Figure 14 for a timing diagram showing operation of the A8589 in LowIQPFM mode. In LowIQPFM mode the A8589 dissipates very little power, so the thermal monitoring circuit (TSD) is not needed and is disabled to minimize the quiescent current and improve efficiency. Figure 6 shows PWM to LowIQPFM transitions for a typical microcontroller or DSP system. The system starts in PWM mode at IOUT = 250mA and then transitions to LowIQPFM mode, also at IOUT = 250mA (time A). While in LowIQPFM mode the current drops from 250mA to 0A (time B) and also cycles from no load to 100mA (time C). In Low-IQ PFM mode the load steps from IOUT = 0A to 250mA (time D) and then the A8589 transitions back to PWM mode (time E). For this example, the output ripple voltage is always less than 30mVPP and the transient deflection between modes is always less than 50mVPEAK. Soft Start (Startup) and Inrush Current Control Inrush current is controlled by a soft start function. When the A8589 is enabled and all faults are cleared, the soft start pin will source ISSSU and the voltage on the soft start capacitor, CSS, will ramp upward from 0V. When the voltage at the soft start pin exceeds approximately 400mV, the error amplifier will slew its output voltage above the PWM Ramp Offset (VPWMOFFS). At that instant, the high-side and low-side MOSFETs will begin switching. As shown in Figure 7, there is a small delay (tD(SS)) between when the enable pin transitions high, and when both the soft start voltage exceeds 400mV and the error amplifier slews its output high enough to initiate PWM switching. After the A8589 begins switching, the error amplifier will regulate the voltage at the FB pin to the soft start pin voltage minus approximately 400mV. During the active portion of soft start, VSLEEPn tD(SS) 3.3 V tSS VSS=1.2 V Reduced Current (Low-IP) PWM Mode The A8589 supports two different levels of current limiting in PWM modes: * 100% current, which is during normal PWM, and * Low-IP, in which the current is limited to about 50% of the typical current limit The Low-IP PWM mode is invoked when the A8589 is supposed to be in PFM mode but a fault occurs. The purpose of the Low-IP PWM mode is to give priority to maintaining reliable regulation of VOUT while enabling all the protection circuits inside the A8589 that are normally debiased during Low-IQ PFM mode VOUT VCOMP VSS = 400 mV fSW VSS IL fSW/4 fSW/2 Figure 7: Normal Startup to VOUT = 3.3V and IOUT = 1.6A; PWM/PFMn Pin = high, SLEEPn Pin Transitions from Low to High Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 17 Wide Input Voltage, 2.4MHz, 2.5A Asynchronous Buck Regulator With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output A8589 the voltage at the soft start pin rises from 400mV to 1.2V (a difference of 800mV), the voltage at the FB pin rises from 0V to 800mV, and the regulator output voltage rises from 0V to the targeted setpoint, which is determined by the feedback resistor divider on the FB pin. During startup, the PWM switching frequency is reduced to 25% of fOSC while VFB is below 200mV. If VFB is above 200mV but below 400mV, the switching frequency is reduced to 50% of fOSC. Also, if VFB is below 400mV, the gm of the error amplifier is reduced to gm / 2. When VFB is above 400mV the switching frequency will be fOSC and the error amplifier gain will be gm. The reduced switching frequencies and error amplifier gain are necessary to help improve output regulation and stability when VOUT is at a very low voltage. When VOUT is very low, the PWM control loop requires on-times near the minimum controllable on-time, as well as extra-low duty cycles that are not possible at the base operating switching frequencies. When the voltage at the soft start pin reaches approximately 1.2V, the error amplifier will change mode and begin regulating the voltage at the FB pin to the A8589 internal reference, 800mV. The voltage at the soft start pin will continue to rise to approximately VREG. Complete soft start operation from VOUT = 0V is shown in Figure 7. VSLEEPn VOUT rises from 1.6 V, it is not pulled to 0 V VOUT If the output of the regulator (VOUT) is pre-biased to some voltage, the A8589 will modify the normal startup routine to prevent discharging the output capacitors. As described previously, the error amplifier usually becomes active when the voltage at the soft start pin exceeds 400mV. If the output is pre-biased, the FB pin will be at some non-zero voltage. The A8589 will not start switching until the voltage at the soft start pin increases to approximately VFB + 400mV. When the soft start pin voltage exceeds this value: the error amplifier becomes active, the voltage at the COMP pin rises, PWM switching starts, and VOUT ramps upward from the pre-bias level. Figure 8 shows startup when the output voltage is pre-biased to 1.6V. VSS=1.2 V Switching delayed until VSS = VFB +400 mV VSS = 400 mV VIN = 2.2 V VIN VNPOR VCOMP IL Pre-Biased Startup 3.3 V 1.6 V VSS If the A8589 is disabled or a fault occurs, the internal fault latch will be set and the capacitor on the soft start pin will be discharged to ground very quickly by an internal 2k pull-down resistor. The A8589 will clear the internal fault latch when the voltage at the soft start pin decays to approximately 200mV (VSSRST). Conversely, if the A8589 enters hiccup mode, the capacitor on the soft start pin is slowly discharged by a current sink, ISSHIC. Therefore, the soft start capacitor (CSS) not only controls the startup time but also the time between soft start attempts in hiccup mode. Hiccup mode operation is discussed in more detail in the Protection Features section of this datasheet. fSW fSW/2 Figure 8: Pre-biased Startup from VOUT = 1.6V to VOUT = 3.3V, at IOUT = 1.6A Figure 9: Initialization of NPOR as VIN Ramps Up Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 18 Wide Input Voltage, 2.4MHz, 2.5A Asynchronous Buck Regulator With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output A8589 Not Power-On Reset (NPOR) Output The A8589 has an inverted power-on reset output (NPOR) with a fixed delay of its rising edge (tD(NPOR)). The NPOR output is an open drain output so an external pull-up resistor must be used, as shown in the Typical Applications schematics. NPOR transitions high when the output voltage (VOUT), sensed at the FB pin, is within regulation. In PWM mode, NPOR is high when the output voltage is typically within 92.5% to 110% of the target value. In PFM mode, NPOR is high when the output voltage is typically above 87.5% of the target value. The NPOR overvoltage and undervoltage comparators incorporate a small amount of hysteresis (10mV typically) and filtering (5s typically) to help reduce chattering due to voltage ripple at the FB pin. The NPOR output is immediately pulled low either: if an output overvoltage or an undervoltage condition occurs, or if the A8589 junction temperature exceeds the thermal shutdown threshold (TSD). For other faults, NPOR behavior depends on the output voltage. Table 2 summarizes all the A8589 fault modes and their effect on NPOR. At power-up, NPOR must be initialized (set to a logic low) when VIN is relatively low. Figure 9 shows VIN ramping up, and also NPOR being set to a logic low when VIN is only 2.2V. For this test, NPOR was pulled up to an external 3.3V supply via a 2kresistor. At power-down, NPOR must be held in the logic low state as long as possible. Figure 10 shows VIN ramping down and also NPOR being held low until VIN is only 1.3V. For this test, NPOR was pulled up to an external 3.3V supply via a 2k resistor. Protection Features The A8589 was designed to satisfy the most demanding automotive and non-automotive applications. In this section, a description of each protection feature is described and Table 2 summarizes the protection features and operation. UNDERVOLTAGE LOCKOUT (UVLO) An undervoltage lockout (UVLO) comparator monitors the voltage at the VIN pin and keeps the regulator disabled if the voltage is below the stop threshold (VINUV(OFF)). The UVLO comparator incorporates some hysteresis (VINUV(HYS)) to help reduce on-off cycling of the regulator due to resistive or inductive drops in the VIN path during heavy loading or during startup. PULSE-BY-PULSE OVERCURRENT PROTECTION (OCP) The A8589 monitors the current in the high-side MOSFET and if the current exceeds the pulse-by-pulse overcurrent threshold (ILIM) then the high-side MOSFET is turned off. Normal PWM operation resumes on the next clock pulse from the internal oscillator. The A8589 includes leading edge blanking to prevent falsely triggering the pulse-by-pulse current limit when the highside MOSFET is turned on. Because of the addition of the slope compensation ramp to the 4.6 4.4 4.2 4.0 VIN 3.8 ILIM (A) VIN = 1.3 V VNPOR 3.6 3.4 3.2 3.0 Min. at at 2.45 2.45 MHz MHz Min. 2.8 Typ Typ.atat2.45 2.45MHz MHz 2.6 MAX_2.45 MHz Max. at 2.45 MHz 2.4 TYP_250 kHz Typ. at 250 kHz 2.2 MIN_250 kHz Min. at 250 kHz MAX_250 kHz Max. at 250 kHz 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 Duty Cycle (%) Figure 10: NPOR being Held Low as VIN Ramps Down Figure 11: Pulse-by-pulse Current Limiting versus Duty Cycle; at fSW = 250 kHz (dashed curves) and fSW = 2.45MHz (solid curves) Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 19 Wide Input Voltage, 2.4MHz, 2.5A Asynchronous Buck Regulator With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output A8589 inductor current, the A8589 delivers more current at lower duty cycles and less current at higher duty cycles. Also, the slope compensation is not a perfectly linear function of switching frequency. For a given duty cycle, this results in a little more current being available at lower switching frequencies than higher frequencies. Figure 11 shows the typical and worst case min/max pulse-by-pulse current limits versus duty cycle at fSW=250kHz and 2.45MHz. If the synchronization input (PWM/PFMn) is used to increase the switching frequency, the on-time and the current ripple will decrease. This will allow slightly more current than at the base switching frequency (fOSC). The exact current the buck regulators can support is heavily dependent on: duty cycle (VIN, VOUT, Vf), ambient temperature, thermal resistance of the PCB, airflow, component selection, and nearby heat sources. OVERCURRENT PROTECTION (OCP) AND HICCUP MODE An OCP counter and hiccup mode circuit protect the buck regulator when the output of the regulator is shorted to ground or when the load is too high. When the voltage at the soft start pin is below the hiccup OCP threshold (HIC/PFMEN) the hiccup mode counter is disabled. Two conditions must be met for the OCP counter to be enabled and begin counting: * VSS > HIC/PFMEN (2.3 V (typ)) and * VCOMP is clamped at its maximum voltage (OCL =1) As long as these two conditions are met, the OCP counter remains enabled and will count pulses from the overcurrent comparator. If the COMP pin voltage decreases (OCL = 0) the OCP counter is cleared. If the OCP counter reaches OCPLIM counts (120), a hiccup latch is set and the COMP pin is quickly pulled down by a relatively low resistance (1k). The hiccup latch also enables a small current sink connected to the soft start pin (ISSHIC). This causes the voltage at the soft start pin to slowly ramp downward. When the voltage at the soft start pin decays to a low enough level (VSSRST, 200mV (typ)) the hiccup latch is cleared and the small current sink turned off. At that instant, the soft start pin will begin to source current (ISSSU) and the voltage at the soft start pin will ramp upward. This marks the beginning of a new, normal soft start cycle as described earlier. (Note: OCP is the only fault that results in hiccup mode that is ignored when VSS < 2.3V.) When the voltage at the soft start pin exceeds the soft start offset (typically 400mV) the error amplifier forces the voltage at the COMP pin to quickly slew upward and PWM switching will resume. If the short circuit at the regulator output remains, another hiccup cycle will occur. Hiccups will repeat until the short circuit is removed or the regulator is disabled. If the short circuit is removed, the A8589 will soft start normally and the output voltage will automatically recover to the target level, as shown in Figure 12. BOOT CAPACITOR PROTECTION VCOMP VSS IL The A8589 monitors the voltage across the BOOT capacitor to detect if the capacitor is missing or short circuited. If the BOOT capacitor is missing, the regulator will enter hiccup mode after 7PWM cycles. If the BOOT capacitor is short circuited, the regulator will enter hiccup mode after 120PWM cycles, provided there is no VOUT overvoltage detection. At no load or very light loads, the boot charging circuit will increase the output voltage (via the output inductor) and cause an overvoltage condition to be detected if VIN > VOUT + 5.7V. Short removed VOUT 120 OCP counts 2.3 V ILIM(TONMIN) 200 mV For a boot fault, hiccup mode will operate virtually the same as described previously for an output short circuit fault (OCP) with the soft start pin ramping up and down as a timer to initiate repeated soft start attempts. Boot faults are a non-latched condition, so the A8589 will automatically recover when the fault is corrected. Figure 12. Hiccup Mode Operation and Recovery to VOUT = 3.3V, IOUT = 1.6A Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 20 A8589 Wide Input Voltage, 2.4MHz, 2.5A Asynchronous Buck Regulator With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output ASYNCHRONOUS DIODE PROTECTION If the asynchronous diode (D1 in the Typical Applications schematics) is missing or damaged (open) the SW pin will be subject to unusually high negative voltages. These negative voltages may cause the A8589 to malfunction and could lead to damage. The A8589 includes protection circuitry to detect when the asynchronous diode is missing. If the SW pin is below typically -1.25V for more than about 50ns, the A8589 will enter hiccup mode after detecting one missing diode fault. Also, if the asynchronous diode is short circuited, the A8589 will experience extremely high currents in the high-side MOSFET. If this occurs the A8589 will enter hiccup mode after detecting one short circuited diode fault. OUTPUT OVERVOLTAGE PROTECTION (OVP) The A8589 provides a basic level of overvoltage protection by monitoring the voltage level at the FB pin. Two overvoltage conditions can be detected: * The FB pin is disconnected from its feedback resistor divider. In this case, a tiny internal current source forces the voltage at the FB pin to rise. When the voltage at the FB pin exceeds the overvoltage threshold (VOUT(OV)PWM, 880mV (typ)) PWM switching will stop and NPOR will be pulled low. * A higher, external voltage supply is accidently shorted to the A8589s output. VFB will probably rise above the overvoltage threshold and be detected as an overvoltage condition. In this case, the low-side MOSFET will continue to operate and can correct the OVP condition, provided that only a few milliamperes of pull-down current are required. In either case, if the condition causing the overvoltage is corrected the regulator will automatically recover. PIN-TO-GROUND AND PIN-TO-PIN SHORT PROTECTIONS The A8589 is designed to satisfy the most demanding automotive applications. For example, the A8589 has been carefully designed from the very beginning to withstand a short circuit to ground at each pin without suffering damage. In addition, care was taken when defining the A8589 pin-out to optimize protection against pin-to-pin adjacent short circuits. For example, logic pins and high voltage pins are separated as much as possible. Inevitably, some low voltage pins are located adjacent to high voltage pins, but in these instances the low voltage pins are designed to withstand increased voltages, with clamps and/or series input resistance, to prevent damage to the A8589. THERMAL SHUTDOWN (TSD) The A8589 monitors junction temperature and will stop PWM switching and pull NPOR low if it becomes too hot. Also, to prepare for a restart, the soft start and COMP pins will be pulled low until VSS < VSS(RST). TSD is a non-latched fault, so the A8589 will automatically recover if the junction temperature decreases by approximately 20C. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 21 Wide Input Voltage, 2.4MHz, 2.5A Asynchronous Buck Regulator With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output A8589 TABLE 2: Summary of A8589 Fault Modes and Operation During fault counting, before Hiccup mode Fault Mode VSS VCOMP High-Side MOSFET Low-Side MOSFET BOOT Charging NPOR State Output overcurrent, VFB< 200mV Hiccup, after 120 OCP faults Clamped for ILIM, then pulled low for hiccup fOSC / 4 due to VFB < 200mV, responds to VCOMP Can be activated if VBOOT is too low Not affected Depends on VOUT No Automatic, after remove the short Output overcurrent, VFB > 400mV Hiccup, after 120 OCP faults Clamped for ILIM, then pulled low for hiccup fOSC due to VFB > 400 mV, responds to VCOMP Can be activated if VBOOT is too low Not affected Depends on VOUT No Automatic, after decrease load current Boot capacitor open/missing (BOOTOV) Hiccup, after 7BOOTOV faults Pulled low for hiccup Forced off when BOOTOV fault occurs Forced off when BOOT fault occurs Off after BOOT fault occurs Depends on VOUT No Automatic, after replace capacitor Boot capacitor shorted (BOOTUV) Hiccup, after 120 BOOTUV faults Not affected, pulled low for hiccup Forced off when BOOTUV fault occurs Forced off only during hiccup Off only during hiccup Depends on VOUT No Automatic, after unshort capacitor Asynchronous diode missing Hiccup after 1fault Pulled low for hiccup Forced off after 1 fault Can be activated if VBOOT is too low Not affected Depends on VOUT No Automatic, after install diode Asynchronous diode (or SW) hard short to ground Hiccup after 1fault Pulled low for hiccup Forced off after 1 fault Can be activated if VBOOT is too low Not affected Depends on VOUT No Automatic, after remove short Asynchronous diode (or SW) soft short to ground Hiccup, after 120 OCP faults Clamped for ILIM, then pulled low for hiccup Active, responds to VCOMP Can be activated if VBOOT is too low Not affected Depends on VOUT No Automatic, after remove short FB pin open (FB floats high) Begins to ramp up for soft start Transitions low via loop response Forced off by low VCOMP Active during tOFF(MIN)PWM Off when VFB is too high Pulled low when VFB is too high No Automatic, after connect FB pin Output overvoltage (VFB > 880mV) Not affected Transitions low via loop response Forced off by low VCOMP Active during tOFF(MIN)PWM Off when VFB is too high Pulled low when VFB is too high No Automatic, after VFB returns to normal range Output undervoltage Not affected Transitions high via loop response Active, responds to VCOMP Can be activated if VBOOT is too low Not affected Pulled low when VFB is too low No Automatic, after VFB returns to normal range Thermal shutdown Pulled low and latched until VSS < VSSRST Pulled low and latched until VSS < VSSRST Forced off by low VCOMP Disabled Off Pulled low No Automatic, after part cools down Not affected Transitions low via loop response Forced off by low VCOMP Active during tOFF(MIN)PWM No Automatic, VREG or BIAS to normal range VREG or BIAS overvoltage (REGOV) Off Pulled low Latched? Reset Condition Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 22 A8589 Wide Input Voltage, 2.4MHz, 2.5A Asynchronous Buck Regulator With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output Figure 13: Operation with SLEEPn = high and PWM/PFMn = high (PWM mode) Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 23 COMP SS VOUT SW VIN DIODE FAULT BOOT FAULT OC FAULT HICCUP OC HIC_EN NPOR TSD PWM/ PFMn SLEEPn MODE OFF HICCUP Vout shorted to GND OC SS ~500 mV FSW /4 x120 Note: NPOR=1 already, so VSS>HIC/PFMEN starts the 2048 PFM delay counter 2048 LO_IQ SS>2.3V * FB>0.74V FSW 7.5ms PWM FSW/4 then FSW/2 SS FSW/4 OC x120 LOW-IP PWM HICCUP FSW/4 then FSW/2 SS SS>2.3V * FB>0.74V FSW 7.5ms 2048 ~500 mV LO_IQ x7 OV x120 UV BOOT FAULTS HICCUP TO 2.3V FSW/4 FROM 2.3V HICC UP TO 2.3 V FROM 2 .3V FSW/4 x7 OV x120 UV HICC S UP S LOW-IP PWM x7 OV x120 UV S S FSW/4 then FSW/2 SS SS>2.3V * FB>0.74V FSW 7.5ms 2048 HICCUP ~500 mV x1 DIODE or SW FAULTS LO_IQ x1 FSW/4 SS HI C SS 7.5ms 2048 LO_IQ PWM SS>2.3V * FB>0.74V FSW/4 then FSW FSW/2 ~500 mV FSW Note: Faster SS shown here, so NPOR starts the 2048 PFM delay counter, instead of VSS TO FROM TO FROM 2.3V 2.3V 2.3V 2 .3V FSW/4 x1 HI C LOW-IP PWM SS A8589 Wide Input Voltage, 2.4MHz, 2.5A Asynchronous Buck Regulator With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output Figure 14: Operation with SLEEPn = high and PWM/PFMn = low (Low-IQ PFM mode and transition to Low-IP PWM mode) Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 24 Wide Input Voltage, 2.4MHz, 2.5A Asynchronous Buck Regulator With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output A8589 APPLICATION INFORMATION Design and Component Selection SETTING THE OUTPUT VOLTAGE (VOUT) The output voltage of the regulator is determined by connecting a resistor divider from the output node (VOUT) to the FB pin as shown in Figure 15. There are trade-offs when choosing the value of the feedback resistors. If the series combination (RFB1 + RFB2) is too low, then the light load efficiency of the regulator will be reduced. So to maximize the efficiency, it is best to choose higher values of resistors. On the other hand, if the parallel combination (RFB1 // RFB2) is too high, then the regulator may be susceptible to noise coupling onto the FB pin. The feedback resistors must satisfy the ratio shown in the following equation to produce the target output voltage, VOUT: VOUT -1 0.8 (V) Figure 15: Connecting a Feedback Resistor Divider to Set the Output Voltage CFB (1) Compared to typical buck regulators, a PFM capable buck regulator presents some unique challenges when determining its feedback divider. This resistor divider must draw minimal current from VOUT or it will reduce the efficiency during LowIQPFM operation. With this in mind, Allegro recommends the resistor values show in Table 3 on page 34. For LowIQPFM mode, a feedforward capacitor (CFB) should be connected in parallel with RFB1, as shown in Figure 16. The purpose of this capacitor is to offset any stray capacitance (CSTRAY) from the FB pin to ground. Without CFB, the stray capacitance and the relatively high resistor values used for the feedback network form a low pass filter and introduce lag to the LowIQPFM feedback path. The feedforward capacitor helps to maintain sensitivity during LowIQPFM mode and to assure the output voltage ripple is minimized. In general, CFB should be calculated as: CFB > (1.5 x CSTRAY) x (RFB2 / RFB1)(2) where CSTRAY is typically 15 to 25pF. PWM BASE SWITCHING FREQUENCY (FOSC, RFSET) The PWM base switching frequency, fOSC, is set by connecting a resistor from the FSET pin to ground. Figure 17 is a graph show- FB PIN RFB2 RFB1 V OUT FB PIN RFB2 CSTRAY 15 to 25 pF Figure 16: Addition of CFB to Cancel Stray Capacitance at the FB Pin in PFM Mode 2.50 2.25 2.00 1.75 Frequency (MHz) RFB1 = RFB2 RFB1 V OUT 1.50 1.25 1.00 0.75 0.50 0.25 0.00 5.0 15.0 25.0 35.0 45.0 55.0 65.0 75.0 85.0 95.0 RFSET (k) Figure 17: PWM Switching Frequency versus RFSET Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 25 Wide Input Voltage, 2.4MHz, 2.5A Asynchronous Buck Regulator With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output A8589 ing the relationship between the typical switching frequency and the FSET resistor. The base frequency is the output frequency, fSW, when PWMPFMn is high (no external clocking signal). For a given base switching frequency (fOSC), the FSET resistor can be calculated as follows: RFSET = 26385 - 2.75 fOSC (3) where fOSC is in kHz and RFSET is in k. When the PWM base switching frequency is chosen the designer should be aware of the minimum controllable on-time, tON(MIN)PWM of the A8589. If the system required on-time is less than the A8589 minimum controllable on-time, switch node jitter occurs and the output voltage will have increased ripple or oscillations. The PWM base switching frequency required should be calculated as follows: fOSC < VOUT tON(MIN)PWM x VIN(MAX)REQ (4) slope compensation in the A8589 is a fixed value (SE). Therefore, it is important to calculate an inductor value such that the falling slope of the inductor current (SF) will work well with the A8589 slope compensation. The following equation can be used to calculate a range of values for the output inductor based on the well known approach of providing slope compensation that matches 50% to 100% of the falling slope of the inductor current: VOUT + Vf 2 x SE tON(MIN)PWM is the minimum controllable on-time of the A8589 (95ns (typ), 135ns (max)), and VIN(MAX)REQ is the maximum required operational input voltage (not the peak surge voltage). If the A8589 PWM synchronization function is employed, then the base switching frequency should be chosen such that jitter will not result at the maximum synchronized switching frequency, determined from equation 4: fOSC < 0.66 x VOUT tON(MIN)PWM x VIN(MAX)REQ (5) OUTPUT INDUCTOR (LO) For a peak current mode regulator it is common knowledge that, without adequate slope compensation, the system will become unstable when the duty cycle is near or above 50%. However, the VOUT + Vf SE (6) where Vf is the forward voltage of the asynchronous diode, and LO is in H. In equation 6, the slope compensation (SE ) is a function of switching frequency according the following: SE = 0.23 x fOSC2 + 0.63 x fOSC + 0.038 (7) where SE is in A/s and fOSC is in MHz. More recently, Dr. Raymond Ridley presented a formula to calculate the amount of slope compensation required to critically damp the double poles at half the PWM switching frequency: where VOUT is the output voltage, LO LO VOUT+Vf SE 1 - 0.18 D = VOUT+Vf SE 1 - 0.18 x (VIN(min)+Vf ) VOUT+Vf (8) This formula allows the inclusion of the duty cycle (D), which should be calculated at the minimum input voltage to insure optimal stability. Also, to avoid dropout (that is, saturation of the buck regulator), VIN(min) must be approximately 1 to1.5V above VOUT when calculating the inductor value with equation8. If equations 7 or 8 yield an inductor value that is not a standard value, then the next highest available value should be used. The final inductor value should allow for 10% to 20% of initial tolerance and 20% to 30% of inductor saturation. The saturation current of the inductor should be higher than the peak current capability of the A8589. Ideally, for output short circuit conditions, the inductor should not saturate even at the highest pulse-by-pulse current limit at minimum duty cycle, 4.6A. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 26 Wide Input Voltage, 2.4MHz, 2.5A Asynchronous Buck Regulator With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output A8589 This may be too costly. At the very least, the inductor should not saturate at the peak operating current according to the following: IPEAK = 4.1 - SE x (VOUT +Vf ) (9) 1.15 x fOSC x (VIN (max)+Vf ) VOUT = where VIN(max) is the maximum continuous input voltage, such as 18V (not a surge voltage, such as 40V). Starting with equation 9, and subtracting half of the inductor ripple current, provides us with an interesting equation to predict the typical DC load capability of the regulator at a given duty cycle (D): IOUT(DC) = 4.1 - SEx D fOSC VOUT x (1- D) 2 x fOSC x LO (10) OUTPUT CAPACITORS The output capacitors filter the output voltage to provide an acceptable level of ripple voltage and they store energy to help maintain voltage regulation during a load transient. The voltage rating of the output capacitors must support the output voltage with sufficient design margin. The output voltage ripple (VOUT) is a function of the output capacitor parameters: COUT, ESRCOUT, and ESLCOUT: VOUT = IL x ESRCOUT VIN -VOUT LO IL + 8 fSW C OUT IL 8 fSW C OUT (12) To reduce the voltage ripple of a design using ceramic output capacitors, simply: increase the total capacitance, reduce the inductor current ripple (that is, increase the inductor value), or increase the switching frequency. For electrolytic output capacitors the value of capacitance will be relatively high, so the third term in equation 11 will be very small. The output voltage ripple will be determined primarily by the first two terms of equation 11: VOUT = IL x ESRCOUT After an inductor is chosen, it should be tested during output short circuit conditions. The inductor current should be monitored using a current probe. A good design would ensure neither the inductor nor the regulator are damaged when the output is shorted to ground at maximum input voltage and the highest expected ambient temperature. + The type of output capacitors will determine which terms of equation 11 are dominant. For ceramic output capacitors the ESRCOUT and ESLCOUT are virtually zero, so the output voltage ripple will be dominated by the third term of equation 11: x ESLCOUT (11) + VIN -VOUT LO (13) x ESLCOUT To reduce the voltage ripple of a design using electrolytic output capacitors, simply: decrease the equivalent ESRCO and ESLCO by using a high(er) quality capacitor, or add more capacitors in parallel, or reduce the inductor current ripple (that is, increase the inductor value). The ESR of some electrolytic capacitors can be quite high so Allegro recommends choosing a quality capacitor for which the ESR or the total impedance is clearly documented in the datasheet. Also, the ESR of electrolytic capacitors usually increases significantly at cold ambients, as much as 10x, which increases the output voltage ripple and, in most cases, reduces the stability of the system. The transient response of the regulator depends on the quantity and type of output capacitors. In general, minimizing the ESR of the output capacitance will result in a better transient response. The ESR can be minimized by simply adding more capacitors in parallel or by using higher quality capacitors. At the instant of a fast load transient (di/dt), the output voltage will change by the amount: VOUT = ILOAD x ESRCOUT + di ESLCOUT dt (14) Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 27 Wide Input Voltage, 2.4MHz, 2.5A Asynchronous Buck Regulator With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output A8589 After the load transient occurs, the output voltage will deviate from its nominal value for a short time. This time will depend on the system bandwidth, the output inductor value, and output capacitance. Eventually, the error amplifier will bring the output voltage back to its nominal value. The speed at which the error amplifier brings the output voltage back to its setpoint depends mainly on the closed-loop bandwidth of the system. A higher bandwidth usually results in a shorter time to return to the nominal voltage. However, with a higher bandwidth system, it may be more difficult to obtain acceptable gain and phase margins. Selection of the compensation components (RZ, CZ, and CP) are discussed in more detail in the Compensation Components section of this datasheet. LOWIQPFM OUTPUT VOLTAGE RIPPLE CALCULATION After choosing an output inductor and output capacitor(s), its important to calculate the output voltage ripple (VOUT(PFM)) that will occur during LowIQPFM mode. With ceramic output capacitors the output voltage ripple in PWM mode is usually negligible, but that is not the case during LowIQPFM mode. First, calculate the high-side MOSFET on-time and off-time. The on-time is defined as the time it takes for the inductor current to reach the peak current threshold, IPEAK(LO_IQ): tON = IPEAK(LO_IQ) x LO VIN - VOUT - IPEAK(LO_IQ) x ( RDS(on)HS + DCRLO ) (15) If the LowIQPFM output voltage ripple appears to be too high, then the output capacitance should be increased and/or the output inductance should be decreased. Decreasing the inductor value has the drawback of increasing the ripple current, so a higher load current will be required to transition from discontinuous conduction mode (DCM) to continuous conduction mode (CCM). This might not be acceptable. In general, the LowIQPFM output voltage ripple increases as the input voltage decreases. Also, from equation 15, note that tON increases as the VOUT/VIN ratio increases (that is, as VIN decreases). If the VOUT/VIN ratio is too high, the system is not able to achieve IPEAK(LO_IQ) in only one PFM pulse. In this case the on-time is limited to approximately 4.1s and a second PFM pulse is required, about tOFF(PFM) later, as shown in figure 5. INPUT CAPACITORS Three factors should be considered when choosing the input capacitors. First, they must be chosen to support the maximum expected input surge voltage with adequate design margin. Second, the capacitor rms current rating must be higher than the expected rms input current to the regulator. Third, they must have enough capacitance and a low enough ESR to limit the input voltage dV/dt to something much less than the hysteresis of the VIN pin UVLO circuitry (VINUV(HYS), nominally 400mV for the A8589), at maximum loading and minimum input voltage. Where RDS(on) is the on-resistance (110m (typ)) of the highside MOSFET and DCRLO is the DC resistance of the output inductor, LO. For relatively low input voltages, the ontime during Low-IQPFM mode is internally limited to about 4.1s. tOFF IPEAK(LO_IQ) x LO = VOUT+Vf (16) 0.50 0.45 0.40 Ir m s / IOUT The off-time is defined as the time it takes for the inductor current to decay from IPEAK(LO_IQ) to 0 A: 0.55 0.35 0.30 0.25 0.20 0.15 0.10 Finally, the LowIQPFM output voltage ripple can be calculated: VOUT(LO_IQ) = IPEAK(LO_IQ) x (tON + tOFF) 2 x COUT 0.05 0 (17) 0 10 20 30 40 50 60 70 80 90 100 Duty Cycle (%) Figure 18: Input Capacitor Ripple versus Duty Cycle Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 28 Wide Input Voltage, 2.4MHz, 2.5A Asynchronous Buck Regulator With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output A8589 The input capacitors must deliver the rms current according to: Irms = IOUT D x (1- D) (18) where the duty cycle is: D (VOUT+Vf) / (VIN+Vf) (19) and Vf is the forward voltage of the asynchronous diode, D1. Figure 18 shows the normalized input capacitor rms current versus duty cycle. To use this graph, simply find the operational duty cycle (D) on the x-axis and determine the input/output current multiplier on the y-axis. For example, at a 20% duty cycle, the input/output current multiplier is 0.40. Therefore, if the regulator is delivering 2.5A of steady-state load current, the input capacitor(s) must support 0.40 x 2.5A, or 1.0Arms. The input capacitor(s) must limit the voltage deviations at the VIN pin to something significantly less than the A8589 VIN pin UVLO hysteresis during maximum load and minimum input voltage. The minimum input capacitance can be calculated as follows: CIN IOUT x D x (1- D) 0.85 x fOSC x VIN(MIN) (20) where VIN(MIN) is chosen to be much less than the hysteresis of the VIN pin UVLO comparator (VIN(MIN) 150mV is recommended). The Dx(1-D) term in equation 20 has an absolute maximum value of 0.25 at 50% duty cycle. So, for example, a very conservative design, based on: IOUT = 2.5A, fOSC = 85% of 425kHz, Dx(1-D) = 0.25, and VIN = 150mV, yields: CIN 2.5 (A) x 0.25 = 11.5 F 361 (kHz) x 150 (mV) A good design should consider the DC bias effect on a ceramic capacitor: as the applied voltage approaches the rated value, the capacitance value decreases. This effect is very pronounced with the Y5V and Z5U temperature characteristic devices (as much as 90% reduction) so these types should be avoided. The X5R and X7R type capacitors should be the primary choices due to their stability versus both DC bias and temperature. For all ceramic capacitors, the DC bias effect is even more pronounced on smaller sizes of device case, so a good design uses the largest affordable case size (such as 1206 or 1210). Also, it is advisable to select input capacitors with plenty of design margin in the voltage rating to accommodate the worst case transient input voltage (such as a load dump as high as 40V for automotive applications). ASYNCHRONOUS DIODE (D1) There are three requirements for the asynchronous diode. First, the asynchronous diode must be able to withstand the regulator input voltage when the high-side MOSFET is on. Therefore, one should choose a diode with a reverse voltage rating (VR) higher than the maximum expected input voltage (that is, the surge voltage). Second, the forward voltage of the diode (Vf) should be minimized or the regulator efficiency suffers. Also if Vf is too high, the A8589 missing diode protection function could be falsely activated. A Schottky type diode that can maintain a very low Vf when the regulator output is shorted to ground, at the coldest ambient temperature, is highly recommended. Third, the asynchronous diode must conduct the output current when the high-side MOSFET is turned off. Therefore, the average forward current rating of this diode (If(AVG)) must be high enough to deliver the load current according to If(AVG) IOUT(MAX) (1-DMIN) (21) where DMIN is the minimum duty cycle defined in equation19, and IOUT(MAX) is the maximum continuous output current of the regulator. BOOTSTRAP CAPACITOR A bootstrap capacitor must be connected between the BOOT and SW pins to provide the floating gate drive to the high-side MOSFET. Usually, 47nF is an adequate value. This capacitor should be a high-quality ceramic capacitor, such as an X5R or X7R, with a voltage rating of at least 16V. The A8589 incorporates a 10 low-side MOSFET to ensure that the bootstrap capacitor is always charged, even when the regulator is lightly loaded or pre-biased. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 29 Wide Input Voltage, 2.4MHz, 2.5A Asynchronous Buck Regulator With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output A8589 SOFT START AND HICCUP MODE TIMING (CSS) The soft start time of the A8589 is determined by the value of the capacitance at the soft start pin, CSS. When the A8589 is enabled, the voltage at the soft start pin starts from 0V and is charged by the soft start current, ISSSU. However, PWM switching does not begin instantly because the voltage at the soft start pin must rise above 400mV. The soft start delay (tD(SS)) can be calculated as: 400 (mV) tD(SS) = CSS x ISSSU (22) ICO = COUT x VOUT / tSS (23) is higher than the pulse-by-pulse current threshold, as shown in figure 19. This phenomena is more pronounced when using high value electrolytic type output capacitors. To avoid prematurely triggering hiccup mode the soft start capacitor, CSS, should be calculated according to: ISSSU x VOUT x COUT 0.8 (V) x ICO (24) where VOUT is the output voltage, COUT is the output capacitance, ICO is the amount of current allowed to charge the output } ILIM ILOAD tSS The output voltage ramp time, tSS, can be calculated by using either of the following methods: tSS = VOUT x If the A8589 is starting with a very heavy load, a very fast soft start time may cause the regulator to exceed the pulse-by-pulse overcurrent threshold. This occurs because the total of the full load current, the inductor ripple current, and the additional current required to charge the output capacitors: CSS capacitance during soft start (recommended: 0.1A < ICO < 0.3A). Higher values of ICO result in faster soft start times. However, lower values of ICO ensure that hiccup mode is not falsely triggered. Allegro recommends starting the design with an ICO of 0.1A and increasing it only if the soft start time is too slow. If a non-standard capacitor value for CSS is calculated, the next larger value should be used. Output capacitor current, ICO or ICO tSS = 0.8 (V) x CSS ISSSU (25) (26) When the A8589 is in hiccup mode, the soft start capacitor is used as a timing capacitor and sets the hiccup period. The soft start pin charges the soft start capacitor with ISSSU during a startup attempt and discharges the same capacitor with ISSHIC between startup attempts. Because the ratio ISSSU / ISSHIC is approximately 4:1, the time between hiccups will be about four times as long as the startup time. Therefore, the effective dutycycle of the A8589 will be very low and the junction temperature will be kept low. COMPENSATION COMPONENTS (RZ, CZ, AND CP) To properly compensate the system, it is important to understand where the buck power stage, load resistance, and output capacitance form their poles and zeros in frequency. Also, it is important to understand that the (Type II) compensated error amplifier introduces a zero and two more poles, and where these should be placed to maximize system stability, provide a high bandwidth, and optimize the transient response. First, consider the power stage of the A8589, the output capacitors, and the load resistance. This circuitry is commonly referred as the control-to-output transfer function. The low frequency gain of this circuitry depends on the COMP to SW current gain (gmPOWER), and the value of the load resistor (RL). The DC gain (GCO(0Hz)) of the control-to-output is: Figure 19: Output Current (ICO) During Startup COUT GCO(0Hz) = gmPOWER x RL (27) The control-to-output transfer function has a pole (fP1), formed Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 30 Wide Input Voltage, 2.4MHz, 2.5A Asynchronous Buck Regulator With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output A8589 design using ceramic output capacitors). Note: There is more than 90 of total phase shift because of the double-pole at half the switching frequency. by the output capacitance (COUT) and load resistance (RL), locatedat: fP1 = 1 (28) 2 x RL x COUT The control-to-output transfer function also has a zero (fZ1) formed by the output capacitance (COUT) and its associated ESR: fZ1 = 1 2 x ESR x COUT (29) For a design with very low-ESR type output capacitors (such as ceramic or OS-CONTM output capacitors), the ESR zero (fZ1) is usually at a very high frequency, so it can be ignored. On the other hand, if the ESR zero falls below or near the 0dB crossover frequency of the system (as is the case with electrolytic output capacitors), then it should be cancelled by the pole formed by the CP capacitor and the RZ resistor (discussed and identified later asfP3). A Bode plot of the control-to-output transfer function for the configuration shown in typical application schematic B (VOUT =5.0V, IOUT= 2.5A, RL = 2) is shown in Figure 20. The pole at fP1 can easily be seen at 1.9kHz while the ESR zero (fZ1) occurs at a very high frequency, 636kHz (this is typical for a Gain (dB) 20 GC(0Hz) = = RFB2 RFB1 +RFB2 VFB = VOUT VFB VOUT x gm x RO x gm x RO x AVOL (30) where VOUT is the output voltage, VFB is the reference voltage (0.8V), RO is the error amplifier output impedance (AVOL/gm). G CO(0Hz) = 15.1 dB fP1 = 1.9 kHz 0 The transfer function of the Type-II compensated error amplifier has a (very) low frequency pole (fP2) dominated by the output error amplifier output impedance (RO) and the CZ compensation capacitor: fZ1 = 636 kHz -20 -40 -60 180 Phase () The low frequency gain of the control section (GC(0Hz)) is formed by the feedback resistor divider and the error amplifier. It can be calculated using: gm is the error amplifier transconductance (750A/V), and 60 40 Next, consider the feedback resistor divider (RFB1 and RFB2), and the error amplifier (gm) and compensation network RZ-CZ-CP. It greatly simplifies the transfer function derivation if RO>>RZ, and CZ>>CP. In most cases, RO>2M, 1k<RZ<100k, 220pF<CZ<47nF, and CP<50pF, so the following equations are very accurate. fP2 = 90 0 Double Pole at 212.5 kHz -90 -180 101 102 103 104 105 Frequency (Hz) 106 1 2 x RO x CZ (31) The transfer function of the Type-II compensated error amplifier also has frequency zero (fZ2) dominated by the RZ resistor and the CZ capacitor: Figure 20: Control-to-Output Bode Plot Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 31 Wide Input Voltage, 2.4MHz, 2.5A Asynchronous Buck Regulator With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output A8589 fZ2 = 1 2 x RZ x CZ (32) Lastly, the transfer function of the Type-II compensated error amplifier has a (very) high frequency pole (fP3) dominated by the RZ resistor and the CP capacitor: 60 Gain (dB) 40 20 fP2 80 Hz fZ2 3.8 kHz G C(0Hz) = 49 dB fP3 90 kHz -20 -40 Phase () -60 180 90 0 -90 102 103 104 105 1 2 x RZ x CP (33) A Bode plot of the error amplifier and its compensation network is shown in Figure 21, fP2, fP3, and fZ2 are indicated on the magnitude plot. Notice that the zero (fZ2 at 3.8kHz) has been placed so that it is just above the pole at fP1 previously shown in the control-to-output Bode plot (Figure 20) at 1.9kHz. Placing fZ2 just above fP1 will result in excellent phase margin, but relatively slow transient recovery time, as will be shown later. Finally, consider the combined Bode plot of both the controlto-output and the compensated error amplifier (Figure22). Careful examination of this plot shows that the magnitude and phase of the entire system (red curve) are simply the sum of the error amplifier response (blue curve) and the control-to-output response (green curve). The bandwidth of this system (fC) is 60kHz, the phase margin is 69 degrees, and the gain margin is 14dB. 0 -180 101 fP3 = Complete designs for several common output voltages, at fSW of 425kHz, 1MHz, and 2MHz are provided in Table 3 on page 34. 106 Frequency (Hz) A GENERALIZED TUNING PROCEDURE Figure 21: Type-II Compensated Error Amplifier This section presents a methodology to systematically apply the design considerations provided above. 60 Gain (dB) 40 fC = 60 kHz 20 GM = 14 dB 0 -20 -40 Phase () -60 180 2. Calculate the RZ resistor value. This sets the system bandwidth (fC): 2 x COUT RZ = fC x VOUT x (34) VFB gmPOWERx x gm 90 PM = 69 0 -90 -180 101 102 103 104 1. Choose the system bandwidth (fC ). This is the frequency at which the magnitude of the gain crosses 0dB. Recommended values for fC, based on the PWM switching frequency, are in the range fSW / 20 < fC < fSW / 7.5. A higher value of fC generally provides a better transient response, while a lower value of fC generally makes it easier to obtain higher gain and phase margins. 105 106 Frequency (Hz) 3. Determine the frequency of the pole (fP1). This pole is formed by COUT and RL. Use equation 28 (repeated here): Figure 22: Bode Plot of the Complete System (red curves) Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 32 Wide Input Voltage, 2.4MHz, 2.5A Asynchronous Buck Regulator With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output A8589 fP1 = quency (15kHz). The system with fZ2 at 15kHz has 60 of phase margin, but recovers much faster (3x) than the other system. 1 2 x RL x COUT 4. Calculate a range of values for the CZ capacitor. Use the following: 4 1 < CZ < 2 x RZ x fC 2 x RZ x 1.5 x fP1 5. Calculate the frequency of the ESR zero (fZ1) formed by the output capacitor(s). Use equation 29 (repeated here): fZ1 = (35) To maximize system stability (that is, to have the greatest gain margin), use a higher value of CZ. To optimize transient recovery time, although at the expense of some phase margin, use a lower value of CZ. Figure 23 compares the output voltage recovery time due to a 1A load transient for the system shown in Figure 22 (fZ2 = 3.8kHz, 69 phase margin) and a system with fZ2 at 1/4 the crossover fre- 1 2 x ESR x COUT If fZ1 is at least one decade higher than the target crossover frequency (fC) then fZ1 can be ignored. This is usually the case for a design using ceramic output capacitors. Use equation 33 to calculate the value of CP by setting fP3 to either 5 x fC or fSW/2, whichever is higher. Alternatively, if fZ1 is near or below the target crossover frequency (fC), then use equation 33 to calculate the value of CP by setting fP3 equal to fZ1. This is usually the case for a design using high ESR electrolytic output capacitors. 5.00 fZ2 = 15 kHz 4.99 4.98 Voltage (V) fZ2 = 3.8 kHz 4.97 4.96 4.95 4.94 4.93 0 40 80 120 160 200 240 Time (s) Figure 23: Transient Recovery Comparison for fZ2 at 3.8kHz/69 and 15kHz/60 Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 33 Wide Input Voltage, 2.4MHz, 2.5A Asynchronous Buck Regulator With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output A8589 Table 3: Recommended Component Values LO (H) CO2 (F) RFB1 (k) RFB2 (k) CFB (pF) 1.51 3.3 80 63.4 +3.83 76.8 N/A 3.3 8.2 40 147 47.0 10 10 50 221 + 0.499 42.2 8 6.5 15 60 287 +6.5 41.2 6 3.3 3.3 20 147 47.0 10 4.7 30 221 + 0.499 42.2 8 6.5 6.8 40 287 +6.5 41.2 6 3.3 1.5 10 147 47.0 10 2.2 15 221 + 0.499 42.2 8 3.3 20 287 +6.5 41.2 6 VOUT (V) 5.0 5.0 5.0 6.5 fSW (MHz) 0.425 1 2 RFSET (k) 59.0 23.7 10.5 RZ + CZ // CP RZ (k) CZ (pF) CP (pF) BIAS Pin Modes 24.3 560 15 3.3 V EXT PWM and PFM 26.1 560 15 Connected to VOUT PWM and PFM 49.9 270 8 Connected to VOUT PWM and PFM 78.7 180 4.7 3.3 V or 5.0V LDO PWM and PFM 18.2 560 15 Connected to VOUT PWM and PFM 41.2 270 8 Connected to VOUT PWM and PFM 71.5 180 4.7 3.3 V or 5.0V LDO PWM and PFM 11.5 680 15 Connected to VOUT PWM and PFM 26.1 330 8 Connected to VOUT PWM and PFM 45.3 180 4.7 3.3 V or 5.0V LDO PWM and PFM 1If BIAS is not connected to V OUT, then the minimum external load must be 75 A at all temperatures. No load operation is okay at approximately 25C to 75C only. 2Negative tolerance and DC-bias effect must be considered when choosing components to obtain C . O Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 34 Wide Input Voltage, 2.4MHz, 2.5A Asynchronous Buck Regulator With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output A8589 Power Dissipation and Thermal Calculations The power dissipated in the A8589 is the sum of the power dissipated from the VIN supply current (PIN), the power dissipated due to the switching of the high-side power MOSFET (PSW), the power dissipated due to the rms current being conducted by the high-side power MOSFET (PCOND), and the power dissipated by the gate driver (PDRIVER). The power dissipated from the VIN supply current can be calculated using the following equation: PIN = VIN x IQ + (VIN - VGS) x QG x fSW (36) where VIN is the input voltage, IQ is the input quiescent current drawn by the A8589 (nominally 2.5mA), QG is the MOSFET gate charge (approximately 2.5nC), and fSW is the PWM switching frequency. The power dissipated by the high-side MOSFET during PWM switching can be calculated using the following equation: VIN x IOUT x (tr + tf ) x fSW 2 IOUT is the regulator output current, IL is the peak-to-peak inductor ripple current, RDS(on)HS is the on-resistance of the high-side MOSFET, and Vf is the forward voltage of the asynchronous diode. The RDS(on)of the high-side MOSFET has some initial tolerance plus an increase from self-heating and elevated ambient temperatures. A conservative design should accommodate an RDS(on) with at least a 15% initial tolerance plus 0.39%/C increase due to temperature. The sum of the power dissipated by the internal gate driver can be calculated using the following equation: PDRIVER = QG x VGS x fSW VGS is the MOSFET gate drive voltage (typically 5V), PSW = where (37) (39) where VGS is the gate drive voltage (typically 5V), QG is the gate charge to drive MOSFET to VGS = 5V (about 2.5nC), and fSW is the PWM switching frequency. Finally, the total power dissipated (PTOTAL) is the sum of the previous equations: where PTOTAL = PIN + PSW + PCOND + PDRIVER VIN is the input voltage, The average junction temperature can be calculated with the following equation: IOUT is the regulator output current, TJ = PTOTAL + RJA + TA fSW is the PWM switching frequency, and tr and tf are the rise and fall times measured at the SW node. The exact rise and fall times at the SW node depend on the external components and PCB layout so each design should be measured at full load. Approximate values for both tr and tf range from 10to15ns. The power dissipated by the internal high-side MOSFET while it is conducting can be calculated using the following equation: 2 PCOND = Irms(FET) x RDS(on)HS = VOUT +Vf IL2 2 x IOUT + 12 x RDS(on)HS VIN +Vf (38) (40) (41) where PTOTAL is the total power dissipated as described in equation 40, RJA is the junction-to-ambient thermal resistance (34C/W on a 4-layer PCB), and TA is the ambient temperature. The maximum junction temperature will be dependent on how efficiently heat can be transferred from the PCB to ambient air. It is critical that the thermal pad on the bottom of the IC should be connected to a at least one ground plane using multiple vias. As with any regulator, there are limits to the amount of heat that can be dissipated before risking thermal shutdown. There are tradeoffs between: ambient operating temperature, input voltage, output voltage, output current, switching frequency, PCB thermal resistance, airflow, and other nearby heat sources. Even a small amount of airflow will reduce the junction temperature considerably. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 35 A8589 Wide Input Voltage, 2.4MHz, 2.5A Asynchronous Buck Regulator With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output PCB Component Placement and Routing A good PCB layout is critical if the A8589 is to provide clean, stable output voltages. Follow these guidelines to insure a good PCB layout. Figure 24 shows a typical buck converter schematic with the critical power paths/loops. Figure 25 shows an example PCB component placement and routing with the same critical power paths/loops as shown in the schematic. 1. By far, the highest di/dt in the asynchronous buck regulator occurs at the instant the high-side MOSFET turns on and the capacitance of the asynchronous Schottky diode (200to1000pF) is quickly charged to VIN. The ceramic input capacitors must deliver this fast, short pulse of current. Therefore the loop, from the ceramic input capacitors through the high-side MOSFET and into the asynchronous diode to ground, must be minimized. Ideally these components are all connected using only the top metal layer (that is, do not use vias to other power/signal layers). 2. When the high-side MOSFET is on, current flows from the input supply and capacitors, through the high-side MOSFET, into the load via the output inductor, and back to ground. This loop should be minimized and have relatively wide traces. 3. When the high-side MOSFET is off, free-wheeling current flows from ground, through the asynchronous diode, into the load via the output inductor, and back to ground. This loop should be minimized and have relatively wide traces. 4. The voltage on the SW node transitions from 0V to VIN very quickly and is the root cause of many noise issues. It is best to place the asynchronous diode and output inductor close to the A8589 to minimize the size of the SW polygon. Also, keep low level analog signals (like FB and COMP) away from the SW polygon. 5. Place the feedback resistor divider (RFB1 and RFB2) very close to the FB pin. Ground this resistor divider as close as possible to the A8589. 6. To have the highest output voltage accuracy, the output voltage sense trace (from VOUT to RFB1) should be connected as close as possible to the load. 7. Place the compensation components (RZ, CZ, and CP) as close as possible to the COMP pin. Place vias to the GND plane as close as possible to these components. 8. Place the soft start capacitor (CSS) as close as possible to the SS pin. Place a via to the GND plane as close as possible to this component. 9. Place the boot strap capacitor (CBOOT) near the BOOT pin and keep the routing from this capacitor to the SW polygon as short as possible. 10. When connecting the input and output ceramic capacitors, use multiple vias to GND and place the vias as close as possible to the pads of the components. 11. To minimize PCB losses and improve system efficiency, the input and output traces should be as wide as possible and be duplicated on multiple layers, if possible. 12. To improve thermal performance, place multiple vias to the GND plane around the anode of the asynchronous diode. 13. The thermal pad under the A8589 must connect to the GND plane using multiple vias. More vias will ensure the lowest junction temperature and highest efficiency. 14. EMI/EMC issues are always a concern. Allegro recommends having component locations for an RC snubber from SW to ground. The resistor should be 1206 size. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 36 Wide Input Voltage, 2.4MHz, 2.5A Asynchronous Buck Regulator With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output A8589 SW VIN VOUT LO CIN3 CIN2 CIN1 Q1 D1 Rsnub CO1 CO2 CO3 CO4 LOAD Csnub 2 1 3 Figure 24: Typical B uck Converter with Critical Paths/Loops Shown Loop 1 (red). At the instant Q1 turns on, Schottky diode D1, which is very capacitive, must be very quickly shut off (only 5to15ns of charging time). This spike of charging current must come from the local input ceramic capacitor, CIN1. This spike of current is quite large and will be an EMI/EMC issue if loop 1 (red) is not minimized. Therefore, the input capacitor CIN1 and Schottky diode D1 must be placed be on the same (top) layer, be located near each other, and be grounded at virtually the same point on the PCB. Loop 2 (magenta). When Q1 is off, free-wheeling inductor current must flow from ground through diode D1 (SW will be at -Vf), into the output inductor, out to the load and return via ground. While Q1 is off, the voltage on the output capacitors decreases. The output capacitors and Schottky diode D1 should be placed on the same (top) layer, be located near each other, and be sharing a good, low inductance ground connection. Loop 3 (blue). When Q1 is on, current will flow from the input supply and input capacitors through the output inductor and into the load and the output capacitors. At this time the voltage on the output capacitors increases. 2 3 1 Figure 25: Example PCB Component Placement and Routing Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 37 Wide Input Voltage, 2.4MHz, 2.5A Asynchronous Buck Regulator With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output A8589 TYPICAL APPLICATIONS SCHEMATICS LO 8.2 H Vin 1 2 CIN1 4.7uF 50V 1210 CP 15pF CIN2 4.7uF 50V 1210 RZ 26.1K CIN3 0.47uF 100V 0805 CIN4 47nF 50V 0603 SW SW A8589 5 13 GND GND 9 3 8 12 CSS 22nF RFSET 59K CZ 560pF VIN VIN BOOT COMP SS FSET VREG VOUT 15 14 CBOOT 47 nF BIAS FB C1 1uF D1 2A/40V SMP 16 11 10 4 Mode 6 CO2 22uF 16V X7R 1210 CO3 0.47uF 100V 0805 CO4 47nF 50V 0603 COUT = 38.2uF to 42.4uF total at 3.3V bias and 10% tolerance RFB1147K RFB2 47K EN CO1 22uF 16V X7R 1210 3.3V CFB 10pF RPU 10K SLEEPn PWM/PFMn NPOR NPOR 7 Typical Applications Schematic: 12V IN/3.3VOUT/2.5A at 425KHz Figure 26: Typical Application Schematic A. Configuration for VIN = 12 V, VOUT = 3.3 V, IOUT = 2.5A at 425kHz LO 10 H Vin CIN1 4.7 F 50 V 1210 CP 8.0 pF CIN2 4.7 F 50 V 1210 RZ 49.9 K CZ 270 pF CIN3 0.47 F 100 V 0805 CSS 22 nF CIN4 47 nF 50 V 0603 1 VIN 2 VIN A8589 5 GND 13 GND 9 COMP 3 SS 8 FSET 12 VREG RFSET 59 K 15 SW 14 SW CBOOT 47 nF BOOT BIAS FB VOUT D2 2 A/40 V SMP 16 11 10 C1 1 F RFB2 42.2 K RFB1 221 K RFB 499 CO1 22 F 16 V X7R 1210 CO2 22 F 16 V X7R 1210 CO3 22 F 16 V X7R 1210 CO4 0.47 F 100 V 0805 CO5 47 F 50 V 0603 COUT = 53.9 F to 59.9 F total at 5.0 V bias and 10% tolerance 3.3 V CFB 8.0 pF RPU 10 k EN 4 Mode 6 SLEEPn PWM/PFMn NPOR 7 NPOR Figure 27: Typical Application Schematic B. Configured for VIN = 12 V, VOUT = 5.0 V, IOUT = 2.5A at 425kHz Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 38 Wide Input Voltage, 2.4MHz, 2.5A Asynchronous Buck Regulator With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output A8589 Package Outline Drawing For Reference Only - Not for Tooling Use (Reference MO-153 ABT) Dimensions in millimeters. NOT TO SCALE Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown 0.65 0.45 8 0 5.00 0.10 16 16 0.20 0.09 1.70 B 3 NOM 4.40 0.10 3.00 6.40 0.20 A 6.10 0.60 0.15 1.00 REF 1 2 3 NOM 1 0.25 BSC 2 Branded Face 3.00 SEATING PLANE C 16X 0.10 SEATING PLANE C 0.30 0.19 GAUGE PLANE C PCB Layout Reference View 1.20 MAX 0.65 BSC NNNNNNN YYWW LLLL 0.15 0.00 A Terminal #1 mark area B Exposed thermal pad (bottom surface); dimensions may vary with device C Reference land pattern layout (reference IPC7351 SOP65P640X110-17M); All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) D 1 D Standard Branding Reference View N = Device part number = Supplier emblem Y = Last two digits of year of manufacture W = Week of manufacture L = Characters 5-8 of lot number Branding scale and appearance at supplier discretion Figure 28: Package LP, 16-Pin TSSOP with Exposed Thermal Pad Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 39 A8589 Wide Input Voltage, 2.4MHz, 2.5A Asynchronous Buck Regulator With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output Revision History Revision Revision Date 1 September 9, 2014 Revised equation 8 on p. 26 Description of Revision 2 February 11, 2015 Revised Table 2 and PWM Base Frequency section OS-CON is a trademark of SANYO North America Corporation. Copyright (c)2013-2015, Allegro MicroSystems, LLC Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro's products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of Allegro's product can reasonably be expected to cause bodily harm. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 40