Designed to provide the power supply requirements of next
generation car audio and infotainment systems, the A8589
provides all the control and protection circuitry to produce a
high current regulator with ±1.0% output voltage accuracy. The
A8589 employs pulse frequency modulation (PFM) to draw
less than 50 µA from 12VIN while supplying 3.3 V/40 µA.
After startup, the A8589 operates down to at least 3.6 VIN
(VIN falling).
Features of the A8589 include a PWM/PFMn mode control
input to enable PWM (logic high) or PFM (logic low). If
the PWM/PFMn input is driven by an external clock signal
higher than the base frequency ( fOSC
) the PWM frequency
synchronizes to the incoming clock frequency. The SLEEPn
input pin commands an ultra-low current shutdown mode
requiring less than 5 µA for internal circuitry and 10 µA (max)
for MOSFET leakage at 16 VIN
, 85ºC. The A8589 has external
compensation to accommodate a wide range of frequencies
and external components, and provides a power-on reset
(NPOR) signal validated by the output voltage.
A8589-DS, Rev. 2
• Automotive AEC-Q100 qualified
• Withstands surge voltages up to 40 V
• Operates as low as 3.4 VIN (typ) with VIN decreasing
• Utilizes pulse frequency modulation (PFM) to draw only
tens of microamperes from VIN while maintaining
keep-alive VOUT
• PWM/PFMn mode control input pin
• Delivers up to 2.5 A of output current with integrated
110mΩhighvoltageMOSFET
• SLEEPn input pin commands ultra-low current
shutdown mode
• Adjustable output voltage with ±1.0% accuracy from 0°C
to 85°C, ±1.5% from –40°C to 150°C
• Programmable switching frequency: 250 kHz to 2.4 MHz
• Synchronization capability: applying a clock input to the
PWM/PFMn input pin will increase the PWM frequency
• Active low, power-on reset (NPOR) open-drain output
• Maximized duty cycle for low dropout
Wide Input Voltage, 2.4 MHz, 2.5 A Asynchronous Buck Regulator
With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output
Package: 16-pin TSSOP with exposed
thermal pad (suffix LP)
Typical Application Diagram
Not to scale
A8589
Continued on the next page…
Continued on the next page…
VIN
CIN
CPRZ
CZ
CSS
RFSET CVREG
EN
Mode
1
2
5
13
9
3
8
12
4
67
10
11
16
14
15
VIN
VIN
GND
GND
COMP
SS
FSET
VREG
SLEEP
SW
SW
BOOT
BIAS
FB
PWM/PFM POK
LO
CBOOT D1 CO
RFB1
CFB
RFB2
POK
VOUT
U1
A8589
APPLICATIONS:
• Automotive:
□Instrument
clusters
□Audio Systems
□Navigation
□HVAC
• Home Audio
FEATURES AND BENEFITS DESCRIPTION
Wide Input Voltage, 2.4 MHz, 2.5 A Asynchronous Buck Regulator
With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output
A8589
2
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Extensive protection features of the A8589 include pulse-by-pulse
current limit, hiccup mode short circuit protection, open/short
asynchronous diode protection, BOOT open/short voltage protection,
VIN undervoltage lockout, VOUT overvoltage protection and thermal
shutdown.
The A8589 is supplied in a low profile 16-pin TSSOP package
with exposed power pad (suffix LP). It is lead (Pb) free, with 100%
matte-tin leadframe plating.
• Pre-bias startup capable, VOUT will not cause a reset
• External compensation for maximum flexibility
• Stable with ceramic or electrolytic output capacitors
• Excellent set of protection features to satisfy the most
demanding applications
• Overvoltage, pulse-by-pulse current limit, hiccup mode short
circuit, and thermal protection
• Robust FMEA, with pin open/short and component faults
• Thermally enhanced, surface mount package
FEATURES AND BENEFITS (CONTINUED) DESCRIPTION (CONTINUED)
Selection Guide
Part Number Operating Ambient Temperature
Range TA, (°C) Packing
A8589KLPTR-T –40 to 125 4000 pieces per 13-in. reel
Contact Allegro® for additional packing options.
Table of Contents
Specifications 3
Functional Block Diagram 4
Pin-out Diagram and Terminal List 5
Electrical Characteristics 6
Characteristic Performance 10
Functional Description 12
Overview 12
Reference Voltage 12
PWM Switching Frequency 12
SLEEPn Input 12
PWM/PFMn Input and PWM Synchronization 13
BIAS Input Functionality, Ratings, and Connections 13
Transconductance Error Amplifier 14
Slope Compensation 14
Current Sense Amplifier 14
Power MOSFETs 14
BOOT Regulator 14
Pulse Width Modulation (PWM) Mode 14
Low-IQ Pulse Frequency Modulation (PFM) Mode 15
Maximized Duty Cycle Control 15
Reduced Current (Low-IP) PWM Mode 17
Soft Start (Startup) and Inrush Current Control 17
Pre-Biased Startup 18
Not Power-On Reset (NPOR) Output 18
Protection Features 18
Undervoltage Lockout (UVLO) 18
Pulse-by-Pulse Overcurrent Protection (OCP) 18
Overcurrent Protection (OCP) and Hiccup Mode 20
BOOT Capacitor Protection 20
Asynchronous Diode Protection 21
Output Overvoltage Protection (OVP) 21
Pin-to-Ground and Pin-to-Pin Short Protections 21
Thermal Shutdown (TSD) 21
Application Information 25
Design and Component Selection 25
Setting the Output Voltage (VOUT) 25
PWM Base Switching Frequency (fOSC, RFSET) 25
Output Inductor (LO) 26
Output Capacitors 27
Low-IQ PFM Output Voltage Ripple Calculation 28
Input Capacitors 28
Asynchronous Diode (D1) 29
Bootstrap Capacitor 29
Soft Start and Hiccup Mode Timing (CSS) 30
Compensation Components (RZ, CZ, and CP) 30
A Generalized Tuning Procedure 32
Power Dissipation and Thermal Calculations 35
PCB Component Placement and Routing 36
Typical Applications Schematics 38
Package Outline Drawing 39
Wide Input Voltage, 2.4 MHz, 2.5 A Asynchronous Buck Regulator
With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output
A8589
3
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Absolute Maximum Ratings*
Characteristic Symbol Notes Rating Unit
VIN, SLEEPn, SS Pin Voltage –0.3 to 40 V
SW Pin Voltage VSW
Continuous (minimum limit is a function of
temperature) –0.3 to VIN + 0.3 V
t < 50 ns –1.0 to VIN + 3 V
BOOT Pin Voltage VBOOT
Continuous VSW
– 0.3 to VSW + 5.5 V
BOOT OV Fault Condition VSW
– 0.3 to VSW + 7.0 V
BIAS Pin Voltage VBIAS
Continuous –0.3 to 5.5
BIAS OV Fault Condition –0.3 to 6 V
All Other Pins Voltage –0.3 to 5.5 V
Operating Ambient Temperature TAK temperature range –40 to 125 ºC
Maximum Junction Temperature TJ(max) 150 ºC
Storage Temperature Tstg –55 to 150 ºC
*Operation at levels beyond the ratings listed in this table may cause permanent damage to the device. The Absolute Maximum ratings are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated in the Electrical Characteristics table is not implied. Exposure to Absolute
Maximum-rated conditions for extended periods may affect device reliability.
Thermal Characteristics may require derating at maximum conditions, see application information
Characteristic Symbol Test Conditions* Value Unit
Package Thermal Resistance RθJA On 4-layer PCB based on JEDEC standard 34 ºC/W
*Additional thermal information available on the Allegro website.
SPECIFICATIONS
Wide Input Voltage, 2.4 MHz, 2.5 A Asynchronous Buck Regulator
With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output
A8589
4
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Functional Block Diagram
V
BIAS
>
LDO
OUT
+ 50 mV
5.75V
V
BIAS
rising
HICCUP
LOGIC
S Q
R Q
SW
COMP
FB
SS
20µA 5µA
HICCUP
PULL DOWN
Current
Comp
Soft Start
Offset 400 mV
+
–
+
Error
Amplifier
G
CSA
I
SENSE
V
REF
800 mV
400 mV
2V, 4.1V
5.0V
BOOT
+
–
OC
250 mA
BOOT REG
BOOT > 4.1V
E N
B OOT
R E G
Q
BOOT
FAULT
B OOT
OFF
1 2kΩ kΩ
I
FB
FB < 0.2V
CLAMP OCL
VREG
BIAS
VREG
LDO
POR
+
–
2.90V
1.205 V
BG
VREG
DELAY
103µs↓SLEEPn
LDO OFF
Digital
PFM
Controller
FSET
sleep
P WM
P WM
P WM
FB < 0.4V
CLK
minOff
PWM/PFMn
DELAY
2048 ↓
P FM
750mA
f
SYNC
>1.2 x f
OSC
FAULT
LOGIC
(See Fault
Table)
NPOR
VIN
+
–
DELAY
7. 5ms↓
REGOV
FB < 0.8 V
Low IP P WM
2x
sleep
P WM
FB<740 mV (PWM )
FB>880 mV (PWM)
TSD
sleep
P WM
sleep
P WM
DIODEOK
+
–UVLO
Q
FB > 880 mV (PWM)
FB < 700 mV ( PFM)
OCL
BOOT FAULT
DIODEOK
UVLO
REGOV
POR
HIC SET
HIC RST
BOOT OFF
sleep
P WM
BOOT
OFF
F
F/2
F/4
FB<700 mV (PFM )
3.8V
3.4V
f
OSC
f
SYNC
f
SW
10 Ω
110 mΩ
S
E
VPWMOFFS
Wide Input Voltage, 2.4 MHz, 2.5 A Asynchronous Buck Regulator
With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output
A8589
5
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Package LP, 16-Pin TSSOP Pin-out Diagram
Terminal List Table
Name Number Function
11 BIAS Bias input, supplies internal circuitry.
16 BOOT High-side gate drive boost input. This pin supplies the drive for the high-side N-channel MOSFET. Connect a 47 nF
ceramic capacitor from BOOT to SW.
9 COMP
Output of the error amplifier and compensation node for the current mode control loop. Connect a series RC network from
this pin to GND for loop compensation. See the Design and Component Selection section of this datasheet for further
details.
10 FB Feedback (negative) input to the error amplifier. Connect a resistor divider from the regulator output, VOUT, to this pin to
program the output voltage.
8 FSET Frequency setting pin. A resistor, RFSET, from this pin to GND sets the base PWM switching frequency (fOSC). See the
Design and Component Selection section for information on determining the value of RFSET.
5, 13 GND Ground pins.
7 NPOR Active low, power-on reset output signal. This pin is an open drain output that transitions from low to high impedance after
the output has maintained regulation for tD(NPOR).
–PAD Exposed pad of the package providing enhanced thermal dissipation. This pad must be connected to the ground plane(s)
of the PCB with at least 6 vias, directly in the pad land.
6 PWM/PFMn
Sets operating output mode (fSW). Setting this pin low forces Low-IQ PFM mode (fSW set by load). Setting this pin high
forces PWM mode switching at the the base frequency (fOSC), set by RFSET. Applying an external clock input to this pin
forces synchronization of PWM to the clock input rate (fSYNC), at a rate higher than fOSC. SLEEPn low overrides this pin.
4 SLEEPn Setting this pin low forces sleep mode (very low current shutdown mode: VOUT = 0 V). This pin must be set high to enable
the A8589. If the application does not require a sleep mode, then this pin can be tied directly to VIN. Do not float this pin.
3 SS Soft start and hiccup pin. Connect a capacitor, CSS , from this pin to GND to set soft start mode duration. The capacitor
also determines the hiccup period during overcurrent.
14, 15 SW The source of the high-side N-channel MOSFET. The external free-wheeling diode (D1) and output inductor (LO) should
be connected to this pin. Both D1 and LO should be placed close to this pin and connected with relatively wide traces.
1, 2 VIN Power input for the control circuits and the drain of the high-side N-channel MOSFET. Connect this pin to a power supply
providing from 4.0 to 35 V. A high quality ceramic capacitor should be placed and grounded very close to this pin.
12 VREG Internal voltage regulator bypass capacitor pin. Connect a 1 µF ceramic capacitor from this pin to ground and place it very
close to the A8589.
VIN
VIN
SS
SLEEPn
GND
PWM/PFMn
NPOR
FSET
BOOT
SW
SW
GND
VREG
BIAS
FB
COMP
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
PAD
Pin-out Diagram and Terminal List
Wide Input Voltage, 2.4 MHz, 2.5 A Asynchronous Buck Regulator
With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output
A8589
6
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Characteristic Symbol Test Conditions Min. Typ. Max. Unit
Input Voltage
Input Voltage Range1VIN 4.0 – 35 V
VIN UVLO Start VINUV(ON) VIN rising 3.6 3.8 4.0 V
VIN UVLO Stop VINUV(OFF) VIN falling 3.2 3.4 3.6 V
VIN UVLO Hysteresis VINUV(HYS) – 400 – mV
Input Supply Current
Sleep Mode Input Supply Current2,6 IIN(SLEEP)
VSLEEPn ≤ 0.5 V, TJ = 85°C, VIN =16 V – 5 15 µA
VSLEEPn ≤ 0.5 V, TJ = 85°C, VIN = 35 V – 7 25 µA
PWM Mode Input Supply Current2IIN(PWM) VBIAS > 3.2 V, IOUT = 0 mA – 2.5 5.0 mA
Low-IQ PFM Input Supply Current2,3
ILO_IQ(0)
VIN = 12 V, VOUT = 3.3 V, VPWMPFMn ≤ 0.8 V,
IOUT = 40 µA, TA =25ºC, components selected
per table 3
– – 50 µA
ILO_IQ(1)
VIN = 12 V, VOUT = 5.0 V, VPWMPFMn ≤ 0.8 V,
IOUT = 200 µA, TA = 25ºC, components selected
per table 3
– – 250 µA
ILO_IQ(2)
VIN = 12 V, VOUT = 6.5 V, VPWMPFMn ≤ 0.8 V,
IOUT = 1 mA, TA = 25ºC, components selected
per table 3
– – 750 µA
Voltage Regulation
Feedback Voltage Accuracy4VFB
0ºC < TJ < 85ºC, VIN ≥ 4.1 V, VFB = VCOMP 792 800 808 mV
–40ºC < TJ < 150ºC, VIN ≥ 4.1 V, VFB = VCOMP 788 800 812 mV
Low-IQ PFM Mode Output Voltage
Setting Range1,3 VOUT(LO_IQ)
3.0 V < VBIAS < 5.5 V and ILO_IQ specifications
satisfied 3.3 – 6.5 V
PWM Output Voltage Setting Range3VOUT VBIAS = GND, PWM only, no PFM mode 0.8 – 10 V
Output Dropout Voltage3VOUT(SAT)
TA = 85°C, DCRLO ≤ 75 mΩ, VIN = 3.6 V,
IOUT = 1 A, fSW = 425 kHz 3.27 3.3 – V
TA = 85°C, DCRLO ≤ 75 mΩ, VIN = 5.3 V,
IOUT = 1 A, fSW = 425 kHz 4.95 5.0 – V
TA = 85°C, DCRLO ≤ 50 mΩ, VIN = 3.75 V,
IOUT = 1 A, fSW = 2 MHz 3.25 3.3 – V
TA = 85°C, DCRLO ≤ 50 mΩ, VIN = 5.5 V,
IOUT = 1 A, fSW = 2 MHz 4.89 5.0 – V
Low-IQ PFM Mode Ripple Voltage3ΔVOUT(LO
_
IQ)
8 V < VIN < 12 V, components selected per
table 3 – 30 65 mVPP
Low-IQ PFM Mode Peak Current
Threshold IPEAK(LO_IQ)
fSW < 750 kHz – 750 – mAPEAK
fSW > 750 kHz – 850 – mAPEAK
Low-IQ PFM Mode DC Load Current3IOUT(LO_IQ)
Maximum load to maintain ΔVOUT(LO_IQ)
,
components selected per table 3 400 550 700 mA
Continued on the next page…
ELECTRICAL CHARACTERISTICS: valid at 4.0 V ≤ VIN ≤ 35 V, –40°C ≤ TA = TJ ≤ 150°C; unless otherwise specied
Wide Input Voltage, 2.4 MHz, 2.5 A Asynchronous Buck Regulator
With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output
A8589
7
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Characteristic Symbol Test Conditions Min. Typ. Max. Unit
Error Amplifier
Feedback Input Bias Current2IFB –38 – –16 nA
Open Loop Voltage Gain AVOL VCOMP = 1.2 V – 65 – dB
Transconductance gm
400 mV < VFB 550 750 950 μA/V
0 V < VFB < 400 mV 275 375 475 μA/V
Output Current IEA VCOMP = 1.2 V – ±75 – μA
COMP Pull-Down Resistance RCOMP FAULT = 1 or HICCUP = 1 – 1 – KΩ
Pulse Width Modulation (PWM)
PWM Ramp Offset PWMOFFS VCOMP level required for 0% duty cycle – 400 – mV
Minimum Controllable PWM On-Time tON(MIN)PWM
12 V < VIN < 16 V, IOUT = 1 A,
VBOOT – VSW = 4.5 V – 95 135 ns
Minimum Switch Off-Time tOFF(MIN)PWM – 95 130 ns
COMP to SW Current Gain gmPOWER – 2.85 – A/V
Slope Compensation3SE
fOSC = 2.44 MHz 2.1 3.0 3.9 A/μs
fOSC = 1.00 MHz 0.60 0.91 1.2 A/μs
fOSC = 252 kHz 0.14 0.20 0.26 A/μs
MOSFET Parameters1
High-Side MOSFET On-Resistance5RDS(on)HS
TJ =25ºC, VBOOT – VSW = 4.5 V, IDS = 0.4 A – 110 125 mΩ
TJ =150ºC, VBOOT – VSW = 4.5 V, IDS = 0.4 A – 190 215 mΩ
High-Side MOSFET Leakage2,6 Ilkg(HS)
TJ < 85°C, VSLEEPn ≤ 0.5 V, VSW = 0 V,
VIN = 16 V – – 10 µA
TJ ≤ 150°C, VSLEEPn ≤ 0.5 V, VSW = 0 V,
VIN = 16 V – 60 150 µA
SW Node Slew Rate3SRSW 12 V < VIN < 16 V – 0.72 – V/ns
Low-Side MOSFET On-Resistance5RDS(on)LS TJ = 25ºC, VIN ≥ 6 V, IDS = 0.1 A – – 10 Ω
PWM Switching Frequency
Base PWM Switching Frequency fOSC
RFSET = 8.06 kΩ, VPWM/PFMn= high 2.20 2.44 2.70 MHz
RFSET = 23.7 kΩ, VPWM/PFMn= high 0.90 1.00 1.10 MHz
RFSET = 102 kΩ, VPWM/PFMn= high – 252 – kHz
PWM Synchronization Timing
Synchronization Frequency Range fSYNC(MULT) 1.2 ×
fOSC(typ) –1.5 ×
fOSC(typ) −
Synchronized PWM Frequency fSYNC(PWM) – – 2.9 MHz
Synchronization Input Duty Cycle DSYNC – – 80 %
Synchronization Input Pulse Width twSYNC 200 – – ns
Synchronization Input Rise Time3trSYNC – 10 15 ns
Synchronization Input Fall Time3tfSYNC – 10 15 ns
Continued on the next page…
ELECTRICAL CHARACTERISTICS (continued): valid at 4.0 V ≤ VIN ≤ 35 V, –40°C ≤ TA = TJ ≤ 150°C; unless otherwise
specied
Wide Input Voltage, 2.4 MHz, 2.5 A Asynchronous Buck Regulator
With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output
A8589
8
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Characteristic Symbol Test Conditions Min. Typ. Max. Unit
PWM/PFMn Pin Input Thresholds
PWM/PFMn High Threshold VPWMPFMn(H)
3.0 V < VBIAS < 3.6 V, VPWMPFMn rising – – 2.0 V
4.5 V < VBIAS < 5.5 V, VPWMPFMn rising – – 2.6 V
PWM/PFMn Low Threshold VPWMPFMn(L)
3.0 V < VBIAS < 3.6 V, VPWMPFMn falling 0.8 – – V
4.5 V < VBIAS < 5.5 V, VPWMPFMn falling 1.2 – – V
PWM/PFMn Hysteresis VPWMPFMnhys
3.0 V < VBIAS < 3.6 V, VPWMPFM(H) – VPWMPFM(L) – 200 – mV
4.5 V < VBIAS < 5.5 V, VPWMPFM(H) – VPWMPFM(L) – 400 – mV
PWM/PFMn Input Resistance RPWMPFMn 120 200 280 kΩ
Low-IQ PFM Transition Delay tD(LO_IQ)
PWM/PFMn = low, VSS > HIC/PFMEN ,
NPOR = high – 2048 – counts
PFM Mode Timing
Constant PFM Off-Time tOFF(PFM)
fOSC < 1.5 MHz – 435 – ns
fOSC > 1.5 MHz – 275 – ns
Maximum PFM On-Time tON(PFM)MAX – 4.1 – µs
SLEEPn Pin Input Thresholds
SLEEPn High Threshold VSLEEP(H) VSLEEPn rising – 1.3 2.1 V
SLEEPn Low Threshold VSLEEP(L) VSLEEPn falling 0.5 1.2 – V
SLEEPn Delay tD(SLEEP) VSLEEPn transitioning low 55 103 150 µs
SLEEPn Input Bias Current ISLEEPBIAS VSLEEPn = 5 V – 500 – nA
VREG Pin Output
VREG Output Voltage VVREG VBIAS = 0 V – 3.05 – V
BIAS Pin Input
BIAS Input Voltage Range VBIAS 3.2 – 5.5 V
BOOT Regulator
BOOT Voltage Enable Threshold VBOOT(EN) VBOOT rising 1.7 2.0 2.2 V
BOOT Voltage Enable Hysteresis VBOOT(HYS) – 200 – mV
BOOT Voltage Low-Side Switch
Disable Threshold VBOOTLS(DIS) VBOOT rising – 4.1 – V
Soft Start Pin
FAULT, HICCUP Reset Voltage VSSRST VSS falling due to RSS(FLT) – 200 275 mV
Hiccup OCP (and Low IQ PFM
Counter Enable) Threshold HIC/PFMEN VSS rising – 2.3 – V
Maximum Charge Voltage VSS(MAX) – VVREG –−
Startup (Source) Current ISSSU HICCUP = FAULT = 0 –30 –20 –10 µA
Hiccup (Sink) Current ISSHIC HICCUP = 1 2.4 5 10 µA
Pull-Down Resistance RSS(FLT) FAULT = 1 or VSLEEPn = low – 2 – kΩ
Continued on the next page…
ELECTRICAL CHARACTERISTICS (continued): valid at 4.0 V ≤ VIN ≤ 35 V, –40°C ≤ TA = TJ ≤ 150°C; unless otherwise
specied
Wide Input Voltage, 2.4 MHz, 2.5 A Asynchronous Buck Regulator
With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output
A8589
9
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Characteristic Symbol Test Conditions Min. Typ. Max. Unit
Soft Start Pin (continued)
Soft Start Frequency Foldback fSW(SS)
0 V < VFB < 200 mV – fOSC / 4 – −
200 mV < VFB < 400 mV – fOSC / 2 – −
400 mV < VFB – fOSC –−
Soft Start Delay Time3tD(SS) CSS = 22 nF – 440 – µs
Soft Start Output Ramp Time3tSS CSS = 22 nF – 880 – µs
Hiccup Modes
Hiccup, OCP Count OCPLIM VSS > 2.3 V and OCL = 1 – 120 – counts
Hiccup, BOOT Undervoltage
(Shorted) Count BOOTUV – 120 – counts
Hiccup, BOOT Overvoltage (Open)
Count BOOTOV – 7 – counts
Overcurrent Protection (OCP)
PWM Pulse-by-Pulse Limit
ILIM(TONMIN) tON = tON(MIN)PWM 3.6 4.1 4.6 A
ILIM(TONMAX)
tON = (1 / fSW) – tOFF(MIN)PWM, no PWM
synchronization 2.3 3.1 3.9 A
Output Voltage Protection (OVP)
VOUT Overvoltage PWM Threshold VOUT(OV)PWM VFB rising, PWM mode 860 880 902 mV
VOUT Overvoltage Hysteresis VOUT(OV)HYS VFB falling, relative to VOUT(OV)PWM – –10 – mV
VOUT Undervoltage PWM Threshold VOUT(UV)PWM VFB falling, PWM mode 715 740 765 mV
VOUT Undervoltage Hysteresis VOUT(UV)HYS VFB rising, relative to VOUT(UV)PWM – 10 – mV
VOUT Undervoltage PFM Threshold VOUT(UV)PFM VFB falling, Low-IQ PFM mode 665 700 735 mV
Power-On Reset (NPOR) Output
NPOR Rising Delay tD(NPOR) VFB rising only 5 7.5 10 ms
NPOR Low Output Voltage VNPOR(L) INPOR = 5 mA – 185 400 mV
NPOR Leakage Current2INPOR(LKG) VNPOR = 5.5 V –1 – 1 µA
Thermal Protection
Thermal Shutdown Rising Threshold3TSD
PWM stops immediately and COMP and SS are
pulled low 155 170 185 ºC
Thermal Shutdown Hysteresis3TSDHYS – 20 – ºC
1Thermally limited depending on input voltage, output voltage, duty cycle, regulator load currents, PCB layout, and airflow.
2Negative current is defined as coming out of the node or pin, positive current is defined as going into the node or pin.
3Ensured by design and characterization, not production tested.
4Performance at the 0°C and 85°C ranges ensured by design and characterization, not production tested.
5Performance at 25°C ensured by design and characterization, not production tested.
6Performance at 85°C ensured by design and characterization, not production tested.
ELECTRICAL CHARACTERISTICS (continued): valid at 4.0 V ≤ VIN ≤ 35 V, –40°C ≤ TA = TJ ≤ 150°C; unless otherwise
specied
Wide Input Voltage, 2.4 MHz, 2.5 A Asynchronous Buck Regulator
With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output
A8589
10
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
CHARACTERISTIC PERFORMANCE
792
794
796
798
800
802
804
806
808
-50 -25 0 25 50 75 100 125150
VVREF (mV)
Temperature (°C)
0.50
1.00
1.50
2.00
2.50
3.00
3.50
-50 -25 0 25 50 75 100 125150
f
OSC
(MHz)
Temperature (°C)
f
OSC
= 2.44 MHz
f
OSC
= 1.00 MHz
3.3
3.4
3.5
3.6
3.7
3.8
3.9
-50 -25 0 25 50 75 100 125150
VIN UVLO Thresholds (V)
Temperature (°C)
START, V
INUV(ON)
STOP, V
INUV(OFF)
650
700
750
800
850
900
950
-50 -25 0 25 50 75 100 125150
VOUT OV and UV Thresholds (V)
Temperature (°C)
V
OUT(OV)PWM
V
OUT(UV)PWM
V
OUT(UV)PFM
3.70
3.80
3.90
4.00
4.10
4.20
4.30
4.40
4.50
-50 -25 0 25 50 75 100 125150
ILIM(TONMIN)
(A)
Temperature (°C)
- -
VFB>400 mV
VFB<400mV
V
FB
>400 mV
V
FB
<400 mV
100
200
300
400
500
600
700
800
900
50 25 0 25 50 75 100 125150
Transconductane (µA/V)
Temperature (°C)
Reference Voltage versus Temperature Switching Frequency versus Temperature
VIN UVLO Start and Stop Thresholds
versus Temperature
VOUT Overvoltage and Undervoltage Thresholds
versus Temperature
Error Amplifier Transconductance
versus Temperature
Pulse-by-Pulse Current Limit at tON(MIN)PWM
versus Temperature
(ILIM(TONMIN))
Wide Input Voltage, 2.4 MHz, 2.5 A Asynchronous Buck Regulator
With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output
A8589
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1.15
1.20
1.25
1.30
1.35
1.40
1.45
1.50
1.55
1.60
-50 -25 0 25 50 75 100 125150
PWM/PFMn Thresholds (V)
Temperature (°C)
VPWMPFMn(H)
VPWMPFMn(L)
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
-50 -25 0 25 50 75 100 125150
PWM/PFMn Thresholds (V)
Temperature (°C)
0.60
0.80
1.00
1.20
1.40
1.60
-50 -25 0 25 50 75 100 125150
SLEEPn Thresholds (V)
Temperature (°C)
VSLEEP(H)
VSLEEP(L)
0
5.0
10.0
15.0
20.0
25.0
-50 -25 0 25 50 75 100 125150
Current (µA)
Temperature (°C)
Startup, I
SSSU
Hiccup, I
SSHIC
0
50
100
150
200
250
300
350
400
-50 -25 0 25 50 75 100 125150
VNPOR (mV)
Temperature (°C)
7.00
7.10
7.20
7.30
7.40
7.50
7.60
7.70
7.80
7.90
8.00
-50 -25 0 25 50 75 100 125150
t
D(NPOR)
(ms)
Temperature (°C)
VPWMPFMn(H)
VPWMPFMn(L)
PWM/PFMn High and Low Voltage Thresholds
versus Temperature, VBIAS = 3.3 V
PWM/PFMn High and Low Voltage Thresholds
versus Temperature, VBIAS = 5.0 V
SLEEPn High and Low Voltage Thresholds
versus Temperature
SS Start and Hiccup Currents versus Temperature
NPOR Low Output Voltage at 5 mA
versus Temperature
NPOR Time Delay versus Temperature
Wide Input Voltage, 2.4 MHz, 2.5 A Asynchronous Buck Regulator
With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output
A8589
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The A8589 is an asynchronous, current mode, buck regulator that
incorporates all the control and protection circuitry necessary to
provide the power supply requirements of car audio and infotain-
ment systems.
The A8589 has three modes of operation. First, the A8589 can
deliver up to 2.5 A in pulse width modulation (PWM) mode.
Second, in Low-IQ pulse frequency modulation (PFM) mode,
the A8589 will draw only tens of microamperes from VIN while
maintaining VOUT (at no load). Under most conditions, Low-IQ
PFM mode is typically capable of supporting up to 550 mA.
Third, with the SLEEPn pin low, the A8589 will enter an ultra-
low current shutdown (sleep) mode where VOUT = 0 V and the
total current drawn from VIN will typically be less than 10 µA.
The PWM/PFMn input pin is used to select either PWM or
Low-IQ PFM mode. In PFM mode the A8589 is able to supply a
relatively high amount of current (typically 550 mA). This allows
enough current for a microcontroller or DSP to fully power-up.
After power-up, to obtain the full current capability of the A8589,
the microcontroller or DSP must change the PWM/PFMn input
from a logic low to a logic high to force PWM mode. This will
provide full current to the remainder of the system.
The A8589 was designed to support up to 2.5 A. However, the
exact amount of current it will supply, before possible thermal
shutdown, depends heavily on: duty cycle, ambient temperature,
airflow, PCB layout, and PCB construction. Figure 1 shows
calculated current ratings versus ambient temperature for VIN =
12 V, and VOUT = 3.3 V and 5.0 V, at both fSW = 425 kHz and
fSW = 2 MHz. This analysis assumed a 4-layer PCB constructed
according to the JEDEC standard (vielding a thermal resistance
of 34°C/W), with no nearby heat sources, and no airflow.
Reference Voltage
The A8589 incorporates an internal reference that allows output
voltages ( VOUT
) as low as 0.8 V. The accuracy of the internal
referenceis±1.0%from0°Cto85°Cand±1.5%from−40°Cto
150°C. The output voltage is programmed by connecting a resis-
tor divider from VOUT to the FB pin of the A8589, as shown in
the Typical Applications schematics.
PWM Switching Frequency
The PWM switching frequency of the A8589 is adjustable from
250 kHz to 2.4 MHz and has an accuracy of about ±10% across
the operating temperature range.
During startup, the PWM switching frequency changes from 25%
to 50% and finally to 100% of fOSC , as VOUT rises from 0 V to
the regulation voltage. The startup switching frequency is dis-
cussed in more detail in the section describing soft start, below.
If the regulator output is shorted to ground, VFB≈0V,thePWM
frequency will be 25% of fOSC
. In this case, the extra low switch-
ing frequency allows extra off-time between SW pulses. The
extra off-time allows the output inductor current to decay back to
0 A before the next SW pulse occurs. This prevents the inductor
current from climbing to a value that could damage the A8589 or
the output inductor.
SLEEPn Input
The A8589 has a SLEEPn logic level input pin. To get the A8589
to operate, the SLEEPn pin must be a logic high (>2.1 V). The
SLEEPn pin is rated to 40 V, allowing the SLEEPn pin to be con-
nected directly to VIN if there is no suitable logic signal available
to wake up the A8589.
When SLEEPn transitions low, the A8589 waits approximately
103 µs before shutting down. This delay provides plenty of
filtering to prevent the A8589 from prematurely entering sleep
mode because of any small glitch coupling onto the PCB trace or
SLEEPn pin.
FUNCTIONAL DESCRIPTION
VIN = 12 V, VOUT = 5 V, fSW = 2 MHz
VIN = 12 V, VOUT = 5 V, fSW = 425 kHz
VIN = 12 V, VOUT = 3.3 V, fSW = 2 MHz
VIN = 12 V, VOUT = 3.3 V, fSW = 425 kHz
Figure 1: A8589 Typical Current Derating
Overview
Wide Input Voltage, 2.4 MHz, 2.5 A Asynchronous Buck Regulator
With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output
A8589
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PWM/PFMn Input and PWM Synchronization
The PWM/PFMn pin provides two major functions. It is a control
input that sets the operating mode, and also an optional clock
input for setting PWM frequency.
If PWM/PFMn is a logic high, the A8589 operates in PWM
mode. If PWM/PFMn is a logic low, the A8589 operates in
Low-IQ PFM (keep alive) mode. When PWM/PFMn transitions
from logic high to logic low, the A8589 checks for VSS >2.3 V
and NPOR at logic high. If these two conditions are satisfied,
then the A8589 will wait 2048 internal clock cycles and then
enter Low-IQ PFM mode. This delay provides plenty of filter-
ing to prevent the regulator from prematurely entering PFM
mode because of any small glitch coupling onto the PCB trace or
PWM/PFMn pin.
Also, note that the SLEEPn pin must be a logic high or the
PWM/PFMn input has no effect. The interaction between the
SLEEPn pin and PWM/PFMn pin is summarized in Table 1.
If an external clock is applied to the PWM/PFMn pin, the A8589
synchronizes its PWM frequency to the external clock. The
external clock may be used to increase the A8589 base PWM
frequency (fOSC) set by RFSET. Synchronization operates from
1.2 × fOSC(typ) to 1.5 × fOSC(typ) . The external clock pulses must
satisfy the pulse width, duty cycle, and rise/fall time requirements
shown in the Electrical Characteristics table in this datasheet.
BIAS Input Functionality, Ratings, and Con-
nections
When the A8589 is powering up, it operates from an internal
LDO regulator, directly from VIN. However, VIN can be a rela-
tively high voltage and an LDO is very inefficient and generates
extra heat. To improve efficiency, especially in Low-IQ PFM
mode, a BIAS pin is utilized. For most applications, the BIAS pin
should be connected directly to the output of the regulator, VOUT
.
When VOUT rises to an adequate level (approximately 3.1 V), the
A8589 will shut down the inefficient LDO and begin running its
control circuitry directly from the output of the regulator. This
makes the A8589 much more efficient and cooler.
The BIAS pin is designed to operate in the range from
3.2 to 5.5 V. If the output of the regulator is in this range then
VOUT should be routed directly to the BIAS pin. However, if
the output of the regulator is above 5.6 V then a very small
LDO, capable of at least 5 mA, must be used to reduce the volt-
age to either 3.3 V or 5.0 V before routing it to the BIAS pin.
Operating with an external LDO will reduce the efficiency in
Low-IQ PFM mode.
The BIAS pin may be driven by an external power supply. For
startup, there are no sequencing requirements between VIN and
BIAS. However, for shutdown, VIN should be removed before
BIAS. If BIAS is removed before VIN it will cause the A8589 to
reset. The reset will cause the A8589 to terminate PWM switch-
ing and VOUT will decay. Also, NPOR, VSS
, and VCOMP will be
pulled low. Ideally, the SLEEPn pin should be used to set the
mode of the A8589 before VIN and/or BIAS are turned on or off.
If the BIAS pin is grounded, the A8589 will simply operate
continuously from VIN. However, during PFM mode, the input
current will increase and the PFM efficiency will be significantly
reduced.
Table 1: A8589 Modes of Operation
Pin Inputs Operating Mode
SLEEPn PWM/PFMn Name Description
Low Don’t care Sleep VOUT = 0 V
High High
PWM
fSW = fOSC VOUT = OK
and
IOUT ≤ 2.5 A
High
fSW =
PWM/PFMn
clock in
High Enter Low-IQ PFM after 2048 cycles,
if VSS > 2.3 V (typ) and NPOR = high
High Low Low-IQ PFM fSW is VOUT
dependent
VOUT = OK
and
IOUT ≤
550 mA
(typ)
High Low Low-IP PWM Fault, ILIM at 50%
+
-
+
Error Amplifier
COMP
Pin
SS Pin
FB Pin
VREF
800 mV
400 mV
Figure 2: The A8589 Error Amplier
Wide Input Voltage, 2.4 MHz, 2.5 A Asynchronous Buck Regulator
With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output
A8589
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Transconductance Error Amplifier
The transconductance error amplifier primary function is to con-
trol the regulator output voltage. The error amplifier is shown in
Figure 2. Here, it is shown as a three-terminal input device with
two positive and one negative input. The negative input is simply
connected to the FB pin and is used to sense the feedback voltage
for regulation. The two positive inputs are used for soft start and
steady-state regulation. The error amplifier performs an analog
OR selection between its two positive inputs. The error amplifier
regulates to either the soft start pin voltage (minus 400 mV) or
the A8589 internal reference, VREF, whichever is lower.
To stabilize the regulator, a series RC compensation network
(RZ and CZ) must be connected from the error amplifier output
(the COMP pin) to GND, as shown in the Typical Applica-
tions schematics. In most instances an additional, relatively low
value, capacitor (CP) should be connected in parallel with the
RZ-CZ components to reduce the loop gain at very high frequen-
cies. However, if the CP capacitor is too large, the phase mar-
gin of the regulator may be reduced. Calculating RZ, CZ, and
CP is covered in detail in the Component Selection section of
this datasheet.
If a fault occurs or the regulator is disabled (SLEEPn = low), the
COMPpinispulledtoGNDviaapproximately1kΩandPWM
switching is inhibited.
Slope Compensation
The A8589 incorporates internal slope compensation (SE
) to
allow PWM duty cycles above 50% for a wide range of input/out-
put voltages and inductor values. The slope compensation signal
is added to the sum of the current sense amplifier output and the
PWM ramp offset. As shown in the Electrical Characteristics
table, the amount of slope compensation scales with the base
switching frequency set by RFSET (fOSC
). The amount of slope
compensation does not change when the regulator is synchro-
nized to an external clock.
The value of the output inductor should be chosen such that SE is
from 0.5× to 1× the falling slope of the inductor current (SF).
Current Sense Amplifier
The A8589 incorporates a high-bandwidth current sense ampli-
fier to monitor the current in the high-side MOSFET. This current
signal is used by both the PWM and PFM control circuitry to
regulate the peak current. The current signal is also used by the
protection circuitry to prevent damage to the A8589.
Power MOSFETs
TheA8589includesa40V,110mΩhigh-sideN-channel
MOSFET, capable of delivering at least 2.5 A. The A8589 also
includesa10Ω,low-sideMOSFETtohelpensuretheBOOT
capacitor is always charged. The typical RDS(on) increase versus
temperature is shown in Figure 3.
BOOT Regulator
The A8589 contains a regulator to charge the boot capacitor.
The voltage across the BOOT capacitor is typically 5.0 V. If
the BOOT capacitor is missing, the A8589 detects a boot over-
voltage. Similarly, if the BOOT capacitor is shorted the A8589
detects a boot undervoltage. Also, the BOOT regulator has a
current limit to protect itself during a short circuit condition. The
details of how each type of boot fault is handled by the A8589 are
shown in Figures 13 and 14 and summarized in Table 2.
Pulse Width Modulation (PWM) Mode
The A8589 utilizes fixed-frequency, peak current mode control to
provide excellent load and line regulation, fast transient response,
and ease of compensation. A high-speed comparator and control
logic, capable of typical pulse widths of 95 ns, are included in the
A8589. The inverting input of the PWM comparator is connected
to the output of the error amplifier. The non-inverting input is
connected to the sum of the current sense signal, the slope com-
pensation, and a DC offset voltage (VPWMOFFS
, 400 mV (typ) ).
At the beginning of each PWM cycle, the CLK signal sets the
PWM flip flop and the high-side MOSFET is turned on. When
the summation of the DC offset, slope compensation, and current
sense signal rises above the error amplifier voltage, the PWM flip
flop is reset and the high-side MOSFET is turned off.
Figure 3: Typical MOSFET RDS(on) versus Temperature
Normalized RDS(on)
Temperature (°C)
Wide Input Voltage, 2.4 MHz, 2.5 A Asynchronous Buck Regulator
With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output
A8589
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The PWM flip flop is reset-dominant, so the error amplifier
may override the CLK signal in certain situations. For example,
at very light loads or extremely high input voltages the error
amplifier reduces (temporarily) output voltage below the 400 mV
DC offset and the PWM flip flop will ignore one or more of the
incoming CLK pulses. The high-side MOSFET will not turn
on, and the regulator will skip pulses to maintain output voltage
regulation.
In PWM mode all of the A8589 fault detection circuits are active.
See Figure 13 for a timing diagram showing how faults are han-
dled when in PWM mode. Also, the Protection Features section
of this datasheet provides a detailed description of each fault and
Table 2 presents a summary.
Maximized Duty Cycle Control
Most fixed frequency PWM controllers have limited maximum
duty cycle. This is due to the off-time required to keep the BOOT
capacitor charged in order to drive the high-side N-channel MOS-
FET. This limitation becomes significant in high-frequency, low-
input voltage regulators. It may cause the output voltage to drop
out of regulation during stop/start profiles in automotive designs.
The A8589 employs a technique that helps extend the maximum
duty cycle during drop out conditions. Without this technique the
typical maximum duty cycle would be 74% at 2 MHz switch-
ing frequency. Utilizing the extended duty cycle technique, the
A8589 can achieve typical drop out duty cycles of greater than
95% in 2 MHz designs.
Low-IQ Pulse Frequency Modulation (PFM)
Mode
The A8589 enters Low-IQ PFM mode after 2048 internal clock
cycles, if SLEEPn is high, VSS > HIC/PFMEN (2.3 V (typ)), and
NPOR is high. In Low-IQ PFM mode, the regulator operates with
a switching frequency, fSW , that depends on the load condition.
In Low-IQ PFM mode, a comparator monitors the voltage at
the FB pin. If VFB is above about 800 mV, the A8589 remains
in coast mode and draws extremely low current from the input
supply.
If the voltage at the FB pin drops below about 800 mV, the A8589
will fully power-up, delay approximately 2.5 µs while it wakes
up, and then turn on the high-side MOSFET . VOUT will rise at
a rate dependent on the input voltage, inductor value, output
capacitance, and load. The high-side MOSFET will be turned off
when either:
• current in the high-side MOSFET reaches IPEAK(LO_IQ) , or
• the high-side MOSFET has been on for tON(PFM)MAX
.
After the high-side MOSFET is turned off, the A8589 will again
Figure 4. Low-IQ PFM Mode Operation at VIN = 12 V,
VOUT = 3.3 V, and IOUT = 66 mA.
SW turns on only once every 18.5 µs to regulate VOUT
Figure 5. Low-IQ PFM Mode Operation at VIN = 12 V,
VOUT = 3.3 V, and IOUT = 330 mA.
SW turns on only twice every 5 µs to regulate VOUT
VOUT
VSW
IL
IPEAK(LO_IQ)
IPEAK(LO_IQ)
18.5 µs
3.3 V VOUT
VSW
IL
IPEAK(LO_IQ)
3.3 V tOFF(PFM) = 435 ns
Wide Input Voltage, 2.4 MHz, 2.5 A Asynchronous Buck Regulator
With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output
A8589
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Figure 6: Transitions between PWM Mode and Low-IQ PFM Mode, and Load Transient Responses;
using circuit in typical application schematic B (VIN = 12 V, VOUT = 5 V, fSW = 425 kHz)
Time D: Load steps from 0 A to 250 mA in Low-IQ PFM mode Time E: Transition from Low-IQ PFM to PWM mode at 250 mA
VOUT
VOUT
VOUT
IOUT
IOUT IOUT
VPWM/PFMn
VPWM/PFMn VPWM/PFMn
A
A
E
D
B
B
C
C
Overall
Waveforms
VOUT VOUT
IOUT
IOUT
VPWM/PFMn VPWM/PFMn
E
D
Time A: Transition from PWM to PFM at 250 mA
Time B: Load steps from 250 mA to 0 A in Low-IQ PFM mode
Time C: Load steps from 0 A to 100 mA and back to
0 A in Low-IQ PFM mode
Wide Input Voltage, 2.4 MHz, 2.5 A Asynchronous Buck Regulator
With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output
A8589
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delay approximately tOFF(PFM) and either:
• turn on the MOSFET again, if VFB < 800 mV, or
• return to the Low-IQ PFM mode
Figures 4 and 5 demonstrate Low-IQ PFM mode operation for a
light load (66 mA) and a heavy load (330 mA), respectively.
In Low-IQ PFM mode the average current drawn from the input
supply depends primarily on both the load, and how often the
A8589 must fully power-up to maintain regulation. In Low-IQ
PFM mode the following faults are detected: a missing asynchro-
nous diode, an open or shorted boot capacitor, VOUT shorted
to ground, and SW shorted to ground. As described in the next
section, if any of these faults occur the A8589 will transition
from Low-IQ PFM mode to Low-IP PWM mode, with operation
at 50% of the current limit of the PWM switching mode. See
Figure 14 for a timing diagram showing operation of the A8589
in Low-IQ PFM mode.
In Low-IQ PFM mode the A8589 dissipates very little power, so
the thermal monitoring circuit (TSD) is not needed and is dis-
abled to minimize the quiescent current and improve efficiency.
Figure 6 shows PWM to Low-IQ PFM transitions for a typical
microcontroller or DSP system. The system starts in PWM mode
at IOUT = 250 mA and then transitions to Low-IQ PFM mode,
also at IOUT = 250 mA (time A). While in Low-IQ PFM mode the
current drops from 250 mA to 0 A (time B) and also cycles from
no load to 100 mA (time C). In Low-IQ PFM mode the load steps
from IOUT = 0 A to 250 mA (time D) and then the A8589 transi-
tions back to PWM mode (time E). For this example, the output
ripple voltage is always less than 30 mVPP and the transient
deflection between modes is always less than 50 mVPEAK.
Reduced Current (Low-IP) PWM Mode
The A8589 supports two different levels of current limiting in
PWM modes:
• 100% current, which is during normal PWM, and
• Low-IP, in which the current is limited to about 50% of the
typical current limit
The Low-IP PWM mode is invoked when the A8589 is supposed
to be in PFM mode but a fault occurs. The purpose of the Low-IP
PWM mode is to give priority to maintaining reliable regula-
tion of VOUT while enabling all the protection circuits inside the
A8589 that are normally debiased during Low-IQ PFM mode
(high precision comparators, timers, and counters).
There are several faults that cause a transition from Low-IQ
PFM to Low-IP PWM mode: a missing asynchronous diode, an
open or shorted boot capacitor, VOUT shorted to ground, or SW
shorted to ground. See Figure 14 for a timing diagram showing
operation when the A8589 transitions from Low-IQ PFM mode
to Low-IP PWM mode.
Soft Start (Startup) and Inrush Current Con-
trol
Inrush current is controlled by a soft start function. When the
A8589 is enabled and all faults are cleared, the soft start pin will
source ISSSU and the voltage on the soft start capacitor, CSS , will
ramp upward from 0 V. When the voltage at the soft start pin
exceeds approximately 400 mV, the error amplifier will slew its
output voltage above the PWM Ramp Offset ( VPWMOFFS
). At that
instant, the high-side and low-side MOSFETs will begin switch-
ing. As shown in Figure 7, there is a small delay (tD(SS)
) between
when the enable pin transitions high, and when both the soft start
voltage exceeds 400 mV and the error amplifier slews its output
high enough to initiate PWM switching.
After the A8589 begins switching, the error amplifier will regu-
late the voltage at the FB pin to the soft start pin voltage minus
approximately 400 mV. During the active portion of soft start,
Figure 7: Normal Startup to VOUT = 3.3 V and IOUT =
1.6 A; PWM/PFMn Pin = high, SLEEPn Pin Transitions
from Low to High
3.3 V
VSS = 400 mV
VSS = 1.2 V
VSLEEPn
tD(SS) tSS
VOUT
VCOMP
fSW/4 fSW/2
fSW
VSS
IL
Wide Input Voltage, 2.4 MHz, 2.5 A Asynchronous Buck Regulator
With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output
A8589
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the voltage at the soft start pin rises from 400 mV to 1.2 V (a
difference of 800 mV), the voltage at the FB pin rises from 0 V
to 800 mV, and the regulator output voltage rises from 0 V to the
targeted setpoint, which is determined by the feedback resistor
divider on the FB pin.
During startup, the PWM switching frequency is reduced to 25%
of fOSC while VFB is below 200 mV. If VFB is above 200 mV but
below 400 mV, the switching frequency is reduced to 50% of
fOSC . Also, if VFB is below 400 mV, the gm of the error amplifier
is reduced to gm / 2. When VFB is above 400 mV the switching
frequency will be fOSC and the error amplifier gain will be gm .
The reduced switching frequencies and error amplifier gain are
necessary to help improve output regulation and stability when
VOUT is at a very low voltage. When VOUT is very low, the
PWM control loop requires on-times near the minimum control-
lable on-time, as well as extra-low duty cycles that are not pos-
sible at the base operating switching frequencies.
When the voltage at the soft start pin reaches approximately
1.2 V, the error amplifier will change mode and begin regulating
the voltage at the FB pin to the A8589 internal reference, 800 mV.
The voltage at the soft start pin will continue to rise to approxi-
mately VREG . Complete soft start operation from VOUT = 0 V is
shown in Figure 7.
If the A8589 is disabled or a fault occurs, the internal fault latch
will be set and the capacitor on the soft start pin will be dis-
chargedtogroundveryquicklybyaninternal2kΩpull-down
resistor. The A8589 will clear the internal fault latch when the
voltage at the soft start pin decays to approximately 200 mV
(VSSRST). Conversely, if the A8589 enters hiccup mode, the
capacitor on the soft start pin is slowly discharged by a current
sink, ISSHIC
. Therefore, the soft start capacitor (CSS) not only
controls the startup time but also the time between soft start
attempts in hiccup mode. Hiccup mode operation is discussed in
more detail in the Protection Features section of this datasheet.
Pre-Biased Startup
If the output of the regulator (VOUT) is pre-biased to some volt-
age, the A8589 will modify the normal startup routine to prevent
discharging the output capacitors. As described previously, the
error amplifier usually becomes active when the voltage at the
soft start pin exceeds 400 mV. If the output is pre-biased, the
FB pin will be at some non-zero voltage. The A8589 will not
start switching until the voltage at the soft start pin increases
to approximately VFB + 400 mV. When the soft start pin volt-
age exceeds this value: the error amplifier becomes active, the
voltage at the COMP pin rises, PWM switching starts, and VOUT
ramps upward from the pre-bias level. Figure 8 shows startup
when the output voltage is pre-biased to 1.6 V.
Figure 8: Pre-biased Startup from VOUT = 1.6 V to VOUT
= 3.3 V, at IOUT = 1.6 A
Figure 9: Initialization of NPOR as VIN Ramps Up
VSS
VSLEEPn
VOUT
VCOMP
IL
VOUT rises from 1.6 V, it
is not pulled to 0 V
Switching delayed until VSS
= VFB +400 mV
3.3 V
1.6 V
VSS = 400 mV
VSS = 1.2 V
fSW/2
fSW
VIN = 2.2 V
VIN
VNPOR
Wide Input Voltage, 2.4 MHz, 2.5 A Asynchronous Buck Regulator
With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output
A8589
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2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
4.0
4.2
4.4
4.6
2.2
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100
I
LIM
(A)
Duty Cycle (%)
Min. at 2.45 MHz
Typ at 2.45 MHz
MAX_2.45 MHz
MIN_250 kHz
TYP_250 kHz
MAX_250 kHz
Min. at 2.45 MHz
Typ. at 2.45 MHz
Max. at 2.45 MHz
Min. at 250 kHz
Typ. at 250 kHz
Max. at 250 kHz
Not Power-On Reset (NPOR) Output
The A8589 has an inverted power-on reset output (NPOR) with a
fixed delay of its rising edge ( tD(NPOR)
). The NPOR output is an
open drain output so an external pull-up resistor must be used, as
shown in the Typical Applications schematics. NPOR transitions
high when the output voltage ( VOUT
), sensed at the FB pin, is
within regulation. In PWM mode, NPOR is high when the output
voltage is typically within 92.5% to 110% of the target value. In
PFM mode, NPOR is high when the output voltage is typically
above 87.5% of the target value. The NPOR overvoltage and
undervoltage comparators incorporate a small amount of hyster-
esis (10 mV typically) and filtering (5 µs typically) to help reduce
chattering due to voltage ripple at the FB pin.
The NPOR output is immediately pulled low either: if an output
overvoltage or an undervoltage condition occurs, or if the A8589
junction temperature exceeds the thermal shutdown threshold
(TSD). For other faults, NPOR behavior depends on the output
voltage. Table 2 summarizes all the A8589 fault modes and their
effect on NPOR.
At power-up, NPOR must be initialized (set to a logic low)
when VIN is relatively low. Figure 9 shows VIN ramping up, and
also NPOR being set to a logic low when VIN is only 2.2 V. For
this test, NPOR was pulled up to an external 3.3 V supply via a
2kΩresistor.
At power-down, NPOR must be held in the logic low state as
long as possible. Figure 10 shows VIN ramping down and also
NPOR being held low until VIN is only 1.3 V. For this test, NPOR
waspulleduptoanexternal3.3Vsupplyviaa2kΩresistor.
Protection Features
The A8589 was designed to satisfy the most demanding automo-
tive and non-automotive applications. In this section, a descrip-
tion of each protection feature is described and Table 2 summa-
rizes the protection features and operation.
UNDERVOLTAGE LOCKOUT (UVLO)
An undervoltage lockout (UVLO) comparator monitors the volt-
age at the VIN pin and keeps the regulator disabled if the voltage
is below the stop threshold ( VINUV(OFF)
). The UVLO comparator
incorporates some hysteresis ( VINUV(HYS)
) to help reduce on-off
cycling of the regulator due to resistive or inductive drops in the
VIN path during heavy loading or during startup.
PULSE-BY-PULSE OVERCURRENT PROTECTION (OCP)
The A8589 monitors the current in the high-side MOSFET and
if the current exceeds the pulse-by-pulse overcurrent threshold
( ILIM
) then the high-side MOSFET is turned off. Normal PWM
operation resumes on the next clock pulse from the internal
oscillator. The A8589 includes leading edge blanking to prevent
falsely triggering the pulse-by-pulse current limit when the high-
side MOSFET is turned on.
Because of the addition of the slope compensation ramp to the
Figure 10: NPOR being Held Low as VIN Ramps Down Figure 11: Pulse-by-pulse Current Limiting versus Duty
Cycle; at fSW = 250 kHz (dashed curves) and fSW =
2.45 MHz (solid curves)
VIN = 1.3 V VIN
VNPOR
Wide Input Voltage, 2.4 MHz, 2.5 A Asynchronous Buck Regulator
With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output
A8589
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inductor current, the A8589 delivers more current at lower duty
cycles and less current at higher duty cycles. Also, the slope
compensation is not a perfectly linear function of switching
frequency. For a given duty cycle, this results in a little more cur-
rent being available at lower switching frequencies than higher
frequencies. Figure 11 shows the typical and worst case min/max
pulse-by-pulse current limits versus duty cycle at fSW = 250 kHz
and 2.45 MHz.
If the synchronization input (PWM/PFMn) is used to increase
the switching frequency, the on-time and the current ripple will
decrease. This will allow slightly more current than at the base
switching frequency ( fOSC
).
The exact current the buck regulators can support is heavily
dependent on: duty cycle ( VIN, VOUT , Vf ), ambient temperature,
thermal resistance of the PCB, airflow, component selection, and
nearby heat sources.
OVERCURRENT PROTECTION (OCP) AND HICCUP
MODE
An OCP counter and hiccup mode circuit protect the buck regula-
tor when the output of the regulator is shorted to ground or when
the load is too high. When the voltage at the soft start pin is
below the hiccup OCP threshold ( HIC/PFMEN ) the hiccup mode
counter is disabled. Two conditions must be met for the OCP
counter to be enabled and begin counting:
• VSS > HIC/PFMEN (2.3 V (typ)) and
• VCOMP is clamped at its maximum voltage (OCL =1)
As long as these two conditions are met, the OCP counter
remains enabled and will count pulses from the overcurrent com-
parator. If the COMP pin voltage decreases ( OCL = 0 ) the OCP
counter is cleared.
If the OCP counter reaches OCPLIM counts (120), a hiccup latch
is set and the COMP pin is quickly pulled down by a relatively
lowresistance(1kΩ).Thehiccuplatchalsoenablesasmallcur-
rent sink connected to the soft start pin ( ISSHIC
). This causes the
voltage at the soft start pin to slowly ramp downward. When the
voltage at the soft start pin decays to a low enough level (VSSRST
,
200 mV (typ)) the hiccup latch is cleared and the small current
sink turned off. At that instant, the soft start pin will begin to
source current ( ISSSU
) and the voltage at the soft start pin will
ramp upward. This marks the beginning of a new, normal soft
start cycle as described earlier. (Note: OCP is the only fault that
results in hiccup mode that is ignored when VSS < 2.3 V.)
When the voltage at the soft start pin exceeds the soft start
offset (typically 400 mV) the error amplifier forces the voltage
at the COMP pin to quickly slew upward and PWM switching
will resume. If the short circuit at the regulator output remains,
another hiccup cycle will occur. Hiccups will repeat until the
short circuit is removed or the regulator is disabled. If the short
circuit is removed, the A8589 will soft start normally and the
output voltage will automatically recover to the target level, as
shown in Figure 12.
BOOT CAPACITOR PROTECTION
The A8589 monitors the voltage across the BOOT capacitor to
detect if the capacitor is missing or short circuited. If the BOOT
capacitor is missing, the regulator will enter hiccup mode after
7 PWM cycles. If the BOOT capacitor is short circuited, the
regulator will enter hiccup mode after 120 PWM cycles, provided
there is no VOUT overvoltage detection. At no load or very light
loads, the boot charging circuit will increase the output voltage
(via the output inductor) and cause an overvoltage condition to be
detected if VIN > VOUT + 5.7 V.
For a boot fault, hiccup mode will operate virtually the same
as described previously for an output short circuit fault (OCP)
with the soft start pin ramping up and down as a timer to initiate
repeated soft start attempts. Boot faults are a non-latched condi-
tion, so the A8589 will automatically recover when the fault is
corrected.
Figure 12. Hiccup Mode Operation and Recovery to
VOUT = 3.3 V, IOUT = 1.6 A
VSS
VOUT
VCOMP
IL
2.3 V
200 mV
ILIM(TONMIN)
120 OCP counts
Short removed
Wide Input Voltage, 2.4 MHz, 2.5 A Asynchronous Buck Regulator
With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output
A8589
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ASYNCHRONOUS DIODE PROTECTION
If the asynchronous diode (D1 in the Typical Applications sche-
matics) is missing or damaged (open) the SW pin will be subject
to unusually high negative voltages. These negative voltages may
cause the A8589 to malfunction and could lead to damage.
The A8589 includes protection circuitry to detect when the
asynchronous diode is missing. If the SW pin is below typically
−1.25Vformorethanabout50ns,theA8589willenterhic-
cup mode after detecting one missing diode fault. Also, if the
asynchronous diode is short circuited, the A8589 will experience
extremely high currents in the high-side MOSFET. If this occurs
the A8589 will enter hiccup mode after detecting one short cir-
cuited diode fault.
OUTPUT OVERVOLTAGE PROTECTION (OVP)
The A8589 provides a basic level of overvoltage protection by
monitoring the voltage level at the FB pin. Two overvoltage con-
ditions can be detected:
• The FB pin is disconnected from its feedback resistor divider.
In this case, a tiny internal current source forces the voltage at
the FB pin to rise. When the voltage at the FB pin exceeds the
overvoltage threshold ( VOUT(OV)PWM , 880 mV (typ)) PWM
switching will stop and NPOR will be pulled low.
• A higher, external voltage supply is accidently shorted to the
A8589s output. VFB will probably rise above the overvoltage
threshold and be detected as an overvoltage condition. In
this case, the low-side MOSFET will continue to operate
and can correct the OVP condition, provided that only a few
milliamperes of pull-down current are required. In either
case, if the condition causing the overvoltage is corrected the
regulator will automatically recover.
PIN-TO-GROUND AND PIN-TO-PIN SHORT PROTEC-
TIONS
The A8589 is designed to satisfy the most demanding automotive
applications. For example, the A8589 has been carefully designed
from the very beginning to withstand a short circuit to ground at
each pin without suffering damage.
In addition, care was taken when defining the A8589 pin-out to
optimize protection against pin-to-pin adjacent short circuits. For
example, logic pins and high voltage pins are separated as much
as possible. Inevitably, some low voltage pins are located adja-
cent to high voltage pins, but in these instances the low voltage
pins are designed to withstand increased voltages, with clamps
and/or series input resistance, to prevent damage to the A8589.
THERMAL SHUTDOWN (TSD)
The A8589 monitors junction temperature and will stop PWM
switching and pull NPOR low if it becomes too hot. Also, to pre-
pare for a restart, the soft start and COMP pins will be pulled low
until VSS < VSS(RST)
. TSD is a non-latched fault, so the A8589
will automatically recover if the junction temperature decreases
by approximately 20°C.
Wide Input Voltage, 2.4 MHz, 2.5 A Asynchronous Buck Regulator
With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output
A8589
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Fault
Mode VSS
During fault counting,
before Hiccup mode
BOOT
Charging
NPOR
State Latched?
Reset
ConditionVCOMP
High-Side
MOSFET
Low-Side
MOSFET
Output
overcurrent,
VFB< 200 mV
Hiccup, after
120 OCP
faults
Clamped for
ILIM, then
pulled low for
hiccup
fOSC / 4 due to
VFB < 200 mV,
responds to
VCOMP
Can be
activated if
VBOOT is too
low
Not affected Depends on
VOUT
No
Automatic,
after remove
the short
Output
overcurrent,
VFB > 400 mV
Hiccup, after
120 OCP
faults
Clamped for
ILIM, then
pulled low for
hiccup
fOSC due to
VFB > 400 mV,
responds to
VCOMP
Can be
activated if
VBOOT is too
low
Not affected Depends on
VOUT
No
Automatic,
after decrease
load current
Boot capacitor
open/missing
(BOOTOV)
Hiccup, after
7 BOOTOV
faults
Pulled low for
hiccup
Forced
off when
BOOTOV fault
occurs
Forced off
when BOOT
fault occurs
Off after
BOOT fault
occurs
Depends on
VOUT
No
Automatic,
after replace
capacitor
Boot capacitor
shorted
(BOOTUV)
Hiccup, after
120 BOOTUV
faults
Not affected,
pulled low for
hiccup
Forced
off when
BOOTUV fault
occurs
Forced off
only during
hiccup
Off only during
hiccup
Depends on
VOUT
No
Automatic,
after unshort
capacitor
Asynchronous
diode missing
Hiccup after
1 fault
Pulled low for
hiccup
Forced off
after 1 fault
Can be
activated if
VBOOT is too
low
Not affected Depends on
VOUT
No
Automatic,
after install
diode
Asynchronous
diode (or SW)
hard short to
ground
Hiccup after
1 fault
Pulled low for
hiccup
Forced off
after 1 fault
Can be
activated if
VBOOT is too
low
Not affected Depends on
VOUT
No
Automatic,
after remove
short
Asynchronous
diode (or SW)
soft short to
ground
Hiccup, after
120 OCP
faults
Clamped for
ILIM, then
pulled low for
hiccup
Active,
responds to
VCOMP
Can be
activated if
VBOOT is too
low
Not affected Depends on
VOUT
No
Automatic,
after remove
short
FB pin open
(FB floats
high)
Begins to
ramp up for
soft start
Transitions
low via loop
response
Forced off by
low VCOMP
Active during
tOFF(MIN)PWM
Off when VFB
is too high
Pulled low
when VFB is
too high
No
Automatic,
after connect
FB pin
Output
overvoltage
(VFB >
880 mV)
Not affected
Transitions
low via loop
response
Forced off by
low VCOMP
Active during
tOFF(MIN)PWM
Off when VFB
is too high
Pulled low
when VFB is
too high
No
Automatic,
after VFB
returns to
normal range
Output
undervoltage Not affected
Transitions
high via loop
response
Active,
responds to
VCOMP
Can be
activated if
VBOOT is too
low
Not affected
Pulled low
when VFB is
too low
No
Automatic,
after VFB
returns to
normal range
Thermal
shutdown
Pulled low and
latched until
VSS < VSSRST
Pulled low and
latched until
VSS < VSSRST
Forced off by
low VCOMP
Disabled Off Pulled low No
Automatic,
after part
cools down
VREG
or BIAS
overvoltage
(REGOV)
Not affected
Transitions
low via loop
response
Forced off by
low VCOMP
Active during
tOFF(MIN)PWM
Off Pulled low No
Automatic,
VREG or
BIAS to
normal range
TABLE 2: Summary of A8589 Fault Modes and Operation
Wide Input Voltage, 2.4 MHz, 2.5 A Asynchronous Buck Regulator
With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output
A8589
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Figure 13: Operation with SLEEPn = high and PWM/PFMn = high (PWM mode)
Wide Input Voltage, 2.4 MHz, 2.5 A Asynchronous Buck Regulator
With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output
A8589
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Allegro MicroSystems, LLC
115 Northeast Cutoff
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1.508.853.5000; www.allegromicro.com
Figure 14: Operation with SLEEPn = high and PWM/PFMn = low (Low-IQ PFM mode and transition to Low-IP PWM
mode)
~500mV
~500mV
~500mV
BOOT
FAULTS
LOW-IP PWMLOW-IP PWMPWM
DIODE or SW
FAULTS
MODE
PWM/
PFMn
TSD
OC
HIC_EN
HICCUP
OC
FAULT
BOOT
FAULT
VIN
VOUT
SS
COMP
DIODE
FAULT
SW
SS LO_IQ HICCUPOC
F
SW
F
SW
SS SS LO_IQ S
SLO_IQ
x1
PWMOC HICCUP
x1
F
SW
LO_IQ
HICC
UP HICCUP SS SS
x1
S
S
HICC
UP SS HI
CSS HI
C
F
SW
SS>2.3V •
FB>0.74V
x7 OV
x120 UV
TO
2.3V
FROM
2.3V
TO
2.3V
FROM
2.3V TO
2.3V
FROM
2.3V
TO
2.3V
FROM
2.3V
LOW-IP PWM
2048 2048
OFF
Vout shorted to GND
x120
SLEEPn
F
SW
/4
SS>2.3V •
FB>0.74V
F
SW
/4
then
F
SW
/2
F
SW
/4
then
F
SW
/2
F
SW
/4
then
F
SW
/2
F
SW
/4 F
SW
/4 F
SW
/4 F
SW
/4 F
SW
/4
x7 OV
x120 UV
x7 OV
x120 UV
HICCUP
~500mV
x120
NPOR
7.5ms 7.5m s 7.5ms 7.5m s
2048
Note: NPOR=1 already, so V
SS
>HIC/PFM
EN
starts the 2048 PFM delay counter
SS>2.3V •
FB>0.74V
F
SW
F
SW
/4
then
F
SW
/2
2048
SS>2.3V •
FB>0.74V
Note: Faster SS shown here, so NPOR↑ starts
the 2048 PFM delay counter, instead of V
SS
Wide Input Voltage, 2.4 MHz, 2.5 A Asynchronous Buck Regulator
With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output
A8589
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Design and Component Selection
SETTING THE OUTPUT VOLTAGE (VOUT)
The output voltage of the regulator is determined by connecting
a resistor divider from the output node (VOUT) to the FB pin
as shown in Figure 15. There are trade-offs when choosing the
value of the feedback resistors. If the series combination (RFB1
+ RFB2) is too low, then the light load efficiency of the regula-
tor will be reduced. So to maximize the efficiency, it is best to
choose higher values of resistors. On the other hand, if the paral-
lel combination (RFB1 // RFB2) is too high, then the regulator
may be susceptible to noise coupling onto the FB pin.
The feedback resistors must satisfy the ratio shown in the follow-
ing equation to produce the target output voltage, VOUT
:
=– 1
0.8 (V)
VOUT
RFB2
RFB1
(1)
Compared to typical buck regulators, a PFM capable buck
regulator presents some unique challenges when determining its
feedback divider. This resistor divider must draw minimal current
from VOUT or it will reduce the efficiency during Low-IQ PFM
operation. With this in mind, Allegro recommends the resistor
values show in Table 3 on page 34.
For Low-IQ PFM mode, a feedforward capacitor (CFB) should
be connected in parallel with RFB1, as shown in Figure 16.
The purpose of this capacitor is to offset any stray capacitance
(CSTRAY) from the FB pin to ground. Without CFB, the stray
capacitance and the relatively high resistor values used for the
feedback network form a low pass filter and introduce lag to the
Low-IQ PFM feedback path. The feedforward capacitor helps to
maintain sensitivity during Low-IQ PFM mode and to assure the
output voltage ripple is minimized.
In general, CFB should be calculated as:
CFB > (1.5 × CSTRAY) × ( RFB2 / RFB1 ) (2)
where CSTRAY is typically 15 to 25 pF.
PWM BASE SWITCHING FREQUENCY (FOSC, RFSET)
The PWM base switching frequency, fOSC, is set by connecting a
resistor from the FSET pin to ground. Figure 17 is a graph show-
APPLICATION INFORMATION
Figure 15: Connecting a Feedback Resistor Divider to
Set the Output Voltage
Figure 16: Addition of CFB to Cancel Stray Capacitance
at the FB Pin in PFM Mode
RFB1
RFB2
V
OUT
FB PIN
RFB1
RFB2
VOUT FB PIN
CSTRAY
15 to 25 pF
CFB
0.00
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
5.0 15.0 25.0 35.0 45.0 55.0 65.0 75.0 85.0 95.0
Frequency (MHz)
R
FSET
(kΩ)
Figure 17: PWM Switching Frequency versus RFSET
Wide Input Voltage, 2.4 MHz, 2.5 A Asynchronous Buck Regulator
With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output
A8589
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ing the relationship between the typical switching frequency and
the FSET resistor. The base frequency is the output frequency,
fSW , when PWMPFMn is high (no external clocking signal). For
a given base switching frequency ( fOSC
), the FSET resistor can
be calculated as follows:
=– 2.75
fOSC
26385
RFSET (3)
where fOSC is in kHz and RFSETisinkΩ.
When the PWM base switching frequency is chosen the
designer should be aware of the minimum controllable on-time,
tON(MIN)PWM of the A8589. If the system required on-time is less
than the A8589 minimum controllable on-time, switch node jitter
occurs and the output voltage will have increased ripple or oscil-
lations.
The PWM base switching frequency required should be calcu-
lated as follows:
<
fOSC
VOUT
tON(MIN)PWM × VIN(MAX)REQ (4)
where
VOUT is the output voltage,
tON(MIN)PWM is the minimum controllable on-time of the A8589
(95 ns (typ), 135 ns (max)), and
VIN(MAX)REQ is the maximum required operational input voltage
(not the peak surge voltage).
If the A8589 PWM synchronization function is employed, then
the base switching frequency should be chosen such that jitter
will not result at the maximum synchronized switching fre-
quency, determined from equation 4:
<
fOSC 0.66 ×VOUT
tON(MIN)PWM × VIN(MAX)REQ
(5)
OUTPUT INDUCTOR (LO)
For a peak current mode regulator it is common knowledge that,
without adequate slope compensation, the system will become
unstable when the duty cycle is near or above 50%. However, the
slope compensation in the A8589 is a fixed value (SE). Therefore,
it is important to calculate an inductor value such that the falling
slope of the inductor current (SF) will work well with the A8589
slope compensation. The following equation can be used to cal-
culate a range of values for the output inductor based on the well
known approach of providing slope compensation that matches
50% to 100% of the falling slope of the inductor current:
≤≤ LO
2 × SE
VOUT + Vf
SE
VOUT + Vf
(6)
where Vf is the forward voltage of the asynchronous diode, and
LO is in µH.
In equation 6, the slope compensation (SE ) is a function of
switching frequency according the following:
=
SE0.23 × fOSC2 + 0.63 × fOSC + 0.038 (7)
where SE is in A/µs and fOSC is in MHz.
More recently, Dr. Raymond Ridley presented a formula to calcu-
late the amount of slope compensation required to critically damp
the double poles at half the PWM switching frequency:
≥
LO1–
V+V
OUT f
SE
0.18
D
=1– ( (min) )V+V
IN f
V+V
OUT f
V+V
OUT f
SE
0.18 × (8)
This formula allows the inclusion of the duty cycle (D), which
should be calculated at the minimum input voltage to insure
optimal stability. Also, to avoid dropout (that is, saturation of
the buck regulator), VIN(min) must be approximately 1 to 1.5 V
above VOUT when calculating the inductor value with equation 8.
If equations 7 or 8 yield an inductor value that is not a standard
value, then the next highest available value should be used. The
final inductor value should allow for 10% to 20% of initial toler-
ance and 20% to 30% of inductor saturation.
The saturation current of the inductor should be higher than the
peak current capability of the A8589. Ideally, for output short cir-
cuit conditions, the inductor should not saturate even at the high-
est pulse-by-pulse current limit at minimum duty cycle, 4.6 A.
Wide Input Voltage, 2.4 MHz, 2.5 A Asynchronous Buck Regulator
With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output
A8589
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This may be too costly. At the very least, the inductor should not
saturate at the peak operating current according to the following:
=
IPEAK 4.1 – SE × (VOUT+Vf )
1.15 × fOSC × (VIN(max)+Vf )
(9)
where VIN(max) is the maximum continuous input voltage, such
as 18 V (not a surge voltage, such as 40 V).
Starting with equation 9, and subtracting half of the inductor
ripple current, provides us with an interesting equation to predict
the typical DC load capability of the regulator at a given duty
cycle (D):
=
IOUT(DC) 4.1 – SE× D
fOSC 2 × fOSC × LO
VOUT × (1– D) (10)
After an inductor is chosen, it should be tested during output
short circuit conditions. The inductor current should be monitored
using a current probe. A good design would ensure neither the
inductor nor the regulator are damaged when the output is shorted
to ground at maximum input voltage and the highest expected
ambient temperature.
OUTPUT CAPACITORS
The output capacitors filter the output voltage to provide an
acceptable level of ripple voltage and they store energy to help
maintain voltage regulation during a load transient. The voltage
rating of the output capacitors must support the output voltage
with sufficient design margin.
Theoutputvoltageripple(ΔVOUT ) is a function of the output
capacitor parameters: COUT
, ESRCOUT
, and ESLCOUT
:
=
∆VOUT ∆IL × ESRCOUT
∆IL
× ESLCOUT
VIN–VOUT
LO
8 fSWCOUT
+
+
(11)
The type of output capacitors will determine which terms of
equation 11 are dominant. For ceramic output capacitors the ESR-
COUT and ESLCOUT are virtually zero, so the output voltage ripple
will be dominated by the third term of equation 11:
=
∆VOUT
∆IL
8 fSWCOUT (12)
To reduce the voltage ripple of a design using ceramic output
capacitors, simply: increase the total capacitance, reduce the
inductor current ripple (that is, increase the inductor value), or
increase the switching frequency.
For electrolytic output capacitors the value of capacitance will
be relatively high, so the third term in equation 11 will be very
small. The output voltage ripple will be determined primarily by
the first two terms of equation 11:
=
∆VOUT ∆IL × ESRCOUT
× ESLCOUT
VIN–VOUT
LO
+
(13)
To reduce the voltage ripple of a design using electrolytic output
capacitors, simply: decrease the equivalent ESRCO and ESLCO
by using a high(er) quality capacitor, or add more capacitors in
parallel, or reduce the inductor current ripple (that is, increase the
inductor value).
The ESR of some electrolytic capacitors can be quite high so
Allegro recommends choosing a quality capacitor for which the
ESR or the total impedance is clearly documented in the data-
sheet. Also, the ESR of electrolytic capacitors usually increases
significantly at cold ambients, as much as 10×, which increases
the output voltage ripple and, in most cases, reduces the stability
of the system.
The transient response of the regulator depends on the quantity
and type of output capacitors. In general, minimizing the ESR of
the output capacitance will result in a better transient response.
The ESR can be minimized by simply adding more capacitors in
parallel or by using higher quality capacitors. At the instant of a
fast load transient (di/dt), the output voltage will change by the
amount:
= × +
∆VOUT ∆ILOAD
di
dt ESLCOUT
ESRCOUT (14)
Wide Input Voltage, 2.4 MHz, 2.5 A Asynchronous Buck Regulator
With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output
A8589
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After the load transient occurs, the output voltage will deviate
from its nominal value for a short time. This time will depend
on the system bandwidth, the output inductor value, and output
capacitance. Eventually, the error amplifier will bring the output
voltage back to its nominal value.
The speed at which the error amplifier brings the output voltage
back to its setpoint depends mainly on the closed-loop bandwidth
of the system. A higher bandwidth usually results in a shorter
time to return to the nominal voltage. However, with a higher
bandwidth system, it may be more difficult to obtain acceptable
gain and phase margins. Selection of the compensation com-
ponents (RZ, CZ, and CP) are discussed in more detail in the
Compensation Components section of this datasheet.
LOW-IQ PFM OUTPUT VOLTAGE RIPPLE CALCULATION
After choosing an output inductor and output capacitor(s), its
importanttocalculatetheoutputvoltageripple(ΔVOUT
(PFM))
that will occur during Low-IQ PFM mode. With ceramic output
capacitors the output voltage ripple in PWM mode is usually
negligible, but that is not the case during Low-IQ PFM mode.
First, calculate the high-side MOSFET on-time and off-time. The
on-time is defined as the time it takes for the inductor current to
reach the peak current threshold, IPEAK(LO_IQ)
:
=
tON VIN – VOUT – IPEAK(LO_IQ) × (
RDS(on)HS + DCRLO
)
IPEAK(LO_IQ) × LO(15)
Where RDS(on)istheon-resistance(110mΩ(typ))ofthehigh-
side MOSFET and DCRLO is the DC resistance of the output
inductor, LO. For relatively low input voltages, the on-time dur-
ing Low-IQ PFM mode is internally limited to about 4.1 µs.
The off-time is defined as the time it takes for the inductor cur-
rent to decay from IPEAK(LO_IQ) to 0 A:
=
tOFF
IPEAK(LO_IQ) × LO
VOUT+Vf
(16)
Finally, the Low-IQ PFM output voltage ripple can be calculated:
=
∆VOUT(LO_IQ)
IPEAK(LO_IQ) × (tON + tOFF)
2 × C
OUT
(17)
If the Low-IQ PFM output voltage ripple appears to be too high,
then the output capacitance should be increased and/or the output
inductance should be decreased. Decreasing the inductor value
has the drawback of increasing the ripple current, so a higher load
current will be required to transition from discontinuous conduc-
tion mode (DCM) to continuous conduction mode (CCM). This
might not be acceptable.
In general, the Low-IQ PFM output voltage ripple increases as
the input voltage decreases. Also, from equation 15, note that
tON increases as the VOUT
/ VIN ratio increases (that is, as VIN
decreases). If the VOUT
/ VIN ratio is too high, the system is not
able to achieve IPEAK(LO_IQ) in only one PFM pulse. In this case
the on-time is limited to approximately 4.1 µs and a second PFM
pulse is required, about tOFF(PFM) later, as shown in figure 5.
INPUT CAPACITORS
Three factors should be considered when choosing the input
capacitors. First, they must be chosen to support the maximum
expected input surge voltage with adequate design margin.
Second, the capacitor rms current rating must be higher than the
expected rms input current to the regulator. Third, they must have
enough capacitance and a low enough ESR to limit the input
voltage dV/dt to something much less than the hysteresis of the
VIN pin UVLO circuitry ( VINUV(HYS) , nominally 400 mV for the
A8589), at maximum loading and minimum input voltage.
0.55
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
0 10 20 30 50 60 70 80 1009040
Duty Cycle (%)
Ir
m
s / IOUT
Figure 18: Input Capacitor Ripple versus Duty Cycle
Wide Input Voltage, 2.4 MHz, 2.5 A Asynchronous Buck Regulator
With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output
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The input capacitors must deliver the rms current according to:
=×
Irms IOUT D(1– D) (18)
where the duty cycle is:
D≈(VOUT+ V f
)/(VIN+ V f ) (19)
and Vf is the forward voltage of the asynchronous diode, D1
.
Figure 18 shows the normalized input capacitor rms current
versus duty cycle. To use this graph, simply find the operational
duty cycle (D) on the x-axis and determine the input/output cur-
rent multiplier on the y-axis. For example, at a 20% duty cycle,
the input/output current multiplier is 0.40. Therefore, if the
regulator is delivering 2.5 A of steady-state load current, the input
capacitor(s) must support 0.40 × 2.5 A, or 1.0 Arms.
The input capacitor(s) must limit the voltage deviations at the
VIN pin to something significantly less than the A8589 VIN pin
UVLO hysteresis during maximum load and minimum input
voltage. The minimum input capacitance can be calculated as
follows:
≥×
××
CIN
IOUT
∆VIN(MIN)
fOSC
0.85
×
D(1– D)(20)
whereΔVIN(MIN) is chosen to be much less than the hysteresis of
theVINpinUVLOcomparator(ΔVIN(MIN)≤150mVisrecom-
mended).
The D × (1-D) term in equation 20 has an absolute maximum
value of 0.25 at 50% duty cycle. So, for example, a very conser-
vative design, based on: IOUT = 2.5 A, fOSC = 85% of 425 kHz,
D×(1-D)=0.25,andΔVIN = 150 mV, yields:
≥=
×
×
CIN 361 (kHz) 150 (mV) 11.5 µF
2.5 (A) 0.25
A good design should consider the DC bias effect on a ceramic
capacitor: as the applied voltage approaches the rated value, the
capacitance value decreases. This effect is very pronounced with
the Y5V and Z5U temperature characteristic devices (as much as
90% reduction) so these types should be avoided. The X5R and
X7R type capacitors should be the primary choices due to their
stability versus both DC bias and temperature.
For all ceramic capacitors, the DC bias effect is even more pro-
nounced on smaller sizes of device case, so a good design uses
the largest affordable case size (such as 1206 or 1210). Also, it is
advisable to select input capacitors with plenty of design margin
in the voltage rating to accommodate the worst case transient
input voltage (such as a load dump as high as 40 V for automo-
tive applications).
ASYNCHRONOUS DIODE (D1)
There are three requirements for the asynchronous diode. First,
the asynchronous diode must be able to withstand the regulator
input voltage when the high-side MOSFET is on. Therefore, one
should choose a diode with a reverse voltage rating ( VR
) higher
than the maximum expected input voltage (that is, the surge volt-
age).
Second, the forward voltage of the diode ( Vf
) should be mini-
mized or the regulator efficiency suffers. Also if Vf is too high,
the A8589 missing diode protection function could be falsely
activated. A Schottky type diode that can maintain a very low
Vf when the regulator output is shorted to ground, at the coldest
ambient temperature, is highly recommended.
Third, the asynchronous diode must conduct the output current
when the high-side MOSFET is turned off. Therefore, the average
forward current rating of this diode (If (AVG)) must be high enough
to deliver the load current according to
If(AVG)≥IOUT(MAX) ( 1 – DMIN ) (21)
where DMIN is the minimum duty cycle defined in equation 19,
and IOUT(MAX) is the maximum continuous output current of the
regulator.
BOOTSTRAP CAPACITOR
A bootstrap capacitor must be connected between the BOOT and
SW pins to provide the floating gate drive to the high-side MOS-
FET. Usually, 47 nF is an adequate value. This capacitor should
be a high-quality ceramic capacitor, such as an X5R or X7R, with
a voltage rating of at least 16 V.
TheA8589incorporatesa10Ωlow-sideMOSFETtoensurethat
the bootstrap capacitor is always charged, even when the regula-
tor is lightly loaded or pre-biased.
Wide Input Voltage, 2.4 MHz, 2.5 A Asynchronous Buck Regulator
With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output
A8589
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SOFT START AND HICCUP MODE TIMING (CSS)
The soft start time of the A8589 is determined by the value of the
capacitance at the soft start pin, CSS
. When the A8589 is enabled,
the voltage at the soft start pin starts from 0 V and is charged by
the soft start current, ISSSU
. However, PWM switching does not
begin instantly because the voltage at the soft start pin must rise
above 400 mV. The soft start delay (tD(SS)
) can be calculated as:
=×
tD(SS) CSS ISSSU
400 (mV) (22)
If the A8589 is starting with a very heavy load, a very fast soft
start time may cause the regulator to exceed the pulse-by-pulse
overcurrent threshold. This occurs because the total of the full
load current, the inductor ripple current, and the additional cur-
rent required to charge the output capacitors:
ICO = COUT×VOUT / tSS (23)
is higher than the pulse-by-pulse current threshold, as shown in
figure 19. This phenomena is more pronounced when using high
value electrolytic type output capacitors. To avoid prematurely
triggering hiccup mode the soft start capacitor, CSS , should be
calculated according to:
≥× ×
CSS
COUT
VOUT
ISSSU
×
0.8 (V) ICO (24)
where VOUT is the output voltage, COUT is the output capaci-
tance, ICO is the amount of current allowed to charge the output
capacitance during soft start (recommended: 0.1 A < ICO < 0.3 A).
Higher values of ICO result in faster soft start times. However,
lower values of ICO ensure that hiccup mode is not falsely trig-
gered. Allegro recommends starting the design with an ICO of
0.1 A and increasing it only if the soft start time is too slow. If a
non-standard capacitor value for CSS is calculated, the next larger
value should be used.
The output voltage ramp time, tSS , can be calculated by using
either of the following methods:
=
=
×
tSS
tSS
COUT
CSS
ISSSU
VOUT
×
0.8 (V)
or ICO (25)
(26)
When the A8589 is in hiccup mode, the soft start capacitor is
used as a timing capacitor and sets the hiccup period. The soft
start pin charges the soft start capacitor with ISSSU during a
startup attempt and discharges the same capacitor with ISSHIC
between startup attempts. Because the ratio ISSSU / ISSHIC is
approximately 4:1, the time between hiccups will be about four
times as long as the startup time. Therefore, the effective duty-
cycle of the A8589 will be very low and the junction temperature
will be kept low.
COMPENSATION COMPONENTS (RZ, CZ, AND CP)
To properly compensate the system, it is important to understand
where the buck power stage, load resistance, and output capaci-
tance form their poles and zeros in frequency. Also, it is impor-
tant to understand that the (Type II) compensated error amplifier
introduces a zero and two more poles, and where these should be
placed to maximize system stability, provide a high bandwidth,
and optimize the transient response.
First, consider the power stage of the A8589, the output capaci-
tors, and the load resistance. This circuitry is commonly referred
as the control-to-output transfer function. The low frequency
gain of this circuitry depends on the COMP to SW current gain
(gmPOWER
), and the value of the load resistor (RL). The DC gain
(GCO(0Hz)) of the control-to-output is:
G
CO(0Hz) = gmPOWER × RL (27)
The control-to-output transfer function has a pole (fP1), formed
Figure 19: Output Current (ICO) During Startup
Output
capacitor
current, ICO
}
I
LIM
ILOAD
tSS
Wide Input Voltage, 2.4 MHz, 2.5 A Asynchronous Buck Regulator
With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output
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by the output capacitance (COUT) and load resistance (RL),
located at:
=
fP1 COUT
RL
× ×
2�
1
(28)
The control-to-output transfer function also has a zero (fZ1)
formed by the output capacitance (COUT) and its associated ESR:
=
fZ1 COUT
ESR
× ×
2�
1
(29)
For a design with very low-ESR type output capacitors (such as
ceramic or OS-CON™ output capacitors), the ESR zero (fZ1
)
is usually at a very high frequency, so it can be ignored. On the
other hand, if the ESR zero falls below or near the 0 dB crossover
frequency of the system (as is the case with electrolytic output
capacitors), then it should be cancelled by the pole formed by the
CP capacitor and the RZ resistor (discussed and identified later
as fP3).
A Bode plot of the control-to-output transfer function for the
configuration shown in typical application schematic B (VOUT
= 5.0 V, IOUT = 2.5 A, RL=2Ω)isshowninFigure20.Thepole
at fP1 can easily be seen at 1.9 kHz while the ESR zero (fZ1)
occurs at a very high frequency, 636 kHz (this is typical for a
design using ceramic output capacitors). Note: There is more
than 90° of total phase shift because of the double-pole at half the
switching frequency.
Next, consider the feedback resistor divider (RFB1 and
RFB2), and the error amplifier (gm) and compensation network
RZ-CZ-CP. It greatly simplifies the transfer function deriva-
tion if RO >> RZ
, and CZ >> CP . In most cases, RO
>2MΩ,
1kΩ<RZ <100kΩ,220pF<CZ < 47 nF, and CP < 50 pF, so the
following equations are very accurate.
The low frequency gain of the control section (GC(0Hz)) is formed
by the feedback resistor divider and the error amplifier. It can be
calculated using:
=× ×
GC(0Hz)
RFB2 RO
RFB1+RFB2
gm
=× ×
VFB RO
VOUT
gm
=×
VFB
VOUT
AVOL (30)
where
VOUT is the output voltage,
VFB is the reference voltage (0.8 V),
gm is the error amplifier transconductance (750 µA/V ), and
RO is the error amplifier output impedance (A
VOL/gm
).
The transfer function of the Type-II compensated error amplifier
has a (very) low frequency pole (fP2
) dominated by the output
error amplifier output impedance (RO) and the CZ compensation
capacitor:
=
fP2 CZ
RO
× ×
2�
1
(31)
The transfer function of the Type-II compensated error amplifier
also has frequency zero (fZ2) dominated by the RZ resistor and
the CZ capacitor:
60
40
20
0
-20
-40
-60
180
90
0
-90
-180
101106
105
104
103
102
Frequency (Hz)
Phase (°) Gain (dB)
Double Pole at
212.5 kHz
fP1 = 1.9 kHz
fZ1 = 636 kHz
GCO(0Hz) = 15.1 dB
Figure 20: Control-to-Output Bode Plot
Wide Input Voltage, 2.4 MHz, 2.5 A Asynchronous Buck Regulator
With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output
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=
fZ2 CZ
RZ
× ×
2�
1
(32)
Lastly, the transfer function of the Type-II compensated error
amplifier has a (very) high frequency pole (fP3) dominated by the
RZ resistor and the CP capacitor:
=
fP3 CP
RZ
× ×
2�
1
(33)
A Bode plot of the error amplifier and its compensation network
is shown in Figure 21, fP2
, fP3
, and fZ2 are indicated on the mag-
nitude plot. Notice that the zero (fZ2 at 3.8 kHz) has been placed
so that it is just above the pole at fP1 previously shown in the
control-to-output Bode plot (Figure 20) at 1.9 kHz. Placing fZ2
just above fP1 will result in excellent phase margin, but relatively
slow transient recovery time, as will be shown later.
Finally, consider the combined Bode plot of both the control-
to-output and the compensated error amplifier (Figure 22).
Careful examination of this plot shows that the magnitude and
phase of the entire system (red curve) are simply the sum of the
error amplifier response (blue curve) and the control-to-output
response (green curve). The bandwidth of this system (fC) is
60 kHz, the phase margin is 69 degrees, and the gain margin is
14 dB.
Complete designs for several common output voltages, at fSW of
425 kHz, 1 MHz, and 2 MHz are provided in Table 3 on page 34.
A GENERALIZED TUNING PROCEDURE
This section presents a methodology to systematically apply the
design considerations provided above.
1. Choose the system bandwidth (fC ). This is the frequency at
which the magnitude of the gain crosses 0 dB. Recommended
values for fC
, based on the PWM switching frequency, are in the
range fSW / 20 < fC < fSW / 7.5. A higher value of fC generally
provides a better transient response, while a lower value of fC
generally makes it easier to obtain higher gain and phase margins.
2. Calculate the RZ resistor value. This sets the system bandwidth
(fC):
=
RZfCgmPOWERx gm
COUT
VOUT
VFB
× × ×
×
2�(34)
3. Determine the frequency of the pole (fP1). This pole is formed
by COUT and RL. Use equation 28 (repeated here):
60
40
20
0
-20
-40
-60
180
90
0
-90
-180
101106
105
104
103
102
Frequency (Hz)
Phase (°) Gain (dB)
GM = 14 dB
PM = 69°
fC = 60 kHz
Figure 21: Type-II Compensated Error Amplier
Figure 22: Bode Plot of the Complete System (red
curves)
60
40
20
0
-20
-40
-60
180
90
0
-90
-180
101106
105
104
103
102
Frequency (Hz)
Phase (°) Gain (dB)
fP3 ≈ 90 kHz
fP2 ≈ 80 Hz
fZ2 ≈ 3.8 kHz
GC(0Hz)
= 49 dB
Wide Input Voltage, 2.4 MHz, 2.5 A Asynchronous Buck Regulator
With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output
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=
fP1 COUT
RL
× ×
2�
1
4. Calculate a range of values for the CZ capacitor. Use the fol-
lowing:
< <
CZ
fC
RZ
× ×
2�
4
fP1
RZ
× × ×
2�1.5
1
(35)
To maximize system stability (that is, to have the greatest gain
margin), use a higher value of CZ . To optimize transient recovery
time, although at the expense of some phase margin, use a lower
value of CZ .
Figure 23 compares the output voltage recovery time due to a 1 A
load transient for the system shown in Figure 22 (fZ2 = 3.8 kHz,
69° phase margin) and a system with fZ2 at 1/4 the crossover fre-
quency (15 kHz). The system with fZ2 at 15 kHz has 60° of phase
margin,butrecoversmuchfaster(≈3×)thantheothersystem.
5. Calculate the frequency of the ESR zero (fZ1) formed by the
output capacitor(s). Use equation 29 (repeated here):
=
fZ1 COUT
ESR
× ×
2�
1
If fZ1 is at least one decade higher than the target crossover
frequency (fC) then fZ1 can be ignored. This is usually the case
for a design using ceramic output capacitors. Use equation 33 to
calculate the value of CP by setting fP3 to either 5 × fC or fSW / 2,
whichever is higher.
Alternatively, if fZ1 is near or below the target crossover fre-
quency (fC), then use equation 33 to calculate the value of CP by
setting fP3 equal to fZ1. This is usually the case for a design using
high ESR electrolytic output capacitors.
0
5.00
4.99
4.98
4.97
4.96
4.95
4.94
4.93
40 80 120
Time (µs)
160 200 240
Voltage (V)
fZ2 = 15 kHz
fZ2 = 3.8 kHz
Figure 23: Transient Recovery Comparison for fZ2 at
3.8 kHz / 69° and 15 kHz / 60°
Wide Input Voltage, 2.4 MHz, 2.5 A Asynchronous Buck Regulator
With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output
A8589
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VOUT
(V)
fSW
(MHz)
RFSET
(kΩ)
LO
(µH)
CO2
(µF)
RFB1
(kΩ)
RFB2
(kΩ)
CFB
(pF)
RZ + CZ // CP
BIAS Pin Modes
RZ
(kΩ)
CZ
(pF)
CP
(pF)
1.51
0.425 59.0
3.3 80 63.4 +3.83 76.8 N/A 24.3 560 15 3.3 V EXT PWM and PFM
3.3 8.2 40 147 47.0 10 26.1 560 15 Connected to
VOUT PWM and PFM
5.0 10 50 221 + 0.499 42.2 8 49.9 270 8 Connected to
VOUT PWM and PFM
6.5 15 60 287 +6.5 41.2 6 78.7 180 4.7 3.3 V or 5.0 V
LDO PWM and PFM
3.3
1 23.7
3.3 20 147 47.0 10 18.2 560 15 Connected to
VOUT PWM and PFM
5.0 4.7 30 221 + 0.499 42.2 8 41.2 270 8 Connected to
VOUT PWM and PFM
6.5 6.8 40 287 +6.5 41.2 6 71.5 180 4.7 3.3 V or 5.0 V
LDO PWM and PFM
3.3
2 10.5
1.5 10 147 47.0 10 11.5 680 15 Connected to
VOUT PWM and PFM
5.0 2.2 15 221 + 0.499 42.2 8 26.1 330 8 Connected to
VOUT PWM and PFM
6.5 3.3 20 287 +6.5 41.2 6 45.3 180 4.7 3.3 V or 5.0 V
LDO PWM and PFM
1If BIAS is not connected to VOUT, then the minimum external load must be ≥75 µA at all temperatures. No load operation is okay at approximately
25ºC to 75ºC only.
2Negative tolerance and DC-bias effect must be considered when choosing components to obtain CO.
Table 3: Recommended Component Values
Wide Input Voltage, 2.4 MHz, 2.5 A Asynchronous Buck Regulator
With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output
A8589
35
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
The power dissipated in the A8589 is the sum of the power dis-
sipated from the VIN supply current (PIN), the power dissipated
due to the switching of the high-side power MOSFET (PSW
), the
power dissipated due to the rms current being conducted by the
high-side power MOSFET (PCOND
), and the power dissipated by
the gate driver (PDRIVER).
The power dissipated from the VIN supply current can be calcu-
lated using the following equation:
PIN=VIN × IQ+(VIN–VGS) × QG × fSW (36)
where
VIN is the input voltage,
IQ is the input quiescent current drawn by the A8589 (nominally
2.5 mA),
VGS is the MOSFET gate drive voltage (typically 5 V),
QG is the MOSFET gate charge (approximately 2.5 nC), and
fSW is the PWM switching frequency.
The power dissipated by the high-side MOSFET during PWM
switching can be calculated using the following equation:
=
PSW
VIN IOUT fSW
(tr + tf )
× × ×
2
(37)
where
VIN is the input voltage,
IOUT is the regulator output current,
fSW is the PWM switching frequency, and
tr and tf are the rise and fall times measured at the SW node.
The exact rise and fall times at the SW node depend on the
external components and PCB layout so each design should be
measured at full load. Approximate values for both tr and tf range
from 10 to 15 ns.
The power dissipated by the internal high-side MOSFET while it
is conducting can be calculated using the following equation:
=
PCOND Irms(FET) RDS(on)HS
VOUT+Vf
VIN+Vf
×
×+12
2
∆IL
2
IOUT
2
=RDS(on)HS
×(38)
where
IOUT is the regulator output current,
ΔIL is the peak-to-peak inductor ripple current,
RDS(on)HS is the on-resistance of the high-side MOSFET, and
Vf is the forward voltage of the asynchronous diode.
The RDS(on)of the high-side MOSFET has some initial tolerance
plus an increase from self-heating and elevated ambient tempera-
tures. A conservative design should accommodate an RDS(on) with
at least a 15% initial tolerance plus 0.39%/°C increase due to
temperature.
The sum of the power dissipated by the internal gate driver can
be calculated using the following equation:
PDRIVER = QG×VGS × fSW (39)
where
VGS is the gate drive voltage (typically 5 V),
QG is the gate charge to drive MOSFET to VGS = 5 V (about
2.5 nC), and
fSW is the PWM switching frequency.
Finally, the total power dissipated (PTOTAL) is the sum of the
previous equations:
PTOTAL = PIN + PSW + PCOND + PDRIVER (40)
The average junction temperature can be calculated with the fol-
lowing equation:
TJ = PTOTAL + RθJA + TA (41)
where PTOTAL is the total power dissipated as described in
equation 40, RθJA is the junction-to-ambient thermal resistance
(34°C/W on a 4-layer PCB), and TA is the ambient temperature.
The maximum junction temperature will be dependent on how
efficiently heat can be transferred from the PCB to ambient air. It
is critical that the thermal pad on the bottom of the IC should be
connected to a at least one ground plane using multiple vias.
As with any regulator, there are limits to the amount of heat that
can be dissipated before risking thermal shutdown. There are
tradeoffs between: ambient operating temperature, input voltage,
output voltage, output current, switching frequency, PCB
thermal resistance, airflow, and other nearby heat sources. Even
a small amount of airflow will reduce the junction temperature
considerably.
Power Dissipation and Thermal Calculations
Wide Input Voltage, 2.4 MHz, 2.5 A Asynchronous Buck Regulator
With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output
A8589
36
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A good PCB layout is critical if the A8589 is to provide clean,
stable output voltages. Follow these guidelines to insure a good
PCB layout. Figure 24 shows a typical buck converter schematic
with the critical power paths/loops. Figure 25 shows an example
PCB component placement and routing with the same critical
power paths/loops as shown in the schematic.
1. By far, the highest di/dt in the asynchronous buck regula-
tor occurs at the instant the high-side MOSFET turns on and the
capacitance of the asynchronous Schottky diode (200 to 1000 pF)
is quickly charged to VIN . The ceramic input capacitors must
deliver this fast, short pulse of current. Therefore the loop, from
the ceramic input capacitors through the high-side MOSFET and
into the asynchronous diode to ground, must be minimized. Ide-
ally these components are all connected using only the top metal
layer (that is, do not use vias to other power/signal layers).
2. When the high-side MOSFET is on, current flows from the
input supply and capacitors, through the high-side MOSFET, into
the load via the output inductor, and back to ground. This loop
should be minimized and have relatively wide traces.
3. When the high-side MOSFET is off, free-wheeling current
flows from ground, through the asynchronous diode, into the load
via the output inductor, and back to ground. This loop should be
minimized and have relatively wide traces.
4. The voltage on the SW node transitions from 0 V to VIN very
quickly and is the root cause of many noise issues. It is best to
place the asynchronous diode and output inductor close to the
A8589 to minimize the size of the SW polygon. Also, keep low
level analog signals (like FB and COMP) away from the SW
polygon.
5. Place the feedback resistor divider (RFB1 and RFB2) very
close to the FB pin. Ground this resistor divider as close as pos-
sible to the A8589.
6. To have the highest output voltage accuracy, the output volt-
age sense trace (from VOUT to RFB1) should be connected as
close as possible to the load.
7. Place the compensation components (RZ, CZ, and CP
) as
close as possible to the COMP pin. Place vias to the GND plane
as close as possible to these components.
8. Place the soft start capacitor (CSS) as close as possible to the
SS pin. Place a via to the GND plane as close as possible to this
component.
9. Place the boot strap capacitor (CBOOT) near the BOOT pin
and keep the routing from this capacitor to the SW polygon as
short as possible.
10. When connecting the input and output ceramic capacitors,
use multiple vias to GND and place the vias as close as possible
to the pads of the components.
11. To minimize PCB losses and improve system efficiency,
the input and output traces should be as wide as possible and be
duplicated on multiple layers, if possible.
12. To improve thermal performance, place multiple vias to the
GND plane around the anode of the asynchronous diode.
13. The thermal pad under the A8589 must connect to the GND
plane using multiple vias. More vias will ensure the lowest junc-
tion temperature and highest efficiency.
14. EMI/EMC issues are always a concern. Allegro recommends
having component locations for an RC snubber from SW to
ground. The resistor should be 1206 size.
PCB Component Placement and Routing
Wide Input Voltage, 2.4 MHz, 2.5 A Asynchronous Buck Regulator
With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output
A8589
37
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Figure 25: Example PCB Component Placement and Routing
2
1
3
Loop 1 (red). At the instant Q1 turns on, Schottky diode D1,
which is very capacitive, must be very quickly shut off (only
5 to 15 ns of charging time). This spike of charging current must
come from the local input ceramic capacitor, CIN1. This spike
of current is quite large and will be an EMI/EMC issue if loop 1
(red) is not minimized. Therefore, the input capacitor CIN1 and
Schottky diode D1 must be placed be on the same (top) layer, be
located near each other, and be grounded at virtually the same
point on the PCB.
Loop 2 (magenta). When Q1 is off, free-wheeling inductor
current must flow from ground through diode D1 (SW will be
at –Vf
), into the output inductor, out to the load and return via
ground. While Q1 is off, the voltage on the output capacitors
decreases. The output capacitors and Schottky diode D1 should
be placed on the same (top) layer, be located near each other, and
be sharing a good, low inductance ground connection.
Loop 3 (blue). When Q1 is on, current will flow from the input
supply and input capacitors through the output inductor and into
the load and the output capacitors. At this time the voltage on the
output capacitors increases.
D1
CO3
LO
VOUT
CO4CO2CO1
SW
CIN1CIN3 CIN2 R
snub
C
snub
Q1
VIN
LOAD
2
1
3
Figure 24: Typical B uck Converter with Critical Paths/Loops Shown
Wide Input Voltage, 2.4 MHz, 2.5 A Asynchronous Buck Regulator
With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output
A8589
38
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
VOUT
Vin
EN
C1
1uF
CSS
22nF
RFB2
47K
RFB1147K
CIN2
4.7uF
50V
1210
RFSET
59K
Mode
D1
2A/40V
SMP
RZ
26.1K
CP
15pF
CZ
560pF CFB
10pF
RPU
10K
3.3V
C= 38.2uF to 42.4uF total
OUT
at 3.3V bias and 10% tolerance
CIN1
4.7uF
50V
1210
CIN3
0.47uF
100V
0805
CIN4
47nF
50V
0603
NPOR
PWM/PFMn
6
FSET
8
VIN
1
GND
5
NPOR 7
COMP
9
BOOT 16
SW 14
FB 10
BIAS 11
SLEEPn
4
SS
3
VREG
12
VIN
2SW 15
GND
13
CO3
0.47uF
100V
0805
CO4
47nF
50V
0603
CO1
22uF
16V X7R
1210
CO2
22uF
16V X7R
1210
CBOOT
47 nF
LO 8.2 µH
A8589
Typical Applications Schematic: 12VIN/3.3VOUT/2.5A at 425KHz
Figure 26: Typical Application Schematic A. Conguration for VIN = 12 V , VOUT = 3.3 V, IOUT = 2.5 A at 425 kHz
Figure 27: Typical Application Schematic B. Congured for VIN = 12 V , VOUT = 5.0 V, IOUT = 2.5 A at 425 kHz
TYPICAL APPLICATIONS SCHEMATICS
Vin
CIN1
4.7 µF
50 V
1210
CIN2
4.7 µF
50 V
1210
CIN3
0.47 µF
100 V
0805
CIN4
47 nF
50 V
0603
CP
8.0 pF RZ
49.9 K
CZ
270 pF
CSS
22 nF RFSET
59 K C1
1 µF
EN
Mode
1
2
5
13
9
3
8
12
4
67
10
11
16
14
15
VIN
VIN
GND
GND
COMP
SS
FSET
VREG
SLEEPn
SW
SW
BOOT
BIAS
FB
PWM/PFMn NPOR
LO 10 µH
CBOOT
47 nF
D2
2A/40 V
SMP
CO1
22 µF
16 V X7R
1210
CO2
22 µF
16 V X7R
1210
CO3
22 µF
16 V X7R
1210
CO4
0.47 µF
100 V
0805
CO5
47 µF
50 V
0603
RFB1
221 K
RFB
499
CFB
8.0 pF
RFB2
42.2 K 3.3 V
RPU
10 k
C= 53.9 µF to 59.9 µF total
OUT
at 5.0 V bias and 10% tolerance
NPOR
VOUT
A8589
Wide Input Voltage, 2.4 MHz, 2.5 A Asynchronous Buck Regulator
With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output
A8589
39
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Package Outline Drawing
A
1.20 MAX
0.15
0.00
0.30
0.19
0.20
0.09
8º
0º
0.60 ±0.15
1.00 REF
C
SEATING
PLANE
C0.10
16X
0.65 BSC
0.25 BSC
21
16
5.00 ±0.10
4.40 ±0.10 6.40 ±0.20
GAUGE PLANE
SEATING PLANE
A
B
B
C
D
Exposed thermal pad (bottom surface); dimensions may vary with device
6.10
0.65
0.45
1.70
3.00
3.00
16
21
1
C
D
Branded Face
3 NOM
3 NOM
For Reference Only – Not for Tooling Use
(Reference MO-153 ABT)
Dimensions in millimeters. NOT TO SCALE
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
PCB Layout Reference View
Terminal #1 mark area
Reference land pattern layout (reference IPC7351 SOP65P640X110-17M);
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances; when
mounting on a multilayer PCB, thermal vias at the exposed thermal pad land
can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)
Branding scale and appearance at supplier discretion
Standard Branding Reference View
YYWW
NNNNNNN
LLLL
= Device part number
= Supplier emblem
= Last two digits of year of manufacture
= Week of manufacture
= Characters 5-8 of lot number
N
Y
W
L
Figure 28: Package LP, 16-Pin TSSOP with Exposed Thermal Pad
Wide Input Voltage, 2.4 MHz, 2.5 A Asynchronous Buck Regulator
With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output
A8589
40
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
OS-CON is a trademark of SANYO North America Corporation.
Copyright ©2013-2015, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
Revision History
Revision Revision Date Description of Revision
1 September 9, 2014 Revised equation 8 on p. 26
2 February 11, 2015 Revised Table 2 and PWM Base Frequency section