IDT70V7339S133DDI - Integrated Device Technology

APRIL 2010

DSC 5628/9



Functional Block Diagram

Features:

◆512K x 18 Synchronous Bank-Switchable Dual-ported

SRAM Architecture

–64 independent 8K x 18 banks

– 9 megabits of memory on chip

◆Bank access controlled via bank address pins

◆High-speed data access

– Commercial: 3.4ns (200MHz)/3.6ns (166MHz)/

4.2ns (133MHz) (max.)

– Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)

◆Selectable Pipelined or Flow-Through output mode

◆Counter enable and repeat features

◆Dual chip enables allow for depth expansion without

additional logic

◆Full synchronous operation on both ports

– 5ns cycle time, 200MHz operation (14Gbps bandwidth)

– Fast 3.4ns clock to data out

– 1.5ns setup to clock and 0.5ns hold on all control, data, and

address inputs @ 200MHz

– Data input, address, byte enable and control registers

– Self-timed write allows fast cycle time

◆Separate byte controls for multiplexed bus and bus

matching compatibility

◆LVTTL- compatible, 3.3V (±150mV) power supply

for core

◆LVTTL compatible, selectable 3.3V (±150mV) or 2.5V

(±100mV) power supply for I/Os and control signals on

each port

◆Industrial temperature range (-40°C to +85°C) is

available at 166MHz and 133MHz

◆Available in 208-pin fine pitch Ball Grid Array (fpBGA) and

256-pin Ball Grid Array (BGA)

◆Supports JTAG features compliant with IEEE 1149.1

◆Green parts available, see ordering information

HIGH-SPEED 3.3V 512K x 18

SYNCHRONOUS

BANK-SWITCHABLE

DUAL-PORT STATIC RAM

WITH 3.3V OR 2.5V INTERFACE

IDT70V7339S

8Kx18

MEMORY

ARRAY

(BANK 63)

MUX

PL/FT

OPT

CLK

ADS

CNTEN

REPEAT

R/W

I/O

0L-17L

12L

JTAG

8Kx18

MEMORY

ARRAY

(BANK 1)

MUX

8Kx18

MEMORY

ARRAY

(BANK 0)

MUX

CONTROL

LOGIC

I/O

CONTROL

BANK

DECODE

ADDRESS

DECODE

I/O

0R-17R

12R

CONTROL

LOGIC

I/O

CONTROL

BANK

DECODE

ADDRESS

DECODE

5628 drw 01

PL/FT

OPT

CLK

ADS

CNTEN

REPEAT

R/W

TMS

TCK

TRST

TDI

TDO

NOTE:

1. The Bank-Switchable dual-port uses a true SRAM

core instead of the traditional dual-port SRAM core.

As a result, it has unique operating characteristics.

Please refer to the functional description on page 18

for details.

6.42

IDT70V7339S

High-Speed 512K x 18 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Description:

The IDT70V7339 is a high-speed 512Kx18 (9Mbit) synchronous

Bank-Switchable Dual-Ported SRAM organized into 64 independent

8Kx18 banks. The device has two independent ports with separate

control, address, and I/O pins for each port, allowing each port to access

any 8Kx18 memory block not already accessed by the other port.

Accesses by the ports into specific banks are controlled via the bank

address pins under the user's direct control.

Registers on control, data, and address inputs provide minimal setup

and hold times. The timing latitude provided by this approach allows

systems to be designed with very short cycle times. With an input data

Pin Configuration(1,2,3,4)

NOTES:

1. All VDD pins must be connected to 3.3V power supply.

2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is

set to VIL (0V).

3. All VSS pins must be connected to ground supply.

4. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch.

5. This package code is used to reference the package diagram.

6. This text does not indicate orientation of the actual part-marking.

A17

B17

C17

D17

I/O

E16

E17

D16

I/O

C16

B16

I/O

A16

A15

OPT

B15

DDQR

C15

I/O

D15

DDQL

E15

E14

I/O

D14

D13

C12

C14

B14

A14

A12

CNTEN

B12

C11

R/W

D12

D11

REPEAT

C10

B11

ADS

A11

CLK

D10

10L

B13

A13

A10

12L

11L

TDO

TDI

PL/

DDQR

I/O

10L

I/O

DDQL

I/O

11L

DDQR

I/O

10R

DDQL

I/O

11R

I/O

12L

DDQR

I/O

12R

DDQL

I/O

14R

I/O

13R

I/O

14L

DDQR

I/O

13L

DDQL

I/O

15R

I/O

15L

I/O

16R

I/O

16L

DDQR

I/O

17R

TCK

I/O

17L

DDQL

TMS

PL/

TRST

11R

P12

CNTEN

U10

P10

T11

R/W

P11

CLK

R12

T12

U12

P13

12R

R13

T13

U13

U14

T14

R14

P14

P15

I/O

R15

DDQL

T15

U15

OPT

U16

U17

I/O

T16

T17

R17

DDQR

R16

I/O

P17

P16

N17

I/O

N16

N15

DDQL

N14

I/O

M17

DDQR

M16

I/O

M15

M14

L17

I/O

L16

L15

I/O

L14

K17

K16

I/O

K15

DDQL

K14

I/O

J17

DDQR

J16

J15

J14

H17

I/O

H16

H15

H14

G17

G16

I/O

G15

DDQL

G14

F17

DDQR

F16

F14

70V7339BF

BF-208

(5)

208-Pin fpBGA

Top View

(6)

F15

I/O

R11

ADS

B10

C13

R10

T10

10R

5628 drw 02c

11/20/01

unidirectional or bidirectional data flow in bursts. An automatic power down

feature, controlled by CE0 and CE1, permits the on-chip circuitry of each

port to enter a very low standby power mode. The dual chip enables also

facilitate depth expansion.

The 70V7339 can support an operating voltage of either 3.3V or 2.5V

on one or both ports, controllable by the OPT pins. The power supply for

the core of the device(VDD) remains at 3.3V. Please refer also to the

functional description on page 18.

6.42

IDT70V7339S

High-Speed 512K x 18 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Pin Configuration(1,2,3,4) (con't.)

NOTES:

1. All VDD pins must be connected to 3.3V power supply.

2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is

set to VIL (0V).

3. All VSS pins must be connected to ground supply.

4. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.

5. This package code is used to reference the package diagram.

6. This text does not indicate orientation of the actual part-marking.

70V7339BC

BC-256(5)

256-Pin BGA

Top View(6)

E16

I/O

D16

I/O

C16

I/O

B16

A16

A15

B15

C15

D15

E15

I/O

E14

D14

D13

C12

C14

OPT

B14

A14

A12

B12

C11

ADS

D12

DDQR

D11

DDQR

C10

CLK

B11

REPEAT

A11

CNTEN

DDQR

DDQL

D10

DDQL

B13

A13

A10

DDQR

12L

10L

DDQL

BA1

DDQL

PL/

TDO

I/O

TDI

I/O

10R

I/O

10L

DDQL

I/O

11L

I/O

11R

DDQL

I/O

12L

DDQR

I/O

12R

DDQR

I/O

13L

I/O

14R

I/O

13R

DDQL

I/O

14L

DDQL

I/O

15L

I/O

15R

DDQR

I/O

16R

I/O

16L

DDQR

I/O

17R

PL/

I/O

17L

TMS

TRST

TCK

P12

P10

CLK

T11

CNTEN

P11

ADS

R12

T12

P13

R13

T13

12R

T14

R14

OPT

P14

P15

R15

T15

T16

R16

P16

I/O

N16

N15

I/O

N14

M16

M15

I/O

M14

I/O

L16

I/O

L15

L14

I/O

K16

I/O

K15

K14

J16

I/O

J15

I/O

J14

I/O

H16

I/O

H15

H14

G16

G15

G14

I/O

F16

I/O

F14

I/O

F15

R11

REPEAT

11R

11L

B10

R/W

C13

10R

R10

R/W

T10

E10

E11

E12

E13

DDQR

F10

F12

F13

DDQR

G10

G11

G12

G13

DDQL

H10

H11

H12

H13

DDQL

J10

J11

J12

J13

DDQR

DDQL

K10

K11

K12

L10

L11

L12

M10

M11

M12

DDQR

N10

DDQR

N11

DDQL

N12

DDQL

K13

DDQR

L13

DDQL

M13

DDQL

N13

F11

5628 drw 02d

11/20/01

6.42

IDT70V7339S

High-Speed 512K x 18 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Pin Names

Left Port Right Port Names

0L,

0R,

Chip Enab les

R/W

Re ad / Write Enab le

Outp ut Enable

- BA

Bank Address

(4)

- A

12L

- A

12R

Address

I/O

- I/O

17L

I/O

- I/ O

17R

Data Inp ut/Output

CLK

Clock

PL/FT

Pipeline/Flow-Through

ADS

Address Strobe Enable

CNTEN

Co unte r E nab le

REPEAT

Counter Repeat

(3)

, UB

By te E nab le s (9-b it by tes )

DDQL

DDQR

Power (I/O Bus) (3.3V or 2.5V)

(1)

OPT

Option for selecting V

DDQX

(1,2)

Po wer (3.3V)

(1)

Ground (0V)

TDI Tes t Da ta In p ut

TDO Tes t Da ta O utp u t

TCK Test Logic Clock (10MHz)

TM S Test Mode S elect

TRST Re s et (Initializ e TAP Co ntrolle r)

56 28 tbl 01

NOTES:

1. VDD, OPTX, and VDDQX must be set to appropriate operating levels prior to

applying inputs on the I/Os and controls for that port.

2. OPTX selects the operating voltage levels for the I/Os and controls on that port.

If OPTX is set to VIH (3.3V), then that port's I/Os and controls will operate at 3.3V

levels and VDDQX must be supplied at 3.3V. If OPTX is set to VIL (0V), then that

port's I/Os and address controls will operate at 2.5V levels and VDDQX must be

supplied at 2.5V. The OPT pins are independent of one another—both ports can

operate at 3.3V levels, both can operate at 2.5V levels, or either can operate

at 3.3V with the other at 2.5V.

3. When REPEATX is asserted, the counter will reset to the last valid address loaded

via ADSX.

4. Accesses by the ports into specific banks are controlled by the bank address

pins under the user's direct control: each port can access any bank of memory

with the shared array that is not currently being accessed by the opposite port

(i.e., BA0L - BA 5L ≠ BA0R - BA5R). In the event that both ports try to access the

same bank at the same time, neither access will be valid, and data at the two

specific addresses targeted by the ports within that bank may be corrupted (in

the case that either or both ports are writing) or may result in invalid output (in

the case that both ports are trying to read).

6.42

IDT70V7339S

High-Speed 512K x 18 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges

NOTES:

1 . "H" = VIH, "L" = VIL, "X" = Don't Care.

2. ADS, CNTEN, REPEAT are set as appropriate for address access. Refer to Truth Table II for details.

3. OE is an asynchronous input signal.

4. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here.

Truth Table I—Read/Write and Enable Control(1,2,3,4)

CLK CE

UB LB R/WUp pe r By te

I/O

9-17

Lower Byte

I/O

0-8

MODE

X↑H X X X X High-Z High-Z Deselected–Power Do wn

X↑X L X X X High-Z High-Z Deselected–Power Do wn

X↑L H H H X High-Z High-Z All Bytes De selected

X↑LHHLL High-Z D

Write to Lo wer By te Only

X↑LHLHL D

High-Z Write to Upper Byte Only

X↑LHLLL D

Write to b o th Byte s

L↑LHHLHHigh-Z D

OUT

Read Lower Byte Only

L↑LHLHH D

OUT

Hig h-Z Re ad Up pe r By te Only

L↑LHLLH D

OUT

Read b oth B yte s

HXXXXXX High-Z High-ZOutputs Disabled

5628 tbl 02

Truth Table II—Address and Address Counter Control(1,2,7)

NOTES:

1 . "H" = VIH, "L" = VIL, "X" = Don't Care.

2. Read and write operations are controlled by the appropriate setting of R/W, CE0, CE1, UB/LB and OE.

3. Outputs configured in flow-through output mode: if outputs are in pipelined mode the data out will be delayed by one cycle.

4. ADS and REPEAT are independent of all other memory control signals including CE0, CE1 and UB/LB

5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other memory control signals including CE0, CE1, UB/LB.

6. When REPEAT is asserted, the counter will reset to the last valid address loaded via ADS. This value is not set at power-up: a known location should be loaded

via ADS during initialization if desired. Any subsequent ADS access during operations will update the REPEAT address location.

7. The counter includes bank address and internal address. The counter will advance across bank boundaries. For example, if the counter is in Bank 0, at address

FFFh, and is advanced one location, it will move to address 0h in Bank 1. By the same token, the counter at FFFh in Bank 63 will advance to 0h in Bank 0. Refer

to Timing Waveform of Counter Repeat, page 17. Care should be taken during operation to avoid having both counters point to the same bank (i.e., ensure BA0L

- BA5L ≠ BA0R - BA5R), as this condition will invalidate the access for both ports. Please refer to the functional description on page 18 for details.

Address Previous

Address Addr

Used CLK ADS CNTEN REPEAT

(6)

I/O

(3)

MODE

An X An ↑ L

(4)

XHD

I/O

(n) External Address Used

XAnAn + 1

↑H L

(5)

I/O

(n+1) Counter Enabled—Internal Address generation

XAn + 1An + 1

↑HH HD

I/O

(n+1) External Addre ss Blocked—Counter disabled (An + 1 reused)

XXAn

↑XX L

(4)

I/O

(0) Counter Set to last valid ADS lo ad

5628 tb l 03

6.42

IDT70V7339S

High-Speed 512K x 18 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Recommended Operating

Temperature and Supply Voltage(1) Recommended DC Operating

Conditions with VDDQ at 2.5V

Absolute Maximum Ratings(1)

NOTES:

1. Undershoot of VIL > -1.5V for pulse width less than 10ns is allowed.

2. VTERM must not exceed VDDQ + 100mV.

3 . To select operation at 2.5V levels on the I/Os and controls of a given port, the

OPT pin for that port must be set to VIL (0V), and VDDQX for that port must be supplied

as indicated above.

NOTES:

1 . Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may

cause permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those indicated

in the operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect reliability.

2. VTERM must not exceed VDD + 150mV for more than 25% of the cycle time or

4ns maximum, and is limited to < 20mA for the period of VTERM > VDD + 150mV.

NOTE:

1. This is the parameter TA. This is the "instant on" case temperature.

Grade Ambient

Temperature GND V

Commercial 0

C to + 70

C0V3.3V

150m V

Industrial -40

C to +85

C0V3.3V

150m V

5628 tbl 04

Symbol Parameter Min. Typ. Max. Unit

Co re Sup p ly Vol tag e 3.15 3. 3 3. 45 V

DDQ

I/O Supp ly Voltag e

(3)

2.4 2.5 2.6 V

Ground 0 0 0 V

Inp u t Hig h Vo l tag e

(Ad d re ss & Co ntro l Inp uts ) 1.7

____

DDQ

+ 100mV

(2)

Input High Voltage - I/O

(3)

1.7

____

DDQ

+ 100mV

(2)

Inp u t Lo w Vo lta g e -0. 3

(1)

____

0.7 V

5628 tb l 0 5a

Symbol Rating Commercial

& Industrial Unit

TERM

(2)

Ter m in a l Volta ge

wi th Re s pe c t to

GND

-0.5 to +4.6 V

BIAS

Temperature

Under Bias -55 to +125

STG

Storage

Temperature -65 to +150

OUT

DC Outp ut Curre nt 50 mA

5628 tbl 06

Recommended DC Operating

Conditions with VDDQ at 3.3V

NOTES:

1. Undershoot of VIL > -1.5V for pulse width less than 10ns is allowed.

2. VTERM must not exceed VDDQ + 150mV.

3 . To select operation at 3.3V levels on the I/Os and controls of a given port, the

OPT pin for that port must be set to VIH (3.3V), and VDDQX for that port must be

supplied as indicated above.

Symbol Parameter Min. Typ. Max. Unit

Core S up ply Voltage 3.15 3. 3 3.45 V

DDQ

I/O Supp ly Vo ltage

(3)

3.15 3.3 3.45 V

Ground 0 0 0 V

Input High Vo l tag e

(Address & Control Inputs)

(3)

2.0

____

DDQ

+ 150mV

(2)

In p ut High Vo l tag e - I/ O

(3)

2.0

____

DDQ

+ 150mV

(2)

Inp ut Lo w Vo ltag e -0.3

(1)

____

0.8 V

562 8 tbl 05b

6.42

IDT70V7339S

High-Speed 512K x 18 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges

DC Electrical Characteristics Over the Operating

T emperature and Supply Voltage Range (VDD = 3.3V ± 150mV)

NOTES:

1. At VDD < 2.0V leakages are undefined.

2. VDDQ is selectable (3.3V/2.5V) via OPT pins. Refer to page 4 for details.

Symbol Parameter Test Conditions

70V7339S

UnitMin. Max.

| Input Leakage Current

(1)

DDQ

= Max., V

= 0V to V

DDQ

___

10 µA

| Outp ut Le ak age Curre nt

(1)

= V

or CE

= V

, V

OUT

= 0V to V

DDQ

___

10 µA

(3. 3V) Outp ut Lo w Vo ltag e

(2)

= +4mA, V

DDQ

= Min.

___

0.4 V

(3.3V) Output High Voltage

(2)

= -4mA, V

DDQ

= Min. 2. 4

___

(2. 5V) Outp ut Lo w Vo ltag e

(2)

= +2mA, V

DDQ

= Min.

___

0.4 V

(2.5V) Output High Voltage

(2)

= -2mA, V

DDQ

= Min. 2. 0

___

5628 tbl 0 8

NOTES:

1. These parameters are determined by device characterization, but are not

production tested.

2. 3dV references the interpolated capacitance when the input and output switch

from 0V to 3V or from 3V to 0V.

3. COUT also references CI/O.

Capacitance(1)

(TA = +25°C, F = 1.0MHZ) PQFP ONLY

Symbol Parameter Conditions

(2)

Max. Unit

Inp ut Cap ac itanc e V

= 3dV 8 pF

OUT

(3)

Outp ut Cap ac itanc e V

OUT

= 3d V 10. 5 p F

5628 tbl 07

6.42

IDT70V7339S

High-Speed 512K x 18 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range(5) (VDD = 3.3V ± 150mV)

NOTES:

1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input

levels of GND to 3V.

2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.

3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

4. VDD = 3.3V, TA = 25°C for Typ, and are not production tested. IDD DC(f=0) = 120mA (Typ).

5. CEX = VIL means CE0X = VIL and CE1X = VIH

CEX = VIH means CE0X = VIH or CE1X = VIL

CEX < 0.2V means CE0X < 0.2V and CE1X > VDDQ - 0.2V

CEX > VDDQ - 0.2V means CE0X > VDDQ - 0.2V or CE1X < 0.2V

"X" represents "L" for left port or "R" for right port.

70V7339S200

(7)

Com'l Only 70V7339S166

(6)

Com'l

& I nd

70V7339S133

Com'l

& I nd

Symbol P arameter Test Condition Version Typ.

(4)

Max. Typ.

(4)

Max. Typ.

(4)

Max. Unit

Dynamic Op e rating

Current (Bo th

Ports Ac tive)

and CE

= V

Outp uts Di s ab l e d ,

f = f

MAX

(1)

COM'L S 815 950 675 790 550 645 mA

IND S

____ ____

675 830 550 675

SB1

Standby Current

(B oth P o rts - TTL

Le vel In p uts )

= CE

= V

f = f

MAX

(1)

COM'L S 340 410 275 340 250 295 mA

IND S

____ ____

275 355 250 310

SB2

Standby Current

(One P o rt - TTL

Le vel In p uts )

"A"

= V

and CE

"B"

= V

(3)

A c ti ve P ort Ou tp uts D i s ab l e d,

f=f

MAX

(1)

COM'L S 690 770 515 640 460 520 mA

IND S

____ ____

515 660 460 545

SB3

Full Standby Current

(B oth P o rts - CM OS

Le vel In p uts )

Bo th P orts CE

and CE

> V

DDQ

- 0. 2V,

> V

DDQ

- 0.2V or V

< 0.2V,

f = 0

(2)

COM'L S 10 30 10 30 10 30 mA

IND S

____ ____

10 40 10 40

SB4

Full Standby Current

(O ne Port - CMO S

Le vel In p uts )

"A"

< 0.2V and CE

"B"

> V

DDQ

- 0.2V

(5)

> V

DDQ

- 0.2V or V

< 0.2V,

A c ti ve P or t, Outp u ts Di s abl e d ,

f = f

MAX

(1)

COM'L S 690 770 515 640 460 520 mA

IND S

____ ____

515 660 460 545

5628 tb l 09

6. 166MHz Industrial Temperature not available in BF-208 package.

7. This speed grade available when VDDQ = 3.3.V for a specific port (i.e., OPTx = VIH). This speed grade is available in BC-256 only.

6.42

IDT70V7339S

High-Speed 512K x 18 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges

AC T est Conditions (VDDQ - 3.3V/2.5V)

Figure 1. AC Output Test load.

Figure 2. Output Test Load

(For tCKLZ, tCKHZ, tOLZ, and tOHZ).

*Including scope and jig.

Figure 3. Typical Output Derating (Lumped Capacitive Load).

Inp ut P ulse Lev el s (Ad dre ss & Co ntrols)

In p ut P ul s e Le ve l s (I/ Os )

In p ut R ise / F al l Ti mes

In p ut Tim i ng Refe r e nc e Le v e l s

Outp ut Refe re nce Le v e ls

Outp ut Lo ad

GND to 3

0V/ GND to 2. 4V

GND to 3. 0V/GND to 2.4V

2ns

1.5V/1.25V

Fi gure s 1 and 2

5628 tbl 10

1.5V/1.25

50Ω

5628 drw 03

10pF

(Tester)

DATA

OUT

5628 drw 04

590Ω

5pF*

435Ω

3.3V

DATA

OUT

833Ω

5pF*

770Ω

2.5V

DATA

OUT

-1

20.5 30 50 80 100 200

10.5pF is the I/O capacitance of this

device, and 10pF is the AC Test Load

Capacitance.

Capacitance (pF)

∆tCD

(Typical, ns)

5628 drw 05

•

6.42

IDT70V7339S

High-Speed 512K x 18 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the Operating Temperature Range

(Read and Write Cycle Timing)(2,3) (VDD = 3.3V ± 150mV, TA = 0°C to +70°C)

NOTES:

1. The Pipelined output parameters (tCYC2, tCD2) apply to either or both left and right ports when FT/PIPEX = VIH. Flow-through parameters (tCYC1, tCD1) apply when

FT/PIPEX = VIL for that port.

2. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE) and FT/PIPEX. FT/PIPEX should be treated as a

DC signal, i.e. steady state during operation.

3. These values are valid for either level of VDDQ (3.3V/2.5V). See page 4 for details on selecting the desired operating voltage levels for each port.

70V7339S200

(5)

Co m 'l O nl y 70V7339S166

(3,4)

Com'l

& I n d

70V7339S133

(3)

Com'l

& I n d

Symbol Parameter Min.Max.Min.Max.Min.Max.Unit

CYC1

Clock Cycle Time (Flow-Through)

(1)

____

CYC2

Clock Cycle Time (Pipelined)

(1)

____

7.5

____

CH1

Cl o c k Hi gh Tim e ( Fl o w -Thr o u g h)

(1)

____

CL1

Cl o c k L o w Ti me ( Fl ow-Th ro u g h )

(1)

____

CH2

Clock High Time (Pipelined)

(2)

2.0

____

2.1

____

2.6

____

CL2

Clock Low Time (Pipelined)

(1)

2.0

____

2.1

____

2.6

____

Clock Rise Time

____

1.5

____

1.5

____

1.5 ns

Clock Fall Time

____

1.5

____

1.5

____

1.5 ns

Address Setup Time 1.5

____

1.7

____

1.8

____

Address Hold Time 0.5

____

0.5

____

0.5

____

Chi p Enab l e Se tup Time 1.5

____

1.7

____

1.8

____

Chip Enable Ho ld Time 0.5

____

0.5

____

0.5

____

Byte Enab le Setup Ti me 1.5

____

1.7

____

1.8

____

By te Enab l e Hold Ti me 0. 5

____

0.5

____

0.5

____

R/ W S etu p Ti me 1. 5

____

1.7

____

1.8

____

R/ W Ho l d Ti m e 0. 5

____

0.5

____

0.5

____

Inp ut Data Se tup Time 1. 5

____

1.7

____

1.8

____

Inp ut Data Ho ld Tim e 0. 5

____

0.5

____

0.5

____

SAD

ADS Se tup Time 1.5

____

1.7

____

1.8

____

HAD

ADS Hol d Ti m e 0.5

____

0.5

____

0.5

____

SCN

CNTEN Se tup Time 1.5

____

1.7

____

1.8

____

HCN

CNTEN Ho ld Time 0.5

____

0.5

____

0.5

____

SRPT

REPEAT Setup Time 1.5

____

1.7

____

1.8

____

HRPT

REPEAT Hold Tim e 0.5

____

0.5

____

0.5

____

Outp ut Enab le to Data Val id

____

4.0

____

4.0

____

4.2 ns

OLZ

Outp ut E nab le to O utp ut Lo w-Z 0.5

____

0.5

____

0.5

____

OHZ

Outp ut E nab le to O utp ut Hig h-Z 1 3.4 1 3. 6 1 4. 2 ns

CD1

Cl ock to Da ta Va l id ( Fl ow- Th rou g h )

(1)

____

15 ns

CD2

Clo ck to Data Valid (Pip elined )

(1)

____

3.4

____

3.6

____

4.2 ns

Data Outp ut Ho ld A fte r Cl oc k Hig h 1

____

CKHZ

Cl o c k Hi gh to O utpu t Hi gh -Z 1 3. 4 1 3. 6 1 4 . 2 ns

CKLZ

Cl o c k Hi gh to O utpu t L ow- Z 0. 5

____

0.5

____

0.5

____

Port-to-Port Delay

Clock-to-Clock Offset 5.0

____

6.0

____

7.5

____

5628 tbl 11

4. 166MHz Industrial Temperature not available in BF-208 package.

5. This speed grade available when VDDQ = 3.3.V for a specific port (i.e., OPTx = VIH). This speed grade available in BC-256 package only.

6.42

IDT70V7339S

High-Speed 512K x 18 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges

An An + 1 An + 2 An + 3

CYC2

CH2

CL2

ADDRESS

CLK

UB/LB

(3)

DATA

OUT

CD2

CKLZ

Qn Qn + 1 Qn + 2

OHZ

OLZ

5628 drw 06

(1)

(4)

(1 Latency)

(5)

Timing Wa veform of Read Cy cle for Pipelined Operation

(ADS Operation) (FT/PIPE'X' = VIH)(2)

NOTES:

1. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.

2. ADS = VIL, CNTEN and REPEAT = VIH.

3. The output is disabled (High-Impedance state) by CE0 = VIH, CE1 = VIL, UB/LB = VIH following the next rising edge of the clock. Refer to

Truth Table 1.

4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers

are for reference use only.

5. If UB/LB was HIGH, then the appropriate Byte of DATAOUT for Qn + 2 would be disabled (High-Impedance state).

6. "x" denotes Left or Right port. The diagram is with respect to that port.

Timing Wa veform of Read Cyc le for Flow-through Output

(FT/PIPE"X" = VIL)(2,6)

An An + 1 An + 2 An + 3

CYC1

CH1

CL1

ADDRESS

DATA

OUT

CLK

CD1

CKLZ

Qn Qn + 1 Qn + 2

OHZ

OLZ

CKHZ

5628 drw 07

(5)

(1)

BEn

(3)

(4)

(5)

6.42

IDT70V7339S

High-Speed 512K x 18 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges

0(B1)

ADDRESS

(B1)

CLK

DATA

OUT(B1)

CH2

CL2

CYC2

ADDRESS

(B2)

0(B2)

DATA

OUT(B2)

CD2

CKHZ

CD2

CKLZ

CKHZ

CD2

CKLZ

CKHZ

CKLZ

CD2

5628 drw 08

Timing Waveform of a Multi-Device Pipelined Read(1,2)

NOTES:

1. B1 Represents Device #1; B2 Represents Device #2. Each Device consists of one IDT70V7339 for this waveform,

and are setup for depth expansion in this example. ADDRESS(B1) = ADDRESS(B2) in this situation.

2. UB/LB, OE, and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and REPEAT = VIH.

Timing Waveform of a Multi-Device Flow-Through Read(1,2)

0(B1)

ADDRESS

(B1)

CLK

5628 drw 09

CD1

CKLZ

CKHZ

(1) (1)

DATA

OUT(B1)

CH1

CL1

CYC1

(1)

ADDRESS

(B2)

0(B2)

DATA

OUT(B2)

CD1

CKHZ

CD1

CKLZ

(1)

CKHZ

(1)

CKLZ

(1)

CD1

CKLZ

(1)

CKHZ

(1)

6.42

IDT70V7339S

High-Speed 512K x 18 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges

CLK

"A"

R/W

"A"

BANK ADDRESS

AND ADDRESS

"A"

DATA

IN"A"

CLK

"B"

R/W

"B"

BANK ADDRESS

AND ADDRESS

"B"

DATA

OUT"B"

CD2

5628 drw 10

(3)

Timing Wa v eform of P ort A Write to Pipelined P ort B Read(1,2,4)

Timing Waveform with Port-to-Port Flow-Through Read(1,2,4)

DATA

IN "A"

CLK

"B"

R/W

"B"

BANK ADDRESS

AND ADDRESS

"A"

R/W

"A"

CLK

"A"

BANK ADDRESS

AND ADDRESS

"B"

DATA

OUT "B"

5628 drw 11

CD1

(3)

NOTES:

1. CE0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.

2. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.

3. If tCO < minimum specified, then operations from both ports are INVALID. If tCO ≥ minimum, then data from Port "B" read is available on first Port "B" clock cycle

(i.e., time from write to valid read on opposite port will be tCO + tCD1).

4. All timing is the same for both left and right ports. Port "A" may be either left or right port. Port "B" is the opposite of Port "A".

NOTES:

1. CE0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.

2. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.

3. If tCO < minimum specified, then operations from both ports are INVALID. If tCO ≥ minimum, then data from Port "B" read is available on first Port "B" clock cycle

(ie, time from write to valid read on opposite port will be tCO + tCYC2 + tCD2).

4. All timing is the same for both left and right ports. Port "A" may be either left or right port. Port "B" is the opposite of Port "A".

6.42

IDT70V7339S

High-Speed 512K x 18 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges

ADDRESS An An +1 An + 2 An + 2 An + 3 An + 4

DATA

Dn + 2

CLK

5628 drw 12

Qn Qn + 3

DATA

OUT

UB/LB

CD2

CKHZ

CKLZ

CD2

CH2

CL2

CYC2

READ NOP READ

(3)

(1)

WRITE

(4)

Timing Waveform of Pipelined Read-to-Write-to-Read

(OE = VIL)(2)

NOTES:

1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.

2. CE0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH. "NOP" is "No Operation".

3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers

are for reference use only.

4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.

ADDRESS An An +1 An + 2 An + 3 An + 4 An + 5

DATA

Dn + 3Dn + 2

CLK

5628 drw 13

DATA

OUT

Qn Qn + 4

UB/LB

CH2

CL2

CYC2

CKLZ

CD2

OHZ

CD2

READ WRITE READ

(3)

(1)

(4)

Timing Waveform of Pipelined Read-to-Write-to-Read ( OE Controlled)(2)

NOTES:

1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.

2. CE0, UB/LB, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.

3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference

use only.

4. This timing does not meet requirements for fastest speed grade. This waveform indicates how logically it could be done if timing so allows.

6.42

IDT70V7339S

High-Speed 512K x 18 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Timing Wav eform of Flow-Through Read-to-Write-to-R ead (OE = VIL)(2)

Timing Waveform of Flow-Through Read-to-Write-to-Read (OE Controlled)(2)

NOTES:

1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.

2. CE0, UB/LB, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.

3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for

reference use only.

4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.

ADDRESS An An +1 An + 2 An + 2 An + 3 An + 4

DATA

Dn + 2

CLK

5628 drw 14

DATA

OUT

UB/LB

CD1

Qn + 1

CH1

CL1

CYC1

CD1

CKHZ

Qn + 3

CD1

READ NOP READ

CKLZ

(3)

(1)

WRITE

(4)

ADDRESS An An +1 An + 2 An + 3 An + 4 An + 5

(3)

DATA

Dn + 2

CLK

5628 drw 15

DATA

OUT

UB/LB

CD1

CH1

CL1

CYC1

CD1

Qn + 4

CD1

READ WRITE READ

CKLZ

(1)

Dn + 3

OHZ

6.42

IDT70V7339S

High-Speed 512K x 18 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges

ADDRESS An

CLK

DATAOUT Qx - 1

(2)

Qx Qn Qn + 2

(2)

Qn + 3

ADS

CNTEN

tCYC2

tCH2 tCL2

5628 drw 16

tSA tHA

tSAD tHAD

tCD2

tDC

READ

EXTERNAL

ADDRESS

READ WITH COUNTER COUNTER

HOLD

tSAD tHAD

tSCN tHCN

READ

WITH

COUNTER

Qn + 1

Timing Waveform of Pipelined Read with Address Counter Advance(1)

NOTES:

1. CE0, OE, UB/LB = VIL; CE1, R/W, and REPEAT = VIH.

2. If there is no address change via ADS = VIL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then

the data output remains constant for subsequent clocks.

Timing Waveform of Flow-Through Read with Address Counter Advance(1)

ADDRESS An

CLK

DATAOUT Qx

(2)

Qn Qn + 1 Qn + 2 Qn + 3

(2)

Qn + 4

ADS

CNTEN

tCYC1

tCH1 tCL1

5628 drw 17

tSA tHA

tSAD tHAD

READ

EXTERNAL

ADDRESS

READ WITH COUNTER COUNTER

HOLD

tCD1

tDC

tSAD tHAD

tSCN tHCN

READ

WITH

COUNTER

6.42

IDT70V7339S

High-Speed 512K x 18 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Timing Waveform of Write with Address Counter Advance

(Flow-through or Pipelined Inputs)(1,6)

NOTES:

1. CE0, UB/LB, and R/W = VIL; CE1 and REPEAT = VIH.

2. CE0, UB/LB = VIL; CE1 = VIH.

3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH.

4. No dead cycle exists during REPEAT operation. A READ or WRITE cycle may be coincidental with the counter REPEAT cycle: Address loaded by last valid

ADS load will be accessed. For more information on REPEAT function refer to Truth Table II.

5. CNTEN = VIL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’Address is

written to during this cycle.

6. The counter includes bank address and internal address. The counter will advance across bank boundaries. For example, if the counter is in Bank 0, at address

FFFh, and is advanced one location, it will move to address 0h in Bank 1. By the same token, the counter at FFFh in Bank 63 will advance to 0h in Bank 0.

7. For Pipelined Mode user should add 1 cycle latency for outputs as per timing waveform of read cycle for pipelined operations.

ADDRESS An

CLK

DATA

Dn Dn + 1 Dn + 1 Dn + 2

ADS

CNTEN

CH2

CL2

CYC2

5628 drw 18

INTERNAL

(3)

ADDRESS An

(5)

An + 1 An + 2 An + 3 An + 4

Dn + 3 Dn + 4

SAD

HAD

WRITE

COUNTER HOLD WRITE WITH COUNTER

WRITE

EXTERNAL

ADDRESS

WRITE

WITH COUNTER

SCN

HCN

Timing Waveform of Counter Repeat for Flow Through Mode(2,6,7)

ADDRESS An

CYC2

CLK

DATA

REPEAT

5628 drw 19

INTERNAL

(3)

ADDRESS

ADS

CNTEN

WRITE TO

ADS

ADDRESS

ADVANCE

COUNTER

WRITE TO

An+1

ADVANCE

COUNTER

WRITE TO

An+2

HOLD

COUNTER

WRITE TO

An+2

REPEAT

READ LAST

ADS

ADDRESS

DATA

OUT

SAD

HAD

SCN

HCN

SRPT

HRPT

CD1

An+1 An+2 An+2 An An+1 An+2 An+2

An An+1 An+2 An+2

ADVANCE

COUNTER

READ

An+1

ADVANCE

COUNTER

READ

An+2

HOLD

COUNTER

READ

An+2

(4)

6.42

IDT70V7339S

High-Speed 512K x 18 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Functional Description

The IDT70V7339 is a high-speed 512Kx18 (9 Mbit) synchronous

Bank-Switchable Dual-Ported SRAM organized into 64 independent

8Kx18 banks. Based on a standard SRAM core instead of a traditional true

dual-port memory core, this bank-switchable device offers the benefits of

increased density and lower cost-per-bit while retaining many of the

features of true dual-ports. These features include simultaneous, random

access to the shared array, separate clocks per port, 166 MHz operating

speed, full-boundary counters, and pinouts compatible with the IDT70V3319

(256Kx18) dual-port family.

The two ports are permitted independent, simultaneous access into

separate banks within the shared array. Access by the ports into specific

banks are controlled by the bank address pins under the user's direct

control: each port can access any bank of memory with the shared array

that is not currently being accessed by the opposite port (i.e., BA0L - BA5L

≠ BA0R - BA5R). In the event that both ports try to access the same bank

at the same time, neither access will be valid, and data at the two specific

addresses targeted by the ports within that bank may be corrupted (in the

case that either or both ports are writing) or may result in invalid output (in

the case that both ports are trying to read).

The IDT70V7339 provides a true synchronous Dual-Port Static RAM

interface. Registered inputs provide minimal setup and hold times on

address, data and all critical control inputs.

An asynchronous output enable is provided to ease asynchronous

bus interfacing. Counter enable inputs are also provided to stall the

operation of the address counters for fast interleaved memory applications.

A HIGH on CE0 or a LOW on CE1 for one clock cycle will power down

the internal circuitry on each port (individually controlled) to reduce static

power consumption. Dual chip enables allow easier banking of multiple

IDT70V7339s for depth expansion configurations. Two cycles are

required with CE0 LOW and CE1 HIGH to read valid data on the outputs.

Depth and Width Expansion

The IDT70V7339 features dual chip enables (refer to Truth

Table I) in order to facilitate rapid and simple depth expansion with no

requirements for external logic. Figure 4 illustrates how to control the

various chip enables in order to expand two devices in depth.

The IDT70V7339 can also be used in applications requiring expanded

width, as indicated in Figure 4. Through combining the control signals, the

devices can be grouped as necessary to accommodate applications

needing 36-bits or wider.

5628 drw 20

IDT70V7339

CE0

CE1

CE0

CE1

BA6

(1)

CE1

CE0

VDD VDD

IDT70V7339

Control Inputs

Control Inputs BE,

R/W,

OE,

CLK,

ADS,

REPEAT,

CNTEN

Figure 4. Depth and Width Expansion with IDT70V7339

NOTE:

1. In the case of depth expansion, the additional address pin logically serves as an extension of the bank address. Accesses by the ports into specific banks are

controlled by the bank address pins under the user's direct control: each port can access any bank of memory within the shared array that is not currently

being accessed by the opposite port (i.e., BA0L - BA6L ≠ BA0R - BA6R). In the event that both ports try to access the same bank at the same time, neither

access will be valid, and data at the two specific addresses targeted by the parts within that bank may be corrupted (in the case that either or both parts are

writing) or may result in invalid output (in the case that both ports are trying to read).

6.42

IDT70V7339S

High-Speed 512K x 18 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges

JT AG AC Electrical

Characteristics(1,2,3,4)

70V7339

Symbol Parameter Min. Max. Units

JCYC

JTAG Clock Input Period 100

____

JCH

JTAG Clock HIGH 40

____

JCL

JTAG Clock Low 40

____

JTAG Clock Rise Time

____

(1)

JTAG Clock Fall Time

____

(1)

JRST

JTAG Rese t 50

____

JRSR

JTAG Rese t Recov ery 50

____

JCD

J TAG Data Outp ut

____

25 ns

JDC

J TA G Data Ou tp ut Hold 0

____

JTAG Se tup 15

____

JTAG Hold 15

____

5628 tbl 12

NOTES:

1. Guaranteed by design.

2. 30pF loading on external output signals.

3. Refer to AC Electrical Test Conditions stated earlier in this document.

4. JTAG operations occur at one speed (10MHz). The base device may run at

any speed specified in this datasheet.

JTAG Timing Specifications

TCK

Device Inputs

(1)

TDI/TMS

Device Outputs

(2)

TDO

TRST

JCD

JDC

JRST

JCYC

JRSR

JCL

JCH

5628 drw 21

Figure 5. Standard JTAG Timing

NOTES:

1. Device inputs = All device inputs except TDI, TMS, TRST, and TCK.

2. Device outputs = All device outputs except TDO.

6.42

IDT70V7339S

High-Speed 512K x 18 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Identification Register Definitions

Instruction Field Value Description

Re vi sio n Num be r (31: 28) 0x 0 Re se rve d for v ers io n num be r

IDT De vic e ID (27: 12) 0x301 De fine s IDT p art numb e r

IDT JEDEC ID (11:1) 0x33 Allows unique identification of device vendor as IDT

ID Register Indicator Bit (Bit 0) 1 Indicates the presence of an ID register

5628 tbl 13

Scan Register Sizes

Instruction (IR) 4

Bypass (BYR) 1

Id e n ti fi ca ti o n (IDR) 32

Bo und ary Sc an (B SR) No te (3)

5628 tbl 14

System Interface Parameters

Instruction Code Description

EXTEST 0000 Forces contents of the bound ary scan cells onto the device outputs

(1)

Plac es the b ound ary s can re giste r (BSR) be twe en TDI and TDO.

B YPAS S 1111 Pl a c es th e bypa s s r eg is t er ( BY R) b et ween TD I a n d TD O .

IDCODE 0010 Loads the ID register (IDR) with the vendor ID code and places the

HIGHZ 0100 Places the bypass register (BYR) between TDI and TDO. Forces all

device output drivers to a High-Z state.

CLAMP 0011 Uses BYR. Forces co ntents of the boundary scan cells onto the de vice

outputs. Places the bypass registe r (BYR) between TDI and TDO.

SAMPLE/PRELOAD 0001 Places the boundary scan registe r (BSR) between TDI and TDO.

SAMPLE allows data from d evic e inputs

(2)

and o utp uts

(1)

to be captured

in the b ound ary s can c e lls and shifte d s eri all y thro ug h TDO. PRE LOAD

allows data to be input serially into the boundary scan cells via the TDI.

RE SERV ED All o the r c od e s S ev eral c o mb inatio ns are re se rve d . Do no t us e co d e s o the r than tho se

identified above.

5628 tbl 15

NOTES:

1. Device outputs = All device outputs except TDO.

2. Device inputs = All device inputs except TDI, TMS, TRST, and TCK.

3. The Boundary Scan Descriptive Language (BSDL) file for this device is available on the IDT website (www.idt.com), or by contacting your local

IDT sales representative.

6.42

IDT70V7339S

High-Speed 512K x 18 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Ordering Information

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

CORPORATE HEADQUARTERS for SALES: for Tech Support:

6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 408-284-2794

San Jose, CA 95138 fax: 408-284-2775 DualPortHelp@idt.com

www.idt.com

Datasheet Document History:

1/5/00: Initial Public Offering

6/20/01: Page 1 Added JTAG information for TQFP package

Page 4 & 22 Changed TQFP package from DA to DD

Corrected Pin number on TQFP package from 100 to 110

Page 20 Increased tJCD from 20ns to 25ns

8/6/01: Page 4 Changed body size for DD package from 22mm x 22mm x1.6mm to 20mm x 20mm x 1.4mm

Page 9 Changed ISB3 values for commercial and industrial DC Electrical Characteristics

11/20/01: Page 2, 3 & 4 Added date revision for pin configurations

Page 11 Changed tOE value in AC Electrical Characteristics, please refer to Errata #SMEN-01-05

Page 1 & 22 Replaced TM logo with ® logo

03/18/02: Page 1, 9, 11 & 22 Added 200MHZ specification

Page 9 Tightened power numbers in DC Electrical Characteristics

Page 14 Changed waveforms to show INVALID operation if tCO < minimum specified

Page 1 - 22 Removed "Preliminary" status

12/4/02: Page 9, 11 & 22 Designated 200Mhz speed grade in BC-256 package only

01/16/04: Page 11 Added byte enable setup time and byte enable hold time parameters and values to all speed grades in the AC Electrical

Characteristics Table

07/25/08: Page 9 Corrected a typo in the DC Chars table

01/29/09: Page 22 Removed "IDT" from orderable part number

04/20/10: Page 1 Added green availability to features

Page 21 Added green indicator to ordering information

Removed the DD 144-pin TQFP (DD-144) Thin Quad Flatpack per PDN: F-08-01



NOTES:

1. Available in BC-256 package only.

2. Industrial Temperature at 166MHz not available in the BF-208 package.

3. Green parts available. For specific speeds, packages and powers contact your local sales office.

Power

999

Speed

Package

Process/

Temperature

Range

Blank

Commercial (0°C to +70°C)

Industrial (-40°C to +85°C)

BC 208-pin fpBGA (BF-208)

256-pin BGA (BC-256)

200

166

133

XXXXX

Device

Type

Speed in Megahertz

5628 drw 22

S Standard Power

70V7339 9Mbit (512K x 18-Bit) Synchronous Bank-Switchable Dual-Port RAM

Commercial Only

(1)

Commercial & Industrial

(2)

Commercial & Industrial

(3)

Green