11195A.book Page 1 Tuesday, November 7, 2000 2:06 PM MCP41XXX/42XXX Single/Dual Digital Potentiometer with SPITM Interface FEATURES * * * PACKAGE TYPES PDIP/SOIC 1 2 SI 3 VSS 4 8 7 6 5 PA0 VDD PB0 PW0 PDIP/SOIC/TSSOP DESCRIPTION The MCP41XXX and MCP42XXX devices are 256 position digital potentiometers available in 10k, 50k, and 100k resistance versions. The MCP41XXX is a single channel device and is offered in an 8-pin PDIP or SOIC package. The MCP42XXX contains two independent channels in a 14-pin PDIP, SOIC, or TSSOP package. The wiper position of the MCP41XXX/42XXX varies linearly and is controlled via an industry-standard SPI interface. The devices consume <1A during static operation. A software shutdown feature is provided that disconnects the "A" terminal from the resistor stack and simultaneously connects the wiper to the "B" terminal. In addition, the dual MCP42XXX has a SHDN pin that performs the same function in hardware. During the shutdown mode, the contents of the wiper register can be changed and the potentiometer returns from shutdown to the new value. The wiper is reset to the mid-scale position, 80h, upon power-up. The RS (reset) pin implements a hardware reset and also returns the wiper to mid-scale. The MCP42XXX SPI interface includes both the SI and SO pins, allowing daisy-chaining of multiple devices. Channel-to-channel resistance matching on the MCP42XXX varies by less than 1%. These devices operate from a single 2.7 5.5V supply and are specified over the extended industrial temperature range of -40C to +85C. CS SCK CS 1 14 VDD SCK 2 13 SO SI 3 VSS 4 PB1 5 PW1 6 PA1 7 MCP42XXX * 256 taps for each potentiometer Potentiometer values for 10k, 50k and 100k Single and dual versions SPI serial interface (mode 0,0 and 1,1) +/- 1 LSB max INL & DNL Low power CMOS technology 1 A maximum supply current in static operation Multiple devices can be daisy-chained together (MCP42XXX only) Shutdown feature open circuits of all resistors for maximum power savings Hardware shutdown pin available on MCP42XXX only Single supply operation (2.7V - 5.5V) Industrial temperature range: -40C to +85C MCP41XXX * * * * * * * * 12 SHDN 11 RS 10 PB0 9 PW0 8 PA0 BLOCK DIAGRAM RS SHDN VDD VSS PB0 Control Logic PA0 PW0 PB1 CS SI Resistor Array 0 Wiper Register Resistor Wiper Register Array 1* 16-Bit Shift Register PA1 PW1 SCK S0 NOTE: Potentiometer P1 is only available on the dual MCP42XXX version. SPI is a trademark of Motorola Inc. 2000 Microchip Technology Inc. DS11195A-page 1 11195A.book Page 2 Tuesday, November 7, 2000 2:06 PM MCP41XXX/42XXX 1.0 ELECTRICAL CHARACTERISTICS DC CHARACTERISTICS:10K VERSION All parameters apply across the specified operating ranges unless noted. PARAMETER Industrial (I): VDD = +2.7V to 5.5V TA = -40C to +85C (Note 8) Typical specifications represent values for VDD = 5V, VSS = 0V, VB = 0V, TA = +25C SYMBOL MIN. TYP. MAX. UNITS CONDITIONS Rheostat Mode Nominal Resistance Rheostat Differential Non Linearity Rheostat Integral Non Linearity Rheostat Tempco Wiper Resistance Wiper Current Nominal Resistance Match R 8 10 12 k R-DNL -1 1/4 +1 LSB Note 2 TA = +25C (Note 1) Note 2 R-INL -1 1/4 +1 LSB RAB/T -- 800 -- ppm/C RW -- 52 100 VDD = 5.5 V, IW = 1 mA, code 00h RW -- 73 125 VDD = 2.7 V, IW = 1 mA, code 00h IW -1 -- +1 mA R/R -- 0.2 1 % Bits MCP42010 only, P0 to P1;TA = 25C Potentiometer Divider Resolution N 8 -- -- Monotonicity N 8 -- -- Bits Differential Non Linearity DNL -1 1/4 +1 LSB Integral Non Linearity Voltage Divider Tempco (Variation between both halves of the voltage divider) INL -1 1/4 +1 LSB VW/T -- 1 -- ppm/C VWFSE -2 -0.7 0 LSB VWFSE -2 -0.7 0 LSB Code FFh, VDD = 3V(Note 9) VWZSE 0 +0.7 +2 LSB Code 00h, VDD = 5V(Note 9) VWZSE 0 +0.7 +2 LSB Code 00h, VDD = 3V(Note 9) Full Scale Error Zero Scale Error Note 3 Note 3 Code 80h Code FFh, VDD = 5V(Note 9) Resistor Terminals 0 -- VDD Capacitance (CA or CB) -- 15 -- pF f =1MHz, Code = 80h, see Figure 2-30 for test circuit Capacitance (CW) -- 5.6 -- pF f =1MHz, Code = 80h, see Figure 2-30 for test circuit BW -- 1 -- MHz Voltage Range VA,B,W Note 4 Dynamic Characteristics (Note 6) Bandwidth -3dB Settling Time Resistor Noise Voltage Crosstalk tS -- 2 -- S eNWB -- 9 -- nV/Hz CT -- -95 -- dB 0.7VDD -- -- V -- -- 0.3VDD V -- 0.05VDD -- Digital Inputs/Outputs (CS, SCK, SI, SO) Note 10 Schmitt Trigger High Level Input Voltage VIH (All digital input pins) Schmitt Trigger Low Level Input Voltage VIL (All digital input pins) Hysteresis of Schmitt Trigger Inputs VHYS VB = 0V, Measured at Code 80h, Output Load = 30PF VA = VDD,VB = 0V, 1% Error Band, Transition from Code 00h to Code 80h, Output Load = 30pF VA = Open, Code 80h, f =1kHz VA = VDD, VB = 0V (Note 5) Low Level Output Voltage VOL -- -- 0.40 V IOL = 2.1 mA,VDD = 5V High Level Output Voltage VOH VDD - 0.5 -- -- V ILI -1 -- 1 A CIN, COUT -- 10 -- pF IOH = -400A, VDD = 5V CS = VDD, VIN = VSS or VDD, includes VA while SHDN = 0 VDD = 5.0V, TA = +25C, fc = 1 MHz Input Leakage Current Pin Capacitance (All inputs/outputs) Power Requirements Operating Voltage Range VDD 2.7 -- 5.5 V Supply Current, Active IDDA -- 340 500 A Supply Current, Static IDDS -- 0.01 1 A PSS -- 0.0015 0.0035 %/% Power Supply Sensitivity Note 1: 2: 3: 4: 5: 6: 7: 8: 9: 10: VDD = 5.5V, CS = VSS, fSCK = 10MHz, SO = Open, Code FFh (Note 7) CS, SHDN, RS = VDD = 5.5V, SO = Open (Note 7) VDD = 4.5V - 5.5V, VA = 4.5V, Code 80h PSS -- 0.0015 0.0035 %/% VDD = 2.7V - 3.3 V, VA = 2.7V, Code 80h VAB = VDD, no connection on wiper. Rheostat position non linearity R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from the ideal between successive tap positions. IW = 50A for VDD = 3V and IW = 400A for VDD = 5V for 10k version. See Figure 2-26 for test circuit. INL and DNL are measured at VW with the device configured in the voltage divider or potentiometer mode. VA = VDD and VB = 0V. DNL specification limits of 1 LSB max are specified monotonic operating conditions. See Figure 2-25 for test circuit. Resistor terminals A,B and W have no restrictions on polarity with respect to each other. Full scale and zero scale error were measured using Figure 2-25. Measured at VW pin where the voltage on the adjacent VW pin is swinging full scale. All dynamic characteristics use VDD = 5V. Supply current is independent of current through the potentiometers. TSSOP devices are only specified at 25C and 85C. See Figure 2-25 for test circuit. See Figure 2-12 for RS and SHDN pin operation. DS11195A-page 2 2000 Microchip Technology Inc. 11195A.book Page 3 Tuesday, November 7, 2000 2:06 PM MCP41XXX/42XXX DC CHARACTERISTICS: 50K VERSION All parameters apply across the specified operating ranges unless noted. PARAMETER Industrial (I): VDD = +2.7V to 5.5V TA = -40C to +85C (Note 8) Typical specifications represent values for VDD = 5V, VSS = 0V, VB = 0V, TA = +25C SYMBOL MIN. TYP. MAX. R R-DNL UNITS CONDITIONS 35 50 65 k -1 1/4 +1 LSB Note 2 Note 2 Rheostat Mode Nominal Resistance Rheostat Differential Non Linearity Rheostat Integral Non Linearity Rheostat Tempco R-INL -1 1/4 +1 LSB RAB/T -- 800 -- ppm/C RW -- 125 175 VDD = 5.5 V, IW = 1 mA, code 00h RW -- 175 250 VDD = 2.7 V, IW = 1 mA, code 00h IW -1 -- +1 mA R/R -- 0.2 1 % Bits Wiper Resistance Wiper Current Nominal Resistance Match TA = +25C (Note 1) MCP42050 only, P0 to P1; TA = 25C Potentiometer Divider Resolution N 8 -- -- Monotonicity N 8 -- -- Bits Differential Non Linearity DNL -1 1/4 +1 LSB VDD = 5V (Note 3) Integral Non Linearity INL -1 1/4 +1 LSB Note 3 VW/T -- 1 -- ppm/C VWFSE -1 -0.25 0 LSB VWFSE -1 -0.35 0 LSB Code FFh, VDD = 3V (Note 9) VWZSE 0 +0.25 +1 LSB Code 00h, VDD = 5V (Note 9) VWZSE 0 +0.35 +1 LSB Code 00h, VDD = 3V (Note 9) Voltage Divider Tempco (Variation between both halves of the voltage divider) Full Scale Error Zero Scale Error Code 80h Code FFh, VDD = 5V (Note 9) Resistor Terminals Voltage Range VA,B,W 0 -- VDD Capacitance (CA or CB) -- 11 -- pF Note 4 Capacitance (CW) -- 5.6 -- pF BW -- 280 -- kHz f =1MHz, Code = 80h, see Figure 2-30 for test circuit f =1MHz, Code = 80h, see Figure 2-30 for test circuit Dynamic Characteristics (Note 6) Bandwidth -3dB Settling Time Resistor Noise Voltage tS -- 8 -- S eNWB -- 20 -- nV/Hz CT -- -95 -- dB VIH 0.7VDD -- -- V VIL -- -- 0.3VDD V VHYS -- 0.05VDD -- Crosstalk VB = 0V, Measured at Code 80h, Output Load = 30PF VA = VDD, VB = 0V, 1% Error Band, Transition from Code 00h to Code 80h, Output Load = 30pF VA = Open, Code 80h, f =1kHz VA = VDD, VB = 0V (Note 5) Digital Inputs/Outputs (CS, SCK, SI, SO) Note 10 Schmitt Trigger High Level Input Voltage (All digital input pins) Schmitt Trigger Low Level Input Voltage (All digital input pins) Hysteresis of Schmitt Trigger Inputs Low Level Output Voltage VOL -- -- 0.40 V IOL = 2.1 mA, VDD = 5V High Level Output Voltage VOH VDD - 0.5 -- -- V IOH = -400A, VDD = 5V ILI -1 -- 1 A CS = VDD, VIN = VSS or VDD, includes VA while SHDN = 0 CIN, COUT -- 10 -- pF VDD = 5.0V, TA = +25C, fc = 1 MHz Operating Voltage Range VDD 2.7 -- 5.5 V Supply Current, Active IDDA -- 340 500 A VDD = 5.5V, CS = VSS, fSCK = 10MHz, SO = Open, Code FFh (Note 7) CS, SHDN, RS = VDD = 5.5V, SO = Open (Note 7) Input Leakage Current Pin Capacitance (All inputs/outputs) Power Requirements Supply Current, Static Power Supply Sensitivity Note 1: 2: 3: 4: 5: 6: 7: 8: 9: 10: IDDS -- 0.01 1 A PSS -- 0.0015 0.0035 %/% VDD = 4.5V - 5.5V, VA = 4.5V, Code 80h PSS -- 0.0015 0.0035 %/% VDD = 2.7V - 3.3V, VA = 2.7V, Code 80h VAB = VDD, no connection on wiper. Rheostat position non linearity R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from the ideal between successive tap positions. IW = VDD/R for +3V or +5V for the 50k version. See Figure 2-26 for test circuit. INL and DNL are measured at VW with the device configured in the voltage divider or potentiometer mode. VA = VDD and VB = 0V. DNL specification limits of 1 LSB max are specified monotonic operating conditions. See Figure 2-25 for test circuit. Resistor terminals A,B and W have no restrictions on polarity with respect to each other. Full scale and zero scale error were measured using Figure 2-25. Measured at VW pin where the voltage on the adjacent VW pin is swinging full scale. All dynamic characteristics use VDD = 5V. Supply current is independent of current through the potentiometers. TSSOP devices are only specified at 25C and 85C. See Figure 2-25 for test circuit. See Figure 2-12 for RS and SHDN pin operation. 2000 Microchip Technology Inc. DS11195A-page 3 11195A.book Page 4 Tuesday, November 7, 2000 2:06 PM MCP41XXX/42XXX DC CHARACTERISTICS OF 100K VERSION All parameters apply across the specified operating ranges unless noted. PARAMETER Industrial (I): VDD = +2.7V to 5.5V TA = -40C to +85C (Note 8) Typical specifications represent values for VDD = 5V, VSS = 0V, VB = 0V, TA = +25C SYMBOL MIN. TYP. MAX. UNITS CONDITIONS Rheostat Mode Nominal Resistance Rheostat Differential Non Linearity Rheostat Integral Non Linearity Rheostat Tempco Wiper Resistance Wiper Current Nominal Resistance Match R 70 100 130 k R-DNL -1 1/4 +1 LSB Note 2 TA = +25C (Note 1) Note 2 R-INL -1 1/4 +1 LSB RAB/T -- 800 -- ppm/C RW -- 125 175 VDD = 5.5 V, IW = 1 mA, code 00h RW -- 175 250 VDD = 2.7 V, IW = 1 mA, code 00h IW -1 -- +1 mA R/R -- 0.2 1 % Bits MCP42100 only, P0 to P1;TA = 25C Potentiometer Divider Resolution N 8 -- -- Monotonicity N 8 -- -- Bits Differential Non Linearity DNL -1 1/4 +1 LSB VDD = 5V (Note 3) Integral Non Linearity Voltage Divider Tempco (Variation between both halves of the voltage divider) INL -1 1/4 +1 LSB Note 3 VW/T -- 1 -- ppm/C VWFSE -1 -0.25 0 LSB VWFSE -1 -0.35 0 LSB Code FFh, VDD = 3V (Note 9) VWZSE 0 +0.25 +1 LSB Code 00h, VDD = 5V (Note 9) VWZSE 0 +0.35 +1 LSB Code 00h, VDD = 3V (Note 9) Full Scale Error Zero Scale Error Code 80h Code FFh, VDD = 5V (Note 9) Resistor Terminals Voltage Range VA,B,W 0 -- VDD Capacitance (CA or CB) -- 11 -- pF Capacitance (CW) -- 5.6 -- pF BW -- 145 -- kHz tS -- 18 -- S eNWB -- 29 -- nV/Hz CT -- -95 -- dB Note 4 f =1MHz, Code = 80h, see Figure 2-30 for test circuit f =1MHz, Code = 80h, see Figure 2-30 for test circuit Dynamic Characteristics (Note 6) Bandwidth -3dB Settling Time Resistor Noise Voltage Crosstalk Digital Inputs/Outputs (CS, SCK, SI, SO) Note 10 Schmitt Trigger High Level Input Voltage (All VIH digital input pins) Schmitt Trigger Low Level Input Voltage (All VIL digital input pins) Hysteresis of Schmitt Trigger Inputs VHYS 0.7VDD -- -- V -- -- 0.3VDD V -- 0.05VDD -- VB = 0V, Measured at Code 80h, Output Load = 30PF VA = VDD,VB = 0V, 1% Error Band, Transition from Code 00h to Code 80h, Output Load = 30pF VA = Open, Code 80h, f =1kHz VA = VDD, VB = 0V (Note 5) Low Level Output Voltage VOL -- -- 0.40 V IOL = 2.1 mA,VDD = 5V High Level Output Voltage VOH VDD - 0.5 -- -- V ILI -1 -- 1 A CIN, COUT -- 10 -- pF IOH = -400A, VDD = 5V CS = VDD, VIN = VSS or VDD, includes VA while SHDN = 0 VDD = 5.0V, TA = +25C, fc = 1 MHz Operating Voltage Range VDD 2.7 -- 5.5 V Supply Current, Active IDDA -- 340 500 A Supply Current, Static IDDS -- 0.01 1 A PSS -- 0.0015 0.0035 %/% PSS -- 0.0015 0.0035 %/% Input Leakage Current Pin Capacitance (All inputs/outputs) Power Requirements Power Supply Sensitivity Note VDD = 5.5V, CS = VSS, fSCK = 10MHz, SO = Open, Code FFh (Note 7) CS, SHDN, RS = VDD = 5.5V, SO = Open (Note 7) VDD = 4.5V - 5.5V, VA = 4.5V Code 80h VDD = 2.7V - 3.3V, VA = 2.7V Code 80h VAB = VDD, no connection on wiper. Rheostat position non linearity R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from the ideal between successive tap positions. IW = VDD/R for +3V or +5V for the 100k version. See Figure 2-26 for test circuit. 3: INL and DNL are measured at VW with the device configured in the voltage divider or potentiometer mode. VA = VDD and VB = 0V. DNL specification limits of 1 LSB max are specified monotonic operating conditions.See Figure 2-25 for test circuit. 4: Resistor terminals A,B and W have no restrictions on polarity with respect to each other. Full scale and zero scale error were measured using Figure 2-25. 5: Measured at VW pin where the voltage on the adjacent VW pin is swinging full scale. 6: All dynamic characteristics use VDD = 5V. 7: Supply current is independent of current through the potentiometers. 8: TSSOP devices are only specified at 25C and 85C 9: See Figure 2-25 for test circuit. 10: See Figure 2-12 for RS and SHDN pin operation. 1: 2: DS11195A-page 4 2000 Microchip Technology Inc. 11195A.book Page 5 Tuesday, November 7, 2000 2:06 PM MCP41XXX/42XXX ELECTRICAL CHARACTERISTICS (CONTINUED) Maximum Ratings* VDD ........................................................................ 7.0V All inputs and outputs w.r.t. VSS .......-0.6V to VDD +1.0V Storage temperature .......................... -60C to +150C Ambient temp. with power applied ..... -60C to +125C ESD protection on all pins ..................................... 2 kV *Notice: Stresses above those listed under "maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. AC TIMING CHARACTERISTICS All parameters apply across the specified operating ranges unless otherwise noted. PARAMETER Industrial (I): VDD = +2.7V to 5.5V TA = -40C to +85C SYMBOL MIN. TYP. MAX. UNITS FCLK -- -- 10 MHz Clock High Time tHI 40 -- -- ns Clock Low Time tLO 40 -- -- ns tCSSR 40 -- -- ns Data Input Setup Time tSU 40 -- -- ns Data Input Hold Time tHD 10 -- -- ns SCK Fall to SO Valid Propagation Delay tDO -- 80 ns SCK Rise to CS Rise Hold Time tCHS 30 -- -- ns ns Clock Frequency CS Fall to First Rising CLK Edge SCK Rise to CS Fall Delay tCS0 10 -- -- CS Rise to CLK Rise Hold tCS1 100 -- -- ns CS High Time tCSH 40 -- -- ns Reset Pulse Width CONDITIONS VDD = 5V (Note 1) CL = 30pF (Note 2) tRS 150 -- -- ns tRSCS 150 -- -- ns Note 2 CS rising to RS or SHDN falling delay time tSE 40 -- -- ns Note 3 CS low time tCSL 100 -- -- ns Note 3 Shutdown Pulse Width tSH 150 -- -- ns Note 3 RS Rising to CS Falling Delay Time Note 2 Note 1: When using the device in the daisy chain configuration, max. clock frequency is determined by a combination of propagation delay time (tDO) and data input setup time (tSU). Max. clock frequency is therefore ~ 5.8MHz based on SCK rise and fall times of 5ns, tHI = 40ns, tDO = 80 ns and tSU = 40ns. Note 2: Applies only to the MCP42XXX devices. Note 3: Applies only when using hardware pins to exit software shutdown mode, MCP42XXX only. 2000 Microchip Technology Inc. DS11195A-page 5 11195A.book Page 6 Tuesday, November 7, 2000 2:06 PM MCP41XXX/42XXX tCSH CS 1/FCLK tCSSR tHI tCSO tCHS tLO tCS1 SCK tSU tHD SI msb in tDO (1ST 16 BITS OUT SO ARE ALWAYS ZEROS) tS 1% Error Band VOUT Figure 1-1: 1% Detailed Serial interface Timing Wiper position is changed to midscale (80h) if RS is held low for 150ns Code 80h is latched on rising edge of RS CS tRSCS tRS RS tS 1% VOUT Figure 1-2: 1% Error Band Reset Timing tCSL CS tSE tRS RS tSE tSH SHDN Figure 1-3: Software Shutdown Exit Timing DS11195A-page 6 2000 Microchip Technology Inc. 11195A.book Page 7 Tuesday, November 7, 2000 2:06 PM MCP41XXX/42XXX 2.0 TYPICAL PERFORMANCE CURVES Note: Unless otherwise indicated, curve represents 10k, 50k, and 100k devices, VDD = 5V, VSS = 0V, TA = 25C, VB = 0V. 12 1 VDD = +3V to +5V RAB Nominal Resistance (k) Normalized Resistance () 10 0.8 0.6 0.4 RWB RWA 8 6 RWB Code = 80h 4 0.2 2 MCP41010, MCP42010 (10k potentiometers) 0 0 0 32 64 96 128 160 192 224 256 -40 -20 0 Code (Decimal) Figure 2-1: Normalized Wiper to End Terminal Resistance vs. Code Figure 2-4: Temperature TA = -40C to +85C Refer to Figure 2-25 0.4 60 80 Nominal Resistance 10k vs. 60 0.3 Nominal Resistance (k) Potentiometer INL Error (LSB) 40 70 0.5 0.2 0.1 0 -0.1 -0.2 -0.3 RAB 50 40 30 RWB Code = 80h 20 10 -0.4 MCP41050, MCP42050 (50k potentiometers) -0.5 0 0 32 64 96 128 160 192 224 -40 256 -20 0 Figure 2-2: 20 40 60 80 Temperature (C) Code (Decimal) Potentiometer INL Error vs. Code Figure 2-5: Temperature Nominal Resistance 50k vs. 140 70 T A = -40C to +85C VA = 3V 60 120 Nominal Resistance (k) Potentiometer Mode TempCo (ppm / C) 20 Temperature (C) 50 40 30 20 10 RAB 100 80 60 RWB Code = 80h 40 20 0 MCP41100, MCP42100 (100k potentiometers) 0 -10 0 32 64 96 128 160 192 224 256 -40 -20 0 Figure 2-3: Potentiometer Mode Tempco vs. Code 2000 Microchip Technology Inc. 20 40 60 80 Temperature (C) Code (Decimal) Figure 2-6: Temperature Nominal Resistance 100k vs. DS11195A-page 7 11195A.book Page 8 Tuesday, November 7, 2000 2:06 PM MCP41XXX/42XXX Note: Unless otherwise indicated, curve represents 10k, 50k, and 100k devices, VDD = 5V, VSS = 0V, TA = 25C, VB = 0V. 90 0.5 Refer to Figure 2-27 VDD = 5V 80 0.3 0.2 Active Supply Current (A) Rheostat INL Error (LSB) 0.4 TA = +85C 0.1 0 TA = +25C -0.1 -0.2 TA = -40C -0.3 FCLK = 3 MHz Code = FFh 70 60 50 40 VDD = 3V -0.4 30 -0.5 0 32 64 96 128 160 192 224 -40 256 -20 0 20 Figure 2-7: Rheostat INL Error vs. Code Figure 2-10: Temperature TA = -40C to 85C, VA = no connect, RWB measured 2500 2000 1500 1000 500 0 32 64 96 128 160 192 224 Active Supply Current (mA) Rheostat Mode TempCo (ppm / C) 3000 0 Active 60 80 Rheostat Mode Tempco vs. Code Current A - VDD = 5.5V, Code = AAh B - VDD = 3.3V, Code = AAh C - VDD = 5.5V, Code = FFh D - VDD = 3.3V, Code = FFh vs. B A C D 1k 256 Supply 1 1000 900 800 700 600 500 400 300 200 100 0 10k Code (Decimal) Figure 2-8: 40 Temperature (C) Code (Decimal) Figure 2-11: Frequency 100k 1M Clock Frequency (Hz) Active Supply Current 10M vs. Clock 1 VDD = 5.5V RS & SHDN Sink Current ( A) 25 Static Current (nA) 20 15 10 5 0 -1 -2 -3 -4 -5 -6 -7 0 -40 -20 0 20 40 60 80 0 Temperature (C) Figure 2-9: Static Current vs. Temperature DS11195A-page 8 1 2 3 4 5 6 RS & SHDN Pin Voltage (V) Figure 2-12: Voltage Reset & Shutdown Pins Current vs. 2000 Microchip Technology Inc. 11195A.book Page 9 Tuesday, November 7, 2000 2:06 PM MCP41XXX/42XXX Note: Unless otherwise indicated, curve represents 10k, 50k, and 100k devices, VDD = 5V, VSS = 0V, TA = 25C, VB = 0V. 180 Number of Occurrences CL = 27pF MCP41010,MCP42010 Code = 00h, Sample Size = 400 160 140 VOUT 120 FFh 100 80 00h 60 40 CS 20 0 47 48 Figure 2-13: Histogram 49 50 51 52 53 54 55 Wiper Resistance () 10k Device 56 57 Wiper 58 59 Resistance Figure 2-16: Full Scale Settling Time 140 Number of Occurrences CL = 27pF MCP41050, MCP41100, MCP42050, MCP42100 Code = 00h, Sample Size = 796 120 100 Code = 80h VOUT 80 60 40 CS 20 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 0 Wiper Resistance () Figure 2-14: 50k, Resistance Histogram 100k Device Wiper Figure 2-17: Digital Feedthrough vs. Time 6 Code = FFh CL = 17pF 0 Code = 80h -6 Code = 40h -12 Code = 20h Code = 7Fh Code = 80h Gain (dB) VOUT -18 Code = 10h -24 Code = 08h -30 Code = 04h -36 Code = 02h -42 Code = 01h CS -48 -54 CL = 30pF, Refer to Figure 2-29 MCP41010, MCP42010 (10k potentiometers) -60 100 Figure 2-15: One Position Settling Time 2000 Microchip Technology Inc. 1k Figure 2-18: Gain Potentiometer 10k 100k Frequency (Hz) vs. 1M Frequency for 10M 10k DS11195A-page 9 11195A.book Page 10 Tuesday, November 7, 2000 2:06 PM MCP41XXX/42XXX Note: Unless otherwise indicated, curve represents 10k, 50k, and 100k devices, VDD = 5V, VSS = 0V, TA = 25C, VB = 0V. 6 40 VDD = 4.5V to 5.5V, Code = 80h, CL = 27pF, VA = 4V Refer to Figure 2-28 Code = FFh 0 35 Code = 80h 10k Potentiometer -6 Code = 40h 30 -12 Code = 20h PSRR (dB) Gain (dB) -18 Code = 10h -24 Code = 08h -30 Code = 04h -36 25 20 50k Potentiometer 15 Code = 02h -42 10 100k Potentiometer Code = 01h -48 5 CL = 30pF, Refer to Figure 2-29 MCP41050, MCP42050 (50k potentiometers) -54 -60 100 0 1k 10k 100k Frequency (Hz) Figure 2-19: Gain Potentiometer vs. 1M Frequency 10M for 50k 1k Figure 2-22: Frequency 6 10k 100k Frequency (Hz) 700 Code = FFh MCP41010, MCP42010 Iw = 1mA, Code = 00h, Refer to Figure 2-27 600 Code = 80h -6 Wiper Resistance () Code = 40h -12 Code = 20h Gain (dB) -18 Code = 10h -24 Code = 08h -30 Code = 04h -36 Code = 02h -42 VDD = 2.7V 500 400 300 200 VDD = 5V Code = 01h 100 -48 CL = 30pF, Refer to Figure 2-29 MCP41100, MCP42100 (100k potentiometers) -54 100 1k Figure 2-20: Gain Potentiometer 10k Frequency (Hz) vs. 0 100k 0 1M Frequency for 100k 1 2 3 4 5 Terminal B Voltage (V) Figure 2-23: 0 10k Wiper Resistance vs. Voltage 450 Code = 00h Refer to Figure 2-27 400 -6 350 Wiper Resistance () 1.06MHz 145kHz -12 Gain (dB) 10M Power Supply Rejection Ratio vs. 0 -60 1M 279kHz 10k -18 -24 300 VDD = 2.7V 250 200 150 VDD = 5V 100 50k -30 50 CL = 30pF, Code = 80h Refer to Figure 2-29 100k 0 -36 1k Figure 2-21: 10k 100k Frequency (Hz) -3 dB Bandwidths DS11195A-page 10 0 1M 10M 1 2 3 4 5 Terminal B Voltage (V) Figure 2-24: Voltage 50k & 100k Wiper Resistance vs. 2000 Microchip Technology Inc. 11195A.book Page 11 Tuesday, November 7, 2000 2:06 PM MCP41XXX/42XXX 2.1 Parametric Test Circuits VA V+ = VDD 1LSB = V+/256 A VDD V+ A V+ W B + - DUT B VMEAS* W + - DUT VMEAS* *Assume infinite input impedance V+ = VDD 10% Figure 2-25: Potentiometer Divider Non-Linearity Error Test Circuit (DNL, INL) VDD PSRR (dB) = 20LOG VMEAS ( ) PSS (%/%) = VDD VMEAS No Connection *Assume infinite input impedance Figure 2-28: Power Supply Sensitivity Test Circuit (PSS, PSRR) A IW W B + - DUT A VMEAS* +5V VIN *Assume infinite input impedance ~ OFFSET GND Figure 2-26: Resistor Position Non-Linearity Error Test Circuit (Rheostat operation DNL, INL) DUT RSW = 0.1V ISW Code = 00h A W B ISW + VOUT - DUT B 2.5V DC Figure 2-29: + - W Gain vs. Frequency Test Circuit A 0.1V DUT B +5V VSS = 0 TO VDD - VOUT MCP601 VIN Figure 2-27: ~ 2.5V DC OFFSET Wiper Resistance Test Circuit Figure 2-30: 2000 Microchip Technology Inc. + Capacitance Test Circuit DS11195A-page 11 11195A.book Page 12 Tuesday, November 7, 2000 2:06 PM MCP41XXX/42XXX 3.0 PIN DESCRIPTIONS PA0, PA1 Potentiometer Terminal A Connection. PB0, PB1 Potentiometer Terminal B Connection. PW0, PW1 Potentiometer Wiper Connection. SHDN Shutdown (MCP42XXX devices only) The Shutdown pin has a Schmit Trigger input. Pulling this pin low will put the device in a power saving mode where A terminal is opened and the B and W terminals are connected for all potentiometers. This pin should not be toggled low when the CS pin is low. In order to minimize power consumption, this pin has an active pull-up circuit. The performance of this circuit is shown in Figure 2-12. This pin will draw negligible current at logic level 0 and logic level 1. CS Chip Select This is the SPI port chip select pin and is used to execute a new command after it has been loaded into the shift register. This pin has a Schmitt Trigger input. SCK Serial Clock This is the SPI port clock pin and is used to clock in new register data. Data is clocked into the SI pin on the rising edge of the clock and out the SO pin on the falling edge of the clock. This pin is gated to the CS pin, i.e., the device will not draw any more current if the SCK pin is toggling when the CS pin is high. This pin has a Schmitt Trigger input. MCP41XXX PINS PIN # NAME 1 CS 2 SCK 3 SI FUNCTION Chip Select Serial Clock Serial Data Input 4 VSS Ground 5 PA0 Terminal A Connection For Pot 0 6 PW0 Wiper Connection For Pot 0 7 PB0 Terminal B Connection For Pot 0 8 VDD Power SI Serial Data Input This is the SPI port serial data input pin. The command and data bytes are clocked into the shift register using this pin. This pin is gated to the CS pin, i.e., the device will not draw any more current if the SI pin is toggling when the CS pin is high. This pin has a Schmitt Trigger input. MCP42XXX PINS PIN # NAME 1 CS 2 SCK 3 SI FUNCTION Chip Select Serial Clock Serial Data Input SO Serial Data Output (MCP42XXX devices only) 4 VSS Ground 5 PB1 Terminal B Connection For Pot 1 This is the SPI port serial data output pin used for daisy chaining more than one device. Data is clocked out of the SO pin on the falling edge of clock. This is a pushpull output and does not go to a high impedance state when CS is high. It will drive a logic low when CS is high. 6 PW1 Wiper Connection For Pot 1 7 PA1 Terminal A Connection For Pot 1 8 PA0 Terminal A Connection For Pot 0 9 PW0 Wiper Connection For Pot 0 10 PB0 Terminal B Connection For Pot 0 RS Reset Input RS Reset (MCP42XXX devices only) 11 The Reset pin will set all potentiometers to mid-scale (Code 80h) if this pin is brought low for at least 150ns. This pin should not be toggled low when the CS pin is low. It is possible to toggle this pin when the SHDN pin is low. In order to minimize power consumption, this pin has an active pull-up circuit. The performance of this circuit is shown in Figure 2-12. This pin will draw negligible current at logic level 0 and logic level 1. 12 DS11195A-page 12 SHDN Shutdown Input 13 SO Data Out for Daisy Chaining 14 VDD Power 2000 Microchip Technology Inc. 11195A.book Page 13 Tuesday, November 7, 2000 2:06 PM MCP41XXX/42XXX 4.0 APPLICATIONS INFORMATION nects the wiper to the B terminal. At power up, all data registers will automatically be loaded with the midscale value, 80h. The serial interface provides the means for loading data into the shift register which is then transferred to the data registers. The serial interface also provides the means to place individual potentiometers in the shutdown mode for maximum power savings. The SHDN pin can also be used to put all potentiometers in shutdown mode and the RS pin is provided to set all potentiometers to mid-scale, 80h. The MCP41XXX/42XXX devices are 256 tap single and dual digital potentiometers that can be used in place of standard mechanical pots. Resistance values of 10k, 50k and 100k are available. As shown in Figure 4-1, each potentiometer is made up of a variable resistor and an 8-bit (256 position) data register that determines the wiper position. There is a nominal wiper resistance of 52 for the 10k version and 125 for the 50k and 100k versions. For the dual devices, the channel to channel matching variation is less than 1%. The resistance between the wiper and either of the resistor endpoints varies linearly according to the value stored in the data register. Code 00h effectively con- PA0 PW0 PB0 PA1 PW1 PB1 RDAC1 RDAC2 Data Register 1 Data Register 0 D7 D7 D0 D0 RS Decode Logic CS D7 D0 16 Bit Shift Register SCK SI SO SHDN Figure 4-1: Block diagram showing the MCP42XXX dual digital potentiometer. Data register 0 and data register 1 are 8-bit registers allowing 256 tap positions for each wiper. Standard SPI pins are used with the addition of the Shutdown (SHDN) and Reset (RS) pins. As shown, reset affects the data register and wipers, bringing them to midscale. Shutdown disconnects the A terminal and connects the wiper to B, without changing the state of the data registers. VDD VDD 0.1uF 0.1uF MCP4XXXX B C Data Lines W A To Application Circuit 2000 Microchip Technology Inc. When laying out the circuit for your digital potentiometer, bypass capacitors should be used. These capacitors should be placed as close as possible to the device pin. A bypass capacitor value of 0.1 F is recommended. Digital and analog traces should be separated as much as possible on the board, and no traces should run underneath the device or the bypass capacitor. Extra precautions should be taken to keep traces with high frequency signals (such as clock lines) as far as possible from analog traces. Use of an analog ground plane is recommended in order to keep the ground potential the same for all devices on the board. DS11195A-page 13 11195A.book Page 14 Tuesday, November 7, 2000 2:06 PM MCP41XXX/42XXX 4.1 Modes of Operation Digital potentiometer applications can be divided up into two categories: rheostat mode and potentiometer or voltage divider mode. 4.1.1 RHEOSTAT MODE In the rheostat mode, the potentiometer is used as a two terminal resistive element. The unused terminal should be tied to the wiper as shown in Figure 4-2. Note that reversing the polarity of the A and B terminals will not affect operation. 4.1.2 POTENTIOMETER MODE In the potentiometer mode, all three terminals of the device are tied to different nodes in the circuit. This allows the potentiometer to output a voltage proportional to the input voltage. This mode is sometimes called voltage divider mode. The potentiometer is used to provide a variable voltage by adjusting the wiper position between the two endpoints as shown in Figure 4-3. Note that reversing the polarity of the A and B terminals will not affect operation. V1 A A W W B B MCP4XXXX MCP4XXXX RESISTOR Figure 4-2: Two terminal or rheostat configuration for the digital potentiometer. Acting as a resistive element in the circuit, resistance is controlled by changing the wiper setting. Using the device in this mode allows control of the total resistance between the two nodes. The total measured resistance would be the least at code 00h, where the wiper is tied to the B terminal. The resistance at this code is equal to the wiper resistance, typically 52 for the 10k devices (MCP4X010), 125 for the 50k (MCP4X050), and 100k (MCP4X100) devices. For the 10k device, the LSB size would be 39.0625 (assuming 10k total resistance). The resistance would then increase with this LSB size until the total measured resistance at code FFh would be 9985.94. The wiper will never directly connect to the A terminal of the resistor stack. In the 00h state, the total resistance is the wiper resistance. To avoid damage to the internal wiper circuitry in this configuration, care should be taken to insure the current flow never exceeds 1mA. For dual devices, the variation of channel-to-channel matching of the total resistance from A to B is less than 1%. The device-to-device matching however can vary up to 30%. In the rheostat mode, the resistance has a positive temperature coefficient. The change in wiperto-end terminal resistance over temperature is shown in Figure 2-8. The most variation over temperature will occur in the first 6% of codes (code 00h to 0Fh) due to the wiper resistance coefficient affecting the total resistance. The remaining codes are dominated by the total resistance tempco RAB, typically 800 ppm/C. DS11195A-page 14 V2 Figure 4-3: Three terminal or voltage divider mode In this configuration, the ratio of the internal resistances define the temperature coefficient of the device. The resistor matching of the RWB resistor to the RAB resistor performs with a typical temperature coefficient of 1 ppm/C (measured at code 80h). At lower codes, the wiper resistance temperature coefficient will dominate. Figure 2-3 shows the effect of the wiper. Above the lower codes, this figure shows that 70% of the states will typically have a temperature coefficient of less than 5 ppm/C. 30% of the states will typically have a ppm/ C of less than 1. 4.2 Typical Applications 4.2.1 PROGRAMMABLE SINGLE ENDED AMPLIFIERS Potentiometers are often used to adjust system reference levels or gain. Programmable gain circuits using digital potentiometers can be realized in a number of different ways. An example of a single supply inverting gain amplifier is shown in Figure 4-4. Due to the high input impedance of the amplifier, the wiper resistance is not included in the transfer function. For a single supply non-inverting gain configuration, the circuit in Figure 4-5 can be used. 2000 Microchip Technology Inc. 11195A.book Page 15 Tuesday, November 7, 2000 2:06 PM MCP41XXX/42XXX approaches either terminal, the step size in the gain calculation increases dramatically. Due to the mismatched ratio of RA and RB at the extreme high and low codes, small increments in wiper position can dramatically affect the gain. As shown in Figure 4-3, recommended gains lie between 0.1 and 10 V/V. . MCP41010 B A VDD W -IN - VOUT MCP606 VREF +IN 10 + VSS V Where: R A OUT = -V R B R B -------- + V 1 + -------- REF IN R R A A R ( 256 - D ) AB n = -----------------------------------------256 R B R D AB n = --------------------256 0.1 Figure 4-4: Single supply programmable inverting gain amplifier using a digital potentiometer. + VOUT MCP606 -IN VSS W RA Where: R A RB MCP41010 V R AB ( 256 - D n ) = -----------------------------------------256 R RAB = Total resistance of pot 0 OUT B = V R B 1 + -------- IN R A R D AB n = --------------------256 64 128 192 256 Decimal code (0-255) Figure 4-6: Gain vs. Code for inverting and differential amplifier circuits. 4.2.2 VDD +IN 1 Dn = Wiper Setting For Dn = 0 to 255 RAB = Total resistance of pot VIN Absolute Gain (V/V) VIN PROGRAMMABLE DIFFERENTIAL AMPLIFIER An example of a differential input amplifier using digital potentiometers is shown in Figure 4-7. For the transfer function to hold, both pots must be programmed to the same code. The resistor matching from channel-tochannel within a dual device can be used as an advantage in this circuit. This circuit will also show stable operation over temperature due to the low potentiometer temperature coefficient. Figure 4-6 also shows the relationship between gain and code for this circuit. As the wiper approaches either terminal, the step size in the gain calculation increases dramatically. This circuit is recommended for gains between 0.1 and 10 V/V. Dn = Wiper Setting For Dn = 0 to 255 Figure 4-5: Single Supply Programmable Noninverting gain amplifier In order for these circuits to work properly, care must be taken in a few areas. For linear operation, the analog input and output signals must be in the range of Vss to VDD for the potentiometer and input and output rails of the op-amp. The circuit in Figure 4-4 requires a virtual ground or reference input to the non-inverting input of the amplifier. Refer to Application Note AN682, "Using Single Supply Operational Amplifiers in Embedded Systems" for more detail. At power up or reset (RS), the resistance is set to mid-scale and RA and RB match. Based on the transfer function for the circuit, the gain is -1 V/V. As the code is increased and the wiper moves towards the A terminal and the gain increases. Conversely, when the wiper is moved towards the B terminal, the gain decreases. Figure 4-6 shows this relationship. Notice the pseudo-logarithmic gain around decimal code 128. As the wiper 2000 Microchip Technology Inc. DS11195A-page 15 11195A.book Page 16 Tuesday, November 7, 2000 2:06 PM MCP41XXX/42XXX 4.3 1/2 MCP42010 VB B A (SIG -) VDD -IN VA + 1/2 MCP42010 +IN VSS B When programming the digital potentiometer settings, the following equations can be used to calculate the resistances. Programming code 00h effectively brings the wiper to the B terminal, leaving only the wiper resistance. Programming higher codes will bring the wiper closer to the A terminal of the potentiometer. The equations in Figure 4-9 can be used to calculate the terminal resistances. Figure 4-10 shows an example calculation using a 10k potentiometer. R V OUT = ( V A - V B ) ------BRA VREF Where: R Vout MCP601 A (SIG +) Calculating Resistances R ( 256 - D ) AB n = -----------------------------------------A 256 R PA PW R D AB n = --------------------B 256 RAB = Total resistance of pot PB (RAB)(256 - Dn) RWA(Dn) = + RW 256 Dn = Wiper Setting For Dn = 0 to 255 NOTE: Potentiometer values must be equal Figure 4-7: Single Supply programmable differential amplifier using digital potentiometers. 4.2.3 PROGRAMMABLE OFFSET TRIM For applications requiring only a programmable voltage reference, the circuit in Figure 4-8 can be used. This circuit shows the device used in the potentiometer mode along with two resistors and a buffered output. This creates a circuit with a linear relationship between voltage out and programmed code. Resistors R1 and R2 can be used to increase or decrease the output voltage step size. The potentiometer in this mode is stable over temperature. The operation of this circuit over temperature is shown in Figure 2-3. The worst performance over temperature will occur at the lower codes due to the dominating wiper resistance. R1 and R2 can also be used to affect the boundary voltages thereby eliminating the use of these lower codes. RWB(Dn) = 256 + RW Where: PA is A terminal PB is B terminal PW is Wiper Terminal RWA is resistance between Terminal A and wiper RWB is resistance between Terminal B and Wiper RAB is overall resistance for pot (10k,50k or 100k) RW is wiper resistance Dn is 8-bit value in data register for pot number n Figure 4-9: Potentiometer resistances are a function of code. It should be noted that when using these equations for most feedback amplifier circuits (see Figure 4-4 and Figure 4-5), the wiper resistance can be omitted due to the high impedance input of the amplifier. 10k PA EXAMPLE: PW R = 10k Code = C0h = 192d PB VDD VDD R1 MCP41010 (RAB)(Dn) -IN - MCP606 A +IN RWA(Dn) = (10k)(256-192) + 52 256 RWA(C0h) = 2552 RWA(C0h) = OUT + VSS B (RAB)(256 - Dn) + RW 256 0.1 uF R2 VSS RWB(Dn) = (RAB)(Dn) + RW 256 (10k)(192) RWB(C0h) = + 52 256 RWB(C0h) = 7552 Figure 4-8: By changing the values of R1 and R2, the voltage output resolution of this programmable voltage reference circuit is affected. Note: All values shown are typical and actual results will vary. Figure 4-10: DS11195A-page 16 Example Resistance calculations. 2000 Microchip Technology Inc. 11195A.book Page 17 Tuesday, November 7, 2000 2:06 PM MCP41XXX/42XXX 5.0 SERIAL INTERFACE Communications from the controller to the MCP41XXX/42XXX digital potentiometers is done using the SPI serial interface. This interface allows three commands: 1. 2. 3. Write a new value to the potentiometer data register(s). Cause a channel to enter low power shutdown mode. NOP (No Operation) command. Executing any command is done by setting CS low, and then clocking in a command byte followed by a data byte into the 16-bit shift register. The command is executed when CS is raised. Data is clocked in on the rising edge of clock and out the SO pin on the falling edge of the clock. See Figure 5-1. The device will track the number of clocks (rising edges) while CS is low and will abort all commands if the number of clocks is not a multiple of 16. 5.1 Command Byte The first byte sent is always the command byte, followed by the data byte. The command byte contains two command select bits and two potentiometer select bits. Unused bits are don't care bits. The command select bits are summarized in Figure 5-2. The command select bits C1 and C0 (bits 4:5) of the command byte determine which command will be executed. If the command bits are both 0's or 1's, then a NOP command will be executed after all 16 bits have been loaded. This command is useful when using the daisychain configuration. When the command bits are 0,1 a write command will be executed with the 8 bits sent in the data byte. The data will be written to the potentiometer(s) determined by the potentiometer select bits. If the command bits are 1,0 then a shutdown command will be executed on the potentiometers determined by the potentiometer select bits. For the MCP42XXX devices, the potentiometer select bits P1 and P0 (bits 0:1) determine which potentiometers are to be acted upon by the command. A corresponding one in the position signifies that the command for that potentiometer will get executed and a zero signifies that the command will not effect that potentiometer. See Figure 5-2. 5.2 Writing Data Into Data Registers When new data is written into one or more of the potentiometer data registers, the write command is followed by the data byte for the new value. The command select bits C1, C0 are set to 0,1. The potentiometer selection bits P1 and P0 allow new values to be written to potentiometer 0, potentiometer 1 or both with a single command. A one for either P1 or P0 will cause the data to be written to the respective data register and a zero for P1 or P0 will cause no change. See Figure 5-2 for the command format summary. 5.3 Using The Shutdown Command The shutdown command allows the user to put the application circuit into a power saving mode. In this mode, the A terminal is open circuited and the B and W terminals are shorted together. The command select bits C1, C0 are set to 1,0. The potentiometer selection bits P1 and P0 allow each potentiometer to be shutdown independently. If either P1 or P0 are high, the respective potentiometer will enter shutdown mode. A zero for P1 or P0 will have no effect. The eight data bits following the command byte still need to be transmitted for the shutdown command but they are don't care bits. See Figure 5-2 for command format summary. Once a particular potentiometer has entered the shutdown mode, it will remain in this mode until: * A new value is written to the potentiometer data register, provided that the SHDN pin is high. The device will remain in the shutdown mode until the rising edge of the CS is detected, at which time the device will come out of shutdown mode and the new value will be written to the data register(s). If the SHDN pin is low when the new value is received, the registers will still be set to the new value, but the device will remain in shutdown mode. This scenario assumes that a valid command was received. If an invalid command was received, the command will be ignored and the device will remain in the shutdown mode. It is also possible to use the hardware shutdown pin and reset pin to remove a device from software shutdown. To do this, a low pulse on the chip select line must first be sent. For multiple devices, sharing a single SHDN or RESET line, allows you to pick an individual device on that chain to remove from software shutdown mode. See Figure 1-3 for timing. With a preceding chip select pulse, either of these situations will also remove a device from software shutdown: * A falling edge is seen on the RS pin and held low for at least 150ns, provided that the SHDN pin is high. If the SHDN pin is low, the registers will still be set to mid-scale but the device will remain in shutdown mode. This condition assumes that CS is high, as bringing the RS pin low while CS is low is an invalid state and results are indeterminate. 2000 Microchip Technology Inc. DS11195A-page 17 11195A.book Page 18 Tuesday, November 7, 2000 2:06 PM MCP41XXX/42XXX * A rising edge on the SHDN pin is seen after being low for at least 100ns, provided that the CS pin is high. Toggling the SHDN pin low while CS is low is an invalid state and results are indeterminate. * The device is powered down and back up. Note: The hardware SHDN pin will always put the device in shutdown regardless of whether a potentiometer has already been put in the shutdown mode using the software command. Data is always clocked out the SO pin after the falling edge of SCK Data is always latched in on the rising edge of SCK CS 1 2 3 4 5 6 7 8 9 10 11 12 Data Registers are loaded on rising edge of CS. Shift register is loaded with zeros at this time 13 14 15 16 SCK COMMAND BYTE Don't Care Bits X SI SO X Command Bits C1 C0 Don't Care Bits X DATA BYTE Channel Select Bits New Register Data X P1* P0 D7 D6 D5 D4 D3 D2 D1 D0 First 16 bits Shifted out will always be zeros X SO pin will always drive low when CS goes high There must always be multiples of 16 clocks while CS is low or commands will abort The serial data out pin (SO) is only available on the MCP42XXX device * P1 is a don't care bit for the MCP41XXX Figure 5-1: Timing Diagram for Writing Instructions or Data to a Digital Potentiometer COMMAND BYTE X X C1 C0 X X P1* P0 Command Selection Bits C1 C0 P1* P0 Potentiometer Selections 0 0 None No Command will be executed 0 0 Dummy Code: Neither Potentiometer affected 0 1 Write Data Write the data contained in Data Byte to the potentiometer(s) determined by the potentiometer selection bits 0 1 Command executed on Potentiometer 0 1 0 Command executed on Potentiometer 1 1 1 1 1 0 1 Figure 5-2: Command Shutdown None Command Summary Potentiometer Selection Bits Potentiometer(s) determined by potentiometer selection bits will enter Shutdown Mode. Data bits for this command are don't cares Command executed on both Potentiometers *PI is a don't care bit for the MCP41XXX No Command will be executed Command Byte Format DS11195A-page 18 2000 Microchip Technology Inc. 11195A.book Page 19 Tuesday, November 7, 2000 2:06 PM MCP41XXX/42XXX 5.4 Daisy-Chain Configuration Multiple MCP42XXX devices can be connected in a daisy-chain configuration as shown in Figure 5-4, by connecting the SO pin from one device to the SI pin on the next device. The data on the SO pin is the output of the 16-bit shift register. The daisy-chain configuration allows the system designer to communicate with several devices without using a separate CS line for each device. The example shows a daisy chain configuration with three devices, although any number of devices (with or without the same resistor values) can be configured this way. While it is not possible to use a MCP41XXX at the beginning or middle of a daisy-chain because it does not provide the serial data out (SO) pin, it is possible to use the device at the end of a chain. As shown in the timing diagram in Figure 5-3, data will be clocked out of the SO pin on the falling edge of the clock. The SO pin has a CMOS push-pull output and will drive low when CS goes high. SO will not go to a high impedance state when CS is held high. When using the daisy-chain configuration, the maximum clock speed possible is reduced to ~5.8MHz because of the propagation delay of the data coming out of the SO pin. When using the daisy-chain configuration, keep in mind that the shift register of each device is automatically loaded with zeros whenever a command is executed (CS = high). Because of this, the first 16 bits that come out of the SO pin after the CS line goes low will always be zeros. This means that when the first command is being loaded into a device, it will always shift a NOP command into the next device on the chain because the command bits (and all the other bits) will be zeros. This feature makes it necessary only to send command and data bytes to the device farthest down the chain that needs a new command. For example, if there were three devices on the chain and it was desired to send a command to the device in the middle, only 32 bytes of data need to be transmitted. The last device on the chain will have a NOP loaded from the previous device so no registers will be affected when the CS pin is raised to execute the command. The user must always ensure that multiples of 16 clocks are always provided (while CS is low) as all commands will abort if the number of clocks provided is not a multiple of 16. Data Registers for all devices are Loaded on Rising Edge of CS CS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 1415 16 SCK Command Byte for Device 3 SI Data Byte for Device 3 X XC C X XP PDDD DDDD D First 16 bits shifted out will always be zeros SO Figure 5-3: Command Byte for Device 2 Data Byte for Device 2 X XCC X X P PDDD DDDD D Command and Data for Device 3 start shifting out after the first 16 clocks X XCC X XP PDDD DDDD D Command Byte for Device 1 Data Byte for Device 1 X XCC X XP PD DD DDDD D Command and Data for Device 2 start shifting out after the first 32 clocks X XCC X X P PDDD DDDD D There must always be multiples of 16 clocks while CS is low or commands will abort The serial data out pin (SO) is only available on the MCP42XXX device Timing Diagram for Daisy-Chain Configuration 2000 Microchip Technology Inc. DS11195A-page 19 11195A.book Page 20 Tuesday, November 7, 2000 2:06 PM MCP41XXX/42XXX CS SCK Microcontroller SO CS SCK SI SO CS SCK Device 1 SI SO CS SCK EXAMPLE: Device 2 If you want to load the following command/data into each part in the chain. Device 3* Device 1 XX10XX11 11001100 Device 2 XX01XX10 11110000 Device 1 XX10XX00 10101010 Device 2 00000000 00000000 Device 3 00000000 00000000 After 32 clocks, Device 2 has the data previously loaded into Device 1 and Device 3 gets 16 more zeros. 2 Clock-In the command and data for Device 2 (16 more clocks). The data that was previously loaded gets shifted to the next device on the chain. Device 3 XX10XX00 10101010 After 16 clocks, Device 2 and Device 3 will both have all zeros clocked in from the previous part's shift register. 1 Start by setting CS low and clocking in the command and data that will end up in Device 3 (16 clocks). SI Device 1 XX01XX10 11110000 Device 2 XX10XX00 10101010 Device 3 00000000 00000000 3 Clock-In the data for Device 1 (16 more clocks). The data that was previously loaded into Device 1 gets shifted into Device 2 and Device 3 contains the first byte loaded. Raise the CS line to execute the commands for all 3 devices at the same time. Figure 5-4: After 48 clocks, all 3 devices have the proper command/ data loaded into their shift registers. Device 1 XX10XX11 11001100 Device 2 XX01XX10 11110000 Device 3 XX10XX00 10101010 *Note: Last device on a daisy chain may be a single channel MCP41XXX device. Daisy-Chain Configuration DS11195A-page 20 2000 Microchip Technology Inc. 11195A.book Page 21 Tuesday, November 7, 2000 2:06 PM MCP41XXX/42XXX 5.5 Reset (RS) Pin Operation The Reset pin (RS) will automatically set all potentiometer data latches to mid scale (Code 80h) when pulled low (provided that the pin is held low at least 150ns and CS is high). The reset will execute regardless of the position of the SCK, SHDN and SI pins. It is possible to toggle RS low and back high while SHDN is low. In this case, the potentiometer registers will reset to mid-scale but the potentiometer will remain in shutdown mode until the SHDN pin is raised. Note: 5.6 Bringing the RS pin low while the CS pin is low constitutes an invalid operating state and will result in indeterminate results when RS and/or CS are brought high. While in shutdown mode, it is still possible to clock in new values for the data registers as well as togging the RS pin to cause all data registers to go to mid-scale. The new values will take affect when the SHDN pin is raised. If the device is powered up with the SHDN pin held low, it will power up in the shutdown mode with the data registers set to mid-scale. 5.7 Truth Table for Logic Inputs SCK CS RS SHDN Action X H H Communication is initiated with device. Device comes out of standby mode. L L H H No action, device is waiting for data to be clocked into shift register or CS to go high to execute command. L H X Shift one bit into shift register. The shift register can be loaded while the SHDN pin is low. L H X Shift one bit out of shift register on the SO pin. The SO pin is active while the SHDN pin is low. X H H Based on command bits, either load data from shift register into data latches or execute shutdown command. Neither command executed unless multiples of 16 clocks have been entered while CS is low. SO pin goes to a logic low. X H H H Static Operation X H H All data registers set and latched to code 80h. X H L All data registers set and latched to code 80h. Device is in hardware shutdown mode and will remain in this mode. X H H All potentiometers put into hardware shutdown mode; terminal A is open and W is shorted to B X H H All potentiometers exit hardware shutdown mode. Potentiometers will also exit software shutdown mode if this rising edge occurs after a low pulse on CS. Contents of data latches are restored. Shutdown (SHDN) Pin Operation When held low, the shutdown pin causes the application circuit to go into a power saving mode by open circuiting the A terminal and shorting the B and W terminals for all potentiometers. Data register contents are not affected by entering shutdown mode, i.e., when the SHDN pin is raised, the data register contents are the same as before the shutdown mode was entered. Note: Table 5-1 Bringing the SHDN pin low while the CS pin is low constitutes an invalid operating state and will result in indeterminate results when SHDN and/or CS are brought high. Power-up Considerations When the device is powered on, the data registers will be set to mid-scale (80h). A power-on reset circuit is utilized to insure that the device powers up in this known state. 2000 Microchip Technology Inc. DS11195A-page 21 11195A.book Page 22 Tuesday, November 7, 2000 2:06 PM MCP41XXX/42XXX 5.8 Using the MCP41XXX/42XXX in SPI Mode 1,1 It is possible to operate the devices in SPI modes 0,0 and 1,1. The only difference between these two modes is that when using mode 1,1 the clock idles in the high state and in mode 0,0 the clock idles in the low state. In both modes, data is clocked into the devices on the rising edge of SCK and data is clocked out the SO pin after the falling edge of SCK. Operations using mode 0,0 are shown in Figure 5-1. The example in Figure 5-5 shows mode 1,1. Data is always latched in on the rising edge of SCK Data is always clocked out the SO pin after the falling edge of SCK CS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Data Registers are loaded on rising edge of CS. Shift register is loaded with zeros at this time SCK COMMAND BYTE Don't Care Bits X SI SO Figure 5-5: X Command Bits C1 C0 Don't Care Bits X DATA BYTE Channel Select Bits New Register Data X P1* P0 D7 D6 D5 D4 D3 D2 D1 D0 First 16 bits Shifted out will always be zeros X There must always be multiples of 16 clocks while CS is low or commands will abort The serial data out pin (SO) is only available on the MCP42XXX device SO pin will always drive low when CS goes high Timing Diagram for SPI Mode 1,1 Operation DS11195A-page 22 2000 Microchip Technology Inc. 11195A.book Page 23 Tuesday, November 7, 2000 2:06 PM MCP41XXX/42XXX 6.0 PACKAGING INFORMATION 6.1 Package Marking Information 8-Lead PDIP (300 mil) Example XXXXXXXX XXXXXNNN YYWW MCP41XXX XXXXXNNN 0025 8-Lead SOIC (150 mil) XXXXXXX XXXYYWW NNN MCP41XXX XXX0025 NNN 14-Lead PDIP (300 mil) XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN 14-Lead SOIC (150 mil) Example MCP42XXX XXXXXXXXXXXXXX 0025NNN Example XXXXXXXXXX MCP42XXX YYWWNNN 0025NNN 14-Lead TSSOP Example XXXXXX YYWW XXXXXX YYWW NNN NNN Legend: XX...X YY WW NNN Note: * Example Customer specific information* Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask rev#, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. 2000 Microchip Technology Inc. DS11195A-page 23 11195A.book Page 24 Tuesday, November 7, 2000 2:06 PM MCP41XXX/42XXX 8-Lead Plastic Dual In-line (P) - 300 mil (PDIP) E1 D 2 n 1 E A2 A L c A1 B1 p eB B Units Dimension Limits n p Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic A A2 A1 E E1 D L c B1 B eB MIN .140 .115 .015 .300 .240 .360 .125 .008 .045 .014 .310 5 5 INCHES* NOM MAX 8 .100 .155 .130 .170 .145 .313 .250 .373 .130 .012 .058 .018 .370 10 10 .325 .260 .385 .135 .015 .070 .022 .430 15 15 MILLIMETERS NOM 8 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 9.14 9.46 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10 MIN MAX 4.32 3.68 8.26 6.60 9.78 3.43 0.38 1.78 0.56 10.92 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-018 DS11195A-page 24 2000 Microchip Technology Inc. 11195A.book Page 25 Tuesday, November 7, 2000 2:06 PM MCP41XXX/42XXX 8-Lead Plastic Small Outline (SN) - Narrow, 150 mil (SOIC) E E1 p D 2 B n 1 h 45 c A2 A L Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic A A2 A1 E E1 D h L c B MIN .053 .052 .004 .228 .146 .189 .010 .019 0 .008 .013 0 0 A1 INCHES* NOM 8 .050 .061 .056 .007 .237 .154 .193 .015 .025 4 .009 .017 12 12 MAX .069 .061 .010 .244 .157 .197 .020 .030 8 .010 .020 15 15 MILLIMETERS NOM 8 1.27 1.35 1.55 1.32 1.42 0.10 0.18 5.79 6.02 3.71 3.91 4.80 4.90 0.25 0.38 0.48 0.62 0 4 0.20 0.23 0.33 0.42 0 12 0 12 MIN MAX 1.75 1.55 0.25 6.20 3.99 5.00 0.51 0.76 8 0.25 0.51 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-057 2000 Microchip Technology Inc. DS11195A-page 25 11195A.book Page 26 Tuesday, November 7, 2000 2:06 PM MCP41XXX/42XXX 14-Lead Plastic Dual In-line (P) - 300 mil (PDIP) E1 D 2 n 1 E A2 A L c A1 B1 eB p B Units Dimension Limits n p MIN INCHES* NOM 14 .100 .155 .130 MAX MILLIMETERS NOM 14 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 18.80 19.05 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10 MIN Number of Pins Pitch Top to Seating Plane A .140 .170 Molded Package Thickness A2 .115 .145 Base to Seating Plane A1 .015 Shoulder to Shoulder Width E .300 .313 .325 Molded Package Width E1 .240 .250 .260 Overall Length D .740 .750 .760 Tip to Seating Plane L .125 .130 .135 c Lead Thickness .008 .012 .015 Upper Lead Width B1 .045 .058 .070 Lower Lead Width B .014 .018 .022 Overall Row Spacing eB .310 .370 .430 Mold Draft Angle Top 5 10 15 Mold Draft Angle Bottom 5 10 15 * Controlling Parameter Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-005 DS11195A-page 26 MAX 4.32 3.68 8.26 6.60 19.30 3.43 0.38 1.78 0.56 10.92 15 15 2000 Microchip Technology Inc. 11195A.book Page 27 Tuesday, November 7, 2000 2:06 PM MCP41XXX/42XXX 14-Lead Plastic Small Outline (SL) - Narrow, 150 mil (SOIC) E E1 p D 2 B n 1 h 45 c A2 A A1 L Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic A A2 A1 E E1 D h L c B MIN .053 .052 .004 .228 .150 .337 .010 .016 0 .008 .014 0 0 INCHES* NOM 14 .050 .061 .056 .007 .236 .154 .342 .015 .033 4 .009 .017 12 12 MAX .069 .061 .010 .244 .157 .347 .020 .050 8 .010 .020 15 15 MILLIMETERS NOM 14 1.27 1.35 1.55 1.32 1.42 0.10 0.18 5.79 5.99 3.81 3.90 8.56 8.69 0.25 0.38 0.41 0.84 0 4 0.20 0.23 0.36 0.42 0 12 0 12 MIN MAX 1.75 1.55 0.25 6.20 3.99 8.81 0.51 1.27 8 0.25 0.51 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-065 2000 Microchip Technology Inc. DS11195A-page 27 11195A.book Page 28 Tuesday, November 7, 2000 2:06 PM MCP41XXX/42XXX 14-Lead Plastic Thin Shrink Small Outline (ST) - 4.4 mm (TSSOP) E E1 p D 2 1 n B A c A1 L Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Molded Package Length Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic A A2 A1 E E1 D L c B1 MIN .033 .002 .246 .169 .193 .020 0 .004 .007 0 0 INCHES NOM 14 .026 .035 .004 .251 .173 .197 .024 4 .006 .010 5 5 A2 MAX .043 .037 .006 .256 .177 .201 .028 8 .008 .012 10 10 MIN MILLIMETERS* NOM 14 0.65 0.85 0.05 6.25 4.30 4.90 0.50 0 0.09 0.19 0 0 0.90 0.10 6.38 4.40 5.00 0.60 4 0.15 0.25 5 5 MAX 1.10 0.95 0.15 6.50 4.50 5.10 0.70 8 0.20 0.30 10 10 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side. JEDEC Equivalent: MO-153 Drawing No. C04-087 DS11195A-page 28 2000 Microchip Technology Inc. 11195A.book Page 29 Tuesday, November 7, 2000 2:06 PM MCP41XXX/42XXX ON-LINE SUPPORT Microchip provides on-line support on the Microchip World Wide Web (WWW) site. The web site is used by Microchip as a means to make files and information easily available to customers. To view the site, the user must have access to the Internet and a web browser, such as Netscape or Microsoft Explorer. Files are also available for FTP download from our FTP site. Connecting to the Microchip Internet Web Site Systems Information and Upgrade Hot Line The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products. Plus, this line provides information on how customers can receive any currently available upgrade kits.The Hot Line Numbers are: 1-800-755-2345 for U.S. and most of Canada, and 1-480-792-7302 for the rest of the world. 000815 The Microchip web site is available by using your favorite Internet browser to attach to: www.microchip.com The file transfer site is available by using an FTP service to connect to: ftp://ftp.microchip.com The web site and file transfer site provide a variety of services. Users may download files for the latest Development Tools, Data Sheets, Application Notes, User's Guides, Articles and Sample Programs. A variety of Microchip specific business information is also available, including listings of Microchip sales offices, distributors and factory representatives. Other data available for consideration is: * Latest Microchip Press Releases * Technical Support Section with Frequently Asked Questions * Design Tips * Device Errata * Job Postings * Microchip Consultant Program Member Listing * Links to other useful web sites related to Microchip Products * Conferences for products, Development Systems, technical information and more * Listing of seminars and events 2000 Microchip Technology Inc. Trademarks: The Microchip name, logo, PIC, PICmicro, PICSTART, PICMASTER, PRO MATE and MPLAB are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FlexROM, microID and fuzzyLAB are trademarks and SQTP is a service mark of Microchip in the U.S.A. All other trademarks mentioned herein are the property of their respective companies. DS11195A-page 29 11195A.book Page 30 Tuesday, November 7, 2000 2:06 PM MCP41XXX/42XXX READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-7578. Please list the following information, and use this outline to provide us with your comments about this Data Sheet. To: Technical Publications Manager RE: Reader Response Total Pages Sent From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y Device: MCP41XXX/42XXX N Literature Number: DS11195A Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this data sheet easy to follow? If not, why? 4. What additions to the data sheet do you think would enhance the structure and subject? 5. What deletions from the data sheet could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? 8. How would you improve our software, systems, and silicon products? DS11195A-page 30 2000 Microchip Technology Inc. 11195A.book Page 31 Tuesday, November 7, 2000 2:06 PM MCP41XXX/42XXX MCP41XXX/42XXX PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. MCP41XXX/42XXX -- X /X Package: Temperature Range: P = PDIP (8-lead/14-lead, 300 mil body) SL = SOIC (8-lead/14-lead, 150 mil body) TS = TSSOP (14-lead, 4.4mm body) I = -40C to +85C MCP41010 MCP41010T MCP410501 MCP41050T MCP41100 MCP41100T = = = = = = Single Digital Potentiometer (10k) Single Digital Potentiometer (10k)[Tape & Reel] Single Digital Potentiometer (50k) Single Digital Potentiometer (50k)[Tape & Reel] Single Digital Potentiometer (100k) Single Digital Potentiometer (100k)[Tape & Reel] MCP42010 MCP42010T MCP42050 MCP42050T MCP42100 MCP42100T = = = = = = Dual Digital Potentiometer (10k) Dual Digital Potentiometer (10k)[Tape & Reel]) Dual Digital Potentiometer (50k) Dual Digital Potentiometer (50k)[Tape & Reel]) Dual Digital Potentiometer (100k) Dual Digital Potentiometer (100k)[Tape & Reel]) Device: Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. Your local Microchip sales office (see last page) 2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 3. The Microchip's Bulletin Board, via your local CompuServe number (CompuServe membership NOT required). Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products. 2000 Microchip Technology Inc. DS11195A-page 31 11195A.book Page 32 Tuesday, November 7, 2000 2:06 PM WORLDWIDE SALES AND SERVICE AMERICAS ASIA/PACIFIC Corporate Office China - Beijing Singapore 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: 480-792-7627 Web Address: http://www.microchip.com Microchip Technology Beijing Office Unit 915 New China Hong Kong Manhattan Bldg. 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Benex S-1 6F 3-18-20, Shinyokohama Kohoku-Ku, Yokohama-shi Kanagawa, 222-0033, Japan Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea Microchip Technology Korea 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku Seoul, Korea Tel: 82-2-554-7200 Fax: 82-2-558-5934 150 Motor Parkway, Suite 202 Hauppauge, NY 11788 Tel: 631-273-5305 Fax: 631-273-5335 San Jose Microchip Technology Inc. 2107 North First Street, Suite 590 San Jose, CA 95131 Tel: 408-436-7950 Fax: 408-436-7955 Italy Arizona Microchip Technology SRL Centro Direzionale Colleoni Palazzo Taurus 1 V. Le Colleoni 1 20041 Agrate Brianza Milan, Italy Tel: 39-039-65791-1 Fax: 39-039-6899883 United Kingdom Arizona Microchip Technology Ltd. 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44 118 921 5869 Fax: 44-118 921-5820 10/01/00 Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999. The Company's quality system processes and procedures are QS-9000 compliant for its PICmicro(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs and microperipheral products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001 certified. Toronto 6285 Northam Drive, Suite 108 Mississauga, Ontario L4V 1X5, Canada Tel: 905-673-0699 Fax: 905-673-6509 All rights reserved. (c) 2000 Microchip Technology Incorporated. Printed in the USA. 11/00 Printed on recycled paper. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, except as maybe explicitly expressed herein, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies. DS11195A-page 32 Preliminary 2000 Microchip Technology Inc.