2000 Microchip Technology Inc. DS1119 5A-page 1
MCP41XXX/42XXX
FEATURES
• 256 taps for each potentiometer
• Potentiometer values for 10kΩ, 50kΩ and 100kΩ
• Single and dual versions
• SPI serial interface (mode 0,0 and 1,1)
• +/- 1 LSB max INL & DNL
• Low power CMO S technology
•1 µA maximum supply current in static operation
• Multiple devices can be daisy-chained together
(MCP42XXX only)
• Shutdown feature open circuits of all resistors for
maximum power savings
• Hardware shutdown pin available on MCP42XXX
only
• Single supply operation (2.7V - 5.5V)
• Industrial temperature range: -40°C to +85°C
DESCRIPTION
The MCP41XXX and MCP42XXX devices are 256
position digital potentiometers available in 10kΩ, 50kΩ,
and 100kΩ resistance versions. The MCP41XXX is a
single channel dev ice and is offered in an 8-pin PDIP
or SO IC package. Th e MCP42XXX contains two inde-
pendent channels in a 14-pin PDIP, SOIC, or TSSOP
package. The wiper position of the MCP41XXX/42XXX
varies linearly and is controlled via an industry-stan-
dard SPI interface. The devices consume <1µA during
static operation. A software shutdown feature is pro-
vided that disconnects the “A” terminal from the resistor
stack and simultaneously connects the wiper to the “B”
terminal. In addition, the dual MCP42XXX has a SHDN
pin that performs the sam e function in hardware. Dur-
ing the shutdown mo de, t he conte nts of the wiper reg-
ister can be changed and the potentiometer returns
from shutdown to th e new v alue. The wiper is res et to
the mid-scale position, 80h, upon power-up. The RS
(reset) pin implements a hardware reset and also
returns the wiper to mid-scale. The MCP42XXX SPI
interface includes both the SI and SO pins, allowing
daisy-chaining of multiple devices. Channel-to-channel
resistance matching on the MCP42XXX varies by less
than 1%. These devices operate from a single 2.7 -
5.5V supply and are specified over the extended indus-
trial temperature range of -40°C to +85°C.
PACKAGE TYPES
BLOCK DIAGRAM
MCP42XXX
1
2
3
411
12
13
14
8
9
10
5
6
7
PDIP/SOIC/TSSOP
PB1
PA1
PW1
SHDN
SO
RS
PW0
PB0
CS
PA0
SCK
SI
VSS
VDD
MCP41XXX
1
2
3
45
6
7
8
PDIP/SOIC
PB0
PA0
VDD
PW0
VSS
CS
SCK
SI
16-Bit
Shift
VDD
VSS
SI
SCK
RS SHDN
PB1
PA1
PW1
Resistor
Array 1*
Wiper
Register
PB0
PW0
PA0
Resistor
Array 0
Wiper
Register
Register
S0
Control
Logic
CS
NOTE: Potentiometer P1 is only available on the dual MCP 42X XX version.
Single/Dual Digital Potentiometer with SPI™ Interf ace
SPI is a trademark of Motorola Inc.
11195A.book Page 1 Tuesday, November 7, 2000 2:06 PM
MCP41XXX/42XXX
DS1119 5A-page 2 2000 Microchip Technology Inc.
1.0 ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS:10KΩ VERSION
All parameters apply across the speci-
fied operating ranges unless noted. Industrial (I): VDD = +2.7V to 5.5V TA = -40°C to +85°C (Note 8)
T y pical specifications represent values for VDD = 5V, VSS = 0V, VB = 0V, TA = +25°C
PARAMETER SYMBOL MIN. TYP. MAX. UNITS CONDITIONS
Rheostat M od e
Nominal Resistance R 8 10 12 kΩTA = +25°C (Note 1)
Rheostat Differenti al Non Linearity R-DNL -1 ±1/4 +1 LSB Note 2
Rheostat Integral Non Linearity R-INL -1 ±1/4 +1 LSB Note 2
Rheostat Tempco ∆RAB/∆T—800 —ppm/°C
Wiper Resistance RW—52 100 ΩVDD = 5.5 V, IW = 1 mA, code 00h
RW—73 125 ΩVDD = 2.7 V, IW = 1 mA, code 00h
Wiper Current IW-1 —+1 mA
Nominal Resistance Match ∆R/R —0.2 1 % MCP42010 only, P0 to P1;TA = 25°C
Potentio meter Divider
Resolution N 8 ——Bits
Monotonicity N 8 ——Bits
Differential Non Linearity DNL -1 ±1/4 +1 LSB Note 3
Integ r al N on Linearity INL -1 ±1/4 +1 LSB Note 3
V oltage Divider Tempco (Variation
between both halves of the voltage
divider) ∆VW/∆T—1—ppm/°C Code 80h
Full Scale Error VWFSE -2 -0.7 0 LSB Code FFh, VDD = 5V(Note 9)
VWFSE -2 -0.7 0 LSB Code FFh, VDD = 3V(Note 9)
Zero Scale Error VWZSE 0 +0.7 +2 LSB Cod e 00 h, VDD = 5V(Note 9)
VWZSE 0 +0.7 +2 LSB Cod e 00 h, VDD = 3V(Note 9)
Resisto r Terminals
Voltage Range VA,B,W 0—VDD Note 4
Capacitance (CA or CB)—15 —pF f =1MHz, C ode = 80h, see Figure 2-30 for test circuit
Capacitance (CW)—5.6 —pF f =1MHz, Code = 80h, see Figure 2-30 for test circuit
Dynamic Characteristics (Note 6)
Bandw i dth -3dB BW —1—MHz VB = 0V, Measured at Code 80h,
Output Load = 30PF
Settling Time tS—2—µS VA = VDD,VB = 0V, ±1% Error Band, Trans i tion from
Code 00h to C ode 80h, Output Load = 30pF
Resistor Noise Voltage eNWB —9—nV/√Hz VA = Open, Code 80h, f =1kHz
Crosstalk CT—-95 —dB VA = VDD, VB = 0V (Note 5)
Digital Inputs/Outputs (CS, SCK, SI, SO) Note 10
Schmitt Trigger High Level Input Voltage
(All digital input pins) VIH 0.7VDD ——V
Schmit t Trigger Low Level Input Voltage
(All digital input pins) VIL ——0.3VDD V
Hysteresis of Schm itt Tri gger Inputs VHYS —0.05VDD —
Low Level Output Voltage VOL ——0.40 V IOL = 2.1 mA,VDD = 5V
High Level Output Voltage VOH VDD - 0.5 ——VI
OH = -400µA, VDD = 5V
Input Leakage Current ILI -1 —1µACS = VDD, VIN = VSS or VDD,
inclu des VA while SHDN = 0
Pin Capacitance (All i nputs/out puts) CIN, COUT —10 —pF VDD = 5.0V, TA = +25°C, fc = 1 MHz
Power Requirements
Operating Voltage Range VDD 2.7 —5.5 V
Supply Current, Active IDDA —340 500 µAVDD = 5.5V, CS = VSS, fSCK = 10MHz,
SO = Open, C ode FFh (Note 7)
Supply Current, Static IDDS —0.01 1 µACS, SHDN, RS = VDD = 5.5V, SO = Open (Note 7)
Power Supply Sensitivity PSS —0.0015 0.0035 %/% VDD = 4.5V - 5.5V , VA = 4.5V, Code 80h
PSS —0.0015 0.0035 %/% VDD = 2.7V - 3.3 V, VA = 2.7V, Code 80h
Note 1: VAB = VDD, no connection on wiper.
2: Rheostat posit i on non lineari ty R-INL is the deviation from an ideal valu e measured between the maximum resistance and the minimum resistance
wiper pos iti ons . R-DN L meas u res t he rel ati ve st ep cha nge fr om the id eal b et ween suc ces sive tap posi tion s . I W = 50µA for VDD = 3V and I W = 4 00µA
for VDD = 5V for 10kΩ ve r si on. Se e F igu r e 2-2 6 fo r test c ircu i t.
3: INL and DNL are mea sure d at VW wi th the de vi ce conf igur ed in t he vol ta ge divi der or pote nt iome ter mode . VA = VDD and VB = 0V. DNL specification
limits of ±1 LSB max are specifie d monotonic operating condi tions. See Fi gure 2-25 for test circuit.
4: Resistor terminals A,B and W have no restrictions on polarity with respect to each othe r. Full scale and z ero scale error were measured using
Figure 2-25.
5: Measured at VW pi n where the vol tage on the adj acent VW pin is swinging fu ll scale.
6: All dynamic characteristics use VDD = 5V.
7: Supply c urrent is independent of curre nt through the potentiomete rs.
8: TSSOP devices are only specified at 25°C and 85°C.
9: See Figure 2-25 for test circuit.
10: See Figure 2-12 for RS and SHDN pin operation.
11195A.book Page 2 Tuesday, November 7, 2000 2:06 PM
2000 Microchip Technology Inc. DS1119 5A-page 3
MCP41XXX/42XXX
DC CHARACTERISTICS: 50KΩ VERSION
All parameters apply across the spe cified
oper ating ranges unl ess noted. Industrial (I): VDD = +2.7V to 5.5V TA = -40°C to +85°C (Note 8)
Typical specifications represe nt values for VDD = 5V, VSS = 0V, VB = 0V, TA = +25°C
PARAMETER SYMBOL MIN. TYP. MAX. UNITS CONDITIONS
Rheostat Mode
Nominal Resistance R 3 5 50 65 kΩTA = +25°C (Note 1)
Rheostat Differenti al Non Linearity R-DNL -1 ±1/4 +1 LSB Note 2
Rheostat Integral Non Linearity R-INL -1 ±1/4 +1 LSB Note 2
Rheostat Tempco ∆RAB/∆T—800 —ppm/°C
Wiper Resistance RW—125 175 ΩVDD = 5.5 V, IW = 1 mA, code 00h
RW—175 250 ΩVDD = 2.7 V, IW = 1 mA, code 00h
Wiper Current IW-1 —+1 mA
Nominal Resistance Match ∆R/R —0.2 1 % MCP42050 only, P0 to P1; TA = 25°C
Potentio meter Divider
Resolution N 8 ——Bits
Monotonicity N 8 ——Bits
Differen tial Non Linearity DNL -1 ± 1/4 +1 LSB VDD = 5V (Note 3)
Integ r al N on Linearity INL -1 ±1/4 +1 LSB Note 3
Voltage Divider Temp co (Variation be twe en
both halves of the voltage divider) ∆VW/∆T—1—ppm/°C Code 80h
Full Scale Error VWFSE -1 -0.25 0 LSB Code FFh, VDD = 5V (Note 9)
VWFSE -1 -0.35 0 LSB Code FFh, VDD = 3V (Note 9)
Zero Sc ale Error VWZSE 0 +0.25 +1 LSB Code 00h, VDD = 5V (Note 9)
VWZSE 0 + 0. 35 +1 LSB C o d e 00 h, VDD = 3V (Note 9)
Resisto r Terminals
Voltage Range VA,B,W 0—VDD Note 4
Capacitance (CA or CB)—11 —pF f =1MH z, Code = 80h, s ee Figure 2-30 for test cir-
cuit
Capacitance (CW)—5.6 —pF f =1MHz, Code = 80h, see Figure 2-30 fo r test ci r-
cuit
Dynamic Characteristics (Note 6)
Bandw i dth -3dB BW —280 —kHz VB = 0V, Measured at Code 80h,
Output Load = 30PF
Settling Time tS—8—µS VA = VDD, VB = 0V , ±1% Error Band, Transition from
Code 00h to Code 80h, Output Load = 30pF
Resistor Noise Voltage eNWB —20 —nV/√Hz VA = Open, Code 80h, f =1kHz
Crosstalk CT—-95 —dB VA = VDD, VB = 0V (Note 5)
Digital Inputs/Outputs (CS, SCK, SI, SO) Note 10
Schmitt Trigger High Level Input Voltage (All
digital input pins) VIH 0.7VDD ——V
Schmitt Trigger Low Level Input Voltage (All
digital input pins) VIL ——0.3VDD V
Hysteresis of Schm itt Tri gger Inputs VHYS —0.05VDD —
Low Level Output Voltage VOL ——0.40 V IOL = 2.1 mA, VDD = 5V
High Level Output Voltage VOH VDD - 0.5 ——VI
OH = -400µA, VDD = 5V
Input Leakage Current ILI -1 —1µACS = VDD, VIN = VSS or VDD,
inclu des VA while SHDN = 0
Pin Capacitance (All i nputs/out puts) CIN, COUT —10 —pF VDD = 5.0V , TA = +25°C, fc = 1 MHz
Power Requirements
Operating Voltage Range VDD 2.7 —5.5 V
Supply Current, Active IDDA —340 500 µAVDD = 5.5V, CS = VSS, fSCK = 10MHz,
SO = Open, C ode FFh (Note 7)
Supply Current, Static IDDS —0.01 1 µACS, SHDN, RS = VDD = 5.5V, S O = Open (Note 7)
Power Supply Sensitivity PSS —0.0015 0.0035 %/% VDD = 4.5V - 5.5V, VA = 4.5V, Code 80h
PSS —0.0015 0.0035 %/% VDD = 2.7V - 3.3V, VA = 2.7V, Code 80h
Note 1: VAB = VDD, no connection on wiper.
2: Rheostat posit i on non lineari ty R-INL is the deviation from an ideal valu e measured between the maximum resistance and the minimum resistance
wiper positions. R-DNL measures the relative ste p change from the ideal between successive tap posit i ons. IW = VDD/R for +3V or +5V for the 50kΩ
version. See Figure 2-26 for test circuit.
3: INL and DNL are meas ured at V W with the device configured in the voltage di vider o r potentiometer mode. VA = VDD and VB = 0V. DNL specification
limits of ±1 LSB max are specified monotonic operating conditions. See Figure 2-25 for te st circu it.
4: Resistor terminals A,B and W have no restrictions on polarity with res pect to each othe r. Full scale and zero scale error were measured using
Figure 2-25.
5: Measured at VW pi n w here the voltage on the adjacent VW pin is swinging full sca le.
6: All dynamic characteristics use VDD = 5V.
7: Supply c urrent is independent of curre nt through the potentiomete rs.
8: TSSOP de vices are only specifi ed at 25°C and 85°C.
9: See Figure 2-25 for test circuit.
10: See Figure 2-12 for RS and SHDN pin operation.
11195A.book Page 3 Tuesday, November 7, 2000 2:06 PM
MCP41XXX/42XXX
DS1119 5A-page 4 2000 Microchip Technology Inc.
DC CHARACTERISTICS OF 100KΩ VERSION
All parameters apply across the spe cified
oper ating ranges unl ess noted. Industrial (I): VDD = +2.7V to 5.5V TA = -40°C to +85°C (Note 8)
Typical specifications represe nt values for VDD = 5V, VSS = 0V, VB = 0V, TA = +25°C
PARAMETER SYMBOL MIN. TYP. MAX. UNITS CONDITIONS
Rheostat M od e
Nominal Resistance R 7 0 1 00 130 kΩTA = +25°C (Note 1)
Rheostat Differenti al Non Lineari ty R-DNL -1 ±1/4 +1 LSB Note 2
Rheostat Integral No n Li nearity R-INL -1 ±1/4 +1 LSB Note 2
Rheostat Tempco ∆RAB/∆T—800 —ppm/°C
Wiper Resistance RW—125 175 ΩVDD = 5. 5 V, IW = 1 mA, code 00h
RW—175 250 ΩVDD = 2. 7 V, IW = 1 mA, code 00h
Wiper Current IW-1 —+1 mA
Nominal Resistance Match ∆R/R —0.2 1 % MCP42100 only, P0 t o P1;TA = 25°C
Potentio meter Divider
Resolution N 8 ——Bits
Monotonicity N 8 ——Bits
Differential Non Linearity DNL -1 ±1/4 +1 LSB VDD = 5V (Note 3)
Integ r al N on Linearity INL -1 ±1/4 +1 LSB Note 3
V oltage Divider Tempco (Variation between
both halves of the voltage divider) ∆VW/∆T—1—ppm/°C Code 80 h
Full Scale Error VWFSE -1 -0.25 0 LSB Code FFh, VDD = 5V (Note 9)
VWFSE -1 -0.35 0 LSB Code FFh, VDD = 3V (Note 9)
Zero Scale Error VWZSE 0 +0.25 +1 LSB Code 00h, VDD = 5V (Note 9)
VWZSE 0 +0.35 +1 LSB Code 00h, VDD = 3V (Note 9)
Resisto r Terminals
Voltage Range VA,B,W 0—VDD Note 4
Capacitance (CA or CB)—11 —pF f =1MHz, Code = 80h, see Figure 2-30 for test cir-
cuit
Capacitance (CW)—5.6 —pF f =1MHz, Code = 80h, see Figure 2-30 for test cir-
cuit
Dynamic Characteristics (Note 6)
Bandw i dth -3dB BW —145 —kHz VB = 0V, Meas ured at Code 80h,
Output Load = 30PF
Settling Time tS—18 —µS VA = VDD,VB = 0V , ±1% Error Band, Transition from
Code 00h to Code 80h, Output Load = 30pF
Resistor Noise Voltage eNWB —29 —nV/√Hz VA = Open, Code 80h, f =1kHz
Crosstalk CT—-95 —dB VA = VDD, VB = 0V (Note 5)
Digital Inputs/Outputs (CS, SCK, SI, SO) Note 10
Schmitt Trigger High Level Input Voltage (All
digital input pins) VIH 0.7VDD ——V
Schmitt Trigger Low Level Input Voltage (All
digital input pins) VIL ——0.3VDD V
Hysteresis of Schm itt Tri gger Inputs VHYS —0.05VDD —
Low Level Output Voltage VOL ——0.40 V IOL = 2.1 mA,VDD = 5V
High Level Output Voltage VOH VDD - 0.5 ——VI
OH = -400µA, VDD = 5V
Input Leakage Current ILI -1 —1µACS = VDD, VIN = VSS or VDD,
includes VA while SHDN = 0
Pin Capacitance (All i nputs/out puts) CIN, COUT —10 —pF VDD = 5.0V, TA = +25°C, fc = 1 MHz
Power Requirements
Operating Voltage Range VDD 2.7 —5.5 V
Supply Current, Active IDDA —340 500 µAVDD = 5.5V, CS = VSS, fSCK = 10MHz,
SO = Open, Code FFh (Note 7)
Supply Current, Static IDDS —0.01 1 µA CS, SHDN, RS = VDD = 5.5V , SO = Open (Note 7)
Power Supply Sensitivity PSS —0.0015 0.0035 %/% VDD = 4.5V - 5.5V, VA = 4.5V Code 80h
PSS —0.0015 0.0035 %/% VDD = 2.7V - 3. 3V, VA = 2.7V Code 80h
Note 1: VAB = VDD, no connection on wiper.
2: Rheostat posit i on non lineari ty R-INL is the deviation from an ideal valu e measured between the maximum resistance and the minimum resistance
wiper pos i tions. R-DNL measures the r el ative step change from the ideal betwee n successive tap positions. IW = VDD/R for +3V or +5V for the
100kΩ v ersion. See Figure 2-26 fo r test ci rcuit.
3: INL and DNL are mea sure d at VW wi th the de vi ce conf igur ed in t he vol ta ge divi der or pote nt iome ter mode . VA = VDD and VB = 0V. DNL specification
limits of ±1 LSB max ar e specified monotonic operating conditions.See Figure 2-25 for test circuit.
4: Resistor terminals A,B and W have no restrictions on polarity with respect to each othe r. Full scale and zero scale erro r were measured usi ng
Figure 2-25.
5: Measured at VW pi n where the vol tage on the adj acent VW pin is swinging fu ll scale.
6: All dynamic characteristics use VDD = 5V.
7: Supply c urrent is independent of curre nt through the potentiomete rs.
8: TSSOP de vices are only specifi ed at 25°C and 85°C
9: See Figure 2-25 for test circuit.
10: See Figure 2-12 for RS and SHDN pin operation.
11195A.book Page 4 Tuesday, November 7, 2000 2:06 PM
2000 Microchip Technology Inc. DS1119 5A-page 5
MCP41XXX/42XXX
ELECTRICAL CHARACTERIS TIC S (CONTINUED)
Maximum Ratings*
VDD ........................................................................7.0V
All inputs and outputs w.r.t. VSS .......-0.6V to VDD +1.0V
Storage temperature..........................-60°C to +150°C
Ambient temp. with power applied.....-60°C to +125°C
ESD protection o n all pins ..................................... ≥ 2 kV
*Notice: Stresses above those listed under “maxim um ratin gs” m ay ca use p erman ent da mage to t he de vice. This i s a s tress rating
only and fu nctional operati on of the device at tho se or any other cond itions above those indicated in the ope rational listings of this
specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
AC TIMING CHARACTERISTICS
All parameters apply across the specified
operating ranges unless otherwise noted. Industrial (I): VDD = +2.7V to 5.5V TA = -40°C to +85°C
PARAMETER SYMBOL MIN. TYP. MAX. UNITS CONDITIONS
Clock Freque ncy FCLK ——10 MHz VDD = 5V (Note 1)
Clock High Time tHI 40 ——ns
Clock Low Time tLO 40 ——ns
CS Fall to First Rising CLK Edge tCSSR 40 ——ns
Data Input Setup Time tSU 40 ——ns
Data Input Hold Time tHD 10 ——ns
SCK Fall to SO Valid Propagation Delay tDO —80 ns CL = 30pF (Note 2)
SCK Rise to CS Ris e Hold Time tCHS 30 ——ns
SCK Rise to CS Fal l Delay tCS0 10 ——ns
CS Rise to CLK Rise Hold tCS1 100 ——ns
CS High Time tCSH 40 ——ns
Reset Pulse Width tRS 150 ——ns Note 2
RS Rising to CS Falling Delay Time tRSCS 150 ——ns Note 2
CS rising to RS or SHDN falling delay time tSE 40 ——ns Note 3
CS low time tCSL 100 ——ns Note 3
Shutdown Pulse Width tSH 150 ——ns Note 3
Note 1: When using the device in the daisy chain configuration, max. clock frequency is determined by a combination of prop-
agation delay time (tDO) and data input setup time (tSU). Max . c loc k f req uen cy i s t her ef ore ~ 5 .8M Hz b ase d on SCK ri se
and fall times of 5ns, tHI = 40ns, tDO = 80 ns and tSU = 40ns.
Note 2: Applies only to the MCP42XXX devices.
Note 3: Applies only when using hardware pins to exit software shutdown mode, MCP42XXX only.
11195A.book Page 5 Tuesday, November 7, 2000 2:06 PM
MCP41XXX/42XXX
DS1119 5A-page 6 2000 Microchip Technology Inc.
Figure 1-1: Detailed Serial interface Timing
Figure 1-2: Reset Timing
Figure 1-3: Software Shutdown Exit Timing
CS
SCK
SI msb in
tSU
tHD
tCSSR
tCSH
tHI tLO
tCSO
SO
tCS1
1/FCLK tCHS
tDO
(1ST 16 BITS OUT ARE ALWAYS ZEROS)
VOUT
±1%
±1% Error BandtS
RS
tS
VOUT
±1%
tRS
±1% Error Band
CS tRSCS
Code 80h is latched
on rising edge of RS
Wiper position is changed to
midscale (80h) if RS is held
low for 150ns
CS
tCSL
RS
SHDN
tSH
tRS
tSE
tSE
11195A.book Page 6 Tuesday, November 7, 2000 2:06 PM
2000 Microchip Technology Inc. DS1119 5A-page 7
MCP41XXX/42XXX
2.0 TYPICAL PERFORMANCE CURVES
Note: Unl ess ot he rwi s e ind i c at ed , cur ve re pr es en ts 10 k Ω, 50kΩ, and 100kΩ devic e s ,
VDD = 5V, VSS = 0V, TA = 25°C, VB = 0V.
Figure 2-1: Normalized Wiper to End Terminal
Resistance vs. Code
Figure 2-2: Potentiometer INL Error vs. Code
Figure 2-3: Potentiometer Mode Tempco vs. Code
Figure 2-4: Nominal Resistance 10kΩ vs.
Temperature
Figure 2-5: Nominal Resistance 50kΩ vs.
Temperature
Figure 2-6: Nominal Resistance 100kΩ vs.
Temperature
0
0.2
0.4
0.6
0.8
1
0 32 64 96 128 160 192 224 256
Code (Decimal)
Normalized Resistance (Ω)
RWB RWA
VDD = +3V to +5V
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0 32 64 96 128 160 192 224 256
Code (Decimal)
Potentiometer INL Error (LSB)
TA = -40°C to +85°C
Refer to Figure 2-25
-10
0
10
20
30
40
50
60
70
0 32 64 96 128 160 192 224 256
Code (Decimal)
Potentiometer Mode TempCo (ppm / °C)
TA = -40°C to +85°C
VA = 3V
0
2
4
6
8
10
12
-40-200 20406080
Temperature (°C)
Nominal Resistance (kΩ)
RAB
RWB
Code = 80h
MCP41010, MCP42010 (10kΩ potentiometers)
0
10
20
30
40
50
60
70
-40-200 20406080
Temperature (°C)
Nominal Resistance (kΩ)
RAB
RWB
Code = 80h
MCP41050, MCP4 2050 (50kΩ potentiometers)
0
20
40
60
80
100
120
140
-40-200 20406080
Temperature (°C)
Nominal Resistance (kΩ)
MCP41100, MCP42100 (100kΩ potentiometers)
RAB
RWB
Code = 80h
11195A.book Page 7 Tuesday, November 7, 2000 2:06 PM
MCP41XXX/42XXX
DS1119 5A-page 8 2000 Microchip Technology Inc.
Note: Unl ess ot he rwi s e ind i c at ed , cur ve re pr es en ts 10 k Ω, 50kΩ, and 100kΩ devic e s ,
VDD = 5V, VSS = 0V, TA = 25°C, VB = 0V.
Figure 2-7: Rheostat INL Error vs. Code
Figure 2-8: Rheostat Mode Tempco vs. Code
Figure 2-9: Static Current vs. Temperature
Figure 2-10: Active Supply Current vs.
Temperature
Figure 2-11: Active Supply Current vs. Clock
Frequency
Figure 2-12: Reset & Shutdown Pins Current vs.
Voltage
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0 32 64 96 128 160 192 224 256
Code (Decimal)
Rheostat IN L Error (LSB)
TA = +25°C
TA = +85°C
TA = -40°C
Refer t o Fi gure 2-27
0
500
1000
1500
2000
2500
3000
0 32 64 96 128 160 192 224 256
Code (Decimal)
Rheostat Mode TempCo (ppm / °C)
TA = -40°C to 85°C,
VA = no connect,
RWB measured
0
5
10
15
20
25
-40-200 20406080
Temperature (°C)
Static Current (nA)
30
40
50
60
70
80
90
-40-200 20406080
Temperature (°C)
Active Supply Current (µA)
VDD = 5V
VDD = 3V
FCLK = 3 MHz
Code = FFh
0
100
200
300
400
500
600
700
800
900
1000
Clock Freq uen cy (Hz)
Active Supply Current (mA)
A - VDD = 5.5V, Code = AAh
B - VDD = 3.3V, Code = AAh
C - VDD = 5.5V, Code = FFh
D - VDD = 3.3V, Code = FFh
A
B
C
D
1k 10k 100k 1M
1
10M
-7
-6
-5
-4
-3
-2
-1
0
1
0123456
RS & SHD N P in Voltage (V)
RS & SHDN Sink Current ( A)
VDD = 5.5V
11195A.book Page 8 Tuesday, November 7, 2000 2:06 PM
2000 Microchip Technology Inc. DS1119 5A-page 9
MCP41XXX/42XXX
Note: Unl ess ot he rwi s e ind i c at ed , cur ve re pr es en ts 10 k Ω, 50kΩ, and 100kΩ devic e s ,
VDD = 5V, VSS = 0V, TA = 25°C, VB = 0V.
Figure 2-13: 10kΩ Device Wiper Resistance
Histogram
Figure 2-14: 50kΩ, 100kΩ Device Wiper
Resistance Histogram
Figure 2-15: One Position Settling Time
Figure 2-16: Full Scale Settling Time
Figure 2-17: Digital Feedthrough vs. Time
Figure 2-18: Gain vs. Frequency for 10kΩ
Potentiometer
0
20
40
60
80
100
120
140
160
180
47 48 49 50 51 52 53 54 55 56 57 58 59
Wiper Resistance (Ω)
Number of Occurrences
MCP41010,MCP42010
Code = 00h,
Sample Size = 400
0
20
40
60
80
100
120
140
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
Wiper Resistance (Ω)
Number of Occurrences
MCP41050, MCP41100,
MCP42050, MCP42100
Code = 00h,
Sample Size = 796
VOUT Code = 7Fh Code = 80h
CS
CL = 17pF
VOUT
00h
FFh
CS
CL = 27pF
CL = 27pF
Code = 80h
VOUT
CS
-60
-54
-48
-42
-36
-30
-24
-18
-12
-6
0
6
Frequency (Hz)
Gain (dB)
CL = 30pF, Refer to Figure 2-29
MCP41010, MCP42010 (10kΩ potentiometers)
Code = FFh
Code = 80h
Code = 40h
Code = 20h
Code = 10h
Code = 08h
Code = 04h
Code = 02h
Code = 01h
100 1k 10k 100k 1M 10M
11195A.book Page 9 Tuesday, November 7, 2000 2:06 PM
MCP41XXX/42XXX
DS1119 5A-page 10 2000 Microchip Technology Inc.
Note: Unl ess ot he rwi s e ind i c at ed , cur ve re pr es en ts 10 k Ω, 50kΩ, and 100kΩ devic e s ,
VDD = 5V, VSS = 0V, TA = 25°C, VB = 0V.
Figure 2-19: Gain vs. Frequency for 50kΩ
Potentiometer
Figure 2-20: Gain vs. Frequency for 100kΩ
Potentiometer
Figure 2-21: -3 dB Bandwidths
Figure 2-22: Power Supply Rejection Ratio vs.
Frequency
Figure 2-23: 10kΩ Wiper Resistanc e vs. Voltage
Figure 2-24: 50kΩ & 100kΩ Wiper Resistance vs.
Voltage
-60
-54
-48
-42
-36
-30
-24
-18
-12
-6
0
6
Frequency (Hz)
Gain (dB)
CL = 30pF, Refer to Figure 2-29
MCP41050, MCP42050 (50kΩ potentiometers)
Code = FFh
Code = 80h
Code = 40h
Code = 20h
Code = 10h
Code = 08h
Code = 04h
Code = 02h
Code = 01h
100 1k 10k 100k 1M 10M
-60
-54
-48
-42
-36
-30
-24
-18
-12
-6
0
6
Frequency (Hz)
Gain (dB)
CL = 30pF, Refer to Figure 2-29
MCP41100, MCP4 2100 (100kΩ potentiometers)
Code = FFh
Code = 80h
Code = 40h
Code = 20h
Code = 10h
Code = 08h
Code = 04h
Code = 02h
Code = 01h
100 1k 10k 100k 1M
-36
-30
-24
-18
-12
-6
0
Frequency (Hz)
Gain (dB)
279kHz
145kHz 1.06MHz
10kΩ
50kΩ
100kΩ
CL = 30pF, Code = 80h
Refer to Figure 2-29
1k 10k 100k 1M 10M
0
5
10
15
20
25
30
35
40
Frequency (Hz)
PSRR (dB)
100kΩ Potentiometer
50kΩ Potentiometer
10kΩ Potentiometer VDD = 4.5V to 5.5V,
Code = 80h,
CL = 27pF,
VA = 4V
Refer to Figure 2-28
1k 10k 100k 1M 10M
0
100
200
300
400
500
600
700
012345
Terminal B Voltage (V)
Wiper Resistance (Ω)
MCP41010, MCP42010
Iw = 1mA, Code = 00h,
Refer to Figure 2-27
VDD = 2.7V
VDD = 5V
0
50
100
150
200
250
300
350
400
450
012345
Terminal B Voltage (V)
Wiper Resistance (Ω)
VDD = 2.7V
VDD = 5V
Code = 00h
Refer to Figure 2-27
11195A.book Page 10 Tuesday, November 7, 2000 2:06 PM
2000 Microchip Technology Inc. DS11195A-page 11
MCP41XXX/42XXX
2.1 Parametric Test Circuits
Figure 2-25: Potentiometer Divider Non-Linearity
Error Tes t Circuit (DNL, INL)
Figure 2-26: Resistor Position Non-Linearity Error
Test Circuit (Rheostat operation DNL, INL)
Figure 2-27: Wiper Resistance Test Circuit
Figure 2-28: Power Supply Sensitivity Test Circuit
(PSS, PSRR)
Figure 2-29: Gain vs. Frequency Test Circuit
Figure 2-30: Capacitance Test Circuit
V+ A
BW
VMEAS*
V+ = VDD
1LSB = V+/256
DUT
*Assume infinite input impedance
+
-
A
BW
DUT
IW
*Ass ume infinite input impedance
VMEAS*
No Connection
+
-
B
DUT W
+
-
ISW
RSW = 0.1 V
ISW
Code = 00h
0.1V
VSS = 0 TO VDD
A
V+ A
BW
DUT
VA
V+ = VDD ± 10%
PSRR (dB) = 20LOG ∆VMEAS)(
PSS (%/%) = ∆VDD
∆VMEAS
VDD
*Assume infinite input impedance
VMEAS*
∆VDD
+
-
VIN
-
+
+5V
VOUT
2.5V DC
OFFSET
GND
A
B
DUT
W
~
VIN
-
+
+5V
VOUT
MCP601
2.5V DC
OFFSET
AB
DUT
~
11195A.book Page 11 Tuesday, November 7, 2000 2:06 PM
MCP41XXX/42XXX
DS1119 5A-page 12 2000 Microchip Technology Inc.
3.0 PIN DESCRIPTIONS
PA0, PA1
Potentiometer Terminal A Connection.
PB0, PB1
Potentiometer Terminal B Connection.
PW0, PW1
Potentiometer Wiper Connection.
CS Chip Select
This is th e SPI po rt chip sel ect pin a nd i s used to ex e-
cute a new command after it has been loaded into the
shift register. This pin has a Schmitt Trigger input.
SCK Serial Clock
This is the SPI port clock pin and is used to clock in new
register data. Data is clocked into the SI pin on the ris-
ing edge of the clock and out the SO pin on the falling
edge of the c lock. This pin is gated to the CS pin, i.e.,
the device will not draw any more current if the SCK pin
is toggling when the CS pin is high. This pin has a
Schmitt Trigger input.
SI Serial Data Input
This is the SPI port serial data input pin. The command
and data bytes are clocked i nto the shift register using
this pin. This pin is gated to the CS pin, i.e., the device
will not draw any more current if the SI pin is toggling
when the CS pin is high. This pin has a Schmitt T rigger
input.
SO Serial Data Output
(MCP42XXX devices only)
This is the SPI port serial data output pin used for daisy
chaining mo re than one dev ice. Data is clocked out of
the SO pin on the falling edge of clock. This is a push-
pull output and does not go to a high impedance state
when CS is high. It will drive a logic low when CS is
high.
RS Reset (MCP42XXX devices only)
The Reset pin will set all potentiometers to mid-scale
(Code 80h) if this pin is bro ught low for at least 150ns.
This pin sh ould not be toggled low when the CS pin is
low. It is possible to toggle this pin when the SHDN pin
is low. In order to minimize power consumption, this pin
has an active pull-up circuit. The performance of this
circuit is shown in Figure 2-12. This pin will draw negli-
gible current at logic level 0 and logic level 1.
SHDN Shutdown
(MCP42XXX devices only)
The Shutdown pin has a Schmit Trigger input. Pulling
this pin low will put the dev ice in a power saving mode
where A terminal is opened and the B and W terminals
are connected for all potentiometers. This pin should
not be toggled low w hen the CS pi n is low. In order to
minimize power consumption, this pin has an active
pull-up circuit. The performance of this circuit is shown
in Figure 2-12. This pin will draw negligible current at
logic level 0 and logic level 1.
MCP41XXX PINS
PIN
#NAME FUNCTION
1CS
Chip Select
2 SCK Serial Clock
3 SI Serial Data Input
4V
SS Ground
5 PA0 Terminal A Connection For Pot 0
6 PW0 Wiper Connection For Pot 0
7 PB0 Terminal B Connection For Pot 0
8V
DD Power
MCP42XXX PINS
PIN
#NAME FUNCTION
1CS
Chip Select
2 SCK Serial Clock
3 SI Serial Data Input
4V
SS Ground
5 PB1 Terminal B Connection For Pot 1
6 PW1 Wiper Connection For Pot 1
7 PA1 Terminal A Connection For Pot 1
8 PA0 Terminal A Connection For Pot 0
9 PW0 Wiper Connection For Pot 0
10 PB0 Terminal B Connection For Pot 0
11 RS Reset Input
12 SHDN Shutdown Input
13 SO Data Out for Daisy Chaining
14 VDD Power
11195A.book Page 12 Tuesday, November 7, 2000 2:06 PM
2000 Microchip Technology Inc. DS11195A-page 13
MCP41XXX/42XXX
4.0 APPLICATIONS INFORMATION
The MCP41XXX/42XXX devices are 256 tap single
and dual digital potentiometers that can be used in
place of stand ard mechanical pots. Re sistance valu es
of 10kΩ, 50kΩ and 100kΩ are available. As shown in
Figure 4-1, each potentiometer is made up of a variable
resistor and an 8-bit (256 position) data register that
determines the wiper position. There is a nominal wiper
resistance of 52Ω for the 10kΩ version and 1 25Ω for
the 50kΩ and 100kΩ versions. For the dual devices,
the channel t o channe l matching variati on is less than
1%. The resistance between the wiper and either of the
resistor endpoints varies linearly according to the value
stored in the data register. Code 00h effectively con-
nects the wiper to the B terminal. At power up, all data
registers will automatically be loaded with the mid-
scale value, 80h. The serial interface provides the
means for loading data into the shift register which is
then transferre d to the data registers. The serial inter-
face also provides the means to place individual poten-
tiometers in the shutdown mode for maximum power
savings. The SHDN pin can also be used to put all
potentiometers in shutdown mode and the RS pin is
provided to set all potentiometers to mid-scale, 80h.
Figure 4-1: Block diagram showing the MC P42XXX d ual digital p otentiometer. Data register 0 a nd data register 1
are 8-bit registers allowing 256 tap positions for each wiper. Standard SPI pins are used with the addition of the
Shutdown (SHDN ) and Reset (RS) pins. As shown, res et affects th e data register and wipers, bringing them to mid-
scale. Shutdown disconnects the A terminal and connects the wiper to B, without changing the state of the data
registers.
When laying out the circuit for your digi tal potentiome-
ter, bypass capacitors s hould be used. Thes e capaci-
tors should be placed as close as possible to the device
pin. A bypass capacitor value of 0.1 µF is recom-
mended. Digit al and analog traces should be separated
as much as possible on the board, and no traces
should run underneath the device or the bypass capac-
itor. Extra precautions sho uld be taken to keep traces
with high frequency signals (such as clock lines) as far
as possible from analog traces. Use of an analog
ground plane is recommended in order to keep the
ground potential the same for all devices on the board.
RDAC1
SCK SO
SI
Decode
Logic
16 Bit Shift Register
PA0 PB0PW0
RDAC2
Data Register 1
PA1 PB1PW1
CS
RS
SHDN
D7 D0
Data Register 0
D7 D0
D7 D0
V
DD
A
B
W
V
DD
MCP4XXXX
µ
C
To Application
Circuit
0.1uF
0.1uF
Data Lines
11195A.book Page 13 Tuesday, November 7, 2000 2:06 PM
MCP41XXX/42XXX
DS1119 5A-page 14 2000 Microchip Technology Inc.
4.1 Modes of Operation
Digital potentiometer applications can be divided up
into two categories: rheostat mode and potentiometer
or voltage divider mode.
4.1.1 RHEOSTAT MODE
In the rheostat mode, the potentiometer is used as a
two terminal resistive element. The unused terminal
should be tied to the wiper as shown in Figure 4-2.
Note that reversing the polarity of the A and B terminals
will not affect operation.
Figure 4-2: Two terminal or rheostat configuration
for the digital potentiometer. Acting as a resistive
element in the circuit, resistance is controlled by
changing the wiper setting.
Using the device in this mode allows control of the total
resistance between the two nodes. The total measured
resistance would be the least at code 00h, where the
wiper is tied to the B terminal. The resistance at this
code is equal to the w iper res istance, typical ly 52Ω for
the 10kΩ devices (MCP4X010), 125Ω for the 50kΩ
(MCP4X050), and 100kΩ (MCP4X100) devices. For
the 10kΩ device, the LSB size would be 39.0625Ω
(assuming 10kΩ total resistance). The resistance
would then increase with this LSB size until the total
measured resistance at code FFh would be 9985.94Ω.
The wiper will nev er directly connect to the A terminal
of the resistor stack.
In the 00h state, th e total resistance is the w iper resis-
tance. To avoid damage to the internal wiper circuitry in
this configuration, care should be taken to insure the
current flow never exceeds 1mA.
For dual devices, the variation of channel-to-channel
matching of the total resistance from A to B is less than
1%. The de vice-to-device matching how ever can vary
up to 30%. In th e rheostat mode, the r esistance has a
positive tempe rature coefficient. The chang e in wiper-
to-end terminal resistance over temperature is shown
in Figure 2-8. The most variation ov er tempera ture will
occur in the first 6% of codes (code 00h to 0Fh) due to
the wiper resistance coefficient affecting the total resis-
tance. The remaining codes are dominated by the total
resistance tempco RAB, typically 800 ppm/°C.
4.1.2 POTENTIOMETER MODE
In the potentiometer mode, all three terminals of the
device are tied to different nodes in the circuit. This
allows the potentiometer to output a voltage propor-
tional to the input voltage. This mode is sometimes
called voltage divider mode. The potentiometer is used
to provide a variable voltage by adjusting the wiper
position between the two endpoints as shown in
Figure 4-3. Note that reversing the polarity of the A and
B terminals will not affect operation.
Figure 4-3: Three terminal or voltage divider mode
In this configuration, the ratio of the internal resistances
define the temperature coefficient of the device. The
resistor matching of the RWB resistor to the RAB res ist or
performs with a typical temperature coefficient of 1
ppm/°C (measured at code 80h). At lower codes, the
wiper resistance temperatur e coefficient will dominate.
Figure 2-3 shows the effect of the wiper. Above the
lower codes, this figure shows that 70% of the states
will typically have a temperature coeffi cient of less than
5 ppm/°C. 30% of the states will typically have a ppm/
°C of less than 1.
4.2 Typical Applications
4.2.1 P ROGRAMMABLE SINGLE ENDED
AMPLIFIERS
Potentiometers are often us ed to adjust system refer-
ence levels or gain. Programmable gain circ uits using
digital potentiometers can be realized in a number of
different ways. An example of a single supply inverting
gain amplifier is shown in Figure 4-4. Due to the high
input impedanc e of the amplifier, the w iper r esistance
is not included in the transfer function. For a single sup-
ply non-inverting gain configuration, the circuit in
Figure 4-5 can be used.
A
BW
MCP4XXXX RESISTOR
A
BW
MCP4XXXX
V1
V2
11195A.book Page 14 Tuesday, November 7, 2000 2:06 PM
2000 Microchip Technology Inc. DS11195A-page 15
MCP41XXX/42XXX
.
Figure 4-4: Single supply programmable inverting
gain amplifier using a digital potentiometer.
Figure 4-5: Single Supply Programmable Non-
inverting gain amplifier
In order for these circuits to work properly, care must
be taken in a few areas. For linear operation, the
analog input and output signals must be in the range of
Vss to VDD for the potentiometer and input and output
rails of the op-amp. T he circuit in Figure 4-4 requires a
virtual ground or reference input to the non-inverting
input of the amplifier. Refer to Application Note AN-
682, “Using Single Supply Operational Amplifiers in
Embedded Systems” for more detail. At power up or
reset (RS), the resistance is set to mid-scale and RA
and RB match. Based on the transfer function for the
circuit, the gain is -1 V/V. As the code is increased and
the wiper moves towards the A terminal and the gain
increases. Conversely, when the wiper is moved
towards the B terminal, the gain decreases. Figure 4-6
shows this relationship. Notice the pseudo-loga rithmic
gain around decimal code 128. As the wiper
approaches either terminal, the step size in the gain
calculation increases dramatically. Due to the
mismatched ratio of RA and R B at the extreme high and
low codes, small increments in wiper position can
dramatically affect the gain. As shown in Figure 4-3,
recommended gains lie between 0.1 and 10 V/V.
Figure 4-6: Gain vs. Code for inverting and
differential amplifier circuits.
4.2.2 PROGRAMMABLE DIFFERENTIAL
AMPLIFIER
An example of a differential input amplifier using digital
potentiometers is shown in Figure 4-7. For the transfer
function to hold, both pots must be programmed to the
same code. The resistor matching from channel-to-
channel within a dual device can be used as an advan-
tage in this circuit. This circuit will also show stable
operation over temperature due to the low potentiome-
ter temper ature coefficient. Figure 4-6 also shows the
relationship between gain and code f or this circuit. As
the wiper approaches either terminal, the step size in
the gain calculation increas es dramatically. This circuit
is recommended for gains between 0.1 and 10 V/V.
MCP606
V
IN
V
SS
-IN
+IN
V
OUT
B
A
W
MCP41010
RARAB 256 Dn
–()
256
------------------------------------------= RBRABDn
256
---------------------=
RAB = Total resistance of pot Dn = Wip e r Sett in g
Where:
VOUT V–IN RB
RA
--------
VREF 1RB
RA
--------+
+=
For Dn = 0 to 255
V
REF
+
-
V
DD
MCP606
VIN
VSS
VDD
+IN
-IN
VOUT
RB
RA
W
MCP41010
VOUT VIN 1RB
RA
--------+
=
RARAB 256 Dn
–()
256
------------------------------------------= RBRABDn
256
---------------------=
RAB = Total resistance of pot Dn = Wiper Setting
Where:
For Dn = 0 to 255
+
-
0.1
1
10
0 64 128 192 256
Decimal code (0-255)
Absolute Gain (V/V)
11195A.book Page 15 Tuesday, November 7, 2000 2:06 PM
MCP41XXX/42XXX
DS1119 5A-page 16 2000 Microchip Technology Inc.
Figure 4-7: Single Supply programmable
differential ampl ifier using digital potentiometer s.
4.2.3 PROGRAMMABLE OFFSET TRIM
For applications requiring only a programmable voltage
reference, the circuit in Figure 4-8 can be used. This
circuit shows the device used in the potentiometer
mode along with two resistors and a buffered output.
This creates a circuit with a linear relationship between
voltage out and programmed code. Resistors R1 and
R2 can be used to increase or decrease the output volt-
age step size. The potentiometer in this mode is stable
over temperature. The operation of this circuit over
temperature is show n in Figure 2-3. The wo rst perfor-
mance over temperatur e will occur at the lower codes
due to the dominating wiper resistance. R1 and R2 can
also be used to affect the boundary voltages thereby
eliminating the us e of these lower codes.
Figure 4-8: By chan ging the va lues of R1 and R2,
the voltage output resolution of this programmable
voltage reference circuit is affected.
4.3 Calculating Resistances
When programm ing the digital potentiometer settings,
the following equations can be used to calculate the
resistances. Programming code 0 0h effectively brin gs
the wiper to the B terminal, leaving only the wiper resis-
tance. Programming higher codes will bring the wiper
closer to the A terminal of the potentiometer . The equa-
tions in Figure 4-9 can be used to calculate the terminal
resistances. F igure 4-10 sho ws an example calcula-
tion using a 10kΩ potentiometer.
Figure 4-9: Potentiometer resistances are a
function of code. It should be noted that when using
these equations for most feedback amplifier circuits
(see Figure 4-4 and Figure 4-5), the wiper resistance
can be omitted due to the h igh impedance i nput of the
amplifier.
Figure 4-10: Example Resistance calculations.
MCP601
VB
VSS
VDD
-IN
+IN
Vout
VA
AB
A
B
(SIG -)
(SIG +)
MCP42010
VOUT VAVB
–()
RB
RA
-------=
MCP42010
1/2
1/2
VREF
NOTE: Potentiometer values must be equal
+
-
RARAB 256 Dn
–()
256
------------------------------------------= RBRABDn
256
---------------------=
RAB = Total resistance of pot Dn = Wiper Setting
Where:
For Dn = 0 to 255
MCP606 OUT
VSS
VDD
-IN
+IN
VDD
VSS
R1
R2
B
A
MCP41010
0.1 uF
+
-
PA
PB
PW
RWA(Dn) = (RAB)(256 - Dn)
256 + RW
Where:
PA is A terminal
PB is B terminal
PW is Wiper Terminal
RWA is resi s tance betw ee n Term ina l A an d wipe r
RWB is resistance between Terminal B and Wiper
RAB is overall resistance for pot (10k,50k or 100k)
RW is wiper resistance
Dn is 8-bit val ue in da ta regi s ter for po t num b er n
(RAB)(Dn)
256 + RW
RWB(Dn) =
PA
PB
PW
RWA(C0h) = (10kΩ)(256-192)
256 + 52Ω
(10kΩ)(192)
256 + 52Ω
RWB(C0h) =
EXAMPLE:
Code = C0h = 192d
R = 10kΩ
RWA(Dn) = (RAB)(256 - Dn)
256 + RW
RWA(C0h) = 2552Ω
(RAB)(Dn)
256 + RW
RWB(Dn) =
RWB(C0h) = 7552Ω
10kΩ
Note: All values shown are typical and
actual results will vary.
11195A.book Page 16 Tuesday, November 7, 2000 2:06 PM
2000 Microchip Technology Inc. DS11195A-page 17
MCP41XXX/42XXX
5.0 SERIAL INTERFACE
Communications from the controller to the
MCP41XXX/42XXX digital potentiometers is done
using the SPI serial interface. This interface allows
three commands:
1. Write a new v alue to the potentiometer data reg-
ister(s).
2. Cause a channel to enter low power shutdown
mode.
3. NOP (No Operation) command.
Executing any command is done by setting CS low,
and then clocking in a command byte followed by a
data byte into the 16-bit shift register. The command is
executed when CS is raised . Data is clocked i n o n the
rising edge of clock and out the SO pin on the falling
edge of the clock. See Figure 5-1. The device will track
the number of clocks (rising edges) while CS is low and
will abort all commands if the number of clocks is not a
multiple of 16.
5.1 Command Byte
The first byte sent is always the command byte, fol-
lowed by the data byte. The command byte contains
two command select bits and two potentiometer select
bits. Unused bits are don’t care bits. The command
select bits are summarized in Figure 5-2. The com-
mand select bits C1 and C 0 (bits 4:5) of th e command
byte determine which command will be executed. If the
command bits are both 0’s or 1’s, then a NOP com-
mand will be executed after all 16 bits have been
loaded. This command is useful when using the daisy-
chain configurat ion. When the co mmand bits are 0,1 a
write command wil l be executed with the 8 bits sent in
the data byte. The data will be written to the potentiom-
eter(s) determined by the potentiometer select bits. If
the command bits are 1,0 then a s hutdown command
will be executed on the potentiome ters determined by
the potentiometer select bits.
For the MCP42XXX devices, the potentiometer select
bits P1 and P0 (bits 0:1) deter mine which pote ntiome-
ters are to be acted upon by the command. A corre-
sponding one in the position signifies that the
command for that potentiome ter will get execute d and
a zero signifies that the command will not effect that
potentiometer. See Figure 5-2.
5.2 Writing Data Into Data Registers
When new data is written into one or more of the poten-
tiometer data regis ters, the write c omm and is followed
by the data byte for the new value. The command
select bits C1, C0 are set to 0,1. The potentiometer
selection bits P1 and P0 allow new values to be written
to potentiome ter 0, potentiome ter 1 or both with a sin-
gle command. A o ne for either P1 or P0 wi ll cause the
data to be written to the res pective da ta register and a
zero for P1 or P0 will cause no change. See Figure 5-2
for the command format summary.
5.3 Using The Shutdown Command
The shutdown command allows the user to put the
application circuit into a power saving mode. In this
mode, the A terminal is open circuited and the B and W
terminals are shorted together. The command select
bits C1, C0 are set to 1,0. The potentiometer selection
bits P1 and P0 allow each potentiometer to be shut-
down independently. If either P1 or P0 are high, the
respective potentiometer will enter shutdown mode. A
zero for P1 or P0 will have no effect. The eight data bits
following the command byte still need to be transmitted
for the shutdown command but they are don’t care bits.
Se e Fi gu r e 5-2 for com ma n d fo rmat sum ma ry. Once a
particular potentiometer has entered the shutdown
mode, it will remain in this mode until:
•A new value is written to the potentiometer data
register, provided that the SHDN pin is high. The
device will remain in the shutdown mode until the
rising edge of the CS is detected, at which time
the device will come out of shutdown mode and
the new value will be written to the da ta regis-
ter(s). If the SHDN pin is low when the new value
is received, the registers will still be set to the new
value, but the device will remain in shutdown
mode. This scenario assumes that a valid com-
mand was received. If an invalid command was
received, the command will be ignored and the
device will remain in the shutdown mode.
It is also possible to use the hardware shutdown pin
and reset pin to remove a device from software shut-
down. To do this, a low pulse on the chip select line
must first be sent. For multiple devices, sharing a single
SHDN or RESET line, allows you to pick an individual
device on that chain to remove from software shutdown
mode. See Figure 1-3 for timing. With a preceding chip
select pulse, either of these situations will also remove
a device from software shutdown:
•A falling edge is seen on the RS pin and held low
for at least 150ns, provided that the SHDN pin is
high. If the SHDN pin is low, the registers will still
be set to mid-scale but the device will remain in
shutdown mode. This condition assumes that CS
is high, as bringing the RS pin low while CS is low
is an invalid state and results are indeterminate.
11195A.book Page 17 Tuesday, November 7, 2000 2:06 PM
MCP41XXX/42XXX
DS1119 5A-page 18 2000 Microchip Technology Inc.
•A rising edge on the SHDN pin is seen after being
low for at least 100ns, provided that the CS pin is
high. Toggling the SHDN pin low while CS is low
is an invalid state and results are indeterminate.
•The dev ice is powered down and back up.
Figure 5-1: Timing Diagram for Writing Instructions or Data to a Digital Potentiometer
Figure 5-2: Command Byte Format
Note: The hardware SHDN pin will always put
the device in shutdown regardless of
whether a potentiometer has already been
put in the shutdown mode using the soft-
ware command.
SO‡
SI
SCK
CS†
23456789101
New Register Data
D7 D6 D5 D4 D3 D2 D1 D0
P1* P0
11 12 13 14 15 16
XC1 C0 XX
X
Channel
Select
Bits
Data Registers are
loaded on ris i ng
edge of CS. Shift
First 16 bits S hi fted out will always be zeros
Don’t
Care
Bits
Command
Bits
Don’t
Care
Bits
† There must always be multi ples of 16 clocks while CS is low or commands will abor t
‡ The serial data out pin (SO) is only available on the MCP42XXX device
* P1 is a don’t care bit for the MCP41 XX X
COMMAND BYTE DATA BYTE
X
register is loaded
with zeros a t this time
Data is always latched in
on the rising edge of SCK Data is always clocked out the SO
pin after th e fall ing edge of SCK
SO pin will always
drive low when CS
goes high
P1* P0 Potentiometer Selections
0 0 Dummy Co de : Nei ther Pote ntiomete r affecte d
0 1 Command executed on Po tentiometer 0
1 0 Command executed on Po tentiometer 1
1 1 Command executed on b oth Potentiometers
*PI is a don’t care bit for the MCP41XXX
P0P1*
XXXXC1C0
COMM AND BYTE
C1 C0 Command Command Summary
0 0 None No Command will be executed
0 1 Write Data Write the data contained in Data Byte to the potenti-
ometer(s) determined by the potentiometer sel ec-
tion bits
1 0 Shutdown Potentiometer(s) determined by potentiometer
selection bits will enter Shutdown Mode. Data bits
for this command are don’t cares
1 1 None No Command will be executed
Command
Selection
Bits
Potentiometer
Selection
Bits
11195A.book Page 18 Tuesday, November 7, 2000 2:06 PM
2000 Microchip Technology Inc. DS11195A-page 19
MCP41XXX/42XXX
5.4 Daisy-Chain Configuration
Multiple MCP42XXX devices can be connected in a
daisy-chain configuration as shown in Figure 5-4, by
connecting the SO pin from one device to the SI pin on
the next device. The data on the SO pin is the output of
the 16-bit shift register. The daisy-chain configuration
allows the system d esigner to communicate wi th sev-
eral devices without using a separate CS li ne for ea ch
device. The example shows a daisy chain configuration
with three devices, although any number of devices
(with or without the same resistor values ) can be con-
figured this way. While it is not possible to use a
MCP41XXX at the beginning or middle of a daisy-chain
because it does not provide the serial data out (SO)
pin, it is possible to use the device at the end of a chain.
As shown in the timing diagram in Figure 5-3, data will
be clocked o ut of the SO pi n on the falling edge o f the
clock. The SO pin has a CMOS push-pull output and
will drive low w hen CS goes high. SO w ill not go to a
high impedance state when CS is held high.
When using the daisy-chain configuration, the maxi-
mum clock speed possible is reduced to ~5.8MHz
because of the propagation delay of the data coming
out of the SO pin.
When using the daisy-chain configuration, keep in mind
that the shift register of each device is automatically
loaded with zeros whenever a command is executed
(CS = high). Because of this, the first 16 bits that come
out of the SO pin after the CS line goes low will always
be zeros. This means that when the first command is
being loaded into a device, it will always shift a NOP
command into the next device on the chain because
the command bits (and all the othe r bits) wil l be zeros.
This feature makes it necessary only to send command
and data bytes to the device farthest down the chain
that needs a new command. For example, if there were
three devices on the chain and it was desired to send a
command to the de vice in the mid dle, only 32 bytes of
data need to be transmitted. The last device on the
chain will have a NOP loaded from the previous device
so no registers will be affected when the CS pin is
raised to execute the command. The user must
always ensure that multiples of 16 clocks are
always provided (while CS is low) as all commands
will abort if the n umbe r of clocks provided is not a
multiple of 16.
Figure 5-3: Timing Diagram for Daisy-Chain Configuration
SO
SI
SCK
CS
Data Regis ters for all
devices ar e Loaded
on Rising Edge of CS
23456789101
DPP
1112131415 16
X C XXX
First 16 bits shi fted out
C DDDDDDD
will always be zeros
23456789101
DPP
1112 131415 16
X C XXX
Command and Data for Device 3
C DDDDDDD
star t shifting out after t he first 16 clocks
DPPXCXXX C DDDDDDD
23456789101
DPP
1112 131415 16
X C XXXC DDDDDDD
DPPXCXXX C DDDDDDD
Command By te
for Dev ice 3 Data Byte
for Device 1
Command Byte
for Device 1
Command Byte
for Device 2 Data Byte
for Device 2
Data Byte
for De vice 3
Command and Data for Device 2
start shifting out after the first 32 clocks
† There must always be multiples of 16 clocks while CS is low or commands will abort
‡ The serial data out pin (SO) is only available on the MCP42XXX device
11195A.book Page 19 Tuesday, November 7, 2000 2:06 PM
MCP41XXX/42XXX
DS1119 5A-page 20 2000 Microchip Technology Inc.
Figure 5-4: Daisy-Chain Configuration
Microcontroller
SO
CS
SCK
SI
SO
CS
SCK
SI
CS
SCK
SI
CS
SCK
SO
Device 1
Device 2
Device 3*
If you want to load the following
command/data into each part
in the chain.
Device 1
XX10XX11 11001100 Device 2
XX01XX10 11110000 Device 3
XX10XX00 10101010
EXAMPLE:
Start by setting CS low and
clocking in the command and
data that will end up in Device
3 (16 clocks).
1
Device 1
XX10XX00 10101010 Device 2
00000000 00000000 Device 3
00000000 00000000
After 16 cloc ks, Device 2 and
Device 3 will both have all
zeros clocked in from the
previous part’s shift register.
Clock-In the command and
data for Device 2 (16 more
clocks). The data that was pre-
viously loaded gets shifted to
the next device on the chain.
2
Device 1
XX01XX10 11110000 Device 2
XX10XX 00 101 010 10 Device 3
00000000 00000000
After 32 cloc k s, D evice 2 has
the data previously loaded
into Device 1 and Device 3
gets 16 more zeros.
Clock-In the data for Device 1
(16 more clocks). The data that
was previously loaded into
Device 1 gets shifted into
Device 2 and Device 3 contains
the first byte loaded. Raise the
CS line to execute the com-
mands for all 3 devices at the
same time.
3
Device 1
XX10XX11 11001100 Device 2
XX01XX 10 11110000 Device 3
XX10XX00 10101010
After 48 clocks, all 3 devices
have the proper command/
data loaded into their shift
registers.
*Note: Last device on a daisy chain may be a single channel MCP41XXX device.
11195A.book Page 20 Tuesday, November 7, 2000 2:06 PM
2000 Microchip Technology Inc. DS11195A-page 21
MCP41XXX/42XXX
5.5 Reset (RS) Pin Operation
The Reset pin (RS) will automatically set all potentiom-
eter data latches to mi d scale (Code 80h) when pulled
low (provided that the pin is held low at least 150ns and
CS is high). The reset will execute regardless of the
position of the SCK, SHDN and SI pins. It is possible to
toggle RS low and back high while SHDN is low . In this
case, the potentiometer registers will reset to mid-scale
but the potentiometer will remain in shutdown mode
until the SHDN pin is raised.
5.6 Shutdown (SHDN) Pin Operation
When held low, the shutdown pin causes the a pplica-
tion circuit to go into a power saving mode by open cir-
cuiting the A terminal and shorting the B and W
terminals for all potentiometers. Data register contents
are not affected by entering shutdown mode, i.e., when
the SHDN pi n is raised, the data register contents are
the same as before the shutdown mode was entered.
While in shutdown mode, it is still poss ible to clock in
new values for the data registers as well as togging the
RS pin to cause all data registers to go to mid-scale.
The new values wi ll take affect when th e SHDN pin is
raised.
If the device is powered up with the SHDN pin held low,
it will power up in the shutdown mode with the data reg-
isters set to mid-scale.
5.7 Power-up Considerations
When the devi ce is pow ered on, the dat a regis ters wi ll
be set to mid-scale (80h). A power-on reset circuit is
utilized to insure that the device powers up in this
known state.
Note: Bringing the RS pin low while the CS pin is
low constitutes an invalid operating state
and will result in indeterminate results
when RS and/or CS are brought high.
Note: Bringing the SHDN pin low while the CS
pin is low constitutes an invalid operating
state and will result in indeterminate
results when SHDN and/or CS are brought
high.
Table 5-1 Truth Table for Logic Inputs
SCK CS RS SHDN Action
X↓H H Communication is initiated with
device. Device comes out of
standby mode.
L L H H No action, device is waiting for
data to be clocked into shift reg-
ister or CS to go high to exe-
cute command.
↑L H X Shift one bit into shift register.
The shift register can be loaded
while the SHDN pin is low.
↓L H X Shift one bit out of shift register
on the SO pin. The SO pin is
active while the SH DN pin is
low.
X↑H H Based on command bits, either
load data from shift register into
data latches or execute shut-
down command. Neither com-
mand executed unless
multiples of 16 clocks have
been entered while CS is low.
SO pin goes to a logic low.
X H H H Static Operation
XH↓H All data registers set and
latched to code 80h.
XH↓L All data registers set and
latched to code 80h. Device is
in hardware shu tdown mode
and will remain in this mode.
XHH ↓All potentiometers put into hard-
ware shutdown mode; terminal
A is open and W is shorted to B
XHH ↑All potentiometers exit hard-
ware shutdown mode. Potenti-
ometers will also exit softwar e
shutdown mode if this rising
edge occurs after a low pulse
on CS. Content s of da ta l atche s
are restored.
11195A.book Page 21 Tuesday, November 7, 2000 2:06 PM
MCP41XXX/42XXX
DS1119 5A-page 22 2000 Microchip Technology Inc.
5.8 Using the MCP41XXX/42XXX in SPI
Mode 1,1
It is possible to operate the dev ices in SPI modes 0,0
and 1,1. The only difference between these two modes
is that when using mode 1,1 the clock idles in the high
state and in mode 0,0 the clock idles in the low state. In
both modes, data is clocked into the devices on the ris-
ing edge of SCK and data is clocked out the SO pin
after the falling edge of SCK. Operations using mode
0,0 are shown in Figure 5-1. The example in
Figure 5-5 shows mode 1,1.
Figure 5-5: Timing Diagram for SPI Mode 1,1 Operation
SO‡
SI
SCK
CS†
23456789101
New Reg i ster Data
D7 D6 D5 D4 D3 D2 D1 D0
P1* P0
11 12 13 14 15 16
XC1 C0 XX
X
Channel
Select
Bits
Data Regi st ers are
loaded on rising
edge of CS. Shift
First 16 bits S hi fted out will always be zeros
Don’t
Care
Bits
Command
Bits
Don’t
Care
Bits
† There must always be multi ples of 16 clocks while CS is low or commands will abor t
‡ The serial data out pin (SO) is only available on the MCP42XXX device
COMMAND BYTE DATA BYTE
X
register i s loaded
with zeros at this time
Data is always latched in
on the rising edge of SCK Data is always clocked out the SO
pin after th e fall ing edge of SCK
SO pin will always
drive low when CS
goes high
11195A.book Page 22 Tuesday, November 7, 2000 2:06 PM
2000 Microchip Technology Inc. DS11195A-page 23
MCP41XXX/42XXX
6.0 PACKAGING INFORMATION
6.1 Package Marking Information
XXXXXXXX
XXXXXNNN
YYWW
8-Lead PDIP (300 mil) Example
MCP41XXX
XXXXXNNN
0025
8-Lead SOIC (150 mil) Example
Legend: XX...X Customer specific information*
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
*Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask
rev#, and as sembly code. For OTP marking beyond this, certain pr ice adders apply. Please check with
your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.
XXXXXXX
XXXYYWW
NNN
MCP41XXX
XXX0025
NNN
14-Lead PDIP (300 mil) Example
14-Lead TSSOP Example
14-Lead SOIC (150 mil) Example
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
YYWWNNN
MCP42XXX
XXXXXXXXXXXXXX
0025NNN
XXXXXXXXXX
YYWWNNN
MCP42XXX
0025NNN
XXXXXX
YYWW
NNN
XXXXXX
YYWW
NNN
11195A.book Page 23 Tuesday, November 7, 2000 2:06 PM
MCP41XXX/42XXX
DS1119 5A-page 24 2000 Microchip Technology Inc.
8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
B1
B
A1
A
L
A2
p
α
E
eB
β
c
E1
n
D
1
2
Units INCHES* MILLIMETERS
Dime nsion Limits MIN NOM MAX MIN NOM MAX
Number of Pins n88
Pitch p.100 2.54
Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32
Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68
Base to Seating Plane A1 .015 0.38
Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26
Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60
Overall Length D .360 .373 .385 9.14 9.46 9.78
Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43
Lead Thickness c.008 .012 .015 0.20 0.29 0.38
Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78
Lower Lead Width B .014 .018 .022 0.36 0.46 0.56
Overall Row Spacing §eB .310 .370 .430 7.87 9.40 10.92
Mold Dra ft An gl e Top α5 10 15 5 10 15
Mold Dra ft An gl e Bottom β5 10 15 5 10 15
* Co ntrolling Parameter
Notes:
Dim ensions D and E1 do not include mold flash or protrusions. Mold flas h or protrusions shall not exceed
JEDEC Equivalent: MS-001
Drawing No. C04-018
.010” (0.254mm) per side.
§ Significant Characteristic
11195A.book Page 24 Tuesday, November 7, 2000 2:06 PM
2000 Microchip Technology Inc. DS11195A-page 25
MCP41XXX/42XXX
8-Lead Plastic Small Outline (SN) –Narrow, 150 mil (SOIC)
Foot Angle φ048048
1512015120
β
Mold Draft Angle Bottom 1512015120
α
Mold Draft Angle Top 0.510.420.33.020.017.013BLead Width 0.250.230.20.010.009.008
c
Lead Thickness
0.760.620.48.030.025.019LFoot Length 0.510.380.25.020.015.010hChamfer Distance 5.004.904.80.197.193.189DOve ral l Le ng th 3.993.913.71.157.154.146
E1
Molded Package Width 6.206.025.79.244.237.228EOverall Width 0.250.180.10.010.007.004A1Standoff §1.551.421.32.061.056.052A2Molded Package Thickness 1.751.551.35.069.061.053AOveral l He ight 1.27.050
p
Pitch 88
n
Number of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units
2
1
D
n
p
B
E
E1
h
L
β
c
45°
φ
A2
α
A
A1
* Co ntrolling Parameter
Notes:
Dim e nsions D and E1 do not i nclude mold flash or protrusions. Mold flash or protrusions s hall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-057
§ Significant Characteristic
11195A.book Page 25 Tuesday, November 7, 2000 2:06 PM
MCP41XXX/42XXX
DS1119 5A-page 26 2000 Microchip Technology Inc.
14-Lead Plastic Dual In-line (P) –300 mil (PDIP)
E1
n
D
1
2
eB
β
E
c
A
A1
B
B1
L
A2
p
α
Units INCHES* MILLIMETERS
Dimension Limits MIN NOM MAX MIN NOM MAX
Numbe r of Pins n14 14
Pitch p.100 2.54
To p to S ea ti ng Plane A .14 0 .1 55 .1 70 3.56 3.94 4.32
Molded Package T hickness A2 .115 .130 .145 2.92 3.30 3.68
Base to S eating Plane A1 .015 0.38
Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26
Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60
Overall Length D .740 .750 .760 18.80 19.05 19.30
Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43
Lead Thickness c.008 .012 .015 0.20 0.29 0.38
Upp er Le ad Wi dt h B1 . 04 5 .0 5 8 .0 70 1.1 4 1.46 1.7 8
Lower Lead Width B .014 .018 .022 0.36 0.46 0.56
Overall Row Spacing §eB .310 .370 .430 7.87 9.40 10.92
Mold Draft Angle Top α51015 51015
β51015 51015
Mold Draft Angle Bottom
* Controlling Parameter
Notes:
Dime nsions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS -001
Drawing No. C04-005
§ Significant Characteristic
11195A.book Page 26 Tuesday, November 7, 2000 2:06 PM
2000 Microchip Technology Inc. DS11195A-page 27
MCP41XXX/42XXX
14-Lead Plastic Small Outline (SL) –Narrow, 150 mil (SOIC)
Foot Angle φ048048
1512015120
β
Mold Draft Angle Bottom 1512015120
α
Mold Draft Angle Top 0.510.420.36.020.017.014BLead Width 0.250.230.20.010.009.008
c
Lead Thickness
1.270.840.41.050.033.016LFoot Length 0.510.380.25.020.015.010hChamfer Distance 8.818.698.56.347.342.337DOverall Length 3.993.903.81.157.154.150
E1
Molde d Package Width 6.205.995.79.244.236.228EOverall Width 0.250.180.10.010.007.004A1Standoff §1.551.421.32.061.056.052A2Molded Package Thickness 1.751.551.35.069.061.053AOverall Height 1.27.050
p
Pitch 1414
n
Numbe r of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units
2
1
D
p
n
B
E
E1
h
L
c
β
45°
φ
α
A2
A
A1
* Controlling Parameter
Notes:
Dime nsions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C 04-065
§ Significant Characteristic
11195A.book Page 27 Tuesday, November 7, 2000 2:06 PM
MCP41XXX/42XXX
DS1119 5A-page 28 2000 Microchip Technology Inc.
14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)
840840
φ
Foot Angle
10501050
β
Mold Draft Angle Bottom 10501050
α
Mold Draft Angle Top 0.300.250.19.012.010.007B1Lead Width 0.200.150.09.008.006.004
c
Lead Thickness
0.700.600.50.028.024.020LFoot Length 5.105.004.90.201.197.193DMolded Package Length 4.504.404.30.177.173.169E1Molded Package Width 6.506.386.25.256.251.246EOverall Width 0.150.100.05.006.004.002A1Standoff §0.950.900.85.037.035.033A2Molded Package Thickness 1.10.043AOverall Height 0.65.026
p
Pitch 1414
n
Numbe r of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERS*INCHESUnits
L
β
c
φ
2
1
D
n
B
p
E1
E
α
A2A1
A
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.005” (0.1 27 m m) pe r sid e .
JEDE C Equivalent: M O-153
Drawing No. C04-087
§ Significant Characteristic
11195A.book Page 28 Tuesday, November 7, 2000 2:06 PM
2000 Microchip Technology Inc. DS11195A-page 29
MCP41XXX/42XXX
ON-LINE SUPPORT
Microchip provides on-line support on the Microchip
World Wide Web (WWW) site.
The web site is used by Microchip as a means to make
files and information easily availabl e to custome rs. To
view the site, the user must have access to the Internet
and a web browser, such as Netscape or Microsoft
Explorer. Files are also available for FTP download
from our FTP site.
Connecting to the Microchip Internet Web Site
The Microchip web site is available by using your
favorite Internet browser to attach to:
www.microchip.com
The file transfer site is available by using an FTP ser-
vice to connect to:
ftp://ftp.microchip.com
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
User’s Guides, Articles and Sample Programs. A vari-
ety of Microchip specific business information is also
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available for consideration is:
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technical informati on and more
•Listing of seminars and events
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The Systems Information and Upgrade Line provides
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Plus, this line provi des information on how customer s
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Hot Line N umbers are:
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1-480-792-7302 for the rest of the wor ld. 000815
Trademarks: The Microchip name, logo, PIC, PICmicro,
PICSTART, PICMASTER, PRO MATE and MPLAB are
registered trademarks of Microchip Technology Incorpo-
rated in the U.S.A. and other countries. FlexROM, microID
and fuzzyLAB are trademarks and SQTP is a service mark
of Microchip in the U.S.A.
All other trademarks mentioned herein are the property of
their respective companies.
11195A.book Page 29 Tuesday, November 7, 2000 2:06 PM
MCP41XXX/42XXX
DS1119 5A-page 30 2000 Microchip Technology Inc.
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DS11195A
MCP41XXX/42XXX
1. What are the best features of this document?
2. How does this d ocument meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
5. What deletions from the data sheet could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you i mprove this document?
8. How would you i mprove our software, systems, and silicon products?
11195A.book Page 30 Tuesday, November 7, 2000 2:06 PM
2000 Microchip Technology Inc. DS11195A-page 31
MCP41XXX/42XXX
MCP41XXX/42XXX PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Sales and Support
Package: P = PDIP (8-lead/14-lead, 300 mil body)
SL = SOIC (8-lead/14-lead, 150 mil body)
TS = TSSOP (14-lead, 4.4mm body)
Temperature
Range: I=–40°C to +85°C
Device:
MCP41010 = Single Digital Potentiometer (10kΩ)
MCP41010T = Single Digital Potentiometer (10kΩ)[Tape & Reel]
MCP410501 = Single Digital Potentiometer (50kΩ)
MCP41050T = Single Digital Potentiometer (50kΩ)[Tape & Reel]
MCP41100 = Single Digital Potentiometer (100kΩ)
MCP41100T = Single Digital Potentiometer (100kΩ)[Tape & Reel]
MCP42010 = Dual Digital Potentiometer (10kΩ)
MCP42010T = Dual Digital Potentiometer (10kΩ)[Tape & Reel])
MCP42050 = Dual Digital Potentiometer (50kΩ)
MCP42050T = Dual Digital Potentiometer (50kΩ)[Tape & Reel])
MCP42100 = Dual Digital Potentiometer (100kΩ)
MCP42100T = Dual Digital Potentiometer (100kΩ)[Tape & Reel])
MCP41XXX/42XXX —X/X
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office (see last page)
2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277
3. The Microchip’s Bulletin Board, via your local CompuServe number (CompuServe membership NOT required).
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
11195A.book Page 31 Tuesday, November 7, 2000 2:06 PM
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by
upda tes. It is y our r esp onsib ility to en sure that your applic ation mee ts wit h yo ur sp ecifi catio ns. N o repr esen tation or warra nty is g iven and n o li abili ty is
ass ume d by M icro chip Techno logy I nco rpor ated with r espec t to the a ccur acy or us e of such info rm ation, or inf rin gem ent o f pate nts or other inte llectua l
proper ty ri ght s ar ising f rom suc h use or othe rwis e. Use of Micr ochi p’s p r od ucts as critica l c o mp onents i n lif e su ppo r t systems is not a ut h ori z ed except wi th
expres s w ri t ten ap pr o val by Mi cr o chi p. No licenses a r e co nv ey ed , imp li c it ly o r ot he rw is e , e xcep t as ma ybe exp licitly exp res se d h erein, under any intellec-
tual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights
reserved. All other trademarks mentioned herein are the property of their respective companies.
DS1119 5A-page 32 Preliminary 2000 Microchip Technology Inc.
All rights reserved. © 2000 Microchip Technology Incorporated. Printed i n the USA. 11/00 Printed on recycled paper.
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11195A.book Page 32 Tuesday, November 7, 2000 2:06 PM
