THS1240IPHP - Texas Instruments

THS1240

12-BIT 40 MSPS IF SAMPLING COMMUNICATIONS

ANALOG-TO-DIGITAL CONVERTER

SLAS279D – JUNE 2000 – REVISED JANUAR Y 2001

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

features

40-MSPS Sample Rate

12-Bit Resolution

No Missing Codes

On-Chip Sample and Hold

77-dB Spurious Free Dynamic Range at

fIN = 15.5 MHz

5-V Analog and Digital Supply

3-V and 5-V CMOS Compatible Digital

Output

10.4 Bit ENOB at fIN = 31 MHz

65 dB SNR at fIN = 15.5 MHz

120-MHz Bandwidth

Internal or External Reference

Buffered Differential Analog Input

2s Complement Digital Outputs

Typical 380 mW Power Consumption

Single-Ended or Differential Low-Level

Clock Input

applications

Wireless Local Loop

Wireless Internet Access

Cable Modem Receivers

Medical Ultrasound

Magnetic Resonant Imaging

description

The THS1240 is a high-speed low noise 12-bit CMOS pipelined analog-to-digital converter. A differential sample

and hold minimizes even order harmonics and allows for a high degree of common mode rejection at the analog

input. A buffered analog input enables operation with a constant analog input impedance, and prevents transient

voltage spikes from feeding backward to the analog input source. Full temperature DNL performance allows

for industrial application with the assurance of no missing codes. The THS1240 can operate with either internal

or external references. Internal reference usage selection is accomplished simply by externally connecting

reference output terminals to reference input terminals.

AVAILABLE OPTIONS

PACKAGE

TA48-TQFP

(PHP)

–40°C to 85°C THS1240I

0°C to 70°C THS1240C

14 15

D10

D11

AVSS

AVDD

VIN+

VIN–

AVDD

VREFOUT–

VREFIN–

VREFIN+

VREFOUT+

VBG

AVSS

AVDD 17 18 19 20

47 46 45 44 4348 42

CLK+

40 39 3841

21 22 23 24

CLK–

48 PHP PACKAGE

(TOP VIEW)

DVDD

DVSS

DVDD

DVSS

DVDD

DRVSS

DRVDD

AVSS

AVDD

AVSS

DRVSS

AVSS

DRVSS

AVDD

DRVDD

DVSS

AV SS

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

THS1240

12-BIT 40 MSPS IF SAMPLING COMMUNICATIONS

ANALOG-TO-DIGITAL CONVERTER

SLAS279D – JUNE 2000 – REVISED JANUARY 2001

2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagram

Digital Error Correction

S/H

Stage 1 Stage 10

Reference

3.0 V

2.0 V AVDD/2

Timing

VIN–

VREFOUT+

VCM

CLK+

DVSS D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

AVDD DVDD

D/A

ΣA/D

D/AA/D A/D

VREFOUT–

VREFIN+

VREFIN–

CLK–

Buffer

DRVDD

AVSS DRVSS

Stages 2 – 9

VIN+ Stage 11

D10D11

1 kΩ

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME NO.

I/O

DESCRIPTION

AVDD 2, 5, 12, 43,

45, 47 IAnalog power supply

AVSS 1, 11, 13, 41,

42, 44, 46 IAnalog ground return for internal analog circuitry

CLK+ 15 I Clock input

CLK–16 I Complementary clock input

D11–D0 25–36 O Digital data output bits; LSB= D0, MSB = D11 (2s complement output format)

DRVDD 24, 37, 38 IDigital output driver supply

DRVSS 23, 39, 40 IDigital output driver ground return

DVDD 17, 20, 22 IPositive digital supply

DVSS 18, 19, 21 IDigital ground return

VBG 10 O Band gap reference. Bypass to ground with a 1-µF and a 0.01-µF chip capacitor.

VCM 48 O Common mode voltage output. Bypass to ground with a 0.1-µF and a 0.01-µF chip capacitor.

VIN+ 3 I Analog signal input

VIN–4 I Complementary analog signal input

VREFIN–7 I External reference input low

VREFIN+ 8 I External reference input high

VREFOUT+ 9 O Internal reference output. Compensate with a 1-µF and a 0.01-µF chip capacitor.

VREFOUT–6 O Internal reference output. Compensate with a 1-µF and a 0.01-µF chip capacitor .

THS1240

12-BIT 40 MSPS IF SAMPLING COMMUNICATIONS

ANALOG-TO-DIGITAL CONVERTER

SLAS279D – JUNE 2000 – REVISED JANUARY 2001

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional description

The THS1240 uses a differential pipeline architecture and assures no missing codes over the full operating

temperature range. The device uses a 1 bit per stage architecture in order to achieve the highest possible

bandwidth. The differential analog inputs are terminated with a 1-kΩ resistor . The inputs are then fed to a unity

gain buffer followed by the S/H (sample and hold) stage. This S/H stage is a switched capacitor operational

amplifier-based circuit, see Figure 3. The pipeline is a typical 1 bit per stage pipeline as shown in the functional

block diagram. The digital output of the 12 stages is sent to a digital correction logic block which then outputs

the final 12 bits.

absolute maximum ratings over operating free-air temperature (unless otherwise noted)†

Supply voltage range: AVDD –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DVDD –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DRVDD –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage between AVSS and DVSS and DRVSS –0.3 V to 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage between DRVDD and DVDD –0.5 V to 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage between AVDD and DVDD –0.5 V to 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital data output –0.3 V to DVDD+0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CLK peak input current, Ip(CLK) 20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Peak total input current (all inputs), Ip –30 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, TA: THS1240C 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

THS1240I –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . .

†Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only , and

functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.

Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

MIN NOM MAX UNIT

Sample rate 1 40 MSPS

Analog supply voltage, AVDD 4.75 5 5.25 V

Digital supply voltage, DVDD 4.75 5 5.25 V

Digital output driver supply voltage, DRVDD 3 3.3 5.25 V

CLK + high level input voltage, VIH‡3.5 5 5.25 V

CLK + low-level input voltage, VIL‡0 1.5 V

CLK pulse-width high, tp(H) 10 12.5 ns

CLK pulse-width low, tp(L) 10 12.5 ns

erating free air tem

erature range TA

THS1240C 0 70

°C

Operating

free

air

temperature

range

ATHS1240I –40 85

°C

‡CLK– Input tied to ground with 0.01 µF capacitor for single-ended clock source.

THS1240

12-BIT 40 MSPS IF SAMPLING COMMUNICATIONS

ANALOG-TO-DIGITAL CONVERTER

SLAS279D – JUNE 2000 – REVISED JANUARY 2001

4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range,

AVDD = DVDD = 5 V, DRVDD = 3.3 V, internal references, CLK = 40 MHz, single-ended clock source

at 40 MHz with 50% duty cycle (unless otherwise noted)

dc accuracy

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

DNL Differential nonlinearity fIN = 15.5 MHz –1±0.6 1.25 LSB

No missing codes Assured

INL Integral nonlinearity fIN = 15.5 MHz ±2 LSB

EOOffset error V(VIN+) = V(VIN_) = VCM 14 70 mV

EGGain error –7–10 %FSR

†All typical values are at TA = 25°C.

power supply

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

I(AVDD) Analog supply current V(VIN) = (VCM) 73 110 mA

I(DVDD) Digital supply current V(VIN) = (VCM) 2 4 mA

I(DRVDD) Output driver supply current‡V(VIN) = (VCM) 2 7 mA

PDPower dissipation V(VIN) = (VCM) 380 mW

†All typical values are at TA = 25°C.

‡15 pF load on digital outputs

reference

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

VREFOUT–Negative reference output voltage 1.9 2 2.1 V

VREFOUT+ Positive reference output voltage 2.9 3 3.1 V

VREFIN–External reference supplied 2 V

VREFIN+ External reference supplied 3 V

V(VCM)Common mode output voltage AVDD/2 V

I(VCM)Common mode output current 80 µA

†All typical values are at TA = 25°C.

analog input

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

RIDifferential input resistance 1 kΩ

CIDifferential input capacitance 4 pF

VIAnalog input common mode range VCM ±0.05 V

VID Differential input voltage range 2Vp-p

BW Analog input bandwidth (large signal) –3 dB 120 MHz

†All typical values are at TA = 25°C.

digital outputs

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

VOH High-level output voltage IOH = –50 µA 0.8DRVDD V

VOL Low-level output voltage IOL = 50 µA 0.2DRVDD VDD

CLOutput load capacitance 15 pF

†All typical values are at TA = 25°C.

THS1240

12-BIT 40 MSPS IF SAMPLING COMMUNICATIONS

ANALOG-TO-DIGITAL CONVERTER

SLAS279D – JUNE 2000 – REVISED JANUARY 2001

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ac specifications over recommended operating free-air temperature range, AVDD = DVDD = 5 V,

DRVDD = 3.3 V, internal references, CLK = 40 MHz, analog input at –2 dBFS, single-ended clock

source at 40 MHz with 50% duty cycle (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

fIN = 2.2 MHz 64.6

fIN = 15.5 MHz 64

SNR Signal-to-noise ratio fIN = 15.5 MHz, V(IN) = –0.5 dBFS 63 65.5 dB

fIN = 31 MHz 64

fIN = 70 MHz 64

fIN = 2.2 MHz 63.3

fIN = 15.5 MHz 64

SINAD Signal-to-noise and distortion fIN = 15.5 MHz, V(IN) = –0.5 dBFS 62 64.5 dB

fIN = 31 MHz 63.2

fIN = 70 MHz 55.7

ENOB

Effective number of bits

fIN = 15.5 MHz 10.2

bits

ENOB

Effective

number

bits

fIN = 15.5 MHz, V(IN) = –0.5 dBFS 10 10.4

bits

THD

Total harmonic distortion

fIN = 15.5 MHz –72 –68

dBc

THD

Total

harmonic

distortion

fIN = 15.5 MHz, V(IN) = –0.5 dBFS –71

dBc

fIN = 2.2 MHz 73

fIN = 15.5 MHz 70 77

SFDR Spurious-free dynamic range fIN = 15.5 MHz, V(IN) = –0.5 dBFS 72 dBc

fIN = 31 MHz 77

fIN = 70 MHz 59.6

fIN = 2.2 MHz 82

2nd Harmonic

Distortion

fIN = 15.5 MHz –87 –70

dBc

2nd

Harmonic

Distortion

fIN = 31 MHz –77

dBc

fIN = 70 MHz –60.5

fIN = 2.2 MHz –73

3rd Harmonic

Distortion

fIN = 15.5 MHz –80.4 –70

dBc

3rd

Harmonic

Distortion

fIN = 31 MHz –77

dBc

fIN = 70 MHz –60

Two tone SFDR F1 = 14.9 MHz, F2 = 15.6 MHz,

Analog inputs at – 8 dBFS each 72 dBc

†All typical values are at TA = 25°C.

operating characteristics over recommended operating conditions, AVDD = DVDD = 5 V,

DRVDD = 3.3 V

switching specifications

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

Aperture delay, td(A) 120 ps

Aperture jitter 1ps RMS

Output delay td(O), after falling edge of CLK+ Digital outputs driving a 15 pF load each 13 ns

Pipeline delay td(PIPE) 6.5 CLK

Cycle

†All typical values are at TA = 25°C.

THS1240

12-BIT 40 MSPS IF SAMPLING COMMUNICATIONS

ANALOG-TO-DIGITAL CONVERTER

SLAS279D – JUNE 2000 – REVISED JANUARY 2001

6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

definitions of specifications

analog bandwidth

The analog input frequency at which the spectral power of the fundamental frequency of a large input signal

is reduced by 3 dB.

aperture delay

The delay between the 50% point of the rising edge of the clock and the instant at which the analog input is

sampled.

aperture uncertainity (jitter)

The sample-to-sample variation in aperture delay

differential nonlinearity

The deviation of any output code from the ideal width of 1 LSB.

integral nonlinearity

The deviation of the transfer function from an end-point adjusted reference line measured in fractions of 1 LSB.

Also the integral of the DNL curve.

clock pulse width/duty cycle

Pulse width high is the minimum amount of time that the clock pulse should be left in logic 1 state to achieve

rated performance; pulse width low is the minimum time clock pulse should be left in low state. At a given clock

rate, these specs define acceptable clock duty cycles.

offset error

The difference between the analog input voltage at which the ADC output changes from mid-scale to 1 LSB

above mid-scale, and the ideal voltage at which this transition should occur.

gain error

The difference between the analog input voltage at which the ADC output changes from full-scale to 1 LSB below

full scale, and the ideal voltage at which this transition should occur, minus the offset error

Gain Error

100%x2

*ǒ

VIN

VIN_

2V @Code 4096

total harmonic distortion

The ratio of the power of the fundamental to a given harmonic component reported in dBc.

output delay

The delay between the 50% point of the falling edge of the clock and the time when all output data bits are within

valid logic levels (not including pipeline delay).

signal-to-noise-and distortion (SINAD)

When tested with a single tone, the ratio of the signal power to the sum of the power of all other spectral

components, excluding dc, referenced to full scale.

signal-to-noise ratio (SNR)

When tested with a single tone, the ratio of the signal power to the sum of the power of all other power spectral

components, excluding dc and the first 9 harmonics, referenced to full scale.

effective number of bits (ENOB)

For a sine wave, SINAD can be expressed in terms of the effective number of bits, using the following formula,

ENOB

(SINAD

1.76)

6.02

spurious-free dynamic range (SFDR)

The ratio of the signal power to the power of the worst spur , excluding dc. The worst spurious component may

or may not be a harmonic. The ratio is reported in dBc (that is, degrades as signal levels are lowered).

THS1240

12-BIT 40 MSPS IF SAMPLING COMMUNICATIONS

ANALOG-TO-DIGITAL CONVERTER

SLAS279D – JUNE 2000 – REVISED JANUARY 2001

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

V(VIN)

CLK+

Digital Output

(D0 – D11) Data N–7

tp(H) tP(L)

td(A)

Sample N

tctd(O)

td(Pipe)

Data N–6 Data N–5 Data N–4 Data N–3 Data N–2 Data N–1 Data N Data N+1 Data N+2

Figure 1. Timing Diagram

equivalent circuits

Figure 2. References Figure 3. Analog Input Stage

φ1′

φ1

φ2

VCM

AVDD

VCM

AVSS

600 Ω

VREFOUT+

VREFOUT–

BAND

GAP

VIN+

VIN–

1 kΩ

Figure 4. Clock Inputs

DVDD

CLK+

DVSS

5 kΩ

GND

VDD

DVDD

5 kΩ

CLK–

DVSS

Timing

Circuits

DRVSS

DRVDD

10 ΩD0–D11

Figure 5. Digital Outputs

THS1240

12-BIT 40 MSPS IF SAMPLING COMMUNICATIONS

ANALOG-TO-DIGITAL CONVERTER

SLAS279D – JUNE 2000 – REVISED JANUARY 2001

8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

using the THS1240 references

The option of internal or external reference is provided by allowing for an external connection of the internal

reference to the reference inputs. This type of reference selection offers the lowest noise possible by not relying

on any active switch to make the selection. Compensating each reference output with a 1-µF and 0.01-µF chip

capacitor is required as shown in Figure 6. The differential analog input range is equal to 2 (VREFOUT+ –

VREFOUT–). When using external references, it is best to decouple the reference inputs with a 0.1-µF and

0.01-µF chip capacitor as shown in Figure 7.

0.01 µF 1 µF

VREFIN+

VREFOUT+

VREFIN–

VREFOUT–

Figure 6. Internal Reference Usage Figure 7. External Reference Usage

0.01 µF 0.1 µF

External Reference + VREFIN+

VREFIN–

External Reference –

using the THS1240 clock input

The THS1240 clock input can be driven with either a differential clock signal or a single ended clock input with

little or no difference in performance between the single-ended and differential-input configurations. The

common mode of the clock inputs is set internally to VDD/2 using 5-kΩ resistors (Figure 4).

The THS1240 clock input requires a common mode voltage or dc component of VDD/2. It is possible for the

common mode voltage of the clock source to differ from VDD/2 by as much as 10% with little or no performance

degradation. The clock input should be either a sinewave or a square wave having a 50% duty cycle.

When driven with a single-ended CMOS clock input, it is best to connect the CLK– input to ground with a 0.01 µF

capacitor (see Figure 8).

CLK+

THS1240

CLK–

Square Wave or Sine W ave

2 V p-p to 5 V p-p

Common Mode Voltage = VDD/2

0.01 µF

Figure 8. Driving the Clock From a Single-Ended Clock Source

THS1240

12-BIT 40 MSPS IF SAMPLING COMMUNICATIONS

ANALOG-TO-DIGITAL CONVERTER

SLAS279D – JUNE 2000 – REVISED JANUARY 2001

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

using the THS1240 clock input (continued)

If the dc component of the input clock differs from VDD/2 by more than 10%, it is best to connect the CLK+ input

to the clock source through a 0.01 µF capacitor. In this mode, the converter can operate with a clock having a

peak-to-peak voltage of as little as 2 V with little or no performance degradation (see Figure 9).

CLK+

THS1240

CLK–

Square Wave or

Sine W ave

2 V p-p to 5 V p-p

0.01 µF

Figure 9. AC-Coupled Single-Ended Clock Input

The THS1240 clock input can also be driven differentially . If the common mode of the clock input is VDD/2, then

the clock inputs can be driven directly (see Figure 10)

CLK+

THS1240

CLK–

Differential Square Wave or

Sine Wave 2 V p-p to 5 V p-p

Common Mode Voltage = VDD/2

Figure 10. Differential Clock Input

If the clock input is driven differentially with a clock signal having a common mode voltage that is dif ferent from

VDD/2, then it is best to connect both clock inputs to the differential input clock signal with 0.01 µF capacitors

(see Figure 11). The differential input swing can vary between 2 V and 5 V with little or no performance

degradation.

CLK+

THS1240

CLK–

Differential Square Wave or

Sine W ave

2 V p-p to 5 V p-p 0.01 µF

0.01 µF

Figure 11. AC-Coupled Differential Clock Input

THS1240

12-BIT 40 MSPS IF SAMPLING COMMUNICATIONS

ANALOG-TO-DIGITAL CONVERTER

SLAS279D – JUNE 2000 – REVISED JANUARY 2001

10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

using the analog input

The THS1240 obtains optimum performance when the analog signal inputs are driven differentially. The circuit

below shows the optimum configuration, see Figure 12. The signal is fed to the primary of an RF transformer.

Since the input signal must be biased around the common mode voltage of the internal circuitry, the common

mode (VCM) reference from the THS1240 is connected to the center-tap of the secondary. To ensure a steady

low noise VCM reference, the best performance is obtained when the VCM output is connected to ground with

a 0.1-µF and 0.01-µF low inductance capacitor.

VIN+

VCM

THS1240

0.01 µF 0.1 µF

Z0 = 50 Ω1:1

VIN–

50 Ω

AC Signal Source

T1-1T

50 Ω

Figure 12. Driving the THS1240 Analog Input With Impedance Matched Transmission Line

When it is necessary to buffer or apply a gain to the incoming analog signal, it is also possible to combine a

single-ended amplifier with an RF transformer as shown in Figure 13. For this application, a wide-band current

mode feedback amplifier such as the THS3001 is best. The noninverting input to the operational amplifier is

terminated with a resistor having an impedance equal to the characteristic impedance of the trace that sources

the IF input signal. The single-ended output allows the use of standard passive filters between the amplifier

output and the primary. In this case, the SFDR of the operational amplifier is not as critical as that of the A/D

converter. While harmonics generated from within the A/D converter fold back into the first Nyquist zone,

harmonics generated externally in the operational amplifier can be filtered out with passive filters.

VIN+

VIN–VCM

THS1240

0.1 µF 0.01 µF

+BPF

10 Ω

1 kΩ1 kΩ

IF Input THS3001

Impedance Ratio = 1:n

Figure 13. IF Input Buffered With THS3001 Operational Amplifier

THS1240

12-BIT 40 MSPS IF SAMPLING COMMUNICATIONS

ANALOG-TO-DIGITAL CONVERTER

SLAS279D – JUNE 2000 – REVISED JANUARY 2001

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

digital outputs

The digital outputs are in 2s complement format and can drive either TTL, 3-V CMOS, or 5-V CMOS logic. The

digital output high voltage level is equal to DRVDD. Table 1 shows the value of the digital output bits for full scale

analog input voltage, midrange analog input voltage, and negative full scale input voltage. To reduce capacitive

loading, each digital output of the THS1240 should drive only one digital input. The CMOS output drivers are

capable of handling up to a 15-pF load. For better SNR performance, use 3.3 V for DRVDD. Resistors of 200 Ω

in series with the digital output can be used for optimizing SNR performance.

Table 1. Digital Outputs

ANALOG INPUT

D11

D10

VIN+ VIN–

D11

D10

Vref+ Vref–011111111111

VCM VCM 000000000000

Vref–Vref+ 100000000000

power supplies

Best performance is obtained when AVDD is kept separate from DVDD. Regulated or linear supplies, as opposed

to switched power supplies, must be used to minimize supply noise. It is also recommended to partition the

analog and digital components on the board in such a way that the analog supply plane does not overlap with

the digital supply plane in order to limit dielectric coupling between the different supplies.

package

The THS1240 is packaged in a small 48-pin quad flat-pack PowerPAD package. The die of the THS1240 is

bonded directly to copper alloy plate which is exposed on the bottom of the package. Although, the PowerPAD

provides superior heat dissipation when soldered to a ground land, it is not necessary to solder the bottom of

the PowerPAD to anything in order to achieve minimum performance levels indicated in this specification over

the full recommended operating temperature range.

Only if the device is to be used at ambient temperatures above the recommended operating temperatures, use

of the PowerPAD is suggested.

The copper alloy plate or PowerPAD is exposed on the bottom of the device package for a direct solder

attachment to a PCB land or conductive pad. The land dimensions should have minimum dimensions equal to

the package dimensions minus 2 mm, see Figure 14.

For a multilayer circuit board, a second land having dimensions equal to or greater than the land to which the

device is soldered should be placed on the back of the circuit board (see Figure 15). A total of 9 thermal vias

or plated through-holes should be used to connect the two lands to a ground plane (buried or otherwise) having

a minimum total area of 3 inches square in 1 oz. copper. For the THS1240 package, the thermal via centers

should be spaced at a minimum of 1 mm. The ground plane need not be directly under or centered around the

device footprint if a wide ground plane thermal run having a width on the order of the device is used to channel

the heat from the vias to the larger portion of the ground plane. The THS1240 package has a standoff of 0.19

mm or 7.5 mils. In order to apply the proper amount of solder paste to the land, a solder paste stencil with a 6

mils thickness is recommended for this device. Too thin a stencil may lead to an inadequate connection to the

land. Too thick a stencil may lead to beading of solder in the vicinity of the pins which may lead to shorts. For

more information, refer to Texas Instruments literature number SLMA002 PowerPAD Thermally Enhanced

Package.

PowerPAD is a trademark of Texas Instruments.

THS1240

12-BIT 40 MSPS IF SAMPLING COMMUNICATIONS

ANALOG-TO-DIGITAL CONVERTER

SLAS279D – JUNE 2000 – REVISED JANUARY 2001

12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

package (continued)

5 mm

2 x 1,25 mm1,25 mm

2 x 1,25 mm

1,25 mm

0,33 mm Diameter

Plated Through Hole

Figure 14. Thermal Land (top view)

ÎÎÎÎÎÎ

ÏÏÏÏÏ

ÏÏÏÏ

ÎÎÎÎÎ

ÌÌ

ÎÎ

Thermal

Land PWB

PHP (S-PQFP-G48)

Plated Through Hole

Figure 15. Top and Bottom Thermal Lands With Plated Through Holes (side view)

THS1240

12-BIT 40 MSPS IF SAMPLING COMMUNICATIONS

ANALOG-TO-DIGITAL CONVERTER

SLAS279D – JUNE 2000 – REVISED JANUARY 2001

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0 5 10 15 20

OUTPUT POWER SPECTRUM

f – Frequency – MHz

FS = 40 MSPS

fIN = 2.2 MHz

VIN = –2 dBFS

8K Point Discrete

Fourier Transform

Power – dBFS

Figure 16

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0 5 10 15 20

OUTPUT POWER SPECTRUM

f – Frequency – MHz

FS = 40 MSPS

fIN = 15.5 MHz

VIN = –2 dBFS

8K Point Discrete

Fourier Transform

Power – dBFS

Figure 17

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0 5 10 15 20

OUTPUT POWER SPECTRUM

f – Frequency – MHz

FS = 40 MSPS

fIN = 31 MHz

VIN = –2 dBFS

8K Point Discrete

Fourier Transform

Power – dBFS

Figure 18

THS1240

12-BIT 40 MSPS IF SAMPLING COMMUNICATIONS

ANALOG-TO-DIGITAL CONVERTER

SLAS279D – JUNE 2000 – REVISED JANUARY 2001

14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0 5 10 15 20

OUTPUT POWER SPECTRUM

f – Frequency – MHz

FS = 40 MSPS

fIN = 69 MHz

VIN = –2 dBFS

8K Point Discrete

Fourier Transform

Power – dBFS

Figure 19

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0 5 10 15 20

TWO-TONE OUTPUT POWER SPECTRUM

f – Frequency – MHz

FS = 40 MSPS

fIN = 14.9 MHz and 15.6 MHz

VIN = –8 dBFS Each

8K Point Discrete

Fourier Transform

Power – dBFS

Figure 20

100

–60 –50 –40 –30 –20 –10 0

DYNAMIC POWER PERFORMANCE

ANALOG INPUT POWER

Analog Input Power – dBFS

FS = 40 MSPS

fIN = 15.5 MHz 3rd Harmonic (dBc)

2nd Harmonic (dBc) SINAD (dB) SFDR (dBc)

SNR (dB)

Dynamic Power Performance – dB

Figure 21

THS1240

12-BIT 40 MSPS IF SAMPLING COMMUNICATIONS

ANALOG-TO-DIGITAL CONVERTER

SLAS279D – JUNE 2000 – REVISED JANUARY 2001

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

100

0 102030405060

DYNAMIC POWER PERFORMANCE

SAMPLING RATE

Sampling Rate – MSPS

fIN = 15.5 MHz

VIN = –2 dBFS

3rd Harmonic (dBc)

2nd Harmonic (dBc)

SINAD (dB) SFDR (dBc)

SNR (dB)

Dynamic Power Performance – dB

Figure 22

100

30 40 50 60 70

DYNAMIC POWER PERFORMANCE

DUTY CYCLE

Duty Cycle – %

fIN = 15.5 MHz

VIN_ –2 dBFS

Dynamic Power Performance – dB, dBc

SINAD (dB)

SFDR (dBc) SNR (dB)

Figure 23

THS1240

12-BIT 40 MSPS IF SAMPLING COMMUNICATIONS

ANALOG-TO-DIGITAL CONVERTER

SLAS279D – JUNE 2000 – REVISED JANUARY 2001

16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

100

0 1020304050607080

DYNAMIC POWER PERFORMANCE

ANALOG INPUT FREQUENCY

Analog Input Frequency – MHz

FS = 40 MSPS

VIN = –2 dBFS

3rd Harmonic (dBc)

2nd Harmonic (dBc)

SINAD (dB)SFDR (dBc)

SNR (dB)

Dynamic Power Performance – dB, dBc

Figure 24

–1

0 512 1024 1536 2048 2560 3072 3584 4096

DIFFERENTIAL NONLINEARITY

OUTPUT CODE

Output Code

fIN = 15.5 MHz

Differential Nonlinearity – LSB

Figure 25

THS1240

12-BIT 40 MSPS IF SAMPLING COMMUNICATIONS

ANALOG-TO-DIGITAL CONVERTER

SLAS279D – JUNE 2000 – REVISED JANUARY 2001

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

–2

–1

0 512 1024 1536 2048 2560 3072 3584 4096

INTEGRAL NONLINEARITY

OUTPUT CODE

Output Code

fIN = 15.5 MHz

Integral Nonlinearity – LSB

Figure 26

–30

–25

–20

–15

–10

–5

0 20 40 60 80 100 120 140 160 180 200

ANALOG INPUT POWER BANDWIDTH

f – Frequency – MHz

FS = 40 MSPS

VIN = –2 dBFS

Power – dBFS

Figure 27

THS1240

12-BIT 40 MSPS IF SAMPLING COMMUNICATIONS

ANALOG-TO-DIGITAL CONVERTER

SLAS279D – JUNE 2000 – REVISED JANUARY 2001

18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

PHP (S-PQFP-G48) PowerPAD PLASTIC QUAD FLATPACK

Thermal Pad

(see Note D)

Gage Plane

0,13 NOM

0,25

0,45

0,75

Seating Plane

4146927/A 01/98

0,17

0,27

7,20

6,80

5,50 TYP

8,80

9,20

1,05

0,95

1,20 MAX

0,50 M

0,08

0°–7°

0,05

0,15

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusions.

D. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane. This pad is electrically

and thermally connected to the backside of the die and possibly selected leads.

E. Falls within JEDEC MO-153

PowerPAD is a trademark of Texas Instruments.

PACKAGING INFORMATION

Orderable Device Status (1) Package

Type Package

Drawing Pins Package

Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)

THS1240CPHP OBSOLETE HTQFP PHP 48 TBD Call TI Call TI

THS1240IPHP OBSOLETE HTQFP PHP 48 TBD Call TI Call TI

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

PACKAGE OPTION ADDENDUM

www.ti.com 30-Mar-2005

Addendum-Page 1

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