MLX71121KLQ-AAA-000-TU - Melexis

dsPIC30F2011/2012/3012/3013

Data Sheet

High-Performance,

16-bit Digital Signal Controllers

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defen d, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,

KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,

PIC32 logo, rfPIC and UNI/O are registered trademarks of

Microchip Te chnology Incorporated in the U.S.A. and other

countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,

MXDEV, MXLAB, SEEVAL and The Embedded Control

Solutions Company are registered trademarks of Microchip

Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,

ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial

Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified

logo, MPLIB, MPLINK, mTouch, Omniscient Code

Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,

PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,

TSHARC, UniWinDriver, WiperLock and ZENA are

trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

SQTP is a service mark of Microchip T echnology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

ISBN: 978-1-60932-631-9

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:200 2 certif ication for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in Calif ornia

and India. The Company’s quality system processes and procedures

are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping

devices, Serial EEPROMs, microper ipher als, nonvol ati le memo ry and

analog product s. In addition, Microchip ’s quality system for th e design

and manufacture of development systems is ISO 9001:2000 certified.

dsPIC30F2011/2012/3012/3013

High-Performance Modified RISC CPU:

• Modified Harvard architecture

• C compiler optimized instruction set architecture

• Flexible addressing modes

• 83 base instructions

• 24-bit wide instructions, 16-bit wide data path

• Up to 24 Kbytes on-chip Flash program space

• Up to 2 Kbytes of on-chip data RAM

• Up to 1 Kbytes of nonvolatile data EEPROM

• 16 x 16-bit working register array

• Up to 30 MIPS operation:

- DC to 40 MHz external clock input

- 4 MHz - 10 MHz oscillator input with

PLL active (4x, 8x, 16x)

• Up to 21 interrupt sources:

- 8 user-selectable priority levels

- 3 external interrupt sources

- 4 processor trap sources

DSP Features:

• Dual data fetch

• Modulo and Bit-Reversed modes

• Two 40-bit wide accumulators with optional

saturation logic

• 17-bit x 17-bit single-cycle hardware fractional/

integer multiplier

• All DSP instructions are single cycle

- Multiply-Accumulate (MAC) operation

• Single-cycle ±16 shift

Peripheral Features:

• High-current sink/source I/O pins: 25 mA/25 mA

• Three 16-bit timers/counters; optionally pair up

16-bit timers into 32-bit timer modules

• 16-bit Capture input functions

• 16-bit Compare/PWM output functions

• 3-wire SPI modules (supports four Frame modes)

•I

2C™ module supports Multi-Master/Slave mode

and 7-bit/10-bit addressing

• Up to two addressable UART modules with FIFO

buffers

Analog Features:

• 12-bit Analog-to-Digital Converter (ADC) with:

- 200 ksps conversion rate

- Up to 10 input channels

- Conversion available during Sleep and Idle

• Programmable Low-Voltage Detection (PLVD)

• Programmable Brown-out Reset

Special Microcontroller Features:

• Enhanced Flash program memory:

- 10,000 erase/write cycle (min.) for

industrial temperature range, 100K (typical)

• Data EEPROM memory:

- 100,000 erase/write cycle (min.) for

industrial temperature range, 1M (typical)

• Self-reprogrammable under software control

• Power-on Reset (POR), Power-up Timer (PWR T)

and Oscillator Start-up Timer (OST)

• Flexible Wa tchdog Timer (WDT) with on-chip

low-power RC oscillator for reliable operation

• Fail-Safe Clock Monitor operation:

- Detects clock failure and switches to on-chip

low-power RC oscillator

• Programmable code protection

• In-Circuit Serial Programming™ (ICSP™)

• Selectable Power Management mode s:

- Sleep, Idle and Alternate Clock modes

CMOS Technology:

• Low-power, high-speed Flash technology

• Wide operating voltage range (2.5V to 5.5V)

• Industrial and Extended temperature ranges

• Low-power consumption

Note: This data sheet summarizes features of

this group of dsPIC30F devices and is not

intended to be a complete reference

source. For more information on the CPU,

peripherals, register descriptions and

general device functionality, refer to the

“dsPIC30F Family Reference Manual”

(DS70046). For more information on the

device instruction set and programming,

refer to the “16-bit MCU and DSC

Programmer’s Reference Manual”

(DS70157).

High-Performance, 16-bit Digital Signal Contr ollers

dsPIC30F2011/2012/3012/3013

dsPIC30F2011/2012/3012/3013 Sensor Family

Pin Diagrams

Device Pins Program Memory SRAM

Bytes EEPROM

Bytes Timer

16-bit Input

Cap

Output

Comp/Std

PWM

A/D 12-bit

200 Ksps

UART

SPI

I2C™

Bytes Instructions

dsPIC30F2011 18 12K 4K 1024 – 3 2 2 8 ch 1 1 1

dsPIC30F3012 18 24K 8K 2048 1024 3 2 2 8 ch 1 1 1

dsPIC30F2012 28 12K 4K 1024 – 3 2 2 10 ch 1 1 1

dsPIC30F3013 28 24K 8K 2048 1024 3 2 2 10 ch 2 1 1

EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13

EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14

OSC1/CLKI VDD

OSC2/CLKO/RC15 PGD/EMUD/AN4/U1TX/SDO1/SCL/CN6/RB4

AVDD

PGC/EMUC/AN5/U1RX/SDI1/SDA/CN7/RB5

EMUD2/AN7/OC2/IC2/INT2/RB7

EMUD3/AN0/VREF+/CN2/RB0

VSS

AN6/SCK1/INT0/OCFA/RB6

AVSS

EMUC3/AN1/VREF-/CN3/RB1

AN2/SS1/LVDIN/CN4/RB2

10 EMUC2/OC1/IC1/INT1/RD0

18-Pin PDIP and SOIC

dsPIC30F2011

dsPIC30F3012

AN3/CN5/RB3

MCLR

28-Pin PDIP and SOIC

MCLR

VSS

VDD

EMUD3/AN0/VREF+/CN2/RB0

EMUC3/AN1/VREF-/CN3/RB1

AVDD

AVSS

AN2/SS1/LVDIN/CN4/RB2

IC2/INT2/RD9 EMUC2/IC1/INT1/RD8

EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14

EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 VSS

OSC2/CLKO/RC15

OSC1/CLKI VDD

SCK1/INT0/RF6

PGC/EMUC/U1RX/SDI1/SDA/RF2

PGD/EMUD/U1TX/SDO1/SCL/RF3

AN5/CN7/RB5

AN4/CN6/RB4

AN3/CN5/RB3

AN6/OCFA/RB6

EMUD2/AN7/RB7

AN8/OC1/RB8

AN9/OC2/RB9

CN17/RF4

CN18/RF5

dsPIC30F2012

MCLR

VSS

VDD

EMUD3/AN0/VREF+/CN2/RB0

EMUC3/AN1/VREF-/CN3/RB1

AVDD

AVSS

AN2/SS1/LVDIN/CN4/RB2

IC2/INT2/RD9 EMUC2/IC1/INT1/RD8

EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14

EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 VSS

OSC2/CLKO/RC15

OSC1/CLKI VDD

SCK1/INT0/RF6

PGC/EMUC/U1RX/SDI1/SDA/RF2

PGD/EMUD/U1TX/SDO1/SCL/RF3

AN5/CN7/RB5

AN4/CN6/RB4

AN3/CN5/RB3

AN6/OCFA/RB6

EMUD2/AN7/RB7

AN8/OC1/RB8

AN9/OC2/RB9

U2RX/CN17/RF4

U2TX/CN18/RF5

dsPIC30F3013

28-Pin SPDIP and SOIC

dsPIC30F2011/2012/3012/3013

Pin Diagrams

28-Pin QFN-S(1)

EMUC3/AN1/VREF-/CN3/RB1

EMUD3/AN0/VREF+/CN2/RB0

MCLR

dsPIC30F2011

AVDD

AVSS

AN6/SCK1/INT0/OCFA/RB6

EMUD2/AN7/OC2/IC2/INT2/RB7

VDD

VSS

PGC/EMUC/AN5/U1RX/SDI1/SDA/CN7/RB5

AN2/SS1/LVDIN/CN4/RB2

AN3/CN5/RB3

VSS

OSC1/CLKI

OSC2/CLKO/RC15

PGD/EMUD/AN4/U1TX/SDO1/SCL/CN6/RB4

EMUC2/OC1/IC1/INT1/RD0

EMUD1/SOSC1/T2CK/U1ATX/CN1/RC13

EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14

VDD

Note 1: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.

dsPIC30F2011/2012/3012/3013

Pin Diagrams

716

dsPIC30F2012

EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13

AVDD

AVSS

AN6/OCFA/RB6

EMUD2/AN7/RB7

AN8/OC1/RB8

AN9/OC2/RB9

CN17/RF4

CN18/RF5

VDD

VSS

PGC/EMUC/U1RX/SDI1/SDA/RF2

PGD/EMUD/U1TX/SDO1/SCL/RF3

SCK1/INT0/RF6

EMUC2/IC1/INT1/RD8

MCLR

EMUD3/AN0/VREF+/CN2/RB0

EMUC3/AN1/VREF-/CN3/RB1

AN2/SS1/LVDIN/CN4/RB2

AN3/CN5/RB3

AN4/CN6/RB4

AN5/CN7/RB5

VSS

OSC1/CLKI

OSC2/CLKO/RC15

EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14

VDD

IC2/INT2/RD9

28-Pin QFN-S(1)

Note 1: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.

dsPIC30F2011/2012/3012/3013

Pin Diagram

44434241403938373635

12131415161718192021

330

232

VDD

VSS

PGC/EMUC/AN5/U1RX/SDI1/SDA/CN7/RB5

EMUC3/AN1/VREF-/CN3/RB1

EMUD3/AN0/VREF+/CN2/RB0

MCLR

AVDD

AN6/SCK1/INT0/OCFA/RB6

EMUD2/AN7/OC2/IC2/INT2/RB7

AN2/SS1/LVDIN/CN4/RB2

AN3/CN5/RB3

VSS

OSC1/CLKI

OSC2/CLKO/RC15

PGD/EMUD/AN4/U1TX/SDO1/SCL/CN6/RB4

EMUC2/OC1/IC1/INT1/RD0

EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14

VDD

AVSS

EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13

VSS

dsPIC30F3012

44-Pin QFN(1)

Note 1: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.

dsPIC30F2011/2012/3012/3013

Pin Diagrams

44-Pin QFN(1)

AN8/OC1/RB8

AN9/OC2/RB9

U2RX/CN17/RF4

U2TX/CN18/RF5

VDD

VSS

PGC/EMUC/U1RX/SDI1/SDA/RF2

EMUC3/AN1/VREF-/CN3/RB1

EMUD3/AN0/VREF+/CN2/RB0

MCLR

AVDD

AN6/OCFA/RB6

EMUD2/AN7/RB7

AN2/SS1/LVDIN/CN4/RB2

AN3/CN5/RB3

AN4/CN6/RB4

AN5/CN7/RB5

VSS

OSC1/CLKI

OSC2/CLKO/RC15

PGD/EMUD/U1TX/SDO1/SCL/RF3

SCK1/INT0/RF6

EMUC2/IC1/INT1/RD8

EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14

IC2/INT2/RD9

VDD

AVSS

EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13

VSS

dsPIC30F3013

330

232

Note 1: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.

dsPIC30F2011/2012/3012/3013

Table of Content s

1.0 Device Overview ........................................................................................................................................................................ 11

2.0 CPU Architecture Overview........................................................................................................................................................ 19

3.0 Memory Organization................................................................................................................................................................. 29

4.0 Address Generator Units............................................................................................................................................................ 43

5.0 Flash Program Memory.............................................................................................................................................................. 49

6.0 Data EEPROM Memory.................................... ......................................................................................................................... 55

7.0 I/O Ports..................................................................................................................................................................................... 59

8.0 Interrupts.................................................................................................................................................................................... 65

9.0 Timer1 Module ........................................................................................................................................................................... 73

10.0 Timer2/3 Module ........................................................................................................................................................................ 77

11.0 Input Capture Module................................................................................................................................................................. 83

12.0 Output Compare Module............................................................................................................................................................ 87

13.0 SPI™ Module............................................................................................................................................................................. 93

14.0 I2C™ Module ............................................................................................................................................................................. 97

15.0 Universal Asynchronous Receiver Transmitter (UART) Module .............................................................................................. 105

16.0 12-bit Analog-to-Digital Converter (ADC) Module.................................................................................................................... 113

17.0 System Integration ...................................................................................... ............................................................................. 123

18.0 Instruction Set Summary.......................................................................................................................................................... 137

19.0 Develo pment Support............................................................................................................................................................... 145

20.0 Electrical Characteristics.......................................................................................................................................................... 149

21.0 Packaging Information....................................... ....................................................................................................................... 187

Index .................................................................................................................................................................................................. 201

The Microchip Web Site..................................................................................................................................................................... 207

Customer Change Notification Service.............................................................................................................................................. 207

Customer Support.............................................................................................................................................................................. 207

Reader Response.............................................................................................................................................................................. 208

Product Identification System ............................................................................................................................................................ 209

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If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via

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Most Current Data Sheet

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http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.

The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current

devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of

silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

• Microchip’s Worldwide Web site; http://www.microchip.com

• Your local Microchip sales office (see last page)

When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are

using.

Customer Notific atio n Syste m

dsPIC30F2011/2012/3012/3013

NOTES:

dsPIC30F2011/2012/3012/3013

1.0 DEVICE OVERVIEW

This data sheet contains information specific to the

dsPIC30F2011, dsPIC30F2012, dsPIC30F3012 and

dsPIC30F3013 Digital Signal Controllers (DSC). These

devices contain extensive Digital Signal Processor

(DSP) functionality within a high-performance 16-bit

microcontroller (MCU) architecture.

The following block diagrams depict the architecture for

these devices:

•Figure 1-1 illustrates the dsPIC30F2011

•Figure 1-2 illustrates the dsPIC30F2012

•Figure 1-3 illustrates the dsPIC30F3012

•Figure 1-4 illustrates the dsPIC30F3013

Following the block diagrams, Table 1-1 relates the I/O

functions to pinout information.

Note: This data sheet summarizes features of

this group of dsPIC30F devices and is not

intended to be a complete reference

source. For more information on the CPU,

peripherals, register descriptions and

general device functionality, refer to the

“dsPIC30F Family Reference Manual”

(DS70046). For more information on the

device instruction set and programming,

refer to the “16-bit MCU and DSC

Programmer’s Reference Manual”

(DS70157).

dsPIC30F2011/2012/3012/3013

FIGURE 1-1: dsPIC30F2011 BLOCK DIAGRAM

Power-up

Timer

Oscillator

S tart-up Timer

POR/BOR

Reset

Watchdog

Timer

Instruction

Decode &

Control

OSC1/CLKI

MCLR

, V

PGD/EMUD/AN4/U1TX/SDO1/SCL/CN6/RB4

Low-Voltage

Detect

UART1

Timing

Generation

PGC/EMUC/AN5/U1RX/SDI1/SDA/CN7/R

PCH PCL

Program Counter

ALU<16>

X Data Bus

C™

AN6/SCK1/INT0/OCFA/RB6

EMUD2/AN7/OC2/IC2/INT2/RB7

PCU

12-bit ADC

Timers

Input

Capture

Module

Output

Compare

Module

EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14

EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13

PORTB

PORTD

16 16

16 x 16

W Reg Array

Divide

Unit

Engine

DSP

Decode

ROM Latch

Y Data Bus

Effective Address

X RAGU

X WAGU

Y AGU EMUD3/AN0/V

REF

+/CN2/RB0

EMUC3/AN1/V

REF

-/CN3/RB1

AN2/SS1/LVDIN/CN4/RB2

AN3/CN5/RB3

OSC2/CLKO/RC15

, A V

PORTC

Interrupt

Controller

PSV & Table

Data Access

Control Block

Stack

Control

Logic

Loop

Control

Logic

Data LatchData Latch

Y Data

(512 bytes)

RAM X Data

(512 bytes)

RAM

Address

Latch Address

Latch

EMUC2/OC1/IC1/INT1/RD0

SPI1

Address Latch

Program Memory

(12 Kbytes)

Dat a L a tch

dsPIC30F2011/2012/3012/3013

FIGURE 1-2: dsPIC30F2012 BLOCK DIAGRAM

AN8/OC1/RB8

AN9/OC2/RB9

Power-up

Timer

Oscillator

Start-up Timer

POR/BOR

Reset

Watchdog

Timer

Instruction

Decode &

Control

OSC1/CLKI

MCLR

, V

AN4/CN6/RB4

Low-Voltage

Detect

UART1

Timing

Generation

AN5/CN7/RB5

PCH PCL

Program Counter

ALU<16>

X Data Bus

C™

AN6/OCFA/RB6

EMUD2/AN7/RB7

PCU

12-bit ADC

Timers

CN18/RF5

SCK1/INT0/RF6

Input

Capture

Module

Output

Compare

Module

EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14

EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13

EMUD3/AN0/V

REF

+/CN2/RB0

PORTB

PGC/EMUC/U1RX/SDI1/SDA/RF2

PGD/EMUD/U1TX/SDO1/SCL/RF3

PORTD

16 16

16 x 16

W Reg Array

Divide

Unit

Engine

DSP

Decode

ROM Latch

Y Data Bus

Effective Address

X RAGU

X WAGU

Y AGU AN2/SS1/LVDIN/CN4/RB2

AN3/CN5/RB3

OSC2/CLKO/RC15

CN17/RF4

, A V

PORTC

PORTF

Interrupt

Controller

PSV & Table

Data Access

Control Block

Stack

Control

Logic

Loop

Control

Logic

Data LatchData Latch

Y Data

(512 bytes)

RAM X Data

RAM

Address

Latch Address

Latch

EMUC2/IC1/INT1/RD8

IC2/INT2/RD9

EMUC3/AN1/V

REF

-/CN3/RB1

SPI1

Address Latch

Program Memory

(12 Kbytes)

Data L atch

(512 bytes)

dsPIC30F2011/2012/3012/3013

FIGURE 1-3: dsPIC30F3012 BLOCK DIAGRAM

Power-up

Timer

Oscillator

S tart-up Timer

POR/BOR

Reset

Watchdog

Timer

Instruction

Decode &

Control

OSC1/CLKI

MCLR

, V

PGD/EMUD/AN4/U1TX/SDO1/SCL/CN6/RB4

Low-Voltage

Detect

UART1

Timing

Generation

PGC/EMUC/AN5/U1RX/SDI1/SDA/CN7/R

PCH PCL

Program Counter

ALU<16>

X Data Bus

C™

AN6/SCK1/INT0/OCFA/RB6

EMUD2/AN7/OC2/IC2/INT2/RB7

PCU

12-bit ADC

Timers

Input

Capture

Module

Output

Compare

Module

EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14

EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13

PORTB

PORTD

16 16

16 x 16

W Reg Array

Divide

Unit

Engine

DSP

Decode

ROM Latch

Y Data Bus

Effective Address

X RAGU

X WAGU

Y AGU EMUD3/AN0/V

REF

+/CN2/RB0

EMUC3/AN1/V

REF

-/CN3/RB1

AN2/SS1/LVDIN/CN4/RB2

AN3/CN5/RB3

OSC2/CLKO/RC15

, A V

PORTC

Interrupt

Controller

PSV & Table

Data Access

Control Block

Stack

Control

Logic

Loop

Control

Logic

Data LatchData Latch

Y Data

(1 Kbytes)

RAM X Data

(1 Kbytes)

RAM

Address

Latch Address

Latch

EMUC2/OC1/IC1/INT1/RD0

SPI1

Address Latch

Program Memory

(24 Kb ytes)

Dat a L a tch

Data EEPROM

(1 Kb ytes)

dsPIC30F2011/2012/3012/3013

FIGURE 1-4: dsPIC30F3013 BLOCK DIAGRAM

AN8/OC1/RB8

AN9/OC2/RB9

Power-up

Timer

Oscillator

S tart-up Tim er

POR/BOR

Reset

Watchdog

Timer

Instruction

Decode &

Control

OSC1/CLKI

MCLR

, V

AN4/CN6/RB4

Low-Voltage

Detect

UART1,

Timing

Generation

AN5/CN7/RB5

PCH PCL

Program Counter

ALU<16>

X Data Bus

C™

AN6/OCFA/RB6

EMUD2/AN7/RB7

PCU

12-bit ADC

Timers

U2TX/CN18/RF5

SCK1/INT0/RF6

Input

Capture

Module

Output

Compare

Module

EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14

EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13

EMUD3/AN0/V

REF

+/CN2/RB0

PORTB

PGC/EMUC/U1RX/SDI1/SDA/RF2

PGD/EMUD/U1TX/SDO1/SCL/RF3

PORTD

16 16

16 x 16

W Reg Array

Divide

Unit

Engine

DSP

Decode

ROM Latch

Y Data Bus

Effective Address

X RAGU

X WAGU

Y AGU AN2/SS1/LVDIN/CN4/RB2

AN3/CN5/RB3

OSC2/CLKO/RC15

U2RX/CN17/RF4

, A V

UART2

PORTC

PORTF

Interrupt

Controller

PSV & Table

Data Access

Control Block

Stack

Control

Logic

Loop

Control

Logic

Data LatchData Latch

Y Data

(1 Kbytes)

RAM X Data

RAM

Address

Latch Address

Latch

EMUC2/IC1/INT1/RD8

IC2/INT2/RD9

EMUC3/AN1/V

REF

-/CN3/RB1

SPI1

(1 Kbytes)

Address Latch

Program Memory

(24 Kbytes)

Dat a L a tch

Data EEPR OM

(1 Kbyt es)

dsPIC30F2011/2012/3012/3013

Table 1-1 provides a brief description of device I/O

pinouts and the functions that may be multip lexed to a

port pin. Multiple functions may exist on one port pin.

When multiplexing occurs, the peripheral module’s

functional requirements may force an override of the

data direction of the port pin.

TABLE 1-1: PINOUT I/O DESCRIPTIONS

Pin Name Pin

Type Buffer

Type Description

AN0 - AN9 I Analog Analog input channels.

AVDD P P Positive supply for analog module. This pin must be connected at all times.

AVSS P P Ground reference for analog module. This pin must be connected at all times.

CLKI

CLKO I

OST/CMOS

—External clock source input. Always associ ated with OSC1 pin fu nct i on .

Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator

mode. Optionally functions as CLKO in RC and EC modes. Always associated

with OSC2 pin function.

CN0 - CN7 I ST Input change notification inputs.

Can be software programmed for internal weak pull-ups on all inputs.

EMUD

EMUC

EMUD1

EMUC1

EMUD2

EMUC2

EMUD3

EMUC3

I/O

ICD Primary Communication Channel data input/output pin.

ICD Primary Communication Channel clock input/output pin.

ICD Secondary Communication Channel data input/output pin.

ICD Secondary Communication Channel clock input/output pin.

ICD Tertiary Communication Channel data input/output pin.

ICD Tertiary Communication Channel clock input/output pin.

ICD Quaternary Communication Channel data input/output pin.

ICD Quaternary Communication Channel clock input/output pin.

IC1 - IC2 I ST Capture inputs 1 through 2.

INT0

INT1

INT2

External interrupt 0.

External interrupt 1.

External interrupt 2.

LVDIN I Anal og Low-Voltage Detect Reference Voltage Input pin.

MCLR I/P ST Master Clear (Reset) input or programming voltage input. This pin is an

active-low Reset to the device.

OC1-OC2

OCFA O

I—

ST Compare outputs 1 through 2.

Compare Fault A input.

OSC1

OSC2

I/O

ST/CMOS

—

Oscillator crystal input. ST buffer when configured in RC mode; CMOS

otherwise.

Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator

mode. Optionally functions as CLKO in RC and EC modes.

PGD

PGC I/O

IST

ST In-Circuit Serial Programming™ data input/output pin.

In-Circuit Serial Programming clock input pin.

RB0 - RB9 I/O ST PORTB is a bidirectional I/O port.

RC13 - RC15 I/O ST PORTC is a bidirectional I/O port.

RD0,

RD8-RD9 I/O ST PORTD is a bidirectional I/O port.

RF2 - RF5 I/O ST PORTF is a bidirectional I/O port.

SCK1

SDI1

SDO1

SS1

I/O

—

Synchronous serial clock input/ou tput for SPI1.

SPI1 Data In.

SPI1 Data Out.

SPI1 Slave Synchronization.

Legend: CMO S = CMOS compatible input or output Analog = Analog input

ST = Schmitt Trigger input with CMOS levels O = Outpu t

I = Input P = Power

dsPIC30F2011/2012/3012/3013

SCL

SDA I/O

I/O ST

ST Synchronous serial clock input/o utput for I2C™.

Synchronous serial data input/output for I2C.

SOSCO

SOSCI O

I—

ST/CMOS 32 kHz low-power oscillator crystal output.

32 kHz low-power oscillator crystal input. ST buffer when configured in RC

mode; CMOS otherwise.

T1CK

T2CK I

IST

ST Timer1 external clock input.

Timer2 external clock input.

U1RX

U1TX

U1ARX

U1ATX

U2RX

U2TX

—

UART1 Receive.

UART1 Transmit.

UART1 Alternate Receive.

UART1 Alternate Transmit.

UART2 Receive.

UART2 Transmit.

VDD P — Positive supply for logic and I/O pins.

VSS P — Ground reference for logic and I/O pins.

VREF+ I Anal og Analog Voltage Reference (High) input.

VREF- I Anal og Analog Voltage Reference (Low) input.

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name Pin

Type Buffer

Type Description

Legend: CMOS = CMOS compatible input or outp ut Analog = Analog input

ST = Schmitt Trigger input with CMOS levels O = Output

I = Input P = Power

dsPIC30F2011/2012/3012/3013

NOTES:

dsPIC30F2011/2012/3012/3013

2.0 CPU ARCHITECTURE

OVERVIEW

This section is an overview of the CPU architecture of

the dsPIC30F. The core has a 24-bit instruction word.

The Program Counter (PC) is 23 bits wide with the

Least Significant bit (LSb) always clear (see

Section 3.1 “Program Address Space”). The Most

Significant bit (MSb ) is i gnore d d uring no rma l pro gram

execution, except for certain specialized instructions.

Thus, the PC can address up to 4M instruction words

of user program space. An instruction prefetch

mechanism helps maintain throughput. Program loop

constructs, free from loop count management

overhead, are supported using the DO and REPEAT

instructions, both of which are interruptible at any point.

2.1 Core Overview

The working register array consists of 16 x 16-bit

registers, each of which can act as data, address or

offset registers. One working register (W15) operates

as a Software Stack Pointer for interrupts and calls.

The data space is 64 Kbytes (32K words) and is split

into two blocks, referred to as X and Y data memory.

Each block has its own independent Address Genera-

tion Unit (AGU). Most instructions operate solely

through the X memory, AGU, which provides the

appearance of a single unified data space. The

Multiply-Accumulate (MAC) class of dual source DSP

instructions operate through both the X and Y AGUs,

splitting the data address space into two parts (see

Section 3.2 “Data Address Space”). The X and Y

data space boundary is device specific and cannot be

altered by the user. Each data word consist s of 2 bytes

and most instructions can address data either as words

or bytes.

Two ways to access data in program memory are:

• The upper 32 Kbytes of data space memory can

be mapped into the lower half (user space) of

program space at any 16K program word

boundary, defined by the 8-bit Program S pace

Visibility Page register (PSVPAG). Thus any

instruction can access program space as if it were

data space, with a limitation that the access

requires an additional cycle. Only the lower 16

bits of each instruction word can be accessed

using this method.

• Linear indirect access of 32K word pages within

program space is also possible using any working

Table read and write instructions can be used to

access all 24 bits of an instruction word.

Overhead-free circular buffers (Modulo Addressing)

are supported in both X and Y address spaces. This is

primarily intended to remove the loop overhead for

DSP algorithms.

The X AGU also supports Bit-Reversed Addressing on

destination effective addresses to greatly simplify input

or output data reordering for radix-2 FFT algorithms.

Refer to Section 4.0 “Address Generator Units” for

details on Modulo and Bit-Reversed Addressing.

The core supports Inherent (no operand), Relative,

Literal, Memory Direct, Register Direct, Register

Indirect, Register Offset and Literal Offset Addressing

modes. Instructions are associated with pre-defined

addressing modes, depending upon their functional

requirements.

For most instructions, the core is capable of executing

a data (or program data) memory read, a working

program (instruction) memory read per instruction

cycle. As a result, 3 operand instructions are

supported, allowing C = A+B operations to be exe-

cuted in a single cycle.

A DSP engine has been included to significantly

enhance the core arithmetic capability and throughput.

It features a high-speed 17-bit by 17-bit multiplier, a

40-bit ALU, two 40-bit saturating accumulators and a

40-bit bidirectional barrel shifter. Data in the

accumulator or any working register can be shifted up

to 15 bits right, or 16 bit s left in a single cycle. The DSP

instructions operate seamlessly with all other

instructions and have been designed for optimal

real-time performance. The MAC class of instructions

can concurrently fetch two data operands from memory

while multiplying two W registers. To enable this

concurrent fetching of data operands, the data space

has been split for these instructions and linear is for all

others. This has been achieved in a transparent and

flexible manner , by dedicating certain working registers

to each address space for the MAC class of

instructions.

Note: This data sheet summarizes features of

this group of dsPIC30F devices and is not

intended to be a complete reference

source. For more information on the CPU,

peripherals, register descriptions and

general device functionality, refer to the

“dsPIC30F Family Reference Manual”

(DS70046). For more information on the

device instruction set and programming,

refer to the “16-bit MCU and DSC

Programmer’s Reference Manual”

(DS70157).

dsPIC30F2011/2012/3012/3013

The core does not support a multi-stage instruction

pipeline. However, a single-stage instruction prefetch

mechanism is used, which accesses and partially

decodes instructions a cycle ahead of execution, in

order to maximize available execution time. Most

instructions execute in a single cycle with certain

exceptions.

The core features a vectored exception processing

structure for traps and interrupts, with 6 2 independent

vectors. The exceptions consist of up to 8 traps (of

which 4 are reserved) and 54 interrupts. Each interrupt

is prioritized based on a user-assigned priority between

1 and 7 (1 being the lowest priority and 7 being the

highest), in conjunction with a predetermined ‘natural

order’. Traps have fixed priorities ranging from 8 to 15.

2.2 Programmer’s Model

The programmer’s model is shown in Figure 2-1 and

consists of 16 x 16-bit working registers (W0 through

W15), 2 x 40-bit accumulators (ACCA and ACCB),

STATUS register (SR), Data Table Page register

(TBLPAG), Program Space Visibility Page register

(PSVPAG), DO and REPEAT registers (DOSTART,

DOEND, DCOUNT and RCOUNT) and Program Coun-

ter (PC). The working registers can act as data,

address or offset registers. All registers are memory

mapped. W0 acts as the W register for file register

addressing.

Some of these registers have a shado w register asso-

ciated with each of them, as shown in Figure 2-1. The

shadow register is used as a temporary holding register

and can transfer its contents to or from its host register

upon the occurrence of an event. None of the shado w

registers are accessible directly. The following rules

apply for transfer of registers into and out of shadows.

•PUSH.S and POP.S

W0, W1, W2, W3, SR (DC, N, OV, Z and C bits

only) are transferred.

•DO instruction

DOSTART, DOEND, DCOUNT shadows are

pushed on loop start and popped on loop end.

When a byte operation is performed on a working reg-

ister, only the Least Significant Byte (LSB) of the target

mapped working registers is that both the Least and

Most Significant Bytes (MSB) can be manipulated

through byte-wide data memory space accesses.

2.2.1 SOFTWARE STACK POINTER/

FRAME POINTER

The dsPIC® DSC devices contain a software stack.

W15 is the dedicated Software Stack Pointer (SP),

which is automatically modified by exception

processing and subroutine calls and returns. However,

W15 can be referenced by any instruction in th e same

manner as all other W registers. This simplifies the

reading, writing and manipulation of the Stack Pointer

(e.g., creating stack frames).

W15 is initialized to 0x0800 during a Reset. The user

may reprogram the SP during initialization to any

location within data space.

W14 has been dedicated as a S t ack Frame Pointer, as

defined by the LNK and ULNK instructions. However,

W14 can be referenced by any instruction in th e same

manner as all other W registers.

2.2.2 STATUS REGISTER

The dsPIC DSC core has a 16-bit STATUS register

(SR), the LSB of which is referred to as the SR Low

byte (SRL) and the MSB as the SR High byte (SRH).

See Figure 2-1 for SR layout.

SRL contains all the MCU ALU operation Status flags

(including the Z bit), as well as the CPU Interrupt

Priority Level Status bits, IPL<2:0>, and the Repeat

Active Status bit, RA. During exception processing,

SRL is concatenated with the MSB of the PC to form a

complete word value which is then stacked.

The upper byte of the STATUS register contains the

DSP Adder/Subtracter Status bits, the DO Loop Active

bit (DA) and the Digit Carry (DC) Status bit.

2.2.3 PROGRAM COUNTER

The program counter is 23 bits wide; bit 0 is always

clear. Therefore, the PC can address up to 4M

instruction words.

Note: In order to protect against misaligned

stack accesses, W15<0> is always clear.

dsPIC30F2011/2012/3012/3013

FIGURE 2-1: PROGRAMMER’S MODEL

TABPAG

PC22 PC0

7 0

D0D15

Program Counter

Data Table Page Address

STATUS register

Working Registers

DSP Operand

Registers

W10

W11

W12/DSP Offset

W13/DSP Write-Back

W14/Frame Pointer

W15/Stack Pointer

DSP Address

Registers

AD39 AD0AD31

DSP

Accumulators ACCA

ACCB

PSVPAG

7 0Program Space Visibility Page Address

OA OB SA SB

RCOUNT

15 0REPEAT Loop Counter

DCOUNT

15 0DO Loop Counter

DOSTART

22 0 DO Loop Start Address

IPL2 IPL1

SPLIM Stack Pointer Limit Register

AD15

SRL

PUSH.S Shadow

DO Shadow

OAB SAB

15 0Core Configuration Register

Legend

CORCON

DA DC RA N

TBLPAG

PSVPAG

IPL0 OV

W0/WREG

SRH

DO Loop End Address

DOEND

dsPIC30F2011/2012/3012/3013

2.3 Divide Support

The dsPIC DSC devices feature a 16/16-bit signed

fractional divide operation, as well as 32/16-bit and

16/16-bit signed and unsigned integer divide opera-

tions, in the form of single instruction ite rative divides.

The following instructions and data sizes are

supported:

1. DIVF - 16/16 signed fractional divide

2. DIV.sd - 32/16 signed divide

3. DIV.ud - 32/16 unsigned divide

4. DIV.s - 16/16 signed divide

5. DIV.u - 16/16 unsigned divide

The 16/16 divides are similar to the 32/16 (same number

of iterations), but the dividend i s either zero-extended or

sign-extended during the first iteration.

The divide instructions must be executed within a

REPEAT loop. Any other form of execution

(e.g., a series of discrete divide instructions) will not

function correctly because the instruction flow depends

on RCOUNT. The divide instruction does not

automatically set up the RCOUNT value and it must,

therefore, be explicitly and correctly specified in the

REPEAT instruction, as shown in Table 2-1 (REPEAT

executes the target instruction {operand value+1}

times). The REPEAT loop count must be setup for 18

iterations of the DIV/DIVF instruction. Thus, a

complete divide operation requires 19 cycles.

TABLE 2-1: DIVIDE INSTRUCTIONS

Note: The divide flow is interruptible; however,

the user needs to save the context as

appropriate.

Instruction Function

DIVF Signed fractional divide: Wm/Wn → W0; Rem → W1

DIV.sd Signed divide: (Wm+1:Wm)/Wn → W0; Rem → W1

DIV.s Signed divide: Wm/Wn → W0; Rem → W1

DIV.ud Unsigned divide: (Wm+1:Wm)/Wn → W0; Rem → W1

DIV.u Unsigned divide: Wm/Wn → W0; Rem → W1

dsPIC30F2011/2012/3012/3013

2.4 DSP Engine

The DSP engine consists of a high-speed 17-bit x

17-bit multiplier, a barrel shifter and a 40-bit

adder/subtracter (with two target accumulators, round

and saturation logic).

The DSP engine also has the capability to perform

inherent accumulator-to-accumulator operations,

which require no additional data. These instructions are

ADD, SUB and NEG.

The dsPIC30F is a single-cycle instruction flow

architecture, therefore, concurrent operation of the

DSP engine with MCU in struction flow is not possible.

However, some MCU ALU and DSP engine reso urces

may be used concurrently by the same instruction

(e.g., ED, EDAC). See Table 2-2.

The DSP engine ha s several o ptions selected through

various bits in the CPU Core Configuration register

(CORCON), which are:

1. Fractional or inte ger DSP multip ly (IF).

2. Signed or unsigned DSP multiply (US).

3. Conventional or convergent rounding (RND).

4. Automatic saturation on/off for ACCA (SATA).

5. Automatic saturation on/off for ACCB (SATB).

6. Automatic saturation on/off for writes to data

memory (SATDW).

7. Accumulator Saturation mode selection

(ACCSAT).

A block diagram of the DSP engine is shown in

Figure 2-2.

TABLE 2-2: DSP INSTRUCTION

SUMMARY

Instruction Algebraic

Operation ACC WB?

CLR A = 0 Yes

ED A = (x – y)2No

EDAC A = A + (x – y)2No

MAC A = A + (x * y) Yes

MAC A = A + x2No

MOVSAC No change in A Yes

MPY A = x • y No

MPY.N A = – x • y No

MSC A = A – x • y Yes

Note: For CORCON layout, see Table 3-3.

dsPIC30F2011/2012/3012/3013

FIGURE 2-2: DSP ENGINE BLOCK DIAGRAM

Zero Backfill

Sign-Extend

Barrel

Shifter

40-bit Accumulator A

40-bit Accumulator B Round

Logic

X Data Bus

To/From W Array

Adder

Saturate

Negate

16 16

40 40

Y Data Bus

Carry/Borrow Out

Carry/Borrow In

Multiplier/Scaler

17-bit

dsPIC30F2011/2012/3012/3013

2.4.1 MULTIPLIER

The 17 x 17-bit multiplier is capable of signed or

unsigned operation and can multiplex its output using a

scaler to support either 1.31 fractional (Q31) or 32-bit

integer results. Unsigned operands are zero-extende d

into the 17th bit of the multiplier input value. Signed

operands are sign-extended into the 17th bit of the

multiplier input value. The output of the 17 x 17-bit

multiplier/scaler is a 33-bit value which is

sign-extended to 40 bits. Integer data is inherently

represented as a signed two’s complement value,

where the MSB is defined as a sign bit. Generally

speaking, the range of an N-bit two’s complement

integer is -2N-1 to 2N-1 – 1. For a 16-bit inte ger , the data

range is -32768 (0x8000) to 32767 (0x7F FF) incl uding

‘0’. For a 32-bit integer, the data range is

-2,147,483,648 (0x8000 0000) to 2,147,483,645

(0x7FFF FFFF).

When the multiplier is configured for fractional

multiplication, the data is represented as a two’s

complement fraction, where the MSB is defined as a

sign bit and the radix point is implied to lie just after the

sign bit (QX format). The range of an N-bit two’s

complement fraction with this implied radix point is -1.0

to (1 – 21-N). For a 16 -bit fraction, the Q15 data range

is -1.0 (0x8000) to 0.999969482 (0x7FFF) including ‘0’

and has a precision of 3.01518x10-5. In Fractional

mode, the 16x16 multiply operation generates a 1.31

product, which has a precision of 4.65661 x 10-10.

The same multiplier is used to support the MCU

multiply instructions, which include integer 16-bit

signed, unsigned and mixed sign multipl ies.

The MUL instruction can be directed to use byte or

word-sized operands. Byte operands direct a 16-bit

result. Word operands direct a 32-bit result to the

specified register(s) in the W array.

2.4.2 DATA ACCUMULATORS AND

ADDER/SUBTRACTER

The data accumulator consists of a 40-bit

adder/subtracter with automatic sign extension logic. It

can select one of two accumulators (A or B) as its

pre-accumulation source and post-accumulation

destination. For the ADD and LAC instructions, the data

to be accumulated or lo aded can be optionally scaled

through the barrel shifter prior to accumulation.

2.4.2.1 Adder/Subtracter, Overflow and

Saturation

The adder/subtracter is a 40-bi t a dder with an option al

zero input into one side and either true or co mplement

data into the other input. In the case of addition, the

carry/borrow input is active high and the other input is

true data (not complemented), where as in the case of

subtraction, the carry/borrow input is active low and the

other input is complemented. The adder/subtracter

generates overflow status bits SA/SB and OA/OB,

which are latched and reflected in the ST A TUS register:

• Overflow from bit 39: This is a catastrophic

overflow in which the sign of the accumulator is

destroyed.

• Overflow into guard bits 32 through 39: This is a

recoverable overflow. This bit is set whenever all

the guard bits are not identical to each other.

The adder has an additional saturation block which

controls accumulator data saturation if selected. It uses

the result of the adder, the overflow Status bits

described above, and the mode control bits SATA/B

(CORCON<7:6>) and ACCSAT (CORCON<4>) to

determine when and to what value to sa turate.

Six STATUS register bits have been provided to

support saturation and overflow. They are:

• OA: ACCA overflowed into guard bits

• OB: ACCB overflowed into guard bits

• SA: ACCA saturated (bit 31 overflow and

saturation)

ACCA overflowed into guard bits and saturated

(bit 39 overflow and saturation)

• SB: ACCB saturated (bit 31 overflow and

saturation)

ACCB overflowed into guard bits and saturated

(bit 39 overflow and saturation)

• OAB: Logical OR of OA and OB

• SAB: Logical OR of SA and SB

The OA and OB bits are modified each time data

passes through the adder/subtracter. When set, they

indicate that the most recent ope ration has overflowed

into the accumulator guard bits (bits 32 through 39).

The OA and OB bits can also optionally generate an

arithmetic warning trap when set and the

corresponding overflow trap flag enable bit (OVATE,

OVBTE) in the INTCON1 register (refer to Section 8.0

“Interrupts”) is set. This allows the user to take

immediate action, for example, to correct system gain.

dsPIC30F2011/2012/3012/3013

The SA and SB bits are modified each time data

passes through the adder/subtracter but can only be

cleared by the user. When set, they indicate that the

accumulator has overflowed its maximum range (bit 31

for 32-bit saturation or bit 39 for 40-bit saturation) and

will be saturated if saturation is enabled. When satura-

tion is not enabled, SA and SB default to bit 39 overflow

and thus indicate that a catastrophic overflow has

occurred. If the COVTE bit in the INTCON1 register is

set, SA and SB bits generate an arithmetic warning trap

when saturation is disabled.

The overflow and saturation Status bits can optionally

be viewed in the STATUS register (SR) as the logical

OR of OA and OB (in bit OAB) and the logical OR of SA

and SB (in bit SAB). This allows programmers to check

one bit in the STATUS register to determine if either

accumulator has overflowed, or one bit to determin e if

either accumulator has saturated. This would be useful

for complex number arithmetic which typically uses

both the accumulators.

The device supports three saturation and overflow

modes:

1. Bit 39 Overflow and Saturation:

When bit 39 overflow and saturation occurs, the

saturation logic loads the maximally positive 9.31

(0x7FFFFFFFFF) or maximally negative 9.31

value (0x8000000000) into the target

accumulator . The SA or SB bit is set and remains

set until cleared by the user. This is referred to as

‘super saturation’ and provides protection against

erroneous data or unexpected algorithm

problems (e.g., gain calculations).

2. Bit 31 Overflow and Saturation:

When bit 31 overflow and saturation occurs, the

saturation logic then loads the maximally posi-

tive 1.31 value (0x007FFFFFFF) or maximally

negative 1.31 value (0x0080000000) into the

target accumulator. The SA or SB bit is set and

remains set until cleared by the user. When this

Saturation mode is in effect, the guard bits are

not used, so the OA, OB or OAB bits are never

set.

3. Bit 39 Catastrophi c Ov er fl ow:

The bit 39 overfl ow Status bit from the ad der is

used to set the SA or SB bit which remains set

until cleared by the user . No saturation operation

is performed and the accumula tor is allowed to

overflow (destroying its sign). If the COVTE bit in

the INTCON1 register is set, a catastrophic

overflow can initiate a trap exception.

2.4.2.2 Accumulator ‘Write-Back’

The MAC class of instructions (with the exception of

MPY, MPY.N, ED and EDAC) can optionally write a

rounded version of the high word (bits 31 through 16)

of the accumulator that is not targeted by the instruction

into data space memory. The write is performed across

the X bus into combined X and Y address space. The

following addressing modes are supported:

1. W13, Register Direct:

The rounded contents of the non-target

accumulator are written into W13 as a 1.15

fraction.

2. [W13]+ = 2, Register Indirect with

Post-Increment:

The rounded contents of the non-target

accumulator are written into the address pointed

to by W13 as a 1.15 fraction. W13 is then

incremented by 2 (for a word write).

2.4.2.3 Round Logic

The round logic is a combinational block which

performs a conventional (biased) or convergent

(unbiased) round fu nction during an accumu lator write

(store). The Round mode is determined b y the state of

the RND bit in the CORCON register. It generates a

16-bit, 1.15 data value, which is passed to the data

space write saturation logic. If rounding is not indicated

by the instruction, a truncated 1.15 data value is stored

and the least significant word (lsw) is simply discarded.

Conventional rounding takes bit 15 of the accumulator,

zero-extends it and adds it to the ACCxH word (bits 16

through 31 of the accumulator). If the ACCxL word

(bits 0 through 15 of the accumulator) is between

0x8000 and 0xFFFF (0x8000 included), ACCxH is

incremented. If ACCxL is between 0x0000 and 0x7FFF ,

ACCxH is left unchanged. A consequence of this

algorithm is that over a succession of random rounding

operations, the value tends to be biased slightly

positive.

Convergent (or unbiased) rounding operates in the

same manner as conventi onal rounding, except when

ACCxL equals 0x8000. If this is the case, the LSb

(bit 16 of the accumulator) of ACCxH is examined. If it

is ‘1’, ACCxH is incremented. If it is ‘0’, ACCxH is not

modified. Assuming that bit 16 is effectively random in

nature, this scheme will remove any rounding bias that

may accumulate.

The SAC and SAC.R instructions store either a

truncated (SAC) or rounded (SAC.R) version of the

contents of the target accumulator to data memory via

the X bus (subject to data saturation, see

Section 2.4.2.4 “Data Space Write Saturation”).

Note that for the MAC class of instructions, the

accumulator write-back operation functions in the

same manner, addressing combined MCU (X and Y)

data space though the X bus. For this class of

instructions, the data is always subject to rounding.

dsPIC30F2011/2012/3012/3013

2.4.2.4 Data Space Write Saturation

In addition to adder/subtracter saturation, writes to data

space may also be saturated but without affecting the

contents of the source accumulator. The data space

write saturation logic block accepts a 16-bit, 1.15

fractional value from the round lo gic block as its input,

together with overflow status from the original source

(accumulator) and the 16-bit round adder. These are

combined and used to select the appropriate 1.15

fractional value as output to write to data space

memory.

If the SATDW bit in th e CORCON register is set, data

(after rounding or truncation) is tested for overflow and

adjusted accordingly. For input data greater than

0x007FFF, data written to memory is forced to the

maximum positive 1.15 value, 0x7FFF. For input data

less than 0xFF8000, data written to memory is forced

to the maximum negative 1.15 value, 0x8000. The MSb

of the source (bit 39) is used to determine the sign of

the operand bei ng tested.

If the SATDW bit in the CORCON register is not set, the

input data is always passed through unmodified under

all conditions.

2.4.3 BARREL SHIFTER

The barrel shifter is capable of performing up to 16-bit

arithmetic or logic right shifts, or up to 16-bit left shifts

in a single cycle. The source can be either of the two

DSP accumulators, or the X bus (to support multi-bit

shifts of register or memory data).

The shifter requires a signed binary value to determine

both the magnitude (number of bits) and direction of the

shift operation. A positive value shifts the operand right.

A negative value shifts the operand left. A value o f ‘0’

does not modify the operand.

The barrel shifter is 40 bits wide, thereby obtaining a

40-bit result for DSP shift operations and a 16-bit result

for MCU shift operations. Data from the X bus is

presented to the barrel shifter between bit positions 16

to 31 for right shifts, and bit positions 0 to 16 for left

shifts.

dsPIC30F2011/2012/3012/3013

NOTES:

dsPIC30F2011/2012/3012/3013

3.0 MEMORY ORGANIZATION

3.1 Program Address Space

The program address space is 4M instruction words.

The program space memory maps for the

dsPIC30F2011/2012/3012/3013 devices is shown in

Figure 3-1.

Program memory is addressable by a 24-bit value from

either the 23-bit PC, table instruction Effective Address

(EA), or data space EA, when program space is

mapped into data space as defined by Table 3-1. Note

that the program space address is incremented by two

between successive program words in order to provide

compatibility with data space addressing.

User program space access is restricted to the lower

4M instruction word address range (0x000000 to

0x7FFFFE) for all accesses other than TBLRD/TBLWT,

which uses TBLPAG<7> to determine user or con figu-

ration space access. In Table 3-1, Program Space

Address Construction, bit 23 allows access to the

Device ID, the User ID and the Configuration bits.

Otherwise, bit 23 is always clear.

Note: This data sheet summarizes features of

this group of dsPIC30F devices and is not

intended to be a complete reference

source. For more information on the CPU,

peripherals, register descriptions and

general device functionality, refer to the

“dsPIC30F Family Reference Manual”

(DS70046). For more information on the

device instruction set and programming,

refer to the “16-bit MCU and DSC

Programmer’s Reference Manual”

(DS70157).

dsPIC30F2011/2012/3012/3013

FIGURE 3-1: PROGRAM SPACE MEMORY MAPS

Reset - Target Address

User Memory

Space

000000

00007E

000002

000080

Device Configuration

User Flash

Program Memory

002000

001FFE

Configuration Memory

Space

(4K instructions)

800000

F80000

Registers F8000E

F80010

DEVID (2) FEFFFE

FF0000

FFFFFE

Reserved F7FFFE

Reserved

(Read ‘0’s)

8005FE

800600

UNITID (32 instr.)

Vector Tables

8005BE

8005C0

Reset - GOTO Instruction

000004

Reserved

7FFFFE

Reserved

000100

0000FE

000084

Alternate Vector Table

Reserved

Interrupt Vector Table

Reset - Target Address

User Memory

Space

000000

00007E

000002

000080

Device Configuration

User Flash

Program Memory

004000

003FFE

Configuration Memory

Space

Data EEPROM

(8K instructions)

(1 Kbyte)

800000

F80000

Registers F8000E

F80010

DEVID (2) FEFFFE

FF0000

FFFFFE

Reserved F7FFFE

Reserved

7FFC00

7FFBFE

(Read ‘0’s)

8005FE

800600

UNITID (32 instr.)

Vector Tables

8005BE

8005C0

Reset - GOTO Instruction

000004

Reserved

7FFFFE

Reserved

000100

0000FE

000084

Alternate Vector Table

Reserved

Interrupt Vector Table

dsPIC30F2011/2012 dsPIC30F3012/3013

dsPIC30F2011/2012/3012/3013

TABLE 3-1: PROGRAM SPACE ADDRESS CONSTRUCTION

FIGURE 3-2: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION

Access Type Access

Space Program Space Address

<23> <22:16> <15> <14:1> <0>

Instruction Access User 0PC<22:1> 0

TBLRD/TBLWT User

(TBLPAG<7> = 0)TBLPAG<7:0> Data EA<15:0>

TBLRD/TBLWT Configuration

(TBLPAG<7> = 1)TBLPAG<7:0> Data EA<15:0>

Program Space Visibility User 0PSVPAG<7:0> Data EA<14:0>

0Program Counter

23 bits

PSVPAG Reg

8 bits

15 bits

Program

Using

Select

TBLPAG Reg

8 bits

16 bits

Using

Byte

24-bit EA

1/0

Select

User/

Configuration

Table

Instruction

Program

Space

Counter

Using

Space

Select

Visibility

Note: Program space visibility cannot be used to access bits <23:16> of a word in program memory .

dsPIC30F2011/2012/3012/3013

3.1.1 DATA ACCESS FROM PROGRAM

MEMORY USING TABLE

INSTRUCTIONS

This architecture fetches 24-bit wide program memory.

Consequently, instructions are always aligned.

However, as the architecture is modified Harvard, data

can also be present in program space.

There are two methods by which program space can

be accessed: via special table instructions, or through

the remapping of a 16K word program space page into

the upper half of data space (see Section 3.1.2 “Data

Access from Program Memory Using Program

Space Visibility”). The TBLRDL and TBLWTL

instructions offer a direct method of reading or writing

the lsw of any address within program space, without

going through data space. The TBLRDH and TBLWTH

instructions are the only metho d whereby the upper 8

bits of a program space word can be accessed as data.

The PC is incremented by two for each successive

24-bit program word. This allows program memory

addresses to directly map to data space addresses.

Program memory can thus be regarded as two 16-bit

word wide address spaces, residing side by side, each

with the same address range. TBLRDL and TBLWTL

access the space which contains the lsw, and TBLRDH

and TBLWTH access the space which contains the

MSB.

Figure 3-2 shows how the EA is created for table

operations and data space accesses (PSV = 1). Here,

P<23:0> refers to a program space word, whereas

D<15:0> refers to a data space word.

A set of table instructions are provided to move byte or

word-sized data to and from program space. See

Figure 3-4 and Figure 3-5.

1. TBLRDL: Table Read Low

Word: Read the LS W ord of the program address;

P<15:0> maps to D<15:0>.

Byte: Read one of the LSB of the program

address;

P<7:0> maps to the destination byte when byte

select = 0;

P<15:8> maps to the destination byte when byte

select = 1.

2. TBLWTL: Table Write Low (refer to Section 5.0

“Flash Program Memory” for details on Flash

Programming)

3. TBLRDH: Table Read High

Word: Read the MS Word of the program address;

P<23:16> maps to D<7:0>; D<15:8> will always

be = 0.

Byte: Read one of the MSB of the program

address;

P<23:16> maps to the destination byte when

byte select = 0;

The destination byte will always be = 0 when

byte select = 1.

4. TBLWTH: Table Write High (refer to Section 5.0

“Flash Program Memory” for details on Flash

Programming)

FIGURE 3-3: PROGRAM DATA TABLE ACCESS (lsw)

PC Address

0x000000

0x000002

0x000004

0x000006

00000000

Program Memory

‘Phantom’ Byte

(read as ‘0’)

TBLRDL.W

TBLRDL.B (Wn<0> = 1)

TBLRDL.B (Wn<0> = 0)

dsPIC30F2011/2012/3012/3013

FIGURE 3-4: PROGRAM DATA TABLE ACCESS (MSB)

3.1.2 DATA ACCESS FROM PROGRAM

MEMORY USING PROGRAM SPACE

VISIBILITY

The upper 32 Kbytes of data space may optionally be

mapped into any 16K word progra m space page. This

provides transparent access of stored constant data

from X data space without the need to use special

instructions (i.e., TBLRDL/H, TBLWTL/H instructions).

Program space access through the data space occurs

if the MSb of the data space EA is set and program

space visibility is enabled by setting the PSV bit in the

Core Control register (CORCON). The functions of

CORCON are discussed in Section 2.4 “DSP

Engine”.

Data accesses to this area add an additional cycle to

the instruction being executed, since two program

memory fetches are required.

Note that the upper half of addressable data space is

always part of the X data space. Therefore, when a

DSP operation uses program space mapping to access

this memory region, Y data space should typically

contain state (variable) data for DSP operations,

whereas X data space should typically contain

coefficient (constant) data.

Although each data space address, 0x8000 and higher ,

maps directly into a corresponding program memory

address (see Figure 3-5), only the lower 16 bits of the

24-bit program word are used to contain the data. The

upper 8 bits should be programmed to force an illegal

instruction to maintain machine robustness. Refer to

the “16-bit MCU and DSC Programmer’s Reference

Manual” (DS70157) for details on instruction encoding.

Note that by incrementing the PC by 2 for each

program memory word, the LS 15 bits of data space

addresses directly map to the LS 15 bits in the

corresponding program space addresses. The

remaining bits are provided by the Program Space

Visibility Page register, PSVPAG<7:0>, as shown in

Figure 3-5.

For instructions that use PSV which are executed

outside a REPEAT loop:

• The following instruction s require one instruction

cycle in addition to the specified execution time:

-MAC class of instructions with data operand

prefetch

-MOV instruction s

-MOV.D instructions

• All other instructions require two instruction cycles

in addition to the specified execution time of the

instruction.

For instructions that use PSV which are executed

inside a REPEAT loop:

• The following instances require two instruction

cycles in addition to the specified execution time

of the instruction:

- Execution in the first iteration

- Execution in the last iteration

- Execution pr ior to exiting the loop due to an

interrupt

- Execution upon re-entering the loop after an

interrupt is serviced

• Any other iteration of the REPEAT loop allow the

instruction accessing data, using PSV, to execute

in a single cycle.

PC Address

0x000000

0x000002

0x000004

0x000006

00000000

Program Memory

‘Phantom’ Byte

(read as ‘0’)

TBLRDH.W

TBLRDH.B (Wn<0> = 1)

TBLRDH.B (Wn<0> = 0)

Note: PSV access is temporarily disabled during

table reads/writes.

dsPIC30F2011/2012/3012/3013

FIGURE 3-5: DATA SPACE WINDOW INTO PROGRAM SPACE OPERATION

23 15 0

PSVPAG(1)

EA<15> =

EA<15> = 1

Data

Space

Data Space Program Space

15 23

0x0000

0x8000

0xFFFF

0x00

0x001FFF

Dat a Read

Upper Half of Data

Space is Mapped

into Program Space

0x001200

Address

Concatenation

BSET CORCON,#2 ; Set PSV bit

MOV #0x0, W0 ; Set PSVPAG register

MOV W0, PSVPAG

MOV 0x9200, W0 ; Access program memory location

; using a data space access

Note 1: PSVPAG is an 8-bit register, containing bits <22:15> of the program space address.

0x000000

dsPIC30F2011/2012/3012/3013

3.2 Data Address Space

The core has two data spaces. The data spaces can be

considered either separate (for some DSP

instructions), or as one unified linear address range (for

MCU instructions). The data spaces are accessed

using two Address Generation Units (AGUs) and

separate data paths.

3.2.1 DATA SPACE MEMORY MAP

The data space memory is split into two blocks, X and

Y data space. A key element of this architecture is that

Y space is a subset of X space, and is fully contained

within X space. In order to provide an apparent Linear

Addressing space, X and Y spaces have contiguous

addresses.

When executing any instruction other than one of the

MAC class of instructions, the X block consists of the 64

Kbyte data address space (including all Y addresse s).

When executing one of the MAC class of instructions,

the X block consists of the 64 Kbyte data address

space, excluding the Y address block (for data reads

only). In other words, all other instructions regard the

entire data memory as one comp osite address space.

The MAC class instructions extract the Y address space

from data space and address it using EAs sourced from

W10 and W11. The remaining X data space is

addressed using W8 and W9. Both address spaces are

concurrently accessed only with the MAC class

instructions.

The data space memory map for the dsPIC30F2011

and dsPIC30F2012 is shown in Figure 3-6. The data

space memory map for the dsPIC30F3012 and

dsPIC30F3013 is shown in Figure 3-7.

FIGURE 3-6: dsPIC30F2011/2012 DATA SPACE MEMORY MAP

0x0000

0x07FE

0x09FE

0xFFFE

LSB

Address

16 bits

LSBMSB

MSB

Address

0x0001

0x07FF

0x09FF

0xFFFF

0x8001 0x8000

Optionally

Mapped

into Program

Memory

0x0BFF 0x0BFE

0x0C000x0C01

0x0801 0x0800

0x0A01

0x0A00

Near

Data

0x1FFE 0x1FFF

2 Kbyte

SFR Space

1 Kbyte

SRAM Space

8 Kbyte

Space

X Data

Unimplemented (X)

SFR

Space

X Data RAM (X)

Y Data RAM (Y)

dsPIC30F2011/2012/3012/3013

FIGURE 3-7: dsPIC30F3012/3013 DATA SPACE MEMORY MAP

0x0000

0x07FE

0x0BFE

0xFFFE

LSB

Address

16 bits

LSBMSB

MSB

Address

0x0001

0x07FF

0x0BFF

0xFFFF

0x8001 0x8000

Optionally

Mapped

into Program

Memory

0x0FFF 0x0FFE

0x10000x1001

0x0801 0x0800

0x0C01

0x0C00

Near

Data

0x1FFE 0x1FFF

2 Kbyte

SFR Space

2 Kbyte

SRAM Space

8 Kbyte

Space

X Data

Unimplemented (X)

SFR Space

X Data RAM (X)

Y Data RAM (Y)

dsPIC30F2011/2012/3012/3013

FIGURE 3-8: DATA SPACE FOR MCU AND DSP (MAC CLASS) INSTRUCTIONS EXAMPLE

SFR SPACE

(Y SPACE)

X SPACE

SFR SPACE

UNUSED

X SP ACE

Y SP ACE

UNUSED

Non-MAC Class Ops (Read/Write) MAC Class Ops (Read)

Indirect EA using any W Indirect EA using W8, W9 Indirect EA using W10, W11

MAC Class Ops (Write)

dsPIC30F2011/2012/3012/3013

3.2.2 DATA SPACES

The X data space is used by all instructions and sup-

ports all addressing modes. There are separate read

and write data buses. The X read data bus is the return

data path for all instructions that view data space as

combined X and Y address space. It is also the X

address space data path for the dual operand read

instructions (MAC class). The X write data bus is the

only write path to data space for all instructions.

The X data space also supports Modulo Addressing for

all instructions, subject to Addressing mode restric-

tions. Bit-Reversed Addressing is only supported for

writes to X data space.

The Y data space is used in concert with the X data

space by the MAC class of instructions (CLR, ED,

EDAC, MAC, MOVSAC, MPY, MPY.N and MSC) to

provide two concurrent data read paths. No writes

occur across the Y bus. This class of instructions

dedicates two W register pointers, W10 and W11, to

always address Y data space, independent of X data

space, whereas W8 and W9 always address X data

space. Note that during accumulator write back, the

data address space is considered a combination of X

and Y data spaces, so the write occurs across the X

bus. Consequently, the wri te can be to any address in

the entire data space.

The Y data space can only be used for the data

prefetch operation associated with the MAC class of

instructions. It also supports Modulo Addressing for

automated circular buffers. Of course, all other

instructions can access the Y data address space

through the X data path as part of the composite linear

space.

The boundary between the X and Y data spaces is

defined as shown in Figure 3-7 and is not user

programmable. Should a n EA point to data outside its

own assigned address space, or to a location outside

physical memory, an all zero word/byte is returned. For

example, although Y address space is visible by all

non-MAC instructions using any addressing mode, an

attempt by a MAC instruction to fetch data from that

space using W8 or W9 (X space pointers)

returns 0x0000.

TABLE 3-2: EFFECT OF INVALID

MEMORY ACCESSES

All Effective Addresses are 16 bits wide and point to

bytes within the data space. Therefore, the data space

address range is 64 Kbytes or 32K words.

3.2.3 DATA SPACE WIDTH

The core data width is 16 bits. All internal registers are

organized as 16-bit wide words. Data space memory is

organized in byte addressable, 16-bit wide blocks.

3.2.4 DATA ALIGNMENT

To help maintain backward compatibility with

PIC®MCU devices and improve data space memory

usage efficiency, the dsPIC30F instruction set supports

both word and byte operations. Data is aligned in data

memory and registers as words, but all data space EAs

resolve to bytes. Data byte reads read the complete

word that contains the byte, using the LSb of any EA to

determine which byte to select. The selected byte is

placed onto the LSB of the X data path (no byte

accesses are possible from the Y data path as the MAC

class of instruction can only fetch words). That is, data

memory and registers are organized as two parallel

byte wide entities with shared (word) address decode

but separate write lines. Data byte writes only write to

the corresponding side of the array or register which

matches the byte address.

As a consequence of this byte accessibility , all Effective

Address calcul ations (including those generated by the

DSP operations which are restricted to word-sized

data) are internally scaled to step through word-aligned

memory. For example, the core would recognize that

Post-Modified Register Indirect Addressing mode

[Ws++] results in a value of Ws + 1 for byte operations

and Ws + 2 for word operations.

All word accesses must be aligned to an even address.

Misaligned word data fetches are not supported, so

care should be taken when mixing byte and word

operations, or translating from 8-bit MCU code. Should

a misaligned read or write be attempted, an address

error trap is generated. If th e error occurred on a read,

the instruction underway is completed, whereas if it

occurred on a write, the instruction is executed, but the

write does not occur. In either case, a trap is then

executed, allowing the system and/or user to examine

the machine state prior to execution of the address

fault.

FIGURE 3-9: DATA ALIGNMENT

Attempted Operation Data Returned

EA = an unimplemented address 0x0000

W8 or W9 used to access Y data

space in a MAC instruction 0x0000

W10 or W11 used to access X

data space in a MAC instr uction 0x0000

15 8 7 0

0001

0003

0005

0000

0002

0004

Byte 1 Byte 0

Byte 3 Byte 2

Byte 5 Byte 4

LSBMSB

dsPIC30F2011/2012/3012/3013

All byte loads into any W register are loaded into the

LSB. The MSB is not modified.

A Sign-Extend (SE) instruction is provided to allow

users to translate 8-bit signed data to 16-bit signed

values. Alternatively, for 16-bit unsigned data, users

can clear the MSB of any W register by executing a

Zero-Extend (ZE) instruction on the appropriate

address.

Although most instructions are capable of operating on

word or byte data sizes, it should be noted that some

instructions, including the DSP instructions, operate

only on words.

3.2.5 NEAR DATA SPACE

An 8 Kbyte near data space is reserved in X address

memory space between 0x0000 and 0x1FFF, which is

directly addressable via a 13-bit absolute address field

within all memory direct instructions. The remaining X

address space and all of the Y address space is

addressable indirectly . Additionally, the whole of X data

space is addressable using MOV instructions, which

support memory direct addressing with a 16-bit

address field.

3.2.6 SOFTWARE STACK

The dsPIC DSC devices contain a software stack. W15

is used as the Stack Pointer.

The Stack Pointer always points to the first available

free word and grows from lower addresses towards

higher addresses. It pre-decrements for stack pops

and post-increments for stack pushes, as shown in

Figure 3-10. Note that for a PC push during any CALL

instruction, the MSB of the PC is zero-extended before

the push, ensuring that the MSB is always clear.

FIGURE 3-10: CALL STACK FRAME

There is a Stack Pointer Limit register (SPLIM)

associated with the Stack Pointer. SPLIM is

uninitialized at Reset. As is the case for the Stack

Pointer, SPLIM<0> is forced to ‘0’ because all stack

operations must be word aligned. Whenever an

Effective Address (EA) is generated using W15 as a

source or destination pointer, the address thus

generated is compared with the value in SPLIM. If the

contents of the Stack Pointer (W15) and the SPLIM reg-

ister are equal, and a push operation is performed, a

stack error trap does not occur. The stack error trap

occurs on a subsequent push operation. Thus, for

example, if it is desirable to cause a stack error trap

when the stack grows beyond address 0x2000 in RAM,

initialize the SPLIM with the value, 0x1FFE.

Similarly, a S tack Pointer underflow (stack error) trap is

generated when the Stack Pointer address is found to

be less than 0x0800, thus preventing the stack from

interfering with the Special Function Register (SFR)

space.

A write to the SPLIM register should not be immediately

followed by an indirect read operation usi ng W15.

Note: A PC push during exception processing

concatenates the SRL register to the MSB

of the PC prior to the push.

PC<15:0>

000000000

015

W15 (before CALL)

W15 (after CALL)

Stack Grows Towards

Higher Address

0x0000

PC<22:16>

POP : [--W15]

PUSH : [W15++]

dsPIC30F2011/2012/3012/3013

TABLE 3-3: CORE REGISTER MAP

SFR Name Address

(Home) Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

W0 0000 W0/WREG 0000 0000 0000 0000

W1 0002 W1 0000 0000 0000 0000

W2 0004 W2 0000 0000 0000 0000

W3 0006 W3 0000 0000 0000 0000

W4 0008 W4 0000 0000 0000 0000

W5 000A W5 0000 0000 0000 0000

W6 000C W6 0000 0000 0000 0000

W7 000E W7 0000 0000 0000 0000

W8 0010 W8 0000 0000 0000 0000

W9 0012 W9 0000 0000 0000 0000

W10 0014 W10 0000 0000 0000 0000

W11 0016 W11 0000 0000 0000 0000

W12 0018 W12 0000 0000 0000 0000

W13 001A W13 0000 0000 0000 0000

W14 001C W14 0000 0000 0000 0000

W15 001E W15 0000 1000 0000 0000

SPLIM 0020 SPLIM 0000 0000 0000 0000

ACCAL 0022 ACCAL 0000 0000 0000 0000

ACCAH 0024 ACCAH 0000 0000 0000 0000

ACCAU 0026 Sign Extension (ACCA<39>) ACCAU 0000 0000 0000 0000

ACCBL 0028 ACCBL 0000 0000 0000 0000

ACCBH 002A ACCBH 0000 0000 0000 0000

ACCBU 002C Sign Extension (ACCB<39>) ACCBU 0000 0000 0000 0000

PCL 002E PCL 0000 0000 0000 0000

PCH 0030 — — — — — — — — —PCH0000 0000 0000 0000

TBLPAG 0032 — — — — — — — —TBLPAG0000 0000 0000 0000

PSVPAG 0034 — — — — — — — — PSVPAG 0000 0000 0000 0000

RCOUNT 0036 RCOUNT uuuu uuuu uuuu uuuu

DCOUNT 0038 DCOUNT uuuu uuuu uuuu uuuu

DOSTARTL 003A DOSTARTL 0uuuu uuuu uuuu uuu0

DOSTARTH 003C — — — — — — — — —DOSTARTH0000 0000 0uu u uuuu

DOENDL 003E DOENDL 0uuuu uuuu uuuu uuu0

DOENDH 0040 — — — — — — — — — DOENDH 0000 0000 0uuu uuuu

SR 0042 OA OB SA SB OAB SAB DA DC IPL2 IPL1 IPL0 RA N OV Z C 0000 0000 0000 0000

Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’

Note: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.

dsPIC30F2011/2012/3012/3013

CORCON 0044 — — — US EDT DL2 DL1 DL0 SATA SATB SATDW ACCSAT IPL3 PSV RND IF 0000 0000 0010 0000

MODCON 0046 XMODEN YMODEN —— BWM<3:0> YWM<3:0> XWM<3:0> 0000 0000 0000 0000

XMODSRT 0048 XS<15:1> 0 uuuu uuuu uuu u uuu0

XMODEND 004A XE<15:1> 1 uuuu uuuu uuu u uuu1

YMODSRT 004C YS<15:1> 0 uuuu uuuu uuu u uuu0

YMODEND 004E YE<15:1> 1 uuuu uuuu uuu u uuu1

XBREV 0050 BREN XB<14:0> uuuu uuuu uuuu uuuu

DISICNT 0052 —— DISICNT<13:0> 0000 0000 0000 0000

TABLE 3-3: CORE REGISTER MAP (CONTINUED)

SFR Name Address

(Home) Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’

Note: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.

dsPIC30F2011/2012/3012/3013

NOTES:

dsPIC30F2011/2012/3012/3013

4.0 ADDRESS GENERATOR UNITS

The dsPIC DSC core contains two independent

address generator units: the X AGU and Y AGU. The Y

AGU supports word-sized data reads for the DSP MAC

class of instructions only. The dsPIC DSC AGUs

support three types of data addressing:

• Linear Addressing

• Modulo (Circular) Addressing

• Bit-Reversed Addressing

Linear and Modulo Data Addressing modes can be

applied to data space or program space. Bit-Reversed

Addressing is only applicable to data space addresses.

4.1 Instruction Addressing Modes

The addressing modes in Table 4-1 form the basis of

the addressing modes optimized to support the specific

features of individual instructions. The addressing

modes provided in the MAC class of instructions are

somewhat different from those in the other instruction

types.

4.1.1 FILE REGISTER INSTRUCTIONS

Most file register instructions use a 13-bit address field

(f) to directly address data present in the first 8192

bytes of data memory (near data space). Most file

which is denoted as WREG in these instructions. The

destination is typically either the same file register or

WREG (with the exception of the MUL instruction),

which writes the result to a regist er or register p air. The

MOV instruction allows additional flexibility and can

access the entire data space during file register

operation.

4.1.2 MCU INSTRUCTIONS

The three-operand MCU instructions are of the form:

Operand 3 = Operand 1 <function> Operand 2

where Operand 1 is always a working register (i.e., the

addressing mode can only be reg ister direct), which is

referred to as Wb. Operand 2 can be a W register,

fetched from data memory or a 5-bit literal. The result

location can be either a W register or an address

location. The following addressing modes are

supported by MCU instructions:

• Register Direct

• Register Indirect

• Register Indirect Post-modified

• Register Indirect Pre-modified

• 5-bit or 10-bit Literal

TABLE 4-1: FUNDAMENTAL ADDRESSING MODES SUPPORTED

Note: This data sheet summarizes features of

this group of dsPIC30F devices and is not

intended to be a complete reference

source. For more information on the CPU,

peripherals, register descriptions and

general device functionality, refer to the

“dsPIC30F Family Reference Manual”

(DS70046). For more information on the

device instruction set and programming,

refer to the “16-bit MCU and DSC

Programmer’s Reference Manual”

(DS70157).

Note: Not all instructions support all the

addressing modes given above. Individual

instructions may support different subsets

of these addressing mode s.

Addressing Mode Description

File Register Direct The address of the File register is specified explici tl y.

decremented) by a constant value.

to form the EA.

dsPIC30F2011/2012/3012/3013

4.1.3 MOVE AND ACCUMULATOR

INSTRUCTIONS

Move instructions and the DSP accumulator class of

instructions provide a greater degree of addressing

flexibility than other instructions. In addition to the

addressing modes supported by most MCU

instructions, move and accumulator instructions also

support Register Indirect with Register Offset

Addressing mode, also referred to as Register Indexed

mode.

In summary, the following addressing modes are

supported by move and accumulator instructions:

• Register Direct

• Register Indirect

• Register Indirect Post-modified

• Register Indirect Pre-modified

• Register Indirect with Register Offset (Indexed)

• Register Indirect with Litera l Offset

• 8-bit Literal

• 16-bit Lite ral

4.1.4 MAC INSTRUCTIONS

The dual source operand DSP instructions (CLR, ED,

EDAC, MAC, MPY, MPY.N, MOVSAC and MSC), also

referred to as MAC instructions, utilize a simplified set of

addressing modes to allow the user to effectively

manipulate the data pointers through register indirect

tables.

The two source operand prefetch registers must belong

to the set {W8, W9, W10, W11}. For data reads, W8

and W9 are always dire cted to the X RAGU. W10 and

W11 are always directed to the Y AGU. The effective

addresses generated (before and after modification)

must, therefore, be valid addresses within X data space

for W8 and W9 and Y data space for W10 and W11.

In summary, the following addressing modes are

supported by the MAC class of instructions:

• Register Indirect

• Register Indirect Post-modified by 2

• Register Indirect Post-modified by 4

• Register Indirect Post-modified by 6

• Register Indirect with Register Offset (Indexed)

4.1.5 OTHER INSTRUCTIONS

Besides the various addressing modes outlined above,

some instructions use literal constants of various sizes.

For example, BRA (branch) instructions use 16-bit

signed literals to specify the branch destination directly ,

whereas the DISI instruction uses a 14-bit unsigned

literal field. In some instructions, such as ADD Acc, the

source of an operand or result is implied by the opcode

itself. Certain operations, such as NOP, do not have any

operands.

4.2 Modulo Addressing

Modulo Addressing is a method of providing an

automated means to support circular data buffers using

hardware. The objective is to remove the need for

software to perform data address boundary checks

when executing tightly looped code, as is typical in

many DSP algorithms.

Modulo Addressing can operate in either data or

program space (since the data pointer mechanism is

essentially the same for both). One circular buffer can

be supported in each of the X (which also provides the

pointers into program space) and Y data spaces.

Modulo Addressing can operate on any W register

pointer. However, it is not advisable to use W14 or W15

for Modulo Addressing since these two registers are

used as the Stack Frame Pointer and Stack Pointer,

respectively.

In general, any particular circular buffer can only be

configured to operate in one direction, as there are

certain restrictions on the buffer Start address

(for incrementing buffers), or end address

(for decrementing buffers) based upon the direction of

the buffer.

The only exception to the usage restrictions is for

buffers that have a power-of-2 length. As these buffers

satisfy the Start and the end address criteria, they can

operate in a Bidirectional mode (i.e., address boundary

checks are performed on both the lower and upper

address boundaries).

Note: For the MOV instructions, the addressing

mode specified in the instruction can differ

for the source and destination EA.

However, the 4-bit Wb (register offset)

field is shared between both source and

destination (but typically only used by

one).

Note: Not all instructions support all the

addressing modes given above. Individual

instructions may support different subsets

of these addressing modes.

Note: Register Indirect with Register Offset

addressing is only available for W9 (in X

space) and W11 (in Y space).

dsPIC30F2011/2012/3012/3013

4.2.1 START AND END ADDRESS

The Modulo Addressing scheme requires that a

starting and an ending address be specified and loaded

into the 16-bit Modulo Buffer Address registers:

XMODSRT, XMODEND, YMODSRT and YMODEND

(see Table 3-3).

The length of a circular buffer is not directly specified. It

is determined by the difference between the

corresponding S tart and end addresses. The maximum

possible length of the circular buffer is 32K words

(64 Kbytes).

4.2.2 W ADDRESS REGISTER

SELECTION

The Modulo and Bit-Reversed Addressing Control

well as a W register field to specify the W address

registers. The XWM and YWM fields select which

registers operate with Modulo Addressing.

If XWM = 15, X RAGU and X WAGU Modulo

Addressing is disabled. Similarly, if YWM = 15, Y AGU

Modulo Addressing is disabled.

The X Address Space Pointer W register (XWM), to

which Modulo Addressing is to be appli ed, is stored in

MODCON<3:0> (see Table 3-3). Modulo Addressing is

enabled for X data space when XWM is set to any value

other than ‘15’ and the XMODEN bit is set at

MODCON<15>.

The Y Address Space Pointer W register (YWM), to

which Modulo Addressing is to be appli ed, is stored in

MODCON<7:4>. Modulo Addressing is enabled for Y

data space when YWM is set to any value other

than ‘15’ and the YMODEN bit is set at

MODCON<14>.

FIGURE 4-1: MODULO ADDRESSING OPERATION EXAMPLE

Note: Y space Modulo Addressing EA

calculations assume word-sized data

(LSb of every EA is always clear).

0x1100

0x1163

Start Addr = 0x1100

End Addr = 0x1163

Length = 0x0032 words

Byte

Address MOV #0x1100,W0

MOV W0,XMODSRT ;set modulo start address

MOV #0x1163,W0

MOV W0,MODEND ;set modulo end address

MOV #0x8001,W0

MOV W0,MODCON ;enable W1, X AGU for modulo

MOV #0x0000,W0 ;W0 holds buffer fill value

MOV #0x1110,W1 ;point W1 to buffer

DO AGAIN,#0x31 ;fill the 50 buffer locations

MOV W0,[W1++] ;fill the next location

AGAIN: INC W0,W0 ;increment the fill value

dsPIC30F2011/2012/3012/3013

4.2.3 MODULO ADDRESSING

APPLICABILITY

Modulo Addressing can be applied to the Effective

Address (EA) calculation associated with any W

boundaries check for addresses less than, or greater

than the upper (for incrementing buffers), and lower (for

decrementing buffers) boundary addresses (not just

equal to). Address changes may, therefore, jump

beyond boundaries and still be adjusted correctly.

4.3 Bit-Reversed Addressing

Bit-Reversed Addressing is intended to simplify data

re-ordering for radix-2 FFT algorithms. It is supported

by the X AGU for data writes only.

The modifier, which may be a constant value or register

contents, is regarded as having its bit order reversed. The

address source and destination are kep t in normal order.

Thus, the only operand requiring reversa l is the modifier.

4.3.1 BIT-REVERSED ADDRESSING

IMPLEMENTATION

Bit-Reversed Addressing is enabled when:

• BWM (W register selection) in the MODCON reg-

ister is any val ue other than ‘15’ (the st ack cannot

be accessed using Bit-Reversed Addressing)

and

• The BREN bit is set in the XBREV register

and

• The addressing mode used is Register Indirect

with Pre-Increment or Post-Increment.

If the length of a bit-reversed buffer is M = 2N bytes,

then the last ‘N’ bits of the data buffer Start address

must be zeros.

XB<14:0> is the bit-reversed address modifier or ‘pivot

point’ which is typically a constant. In the case of an

FFT computation, its value is equal to half of the FFT

data buffer size.

When enabled, Bit-Reversed Addressing is only

executed for register indirect with pre-increment or

post-increment addressing and word-sized data writes.

It does not function for any other addressing mode or

for byte-sized data. Normal addresses are generated

instead. When Bit-Reversed Addressing is active, the

W address pointer is always added to the address

modifier (XB) and the offset associated with the

addition, as word-sized data is a requirement, the LSb

of the EA is ignored (and always clear).

If Bit-Reversed Addressing has already been enabled

by setting the BREN bit (XBREV<15>), then a write to

the XBREV register should not be immediately followed

by an indirect read operation using the W reg ister that

has been designated as the bit-reversed pointer.

Note: The modulo corrected Effective Address

is written back to the register only when

Pre-Modify or Post-Modify Addressing

mode is used to compute the EA. When

an address offset (e.g., [W7+W2]) is used,

Modulo address correction is performed,

but the contents of the register remain

unchanged.

Note: All bit-reversed EA calculations assume

word-sized data (LSb of every EA is

always clear). The XB value is scaled

accordingly to generate compatible (byte)

addresses.

Note: Modulo Addressing and Bit-Reversed

Addressing should not be enabled

together. In the event that the user

attempts to do this, Bit-Re versed Address-

ing assumes priority when active for the X

WAGU, and X WAGU Modulo Addressing

is disabled. However, Modulo Addressing

continues to function in the X RAGU.

dsPIC30F2011/2012/3012/3013

FIGURE 4-2: BIT-REVERSED ADDRESS EXAMPLE

TABLE 4-2: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY)

TABLE 4-3: BIT-REVERSED ADDRESS MODIFIER VALUES FOR XBREV REGISTER

Normal Address Bit-Reversed Address

A3 A2 A1 A0 Decimal A3 A2 A1 A0 Decimal

0000 00000 0

0001 11000 8

0010 20100 4

0011 31100 12

0100 40010 2

0101 51010 10

0110 60110 6

0111 71110 14

1000 80001 1

1001 91001 9

1010 10 0101 5

1011 11 1101 13

1100 12 0011 3

1101 13 1011 11

1110 14 0111 7

1111 15 1111 15

Buffer Size (Words) XB<14:0> Bit-Reversed Address Mo difier Value

1024 0x0200

512 0x0100

256 0x0080

128 0x0040

64 0x0020

32 0x0010

16 0x0008

8 0x0004

4 0x0002

2 0x0001

b3 b2 b1 0

b2 b3 b4 0

Bit Locations Swapped Left-to-Right

Around Center of Binary Value

Bit-Reversed Address

XB = 0x0008 for a 16-word Bit-Reversed Buffer

b7 b6 b5 b1

b7 b6 b5 b4b11 b10 b9 b8

b11 b10 b9 b8

b15 b14 b13 b12

Sequential Address

Pivot Point

dsPIC30F2011/2012/3012/3013

NOTES:

dsPIC30F2011/2012/3012/3013

5.0 FLASH PROGRAM MEMORY

The dsPIC30F family of devices contains internal

program Flash memory for executing user code. There

are two methods by which the user can program this

memory:

1. Run-T ime Self-Programming (RTSP)

2. In-Circuit Serial Programming™ (ICSP™)

5.1 In-Circuit Seria l Programming

(ICSP)

dsPIC30F devices can be serially programmed while in

the end application circuit. This is simply done with two

lines for Programming Clock and Programming Data

(which are named PGC and PGD respectively), and

three other lines for Power (VDD), Ground (VSS) and

Master Clear (MCLR). This allows customers to

manufacture boards with unprogrammed de vices, and

then program the microcontroller just before shipping

the product. This also allows the mo st recent firmwa re

or a custom firmware to be programmed.

5.2 Run-Time Self-Programming

(RTSP)

RTSP is accomplished using TBLRD (table read) and

TBLWT (table write) instructions.

With RTSP, the user may erase program memory, 32

instructions (96 byt es) at a time and can write program

memory data, 32 instructions (96 bytes) at a time.

5.3 Table Instruction Operation

Summary

The TBLRDL and the TBLWTL instructions are used to

read or write to bits<15:0> of program memory.

TBLRDL and TBLWTL can access program memory in

Word or Byte mode.

The TBLRDH and TBLWTH instructions are used to read

or write to bits<23:16> of program memory. TBLRDH

and TBLWTH can access program memory in Word or

Byte mode.

A 24-bit program memory address is formed using

bits<7:0> of the TBLPAG register and the Effective

Address (EA) from a W register specified in the table

instruction, as shown in Figure 5-1.

FIGURE 5-1: ADDRESSING FOR TABLE AND NVM REGISTERS

Note: This data sheet summarizes features of

this group of dsPIC30F devices and is not

intended to be a complete reference

source. For more information on the CPU,

peripherals, register descriptions and

general device functionality, refer to the

“dsPIC30F Family Reference Manual”

(DS70046). For more information on the

device instruction set and programming,

refer to the “16-bit MCU and DSC

Programmer’s Reference Manual”

(DS70157).

Program Counter

24 bits

NVMADRU Reg

8 bits 16 bits

Program

Using

TBLPAG Reg

8 bits

Working Reg EA

16 bits

Using

Byte

24-bit EA

1/0

Select

Table

Instruction

NVMADR

Addressing

Counter

Using

NVMADR Reg EA

User/Configuration

Space Select

dsPIC30F2011/2012/3012/3013

5.4 RTSP Operation

The dsPIC30F Flash program memory is organized

into rows and panels. Each row consists of 32

instructions or 96 bytes. Each panel consists of 128

rows or 4K x 24 instructions. RTSP allows the user to

erase one row (32 instructions) at a time and to

program four instructions at one time. RTSP may be

used to program multiple program memory panels, but

the table pointer must be changed at each panel

boundary.

Each panel of program memory contains write l atches

that hold 32 instructions of programming data. Prior to

the actual programming ope ration, the write data must

be loaded into the panel write latches. The data to be

programmed into the panel is loaded in sequential

order into the write latches; instruction 0, instruction 1,

etc. The instruction words loaded must always be from

a 32 address boundary.

The basic sequence for RTSP programming is to set up

a Table Pointer, then do a series of TBLWT instructions

to load the write latches. Programming is performed by

setting the special bits in the NVMCON register. 32

TBLWTL and four TBLWTH instructions are required to

load the 32 instructions. If multiple panel programming

is required, the Table Pointer needs to be changed and

the next set of multiple write latches written.

All of the table write operat ions are single-word writes

(2 instruction cycles), because only the table latches

are written. A programming cycle is required for

programming each row.

The Flash Program Memory is readable, writable and

erasable during normal operation over the entire VDD

range.

5.5 Control Registers

The four SFRs used to read and write the program

Flash memory are:

•NVMCON

• NVMADR

• NVMADRU

• NVMKEY

5.5.1 NVMCON REGISTER

The NVMCON register controls which blocks are to be

erased, which memory type is to be p rogrammed, and

start of the programming cycle.

5.5.2 NVMADR REGISTER

The NVMADR register is used to hold the lower two

bytes of the Effective Address. The NVMADR register

captures the EA<15:0> of the last table instruction that

has been executed and selects the row to write.

5.5.3 NVMADRU REGISTER

The NVMADRU register is used to hold the upper byte

of the Effective Address. The NVMADRU register

captures the EA<23:16> of the last table instruction

that has been executed.

5.5.4 NVMKEY REGISTER

NVMKEY is a write-only register that is used for write

protection. To start a programming or an erase

sequence, the user must consecutively write 0x55 and

0xAA to the NVMKEY register. Refer to Section 5.6

“Programming Operations” for further details.

Note: The user can also directly write to the

NVMADR and NVMADRU registers to

specify a program memory address for

erasing or programming.

dsPIC30F2011/2012/3012/3013

5.6 Programming Operations

A complete programming sequence is necessary for

programming or erasing the internal Flash in RTSP

mode. A programming operation is nominally 2 msec in

duration and the processor stalls (waits) until the

operation is finished. Setting the WR bit

(NVMCON<15>) starts the operation and the WR bit is

automatically cleared when the operation is finished.

5.6.1 PROGRAMMING ALGORITHM FOR

PROGRAM FLASH

The user can erase or program one row of program

Flash memory at a time. The general process is:

1. Read one ro w of program Flash (32 instruction

words) and store into data RAM as a data

“image”.

2. Update the data image with the desired new

data.

3. Erase program Flash row.

a) Set up NVMCON register for multi-word,

program Flash, erase, and set WREN bit.

b) Write address of row to be erased into

NVMADRU/NVMDR.

c) Write 0x55 to NVMKEY.

d) Write 0xAA to NVMKEY.

e) Set the WR bit. This begins erase cycle.

f) CPU stalls for the duration of the erase cycle.

g) The WR bit is cleared when erase cycle

ends.

4. Write 32 instruction words of data from data

RAM “image” into the program Flash write

latches.

5. Program 32 instruction words into program

Flash.

a) Set up NVMCON register for multi-word,

program Flash, program, and set WREN

bit.

b) Write 0x55 to NVMKEY.

c) Write 0xAA to NVMKEY.

d) Set the WR bit. This begins program cycle.

e) CPU stalls for duration of the program cycle.

f) The WR bit is cleared by the hardware

when program cycle ends.

6. Repeat steps 1 through 5 as needed to program

desired amount of program Flash memory.

5.6.2 ERASING A ROW OF PROGRAM

MEMORY

Example 5-1 shows a code sequence that can be used

to erase a row (32 instructions) of program memory.

EXAMPLE 5-1: ERASING A ROW OF PROGRAM MEMORY

; Setup NVMCON for erase operation, multi word write

; program memory selected, and writes enabled

MOV #0x4041,W0 ;

MOV W0,NVMCON ; Init NVMCON SFR

; Init pointer to row to be ERASED

MOV #tblpage(PROG_ADDR),W0 ;

MOV W0,NVMADRU ; Initialize PM Page Boundary SFR

MOV #tbloffset(PROG_ADDR),W0 ; Intialize in-page EA[15:0] pointer

MOV W0, NVMADR ; Initialize NVMADR SFR

DISI #5 ; Block all interrupts with priority <7 for

; next 5 instructions

MOV #0x55,W0

MOV W0,NVMKEY ; Write the 0x55 key

MOV #0xAA,W1 ;

MOV W1,NVMKEY ; Write the 0xAA key

BSET NVMCON,#WR ; Start the erase sequence

NOP ; Insert two NOPs after the erase

NOP ; command is asserted

dsPIC30F2011/2012/3012/3013

5.6.3 LOADING WRITE LATCHES

Example 5-2 shows a sequence of instructions that

can be used to load the 96 bytes of write latches. 32

TBLWTL and 32 TBLWTH instructions are needed to

load the write latches selected by the Table Pointer.

5.6.4 INITIATING THE PROGRAMMING

SEQUENCE

For protection, the write initiate sequence for NVMKEY

must be used to allow any erase or prog ram operati on

to proceed. After the programming command has been

executed, the user must wait for the programming time

until programming is complete. The two instructions

following the start of the programming sequence

should be NOPs as shown in Example 5-3.

EXAMPLE 5-2: LOADING WRITE LATCHES

EXAMPLE 5-3: INITIATING A PROGRAMMING SEQUENCE

; Set up a pointer to the first program memory location to be written

; program memory selected, and writes enabled

MOV #0x0000,W0 ;

MOV W0,TBLPAG ; Initialize PM Page Boundary SFR

MOV #0x6000,W0 ; An example program memory address

; Perform the TBLWT instructions to write the latches

; 0th_program_word

MOV #LOW_WORD_0,W2 ;

MOV #HIGH_BYTE_0,W3 ;

TBLWTL W2,[W0] ; Write PM low word into program latch

TBLWTH W3,[W0++] ; Write PM high byte into program latch

; 1st_program_word

MOV #LOW_WORD_1,W2 ;

MOV #HIGH_BYTE_1,W3 ;

TBLWTL W2,[W0] ; Write PM low word into program latch

TBLWTH W3,[W0++] ; Write PM high byte into program latch

; 2nd_program_word

MOV #LOW_WORD_2,W2 ;

MOV #HIGH_BYTE_2,W3 ;

TBLWTL W2, [W0] ; Write PM low word into program latch

TBLWTH W3, [W0++] ; Write PM high byte into program latch

•

; 31st_program_word

MOV #LOW_WORD_31,W2 ;

MOV #HIGH_BYTE_31,W3 ;

TBLWTL W2, [W0] ; Write PM low word into program latch

TBLWTH W3, [W0++] ; Write PM high byte into program latch

Note: In Example 5-2, the contents of the upper byte of W3 has no effect.

DISI #5 ; Block all interrupts with priority <7 for

; next 5 instructions

MOV #0x55,W0 ;

MOV W0,NVMKEY ; Write the 0x55 key

MOV #0xAA,W1 ;

MOV W1,NVMKEY ; Write the 0xAA key

BSET NVMCON,#WR ; Start the erase sequence

NOP ; Insert two NOPs after the erase

NOP ; command is asserted

dsPIC30F2011/2012/3012/3013

TABLE 5-1: NVM REGISTER MAP

File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 1 1 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All RESETS

NVMCON 0760 WR WREN WRERR — — — —TWRI — PROGOP<6:0> 0000 0000 0000 0000

NVMADR 0762 NVMADR<15:0> uuuu uuuu uuuu uuuu

NVMADRU 0764 — — — — — — — — NVMADR<23:16> 0000 0000 uuuu uuuu

NVMKEY 0766 — — — — — — — —KEY<7:0> 0000 0000 0000 0000

Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’

Note: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.

dsPIC30F2011/2012/3012/3013

NOTES:

dsPIC30F2011/2012/3012/3013

6.0 DATA EEPROM MEMORY

The data EEPROM memory is readable and writable

during normal operation over the entire VDD range. The

data EEPROM memory is directly mapped in the

program memory address space.

The four SFRs used to read and write the program

Flash memory are used to access data EEPROM

memory , as well. As described in Section 5.5 “Control

Registers”, these registers are:

•NVMCON

• NVMADR

• NVMADRU

• NVMKEY

The EEPROM data memory allows read and write of

single words and 16-word blocks. Whe n in terfacing to

data memory, NVMADR, in conjunction with the

NVMADRU register, are used to address the

EEPROM location being accessed. TBLRDL and

TBLWTL instructions are used to read and write data

EEPROM. The dsPIC30F devices have up to 8 Kbytes

(4K words) of data EEPROM with an address range

from 0x7FF000 to 0x7FFFFE.

A word write operation should be preceded by an erase

of the corresponding memory location(s). The write

typically requires 2 ms to complete, but the write time

varies with voltage and temperature.

A program or erase operation on the data EEPROM

does not stop the instruction flow. The user is

responsible for waiting for the appropriate duration of

time before initiating another data EEPROM write/

erase operation. Attempting to read the data EEPROM

while a programming o r erase opera tion is in progress

results in unspecified data.

Control bit WR initiates write operations similar to

program Flash writes. This bit cannot be cleared, only

set, in software. They are cleared in hardware at the

completion of the write o peration. The inability to clear

the WR bit in software prevents the accidental or

premature termination of a write operation.

The WREN bit, when set, allows a write o peration. On

power-up, the WREN bit is clear . The WRERR bit is set

when a write operation is interrupted by a MCLR Reset

or a WDT Time-out Reset during normal op eration. In

these situations, following Reset, the user can check

the WRERR bit and rewrite the location. The address

6.1 Reading the Data EEPROM

A TBLRD instruction reads a word at the current

program word address. This example uses W0 as a

pointer to data EEPROM. The result is placed in

EX A M P L E 6 -1 : DAT A EEPROM READ

Note: This data sheet summarizes features of

this group of dsPIC30F devices and is not

intended to be a complete reference

source. For more information on the CPU,

peripherals, register descriptions and

general device functionality, refer to the

“dsPIC30F Family Reference Manual”

(DS70046). For more information on the

device instruction set and programming,

refer to the “16-bit MCU and DSC

Programmer’s Reference Manual”

(DS70157).

Note: Interrupt flag bit NVMIF in the IFS0

must be cleared in software.

MOV #LOW_ADDR_WORD,W0 ; Init Pointer

MOV #HIGH_ADDR_WORD,W1

MOV W1,TBLPAG

TBLRDL [ W0 ], W4 ; read data EEPROM

dsPIC30F2011/2012/3012/3013

6.2 Erasing Data EEPROM

6.2.1 ERASING A BLOCK OF DATA

EEPROM

In order to erase a block of data EEPROM, the

NVMADRU and NVMADR registers must initia lly point

to the block of memory to be erased. Configure

NVMCON for erasing a block of data EEPROM and

set the WR and WREN bits in the NVMCON register.

Setting the WR bit initiates the erase, as shown in

Example 6-2.

EXAMPLE 6-2: DATA EEPROM BLOCK ERASE

6.2.2 ERASING A WORD OF DATA

EEPROM

The NVMADRU and NVMADR registers must point to

the block. Select WR a block of data Flash and set the

WR and WREN bits in the NVMCON register. Setting the

WR bit initiates the erase, as shown in Example 6-3.

EXAM PLE 6-3: DATA EEPROM WORD ERASE

; Select data EEPROM block, WR, WREN bits

MOV #0x4045,W0

MOV W0,NVMCON ; Initialize NVMCON SFR

; Start erase cycle by setting WR after writing key sequence

DISI #5 ; Block all interrupts with priority <7 for

; next 5 instructions

MOV #0x55,W0 ;

MOV W0,NVMKEY ; Write the 0x55 key

MOV #0xAA,W1 ;

MOV W1,NVMKEY ; Write the 0xAA key

BSET NVMCON,#WR ; Initiate erase sequence

NOP

; Erase cycle will complete in 2mS. CPU is not stalled for the Data Erase Cycle

; User can poll WR bit, use NVMIF or Timer IRQ to determine erasure complete

; Select data EEPROM word, WR, WREN bits

MOV #0x4044,W0

MOV W0,NVMCON

; Start erase cycle by setting WR after writing key sequence

DISI #5 ; Block all interrupts with priority <7 for

; next 5 instructions

MOV #0x55,W0 ;

MOV W0,NVMKEY ; Write the 0x55 key

MOV #0xAA,W1 ;

MOV W1,NVMKEY ; Write the 0xAA key

BSET NVMCON,#WR ; Initiate erase sequence

NOP

; Erase cycle will complete in 2mS. CPU is not stalled for the Data Erase Cycle

; User can poll WR bit, use NVMIF or Timer IRQ to determine erasure complete

dsPIC30F2011/2012/3012/3013

6.3 Writing to the Data EEPROM

To write an EEPROM data location, the following

sequence must be followed:

1. Erase data EEPROM word.

a) Select word, data EEPROM erase, and set

WREN bit in NVMCON register.

b) Write address of word to be erased into

NVMADR.

c) Enable NVM interrupt (optional).

d) Wr it e 0x55 to NVMKEY.

e) Write 0xAA to NVMKEY.

f) Set the WR bit. This begins erase cycle.

g) Either poll NVMIF bit or wait for NVMIF

interrupt.

h) The WR bit is cleared when the erase cycle

ends.

2. Write data word into data EEPROM write

latches.

3. Program 1 data word into data EEPROM.

a) Select word, data EEPROM program, and

set WREN bit in NVMCON register.

b) Enable NVM write done interrupt (optional).

c) Write 0x55 to NVMKEY.

d) Write 0xAA to NVMKEY.

e) Set the WR bit. This begins program cycle.

f) Either poll NVMIF bit or wait for NVM

interrupt.

g) The WR bit is cl eared when the write cycl e

ends.

The write does not initiate if the above sequence is not

exactly followed (write 0x55 to NVMKEY, write 0xAA to

NVMCON, then set WR bit) for each word. It is strongly

recommended that interrupts be disabled during this

code segment.

Additionally, the WREN bit in NVMCON must be set to

enable writes. This mechanism prevents accidental

writes to data EEPROM due to unexpected code

execution. The WREN bit should be kept clear at all

times except when updating the EEPROM. The WREN

bit is not cleared by hardware.

After a write sequence has been initiated, clearing the

WREN bit does not affect the current write cycle. The

WR bit is inhibited from being set unless the WREN bit

is set. The WREN bit must be set on a previous

instruction. Both WR and WREN cannot be set with the

same instruction.

At the completion of the write cycle, the WR bit is

cleared in hardware and the Nonvolatile Memory Write

Complete Interrupt Flag bit (NVMIF) is set. The user

may either enable this in terrupt or poll this bit. NVMIF

must be cleared by software.

6.3.1 WRITING A WORD OF DATA

EEPROM

Once the user has erased the word to be programmed,

then a table write instruction is used to write one write

latch, as shown in Example 6-4.

6.3.2 WRITING A BLOCK OF DATA

EEPROM

To write a block of data EEPROM, write to all sixteen

latches first, then set the NVMCON register and

program the block.

EXAMPLE 6-4: DATA EEPROM WORD WRITE

; Point to data memory

MOV #LOW_ADDR_WORD,W0 ; Init pointer

MOV #HIGH_ADDR_WORD,W1

MOV W1,TBLPAG

MOV #LOW(WORD),W2 ; Get data

TBLWTL W2,[ W0] ; Write data

; The NVMADR captures last table access address

; Select data EEPROM for 1 word op

MOV #0x4004,W0

MOV W0,NVMCON

; Operate key to allow write operation

DISI #5 ; Block all interrupts with priority <7 for

; next 5 instructions

MOV #0x55,W0

MOV W0,NVMKEY ; Write the 0x55 key

MOV #0xAA,W1

MOV W1,NVMKEY ; Write the 0xAA key

BSET NVMCON,#WR ; Initiate program sequence

NOP

; Write cycle will complete in 2mS. CPU is not stalled for the Data Write Cycle

; User can poll WR bit, use NVMIF or Timer IRQ to determine write complete

dsPIC30F2011/2012/3012/3013

EXAMPLE 6-5: DATA EEPROM BLOCK WRITE

6.4 Write Verify

Depending on the application, good programming

practice may dictate that the value written to the mem-

ory should be verified against the original value. This

should be used in appli cations where excessive writes

can stress bits near the specification limit.

6.5 Protection Against Spurious Write

There are conditio ns whe n the de vi ce may not want to

write to the data EEPROM memory. To protect against

spurious EEPROM writes, various mechanisms have

been built-in. On power-up, the WREN bit is cleared;

also, the Power-up Timer prevents EEPROM write.

The write initiate sequence and the WREN bit together

help prevent an accidental write during brown-out,

power glitch, or software malfunction.

MOV #LOW_ADDR_WORD,W0 ; Init pointer

MOV #HIGH_ADDR_WORD,W1

MOV W1,TBLPAG

MOV #data1,W2 ; Get 1st data

TBLWTL W2,[ W0]++ ; write data

MOV #data2,W2 ; Get 2nd data

TBLWTL W2,[ W0]++ ; write data

MOV #data3,W2 ; Get 3rd data

TBLWTL W2,[ W0]++ ; write data

MOV #data4,W2 ; Get 4th data

TBLWTL W2,[ W0]++ ; write data

MOV #data5,W2 ; Get 5th data

TBLWTL W2,[ W0]++ ; write data

MOV #data6,W2 ; Get 6th data

TBLWTL W2,[ W0]++ ; write data

MOV #data7,W2 ; Get 7th data

TBLWTL W2,[ W0]++ ; write data

MOV #data8,W2 ; Get 8th data

TBLWTL W2,[ W0]++ ; write data

MOV #data9,W2 ; Get 9th data

TBLWTL W2,[ W0]++ ; write data

MOV #data10,W2 ; Get 10th data

TBLWTL W2,[ W0]++ ; write data

MOV #data11,W2 ; Get 11th data

TBLWTL W2,[ W0]++ ; write data

MOV #data12,W2 ; Get 12th data

TBLWTL W2,[ W0]++ ; write data

MOV #data13,W2 ; Get 13th data

TBLWTL W2,[ W0]++ ; write data

MOV #data14,W2 ; Get 14th data

TBLWTL W2,[ W0]++ ; write data

MOV #data15,W2 ; Get 15th data

TBLWTL W2,[ W0]++ ; write data

MOV #data16,W2 ; Get 16th data

TBLWTL W2,[ W0]++ ; write data. The NVMADR captures last table access address.

MOV #0x400A,W0 ; Select data EEPROM for multi word op

MOV W0,NVMCON ; Operate Key to allow program operation

DISI #5 ; Block all interrupts with priority <7 for

; next 5 instructions

MOV #0x55,W0

MOV W0,NVMKEY ; Write the 0x55 key

MOV #0xAA,W1

MOV W1,NVMKEY ; Write the 0xAA key

BSET NVMCON,#WR ; Start write cycle

NOP

dsPIC30F2011/2012/3012/3013

7.0 I/O PORTS

All of the device pins (except VDD, VSS, MCLR and

OSC1/CLKI) are shared between the peripherals and

the parallel I/O ports.

All I/O input ports feature Schmitt Trigger inputs for

improved noise immunity.

7.1 Parallel I/O (PIO) Ports

When a peripheral is enabled and the peripheral is

actively driving an associated pin, the use of the pin as

a general purpose output pin is disabled. The I/O pin

can be read, but the output driver for the parallel port bit

is disabled. If a peripheral is enabled, but the peripheral

is not actively driving a pin, that pin can be driven by a

port.

All port pins have three registers directly associated

with the operation of the port pin. The Data Direction

or an output. If the data direction bit is a ‘1’, then the pin

is an input. All port pins are defined as inputs after a

Reset. Reads from the latch (LATx), read the latch.

Writes to the latch, write the latch (LAT x). Reads from

the port (PORTx), read the port pins and writes to the

port pins, write the latch (LATx).

Any bit and its associated data and Control registers

that are not valid for a particular device are disabled.

That means the corresponding LATx and TRISx

registers and the port pin read as zeros.

When a pin is shared with another peripheral or

function that is defined as an input only, it is

nevertheless regarded as a dedicated port because

there is no other competing source of outputs.

A parallel I/O (PIO) port that shares a pin with a

peripheral is, in general, subservient to the peripheral.

The peripheral’s output buffer data and control signals

are provided to a pair of multiplexers. The multiplexers

select whether the peripheral or the associated port

has ownership of the output data and control signals of

the I/O pad cell. Figure 7-1 illustrates how ports are

shared with other peripherals and the associated I/O

cell (pad) to which they are connected.

The format of the registers for the shared ports,

(PORTB, PORTC, PORTD and PORTF) are shown in

Table 7-1 through Table 7-6.

FIGURE 7-1: BLOCK DIAGRAM OF A SHARED PORT STRUCTURE

Note: This data sheet summarizes features of

this group of dsPIC30F devices and is not

intended to be a complete reference

source. For more information on the CPU,

peripherals, register descriptions and

general device functionality, refer to the

“dsPIC30F Family Reference Manual”

(DS70046).

Note: The actual bits in use vary between

devices.

WR LAT +

TRIS Latch

I/O Pad

WR Port

Data Bus

Data Latch

Read LAT

Read Port

Read TRIS

WR TRIS

Peripheral Output Data Output Enable

Peripheral Input Data

I/O Cell

Peripheral Module

Peripheral Output Enable

PIO Module

Output Multiplexers

Output Data

Input Data

Peripheral Module Enable

dsPIC30F2011/2012/3012/3013

7.2 Configuring Analog Port Pins

The use of the ADPCFG and TRIS registers control the

operation of the A/D port pins. The port pins that are

desired as analog inputs must have their

corresponding TRIS bit set (input). If the TRIS bit is

cleared (output), the digital output level (VOH or V OL) is

converted.

When the PORT register is read, all pins configured as

analog input channels are read as cleared (a low level).

Pins configured as digital inputs will not convert an

analog input. Analog levels on any pin that is defined as

a digital input (including the ANx pins) may cause the

input buffer to consume the current that exceeds

device specifications.

7.2.1 I/O PORT WRITE/READ TIMING

One instruction cycle is required between a port

direction change or port write operation and a read

operation of the same port. Typically this instruction

would be a NOP.

EXAMPLE 7-1: PORT WRITE/READ

EXAMPLE

MOV #0xF0, W0 ; Configure PORTB<7 :4>

; as inputs

MOV W0, TRISB ; and PORTB<3:0> as output s

NOP ; additional in structi on

cycle

btss PORTB, #7 ; bit test RB7 and skip if

set

dsPIC30F2011/2012/3012/3013

TABLE 7-1: PORTB REGISTER MAP FOR dsPIC30F2011 /3012

TABLE 7-2: PORTB REGISTER MAP FOR dsPIC30F2012/3013

TABLE 7-3: PORTC REGISTER MAP FOR dsPIC30F2011/2012/3012/3013

TABLE 7-4: PORTD REGISTER MAP FOR dsPIC30F2011 /3012

SFR

Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

TRISB 02C6 — — — — — — — — TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 0000 0000 1111 1111

PORTB 02C8 — — — — — — — — RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 0000 0000 0000 0000

LATB 02CB — — — — — — — — LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 0000 0000 0000 0000

Legend: — = unimplemented bit, read as ‘0’

SFR

Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

TRISB 02C6 — — — — — — TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 0000 0011 1111 1111

PORTB 02C8 — — — — — — RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 0000 0000 0000 0000

LATB 02CB — — — — — — LATB9 LATB8 LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 0000 0000 0000 0000

Legend: — = unimplemented bit, read as ‘0’

SFR

Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset St ate

TRISC 02CC TRISC15 TRISC14 TRISC13 — — — — — — — — — — — — — 1110 0000 0000 0000

PORTC 02CE RC15 RC14 RC13 — — — — — — — — — — — — — 0000 0000 0000 0000

LATC 02D0 LATC15 LATC14 LATC13 — — — — — — — — — — — — — 0000 0000 0000 0000

Legend: — = unimplemented bit, read as ‘0’

SFR

Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

TRISD 02D2 — — — — — — — — — — — — — — —TRISD00000 0000 0000 0001

PORTD 02D4 — — — — — — — — — — — — — — — RD0 0000 0000 0000 0000

LATD 02D6 — — — — — — — — — — — — — — —LATD00000 0000 0000 0000

Legend: — = unimplemented bit, read as ‘0’

dsPIC30F2011/2012/3012/3013

TABLE 7-5: PORTD REGISTER MAP FOR dsPIC30F2012/3013

TABLE 7-6: PORTF REGISTER MAP FOR dsPIC30F2012/3013

SFR

Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

TRISD 02D2 — — — — — — TRISD9 TRISD8 — — — — — — — — 0000 0011 0000 0000

PORTD 02D4 — — — — — — RD9 RD8 — — — — — — — — 0000 0000 0000 0000

LATD 02D6 — — — — — —LATD9LATD8— — — — — — — — 0000 0000 0000 0000

Legend: — = unimplemented bit, read as ‘0’

SFR

Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

TRISF 02DE — — — — — — — — — TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 — — 0000 0000 0111 1100

PORTF 02E0 — — — — — — — — — RF6 RF5 RF4 RF3 RF2 — — 0000 0000 0000 0000

LATF 02E2 — — — — — — — — — LATF6 LATF5 LATF4 LATF3 LATF2 — — 0000 0000 0000 0000

Legend: — = unimplemented bit, read as ‘0’

Note: The dsPIC30F2011/3012 devices do not h av e T RISF, PORTF, or LATF.

dsPIC30F2011/2012/3012/3013

7.3 Input Change Notification Module

The input change notification module provides the

dsPIC30F devices the ability to generate interrupt

requests to the processor, in response to a change of

state on selected input pins. This module is capable of

detecting input change of states even in Sleep mode,

when the clocks are disabled. There are up to 10

external signals (CN0 through CN7, CN17 and CN18)

that may be selected (enabled) for generating an

interrupt request on a change of state.

TABLE 7-7: INPUT CHANGE NOTIFICATION REGISTER MAP FOR dsPIC30F201 1/3012 (BIT S 7-0)

TABLE 7-8: INPUT CHANGE NOTIFICATION REGISTER MAP FOR dsPIC30F2012/3013 (BITS 7-0)

SFR

Name Address Bit 7 Bit 6 Bit 5 B it 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

CNEN1 00C0 CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE 0000 0000 0000 0000

CNEN2 00C2 ————————0000 0000 0000 0000

CNPU1 00C4 CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE 0000 0000 0000 0000

CNPU2 00C6 ————————0000 0000 0000 0000

Legend: — = unimplemented bit, read as ‘0’

SFR

Name Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

CNEN1 00C0 CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE 0000 0000 0000 0000

CNEN2 00C2 ————— CN18IE CN17IE —0000 0000 0000 0000

CNPU1 00C4 CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE 0000 0000 0000 0000

CNPU2 00C6 ————— CN18PUE CN17PUE —0000 0000 0000 0000

Legend: — = unimplemented bit, read as ‘0’

Note: Refer to the “ds PI C 3 0F F a m i l y Re fe r e nce Manua l ” (DS70046) for descriptions of register bit fie l ds.

dsPIC30F2011/2012/3012/3013

NOTES:

dsPIC30F2011/2012/3012/3013

8.0 INTERRUPTS

The dsPIC30F sensor family has up to 21 interrupt

sources and 4 processor exceptions (traps) which must

be arbitrated based on a priority scheme.

The CPU is responsible for reading the Interrupt V ector

Table (IVT) and transferring the address contained in

the interrupt vector to the program counter. The

interrupt vector is transferred from the program data

bus into the program counter via a 24-bit wide

multiplexer on the input of the program counter.

The Interrupt V ector Table (IVT) and Alternate Interrupt

Vector Table (AIVT) are placed near the beginning of

program memory (0x000004). The IVT and AIVT are

shown in Figure 8-1.

The interrupt controller is responsible for

pre-processing the interrupts and processor

exceptions before they ar e pr es ented to th e pr ocessor

core. The peripheral interrupts and traps are enabled,

prioritized and controlled using centralized Special

Function Registers (SFRs):

• IFS0<15:0>, IFS1<15:0>, IFS2< 15:0>

All interrupt request flags are maintained in these

three registers. The flags are set by their

respective peripherals or external sign als and

they are cleared via software.

• IEC0<15:0>, IEC1<15:0>, IEC2<15:0>

All interrupt ena b l e co ntrol bits are maintained in

these three registers. These control bits are used

to individually enable interrup ts from the

peripherals or external signals.

• IPC0<15:0> through IPC10<7 :0 >

The user assignable priority level associated with

each of these 41 interrupts is held centrally in

these eleven registers.

•IPL<3:0>

The current CPU priority level is explicitly stored

in the IP L bits. IP L<3 > is pr esen t in t he C OR CON

STATUS register (SR) in the processor core.

• INTCON1<15:0>, INTCON2<15:0>

Global interrupt control functions are derived from

these two registers. INTCON1 contains the

control and status flags for the processor

exceptions. Th e INT CO N 2 register controls the

external interrupt request signal behavior and the

use of the alternate vector table.

All interrupt sources can be user assigned to one of 7

priority levels, 1 thro ugh 7, throug h the IPCx registers.

Each interrupt source is associated with an interrupt

vector , as shown in Table 8-1. Levels 7 and 1 represent

the highest and lowest maskable priorities, respec-

tively.

If the NSTDIS bit (INTCON1<15>) is set, nesting of

interrupts is prevented. Thus, if an interrupt is currently

being serviced, processing of a new interrupt is

prevented even if the new interrupt is of higher priority

than the one currently being serviced.

Certain interrupts have specialized control bits for

features like edge or level triggered interrupts,

interrupt-on-change, etc. Control of these features

remains within the periphera l module which generates

the interrupt.

The DISI instruction can be used to disable the

processing of interrupts of priorities 6 and lower for a

certain number of instructions, during which the DISI bit

(INTCON2<14>) remains set.

When an interrupt is service d, the PC is loaded w ith the

address stored in the vector location in program

memory that corresp onds to th e inte rrupt. Th ere are 63

different vectors within the IVT (refer to Table 8-1).

These vectors are contained in locations 0x000004

through 0x0000FE of program memory (refer to

Table 8-1). These locations contain 24-bit addresses,

and in order to preserve rob ustness, an address error

trap takes place if the PC attempts to fetch any of these

words during normal execution. This prevents

execution of random data as a result of accidentally

decrementing a PC into vector space, accidentally

mapping a data space address into vector space, or the

PC rolling over to 0x000000 after reaching the end of

implemented program memory space. Execution of a

GOTO instruction to this vector space also generates an

address error trap.

Note: This data sheet summarizes features of

this group of dsPIC30F devices and is not

intended to be a complete reference

source. For more information on the CPU,

peripherals, register descriptions and

general device functionality, refer to the

“dsPIC30F Family Reference Manual”

(DS70046). For more information on the

device instruction set and programming,

refer to the “16-bit MCU and DSC

Programmer’s Reference Manual”

(DS70157).

Note: Interrupt flag bits get set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit. User

software should ensure the appropriate

interrupt flag bits are clear prior to

enabling an interrupt.

Note: Assigning a priority level of ‘0’ to an

interrupt source is equivalent to disabl ing

that interrupt.

Note: The IPL bits become read-only whenever

the NSTDIS bit has been set to ‘1’.

dsPIC30F2011/2012/3012/3013

8.1 Interrupt Priority

The user-assignable interrupt priority bits (IP<2:0>) for

each individual interrupt source are located in the

LS 3 bits of each nibble within the IPCx register(s). Bit

3 of each nibble is not used and is read as a ‘0’. These

bits define the priority level assigned to a particular

interrupt by the user.

Natural Order Priority is d etermined by the position of

an interrupt in the vector table, and only affects

interrupt operation when multiple interrupts with the

same user-assigned priority become pending at the

same time.

Table 8-1 lists the interrupt numbers and interrupt

sources for the dsPIC30F2011/2012/3012/3013

devices and their associated vector numbers.

The ability for the user to assign every interrupt to one

of seven priority levels means that the user can assign

a very high overall priority level to an interrupt with a

low natural order priority. For example, the PLVD

(Low Voltage Detect) can be given a priority of 7. The

INT0 (External Interrupt 0) ma y be assigned to priority

level 1, thus giving it a very low effective priority.

TABLE 8-1: INTERRUPT VECTOR TA BLE

Note: The user-assignable priority levels start at

0 as the lowest priority and level 7 as the

highest priority.

Note 1: The natural order priority scheme has 0

as the highest priority and 53 as the

lowest priority.

2: The natural order priority number is the

same as the INT number.

Interrupt

Number Vector

Number Interrupt Source

Highest Natural Order Priority

0 8 INT0 – External In terrupt 0

1 9 IC1 – Input Capture 1

2 10 OC1 – Output Compare 1

3 11 T1 – Timer 1

4 12 IC2 – Input Capture 2

5 13 OC2 – Output Compare 2

6 14 T2 – Timer2

7 15 T3 – Timer3

816SPI1

9 17 U1RX – UART1 Receiver

10 18 U1TX – UART1 Transmitter

11 19 ADC – ADC Convert Done

12 20 NVM – NVM Write Complete

13 21 SI2C – I2C™ Slave Interrupt

14 22 MI2C – I2C Master Interrupt

15 23 Input Change Interrupt

16 24 INT1 – External Interrupt 1

17-22 25-30 Reserved

23 31 INT2 – External Interrupt 2

24 32 U2RX(1) – UART2 Receiver

25 33 U2TX(1) – UART2 Transmitter

26-41 34-49 Reserved

42 50 LVD – Low-Voltage Detect

43-53 51-61 Reserved

Lowest Natural Order Priority

Note 1: Only the dsPIC30F3013 has UART2 and

the U2RX, U2TX interrupts. These

locations are reserved for the

dsPIC30F2011/2012/3012.

dsPIC30F2011/2012/3012/3013

8.2 Reset Sequence

A Reset is not a true exception because the interrupt

controller is not involved in the Reset process. The

processor initializes its registers in response to a Reset

which forces the PC to zero. The processor then begins

program execution at location 0x000000. A GOTO

instruction is stored in the first program memory

location immediately followed by the address target for

the GOTO instruction. The processor executes the GOTO

to the specified address and then begins operation at

the specified target (start) address.

8.2.1 RESET SOURCES

In addition to external Reset and Power-on Reset

(POR), there are six sources of error co nditions which

‘trap’ to the Reset vector.

• W atchdog Time-out:

The watchdog has timed out, indicating that the

processor is no longer executing the correct flow

of code.

• Uninitialized W Register Trap:

An attempt to use an uninitialized W register as

an Address Pointer causes a Reset.

• Illegal Instruction Trap:

Attempted execution of any unused opcodes

results in an illegal instruction trap. Note that a

fetch of an illegal instruction does not result in an

illegal instruction trap if that instruction is flushed

prior to execution due to a flow change.

• Brown-out Reset (BOR):

A momentary dip in the power supply to the

device has been detected which may result in

malfunction.

• Trap Lockout:

Occurrence of multiple trap conditions

simultaneously causes a Reset.

8.3 Traps

Traps can be considered as non-maskable interrupts

indicating a software or hardware error, which adhere

to a predefined priority as shown in Figure 8-1. They

are intended to provide the user a means to correct

erroneous operation during debug and when operating

within the application.

Note that many of these trap conditions can only be

detected when they occur. Consequently, the

questionable instru ction is allowed to co mplete prior to

trap exception processing. If the user chooses to

recover from the error, the result of the erroneous

action that caused the trap may have to be corrected.

There are eight fixed priority levels for traps: Level 8

through Level 15, which implies that the IPL3 is always

set during processing of a trap.

If the user is not currently executing a trap, and he sets

the IPL<3:0> bits to a value of ‘0111’ (Level 7), then all

interrupts are disabled, but traps can still be processed.

8.3.1 TRAP SOURCES

The following traps are provided with increasing

priority. However , since all traps can be nested, priority

has little effect.

Math Error Trap:

The math error trap execu tes under the following four

circumstances:

1. If an attempt is made to divide by zero, the

divide operation is aborted on a cycle boun dary

and the trap is taken.

2. If enabled, a math error trap is taken when an

arithmetic operation on either accumulator A or

B causes an overflow from bit 31 and the

accumulator guard bits are not utilized.

3. If enabled, a math error trap is taken when an

arithmetic operation on either accumulator A or

B causes a catastrophic overflow from bit 39 and

all saturation is disabled.

4. If the shift amount specified in a shift instruction

is greater than the maximum allowed shift

amount, a trap occurs.

Note: If the user does not intend to take

corrective action in the event of a trap

error condition, these vectors must be

loaded with the address of a default

handler that contains the RESET instruc-

tion. If, on the other hand, one of the vec-

tors containing an invalid address is

called, an address error trap is generated.

dsPIC30F2011/2012/3012/3013

Address Error Trap:

This trap is initiated when any of the following

circumstances occurs:

1. A misaligned data word access is attempted.

2. A data fetch from our unimplemented data

memory location is attempted.

3. A data access of an unimplemented program

memory location is attempted.

4. An instruction fetch from vector space is

attempted.

5. Execution of a “BRA #literal” instruction or a

“GOTO #literal” instruction, where literal

is an unimplemented program memory address.

6. Executing instructions after modifying the PC to

point the unimplemented program memory

addresses. The PC may be modified by loading

a value into the stack and executing a RETURN

instruction.

Stack Error Trap:

This trap is initiated under the following conditions:

• The Stack Pointer is loaded with a value which is

greater than the (user programmable) limit value

written into the SPLIM register (stack overflow).

• The Stack Pointer is loaded with a value which is

less than 0x0800 (simple stack underflow).

Oscillator Fail Trap:

This trap is initiated if the external oscillator fails and

operation becomes reliant on an internal RC backup.

8.3.2 HARD AND SOFT TRAPS

It is possible that multiple traps can become active

within the same cycle (e.g., a misaligned word stack

write to an overflowed address). In such a case, the

fixed priority shown in Figure 8-2 is implemented,

which may requi re the user to check if other traps are

pending, in order to completely correct the Fault.

Soft traps include exceptions of priority level 8 through

level 11, inclusive. The arithmetic error trap (level 11)

falls into this category of traps.

Hard traps include exceptions of priority level 12

through level 15, inclusive. The address error (level

12), stack error (level 13) and oscillator error (level 14)

traps fall into this category.

Each hard trap that occurs must be acknowledged

before code execution of any type can continue. If a

lower priority hard trap occurs while a higher priority

trap is pending, acknowledged, or is being processed,

a hard trap conflict occurs.

The device is automatically Reset in a hard trap conflict

condition. The TRAPR Status bit (RCON<15>) is set

when the Reset occurs, so that the condition may be

detected in software.

Note: In the MAC class of instructions, wherein

the data space is split into X and Y data

space, unimplemented X space includes

all of Y space, and unimplemented Y

space includes all of X space.

dsPIC30F2011/2012/3012/3013

FIGURE 8-1: TRAP VECTORS

8.4 Interrupt Sequence

All interrupt event flags are sampled in the beginning of

each instruction cycle by the IFSx registers. A pending

Interrupt Request (IRQ) is indicated by the flag bit

being equal to a ‘1’ in an IFSx register . The IRQ causes

an interrupt to occur if the corresponding bit in the

Interrupt Enable (IECx) register is set. For the

remainder of the instruction cycle, the priorities of all

pending interrupt requests are evaluated.

If there is a pending IRQ with a priority level greater

than the current processor priori ty level in the IPL b its,

the processor is interrupted.

The processor then stacks the current program counter

and the low byte of the processor STATUS register

(SRL), as shown in Figure 8-2. The low byte of the

ST A TUS register cont ains the processor priority level at

the time prior to the beginning of the interrupt cycle.

The processor then loads the priority level for this

interrupt into the STATUS register. This action disables

all lower priority interrupts until the completion of the

Interrupt Service Routine (ISR).

FIGURE 8-2: IN TE RRUPT STAC K

FRAME

The RETFIE (return from interrupt) instruction unstacks

the program counter and STATUS registers to return

the processor to its state prior to the interrupt

sequence.

8.5 Alternate Vector Table

In program memory, the Interrupt Vector Table (IVT) is

followed by the Alternate Interrupt Vector Table (AIVT),

as shown in Figure 8-1. Access to th e alternate vector

table is provided by the ALTIVT bit in the INTCON2

exception processes use the alternate vectors instead

of the default vectors. The alternate vectors are

organized in the same man ner as the default vectors.

The AIVT supports emulation and debugging efforts by

providing a means to switch between an application

and a support environment without requiring the

interrupt vectors to be re programmed. This featur e also

enables switch ing between applications for evaluation

of different software algorithms at run time.

If the AIVT is not required, the program memory

allocated to the AIVT may be used for other purpose s.

AIVT is not a protected section and may be freely

programmed by the user.

Address Error Trap Vector

Oscillator Fail Trap Vector

St ack Error Trap Vector

Reserved Vector

Math Error Trap Vector

Reserved

Oscillator Fail Trap Vector

Address Error Trap Vector

Reserved Vector

Interrupt 0 Vector

Interrupt 1 Vector

—

Interrupt 52 Vector

Interrupt 53 Vector

Math Error Trap Vector

Decreasing

Priority

0x000000

0x000014

Reserved

St ack Error Trap Vector

Reserved Vector

Interrupt 0 Vector

Interrupt 1 Vector

—

Interrupt 52 Vector

Interrupt 53 Vector

IVT

AIVT

0x000080

0x00007E

0x0000FE

Reserved

0x000094

Reset - GOTO Instruction

Reset - GOTO Address 0x000002

Reserved 0x000082

0x000084

0x000004

Reserved Vector

Note 1: The user can always lower the priority

level by writing a new value into SR. The

Interrupt Service Routine must clear the

interrupt flag bits in the IFSx register

before lowering the processor interrupt

priority, in order to avoid recursive

interrupts.

2: The IPL3 bit (CORCON<3>) is always

clear when interrupts are being

processed. It is set only during execution

of traps.

015

W15 (before CALL)

W15 (after CALL)

Stack Grows Towards

Higher Address

0x0000

PC<15:0>

SRL IPL3 PC<22:16>

POP : [--W15]

PUSH: [W15++]

dsPIC30F2011/2012/3012/3013

8.6 Fast Context Saving

A context saving option is available using shadow

registers. Shadow registers are provided for the DC, N,

OV, Z and C bits in SR, and the registers W0 through

W3. The shadows are only one level deep. The shadow

registers are accessible using the PUSH.S and POP.S

instructions only.

When the processor vectors to an interrupt, the

PUSH.S instruction can be used to store the current

value of the aforementioned registers into their

respective shadow registers.

If an ISR of a certain priority uses the PUSH.S and

POP.S instructions for fast context saving, then a

higher priority ISR should not include the same instruc-

tions. Users must save the key registers in software

during a lower priority interrupt if the higher priority ISR

uses fast context saving.

8.7 External Interrupt Requests

The interrupt controller supports three external

interrupt request signals, INT0-INT2. These inputs are

edge sensitive; they require a low-to-high or a

high-to-low transition to genera te an interrupt request.

The INTCON2 register has three bits, INT0EP-INT2EP,

that select the polarity of the edge detection circuitry.

8.8 Wake-up from Sleep and Idle

The interrupt controller may be used to wake-up the

processor from either Sleep or Idle modes, if Sleep or

Idle mode is active when the interrupt is generated.

If an enabled interrupt request of sufficient priority is

received by the interrupt controller, then the standard

interrupt request is presented to the processor. At the

same time, the processor wakes up from Sleep or Idle

and begins execution of the ISR needed to process the

interrupt request.

dsPIC30F2011/2012/3012/3013

TABLE 8-2: dsPIC30F2011/2012/3012 INTERRUPT CONTROLLER REGISTER MA P

SFR

Name ADR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

INTCON1 0080 NSTDIS — — — — OVATE OVBTE COVTE — — — MATHERR ADDRERR STKERR OSCFAIL —0000 0000 0000 0000

INTCON2 0082 ALTIVT DISI — — — — — — — — — — — INT2EP INT1EP INT0EP 0000 0000 0000 0 000

IFS0 0084 CNIF MI2CIF SI2CIF NVMIF ADIF U1TXIF U1RXIF SPI1IF T3IF T 2IF OC2IF IC2IF T1IF OC1IF IC1IF INT0IF 0000 0000 0000 0000

IFS1 0086 — — — — — — — —INT2IF— — — — — —INT1IF

0000 0000 0000 0000

IFS2 0088 — — — — —LVDIF — — — — — — — — — 0000 0000 0000 0000

IEC0 008C CNIE MI2CIE SI2CIE NVMIE ADIE U1TXIE U1RXIE SPI1IE T3IE T2IE OC2IE IC2IE T1IE OC1IE IC1IE INT0IE 0000 0000 0000 0000

IEC1 008E — — — — — — — —INT2IE— — — — — —INT1IE

0000 0000 0000 0000

IEC2 0090 — — — — —LVDIE— — — — — — — — — — 0000 0000 0000 0000

IPC0 0094 — T1IP<2:0> —OC1IP<2:0>—IC1IP<2:0> — INT0IP<2:0> 0100 0100 0100 0100

IPC1 0096 — T31P<2:0> — T2IP<2:0> — OC2IP<2:0> —IC2IP<2:0>

0100 0100 0100 0100

IPC2 0098 —ADIP<2:0>— U1TXIP<2:0> — U1RXIP<2:0> — SPI1IP<2:0> 0100 0100 0100 0100

IPC3 009A — CNIP<2:0> —MI2CIP<2:0>— SI2CIP<2:0> —NVMIP<2:0>

0100 0100 0100 0100

IPC4 009C — — — — — — — — — — — — — INT1IP<2:0> 0000 0000 0000 0100

IPC5 009E — INT2IP<2:0> — — — — — — — — — — — — 0100 0000 0000 0000

IPC6 00A0 — — — — — — — — —10 0 —100

0000 0000 0100 0100

IPC7 00A2 — — — — — — — — — — — — — — — — 0000 0000 0000 0000

IPC8 00A4 — — — — — — — — — — — — — — — — 0000 0000 0000 0000

IPC9 00A6 — — — — — — — — — — — — — — — — 0000 0000 0000 0000

IPC10 00A8 — — — — —LVDIP<2:0>— — — — — — — — 0000 0100 0000 0000

Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’

Note: Refer to the “dsPIC30F Family Reference Manual” (DS70 046) for descriptions of register bit fields.

dsPIC30F2011/2012/3012/3013

TABLE 8-3: dsPIC30F3013 INTERRUPT CONTROLLER REGISTER MAP

SFR

Name ADR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

INTCON1 0080 NSTDIS — — — — OVATE OVBTE COVTE — — — MATHERR ADDRERR STKERR OSCFAIL —0000 0000 0000 0000

INTCON2 0082 ALTIVT DISI — — — — — — — — — — — INT2EP INT1EP INT0EP 0000 0000 0000 0 000

IFS0 0084 CNIF MI2CIF SI2CIF NVMIF ADIF U1TXIF U1RXIF SPI1IF T3IF T 2IF OC2IF IC2IF T1IF OC1IF IC1IF INT0IF 0000 0000 0000 0000

IFS1 0086 — — — — — — U2TXIF U2RXIF INT2IF — — — — — —INT1IF

0000 0000 0000 0000

IFS2 0088 — — — — —LVDIF— — — — — — — — — — 0000 0000 0000 0000

IEC0 008C CNIE MI2CIE SI2CIE NVMIE ADIE U1TXIE U1RXIE SPI1IE T3IE T2IE OC2IE IC2IE T1IE OC1IE IC1IE INT0IE 0000 0000 0000 0000

IEC1 008E — — — — — U2TXIE U2RXIE INT2IE — — — — — —INT1IE

0000 0000 0000 0000

IEC2 0090 — — — — —LVDIE— — — — — — — — — — 0000 0000 0000 0000

IPC0 0094 — T1IP<2:0> —OC1IP<2:0>—IC1IP<2:0> — INT0IP<2:0> 0100 0100 0100 0100

IPC1 0096 — T31P<2:0> — T2IP<2:0> — OC2IP<2:0> —IC2IP<2:0>

0100 0100 0100 0100

IPC2 0098 —ADIP<2:0>— U1TXIP<2:0> — U1RXIP<2:0> — SPI1IP<2:0> 0100 0100 0100 0100

IPC3 009A — CNIP<2:0> —MI2CIP<2:0>— SI2CIP<2:0> —NVMIP<2:0>

0100 0100 0100 0100

IPC4 009C — — — — — — — — — — — — — INT1IP<2:0> 0000 0000 0000 0100

IPC5 009E — INT2IP<2:0> — — — — — — — — — 0100 0000 0000 0000

IPC6 00A0 — — — — — — — — — U2TXIP<2:0> — U2RXIP<2:0> 0000 0000 0100 0100

IPC7 00A2 — — — — — — — — — — — — — — — — 0000 0000 0000 0000

IPC8 00A4 — — — — — — — — — — — — — — — — 0000 0000 0000 0000

IPC9 00A6 — — — — — — — — — — — — — — — — 0000 0000 0000 0000

IPC10 00A8 — — — — —LVDIP<2:0>— — — — — — — — 0000 0100 0000 0000

Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’

Note: Refer to the “dsPIC30F Family Reference Manual” (DS70 046) for descriptions of register bit fields.

dsPIC30F2011/2012/3012/3013

9.0 TIMER1 MODULE

This section describes the 16-bit general purpose

Timer1 module and associated operational modes.

Figure 9-1 depicts the simplified block diagram of the

16-bit Timer1 module. The following sections provide

detailed descriptions including setup and Control

registers, along with associated block diagrams for the

operational modes of the timers.

The Timer1 module is a 16-bit timer that serves as the

time counter for the real-time clock or operates as a

free-running interval timer/counter. The 16-bit timer has

the following modes:

• 16-bit Timer

• 16-bit Synchronous Counter

• 16-bit Asynchronous Counter

These operational characteristics are supported:

• Timer gate operation

• Selectable prescaler settings

• Timer operation during CPU Idle and Sleep

modes

• Interrupt on 16-bit Period register match or fallin g

edge of external gate signal

These operating modes are determined by setting the

appropriate bit(s) in the 16-bit SFR, T1CON. Figure 9-1

presents a block diagram of the 16-bit timer module.

16-bit Timer Mode: In the 16-bit T imer mode, the timer

increments on every instruction cycle up to a match

value preloaded into the Period register PR1, then

resets to ‘0’ and continues to count.

When the CPU goes into the Idle mode, the timer stops

incrementing unless the TSIDL (T1CON<13>) bit = 0.

If TSIDL = 1, the timer module logic resumes the incre-

menting sequence on termination of CPU Id le mode.

16-bit Synchronous Counter Mode: In the 16-bit

Synchronous Counter mode, the timer increments on

the rising edge of the applied external clock signal

which is synchronized with the internal phase clocks.

The timer counts up to a match value preloaded in PR1,

then resets to ‘0’ and continues.

When the CPU goes into the Idle mode, the timer stops

incrementing unless the respective TSIDL bit = 0. If

TSIDL = 1, the timer module logic resumes the

incrementing sequence upon termination of the CPU

Idle mode.

16-bit Asynchronous Counter Mode: In the 16-bit

Asynchronous Counter mode, the timer increm ents on

every rising edge of the applied external clock signal.

The timer counts up to a match value preloaded in PR1,

then resets to ‘0’ and continues.

When the timer is configured for the Asynchronous

mode of operation and the CPU goes into the Idle

mode, the timer stops incrementing if TSIDL = 1.

FIGURE 9-1: 16-BIT TIMER1 MODULE BLOCK DIAGRAM

Note: This data sheet summarizes features of

this group of dsPIC30F devices and is not

intended to be a complete reference

source. For more information on the CPU,

peripherals, register descriptions and

general device functionality, refer to the

“dsPIC30F Family Reference Manual”

(DS70046).

TON

Sync

SOSCI

SOSCO/

PR1

T1IF

Equal Comparator x 16

TMR1

Reset

LPOSCEN

Event Flag

TSYNC

TGATE

TCKPS<1:0>

Prescaler

1, 8, 64, 256

TGATE

TCY

T1CK

TCS

1 x

0 1

TGATE

0 0

Gate

Sync

dsPIC30F2011/2012/3012/3013

9.1 Timer Gate Operation

The 16-bit timer can be placed in the Gated Time

Accumulation mode. This mode allows the internal TCY

to increment the respective timer when the gate input

signal (T1CK pin) is asserted high. Control bit,

TGA T E (T1CON<6>), must be set to enable this mode.

The timer must be enabled (TON = 1) and the timer

clock source set to internal (TCS = 0).

When the CPU goes into Idle mode, the timer stops

incrementing unless TSIDL = 0. If TSIDL = 1, the timer

resumes the incrementing seque nce upon termination

of the CPU Idle mode.

9.2 Timer Prescaler

The input clock (FOSC/4 or external clock) to the 16-bit

T imer has a prescale op tion of 1:1, 1:8, 1:64 and 1:256,

selected by control bits, TCKPS<1:0> (T1CON<5:4>).

The prescaler counter is cleared when any of the

following occurs:

• A write to the TMR1 register

• A write to the T1CON register

• A device Reset, such as a POR and BOR

However, if the timer is disabled (TON = 0), then the

timer prescaler cannot be reset since the prescaler

clock is halted.

The TMR1 register is not cleared when the T1CON

9.3 Timer Operation During Sleep Mode

The timer operates during CPU Sleep mode, if:

• The timer module is enabled (TON = 1), and

• The timer clock source is selected as external

(TCS = 1), and

• The TSYNC bit (T1CON<2>) is asserted to a logic

‘0’ which defines the external clock source as

asynchronous.

When all three condi tio ns are true , the timer continu es

to count up to the Period register and be reset to

0x0000.

When a match between the timer and the Period

respective timer interrupt enable bit is asserted.

9.4 Timer Interrupt

The 16-bit timer has the ability to generate an

interrupt-on-period match. When the timer count

matches the Period register, the T1IF bit is asserted and

an interrupt is generated, if enabled. The T1IF bit must be

cleared in software. The timer interrupt flag, T1IF, is

located in the IFS0 Control register in the interrupt

controller.

When the Gated Time Accumulation mode is enabled,

an interrupt is also generated on the falling edge of the

gate signal (at the end of the accum ulation cycle) .

Enabling an interrupt is accomplished via the

respective timer interrupt enable bit, T1IE. The timer

interrupt enable bit is located in the IEC0 Control

9.5 Real-Time Clock

Timer1, when operating in Real-Time Clock (RTC)

mode, provides time of day and event time-stamping

capabilities. Key operational featur es of the RTC are:

• Operation from 32 kHz LP oscillator

• 8-bit prescaler

• Low powe r

• Real-Time Clock interrupts

These operating modes are de termined by setting the

appropriate bit(s) in the T1CON register.

FIGURE 9-2: REC OMMENDE D

COMPONENTS FOR

TIMER1 LP OSCILLATOR

RTC

9.5.1 RTC OSCILLATOR OPERATION

When the TON = 1, TCS = 1 and TGATE = 0, the timer

increments on the rising edge of the 32 kHz LP oscilla-

tor output signal, up to the value specified in the Period

The TSYNC bit must be asserted to a logic ‘0’

(Asynchronous mode) for correct operation.

Enabling the LPOSCEN bit (OSCCON<1>) disables

the normal Timer and Counter modes and enables a

timer carry-out wake-up event.

When the CPU enters Sleep mode, the RTC continues

to operate, provided the 32 kHz external crystal

oscillator is active and the control bits have not been

changed. The TSIDL bit should be cleared to ‘0’ in

order for RTC to continue operation in Idle mode.

9.5.2 RTC INTERRUPTS

When an interrupt event occurs, the resp ective interrupt

flag, T1IF, is asserted and an interrupt is generated if

enabled. The T1IF bit must be cleared in software. The

respective Timer interrupt flag, T1IF, is located in the

IFS0 register in the interrupt controller.

SOSCI

SOSCO

dsPIC30FXXXX

32.768 kHz

XTAL

C1 = C2 = 18 pF; R = 100K

dsPIC30F2011/2012/3012/3013

Enabling an interrupt is accomplished via the

respective timer interrupt enable bit, T1IE. The timer

interrupt enable bit is located in the IEC0 Control

dsPIC30F2011/2012/3012/3013

TABLE 9-1: TIMER1 REGISTER MAP

SFR Name Addr. Bit 15 Bit 14 Bi t 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

TMR1 0100 T imer1 Register uuuu uuuu uuuu uuuu

PR1 0102 Period Register 1 1111 1111 1111 1111

T1CON 0104 TON —TSIDL— — — — — — TGATE TCKPS1 TCKPS0 — TSYNC TCS —0000 0000 0000 0000

Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’

Note: Refer to the “dsPIC30F Family Reference Manual” (DS70 046) for descriptions of register bit fields.

dsPIC30F2011/2012/3012/3013

10.0 TIMER2/3 MODULE

This section describes the 32-bit general purpose

Timer module (Timer2/3) and associated Operational

modes. Figure 10-1 depicts the simplified block

diagram of the 32-bit Timer2/3 module. Figure 10-2

and Figure 10-3 show Timer2/3 configured as two

independent 16-bit timers, Timer2 and Timer3,

respectively.

The Timer2/3 module is a 32-bit timer (which can be

configured as two 16-bit timers) with selectable

operating modes. These timers are utilized by other

peripheral modules, such as:

• Input Capture

• Output Com pare/Simpl e PWM

The following sections provide a detailed description,

including setup and Control registers, along with

associated block diagrams for the operational modes of

the timers.

The 32-bit timer has the following modes:

• Two independent 16-bit timers (Timer2 and

Timer3) with all 16-bit operating modes (except

Asynchronous Counter mode)

• Single 32-bit timer operation

• Single 32-bit synchronous counter

Further, the following operational characteristics are

supported:

• ADC event trigger

• Timer gate operation

• Selectable prescaler settings

• Timer operation during Idle and Sleep modes

• Interrupt on a 32-bit period register match

These operating modes a re determined by setting the

appropriate bit(s) in the 16-bit T2CON and T3CON

SFRs.

For 32-bit timer/counter operation, Timer2 is the ls word

and Timer3 is the ms word of the 32-bit timer.

16-bit Timer Mode: In the 16-bit mode, Timer2 and

Timer3 can be configured as two independent 16-bit

timers. Each timer can be set up in either 16-bit Timer

mode or 16-bit Synchronous Counter mode. See

Section 9.0 “Timer1 Module” for det ai ls on th ese two

operating modes.

The only functional difference between Timer2 and

Timer3 is that Timer2 provides synchronization of the

clock prescaler output. This is useful for high frequency

external clock inputs.

32-bit Timer Mode: In the 32-bit T imer mode, the timer

increments on every instruction cycle, up to a match

value preloaded into the combined 32-bit Period

count.

For synchronous 32-bit reads of the Timer2/Timer3

pair , reading the ls word (TMR2 register) causes the ms

word to be read and latched into a 16-bit holding

For synchronous 32-bit writes, the holding register

(TMR3HLD) must first be written to. When followed by

a write to the TMR2 register , the contents of TMR3HLD

is transferred and latched into the MSB of the 32-bit

timer (TMR3).

32-bit Synchronous Counter Mode: In the 32-bit

Synchronous Counter mode, the timer increments on

the rising edge of the applied external clock signal

which is synchronized with the internal phase clocks.

The timer counts up to a match value preloaded in the

combined 32-bit period register, PR3/PR2, then resets

to ‘0’ and continues.

When the timer is configured for the Synchronous

Counter mode of operation and the CPU go es into the

Idle mode, the timer stops incrementing unless the

TSIDL bit (T2CON<13>) = 0. If TSIDL = 1, the timer

module logic resumes the incrementing sequence

upon termination of the CPU Id le mode.

Note: This data sheet summarizes features of

this group of dsPIC30F devices and is not

intended to be a complete reference

source. For more information on the CPU,

peripherals, register descriptions and

general device functionality, refer to the

“dsPIC30F Family Reference Manual

“(DS70046).

Note: For 32-bit timer operation, T3CON control

bits are ignored. Only T2CON control bits

are used for setup and control. Timer2

clock and gate inputs are utilized for the

32-bit timer module, but an interrupt is

generated with the Timer3 interrupt flag

(T3IF) and the interrupt is enabled with the

Timer3 interrupt enable bit (T3IE).

dsPIC30F2011/2012/3012/3013

FIGURE 10-1: 32-BIT TIMER2/3 BLOCK DIAGRAM

TMR3 TMR2

T3IF

Equal Comparator x 32

PR3 PR2

Reset

LSB MSB

Event Flag

Note: Timer Configuration bit T32 (T2CON<3>) must be set to ‘1’ for a 32-bit timer/counter operatio n. All control

bits are respective to the T2CON register.

Data Bus<15:0>

Read TMR2

Write TMR2 16

TGATE (T2CON<6>)

(T2CON<6>)

TGATE

TON TCKPS<1:0>

TCY

TCS

1 x

0 1

TGATE

0 0

Gate

T2CK

Sync

ADC Event Trigger

Sync

TMR3HLD

Prescaler

1, 8, 64, 256

dsPIC30F2011/2012/3012/3013

FIGURE 10-2: 16-BIT TIMER2 BLOCK DIAGRAM

FIGURE 10-3: 16-BIT TIMER3 BLOCK DIAGRAM

TON

Sync

PR2

T2IF

Equal Comparator x 16

TMR2

Reset

Event Flag TGATE

TCKPS<1:0>

TGATE

TCY

TCS

1 x

0 1

TGATE

0 0

Gate

T2CK

Sync Prescaler

1, 8, 64, 256

TON

PR3

T3IF

Equal Comparator x 16

TMR3

Reset

Event Flag TGATE

TCKPS<1:0>

TGATE

TCY

TCS

1 x

0 1

TGATE

0 0

T3CK

ADC Event Trigger

Sync

Prescaler

1, 8, 64, 256

dsPIC30F2011/2012/3012/3013

10.1 Timer Gate Operation

The 32-bit timer can be placed in the Gated Time

Accumulation mode. This mode allows the internal TCY

to increment the respective timer when the gate input

signal (T2CK pin) is asserted high. Control bit, TGAT E

(T2CON<6>), must be set to enable this mode. When

in this mode, Timer2 is the originating clock source.

The TGATE setting is ignored for Timer3. The timer

must be enabled (TON = 1) and the timer clock source

set to internal (TCS = 0).

The falling edge of the external signal terminates the

count operation but does not reset the timer. The user

must reset the timer in order to start counting from zero.

10.2 ADC Event Trigger

When a match occurs between the 32-bit timer

(TMR3/TMR2) and the 32-bit combined period register

(PR3/PR2), or between the 16-bit ti mer TMR3 and the

16-bit period register PR3, a special ADC trigger event

signal is generated by Timer3.

10.3 Timer Prescaler

The input clock (F OSC/4 or external clock) to the timer

has a prescale option of 1:1, 1:8, 1:64, and 1:256,

selected by control bits, TCKPS<1:0> (T2CON<5:4>

and T3CON<5:4>). For the 32-bit timer operation, the

originating clock source is Timer2. The prescaler

operation for Timer3 is not applicable in this mode. The

prescaler counter is cleared when any of the followin g

occurs:

• A write to the TMR2/TMR3 register

• A write to the T2CON/T3CON regi ste r

• A device Reset, such as a POR and BOR

However, if the timer is disabled (TON = 0), the Timer

2 prescaler cannot be reset since the prescaler clock is

halted.

TMR2/TMR3 is not cleared when T2CON/T3CON is

written.

10.4 Timer Operation During Sleep

Mode

The timer does not operate during CPU Sleep mode

because the internal clocks are disabled.

10.5 Timer Interrupt

The 32-bit timer module can generate an

interrupt-on-period match or on the falling edge of the

external gate signal. When the 32-bit timer count

matches the respective 32-bit period register, or the

falling edge of the external “gate” signal is detected, the

T3IF bit (IFS0<7>) is asserted and an interrupt is

generated if enabled. In this mode, the T3IF interrupt

flag is used as the source of the interrupt. The T 3IF bit

must be cleared in software.

Enabling an interrupt is accomplished via the

respective timer interrupt enable bit, T3IE (IEC0<7>).

dsPIC30F2011/2012/3012/3013

TABLE 10-1: TIMER2/3 REGISTER MAP

SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

TMR2 0106 T imer2 Register uuuu uuuu uuuu uuuu

TMR3HLD 0108 T imer3 Holding Register (for 32-bit timer operations only) uuuu uuuu uuuu uuuu

TMR3 010A T imer3 Register uuuu uuuu uuuu uuuu

PR2 010C Period Register 2 1111 1111 1111 1111

PR3 010E Pe riod Register 3 1111 1111 1111 1111

T2CON 0110 TON —TSIDL— — — — — — TGATE TCKPS1 TCKPS0 T32 —TCS —0000 0000 0000 0000

T3CON 0112 TON —TSIDL— — — — — — TGATE TCKPS1 TCKPS0 ——TCS —0000 0000 0000 0000

Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’

Note: Refer to the “dsPIC30F Family Reference Manual” (DS70 046) for descriptions of register bit fields.

dsPIC30F2011/2012/3012/3013

NOTES:

dsPIC30F2011/2012/3012/3013

11.0 INPUT CAPTURE MODULE

This section describes the input capture module and

associated operational modes. The features provided

by this module are useful in applications requiring

frequency (period) and pulse measurement.

Figure 11-1 depicts a block diagram of the input

capture module. Input capture is useful for such modes

as:

• Frequency/Period/Pulse Measurements

• Additional Sources of External Interrupts

Important operational features of the input capture

module are:

• Simple Capture Event mode

• Timer2 and Timer3 mode selection

• Interrupt on input capture eve nt

These operating modes a re determined by setting the

appropriate bits in the IC1CON and IC2CON registers.

The dsPIC30F2011/2012/3012/3013 devices have two

capture channels.

11.1 Simple Capture Event Mode

The simple capture events in the dsPIC30F product

family are:

• Capture every falling edge

• Capture every rising edge

• Capture every 4t h ri si ng ed ge

• Capture every 16th rising edge

• Capture every rising and falling edge

These simple Input Capture modes are configured by

setting the appropriate bits, ICM<2:0> (ICxCON<2:0>).

11.1.1 CAPTURE PRESCALER

There are four input capture prescaler settings

specified by bits ICM<2:0> (ICxCON<2:0>). Whenever

the capture channel is turned off, the prescaler counter

is cleared. In addition, any Reset clears the prescaler

counter.

FIGURE 11-1: INPUT CAPTURE MODE BLOCK DIAGRAM(1)

Note: This data sheet summarizes features of

this group of dsPIC30F devices and is not

intended to be a complete reference

source. For more information on the CPU,

peripherals, register descriptions and

general device functionality, refer to the

“dsPIC30F Family Reference Manual”

(DS70046).

ICxBUF

Prescaler

ICx pin

ICM<2:0>

Mode Select

Note 1: Where ‘x’ is shown, reference is made to the registers or bits associated to the respective input capture

channel (1 or 2).

Set Flag

ICxIF

ICTMR

T2_CNT T3_CNT

Edge

Detection

Logic

Clock

Synchronizer

1, 4, 16

From GP Timer Module

16 16

FIFO

R/W

Logic

ICI<1:0>

ICBNE, ICOV

ICxCON Interrupt

Logic

Set Flag

ICxIF

Data Bus

dsPIC30F2011/2012/3012/3013

11.1.2 CAPTURE BUFFER OPERATION

Each capture channel has an associated FIFO buffer

which is four 16-bit words deep. There are two status

flags which provide status on the FIFO buffer:

• ICBNE – Inp ut Ca pture Buffer Not Empty

• ICOV – Input Capture Overflow

The ICBNE is set on the first input capture event and

remains set until all capture events have been read

from the FIFO. As each word is read from the FIFO, the

remaining words are advanced by one position within

the buffer.

In the event that the FIFO is full with four capture

events, and a fifth capture event occurs prior to a read

of the FIFO, an overflow condition occurs and the ICOV

bit is set to a logic ‘1’. The fifth capture event is lost and

is not stored in the FIFO. No additional events are

captured until all four events have been read from the

buffer.

If a FIFO read is performed after the last read and no

new capture event has been received, the read will

yield indeterminate results.

11.1.3 TIMER2 AND TIMER3 SELECTION

MODE

The input capture module consists of up to 8 input

capture channels. Each channel can select between

one of two timers for the time base, Timer2 or Timer3.

Selection of the timer resource is accomplished

through SFR bit, ICTMR (ICxCON<7>). Timer3 is the

default timer resource available for the input capture

module.

11.1.4 HALL SENSOR MODE

When the input capture module is set for capture on

every edge, rising and falling, ICM<2:0> = 001, the

following operations are performed by the input capture

logic:

• The input capture interrupt flag is set on every

edge, rising and falling.

• The interrupt on Capture mode setting bits,

ICI<1:0>, is ignored since every capture

generates an interrupt.

• A capture overflow condition is not generated in

this mode.

11.2 Input Capture Operation During

Sleep and Idle Modes

An input capture event generates a devi ce wake-u p or

interrupt, if enabled, if the device is in CPU Idle or Sleep

mode.

Independent of the timer being enabled, the input

capture module wakes up from the CPU Sleep or Idle

mode when a capture event occurs if ICM<2:0> = 111

and the interrupt enable bit is asserted. The same

wake-up can generate an interrupt if the conditions for

processing the interrupt have been satisfied.

The wake-up feature is useful as a method of adding

extra external pin interrupts.

11.2.1 INPUT CAPTURE IN CPU SLEEP

MODE

CPU Sleep mode allows input capture module

operation with re duced func tionality. In the CPU Sleep

mode, the ICI<1:0> bits are not applicable and the input

capture module can only function as an external

interrupt source.

The capture module must be configured for interrupt

only on rising edge (ICM<2:0> = 111) in order for the

input capture module to be used while the device is in

Sleep mode. The prescale settings of 4:1 or 16:1 are

not applicable in this mode.

11.2.2 INPUT CAPTURE IN CPU IDLE

MODE

CPU Idle mode allows inpu t capture module operation

with full functionality. In the CPU Idle mode, the Interrupt

mode selected by the ICI<1:0> bits is applicable, as well

as the 4:1 and 16:1 capture prescale settings which are

defined by control bits ICM<2:0>. This mode requires

the selected timer to be enabled. Moreover , the ICSIDL

bit must be asserted to a logic ‘0’.

If the input capture module is defined as

ICM<2:0> = 111 in CPU Idle mode, the input capture

pin serves only as an external interrupt pin.

11.3 Input Capture Interrupts

The input capture channels have the ability to generate

an interrupt based on the selected number of capture

events. The selection number is set by control

bits, ICI<1:0> (ICxCON<6:5>).

Each channel provides an interrupt flag (ICxIF) bit. The

respective capture channel interrupt flag is located in

the corresponding IFSx register.

Enabling an interrupt is accomplished via the

respective capture channel interrupt enable (ICxIE) bit.

The capture interrupt enable bit is located in the

corresponding IEC Control register.

dsPIC30F2011/2012/3012/3013

TABLE 11-1: INPUT CAPTURE REGISTER MAP

SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

IC1BUF 0140 Input 1 Capture Register uuuu uuuu uuuu uuuu

IC1CON 0142 ——ICSIDL— — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000

IC2BUF 0144 Input 2 Capture Register uuuu uuuu uuuu uuuu

IC2CON 0146 ——ICSIDL— — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000

Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’

Note: Refer to the “dsPIC30F Family Reference Manual” (DS70 046) for descriptions of register bit fields.

dsPIC30F2011/2012/3012/3013

NOTES:

dsPIC30F2011/2012/3012/3013

12.0 OUTPUT COMPARE MODULE

This section describes the output compare module and

associated operational modes. The features provided

by this module are useful in applications requiring

operational modes, such as:

• Generation of Variable Width Output Pulses

• Power Factor Correction

Figure 12-1 depicts a block diagram of the output

compare module.

The key operational features of the output compare

module include:

• Timer2 and Timer3 Selection mode

• Simple Output Compare Match mode

• Dual Output Compare Match mode

• Simple PWM mode

• Output Compare During Sleep and Idle modes

• Interrupt on Output Compare/PWM Event

These operating modes a re determined by setting the

appropriate bits in the 16-bit OC1CON and OC2CON

registers. The dsPIC30F2011/2012/3012/3013 devices

have 2 compare channels.

OCxRS and OCxR in Figure 12-1 represent the Dual

Compare registers. In the Dual Compare mode, the

OCxR register is used for the first compare and OCxRS

is used for the second compare.

FIGURE 12-1: OUTPUT COMPARE MODE BLOCK DIAGRAM(1)

Note: This data sheet summarizes features of

this group of dsPIC30F devices and is not

intended to be a complete reference

source. For more information on the CPU,

peripherals, register descriptions and

general device functionality, refer to the

“dsPIC30F Family Reference Manual”

(DS70046).

OCxR

Comparator

Output

Logic QS

OCM<2:0>

Output OCx

Set Flag bit

OCxIF

OCxRS

Mode Select

Note 1: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare

channel (1 or 2).

OCFA

OCTSEL 01

T2P2_MATCHTMR2<15:0 TMR3<15:0> T3P3_MATCH

From GP

(for x = 1, 2, 3 or 4)

Timer Module

Enable

dsPIC30F2011/2012/3012/3013

12.1 Timer2 and T imer3 Selection Mode

Each output compare channel can select between one

of two 16-bit timers, T imer2 or Timer3.

The selection of the timers is controlled by the OCTSEL

bit (OCxCON<3>). T imer2 is the default timer resource

for the output compare module.

12.2 Simple Output Compare Match

Mode

When control bits OCM<2:0> (OCxCON<2:0>) = 001,

010 or 011, the selected output compare channel is

configured for one of three simple Output Compare

Match modes:

• Compare forces I/O pin low

• Compare forces I/O pin high

• Compare toggles I/O pin

The OCxR register is used in these modes. The OCxR

selected incrementing timer count. When a compare

occurs, one of these Compare Match modes occurs. If

the counter resets to zero before reaching the val ue i n

OCxR, the state of the OCx pin remains unchanged.

12.3 Dual Output Compare Match Mode

When control bits OCM<2:0> (OCxCON<2:0>) = 100

or 101, the selected output compare channel is

configured for one of two Dual Output Compare modes,

which are:

• Single Output Pulse mode

• Continuous Output Pulse mode

12.3.1 SINGLE PULSE MODE

For the user to configure the module for the generation

of a single output pulse, the following steps are

required (assuming timer is off):

• Determine instruction cycle time TCY.

• Calculate desired pulse width value based on TCY.

• Calculate time to start pulse from timer st art value

of 0x0000.

• Write pulse width start and stop times into OCxR

and OCxRS Compare registers (x denotes

channel 1 to N).

• Set Timer Period register to value equal to or

greater than value in OCxRS Compare register.

• Set OCM<2:0> = 100.

• Enable timer, TON bit (TxCON<15>) = 1.

To initiate another single pulse, issue another write to

set OCM<2:0> = 100.

12.3.2 CONTINUOUS PULSE MODE

For the user to configure the module for the generation

of a continuous stream of ou tput pulses, the following

steps are required:

• Determine instruction cycle time TCY.

• Calculate desired pul se value based on TCY.

• Calculate timer to start pulse width from timer st art

value of 0x0000.

• Write pulse width start and stop times into OCxR

and OCxRS (x denotes channel 1 to N) Compare

registers, respectively.

• Set Timer Period register to value equal to or

greater than value in OCxRS Compare register.

• Set OCM<2: 0> = 101.

• Enable timer, TON bit (TxCON<15>) = 1.

12.4 Simple PWM Mode

When control bits OCM<2:0> (OCxCON<2:0>) = 110

or 111, the selected output compare channel is

configured for the PWM mode of operation. When

configured for the PWM mode of operation, OCxR is

the main latch (read-only) and OCxRS is the secondary

latch. This enables glitchless PWM transitions.

The user must perform the following steps in order to

configure the output compare module for PWM

operation:

1. Set the PWM period by writing to the appropriate

period register.

2. Set the PWM duty cycle by writing to the OCxRS

3. Configure the output compare module for PWM

operation.

4. Set the TMRx prescale value and enable the

Timer, TON bit (TxCON<15>) = 1.

12.4.1 INPUT PIN FAULT PROTECTION

FOR PWM

When control bits OCM<2:0> (OCxCON<2:0> ) = 111,

the selected output compare channel is again

configured for the PWM mode of operation with the

additional feature of input Fault protection. While in this

mode, if a logic ‘0’ is detecte d on the OCFA /B pin, the

respective PWM output pin is placed in the high

impedance input state. The OCFLT bit (OCxCON<4>)

indicates whether a Fault condition has occurre d. This

state is maintained until both of the following events

have occurred:

• The external Fault condition has been removed.

• The PWM mode has been re-enabled by writing

to the appropriate control bits.

dsPIC30F2011/2012/3012/3013

12.4.2 PWM PERIOD

The PWM period is specified by writing to the PRx

Equation 12-1.

EQUATION 12-1:

PWM frequency is defined as 1/[PWM period].

When the selected TMRx is equal to its respective

period register , PRx, the following four events occur on

the next increment cycle:

• TMRx is cleared.

• The OCx pin is set.

- Exception 1: If PWM duty cycle is 0x0000,

the OCx pin remains low.

- Exception 2: If duty cycle is greater than PRx,

the pin remains high.

• The PWM duty cycle is latched from OCxRS into

OCxR.

• The corresponding timer interrupt flag is set.

See Figure 12-2 for key PWM period comparisons.

Timer3 is referred to in Figure 12-2 for clarity.

FIGURE 12-2: PWM OUTPUT TIMING

PWM period = [(PRx) + 1] • 4 • Tosc •

(TMRx pr escale value)

Period

Duty Cycle

TMR3 = Duty Cycle TMR3 = Duty Cycle

TMR3 = PR3

T3IF = 1

(Interrupt Flag)

OCxR = OCxRS

TMR3 = PR3

(Interrupt Flag)

OCxR = OCxRS

T3IF = 1

(OCxR) (OCxR)

dsPIC30F2011/2012/3012/3013

12.5 Output Compare Operation During

CPU Sleep Mode

When the CPU enters Sleep mode, all internal clocks

are stopped. Therefore, when the CPU enters the

Sleep state, the output compare channel drives the pin

to the active state that was observed pri or to entering

the CPU Sleep state.

For example, if the pin was high when the CPU entered

the Sleep state, the pin remains high. Likewise, if the

pin was low when the CPU entered the Sleep state, the

pin remains low. In either case, the output compare

module resumes operation when the device wakes up.

12.6 Output Compare Operation During

CPU Idle Mode

When the CPU enters the Idle mode, the output

compare module can operate with full functionality.

The output compare channel operates during the CPU

Idle mode if the OCSIDL bit (OCxCON<13>) is at logic

‘0’ and the selected time base (Timer2 or Timer3) is

enabled and the TSIDL bit of the selected timer i s set

to logic ‘0’.

12.7 Output Compare Interrupts

The output compare channels have the ability to

generate an interrupt on a compare match, for

whichever Match mode has been selected.

For all modes except the PWM mode, when a compare

event occurs, the respective interrupt flag (OCxIF) is

asserted and an interrupt is generated if enabl ed. The

OCxIF bit is located in the corresponding IFS register

and must be cleared in software. The interrupt is

enabled via the respective compare interrupt enable

(OCxIE) bit located in the corresponding IEC Control

For the PWM mode, when an event occurs, the

respective timer interrupt flag (T2IF or T3IF) is asserted

and an interrupt is generated if enabled. The IF bit is

located in the IFS0 register and must be cleared in

software. The interrupt is enabled via the respective

timer interrupt enable bit (T2IE or T3IE) located in the

IEC0 Control register. The output compare interrupt

flag is never set during the PWM mode of operation.

dsPIC30F2011/2012/3012/3013

TABLE 12-1: OUTPUT COMPARE REGISTER MAP

SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

OC1RS 0180 Output Compare 1 Secondary Register 0000 0000 0000 0000

OC1R 0182 Output Compare 1 Main Regist er 0000 0000 0000 0000

OC1CON 0184 ——OCSIDL— — — — — — — — OCFLT OCTSEL OCM<2:0> 0000 0000 0000 0000

OC2RS 0186 Output Compare 2 Secondary Register 0000 0000 0000 0000

OC2R 0188 Output Compare 2 Main Regist er 0000 0000 0000 0000

OC2CON 018A ——OCSIDL— — — — — — — — OCFLT OCTSEL OCM<2:0> 0000 0000 0000 0000

Legend: — = unimplemented bit, read as ‘0’

Note: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.

dsPIC30F2011/2012/3012/3013

NOTES:

dsPIC30F2011/2012/3012/3013

13.0 SPI™ MODULE

The Serial Peripheral Interface (SPI™) module is a

synchronous serial interface. It is useful for

communicating with other periph eral devices, such as

EEPROMs, shift registers, display drivers and A/D

converters, or other microcontrollers. It is compatible

with Motorola's SPI and SIOP interfaces. The

dsPIC30F2011/2012/3012/3013 devices feature one

SPI module, SPI1.

13.1 Operating Function Description

Figure 13-1 is a simplified block diagram of the SPI

module, which consists of a 16-bit shift register,

SPI1SR, used for shifting data in and out, and a buffer

shown) configures the module. Additionally, status

conditions.

Four I/O pins comprise the serial interface:

• SDI1 (serial data input)

• SDO1 (serial data output)

• SCK1 (shift clock input or output)

• SS1 (active-low slave select).

In Master mode operation, SCK1 is a clock output. In

Slave mode, it is a clock input.

A series of eight (8) or sixteen (16) clock pulses shift

out bits from the SPI1SR to SDO1 pin and

simultaneously shift in data from SDI1 pin. An interrupt

is generated when the transfer is complete and the

interrupt flag bit (SPI1IF) is set. This interrupt can be

disabled through the interrupt enable bit, SPI1IE.

The receive operation is double-buffered. When a

complete byte is received, it is transferred from SPI1SR

to SPI1BUF.

If the receive buffer is full when new data is being

transferred from SPI1SR to SPI1BUF, the module will

set the SPIROV bit indicating an overflow condition.

The transfer of the data from SPI1SR to SPI1BUF is not

completed and the new data is lost. The module will not

respond to SCL tra nsitions while SPIROV is ‘ 1’, effec-

tively disabling the module until SPI1BUF is read by

user software.

Transmit writes are also double-buffered. The user

writes to SPI1BUF. When the master or slave transfer

is completed, the contents of the shift register

(SPI1SR) are moved to the receive buffer. If any

transmit data has been written to the buffer register , the

contents of the transmit buffer are moved to SPI1SR.

The received data is thus placed in SPI1BUF and the

transmit data in SPI1SR is ready for the next transfer.

Note: This data sheet summarizes features of

this group of dsPIC30F devices and is not

intended to be a complete reference

source. For more information on the CPU,

peripherals, register descriptions and

general device functionality, refer to the

“dsPIC30F Family Reference Manual”

(DS70046).

Note: See “dsPIC30F Family Reference

Manual” (DS70046) for detailed

information on the control and status

registers.

Note: Both the transmit buffer (SPI1TXB) and

the receive buffer (SPI1RXB) are mapped

to the same register address, SPI1BUF.

dsPIC30F2011/2012/3012/3013

FIGURE 13-1: SPI BLOCK DIAGRAM

Figure 13-2 depicts the a master/slave connection

between two processors. In Master mode, the clock is

generated by prescaling the system clock. Data is

transmitted as soon as a value is written to SPI1BUF.

The interrupt is generated at the middle of the transfer

of the last bit.

In Slave mode, data is transmitted and received as

external clock pulses appear on SCK. Again, the

interrupt is generated when the last bit is latched. If

SS1 control is enabled, then transmission and

reception are enabled only when SS1 = low . The SDO1

output will be disabled in SS1 mode with SS1 high.

The clock provided to the module is (FOSC/4). This

clock is then prescaled by the primary (PPRE<1:0>)

and the secondary (SPRE<2:0>) prescale factors. The

CKE bit determines whether transmit occurs on

transition from active clock state to Idle clock state, or

vice versa. The CKP bit selects the Idle state (high or

low) for the clock.

13.1.1 WORD AND BYTE

COMMUNICATION

A control bit, MODE16 (SPI1CON<10>), allows the

module to communicate in either 16-bit o r 8-bit mode.

16-bit operation is identical to 8-bit operation except

that the number of bits transmitted is 16 instead of 8.

The user software must disable the module prior to

changing the MODE16 bit. The SPI module is reset

when the MODE16 bit is changed by the user.

A basic difference between 8-bit and 16-bit operation is

that the data is transmitted out of bit 7 of the SPI1SR

for 8-bit operation, and data is transmitted out of bit 15

of the SPI1SR for 16-bit operation. In both modes, data

is shifted into bit 0 of the SPI1SR.

13.1.2 SDO1 DISABLE

A control bit, DISSDO, is provided to the SPI1CON

will allow the SPI module to be connected in an input

only configuration. SDO1 can also b e used for general

purpose I/O.

13.2 Framed SPI Support

The module supports a basic framed SPI protocol in

Master or Slave mode. The control bit, FRMEN,

enables framed SPI support and causes the SS1 pin to

perform the Frame Synchronization Pulse (FSYNC)

function. The control bit, SPIFSD, determines wh ether

the SS1 pin is an input or an output (i.e., whether the

module receives or generates the Frame

Synchronization Pulse). The frame pulse is an

active-high pulse for a single SPI clock cycle. When

Frame Synchronization is enabled, the data

transmission starts only on the subsequent transmit

edge of the SPI clock.

Read Write

Internal

Data Bus

SDI1

SDO1

SS1

SCK1

SPI1SR

SPIxBUF

bit 0

Shift

Clock Edge

Select

FCY

Primary

1, 4, 16, 64

Enable Master Clock

Prescaler

Secondary

Prescaler

1:1 – 1:8

SS & FSYNC

Control Clock

Control

Transmit

SPIxBUF

Receive

dsPIC30F2011/2012/3012/3013

FIGURE 13-2: SPI MASTER/SLAVE CONNECTION

13.3 Slave Select Synchronization

The SS1 pin allows a Synchronous Slave mode. The

SPI must be configured in SPI Slave mode with SS1

pin control enabled (SSEN = 1). When the SS1 pin is

low, transmission and reception are enabled and the

SDOx pin is driven. When SS1 pin goes high, the

SDOx pin is no longer driven. Also, the SPI module is

resynchronized, and all counters/control circuitry are

reset. Therefore, when the SS1 pin is asserted low

again, transmission/reception will begin at the MSb

even if SS1 had been de-asserted in the middle of a

transmit/receive.

13.4 SPI Operation During CPU Sleep

Mode

During Sleep mode, the SPI module is shut down. If the

CPU enters Sleep mode while an SPI transaction is in

progress, then the transmission and reception is

aborted.

The transmitter and receiver will stop in Sleep mode.

However , register contents are not affected by entering

or exiting Sleep mode.

13.5 SPI Operation During CPU Idle

Mode

When the device enters Idle mode, all clock sources

remain functional. The SPISIDL bit (SPI1STAT<13>)

selects if the SPI module will stop or continue on idle. If

SPISIDL = 0, the module will continue to operate when

the CPU enters Idle mode. If SPISIDL = 1, the module

will stop when the CPU enters Idle mode.

Serial Input Buffer

(SPI1BUF)

Shift Register

(SPI1SR)

MSb LSb

SDO1

SDI1

PROCESSOR 1

SCK1

SPI Master

Serial Input Buffer

(SPI1BUF)

Shift Register

(SPI1SR)

LSb

MSb

SDI1

SDO1

PROCESSOR 2

SCK1

SPI Slave

Serial Clock

dsPIC30F2011/2012/3012/3013

TABLE 13-1: SPI1 REGISTER MAP

SFR

Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset St ate

SPI1STAT 0220 SPIEN — SPISIDL — — — — — — SPIROV — — — —SPITBFSPIRBF0000 0000 0000 0000

SPI1CON 0222 — FRMEN SPIFSD — DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE2 SPRE1 SPRE0 PPRE1 PPRE0 0000 0000 0000 0000

SPI1BUF 0224 T ransmit and Receive Buf fer 0000 0000 0000 0000

Legend: — = unimplemented bit, read as ‘0’

Note: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.

dsPIC30F2011/2012/3012/3013

14.0 I2C™ MODULE

The Inter-Integrated Circuit (I2CTM) module provides

complete hardware support for both Slave and

Multi-Master modes of the I2C serial communication

standard, with a 16-bit interface.

This module offers the following key features:

•I

2C interface supporting both master and slave

operation.

•I

2C Slave mode supports 7-bit and 10-bit

addressing.

•I

2C Master mode supports 7-bit and 10-bit

addressing.

•I

2C port allows bidirectional transfers between

master and slaves.

• Serial clock synchronization for I2C port can be

used as a handshake mechanism to suspend and

resume serial transfer (SCLREL control).

•I

2C supports multi-master operation; detects bus

collision and will arbitrate accordingly.

14.1 Operating Function Description

The hardware fully implements all the master and slave

functions of the I2C Standard and Fast mode

specifications, as well as 7 and 10-bit addressing.

Thus, the I2C module can operate e ither as a slave or

a master on an I2C bus.

14.1.1 VARIOUS I2C MODES

The following types of I2C operation are supported:

•I

2C slave operation with 7-bit addressing

•I

2C slave operation with 10-bit addressing

•I

2C master operation with 7-bit or 10-bit addressing

See the I2C programmer ’s model (Figure 14-1).

14.1.2 PIN CONFIG URA TI ON IN I2C MODE

I2C has a 2-pin interface; the SCL pin is clock and the

SDA pin is data.

14.1.3 I2C REGISTERS

I2CCON and I2CSTA T are control and status registers,

respectively. The I2CCON register is readable and

writable. The lower 6 bits of I2CSTAT are read-only.

The remaining bits of the I2CSTAT are read/write.

I2CRSR is the shift register used for shifting data,

whereas I2CRCV is the buffer register to which data

bytes are written, or from which data bytes are read.

I2CRCV is the receive buffer as shown in Figure 14-1.

I2CTRN is the transmit register to which bytes are

written during a transmit operation, as shown in

Figure 14-2.

The I2CADD register holds the slave address. A St atus

bit, ADD10, indicates 10-bit Address mode. The

I2CBRG acts as the Baud Rate Generator reload

value.

In receive operations, I2CRSR and I2CRCV together

form a double-buffered receiver. When I2CRSR

receives a complete byte, it is transferred to I2CRCV

and an interrupt pulse is generated. During

transmission, the I2CTRN is not double-buffered.

FIGURE 14-1: PROGRAMMER’S MODEL

Note: This data sheet summarizes features of

this group of dsPIC30F devices and is not

intended to be a complete reference

source. For more information on the CPU,

peripherals, register descriptions and

general device functionality, refer to the

“dsPIC30F Family Reference Manual”

(DS70046).

Note: Following a Restart condition in 10-bit

mode, the user only needs to match the

first 7-bit address.

Bit 7 Bit 0 I2CRCV (8 bits)

Bit 7 Bit 0 I2CTRN (8 bits)

Bit 8 Bit 0 I2CBRG (9 bits)

Bit 15 Bit 0 I2CCON (16 bits)

Bit 15 Bit 0 I2CSTAT (16 bits)

Bit 9 Bit 0 I2CADD (10 bits)

dsPIC30F2011/2012/3012/3013

FIGURE 14-2: I2C™ BLOCK DI AGRAM

I2CRSR

I2CRCV

Internal

Data Bus

SCL

SDA

Shift

Match Detect

I2CADD

Start and

Stop bit Detect

Clock

Addr_Match

Clock

Stretching

I2CTRN LSB

Shift

Clock

Write

Read

BRG Down I2CBRG

Reload

Control

FCY

Start, Restart,

Stop bit Generate

Write

Read

Acknowledge

Generation

Collision

Detect

Write

Read

Write

Read

I2CCON

Write

Read

I2CSTAT

Control Logic

Read

LSB

Counter

dsPIC30F2011/2012/3012/3013

14.2 I2C Module Addresses

The I2CADD register contains the Slave mode

addresses. The register is a 10-bit regi ster.

If the A10M bit (I2CCON<10>) is ‘0’, the address is

interpreted by the module as a 7-bit address. When an

address is received, it is compared to the 7 LSb of the

I2CADD register.

If the A10M bit is ‘1’, the address is assumed to be a

10-bit address. When an address is received, it will b e

compared with the binary value ‘11110 A9 A8’ (where

A9 and A8 are two Most Signi ficant bits of I2CADD). If

that value matches, the next address will be compared

with the Least Significant 8 bits of I2CADD, as specified

in the 10-bit addressing protocol.

The 7-bit I2C Slave Addresses supported by the

dsPIC30F are shown in Table 14-1.

TABLE 14-1: 7-BIT I2C™ SLAVE

ADDRESSES

14.3 I2C 7-bit Slave Mode Operation

Once enabled (I2CEN = 1), the slave module w ill wait

for a Start bit to occur (i.e., the I2C module is ‘Idle’).

Following the detection of a Start bit, 8 bits are shifted

into I2CRSR and the address is compared against

I2CADD. In 7-bit mode (A10M = 0), bits I2CADD<6:0>

are compared against I2CRSR<7:1> and I2CR SR<0>

is the R_W bit. All incoming bits are sampled on the ris-

ing edge of SCL.

If an address match occurs, an acknowledgement will

be sent, and the slave event interrupt flag (SI2CIF) is

set on the falling edge of the ninth (ACK) bit. The

address match does not affect the contents of the

I2CRCV buffer or the RBF bit.

14.3.1 SLAVE TRANSMISSION

If the R_W bit received is a ‘1’, then the serial port wil l

go into Transmit mode. It will send ACK on the ninth bit

and then hold SCL to ‘0’ until the CPU responds by

writing to I2CTRN. SCL is released by setting the

SCLREL bit, and 8 bits of data are shifted out. Data bits

are shifted out on the falling edge of SCL, such that

SDA is valid during SCL high. The interrupt pulse is

sent on the falling edge of the ninth clock pulse,

regardless of the status of the ACK received from the

master.

14.3.2 SLAVE RECEPTION

If the R_W bit received is a ‘0’ during an address

match, then Receive mode is initiated. Incoming bits

are sampled on the rising edge of SCL. After 8 bits are

received, if I2CRCV is not full or I2COV is not set,

I2CRSR is transferre d to I2CRCV. ACK is sent on the

ninth clock.

If the RBF flag is set, indicating that I2CRCV is still

holding data from a previous operation (RBF = 1), then

ACK is not sent; however, the interrupt pulse is

generated. In the case of an overflow, the contents of

the I2CRSR are not loaded into the I2CRCV.

14.4 I2C 10-bit Slave Mode Operation

In 10-bit mode, the basic receive and transmit

operations are the same as in the 7-bit mode. However ,

the criteria for address match is more complex.

The I2C specification dictates that a slave must be

addressed for a write operation with two address bytes

following a Start bit.

The A10M bit is a control bit that signifies that the

address in I2CADD is a 10-bit address rather than a 7-bit

address. The address detection protocol for the first byte

of a message address is identical for 7-bit and 10-bit

messages, but the bits being compared are dif ferent.

I2CADD holds the entire 10-bit address. Upon

receiving an address following a Start bit, I2CRSR

<7:3> is compared against a literal ‘11110’ (the default

10-bit address) and I2CRSR<2:1> are compared

against I2CADD<9:8>. If a match occurs and if

R_W = 0, the interrupt pulse is sent. The ADD10 bit will

be cleared to indicate a partial address match. If a

match fails or R_W = 1, the ADD10 bit is cleared and

the module returns to the Idle state.

The low byte of the address is then received and

compared with I2CADD<7:0>. If an address match

occurs, the interrupt pulse is generated and the ADD10

bit is set, indicating a complete 10-bit address match. If

an address match did not occur, the ADD10 bit is

cleared and the module returns to the Idle state.

0x00 General call address or start byte

0x01-0x03 Reserved

0x04-0x07 Hs-mode Master codes

0x04-0x77 Valid 7-bit addresses

0x78-0x7b Valid 10-bit addresses (lower 7

bits)

0x7c-0x7f Reserved

Note: The I2CRCV will be loaded if the I2COV

bit = 1 and the RBF flag = 0. In this case,

a read of th e I2CRCV was performe d but

the user did not clear the state of the

I2COV bit before the next receive

occurred. The acknowledgement is not

sent (ACK = 1) and the I2CRCV is

updated.

dsPIC30F2011/2012/3012/3013

14.4.1 10-BIT MODE SLAVE

TRANSMISSION

Once a slave is addressed in this fashion with the full

10-bit address (we will refer to this state as

“PRIOR_ADDR_MATCH”), the master can begin

sending data bytes for a slave reception operation.

14.4.2 10-BIT MODE SLAVE RECEPTION

Once addressed, the master can generate a Repeated

Start, reset the high byte of the address and set the

R_W bit without generating a Stop bit, thus ini tiating a

slave transmit operation.

14.5 Automatic Clock Stretch

In the Slave modes, the module can synchronize buffer

reads and write to the master device by clock stretching.

14.5.1 TRANSMIT CLOCK STRETCHING

Both 10-bit and 7-bit Transmit modes implement clock

stretching by asserting the SCLREL bit after the falling

edge of the ninth clock, if the TBF bit is cleared,

indicating the buffer is empty.

In Slave Transmit modes, clock stretching is always

performed irrespective of the STREN bit.

Clock synchronization takes place following the ninth

clock of the transmit sequence. If the device samples

an ACK on the falling edge of the ninth clock and if the

TBF bit is still clear, then the SCLREL bit is

automatically cleared. The SCLREL being cleared to

‘0’ will assert the SCL line low . The user’s ISR must set

the SCLREL bit before transmission is allowed to

continue. By holding the SCL line low , the user has time

to service the ISR and load the contents of the I2CTRN

before the master device can initiate another transmit

sequence.

14.5.2 RECEIVE CLOCK STRETCHING

The STREN bit in the I2 CCON register can be used to

enable clock stretching in Slave Receive mode. When

the STREN bit is set, the SCL pin will be held low at the

end of each data receive sequence.

14.5.3 CLOCK STRETCHING DURING

7-BIT ADDRESSING (STREN = 1)

When the STREN bit is set in Slave Receive mode, the

SCL line is held low when the buffer register is full. The

method for stretching the SCL output is the same for

both 7 and 10-bit addressing modes.

Clock stretching takes place following the ninth clock of

the receive sequence. On the falling edge of the ninth

clock at the end of the ACK sequence, if the RBF bit is

set, the SCLREL bit is automatically cleared, forcing

the SCL output to be held low . The user’s ISR must set

the SCLREL bit before reception is allowed to continue.

By holding the SCL line low, the user has time to

service the ISR and read the contents of the I2CRCV

before the master device can initiate another receive

sequence. This will prevent buffer overruns from

occurring.

14.5.4 CLOCK STRETCHING DURING

10-BIT ADDRESSING (STREN = 1)

Clock stretching takes place automatically during the

addressing sequence. Because this module has a

the protocol to wait for the address to be updated.

After the address phase is complete, clock stretching

will occur on each data receive or transmit sequence as

was described earlier.

14.6 Software Controlled Clock

Stretching (STREN = 1)

When the STREN bit is ‘1’, the SCLREL bit may be

cleared by software to allow software to control the

clock stretching. The logic will synchronize writes to the

SCLREL bit with the SCL clock. Clearing the SCLREL

bit will not assert the SCL output until the module

detects a falling edge on the SCL output and SCL is

sampled low. If the SCLREL bit is cleared by the user

while the SCL line has been sampled low, the SCL

output will be asserted (held low). The SCL output wi ll

remain low until the SCLREL bit is set, and all other

devices on the I2C bus have de-asserted SCL. This

ensures that a write to the SCLREL bit will not violate

the minimum high time requirement for SC L.

If the STREN bit is ‘0’, a software write to the SCLREL

bit will be disregarded and have no effect on the

SCLREL bit.

Note 1: If the user loads the contents of I2CTRN,

setting the TBF bit before the falling edge

of the ninth clock, the SCLREL bit will not

be cleared and clock stretching will not

occur.

2: The SCLREL bit can be set in software,

regardless of the state of the TBF bit.

Note 1: If the user reads the contents of the

I2CRCV, clearing the RBF b it before the

falling edge of the ninth clock, the

SCLREL bit will not be cleared and clock

stretching will not occur.

2: The SCLREL bit can be set in software

regardless of the state of the RBF bit. The

user should be careful to clear the RBF

bit in the ISR before the next receive

sequence in order to prevent an overflow

condition.

dsPIC30F2011/2012/3012/3013

14.7 Interrupts

The I2C module gen erates two interrupt flags, MI2CIF

(I2C Master Interrupt Flag) and SI2CIF (I2C Slave

Interrupt Flag). The MI2CIF interrupt flag is activated

on completion of a master message event. The SI2CIF

interrupt flag is activated on detection of a message

directed to the slave.

14.8 Slope Control

The I2C standard requires slope control on the SDA

and SCL signals for Fast mode (400 kHz). The contro l

bit, DISSLW, enables the user to disable slew rate

control if desired. It is necessary to disable the slew

rate control for 1 MHz mode.

14.9 IPMI Support

The control bit, IPMIEN, enables the module to support

Intelligent Peripheral Management Interface (IPMI).

When this bit is set, the module accepts and acts upon

all addresses.

14.10 General Call Address Support

The general call address can address all devices.

When this address is used, all devices should, in

theory, respond with an acknowledgement.

The general call address is one of eight addresses

reserved for specific purposes by the I2C protocol. It

consists of all ‘0’s with R_W = 0.

The general call address is recognized when the

General Call Enable (GCEN) bit is set

(I2CCON<7> = 1). Following a S tart bit detection, 8 bits

are shifted into I2CRSR and the address is compared

with I2CADD, and is also compared with the general

call address which is fixed in hardware.

If a general call address match occurs, the I2CRSR is

transferred to the I2CRCV after the eighth clock, the RBF

flag is set and on the fallin g edge of the ninth bit (ACK

bit), the master event interrupt flag (MI2CIF) is set.

When the interrupt is serviced, the source for the

interrupt can be checked by reading the contents of the

I2CRCV to determine if the address was device

specific or a general call address.

14.11 I2C Master Support

As a master device, six operations are supported:

• Assert a Start condition on SDA and SCL.

• Assert a Restart condition on SDA and SCL.

• Write to the I2CTRN register initiating

transmission of data/address.

• Generate a Stop condition on SDA and SCL.

• Configure the I2C port to receive data.

• Generate an ACK condition at the end of a

received byte of data.

14.12 I2C Master Operation

The master device generates all of the serial clock

pulses and the Start and Stop conditions. A transfer is

ended with a Stop condition or with a Repeated Start

condition. Since the Repeated Start condition is also

the beginning of the next serial transfer , the I2C bus will

not be released.

In Master Transmitter mode, serial data is output

through SDA, while SCL outputs the serial clock. The

first byte transmitted contains the slave address of the

receiving device (7 bits) and the data direction bit. In

this case, the data direction bit (R_W) is logic ‘0’. Serial

data is transmitted 8 bits at a time. After each byte is

transmitted, an ACK bit is received. Start and Stop

conditions are output to indicate the beginning and the

end of a serial transfer.

In Master Receive mode, the first byte transmitted

contains the slave address of the transmitting device

(7 bits) and the data direction bit. In this case, the data

direction bit (R_W) is logic ‘1’. Thus, the first byte

transmitted is a 7-bit slave address, followed by a ‘1’ to

indicate receive bit. Serial data is received via SDA

while SCL outputs the serial clock. Serial data is

received 8 bits at a time. After each byte is received, an

ACK bit is transmitted. Start and Stop conditions

indicate the beginning and end of transmission.

14.12.1 I2C MASTER TRANSMISSION

Transmission of a data byte, a 7-bit address, or the sec-

ond half of a 10-bit address, is accomplished by simply

writing a value to I2CTRN register. The user should

only write to I2CTRN when the module is in a WAIT

state. This action will set the Buffer Full Flag (TBF) and

allow the Baud Ra te Generator to begin counting a nd

start the next transmission. Each bit of address/data

will be shifted out onto the SDA pin after the falling

edge of SCL is asserted. The Transmit Status Flag,

TRSTAT (I2CSTAT<14>), indicates that a master

transmit is in progress.

dsPIC30F2011/2012/3012/3013

14.12.2 I2C MASTER RECEPTION

Master mode reception is enabled by programming the

Receive Enable bit, RCEN (I2CCON<3>). The I2C

module must be Idle before the RCEN bit is set,

otherwise the RCEN bit will b e disre garded. The Baud

Rate Generator begins coun ting and on each rollover,

the state of the SCL pin ACK and data are shifted into

the I2CRSR on the rising edge of each clock.

14.12.3 BAUD RATE GENERATOR

In I2C Master mode, the reload value for the BRG is

located in the I2CBRG register. When the BRG is

loaded with this value, the BRG counts down to ‘0’ and

stops until another reload has taken place. If clock

arbitration is taking place, for instance, the BRG is

reloaded when the SCL pin is sampled high.

As per the I2C standard, FSCK may be 100 kHz or

400 kHz. How ever, the user can specify any baud rate

up to 1 MHz. I2CBRG values of ‘0’ or ‘1’ are illegal.

EQUATION 14-1: SERIAL CLOCK RATE

14.12.4 CLOCK ARBITRATION

Clock arbitration occurs when the master de-asserts

the SCL pin (SCL allowed to float high) during any

receive, transmit, or Restart/Stop condition. When the

SCL pin is allowed to float high, the Baud Rate

Generator (BRG) is suspended from counting until the

SCL pin is actually sampled high. When the SCL pin is

sampled high, the Baud Rate Generator is reloaded

with the contents of I2CBRG and begins counting. This

ensures that the SCL high time will always be at least

one BRG rollover count in the event that the clock is

held low by an external device.

14.12.5 MULTI-MASTER COMMUNICATION,

BUS COLLISION, AND BUS

ARBITRATION

Multi-master operation support is achieved by bus

arbitration. When the master outputs address/data bits

onto the SDA pin, arbitration takes place when the

master outputs a ‘1’ on SDA by letting SDA float high

while another master asserts a ‘0’. When the SCL pin

floats high, data should be stable. If the expected data

on SDA is a ‘1’ and the data sampled on the SDA

pin = 0, then a bus collision has taken place. The

master will set the MI2 CIF pulse and reset the master

portion of the I2C port to its Idle state.

If a transmit was in progress when the bus collision

occurred, the transmission is halted, the TBF flag is

cleared, the SDA and SCL lines are de-asserted and a

value can now be written to I2CTRN. When the user

services the I2C master event Interrupt Service

Routine, if the I2C bus is free (i.e., the P bit is set), the

user can resume communication by asserting a Start

condition.

If a Start, Restart, Stop or Acknowled ge condition was

in progress when the bus collision occurred, the

condition is aborted, the SDA and SCL lines are

de-asserted, and the respective control bits in the

I2CCON register are cleared to ‘0’. When the user

services the bus collision Interrupt Service Routine,

and if the I2C bus is free, the user can resume

communication by asserting a Start condition.

The master will continue to monitor the SDA and SCL

pins, and if a Stop condition occurs, the MI2CIF bit will

be set.

A write to the I2CTRN will start the transmission of data

at the first data bit regardless of whe re the transmitter

left off when bus collision occurred.

In a multi-master environment, the interrupt generation

on the detection of St art and S top conditions allows the

determination of when the bus is free. Control of the I2C

bus can be taken when the P b it is set i n the I2CSTAT

cleared.

14.13 I2C Module Operation During CPU

Sleep and Idle Modes

14.13.1 I2C OPERATION DURING CPU

SLEEP MODE

When the device enters Sleep mode, all clock sources

to the module are shut down and stay at logic ‘0’. If

Sleep occurs in the middle of a transmission and the

state machine is partially into a transmission as the

clocks stop, then the transmission is aborted. Similarly,

if Sleep occurs in the middle of a reception, then the

reception is aborted.

14.13.2 I2C OPERATION DURING CPU IDLE

MODE

For the I2C, the I2CSIDL bit selects if the module will

stop on Idle or continue on Idle. If I2CSIDL = 0, the

module will continue ope ration on assertio n of the Idle

mode. If I2CSIDL = 1, the module will stop on Idle.

I2CBRG = FCY FCY

FSCL 1,111,111 – 1

–

()

dsPIC30F2011/2012/3012/3013

TABLE 14-2: I2C REGISTER MAP

SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

I2CRCV 0200 — — — — — — — — Receive R e gi st e r 0000 0000 0000 0000

I2CTRN 0202 — — — — — — — — Transmit Register 0000 0000 1111 1111

I2CBRG 0204 — — — — — — — Baud Rate Generator 0000 0000 0000 0000

I2CCON 0206 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 0001 0000 0000 0000

I2CSTAT 0208 ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 IWCOL I2COV D_A P S R_W RBF TBF 0000 0000 0000 0000

I2CADD 020A — — — — — — Address Register 0000 0000 0000 0000

Legend: — = unimplemented bit, read as ‘0’

Note: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.

dsPIC30F2011/2012/3012/3013

NOTES:

dsPIC30F2011/2012/3012/3013

15.0 UNIVERSAL ASYNCHRONOUS

RECEIVER TRANSMITTER

(UART) MODULE

This section describes the Universal Asynchronous

Receiver/Transmitter Communications module. The

dsPIC30F2011/2012/3012 processors have one UART

module (UART1). The dsPIC30F3013 processor has

two UART modules (UART1 and UART2).

15.1 UART Module Overview

The key featur es of the UART module ar e:

• Full-duplex, 8 or 9-bit data communication

• Even, odd or no parity options (for 8-bit data)

• One or two Stop bits

• Fully integrated Baud Rate Generator with 16-bit

prescaler

• Baud rates range from 38 bps to 1.875 Mbps at a

30 MHz instruction rate

• 4-word deep transmit data buffer

• 4-word deep receive data buffer

• Parity, framing and buffer overrun error detection

• Support for interrupt only on address detect

(9th bit = 1)

• Separate transmit and receive interrupts

• Loopback mode for diagnostic support

• Alternate receive and transmit pins for UART1

FIGURE 15-1: UART TRANSMITTER BLOCK DIAGRAM

Note: This data sheet summarizes features of

this group of dsPIC30F devices and is not

intended to be a complete reference

source. For more information on the CPU,

peripherals, register descriptions and

general device functionality, refer to the

“dsPIC30F Family Reference Manual”

(DS70046).

Write Write

UTX8 UxTXREG Low Byte

Load TSR

Transmit Control

– Control TSR

– Control Buffer

– Generate Flags

– Generate Interrupt

Control and Status bits

UxTXIF

Data

‘0’ (Start)

‘1’ (Stop)

Parity Parity

Generator

T ransmit Shift Register ( UxTSR)

16 Divider

Control

Signals

16x Baud Clock

from Baud Rate

Generator

Internal Data Bus

UTXBRK

UxTX

Note: x = 1 or 2.

dsPIC30F2011/2012/3012/3013

FIGURE 15-2: UART RECEIVER BLOC K DIAGRAM

Read

URX8 UxRXREG Low Byte

Load RSR

UxMODE

Receive Buffer Control

– Generate Flags

– Generate Interrupt

UxRXIF

UxRX

· Start bit Detect

Receive Shift Register

16 Divider

Control

Signals

UxSTA

– Shift Data Characters

Read Read

Write Write

to Buffer

8-9

(UxRSR)

PERR

FERR

· Parity Check

· Stop bit Detect

· Shift Clock Generation

· Wake Logic

Internal Data Bus

LPBACK

From UxTX

16x Baud Clock from

Baud Rate Generator

dsPIC30F2011/2012/3012/3013

15.2 Enabling and Setting Up UART

15.2.1 ENABLING TH E UART

The UART module is enabled by setting the UARTEN

bit in the UxMODE register (where x = 1 or 2). Once

enabled, the UxTX and UxRX pins are configured as an

output and an input respectively, overriding the TRIS

and LAT register bit settings for the corresponding I/O

port pins. The UxTX pin is at logic ‘1’ when no

transmission is taking place.

15.2.2 DISABLING THE UART

The UART module is disabled by clearing the UARTEN

bit in the UxMODE register. This is the default state

after any Reset. If the UART is disabled, all I/O pins

operate as port pins under the control of the LAT and

TRIS bits of the corresponding port pins.

Disablin g the UART module resets the buf fers to empty

states. Any data characters in the buffers are lost and

the baud rate counter is reset.

All error and status flags associated with the UART

module are reset when the module is disabled. The

URXDA, OERR, FERR, PERR, UTXEN, UTXBRK and

UTXBF bits are cleared, whereas RIDLE and TRMT

are set. Other control bits, including ADDEN,

URXISEL<1:0>, UTXISEL, as well as the UxMODE

and UxBRG registers, are not affected.

Clearing the UARTEN bit while the UART is active will

abort all pending transmissions and receptions and

reset the module as defined above. Re-enabling the

UART will restart the UART in the same configuration.

15.2.3 ALTERNATE I/O

The alternate I/O function is enabled by setting the

ALTIO bit (UxMODE<10>). If ALTIO = 1, the UxATX

and UxARX pins (alternate transmit and alternate

receive pins, respectively) are used by the UART

module instead of the UxTX and UxRX pins. If

ALTIO = 0, the UxTX and UxRX pins are used by the

UART module.

15.2.4 SETTING UP DATA, PARITY AND

STOP BIT SELECTIONS

Control bits PDSEL<1:0> in the UxMODE register a re

used to select the data length and parity used in the

transmission. The data length may either be 8 bits with

even, odd or no parity, or 9 bits with no parity.

The STSEL bit determines whether one or two Stop bits

will be used during data transmission.

The default (power-on) setting of the UART is 8 bits, no

parity and 1 Stop bit (typically represented as 8, N, 1).

15.3 Transmitting Data

15.3.1 TRANSMITTING IN 8-BIT DATA

MODE

The following steps must be performed to transmit 8-bit

data:

1. Set up the UART:

First, the data length, parity and number of S top

bits must be selected. Then, the transmit and

receive interrupt enable and priority bits are

setup in the UxMODE and UxSTA registers.

Also, the appropriate baud rate value must be

written to the UxBRG register.

2. Enable the UART by setting the UARTEN bit

(UxMODE<15>).

3. Set the UTXEN bit (UxSTA<10>), thereby

enabling a transmission.

4. Write the byte to be transmitted to the lower byte

of UxTXREG. The value will be transferred to the

Transmit Shift register (UxTSR) immediately

and the serial bit stream will start shifting out

during the next rising edge of the baud clock.

Alternatively, the data byte may be written while

UTXEN = 0, following which, the user may set

UTXEN. This will cause the serial bit stream to

begin immediately because the baud clock will

start from a cleared state.

5. A transmit interrupt will be generated,

depending on the value of the interrupt control

bit UTXISEL (UxSTA<15>).

15.3.2 TRANSMITTING IN 9-BIT DATA

MODE

The sequence of steps involved in the transmission

of 9-bit data is similar to 8-bit transmission, except that

a 16-bit data word (of which the upper 7 bits are always

clear) must be written to the UxTXREG register.

15.3.3 TRANSMIT BUFFER (UXTXB)

The transmit buffer is 9 bits wide and 4 characters deep.

Including the Transmit Shift register (UxTSR), the user

effectively has a 5-deep FIFO (First-In, First- Out) buffer.

The UTXBF bit (UxSTA<9>) indicates whether the

transmit buffer is full.

If a user attempts to write to a full buffer, the new data

will not be accepted into the FIFO and no data shift will

occur within the buffer. This enables recovery from a

buffer overrun condition.

The FIFO is reset during any device Reset, but is not

affected when the device enters or wakes up from a

Power Saving mode.

dsPIC30F2011/2012/3012/3013

15.3.4 TRANSMIT INTERRUPT

The transmit interrupt flag (U1TXIF or U2TXIF) is

located in the corresponding interrupt flag register .

The transmitter generates an edge to set the UxTXIF

bit. The condition for generati ng the interrupt depen ds

on the UTXISEL control bit:

a) If UTXISEL = 0, an interrupt is generate d when

a word is transferred from the transmit bu ffer to

the T ransmit Shift register (UxTSR). This means

that the transmit buffer has at least one empty

word.

b) If UTXISEL = 1, an interrupt is generate d when

a word is transferred from the transmit bu ffer to

the Transmit Shift register (UxTSR) and the

transmit buffer is empty.

Switching between the two Interrupt modes during

operation is possible and sometimes offers more

flexibility.

15.3.5 TRANSMIT BREAK

Setting the UTXBRK bit (UxSTA<11>) will cause the

UxTX line to be driven to logic ‘0’. The UTXBRK bit

overrides all transmission activity. Therefore, the user

should generally wait for the transmitter to be Idle

before setting UTXBRK.

To send a Break character, the UTXBRK bit must be set

by software and must remain set for a minimum of 13

baud clock cycles. The UTXBRK bit is then cleared by

software to generate Stop bits. The user must wait for

a duration of at least one or two baud clock cycles in

order to ensure a valid Stop bit(s) before reloading the

UxTXB, or starting other transmitter activity.

T ransmission of a Break character does not generate a

transmit interrupt.

15.4 Receiving Data

15.4.1 RECEIVING IN 8-BIT OR 9-BIT

DATA MODE

The following steps must be performed while receiving

8-bit or 9-bit data:

1. Set up the UART (see Section 15.3.1

“Transmitting in 8-bit data mode”).

2. Enable the UART (see Section 15.3.1

“Transmitting in 8-bit data mode”).

3. A receive interrupt will be generated when one

or more data words have been received, depend-

ing on the receive interrupt settings specified by

the URXISEL bits (UxSTA<7:6>).

4. Read the OERR bit to determine if an overrun error

has occurred. The OERR bit must be reset in soft-

ware.

5. Read the received data from UxRXREG . The act

of reading UxRXREG will move the next word to

the top of the receive FIFO, and the PERR and

FERR values will be updated.

15.4.2 RECEIVE BUFFER (UXRXB)

The receive buffer is 4 words deep. Including the

Receive Shift register (UxRSR), the user effectively

has a 5-word deep FIFO buffer.

URXDA (UxSTA<0>) = 1 indicates that the receive

buffer has data available. URXDA = 0 implies that the

buffer is empty. If a user attempts to read an empty

buffer, th e old values in the buffer will be read and no

data shift will occur within the FIFO.

The FIFO is reset during any device Reset. It is not

affected when the device enters or wakes up from a

Power Saving mode.

15.4.3 RECEIVE INTERR UPT

The receive interrupt flag (U1RXIF or U2RXIF) can be

read from the corresponding interrupt flag register . The

interrupt flag is set by an edge generated by the

receiver. The condition for setting the receive interrupt

flag depends on the settings specified by

the URXISEL<1:0> (UxSTA<7:6>) control bits.

a) If URXISEL<1:0> = 00 or 01, an interrupt is

generated every time a data word is transferred

from the Receive Shift register (UxRSR) to the

receive buffer. There may be one or more

characters in the receive buffer.

b) If URXISEL<1:0> = 10, an interrupt is generated

when a word is transferred from the Recei ve Shift

result of the transfer, contains 3 characters.

c) If URXISEL<1:0> = 11, an interrupt is set when

a word is transferred from the Receive Shift

a result of the transfer, contains 4 characters

(i.e., becomes full).

Switching between the Interrupt modes during

operation is possible, though generally not advisable

during normal operation.

15.5 Reception Error Handling

15.5.1 RECEIVE BUFFER OVERRUN

ERROR (OERR BIT)

The OERR bit (UxSTA<1> ) is set if all of the following

conditions occur:

a) The receive buffer is full.

b) The Receive Shift register is full, but unable to

transfer the character to the receive buffer.

c) The Stop bit of the character in the UxRSR is

detected, indicating that the UxRSR needs to

transfer the character to the buffer.

Once OERR is set, no further data is shifted in UxRSR

(until the OERR bit is cleared in software or a Reset

occurs). The data held in UxRSR and UxRXREG

remains valid.

dsPIC30F2011/2012/3012/3013

15.5.2 FRAMING ERROR (FERR)

The FERR bit (UxSTA<2>) is set if a ‘0’ is detected

instead of a Stop bit. If two Stop bits are selected, both

Stop bits must be ‘1’, otherwise FERR will be set. The

read-only FERR bit i s bu ffered along w ith the receive d

data. It is cleared on any Reset.

15.5.3 PARITY ERROR (PERR)

The PERR bit (UxSTA<3>) is set if the parity of the

received word is incorrect. This error bit is applicable

only if a Parity mode (odd or even) is selected. The

read-only PERR bit is buffered along with the received

data bytes. It is cleared on any Reset.

15.5.4 IDLE STATUS

When the receiver is active (i.e., between the initial

detection of the S t art bit and the completion of the S t op

bit), the RIDLE bit (UxST A<4>) is ‘0’. Between the com-

pletion of the S top bit and detection of the next S tart bit,

the RIDLE bi t is ‘1’, indicating that the UART is Idle.

15.5.5 RECEIVE BREAK

The receiver will count and expect a certain number of

bit times based on the values programmed in the PDSEL

(UxMODE<2:1>) and STSEL (UxMODE<0>) bits.

If the break is longer than 13 bit times, the reception is

considered complete after the number of bit times

specified by PDSEL and STSEL. The URXDA bit is set,

FERR is set, zeros are loaded into the receive FIFO,

interrupts are generated if appropriate and the RIDLE

bit is set.

When the module receives a long break signal and the

receiver has detected the S tart bit, the data bits and the

invalid Stop bit (which sets the FERR), the receiver

must wait for a valid S top bit before looking for the next

Start bit. It cannot assume that the break condition on

the line is the next Start bit.

Break is regarded as a character containing all ‘0’s with

the FERR bit set. The Break character is loaded into

the buffer . No further reception can occur until a S top bit

is received. Note that RIDLE goes high when the Stop

bit has not yet been received.

15.6 Address Detect Mode

Setting the ADDEN bit (UxSTA<5>) enables this

special mode in which a 9th bit (URX8) value of ‘1’

identifies the received word as an address, rather than

data. This mode is only applicable for 9-bit data

communication. The URXISEL control bit does not

have any impact on interrupt generation in this mode

since an interrupt (if enabled) will be generated every

time the receiv e d word ha s the 9th bit set.

15.7 Loopback Mode

Setting the LPBACK bit enables this special mode in

which the UxTX pin is internally connected to the UxRX

pin. When configured for the Loopback mode, the

UxRX pin is disconnected from the internal UART

receive logic. However, the UxTX pin still functions as

in a normal operation.

To select this mode:

a) Configure UART for desired mode of operation.

b) Set LPBACK = 1 to enable Loopback mode.

c) Enable transmission as defined in Section 15.3

“Transmitting Data”.

15.8 Baud Rate Generator

The UART has a 16-bit Baud Rate Generator to allow

maximum flexibility in baud rate generation. The Baud

Rate Generator register (UxBRG) is readable and

writable. The baud rate is computed as follows:

BRG = 16-bit value held in UxBRG register

(0 through 65535)

FCY = Instruction Clock Rate (1/TCY)

The baud rate i s given by Equation 15-1.

EQUATION 15-1: BAUD RATE

Therefore, the maximum baud rate possible is:

FCY /16 (if BRG = 0),

and the minimum baud rate possible is:

FCY / (16* 65536).

With a full 16-bit Baud Rate Generator at 30 MIPS

operation, the minimum baud rate achievable is

28.5 bps.

15.9 Auto-Baud Support

To allow the system to determine baud rates of

received characters, the input can be optiona lly linked

to a selected capture input (IC1 for UART1 and IC2 for

UART2). To enable this mode, you must program the

input capture module to detect the falling and rising

edges of the Start bit.

Baud Rate = FCY / (16*(BRG+1))

dsPIC30F2011/2012/3012/3013

15.10 UART Operation During CPU

Sleep and Idle Modes

15.10.1 UART OPERATION DURING CPU

SLEEP MODE

When the device enters Sleep mode, a ll clock sources

to the module are shut down and stay at logic ‘0’. If

entry into Sleep mode occurs while a transmission is in

progress, then the tra nsmission is aborted. The UxTX

pin is driven to logic ‘1’. Similarly, if entry into Sleep

mode occurs while a reception is in progress, then th e

reception is aborted. The UxSTA, UxMODE, transmit

and receive registers and buffers, and the UxBRG

If the W AKE bit (UxMODE<7>) is set before the device

enters Sleep mode, then a falling edge on the UxRX pin

will generate a receive interrupt. The Receive Interrupt

Select mode bit (URXISEL) has no effect for this

function. If the receive interrupt is enabled, then this will

wake-up the device from Sleep. The UARTEN bit must

be set in order to generate a wake-up interrupt.

15.10.2 UART OPERATION DURING CPU

IDLE MODE

For the UART, the USIDL bit selects if the module will

stop operation when the device enters Idle mode or

whether the module will continue on Idle. If USIDL = 0,

the module will continue to operate during Idle mode. If

USIDL = 1, the module will stop on Idle.

dsPIC30F2011/2012/3012/3013

TABLE 15-1: UART1 REGISTER MAP FOR dsPIC30F2011/2012/3012/3013

TABLE 15-2: UART2 REGISTER MAP FOR dsPIC30F3013(1)

SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

U1MODE 020C UARTEN —USIDL——ALTIO—— WAKE LPBACK ABAUD —— PDSEL1 PDSEL0 STSEL 0000 0000 0000 0000

U1STA 020E UTXISEL — — — UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA 0000 0001 0001 0000

U1TXREG 0210 — — — — — — — UTX8 Transmit Register 0000 000u uuuu uuuu

U1RXREG 0212 — — — — — — — URX8 Receive Register 0000 0000 0000 0000

U1BRG 0214 Baud Rate Generator Prescaler 0000 0000 0000 0000

Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’

SFR

Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset S tate

U2MODE 0216 UARTEN —USIDL— — — — — WAKE LPBACK ABAUD —— PDSEL1 PDSEL0 STSEL 0000 0000 0000 0000

U2STA 0218 UTXISEL — — — UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA 0000 0001 0001 0000

U2TXREG 021A — — — — — — — UTX8 T ransmit Register 0000 000u uuuu uuuu

U2RXREG 021C — — — — — — — URX8 Receive Register 0000 0000 0000 0000

U2BRG 021E Baud Rate Generator Prescaler 0000 0000 0000 0000

Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’

Note 1: UART2 is not available on dsPIC30F2011/2012/3012 devices.

2: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.

dsPIC30F2011/2012/3012/3013

NOTES:

dsPIC30F2011/2012/3012/3013

16.0 12-BIT ANALOG-TO-DIGIT A L

CONVERTER (ADC) MODULE

The 12-bit Analog-to-Digital Converter allows

conversion of an analog input signal to a 12-bit digital

number. This module is based on a Successive

Approximation Register (SAR) architecture and

provides a maximum sampling rate of 200 ksps. The

ADC module has up to 10 analog inputs which are

multiplexed into a sample and hold amplifier. The

output of the sample and hold is the input into the

converter which generates the result. The analog

reference voltage is software selectable to either the

device supply voltage (AVDD/AVSS) or the voltage lev el

on the (VREF+/VREF-) pin. The ADC has a unique

feature of being able to operate while the device is in

Sleep mode with RC oscillator selection.

The ADC module has six 16-bit registers:

• A/D Control Register 1 (ADCON1)

• A/D Control Register 2 (ADCON2)

• A/D Control Register 3 (ADCON3)

• A/D Input Select Register (ADCHS)

• A/D Port Configuration Register (ADPCFG)

• A/D Input Scan Selection Register (ADCSSL)

The ADCON1, ADCON2 and ADCON3 registers

control the operation of the ADC module . The ADCHS

ADPCFG register configures the port pins as analog

inputs or as digital I/O. The ADCSSL register selects

inputs for scanning.

The block diagram of the 12-bit ADC module is sho wn

in Figure 16-1.

FIGURE 16-1: 12-BIT ADC FUNCTIONAL BLOCK DIAGRAM

Note: This data sheet summarizes features of

this group of dsPIC30F devices and is not

intended to be a complete reference

source. For more information on the CPU,

peripherals, register descriptions and

general device functionality, refer to the

“dsPIC30F Family Reference Manual”

(DS70046).

Note: The SSRC<2:0>, ASAM, SMPI<3:0>,

BUFM and ALTS bits, as well as the

ADCON3 and ADCSSL registers, must

not be written to while ADON = 1. This

would lead to indeterminate results.

Comparator

12-bit SAR Conversion Logic

AVDD/VREF+

DAC

Data Format

16-word, 12-bit

Dual Port

Buffer

Bus Interface

0000

0101

0111

1001

0001

0010

0011

0100

0110

1000

AN8

AN9

AN4

AN5

AN6

AN7

AN0

AN1

AN2

AN3

CH0

AVSS/VREF-

Sample/Sequence

Control

Sample

Input MUX

Control

Input

Switches

S/H

dsPIC30F2011/2012/3012/3013

16.1 A/D Result Buffer

The module contains a 16-word dual port read-only

buffer, called ADCBUF0...ADCBUFF, to buffer the A/D

results. The RAM is 12 bits wide but the data obtained

is represented in one of four different 16-bit data

formats. The contents of the sixteen A/D Conversion

Result Buffer registers, ADCBUF0 through ADCBUFF,

cannot be written by user software.

16.2 Conversion Operation

After the ADC module has been configured, the sample

acquisition is started by setting the SAMP bit. Various

sources, such as a programmable bit, timer time-outs

and external events, will terminate acquisition and start

a conversion. When the A/D conversion is complete,

the result is loaded into ADCBUF0...ADCBUFF, and

the DONE bit and the A/D interrupt flag, ADIF, are set

after the number of samples specified by the SMPI bit.

The ADC module can be configured for different inter-

rupt rates as described in Section 16.3 “Selecting the

Conversion Sequence”.

The following steps should be followed for doing an

A/D conversion:

1. Configure the ADC mo dule:

• Configure analog pins, voltage reference and

digital I/O

• Select A/D input channels

• Select A/D conversion clock

• Select A/D conversion trigger

• Turn on ADC module

2. Configure A/D interrupt (if required):

• Clear ADIF bit

• Select A/D interrupt priority

3. Start sampling

4. W ait the required acquisition time

5. Trigger acquisition end, start conversion

6. Wait for A/D conversion to complete, by either:

• Waiting for the A/D interrupt, or

• Waiting for the DONE bit to get set

7. Read A/D result buffer; clear ADIF if required

16.3 Selecting the Conversion

Sequence

Several groups of control bits select the sequence in

which the A/D connects inputs to the sample/hold

channel, converts a channel, writes the buffer memory

and generates interrupts.

The sequence is controlled by the samp ling clocks.

The SMPI bits select the number of

acquisition/conversion sequences that would be per-

formed before an interrupt occurs. This can vary from 1

sample per interrupt to 16 samples per interrupt.

The BUFM bit will split the 16-word results buffer into

two 8-word groups. W riting to the 8-word buffers will be

alternated on each interrupt event.

Use of the BUFM bit will depend on how much time is

available for the moving of the buffers after the

interrupt.

If the processor can quickly unload a full buffer within

the time it takes to acquire and convert one channel,

the BUFM bit can be ‘0’ and up to 16 conversions

(corresponding to the 16 input channels) may b e done

per interrupt. The processor will have one acquisition

and conversion time to move the sixteen conversions.

If the processor cannot unload the buffer within the

acquisition and conversion time, the BUFM bit should be

‘1’. For example, if SMPI<3:0> (ADCON2<5:2>) = 0111,

then eight conversions will be loaded into 1/2 of the

buffer, following which an interrupt occurs. The next

eight conversions will be loaded in to the other 1/2 of the

buffer. The processor will have the entire time between

interrupts to move the eight co nversions.

The ALTS bit can be used to alternate the inputs

selected during the sampling sequence. The input

multiplexer has two sets of sample inputs: MUX A and

MUX B. If the ALTS bit is ‘0’, only the MUX A inputs are

selected for sampling. If the ALTS bit is ‘1’ and

SMPI<3:0> = 0000 on the first sample/convert

sequence, the MUX A inputs are selected and on the

next acquire/convert sequence , the MUX B inputs are

selected.

The CSCNA bit (ADCON2<10>) will allow the

multiplexer input to be alternately scanned across a

selected number of analog inputs for the MUX A group.

The inputs are selected by the ADCSSL register. If a

particular bit in the ADCSSL register is ‘1’, the

corresponding input is selected. The inputs are always

scanned from lower to higher numbered inputs, starting

after each interrupt. If the number of inp uts selected is

greater than the number of samples taken per interrupt,

the higher numbered inputs are unused.

dsPIC30F2011/2012/3012/3013

16.4 Programming the Start of

Conversion Trigger

The conversion trigger will terminate acquisition and

start the requested conversions.

The SSRC<2:0> bits select the source of the

conversion trigger . The SSRC bits provide for up to four

alternate sources of conversion trigger.

When SSRC<2:0> = 000, the conversion trigger is

under software control. Clearing the SAMP bit will

cause the conversion trigge r.

When SSRC<2:0> = 111 (Auto-Start mode), the

conversion trigger is under A/D clock control. The

SAMC bits select the number of A/D clocks between

the start of acquisition and the start of conversion. This

provides the fastest conversion rates on multiple

channels. SAMC must always be at least one clock

cycle.

Other trigger sources can come from timer modules or

external interrupts.

16.5 Aborting a Conversion

Clearing the ADON bit during a conversion will abort

the current conversion and stop the sampling

sequencing until the next sampling trigger. The

ADCBUF will not be updated with the partially

completed A/D conversion sample. That is, the

ADCBUF will continue to contain the value of the last

completed conversion (or the last value written to the

ADCBUF register).

If the clearing of the ADON bit coincides with an

auto-start, the clearing has a higher p riority and a n ew

conversion will not start.

After the A/D conversion is aborted, a 2 TAD wait is

required before the next sampling may be started by

setting the SAMP bit.

16.6 Selecting the ADC Conversion

Clock

The ADC conversion requires 14 TAD. The source of

the ADC conversion clock is software selected, using a

6-bit counter . There are 64 possible options for TAD.

EQUATION 16-1: ADC CONVERSION

CLOCK

The internal RC oscillator is selected by setting the

ADRC bit.

For correct ADC conversions, the ADC conversion

clock (TAD) must be selected to ensure a minimum TAD

time of 334 nsec (for VDD = 5V). Refer to Section 20.0

“Electrical Characteristics” for minimum TAD under

other operating conditions.

Example 16-1 shows a sample calculation for the

ADCS<5:0> bits, assuming a device operating speed

of 30 MIPS.

EXAMPLE 16-1: ADC CONVERSION

CLOCK AND SAMPLING

RATE CALCULATION

TAD = TCY * (0.5*(ADCS<5:0> + 1))

Minimum TAD = 334 nsec

ADCS<5:0> = 2 – 1

TAD

TCY

TCY = 33 .33 nsec (30 MIPS)

= 2 • – 1

334 nsec

33.33 nsec

= 19.04

Therefore,

Set ADCS<5:0> = 19

Actual TAD = (ADCS<5:0> + 1)

TCY

= (19 + 1)

33.33 nsec

= 334 nsec

If SSRC<2:0> = ‘111’ and SAMC<4:0> = ‘00001’

Since,

Sampling Time = Acquisition Time + Conversion Time

= 1 TAD + 14 TAD

= 15 x 334 nsec

Therefore,

Sampling Rate =

= ~200 kHz

(15 x 334 nsec)

dsPIC30F2011/2012/3012/3013

16.7 ADC Speeds

The dsPIC30F 12-bit ADC specifications permit a

maximum of 200 ksps sampling rate. Table 16-1

summarizes the conversion speeds for the dsPIC30F

12-bit ADC and the required operating conditions.

Figure 16-2 depicts the recommended circuit for the

conversion rates ab ove 200 ksps. The dsPIC30F2011

is shown as an example.

FIGURE 16-2: ADC VOLTAGE REFERENCE SCHEMATIC

TABLE 16-1: 12-BIT ADC EXTENDED CONVERSION RATES

dsPIC30F 12-bit ADC Conversion Rates

Speed TAD

Minimum Sampling

Time Min Rs Max VDD Temperature Channel Configuration

Up to 200

ksps(1) 334 ns 1 TAD 2.5 kΩ4.5V

5.5V

-40°C to +85°C

Up to 100

ksps 668 ns 1 TAD 2.5 kΩ3.0V

5.5V

-40°C to +125°C

Note 1: External VREF- and VREF+ pins must be used for correct operation. See Figure 16-2 for recommended

circuit.

VREF-VREF+

ADC

ANx S/HCHX

VREF-VREF+

ADC

ANx S/HCHX

ANx or VREF-

AVSS or

AVDD

VDD

1 μF

VDD

0.1 μF

VDD

0.01 μF

AVDD

1 μF

AVDD

0.1 μF

AVDD

0.01 μF

See Note 1:

Note 1: Ensure adequate bypass capacitors are provided on each VDD pin.

VREF-

AVDD

VSS

VDD

VSS

VDD

VSS

dsPIC30F2011

VDD

0.1 μFC1

0.01 μF

dsPIC30F2011/2012/3012/3013

The configuration procedures in the next section pro-

vide the required setup values for the conversion

speeds above 100 ksps.

16.7.1 200 KSPS CONFIGURATION

GUIDELINE

The following configuration items are required to

achieve a 200 ksps conversion rate.

• Comply with conditions provi ded in Table 16-1.

• Connect external V REF+ and VREF- pins following

the recommended circuit shown in Figure 16-2.

• Set SSRC<2.0> = 111 in the ADCON1 register to

enable the auto convert option.

• Enable automatic sampling by setting the ASAM

control bit in the ADCON1 register.

• Write the SMPI<3.0> control bits in the ADCON2

between interrupts.

• Configure the ADC clock period to be:

by writing to the ADCS<5:0> control bits in the

ADCON3 register.

• Configure the sampling time to be 1 TAD by

writing: SAMC<4:0> = 00001.

The following figure shows the timing diagram of the

ADC running at 200 ksps. The TAD selection in

conjunction with the guidelines described above allows

a conversion speed of 200 ksps. See Example 16-1 for

code example.

16.8 A/D Acquisition Requirements

The analog input model of the 12-bit ADC is shown in

Figure 16-3. The total sampling time for the A/D is a

function of the internal amplifier settling time and the

holding capacitor charge time.

For the ADC to meet its s pecified accuracy, the charge

holding capacitor (CHOLD) must be allowed to fully

charge to the voltage level on the analog input pin. The

source impedance (RS), the interconnect

impedance (RIC) and the internal sampling switch

(RSS) impedance combine to directly affect the time

required to charge the capacitor CHOLD. The combined

impedance of the analog sources must therefore be

small enough to fully charge the holding capacitor

within the chosen sample time. To minimize the effects

of pin leakage currents on the accuracy of the ADC, the

maximum recommended source impedance, RS,

is 2.5 kΩ. After the analog input channel is selected

(changed), this sampling function must be completed

prior to starting the conversion. The internal holding

capacitor will be in a discharged state prior to each

sample operation.

FIGURE 16-3: 12-BIT A/D CONVERTER ANALOG INPUT MODEL

(14 + 1) x 200,000 = 334 ns

CPIN

Rs ANx VT = 0.6V

VT = 0.6V I leakage

RIC ≤ 250ΩSampling

Switch

RSS

CHOLD

= DAC capacitance

VSS

VDD

= 18 pF

± 500 nA

Legend: CPIN

I leakage

RIC

RSS

CHOLD

= input capacitance

= threshold voltage

= leakage current at the pin due to

= interconnect resistance

= sampl ing switch resistanc e

= sample/hold capacitance (from DAC)

various junctions

Note: CPIN value depends on device package and is not tested. Effect of CPIN negligible if Rs ≤ 2.5 kΩ.

RSS ≤ 3 kΩ

dsPIC30F2011/2012/3012/3013

16.9 Module Power-Down Modes

The module has two internal power modes.

When the ADON bit is ‘1’, the module is in Active mode;

it is fully powered and functi onal.

When ADON is ‘0’, the module is in Off mode. The

digital and analog portions of the circuit are disabled for

maximum current savings.

In order to return to the Active mode from Off mode, the

user must wait for the ADC circuitry to stabilize.

16.10 A/D Operation During CPU Sleep

and Idle Modes

16.10.1 A/D OPERATION DURING CPU

SLEEP MODE

When the device enters Sleep mode, all clock sources

to the module are shut down and stay at logic ‘0’.

If Sleep occurs in the middle of a conversion, the

conversion is aborted. The converter will not continue

with a partially completed conversion on exit from

Sleep mode.

entering or leaving Sleep mode.

The ADC module can operate during Sleep mode if the

A/D clock source is set to RC (ADRC = 1). When the

RC clock source is selected, the ADC module waits

one instruction cycle before starting the conversion.

This allows the SLEEP instruction to be executed which

eliminates all digital switching noise from the

conversion. When the conversion is complete, the

CONV bit will be cleared and the result loaded into the

ADCBUF register.

If the A/D interrupt is enabled, the device will wake-up

from Sleep. If the A/D interrupt is not enabled, the ADC

module will then be turned off, although the ADON bit

will remain set.

16.10.2 A/D OPERATION DURING CPU IDLE

MODE

The ADSIDL bit selects if the module will stop on Idle or

continue on Idle. If ADSIDL = 0, the module will

continue operation on assertion of Idle mode. If

ADSIDL = 1, the module will stop on Idle.

16.11 Effects of a Reset

A device Reset forces all registers to their Reset state.

This forces the ADC module to be turned off, and any

conversion and sampling sequence is aborted. The

values that are in the ADCBUF registers are not

modified. The A/D Result register will contain unknown

data after a Power-on Reset.

16.12 Output Formats

The A/D result is 12 bits wide. The data buffer RAM is

also 12 bits wide. The 12-bit data can be read in one of

four different formats. The FORM<1:0> bits select the

format. Each of the output formats translates to a 16-bit

result on the data bus.

FIGURE 16-4: A/D OUTPUT DATA FORMATS

RAM Contents: d11 d 10 d09 d 08 d07 d 06 d05 d 04 d03 d 02 d01 d 00

Read to Bus:

Signed Fractional d11 d10d09d08d07d06d05d04d03d02d01d000000

Fractional d11d10d09d08d07d06d05d04d03d02d01d000000

Signed Integer d11 d11 d11 d11 d11 d10d09d08d07d06d05d04d03d02d01d00

Integer 0000d11d10d09d08d07d06d05d04d03d02d01d00

dsPIC30F2011/2012/3012/3013

16.13 Configuring Analog Port Pins

The use of the ADPCFG and TRIS registers control the

operation of the A/D port pins. The port pins that are

desired as analog inputs must have their

corresponding TRIS bit set (input). If the TRIS bit is

cleared (output), the digital output level (VOH or VOL)

will be converted.

The A/D operation is independent of the state of the

CH0SA<3:0>/CH0SB<3:0> bits and the TRIS bits.

When reading the PORT register , all pins configured as

analog input channels will read as cleared.

Pins configured as digital inputs will not convert an

analog input. Analog levels on any pin that is defined as

a digital input (including the ANx pins) may cause the

input buffer to consume current that exceeds the

device specifications.

16.14 Connection Considerations

The analog inputs have diodes to VDD and VSS as ESD

protection. This requires that the analog input be

between VDD and VSS. If the input voltage exceeds this

range by greater than 0.3V (either direction), one of the

diodes becomes forward biased and it may damage the

device if the input current specification is exceeded.

An external RC filter is sometimes added for

anti-aliasing of the input signal. The R component

should be selected to ensure that the sampling time

requirements are satisfied. Any external components

connected (via high-impedance) to an analog input pin

(capacitor, zener diode, etc.) should have very little

leakage current at the pin.

dsPIC30F2011/2012/3012/3013

TABLE 16-2: A/D CONVERTER REGISTER MAP FOR dsPIC30F2011/3012

SFR

Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

ADCBUF0 0280 — — — — ADC Data Buffer 0 0000 uuuu uuuu uuuu

ADCBUF1 0282 — — — — ADC Data Buffer 1 0000 uuuu uuuu uuuu

ADCBUF2 0284 — — — — ADC Data Buffer 2 0000 uuuu uuuu uuuu

ADCBUF3 0286 — — — — ADC Data Buffer 3 0000 uuuu uuuu uuuu

ADCBUF4 0288 — — — — ADC Data Buffer 4 0000 uuuu uuuu uuuu

ADCBUF5 028A — — — — ADC Data Buffer 5 0000 uuuu uuuu uuuu

ADCBUF6 028C — — — — ADC Data Buffer 6 0000 uuuu uuuu uuuu

ADCBUF7 028E — — — — ADC Data Buffer 7 0000 uuuu uuuu uuuu

ADCBUF8 0290 — — — — ADC Data Buffer 8 0000 uuuu uuuu uuuu

ADCBUF9 0292 — — — — ADC Data Buffer 9 0000 uuuu uuuu uuuu

ADCBUFA 0294 — — — — ADC Data Buffer 10 0000 uuuu uuuu uuuu

ADCBUFB 0296 — — — — ADC Data Buffer 11 0000 uuuu uuuu uuuu

ADCBUFC 0298 — — — — ADC Dat a Buffer 12 0000 uuuu uuuu uuuu

ADCBUFD 029A — — — — ADC Data Buffer 13 0000 uuuu uuuu uuuu

ADCBUFE 029C — — — — ADC Data Buffer 14 0000 uuuu uuuu uuuu

ADCBUFF 029E — — — — ADC Data Buffer 15 0000 uuuu uuuu uuuu

ADCON1 02A0 ADON —ADSIDL— — — FORM<1:0> SSRC<2:0> —— ASAM SAMP DONE 0000 0000 0000 0000

ADCON2 02A2 VCFG<2:0> —— CSCNA ——BUFS— SMPI<3:0> BUFM ALTS 0000 0000 0000 0000

ADCON3 02A4 — — — SAMC<4:0> ADRC — ADCS<5:0> 0000 0000 0000 0000

ADCHS 02A6 — — — CH0NB CH0SB<3:0> — — — CH0NA CH0SA<3:0> 0000 0000 0000 0000

ADPCFG 02A8 — — — — — — — — PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 0000 0000 0000 0000

ADCSSL 02AA — — — — — — — — CSSL7 CSSL6 CSSL5 CSSL4 CSSL3 CSSL2 CSSL1 CSSL0 0000 0000 0000 0000

Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’

Note: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.

dsPIC30F2011/2012/3012/3013

TABLE 16-3: A/D CONVERTER REGISTER MAP FOR dsPIC30F2012/3013

SFR

Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

ADCBUF0 0280 — — — — ADC Data Buffer 0 0000 uuuu uuuu uuuu

ADCBUF1 0282 — — — — ADC Data Buffer 1 0000 uuuu uuuu uuuu

ADCBUF2 0284 — — — — ADC Data Buffer 2 0000 uuuu uuuu uuuu

ADCBUF3 0286 — — — — ADC Data Buffer 3 0000 uuuu uuuu uuuu

ADCBUF4 0288 — — — — ADC Data Buffer 4 0000 uuuu uuuu uuuu

ADCBUF5 028A — — — — ADC Data Buffer 5 0000 uuuu uuuu uuuu

ADCBUF6 028C — — — — ADC Data Buffer 6 0000 uuuu uuuu uuuu

ADCBUF7 028E — — — — ADC Data Buffer 7 0000 uuuu uuuu uuuu

ADCBUF8 0290 — — — — ADC Data Buffer 8 0000 uuuu uuuu uuuu

ADCBUF9 0292 — — — — ADC Data Buffer 9 0000 uuuu uuuu uuuu

ADCBUFA 0294 — — — — ADC Data Buffer 10 0000 uuuu uuuu uuuu

ADCBUFB 0296 — — — — ADC Data Buffer 11 0000 uuuu uuuu uuuu

ADCBUFC 0298 — — — — ADC Dat a Buffer 12 0000 uuuu uuuu uuuu

ADCBUFD 029A — — — — ADC Data Buffer 13 0000 uuuu uuuu uuuu

ADCBUFE 029C — — — — ADC Data Buffer 14 0000 uuuu uuuu uuuu

ADCBUFF 029E — — — — ADC Data Buffer 15 0000 uuuu uuuu uuuu

ADCON1 02A0 ADON —ADSIDL— — — FORM<1:0> SSRC<2:0> —— ASAM SAMP DONE 0000 0000 0000 0000

ADCON2 02A2 VCFG<2:0> —— CSCNA ——BUFS— SMPI<3:0> BUFM ALTS 0000 0000 0000 0000

ADCON3 02A4 — — — SAMC<4:0> ADRC — ADCS<5:0> 0000 0000 0000 0000

ADCHS 02A6 — — — CH0NB CH0SB<3:0> — — — CH0NA CH0SA<3:0> 0000 0000 0000 0000

ADPCFG 02A8 — — — — — — PCFG9 PCFG8 PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 0000 0000 0000 0000

ADCSSL 02AA — — — — — — CSSL9 CSSL8 CSSL7 CSSL6 CSSL5 CSSL4 CSSL3 CSSL2 CSSL1 CSSL0 0000 0000 0000 0000

Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’

Note: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.

dsPIC30F2011/2012/3012/3013

NOTES:

dsPIC30F2011/2012/3012/3013

17.0 SYSTEM INTEGRATION

There are several features intended to maximize

system reliability, minimize cost through eliminati on of

external components, provide Power Saving Operating

modes and offer code protection:

• Oscillator Selection

• Reset

- Power-on Reset (POR)

- Power-up Timer (PWRT)

- Oscillator Start-up Timer (OST )

- Programmable Brown-out Reset (BOR)

• W atchdog Timer (WDT)

• Low-Voltage Detect

• Power-Saving Modes (Sleep and Idle)

• Code Protection

• Unit ID Locations

• In-Circuit Serial Programming (ICSP)

dsPIC30F devices have a Watchdog Timer which is

permanently enabled via the Configuration bits or can

be software controlled. It runs off its own RC oscillator

for added reliability. There are two timers that offer

necessary delays on power-up. One is the Oscillator

Start-up Timer (OST), intended to keep the chip in

Reset until the crystal oscilla tor is stable. The other is

the Power-up Ti mer (PWRT) wh ich provides a de lay on

power-up only , designed to keep the part in Reset while

the power supply stabilizes. With these two timers

on-chip, most applications need no external Reset

circuitry.

Sleep mode is designed to offer a very low current

Power-Down mode. The user can wake-up from Sleep

through external Reset, Watchdog Timer Wake-up, or

through an interrupt. Several oscillator options are also

made available to allow the part to fit a wide variety of

applications. In the Idle mode, the clock sources are

still active but the CPU is shut-off. The RC oscillator

option saves system cost while the LP crystal option

saves power.

17.1 Oscillator System Overview

The dsPIC30F oscillator system has the following

modules and features:

• Various external and internal oscillator options as

clock sources

• An on-chip PLL to boost internal operating

frequency

• A clock switching mechanism between various

clock sources

• Programmable clock postscaler for system power

savings

• A Fail-Safe Clock Monitor (FSCM) that detects

clock failure and takes fail-safe measures

• Clock Control register (OSCCON)

• Configuration bits for main oscillator selection

Configuration bits determine the clock source upon

Power-on Reset (POR) and Brown-out Reset (BOR).

Thereafter, the clock source can be changed between

permissible clock sources. The OSCCON register

controls the clock switching and reflects system clock

related status bits.

Table 17-1 provides a summary of the dsPIC30F

Oscillator Operating modes. A simplified diagram of the

oscillator system is shown in Figure 17-1.

Note: This data sheet summarizes features of

this group of dsPIC30F devices and is not

intended to be a complete reference

source. For more information on the CPU,

peripherals, register descriptions and

general device functionality, refer to the

“dsPIC30F Family Reference Manual”

(DS70046). For more information on the

device instruction set and programming,

refer to the “16-bit MCU and DSC

Programmer’s Reference Manual”

(DS70157).

dsPIC30F2011/2012/3012/3013

TABLE 17-1: OSCILLATOR OPERATING MODES

Oscillator Mode Description

XTL

XT w/PLL 4x

XT w/PLL 8x

XT w/PLL 16x

200 kHz-4 MHz crystal on OSC1:OSC2.

4 MHz-10 MHz crystal on OSC1:OSC2.

4 MHz-10 MHz crystal on OSC1:OSC2, 4x PLL enabled.

4 MHz-10 MHz crystal on OSC1:OSC2, 8x PLL enabled.

4 MHz-7.5 MHz crystal on OSC1:OSC2, 16x PLL enabled(1).

32 kHz crystal on SOSCO:SOSCI(2).

10 MHz-25 MHz crystal.

HS/2 w/PLL 4x

HS/2 w/PLL 8x

HS/2 w/PLL 16 x

10 MHz-20 MHz crystal, divide by 2, 4x PLL enabled.

10 MHz-20 MHz crystal, divide by 2, 8x PLL enabled.

10 MHz-15 MHz crystal, divide by 2, 16x PLL enabled(1).

HS/3 w/PLL 4x

HS/3 w/PLL 8x

HS/3 w/PLL 16 x

12 MHz-25 MHz crystal, divide by 3, 4x PLL enabled.

12 MHz-25 MHz crystal, divide by 3, 8x PLL enabled.

12 MHz-22.5 MHz crystal, divide by 3, 16x PLL enabled(1).

ECIO

EC w/PLL 4x

EC w/PLL 8x

EC w/PLL 16x

ERC

ERCIO

External clock input (0-40 MHz).

External clock input (0-40 MHz), OSC2 pin is I/O.

External clock input (4-10 MHz), OSC2 pin is I/O, 4x PLL enabled.

External clock input (4-10 MHz), OSC2 pin is I/O, 8x PLL enabled.

External clock input (4-7.5 MHz), OSC2 pin is I/O, 16x PLL enable d(1).

External RC oscillator , OSC2 pin is FOSC/4 output(3).

External RC oscillator , OSC2 pin is I/O(3).

FRC

FRC w/PLL 4x

FRC w/PLL 8x

FRC w/PLL 16x

7.37 MHz internal RC oscillator.

7.37 MHz Internal RC oscillator , 4x PLL enabled.

7.37 MHz Internal RC oscillator , 8x PLL enabled.

7.37 MHz Internal RC oscillator , 16x PLL enabled.

LPRC 512 kHz internal RC oscillator.

Note 1: dsPIC30F maximum operating frequ ency of 120 MHz must be met.

2: LP oscillator can be conveniently shared as system clock, as well as real-time clock for Timer1.

3: Requires external R and C. Frequency operation up to 4 MHz.

dsPIC30F2011/2012/3012/3013

FIGURE 17-1: OSCILLATOR SYSTEM BLOCK DIAGRAM

Primary

OSC1

OSC2

SOSCO

SOSCI

Oscillator

32 kHz LP

Clock

and Control

Block

Switching

Oscillator

x4, x8, x16

PLL

Primary

Oscillator

Stability Dete ctor

Stability Detector

Secondary

Oscillator

Programmable

Clock Divider

Oscillator

Start-up

Timer

Fail-Safe Clock

Monitor (FSCM)

Internal Fast RC

Oscillator (FRC)

Internal Low

Power RC

Oscillator (LPRC)

PWRSAV Instruction

Wake-up Request

Oscillator Configuration bits

System

Clock

Oscillator Trap

To Timer1

LPRC

Secondary Osc

POR Done

Primary Osc

FPLL

POST<1:0>

FCKSM<1:0> 2

PLL

Lock COSC<2:0>

NOSC<2:0>

OSWEN

Internal FRC Osc

dsPIC30F2011/2012/3012/3013

17.2 Oscillator Configurations

17.2.1 INITIAL CLOCK SOURCE

SELECTION

While coming out of Power-on Reset or Brown-out

Reset, the device selects its clock source based on:

a) FOS<2:0> Configuration bits that select one of

four oscillator groups,

b) and FPR<4:0> Configuration bits that select one

of 15 oscillator choices within the primary group.

The selection is as shown in Table 17-2.

17.2.2 OSCILLATOR START-UP TIMER

(OST)

In order to ensure that a crystal oscillator (or ceramic

resonator) has started and stabilized, an Oscillator

Start-up Timer is included. It is a simple 10-bit counter

that counts 1024 TOSC cycles before releasing the

oscillator clock to the rest of the system. The time-out

period is designated as TOST.

The TOST time is involved every time th e oscillator has

to restart (i.e., on POR, BOR and wake-up from Sleep).

The Oscillator Start-up Timer is applied to the LP

oscillator, XT, XTL and HS modes (upon wake-up from

Sleep, POR and BOR) for the primary oscillator.

TABLE 17-2: CONFIGURATION BIT VALUES FOR CLOCK SELECTION

Oscillator Mode Oscillator

Source FOS<2:0> FPR<4:0> OSC2

Function

ECIO w/PLL 4x PLL 11101101 I/O

ECIO w/PLL 8x PLL 11101110 I/O

ECIO w/PL L 16 x PLL 11101111 I/O

FRC w/PLL 4X PLL 11100001 I/O

FRC w/PLL 8x PLL 11101010 I/O

FRC w/PLL 16x PLL 11100011 I/O

XT w/PLL 4x PLL 11100101 OSC2

XT w/PLL 8x PLL 11100110 OSC2

XT w/PLL 16x PLL 11100111 OSC2

HS2 w/PLL 4x PLL 11110001 OSC2

HS2 w/PLL 8x PLL 11110010 OSC2

HS2 w/ PLL 16x PLL 11110011 OSC2

HS3 w/PLL 4x PLL 11110101 OSC2

HS3 w/PLL 8x PLL 11110110 OSC2

HS3 w/PLL 16x PLL 11110111 OSC2

ECIO External 01101100 I/O

XT External 01100100 OSC2

HS External 01100010 OSC2

EC External 01101011 CLKO

ERC External 01101001 CLKO

ERCIO External 01101000 I/O

XTL External 01100000 OSC2

LP Secondary 000XXXXX(Note 1, 2)

FRC Internal FRC 001XXXXX(Note 1, 2)

LPRC Internal LPRC 010XXXXX(Note 1, 2)

Note 1: The OSC2 pin is either usable as a general purpose I/O pin or is completely unusable, depending on the

Primary Oscillator mode selecti on (FPR<4:0>).

2: OSC1 pin cannot be used as an I/O pi n ev en if the secondary oscillator or an internal clock source is

selected at all times.

dsPIC30F2011/2012/3012/3013

17.2.3 LP OSCILLATOR CONTROL

Enabling the LP oscillator is controlled with two elements:

• The current oscillator group bits COSC<2:0>.

• The LPOSCEN bit (OSCCON register).

The LP oscillator is on (even during Sleep mode) if

LPOSCEN = 1. The LP oscillator is the device clock if:

•COSC<2:0> = 000 (LP selected as main osc.) and

• LPOSCEN = 1

Keeping the LP oscillator on at all times allows for a fast

switch to the 32 kHz system clock for lower power oper-

ation. Returning to the faster main oscillator will still

require a start-up time

17.2.4 PHASE LOCKED LOOP (PLL)

The PLL multiplies the clock which is generated by the

primary oscillator or Fast RC oscillator. The PLL is

selectable to have either gains of x4, x8, and x16. Input

and output frequency ranges are summarized in

Table 17-3.

TABLE 17-3: PLL FREQUENCY RANGE

The PLL features a lock output which is asserted when

the PLL enters a phase locked state. Should the loop

fall out of lock (e.g., due to noise), the lock signal will be

rescinded. The state of this signal is reflected in the

read-only LOCK bit in the OSCCON register.

17.2.5 FAST RC OSCILLATOR (FRC)

The FRC oscillator is a fast (7.37 MHz ±2% nominal)

internal RC oscillator. This oscillator is intended to

provide reasonable device operating speeds without

the use of an external crystal, ceramic resonator , or RC

network. The FRC oscillator can be used with the PLL

to obtain higher clock frequencies.

The dsPIC30F operates from the FRC oscillator when-

ever the current oscillator selection control bits in the

OSCCON register (OSCCON<14:12>) are set to ‘001’.

The four bit field specified by TUN<3:0> (OSCTUN

<3:0>) allows the user to tune the internal fast RC

oscillator (nominal 7.37 MHz). The user can tune the

FRC oscillator within a range of +10.5% (840 kHz)

and -12% (960 kHz) in steps of 1.50% around the

factory calibrated setting, as shown in Table 17-4.

If OSCCON<14:12> are set to ‘111’ and FPR<4:0> are

set to ‘00001’, ‘01010’ or ‘00011’, a PLL multiplier of

4, 8 or 16 (respectively) is applied.

TABLE 17-4: FRC TUNING

17.2.6 LOW-POWER RC OSCILLATOR (LPRC)

The LPRC oscillator is a component of the Watchdog

Timer (WDT) and oscillates at a nominal frequency of

512 kHz. The LPRC oscillator is the clock source for

the Power-up Timer (PWRT) circuit, WDT and clock

monitor circuits. It may also be used to provide a

low-frequency clock source option for applications

where power consumption is critical and timing

accuracy is not required.

The LPRC oscillator is always enabled at a Power-on

Reset because it is the clock source for the PWRT.

After the PWRT expires, the LPRC oscillator will remain

on if one of the following is true:

• The Fail-Safe Clock Monitor is enabled

• The WDT is enabled

• The LPRC oscillator is selected as the system

clock via the COSC<2:0> control bits in the

OSCCON register

If one of th e above cond itions is not true, the LPRC will

shut-off after the PWRT expires.

FIN PLL

Multiplier FOUT

4 MHz-10 MHz x4 16 MHz-40 MHz

4 MHz-10 MHz x8 32 MHz-80 MHz

4 MHz-7.5 MHz x16 64 MHz-120 MHz

Note: OSCTUN functionality has b een provided

to help customers compensate for

temperature effects on the FRC frequency

over a wide range of temperatures. The

tuning step size is an approximation and is

neither characterized nor tested.

Note: When a 16x PLL is used, the FRC fre-

quency must not be tuned to a frequency

greater than 7.5 MHz.

TUN<3:0>

Bits FRC Frequency

0111 + 10.5%

0110 + 9.0%

0101 + 7.5%

0100 + 6.0%

0011 + 4.5%

0010 + 3.0%

0001 + 1.5%

0000 Center Frequency (oscillator is

running at calibrated frequency)

1111 - 1.5%

1110 - 3.0%

1101 - 4.5%

1100 - 6.0%

1011 - 7.5%

1010 - 9.0%

1001 - 10.5%

1000 - 12.0%

Note 1: OSC2 pin function is determined by the

Primary Oscillator mode selection

(FPR<4:0>).

2: OSC1 pin cannot be used as an I/O pin

even if the secondary oscillator or an

internal clock source is selected at all

times.

dsPIC30F2011/2012/3012/3013

17.2.7 FAIL-SAFE CLOCK MONITOR

The Fail-Safe Clock Monitor (FSCM) allows the device

to continue to operate even in the event of an oscillator

failure. The FSCM function is enabled by appropriately

programming the FCKSM Configuration bits (clock

switch and monitor selection bits) in the FOSC Device

Configuration register . If the FSCM function is enabled,

the LPRC internal oscillator will run at all times (except

during Sleep mode) and will not be subject to control by

the SWDTEN bit.

In the event of an oscillator fa ilure , the FSCM will ge n-

erate a clock failure trap event and will switch the sys-

tem clock over to the FRC oscillator . The user will then

have the option to either attempt to restart the oscillator

or execute a controlled shutdown. The user may decide

to treat the trap as a warm Reset by simply loading the

Reset address into the oscillato r fail trap vector. In this

event, the CF (Clock Fail) bit (OSCCON<3>) is also set

whenever a clock failure is recognized.

In the event of a clock failure, the WDT is unaffected

and continues to run on the LPRC clock.

If the oscillator has a very slow start-up time coming out

of POR, BOR or Sleep, it is possible that the PWRT

timer will expire before the oscillator has started. In

such cases, the FSCM will be activated and the FSCM

will initiate a clock failure trap, and the COSC<2:0> bits

are loaded with FRC oscillator selection. This will

effectively shut-off the original oscillator that was trying

to start.

The user may detect this situation and restart the

oscillator in the clock fail trap ISR.

Upon a clock failure detection, the FSCM module will

initiate a clock switch to the FRC oscillator as follows:

1. The COSC bits (OSCCON<14:12>) are loaded

with the FRC oscillator selection value.

2. CF bit is set (OSCCON<3>).

3. OSWEN control bit (OSCCON<0>) is cleared.

For the purpose of clock switching, the clock sources

are sectioned into four groups:

• Primary (with or without PLL)

• Secondary

• Internal FRC

• Internal LPRC

The user can switch between these functional groups

but cannot switch between options within a gr oup. If the

primary group is selected, then the choice within the

group is always determined by the FPR<4:0>

Configuration bits.

The OSCCON register holds the Control and Status

bits related to clock switching.

• COSC<2:0>: Read-only bits always reflect the

current oscillator group in effect.

• NOSC<2:0>: Control bits which are written to

indicate the new oscillator group of choice.

- On POR and BOR, COSC<2:0> and

NOSC<2:0> are both loaded with the

Configuration bit values FOS<2:0>.

• LOCK: The LOCK bit indicates a PLL lock.

• CF: Read-only bit indicating if a clock fa il detect

has occurred.

• OSWEN: Control bit changes from a ‘0’ to a ‘1’

when a clock transition sequence is initiated.

Clearing the OSWEN control bit will abort a clock

transition in progress (used for hang-up

situations).

If Configuration bits FCKSM<1:0> = 1x, then the clock

switching and Fail-Safe Clock monitoring functions are

disabled. This is the default Configuration bit setting.

If clock switching is disabled, then the FOS<2:0> and

FPR<4:0> bits directly control the oscillator selection

and the COSC<2:0> bits do not control the clock selec-

tion. However, these bits will reflect the clock source

selection.

17.2.8 PROTECTION AGAINST

ACCIDENTAL WRITES TO OSCCON

A write to the OSCCON register is intentionally made

difficult because it controls clock switching and clock

scaling.

To write to the OSCCON low byte, the following code

sequence must be executed without any other

instructions in between:

Byte Write 0x46 to OSCCON low

Byte Write 0x57 to OSCCON low

Byte write is allowed for one instruction cycle. Write the

desired value or use bit manipulation instruction.

To write to the OSCCON high byte, the following

instructions must be executed without any other

instructions in between:

Byte Write 0x78 to OSCCON high

Byte Write 0x9A to OSCCON high

Byte write is allowed for one instruction cycle. Write the

desired value or use bit manipulation instruction.

Note: The application should not attempt to

switch to a clock of frequency lower than

100 kHz when the Fail-Safe Clock Monitor

is enabled. If such clock switching is

performed, the device may generate an

oscillator fail trap and switch to the Fast

RC oscillator.

dsPIC30F2011/2012/3012/3013

17.3 Reset

The dsPIC30F2011/2012/3012/3013 devices

differentiate between various kinds of Reset:

a) Power-on Reset (POR)

b) MCLR Reset during normal operation

c) MCLR Reset during Sleep

d) Watchdog Timer (WDT) Reset (during normal

operation)

e) Programmable Brown-ou t Reset (BOR)

f) RESET Instruction

g) Reset caused by trap lockup (TRAPR)

h) Reset caused by illegal opcode or by using an

uninitialized W register as an address pointer

(IOPUWR)

Different registers are affected in different ways by

various Reset conditions. Most registers are not

affected by a WDT wake-up since this is viewed as the

resumption of normal operation. Status bits from the

RCON register are set or cleared differently in different

Reset situations, as indicated in Table 17-5. These bits

are used in software to determine the nature of the

Reset.

A block diagram of the On-Chip Reset Circuit is shown

in Figure 17-2.

A MCLR noise filter is provided in the MCLR Reset

path. The filter detects and ignores small pulses.

Internally generated Resets do not drive MCLR pin low .

17.3.1 POR: POWER-ON RESET

A power-on event will gene rate an internal POR pulse

when a VDD rise is detected. The Reset pulse will occur

at the POR circuit threshold voltage (VPOR) which is

nominally 1.85V. The device supply voltage

characteristics must meet specified starting voltage

and rise rate requirements. The POR pulse will reset a

POR timer and place the device in the Reset state. The

POR also selects the device clock source identified by

the oscillator configuration fuses.

The POR circuit inserts a small delay, TPOR, which is

nominally 10 μs and ensures that the device bias

circuits are stable. Furthermore, a user selected

power-up time-out (TPWRT) is applied. The TPWRT

parameter is based on device Configuration bits and

can be 0 ms (no delay), 4 ms, 16 ms or 64 ms. The total

delay is at device power-up, TPOR + TPWRT. When

these delays have expired, SYSRST will be negated on

the next leading edge of the Q1 clock and the PC will

jump to the Reset vector.

The timing for the SYSRST signal is shown in

Figure 17-3 through Figure 17-5.

FIGURE 17-2: RESET SYSTEM BLOCK DIAGRAM

MCLR

VDD

VDD Rise

Detect POR

SYSRST

Sleep or Idle

Brown-out

Reset BOREN

RESET

Instruction

WDT

Module

Digital

Glitch Filter

BOR

Trap Conflict

Illegal Opcode/

Uninitialized W Register

dsPIC30F2011/2012/3012/3013

FIGURE 17-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIE D T O VDD)

FIGURE 17-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1

FIGURE 17-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2

TPWRT

TOST

VDD

INTERNAL POR

PWRT TIME-OUT

OST TIME-OUT

INTERNAL Reset

MCLR

TPWRT

TOST

VDD

INTERNAL POR

PWRT TIME-OUT

OST TIME-OUT

INTERNAL Reset

MCLR

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

OST TIME-OUT

INTERNAL Reset

TPWRT

TOST

dsPIC30F2011/2012/3012/3013

17.3.1.1 POR with Long Crystal S tart-up Time

(with FSCM Enabled)

The oscillator start-up circuitry is not linked to the POR

circuitry. Some crystal circuits (especially low

frequency crystals) will have a relatively long start-up

time. Therefore, one or more of the following conditions

is possible after the POR timer and the PWRT have

expired:

• The oscillator circuit has not begun to oscillate.

• The Oscillator Start-up Timer has not expired (if a

crystal oscillator is used).

• The PLL has not achieved a LOCK (if PLL is

used).

If the FSCM is enabled and one of the above conditions

is true, then a clock failure trap will occur. The device

will automatically switch to the FRC oscillator and the

user can switch to the desired crystal oscillator in the

trap ISR.

17.3.1.2 Operating without FSCM and PWRT

If the FSCM is disabled and the Power-up Timer

(PWRT) is also disabled, then the device will exit ra p-

idly from Reset on power-up. If the clock source is

FRC, LPRC, ERC or EC, it will be active immediately.

If the FSCM is disabled and the system clock has not

started, the device will be in a frozen state at the Reset

vector until the system clock starts. From the user’s

perspective, the de vice will appear to be in Reset u ntil

a system clock is available.

17.3.2 BOR: PROGRAMMABLE

BROWN-OUT RESET

The BOR (Brown-out Reset) module is based on an

internal voltage reference circuit. The main purpose of

the BOR module is to generate a device Reset when a

brown-out condition occurs. Brown-out conditions are

generally caused by glitches on the AC mains

(i.e., missing portions of the AC cycle waveform due to

bad power transmission lines, or voltage sags due to

excessive current draw when a l arge inductive load is

turned on).

The BOR module allows selection of one of the

following voltage trip points (see Table 20-11):

• 2.6V-2.71V

• 4.1V-4.4V

• 4.58V-4.73V

A BOR will generate a Reset pulse which will reset the

device. The BOR will select the clock source based on

the device Configuration bit values (FOS<2:0> and

FPR<4:0>). Furthermore, if an Oscillator mode is

selected, the BOR will activate the Oscillator Start-up

Timer (OST). The system clock is held until OST

expires. If the PL L is used, then the clock will be he ld

until the LOCK bit (OSCCON<5>) is ‘1’.

Concurrently, the POR time-out (TPOR) and the PWRT

time-out (TPWRT) will be applied before the internal Reset

is released. If TPWRT = 0 and a crystal oscillator is being

used, then a nominal delay of TFSCM = 100 μs is applied.

The total delay in this case is (TPOR + TFSCM).

The BOR Status bit (RCON<1>) will be set to indicate

that a BOR has occurred. The BOR circuit, if enabled,

will continue to operate while in Sleep or Idle modes

and will reset the device should VDD fall below the BOR

threshold voltage.

FIGURE 17-6: EXTERNAL POWER-ON

RESET CIRCUIT (FOR

SLOW VDD POWER-UP)

Note: The BOR voltage trip points indicated here

are nominal values provided for design

guidance only. Refer to the Electrical

Specifications in the specific device data

sheet for BOR voltage limit specifications.

Note: Dedicated supervisory devices, such as

the MCP1XX and MCP8XX, may also be

used as an external Power-on Reset

circuit.

Note 1: External Power-on Reset circuit is required

only if the VDD power-up slope is too slow.

The diode D helps discharge the capacitor

quickly when VDD powers down.

2: R should be suitably chosen so as to make

sure that the voltage drop across R does not

violate the device’s electrical specifications.

3: R1 should be suitably chosen so as to limit

any current flowing into MCLR from external

capacitor C, in the event of MCLR/VPP pin

breakdown due to Electrostatic Discharge

(ESD) or Electrical Overstress (EOS).

VDD

dsPIC30F

MCLR

dsPIC30F2011/2012/3012/3013

Table 17-5 shows the Reset conditions for the RCON

are R/W, the information in the table means that all the

bits are negated prior to the action specified in the

condition column.

TABLE 17-5: INITIALIZATION CONDITION FOR RCON REGISTER: CASE 1

Table 17-6 shows a second example of the bit

conditions for the RCON register. In this case, it is not

assumed the user has set/cleared specific bits prior to

action specified in the condition column.

TABLE 17-6: INITIALIZATION CONDITION FOR RCON REGISTER: CASE 2

Condition Program

Counter TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR BOR

Power-on Reset 0x000000 000000011

Brown-out Reset 0x000000 000000001

MCLR Reset during normal

operation 0x000000 001000000

Software Reset during

normal operation 0x000000 000100000

MCLR Reset during Sleep 0x000000 001000100

MCLR Reset during Idle 0x000000 001001000

WDT Time-out Reset 0x000000 000010000

WDT Wake-up PC + 2 000010100

Interrupt Wake-up from

Sleep PC + 2(1) 000000100

Clock Failure Trap 0x0000 04 000000000

Trap Reset 0x000000 100000000

Illegal Operation Trap 0x000000 010000000

Note 1: When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector .

Condition Program

Counter TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR BOR

Power-on Reset 0x000000 000000011

Brown-out Reset 0x000000 uuuuuuu01

MCLR Reset during normal

operation 0x000000 uu10000uu

Software Reset during

normal operation 0x000000 uu01000uu

MCLR Reset during Sleep 0x000000 uu1u001uu

MCLR Reset during Idle 0x000000 uu1u010uu

WDT Time-out Reset 0x000000 uu00100uu

WDT Wake-up PC + 2 uuuu1u1uu

Interrupt Wake-up from

Sleep PC + 2(1) uuuuuu1uu

Clock Failure Trap 0x000004 uuuuuuuuu

Trap Reset 0x000000 1uuuuuuuu

Illegal Operation Reset 0x000000 u1uuuuuuu

Legend: u = unchanged

Note 1: When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector .

dsPIC30F2011/2012/3012/3013

17.4 Watchdog Timer (WDT)

17.4.1 WATCHDOG TIMER OPERATION

The primary function of the Watchdog Timer (WDT) is

to reset the processor in the event of a software

malfunction. The WDT is a free-running timer which

runs off an on-chip RC oscillator, requiring no external

component. Therefore, the WDT timer will continue to

operate even if the main processor clock (e.g., the

crystal oscillator) fails.

17.4.2 ENABLING AND DISABLING

THE WDT

The Watchdog Timer can be “Enabled” or “Disabled”

only through a Configuration bit (FWDTEN) in the

Configuration register, FWDT.

Setting FWDTEN = 1 enables the W atchdog T imer . The

enabling is done when programming the device. By

default, after chip erase, FWDTEN bi t = 1. Any device

programmer capable of programming dsPIC30F

devices allows programming of this and other

Configuration bits.

If enabled, the WDT will incr ement until it overfl ows or

“times out”. A WDT time-out will force a device Reset

(except during Sleep). To prevent a WDT time-out, the

user must clear the Watchdog Timer using a CLRWDT

instruction.

If a WDT times out during Sleep, the device will

wake-up. The WDTO bit in the RCON register will be

cleared to indicate a wake-up resulting from a WDT

time-out.

Setting FWDTEN = 0 allows user software to

enable/disable the Watchdog Timer via the SWDTEN

(RCON<5>) control bit.

17.5 Low-Voltage Detect

The Low-Voltage Detect (LVD) module is used to

detect when the VDD of the device drops below a

threshold value, VLVD, which is determined by the

LVDL<3:0> bits (RCON<11:8>) and is thus user pro-

grammable. The internal voltage reference circuitry

requires a nominal amount of time to stabilize, and th e

BGST bit (RCON<13>) indicates when the voltage

reference has stabilized.

In some devices, the LVD threshold voltage may be

applied externally on the LVDIN pin.

The LVD module is enabled by setting the LVDEN bit

(RCON<12>).

17.6 Power-Saving Modes

There are two power-saving states that can be entered

through the execution of a special instruction, PWRSAV;

these are Sleep and Idle.

The format of the PWRSAV instruction is as follows:

PWRSAV <parameter>, where ‘parameter’ defi nes

Idle or Sleep mode.

17.6.1 SLEEP MODE

In Sleep mode, the clock to the CPU and peripherals is

shut down. If an on-chip oscillator is being used, it is

shut down.

The Fail-Safe Clock Monitor is not functional during

Sleep since there is no clock to monitor. However,

LPRC clock remains active if WDT is operational during

Sleep.

The brown-out protection circuit and the Low-Voltage

Detect circuit, if enabled, will remain functional during

Sleep.

The processor wakes up from Sleep if at least one of

the followin g co nd i ti o ns ha s occurred:

• any interrupt that is individually enabled and

meets the re qu i re d pri o ri ty le ve l

• any Reset (POR , BOR and MCLR)

• WDT time-out

On waking up from Sleep mode, the processor will

restart the same clock that was active prior to entry into

Sleep mode. When clock switching is enabled, bits

COSC<2:0> will determine the oscillator source that

will be used on wake-up. If clock switch is disabled,

then there is only one system clock.

If the clock source is an oscillator, the clock to the

device will be hel d off until OST time s out (in dicating a

stable oscillator). If PLL is used, the system clock is

held off until LOCK = 1 (indicating that the PLL is

stable). In either case, TPOR, TLOCK and TPWRT delays

are applied.

If EC, FRC, LPRC or ERC oscilla tors are used, th en a

delay of TPOR (~ 10 μs) is applied. This is the smallest

delay possible on wake-up from Slee p.

Moreover, i f LP oscillator was active during Sleep a nd

LP is the oscillator used on wake-u p, then the start-up

delay will be equal to TPOR. PWRT delay and OST

timer delay are not applied. In order to have the

smallest possible start-up delay when waking up from

Sleep, one of these faster wa ke-up options should be

selected before entering Sleep.

Note: If a POR or BOR occurred, the selection of

the oscillator is based on the FOS<2:0>

and FPR<4:0> Configuration bits.

dsPIC30F2011/2012/3012/3013

Any interrupt that is individually enabled (using the

corresponding IE bit) and meets the prevailing priority

level will be able to wake-up the processor. The

processor will process the interrupt and branch to the

ISR. The Sleep Status bit in the RCON register is set

upon wake-up.

All Resets will wake-up the processor from Sleep

mode. Any Reset, other than POR, will set the Sleep

Status bit. In a POR, the Sleep bit is cleared.

If the Watchdog Timer is enabled, then the processor

will wake-up from Sleep mode upon WDT time-out. The

Sleep and WDTO Status bits are both set.

17.6.2 IDLE MODE

In Idle mode, the clock to the CPU i s shut down while

peripherals keep running. Unlike Sleep mode, the clock

source remains active.

Several periphera ls have a control bit in each module

that allows them to operate during Idle.

LPRC Fail-Safe Clock remains active if clock failure

detect is enabled.

The processor wakes up from Idle if at least one of the

following conditions has occurred:

• any interrupt that is individually enabled (IE bit is

‘1’) and meets the required priority level

• any Reset (POR, BOR, MCLR)

• WDT time-out

Upon wake-up from Idle mode, the clock is re-applied

to the CPU and instruction execution begins

immediately, starting with the instruction following the

PWRSAV instruction.

Any interrupt that is individually enabled (using IE bit)

and meets the prevailing priority level will be able to

wake-up the processor . The processor will process the

interrupt and branch to the ISR. The Idle Status bit in

the RCON register is set upon wake-up.

Any Reset other than POR will set the Idle Status bit.

On a POR, the Idle bit is cleared.

If Watchdog Timer is enabled, then the processor will

wake-up from Idle mode upo n WDT time-out. The Idle

and WDTO Status bits are both set.

Unlike wake-up from Sleep, there are no time delays

involved in wake-up from Idle.

17.7 Device Configuration Registers

The Configuration bits in each device Configuration

programmed by a device pr ogrammer, or by using the

In-Circuit Serial Programming™ (ICSP™) feature of

the device. Each device Configuration register is a

24-bit register, but only the lower 16 bits of each

five device Configuration registers available to the

user:

1. FOSC (0xF80000): Oscillator Config uration

2. FWDT (0xF80002): Watchdog Timer

Configuration Register

3. FBORPOR (0xF80004): BOR and POR

Configuration Register

4. FGS (0xF8000A): General Code Se gment

Configuration Register

5. FICD (0xF8000C): Debug Confi guration

The placement of the Configuration bits is

automatically handled when you select the device in

your device programmer. The desired state of the

Configuration bits may be specified in the source code

(dependent on the language tool u sed), or throug h the

programming interface. After the device has been

programmed, the application software may read the

Configuration bit values through the table read

instructions. For additional info rmation, please refer to

the Programming Specifications of the device.

Note: In spite of various delays applied (TPOR,

TLOCK and TPWRT), the crystal oscillator

(and PLL) may not be active at the e nd of

the time-out (e.g., for low-frequency

crystals). In such cases, if FSCM is

enabled, then the device will detect this as

a clock failure and process the clock failure

trap, the FRC oscillator will be enabled and

the user will have to re-enable the crystal

oscillator. If FSCM is not enabled, then the

device will simply suspend execution of

code until the clock is stable and will remain

in Sleep until the oscillator clock has

started.

Note: If the code protection Configuration fuse

bits (FGS<GCP> and FGS<GWRP>)

have been programmed, an erase of the

entire code-protected device is only

possible at voltages VDD ≥ 4.5V.

dsPIC30F2011/2012/3012/3013

17.8 Peripheral Module Disable (PMD)

Registers

The Peripheral Module Disable (PMD) registers

provide a method to disable a peripheral module by

stopping all clock sources supplied to that module.

When a peripheral is disabled via the appropriate PMD

control bit, the peripheral is in a minimum power

consumption state. The Control and Status registers

associated with the peripheral will also be disabled so

writes to those registers will have no effect and read

values will be invalid.

A peripheral module will only be enabled if both the

associated bit in the PMD register is cleared and the

peripheral is supported by the specific dsPIC DSC

variant. If the peripheral is present in the device, it is

enabled in the PMD register by default.

17.9 In-Circuit Debugger

When MPLAB® ICD 2 is selected as a Debugger, the

In-Circuit Debugging functionality is enabled. This

function allows simple debugging functions when used

with MPLAB IDE. When the device has this feature

enabled, some of the resources are not available for

general use. These resources include the first 80 bytes

of Data RAM and two I/O pins.

One of four pairs of Debug I/O pins may be selected by

the user using configuration options in MPLAB IDE.

These pin pairs are named EMUD/EMUC,

EMUD1/EMUC1, EMUD2/EMUC2 and

EMUD3/EMUC3.

In each case, the selected EMUD pin is the

Emulation/Debug Data line, and the EMUC pin is the

Emulation/Debug Clock line. These pins will interface

to the MPLAB ICD 2 module available from Microchip.

The selected pair of Debug I/O pins is used by MPLAB

ICD 2 to send commands and receive responses, as

well as to send a nd receive data. To use the In-Circuit

Debugger function of the device, the design must

implement ICSP connections to MCLR, VDD, VSS,

PGC, PGD and the selected EMUDx/EMUCx pin pair.

This gives rise to two possibilities:

1. If EMUD/EMUC is selected as the Debug I/O pin

pair, then only a 5-pin interface is required, as

the EMUD and EMUC pin functions are multi-

plexed with the PGD and PGC pin functions in

all dsPIC30F devices.

2. If EMUD1/EMUC1, EMUD2/EMUC2 or

EMUD3/EMUC3 is selected as the Debug I/O

pin pair , then a 7-pin interface is required, as the

EMUDx/EMUCx pin functions (x = 1, 2 or 3) are

not multiplexed with the PGD and PGC pin

functions.

Note 1: If a PMD bit is set, the corresponding

module is disabled after a delay of 1

instruction cycle. Similarly, if a PMD bit is

cleared, the corresponding module is

enabled after a delay of 1 instruction

cycle (assuming the module Control reg-

isters are already configured to enable

module operati on).

2: In dsPIC30F2011, dsPIC30F3012 and

dsPIC30F2012 devices, the U2MD bit is

readable and writable and will be read as

‘1’ when set.

dsPIC30F2011/2012/3012/3013

TABLE 17-7: SYSTEM INTEGRATION REGISTER MAP

TABLE 17-8: DEVICE CONFIGURATION REGISTER MAP

SFR

Name Address Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

RCON 0740 TRAPR IOPUWR BGST LVDEN LVDL<3:0> EXTR SWR SWDTEN WDTO SLEEP IDLE BOR POR (Note 1)

OSCCON 0742 —COSC<2:0>— NOSC<2:0> POST<1:0> LOCK —CF— LPOSCEN OSWEN (Note 2)

OSCTUN 0744 — — — — — — — — — — — — TUN3 TUN2 TUN1 TUN0 (Note 2)

PMD1 0770 —— T3MD T2MD T1MD — — — I2CMD U2MD(3) U1MD — SPI1MD —— ADCMD 0000 0000 0000 0000

PMD2 0772 — — — — — —IC2MDIC1MD— — — — — —OC2MDOC1MD0000 0000 0000 0000

Legend: — = unimplemented bit, read as ‘0’

Note 1: Reset state depends on type of reset .

2: Reset state depends on Configuration bits.

3: Only available on dsPIC30F3013 devices.

Name Address Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

FOSC F80000 FCKSM<1:0> ——— FOS<2:0> — — — FPR<4:0>

FWDT F80002 FWDTEN — — — — — — — — — FWPSA<1:0> FWPSB<3:0>

FBORPOR F80004 MCLREN — — — —

PWMPIN

(1)

HPOL

(1)

LPOL

(1)

BOREN —BORV<1:0>——FPWRT<1:0>

FBS F80006 —— Reserved(2) ——— Reserved(2) — — — — Reserved(2)

FSS F80008 —— Reserved(2) —— Reserved(2) — — — — Reserved(2)

FGS F8000A — — — — — — — — — — — — — Reserved(3) GCP GWRP

FICD F8000C BKBUG COE — — — — — — — — — — — —ICS<1:0>

Legend: — = unimplemented bit, read as ‘0’

Note 1: These bits are reserved (read as ‘1’ and must be programmed as ‘1’).

2: Reserved bits read as ‘1’ and must be programmed as ‘1’.

3: The FGS<2> bit is a read-only copy of the GCP bit (FGS<1>).

dsPIC30F2011/2012/3012/3013

18.0 INSTRUCTION SET SUMMARY

The dsPIC30F instruction set adds many

enhancements to the previous PIC® MCU instruction

sets, while maintaining an easy migration from PIC

MCU instruction sets.

Most instructions are a single program memory word

(24 bits). Only three instructions require two program

memory locations.

Each single-word instruction is a 24-bit word divided

into an 8-bit opcode which specifies the instruction

type, and one or more o perands which further specify

the operation of the instruction.

The instruction set is highly ortho gonal an d is gr ouped

into five basic categories:

• Word or byte-oriented operations

• Bit-oriented operations

• Literal operations

• DSP operations

• Control operations

Table 18-1 shows the general symbols used in

describing the instructions.

The dsPIC30F instruction set summary in Table 18-2

lists all the instructions, along with the status flags

affected by each instruction.

Most word or byte-oriented W register instructions

(including barrel shift instructions) have three

operands:

• The first source operand whic h is typically a

• The second source operand which is typically a

• The destination of the result which is typically a

However , word or byte-oriented file register instructions

have two operands:

• The file register specified by the value ‘f’

• The destination, which could either be the file

‘WREG’

Most bit-oriented instructions (including simple

rotate/shift instructions) have two operands:

• The W register (with or without an address

modifier) or file register (specified by the value of

‘Ws’ or ‘f’)

• The bit in the W register or file register

(specified by a literal value or indirectly by the

contents of register ‘Wb’)

The literal instructions that involve data movement may

use some of the following operands:

• A literal value to be loaded into a W register or file

• The W register or file register where the literal

value is to be loaded (specified by ‘Wb’ or ‘f’)

However, literal instructions that involve arithmetic or

logical operations use some of the following operands:

• The first source operand which is a register ‘Wb’

without any address modifier

• The second source operand which is a literal

value

• The destination of the result (only if not the same

as the first source operand) which is typically a

The MAC class of DSP instructions may use some of the

following operands:

• The accumulator (A or B) to be used (required

operand)

• The W registers to be used as the two operands

• The X and Y address space prefetch operations

• The X and Y address space prefetch destinations

• The accumulator write-back destination

The other DSP instructions do not involve any

multiplication, and may include:

• The accumulator to be used (required)

• The source or destination operand (designated as

Wso or Wdo, respectively) with or without an

address modifier

• The amount of shift specified by a W register ‘Wn’

or a literal value

The control instructions may use some of the following

operands:

• A program memory address

• The mode of the table read and table write

instructions

Note: This data sheet summarizes features of

this group of dsPIC30F devices and is not

intended to be a complete reference

source. For more information on the CPU,

peripherals, register descriptions and

general device functionality, refer to the

“dsPIC30F Family Reference Manual”

(DS70046). For more information on the

device instruction set and programming,

refer to the “dsPIC30F Programmer’s

Reference Manual” (DS70030).

dsPIC30F2011/2012/3012/3013

All instructions are a single word, except for certain

double-word instructions, which were made

double-word instructions so that all the required

information is available in these 48 bits. In the second

word, the 8 MSbs are ‘0’s. If this second word is

executed as an instruction (by itself), it will exe cute as

a NOP.

Most single-word instru ctions are executed in a single

instruction cycle, unless a conditional test is true or the

program counter is changed as a result of the

instruction. In these cases, the execution takes two

instruction cycles with the additional instruction

cycle(s) executed as a NOP. Notable exceptions are the

BRA (unconditional/computed branch), indirect

CALL/GOTO, all table reads and writes, and

RETURN/RETFIE instructions, which are single-word

instructions but take two or three cycles. Certain

instructions that involve skipping over the subsequent

instruction require either two or three cycles if the skip

is performed, depending on whether the instruction

being skipped is a single-word or two-word instruction.

Moreover, double-word moves require two cycles. The

double-word instructions execute in two instruction

cycles.

Note: For more details on the instruction set,

refer to the “MCU and DSC Programmer’s

Reference Manual” (DS70157).

TABLE 18-1: SYMBOLS USED IN OPCODE DESCRIPTIONS

Field Description

#text Means literal defined by “text”

(text) Means “content of text”

[text] Means “the location addressed by text”

{ } Optional field or operation

<n:m> Register bit field

.b Byte mode selection

.d Double-Word mode selection

.S Shadow register select

.w Word mode selection (default)

Acc One of two accumulators {A, B}

AWB Accumulator write-back destination address register ∈ {W13, [W13]+=2}

bit4 4-bit b it selection field (used in word addressed instructions) ∈ {0...15}

C, DC, N, OV, Z MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero

Expr Absolute address, label or expression (resolved by the linker)

f File register address ∈ {0x0000...0x1FFF}

lit1 1-bit unsigned literal ∈ {0,1}

lit4 4-bit unsigned literal ∈ {0...15}

lit5 5-bit unsigned literal ∈ {0...31}

lit8 8-bit unsigned literal ∈ {0...255}

lit10 10-bit unsigned literal ∈ {0...255} for Byte mode, {0:1023} for Word mode

lit14 14-bit unsigned literal ∈ {0...16384}

lit16 16-bit unsigned literal ∈ {0...65535}

lit23 23-bit unsigned literal ∈ {0...8388608}; LSB must be 0

None Field does not require an entry, may be blank

OA, OB, SA, SB DSP Status bits: ACCA Overflow, ACCB Overflow, ACCA Saturate, ACCB Saturate

PC Program Counter

Slit10 10-bit signed literal ∈ {-512...511}

Slit16 16-bit signed literal ∈ {-32768...32767}

Slit6 6-bit signed literal ∈ {-16...16}

dsPIC30F2011/2012/3012/3013

Wb Base W register ∈ {W0..W15}

Wd Destination W register ∈ { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] }

Wdo Destination W register ∈

{ Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] }

Wm,Wn Dividend, Divisor working register pair (direct addressing)

Wm*Wm Multiplicand and Multiplier working register pair for Square instructions ∈

{W4*W4,W5*W5,W6*W6,W7*W7}

Wm*Wn Multiplicand and Multiplier working register pair for DSP instructions ∈

{W4*W5,W4*W6,W4*W7,W5*W6,W5*W7,W6*W7}

Wn One of 16 working registers ∈ {W0..W15}

Wnd One of 16 destination working registers ∈ {W0..W15}

Wns One of 16 source working registers ∈ {W0..W15}

WREG W0 (working register used in file register instructions)

Ws Source W register ∈ { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] }

Wso Source W register ∈

{ Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] }

Wx X data space prefetch address register for DSP instructions

∈ {[W8]+=6, [W8]+=4, [W8]+=2, [W8], [W8]-=6, [W8]-=4, [W8]-=2,

[W9]+=6, [W9]+=4, [W9]+=2, [W9], [W9]-=6, [W9]-=4, [W9]-=2,

[W9+W12],none}

Wxd X data space prefetch destination register for DSP instructions ∈ {W4..W7}

Wy Y data space prefetch address register for DSP instructions

∈ {[W10]+=6, [W10]+=4, [W10]+=2, [W10], [W10]-=6, [W10]-=4, [W10]-=2,

[W11]+=6, [W11]+=4, [W11]+=2, [W11], [W11]-=6, [W11]-=4, [W11]-=2,

[W11+W12], none}

Wyd Y data space prefetch destination register for DSP instructions ∈ {W4..W7}

TABLE 18-1: SYMBOLS USED IN OPCODE DESCRIPTIONS (CONTINUED)

Field Description

dsPIC30F2011/2012/3012/3013

TABLE 18-2: INSTRUCTION SET OVERVIEW

Base

Instr

Assembly

Mnemonic Assembly Syntax Description # of

Words

# of

Cycle

Status Flags

Affected

1ADD ADD Acc Add Accumulators 1 1 OA,OB,SA,SB

ADD f f = f + WREG 1 1 C,DC,N,OV,Z

ADD f,WREG WREG = f + WREG 1 1 C,DC,N,OV,Z

ADD #lit10,Wn Wd = lit10 + Wd 1 1 C,DC,N,OV,Z

ADD Wb,Ws,Wd Wd = Wb + Ws 1 1 C,DC,N,OV,Z

ADD Wb,#lit5,Wd Wd = Wb + lit5 1 1 C,DC,N,OV,Z

ADD Wso,#Slit4,Acc 16-bit Signed Add to Accumulator 1 1 OA,OB,SA,SB

2 ADDC ADDC f f = f + WREG + (C) 1 1 C,DC,N,OV,Z

ADDC f,WREG WREG = f + WREG + (C) 1 1 C,DC,N,OV,Z

ADDC #lit10,Wn Wd = lit10 + Wd + (C) 1 1 C,DC,N,OV,Z

ADDC Wb,Ws,Wd Wd = Wb + Ws + (C) 1 1 C,DC,N,OV,Z

ADDC Wb,#lit5,Wd Wd = Wb + lit5 + (C) 1 1 C,DC,N,OV,Z

3AND AND f f = f .AND. WREG 1 1 N,Z

AND f,WREG WREG = f .AND. WREG 1 1 N,Z

AND #lit10,Wn Wd = lit10 .AND. Wd 1 1 N,Z

AND Wb,Ws,Wd Wd = Wb .AND. Ws 1 1 N,Z

AND Wb,#lit5,Wd Wd = Wb .AND. lit5 1 1 N,Z

4 ASR ASR f f = Arithmetic Right Shift f 1 1 C,N,OV,Z

ASR f,WREG WREG = Arithmetic Right Shift f 1 1 C,N,OV,Z

ASR Ws,Wd Wd = Arithmetic Right Shift Ws 1 1 C,N,OV,Z

ASR Wb,Wns,Wnd Wnd = Arithmetic Right Shift Wb by Wns 1 1 N,Z

ASR Wb,#lit5,Wnd Wnd = Arithmetic Right Shift Wb by lit5 1 1 N,Z

5BCLRBCLR f,#bit4 Bit Clear f 1 1 None

BCLR Ws,#bit4 Bit Clear Ws 1 1 None

6BRA BRA C,Expr Branch if Carry 1 1 (2) None

BRA GE,Expr Branch if greater than or equal 1 1 (2) None

BRA GEU,Expr Branch if unsigned greater than or equal 1 1 (2) None

BRA GT,Expr Branch if greater than 1 1 (2) None

BRA GTU,Expr Branch if unsigned greater tha n 1 1 (2) None

BRA LE,Expr Branch if less than or equal 1 1 (2) None

BRA LEU,Expr Branch if unsigned less than or equal 1 1 (2) None

BRA LT,Expr Branch if less than 1 1 (2) None

BRA LTU,Expr Branch if unsigned less than 1 1 (2) None

BRA N,Expr Branch if Negative 1 1 (2) None

BRA NC,Expr Bra nch if Not Carry 1 1 (2) None

BRA NN,Expr Bra nch if Not Negative 1 1 (2) None

BRA NOV,Expr Branch if Not Overflow 1 1 (2) None

BRA NZ,Expr Branch if Not Zero 1 1 (2) None

BRA OA,Expr Branch if Accumulator A overflow 1 1 (2) None

BRA OB,Expr Branch if Accumulator B overflow 1 1 (2) None

BRA OV,Expr Branch if Overflow 1 1 (2) None

BRA SA,Expr Branch if Accumulator A saturated 1 1 (2) None

BRA SB,Expr Branch if Accumulator B saturated 1 1 (2) None

BRA Expr Branch Unconditionally 1 2 None

BRA Z,Expr Branch if Zero 1 1 (2) None

BRA Wn Computed Branch 1 2 None

7 BSET BSET f,#bit4 Bit Set f 1 1 None

BSET Ws,#bit4 Bit Set Ws 1 1 None

8 BSW BSW.C Ws,Wb Write C bit to Ws<Wb> 1 1 None

BSW.Z Ws,Wb Write Z bit to Ws<Wb> 1 1 None

dsPIC30F2011/2012/3012/3013

9BTG BTG f,#bit4 Bit Toggle f 1 1 None

BTG Ws,#bit4 Bit Toggle Ws 1 1 None

10 BTSC BTSC f,#bit4 Bit Test f, Skip if Clear 1 1

(2 or 3) None

BTSC Ws,#bit4 Bit Test Ws, Skip if Clear 1 1

(2 or 3) None

11 BTSS BTSS f,#bit4 Bit Test f, Skip if Set 1 1

(2 or 3) None

BTSS Ws,#bit4 Bit Test Ws, Skip if Set 1 1

(2 or 3) None

12 BTST BTST f,#bit4 Bit Test f 1 1 Z

BTST.C Ws,#bit4 Bit Test Ws to C 1 1 C

BTST.Z Ws,#bit4 Bit Test Ws to Z 1 1 Z

BTST.C Ws,Wb Bit Test Ws<Wb> to C 1 1 C

BTST.Z Ws,Wb Bit Test Ws<Wb> to Z 1 1 Z

13 BTSTS BTSTS f,#bit4 Bit Test then Set f 1 1 Z

BTSTS.C Ws,#bit4 Bit Test Ws to C, then Set 1 1 C

BTSTS.Z Ws,#bit4 Bit Test Ws to Z, then Set 1 1 Z

14 CALL CALL lit23 Call subroutine 2 2 None

CALL Wn Call indirect subroutine 1 2 None

15 CLR CLR f f = 0x0000 1 1 None

CLR WREG WREG = 0x0000 1 1 None

CLR Ws Ws = 0x0000 1 1 None

CLR Acc,Wx,Wxd,Wy,Wyd,AWB Clear Accumulator 1 1 OA,OB,SA,SB

16 CLRWDT CLRWDT Clear Watchdog Timer 1 1 WDTO,Sleep

17 COM COM f f = f 11 N,Z

COM f,WREG WREG = f 11 N,Z

COM Ws,Wd Wd = Ws 11 N,Z

18 CP CP f Compare f with WREG 1 1 C,DC,N,OV,Z

CP Wb,#lit5 Compare Wb with lit5 1 1 C,DC,N,OV,Z

CP Wb,Ws Compare Wb with Ws (Wb - Ws) 1 1 C,DC,N,OV,Z

19 CP0 CP0 f Compare f with 0x0000 1 1 C,DC,N,OV,Z

CP0 Ws Compare Ws with 0x0000 1 1 C,DC,N,OV,Z

20 CPB CPB f Compare f with WREG, with Borrow 1 1 C,DC,N,OV,Z

CPB Wb,#lit5 Compare Wb with lit5, with Borrow 1 1 C,DC,N,OV,Z

CPB Wb,Ws Compare Wb with Ws, with Borrow

(Wb - Ws - C)1 1 C,DC,N,OV,Z

21 CPSEQ CPSEQ Wb, Wn Compare Wb with Wn, skip if = 1 1

(2 or 3) None

22 CPSGT CPSGT Wb, Wn Compare Wb with Wn, skip if > 1 1

(2 or 3) None

23 CPSLT CPSLT Wb, Wn Compare Wb with Wn, skip if < 1 1

(2 or 3) None

24 CPSNE CPSNE Wb, Wn Compare Wb with Wn, skip if ≠11

(2 or 3) None

25 DAW DAW Wn Wn = decimal adjust Wn 1 1 C

26 DEC DEC f f = f -1 1 1 C,DC,N,OV,Z

DEC f,WREG WREG = f -1 1 1 C,DC,N,OV,Z

DEC Ws,Wd Wd = Ws - 1 1 1 C,DC,N,OV,Z

27 DEC2 DEC2 f f = f -2 1 1 C,DC,N,OV,Z

DEC2 f,WREG WREG = f -2 1 1 C,DC,N,OV,Z

DEC2 Ws,Wd Wd = Ws - 2 1 1 C,DC,N,OV,Z

28 DISI DISI #lit14 Disable Interrupts for k instruction cycles 1 1 None

TABLE 18-2: INSTRUCTION SET OVERVIEW (CONTINUED)

Base

Instr

Assembly

Mnemonic Assembly Syntax Description # of

Words

# of

Cycle

Status Flags

Affected

dsPIC30F2011/2012/3012/3013

29 DIV DIV.S Wm,Wn Signed 16/16-bit Integer Divide 1 18 N,Z,C,OV

DIV.SD Wm,Wn Signed 32/16-bit Integer Divide 1 18 N,Z,C,OV

DIV.U Wm,Wn Unsigned 16/16-bit Integer Divide 1 18 N,Z,C,OV

DIV.UD Wm,Wn Unsigned 32/16-bit Integer Divide 1 18 N,Z,C,OV

30 DIVF DIVF Wm,Wn Signed 16/16-bit Fractional Divide 1 18 N,Z,C,OV

31 DO DO #lit14,Expr Do code to PC+Expr, lit14+1 times 2 2 None

DO Wn,Expr Do code to PC+Expr, (Wn)+1 times 2 2 None

32 ED ED Wm*Wm,Acc,Wx,Wy,Wxd Euclidean Distance (no accumulate) 1 1 OA,OB,OAB,

SA,SB,SAB

33 EDAC EDAC Wm*Wm,Acc,Wx,Wy,Wxd Euclidean Distance 1 1 OA,OB,OAB,

SA,SB,SAB

34 EXCH EXCH Wns,Wnd Swap Wns with Wnd 1 1 None

35 FBCL FBCL Ws,Wnd Find Bit Change from Left (MSb) Side 1 1 C

36 FF1L FF1L Ws,Wnd Find First One from Left (MSb) Side 1 1 C

37 FF1R FF1R Ws,Wnd Find First One from Right (LSb) Side 1 1 C

38 GOTO GOTO Expr Go to address 2 2 None

GOTO Wn Go to indirect 1 2 None

39 INC INC f f = f + 1 1 1 C,DC,N,OV,Z

INC f,WREG WREG = f + 1 1 1 C,DC,N,OV,Z

INC Ws,Wd Wd = Ws + 1 1 1 C,DC,N,OV,Z

40 INC2 INC2 f f = f + 2 1 1 C,DC,N,OV,Z

INC2 f,WREG WREG = f + 2 1 1 C,DC,N,OV,Z

INC2 Ws,Wd Wd = Ws + 2 1 1 C,DC,N,OV,Z

41 IOR IOR f f = f .IOR. WREG 1 1 N,Z

IOR f,WREG WREG = f .IOR. WREG 1 1 N,Z

IOR #lit10,Wn Wd = lit10 .IOR. Wd 1 1 N,Z

IOR Wb,Ws,Wd Wd = Wb .IOR. Ws 1 1 N,Z

IOR Wb,#lit5,Wd Wd = Wb .IOR. lit5 1 1 N , Z

42 LAC LAC Wso,#Slit4,Acc Load Accumulator 1 1 OA,OB,OAB,

SA,SB,SAB

43 LNK LNK #lit14 Link frame pointer 1 1 None

44 LSR LSR f f = Logical Right Shift f 1 1 C,N,OV,Z

LSR f,WREG WREG = Logical Right Shift f 1 1 C,N,OV,Z

LSR Ws,Wd Wd = Logical Right Shift Ws 1 1 C,N,OV,Z

LSR Wb,Wns,Wnd Wnd = Logical Right Shift Wb by Wns 1 1 N,Z

LSR Wb,#lit5,Wnd Wnd = Logical Right Shift Wb by lit5 1 1 N,Z

45 MAC MAC Wm*Wn,Acc,Wx,Wxd,Wy,Wyd

AWB

Multiply and Accumulate 1 1 OA,OB,OAB,

SA,SB,SAB

MAC Wm*Wm,Acc,Wx,Wxd,Wy,Wyd Square and Accumulate 1 1 OA,OB,OAB,

SA,SB,SAB

46 MOV MOV f,Wn Move f to Wn 1 1 None

MOV f Move f to f 1 1 N,Z

MOV f,WREG Move f to WREG 1 1 N,Z

MOV #lit16,Wn Move 16-bit literal to Wn 1 1 None

MOV.b #lit8,Wn Move 8-bit literal to Wn 1 1 None

MOV Wn,f Move Wn to f 1 1 None

MOV Wso,Wdo Move Ws to Wd 1 1 None

MOV WREG,f Move WREG to f 1 1 N,Z

MOV.D Wns,Wd Move Double from W(ns):W(ns+1) to Wd 1 2 None

MOV.D Ws,Wnd Move Double from Ws to W(nd+1):W(nd) 1 2 None

47 MOVSAC MOVSAC Acc,Wx,Wxd,Wy,Wyd,AWB Prefetch and store accumulator 1 1 None

TABLE 18-2: INSTRUCTION SET OVERVIEW (CONTINUED)

Base

Instr

Assembly

Mnemonic Assembly Syntax Description # of

Words

# of

Cycle

Status Flags

Affected

dsPIC30F2011/2012/3012/3013

48 MPY MPY

Wm*Wn,Acc,Wx,Wxd,Wy,Wyd Multiply Wm by Wn to Accumulator 1 1 OA,OB,OAB,

SA,SB,SAB

MPY

Wm*Wm,Acc,Wx,Wxd,Wy,Wyd Square Wm to Acc umulator 1 1 OA,OB,OAB,

SA,SB,SAB

49 MPY.N MPY.N

Wm*Wn,Acc,Wx,Wxd,Wy,Wyd -(Multiply Wm by Wn) to Accumulator 1 1 None

50 MSC MSC Wm*Wm,Acc,Wx,Wxd,Wy,Wyd

AWB

Multiply and Subtract from Accumulator 1 1 OA,OB,O AB,

SA,SB,SAB

51 MUL MUL.SS Wb,Ws,Wnd {Wnd+1, Wnd} = signed(Wb) * signed(Ws) 1 1 None

MUL.SU Wb,Ws,Wnd {Wnd+1, Wnd} = signed(Wb) *

unsigned(Ws) 11 None

MUL.US Wb,Ws,Wnd {Wnd+1, Wnd} = unsigned(Wb) *

signed(Ws) 11 None

MUL.UU Wb,Ws,Wnd {Wnd+1, Wnd} = unsigned(Wb) *

unsigned(Ws) 11 None

MUL.SU Wb,#lit5,Wnd {Wnd+1, Wnd} = sign ed(Wb) * unsigned(lit5) 1 1 None

MUL.UU Wb,#lit5,Wnd {Wnd+1, Wnd} = unsigned(Wb) *

unsigned(lit5) 11 None

MUL f W3:W2 = f * WREG 1 1 None

52 NEG NEG Acc Negate Accumulator 1 1 OA,OB,OAB,

SA,SB,SAB

NEG f f = f + 1 1 1 C,DC,N,OV,Z

NEG f,WREG WREG = f + 1 1 1 C,DC,N,OV,Z

NEG Ws,Wd Wd = Ws + 1 1 1 C,DC,N,OV,Z

53 NOP NOP No Operation 1 1 None

NOPR No Operation 1 1 None

54 POP POP f Pop f from top-of-stack (TOS) 1 1 None

POP Wdo Pop from top-of-sta ck (TOS) to Wdo 1 1 None

POP.D Wnd Pop from top-of-stack (TOS) to

W(nd):W(nd+1) 12 None

POP.S Pop Shadow Registers 1 1 All

55 PUSH PUSH f Push f to top-of-stack (TOS) 1 1 None

PUSH Wso Push Wso to top-of-st ack (TOS) 1 1 None

PUSH.D Wns Push W(ns):W(ns+1) to top-of-st ack (TOS) 1 2 None

PUSH.S Push Shadow Registers 1 1 None

56 PWRSAV PWRSAV #lit1 Go into Sleep or Idle mode 1 1 WDTO,Sleep

57 RCALL RCALL Expr Relative Call 1 2 None

RCALL Wn Computed Call 1 2 None

58 REPEAT REPEAT #lit14 Repeat Next Instruction lit14+1 times 1 1 None

REPEAT Wn Repeat Next Instruction (Wn)+1 times 1 1 None

59 RESET RESET Software device Reset 1 1 None

60 RETFIE RETFIE Return from interrupt 1 3 (2) None

61 RETLW RETLW #lit10,Wn Return with literal in Wn 1 3 (2) None

62 RETURN RETURN Return from Subroutine 1 3 (2) None

63 RLC RLC f f = Rotate Left through Carry f 1 1 C,N,Z

RLC f,WREG WREG = Rotate Left through Carry f 1 1 C,N,Z

RLC Ws,Wd Wd = Rotate Left through Carry Ws 1 1 C,N,Z

64 RLNC RLNC f f = Rotate Left (No Carry) f 1 1 N,Z

RLNC f,WREG WREG = Rotate Left (No Carry) f 1 1 N,Z

RLNC Ws,Wd Wd = Rotate Left (No Carry) Ws 1 1 N,Z

65 RRC RRC f f = Rotate Right through Carry f 1 1 C,N,Z

RRC f,WREG WREG = Rotate Right through Carry f 1 1 C,N,Z

RRC Ws,Wd Wd = Rotate Right through Carry Ws 1 1 C,N,Z

TABLE 18-2: INSTRUCTION SET OVERVIEW (CONTINUED)

Base

Instr

Assembly

Mnemonic Assembly Syntax Description # of

Words

# of

Cycle

Status Flags

Affected

dsPIC30F2011/2012/3012/3013

66 RRNC RRNC f f = Rotate Right (No Carry) f 1 1 N,Z

RRNC f,WREG WREG = Rotate Right (No Carry) f 1 1 N,Z

RRNC Ws,Wd Wd = Rotate Right (No Carry) Ws 1 1 N,Z

67 SAC SAC Acc,#Slit4,Wdo Store Accumulator 1 1 None

SAC.R Acc,#Slit4,Wdo Stor e Rounded Accumulator 1 1 None

68 SE SE Ws,Wnd Wnd = sign-extended Ws 1 1 C,N,Z

69 SETM SETM f f = 0xFFFF 1 1 None

SETM WREG WREG = 0xFFFF 1 1 None

SETM Ws Ws = 0xFFFF 1 1 None

70 SFTAC SFTAC Acc,Wn Arithmetic Shift Accumulator by (Wn) 1 1 OA,OB,OAB,

SA,SB,SAB

SFTAC Acc,#Slit6 Arithmetic Shift Accumulator by Slit 6 1 1 OA,OB,OAB,

SA,SB,SAB

71 SL SL f f = Left Shift f 1 1 C,N,OV,Z

SL f,WREG WREG = Left Shift f 1 1 C,N,OV,Z

SL Ws,Wd Wd = Left Shift Ws 1 1 C,N,OV,Z

SL Wb,Wns,Wnd Wnd = Left Shift Wb by Wns 1 1 N,Z

SL Wb,#lit5,Wnd Wnd = Left Shift Wb by lit5 1 1 N,Z

72 SUB SUB Acc Subtract Accumulators 1 1 OA,OB,OAB,

SA,SB,SAB

SUB f f = f - WREG 1 1 C,DC,N,OV,Z

SUB f,WREG WREG = f - WREG 1 1 C,DC,N,OV,Z

SUB #lit10,Wn Wn = Wn - lit10 1 1 C,DC,N,OV,Z

SUB Wb,Ws,Wd Wd = Wb - Ws 1 1 C,DC,N,OV,Z

SUB Wb,#lit5,Wd Wd = Wb - lit5 1 1 C,DC,N,OV,Z

73 SUBB SUBB f f = f - WREG - (C) 1 1 C,DC,N,OV,Z

SUBB f,WREG WREG = f - WREG - (C) 1 1 C,DC,N,OV,Z

SUBB #lit10,Wn Wn = Wn - lit10 - (C) 1 1 C,DC,N,OV,Z

SUBB Wb,Ws,Wd Wd = Wb - Ws - (C) 1 1 C,DC,N,OV,Z

SUBB Wb,#lit5,Wd Wd = Wb - lit5 - (C) 1 1 C,DC,N,OV,Z

74 SUBR SUBR f f = WREG - f 1 1 C,DC,N,OV,Z

SUBR f,WREG WREG = WREG - f 1 1 C,DC,N,OV,Z

SUBR Wb,Ws,Wd Wd = Ws - Wb 1 1 C,DC,N,OV,Z

SUBR Wb,#lit5,Wd Wd = lit5 - Wb 1 1 C,DC,N,OV,Z

75 SUBBR SUBBR f f = WREG - f - (C) 1 1 C,DC,N,OV,Z

SUBBR f,WREG WREG = WREG -f - (C) 1 1 C,DC,N,OV,Z

SUBBR Wb,Ws,Wd Wd = Ws - Wb - (C) 1 1 C,DC,N,OV,Z

SUBBR Wb,#lit5,Wd Wd = lit5 - Wb - (C) 1 1 C,DC,N,OV,Z

76 SWAP SWAP.b Wn Wn = nibble swap Wn 1 1 None

SWAP Wn Wn = byte swap Wn 1 1 None

77 TBLRDH TBLRDH Ws,Wd Read Prog<23:16> to Wd<7:0> 1 2 None

78 TBLRDL TBLRDL Ws,Wd Read Prog<15:0> to Wd 1 2 None

79 TBLWTH TBLWTH Ws,Wd Write Ws<7:0> to Prog<23:16> 1 2 None

80 TBLWTL TBLWTL Ws,Wd Write Ws to Prog<15:0> 1 2 None

81 ULNK ULNK Unlink frame pointer 1 1 None

82 XOR XOR f f = f .XOR. WREG 1 1 N,Z

XOR f,WREG WREG = f .XOR. WREG 1 1 N,Z

XOR #lit10,Wn Wd = lit10 .XOR. Wd 1 1 N,Z

XOR Wb,Ws,Wd Wd = Wb .XOR. Ws 1 1 N,Z

XOR Wb,#lit5,Wd Wd = Wb .XOR. lit5 1 1 N , Z

83 ZE ZE Ws,Wnd Wnd = Zero-extend Ws 1 1 C,Z,N

TABLE 18-2: INSTRUCTION SET OVERVIEW (CONTINUED)

Base

Instr

Assembly

Mnemonic Assembly Syntax Description # of

Words

# of

Cycle

Status Flags

Affected

dsPIC30F2011/2012/3012/3013

19.0 DEVELOPMENT SUPPORT

The PIC® microcontrollers and dsPIC® digital signal

controllers are supported with a full range of software

and hardware development tools:

• Integrated Development Environment

- MPLAB® IDE Software

• Compilers/Assemblers/Linkers

- MPLAB C Compiler for Vari ous Device

Families

- HI-TECH C for Various Device Families

- MPASMTM Assembler

-MPLINK

TM Object Linker/

MPLIBTM Object Librarian

- MPLAB Assembler/Linker/Librarian for

Various Device Families

• Simulators

- MPLAB SIM Software Simulator

• Emulators

- MPLAB REAL ICE™ In-Circuit Emulator

• In-Circuit Debuggers

- MPLAB ICD 3

- PIC kit™ 3 Debug Express

• Device Programmers

- PICkit™ 2 Programmer

- MPLAB PM3 Device Programmer

• Low-Cost Demonstra tion/Development Boards,

Evaluation Kits, and Starter Kits

19.1 MPLAB Integrated Development

Environment Software

The MPLAB IDE software brings an ease of software

development previously unseen in the 8/16/32-bit

microcontroller market. The MPLAB IDE is a Windows®

operating system-based application that contains:

• A single graphical interface to all debugging tools

- Simulator

- Programmer (sold separately)

- In-Circuit Emulator (sold separately)

- In-Circuit Debugger (sold separately)

• A full-featured editor with color-coded context

• A multiple project manager

• Customizable data windows with direct edit of

contents

• High-level source code debugging

• Mouse over variable inspection

• Drag and drop variables from source to watch

windows

• Extensive on-line help

• Integration of select third party tools, such as

IAR C Compilers

The MPLAB IDE allows you to:

• Edit your source files (either C or assembly)

• One-touch compile or assemble, and download to

emulator and simulator tools (automatically

updates all project information)

• Debug using:

- Source files (C or assembly)

- Mixed C and assembly

- Machine code

MPLAB IDE supports multiple debugging tools in a

single development paradigm, from the cost-effective

simulators, through low-cost in-circuit debuggers, to

full-featured emulators. This eliminates the learning

curve when upgrading to tools with increased flexibility

and power.

dsPIC30F2011/2012/3012/3013

19.2 MPLAB C Compilers for Various

Device Families

The MPLAB C Compiler code development systems

are complete ANSI C compilers for Microchip’s PIC18,

PIC24 and PIC32 families of microcontrollers and the

dsPIC30 and dsPIC33 families of digital signal control-

lers. These compilers provide powerful integration

capabilities, superior code optimization and ease of

use.

For easy source level debugging, the compilers provide

symbol information that is optimized to the MPLAB IDE

debugger.

19.3 HI-TECH C for Various Device

Families

The HI-TECH C Compiler code development systems

are complete ANSI C compilers for Microchip’s PIC

family of microcontrollers and the dsPIC family of digital

signal controllers. These compilers provide powerful

integration capabilities, omniscient code generation

and ease of us e.

For easy source level debugging, the compilers provide

symbol information that is optimized to the MPLAB IDE

debugger.

The compilers include a macro assembler, linker, pre-

processor , and one-step driver , and can run on multiple

platforms.

19.4 MPASM Assembler

The MPASM Assembler is a full-featured, universal

macro assembler for PIC10/12/16/18 MCUs.

The MPASM Assembler generates relocatable object

files for the MPLINK Object Linker , Intel® standard HEX

files, MAP files to detail memory usage and symbol

reference, absolute LST fi les that contain source lines

and generated machine code and COFF files for

debugging.

The MPASM Assembler features include:

• Integration into MPLAB IDE projects

• User-defined macros to streamline

assembly code

• Conditional assembly for multi-purpose

source files

• Directives that allow complete control over the

assembly process

19.5 MPLINK Object Linker/

MPLIB Object Librarian

The MPLINK Object Linker combines relocatable

objects created by the MPASM Assembler and the

MPLAB C18 C Compiler . It can link relocatable objects

from precompiled libraries, using directives from a

linker script.

The MPLIB Object Librarian manages the creation and

modification of libra ry files of preco mpiled cod e. When

a routine from a library is called from a source file, only

the modules that contain that routine will be linked in

with the application. This allows large libraries to be

used efficiently in many different applications.

The object linker/library features inclu de:

• Efficient linking of single libraries instead of many

smaller files

• Enhanced code maintainability by grou ping

related modules together

• Flexible creation of libra ries with easy module

listing, replacement, deletion and extraction

19.6 MPLAB Assembler, Linker and

Librarian for Various Device

Families

MPLAB Assembler produces relocatable machine

code from symbolic assembly language for PIC24,

PIC32 and dsPIC devices. MPLAB C Compiler uses

the assembler to produce its object file. The assembler

generates relocatable object files that can then be

archived or linked with other relocatable object files and

archives to create an executable file . Notable features

of the assembler include:

• Support for the entire device instruction set

• Support for fixed-point and floating-point data

• Command line interface

• Rich directive set

• Flexible macro lang uage

• MPLAB IDE compatibility

dsPIC30F2011/2012/3012/3013

19.7 MPLAB SIM Software Simulator

The MPLAB SIM Software Simulator allows code

development in a PC-hosted environment by simulat-

ing the PIC MCUs and d sPIC® DSCs on an instruction

level. On any given instruction, the data areas can be

examined or modified a nd stimuli can be applied from

a comprehensive stimulus controller. Registers can be

logged to files for further run-time analysis. The trace

buffer and logic analyzer display extend the power of

the simulator to record and track program execution,

actions on I/O, most peripherals and internal registers.

The MPLAB SIM Software Simulator fully supports

symbolic debugging using the MPLAB C Compilers,

and the MPASM and MPLAB Assemblers. The soft-

ware simulator offers the flexibility to develop and

debug code outside of the hardware laboratory envi-

ronment, making it an excellent, economical software

development tool.

19.8 MPLAB REAL ICE In-Circuit

Emulator System

MPLAB REAL ICE In-Circuit Emulator System is

Microchip’s next generation high-speed emulator for

Microchip Flash DSC and MCU devices. It debugs and

programs PIC® Flash MCUs and dsPIC® Flash DSCs

with the easy-to-use, powerful graphical user interface of

the MPLAB Integrated Development Environment (IDE),

included with each kit.

The emulator is connected to the design engineer ’s PC

using a high-speed USB 2.0 interface and is connected

to the target with either a connector compatible with in-

circuit debugger systems (RJ11) or with the new high-

speed, noise tolerant, Low-Voltage Differential Signal

(LVDS) interconnection (CAT5).

The emulator is field upgradable through future firmware

downloads in MPLAB IDE. In upcoming releases of

MPLAB IDE, new devices will be supported, and new

features will be added. MPLAB REAL ICE offers

significant advantages over competitive emulators

including low-cost, full-speed emulation, run-time

variable watches, trace analysis, complex breakpoints, a

ruggedized probe interface and long (up to three meters)

interconnection cables.

19.9 MPLAB ICD 3 In-Circuit Debugger

System

MPLAB ICD 3 In-Circuit Debugger System is Micro-

chip's most cost effective high-speed hardware

debugger/programmer for Microchi p Flash Digital Sig-

nal Controller (DSC) and microcontroller (MCU)

devices. It debugs and programs PIC® Flash microcon-

trollers and dsPIC® DSCs with the powerful, yet easy-

to-use graphical user interface of MPLAB Integrated

Development Environment (IDE).

The MPLAB ICD 3 In-Circuit Debugger probe is con-

nected to the design engineer's PC using a high-speed

USB 2.0 interface and is connected to the target with a

connector compatible with the MPLAB ICD 2 or MPLAB

REAL ICE systems (RJ-11). MPLAB ICD 3 supports all

MPLAB ICD 2 headers.

19.10 PICkit 3 In-Circuit Debugger/

Programmer and

PICkit 3 Debug Express

The MPLAB PICkit 3 allows debugging and program-

ming of PIC® and dsPIC® Flash microcontrollers at a

most affordable price point using the powerful graphical

user interface of the MPLAB Integrated Development

Environment (IDE). The MPLAB PICkit 3 is connected

to the design engineer's PC using a full speed USB

interface and can be connected to the target via an

Microchip debug (RJ-11) connector (compatible with

MPLAB ICD 3 and MPLAB REAL ICE). The connector

uses two device I/O pins and the reset line to imple-

ment in-circuit debugging and In-Circuit Serial Pro-

gramming™.

The PICkit 3 Debug Express include the PICkit 3, demo

board and microcontroller , hookup cables and CDROM

with user’s guide, lessons, tutorial, compiler and

MPLAB IDE software.

dsPIC30F2011/2012/3012/3013

19.11 PICkit 2 Development

Programmer/Debugger and

PICkit 2 Debug Express

The PICkit™ 2 Development Programmer/Debugger is

a low-cost development tool with an easy to use inter-

face for programming and debugging Microchip’s Flash

families of microcontrollers. The full featured

Windows® programming interface supports baseline

(PIC10F, PIC12F5xx, PIC16F5xx), midrange

(PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30,

dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit

microcontrollers, and many Microchip Serial EEPROM

products. With Microchip’s powerful MPLAB Integrated

Development Environment (IDE) the PICkit™ 2

enables in-circuit debugging on most PIC® microcon-

trollers. In-Circuit-Debugging runs, halts and single

steps the program while the PIC microcontroller is

embedded in the ap plication. When halted at a break-

point, the file registers can be examined and modified.

The PICkit 2 Debug Express include the PICkit 2, demo

board and microcontroller, hookup cables and CDROM

with user’s guide, lessons, tutorial, compiler and

MPLAB IDE software.

19.12 MPLAB PM3 Device Programmer

The MPLAB PM3 Device Programmer is a universal,

CE compliant device programmer with programmable

voltage verification at VDDMIN and VDDMAX for

maximum reliability. It features a large LCD display

(128 x 64) for menus and error messages and a modu-

lar, detachable socket assembly to support various

package types. The ICSP™ cable assembly is included

as a standard item. In Stand-Alone mode, the MPLAB

PM3 Device Programmer can read, verify and program

PIC devices without a PC connection. It can also set

code protection in this mode. The MPLAB PM3

connects to the host PC via an RS-232 or USB cable.

The MPLAB PM3 has high-speed communications and

optimized algorithms for quick programming of large

memory devices and incorporates an MMC card for file

storage and data applications.

19.13 Demonstration/Development

Boards, Evaluation Kits, and

Star ter Kits

A wide variety of demonstration, development and

evaluation boards for various PIC MCUs and dsPIC

DSCs allows quick application development on fully func-

tional systems. Most boards include prototyping areas for

adding custom circuitry and provide application firmware

and source code for examination and modification.

The boards support a variety of features, including LEDs,

temperature sensors, switches, speakers, RS-232

interfaces, LCD displa ys, potentiometers and additiona l

EEPROM memory.

The demonstration and development boards can be

used in teaching environments, for prototyping custom

circuits and for learning about various microcontroller

applications.

In addition to the PICDEM™ and d sPICDEM™ demon-

stration/develop ment board series of circuit s, Microchip

has a line o f evaluation kit s and demons tration softwa re

for analog filter design, KEELOQ® security ICs, CAN,

IrDA®, PowerSmart battery management, SEEVAL®

evaluation system, Sigma-Delta ADC, flow rate

sensing, plus many more.

Also available are starter kits that contain everything

needed to experience the specified device. This usually

includes a single application and debug capability, all

on one board.

Check the Microchip web page (www.microchip.com)

for the complete list of demonstration, development

and evaluation kits.

dsPIC30F2011/2012/3012/3013

20.0 ELECTRICAL CHARACTERISTICS

This section provides an overview of dsPIC30F electrical characteristics. Additional information will be provided in future

revisions of this document as it becomes available.

For detailed informatio n about the ds PIC30F archi tecture an d core, refer to the “dsPIC3 0F Family Reference Manual”

(DS70046).

Absolute maximum ratings for the d sPIC30F famil y are liste d be low. Exposure to these maximum rating condi tions for

extended periods may affect device reliability . Functional operation of the device at these or any other conditions above

the parameters indicated in the operation listings of this specification is not implied.

Absolute Maximum Ratings(†)

Ambient temperature under bias.............................................................................................................-40°C to +125°C

Storage temperature.............................................................................................................................. -65°C to +150°C

Vo ltage on any pin with respect to V SS (except VDD and MCLR) (Note 1).....................................-0.3V to (VDD + 0.3V)

Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +5.5V

Vo ltage on MCLR with respect to VSS................... .............. .............. .............. .. .............. .............. .............0V to +13.25V

Maximum current out of VSS pin..................... .............. .............. ......................... ......................... ............... .........300 mA

Maximum current into VDD pin (Note 2)..................... ... .............. .............. .............. ......................... .............. .......250 mA

Input clamp current, IIK (VI < 0 or VI > VDD)............... ... .............. ......................... .............. .............. .............. .......±20 mA

Output clamp current, IOK (VO < 0 or VO > VDD)...................... .............. .............. .............. .............. .............. .......±20 mA

Maximum output current sunk by any I/O pin............................................................................................ ... ...........25 mA

Maximum output current sourced by any I/O pin ......................................................................................... ...........25 mA

Maximum current sunk by all ports ................. ... ... ........................................................................... .............. .......200 mA

Maximum current sourced by all ports (Note 2)....................... .............. .............. ......................... ............... .........200 mA

Note 1: V olt age spikes below VSS at the MCLR/VPP pin, inducing currents greater than 80 mA, may cause latch-up.

Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR/VPP pin, rather

than pulling this pin directly to VSS.

2: Maximum allowable current is a function of device maximum power dissipation. See Table 20-2 for PDMAX.

†NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions above those

indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for

extended periods may affect device reliability.

Note: All peripheral electrical cha racteristics are specified. For exact peripherals available on specific

devices, please refer to the dsPIC30F2011/2012/3012/3013 Sensor Family table on page 4 of

this data sheet.

dsPIC30F2011/2012/3012/3013

20.1 DC Characteristics

TABLE 20-1: OPERATING MIPS VS. VOLTAGE

VDD Range Temp Range Max MIPS

dsPIC30FXXX-30I dsPIC30FXXX-20E

4.5-5.5V -40°C to 85°C 30 —

4.5-5.5V -40°C to 125°C — 20

3.0-3.6V -40°C to 85°C 20 —

3.0-3.6V -40°C to 125°C — 15

2.5-3.0V -40°C to 85°C 10 —

TABLE 20-2: THERMAL OPERATING CONDITIONS

Rating Symbol Min Typ Max Unit

dsPIC30F201x-30I

dsPIC30F301x-30I

Operating Junction Temperature Rang e TJ-40 — +125 °C

Operating Ambient Temperature Range TA-40 — +85 °C

dsPIC30F201x-20E

dsPIC30F301x-20E

Operating Junction Temperature Range TJ-40 — +150 °C

Operating Ambient Temperature Range TA-40 — +125 °C

Power Dissipation:

Internal chip power dissipation:

PDPINT + PI/OW

I/O Pin power dissipation:

Maximum Allowed Power Dissipation PDMAX (TJ - TA) / θJA W

PINT VDD IDD IOH

∑

–()×=

PI/OVDD VOH

–

{}

IOH

×()

∑VOL IOL

()

∑

TABLE 20-3: THERMAL PACKAGING CHARACTERISTICS

Characteristic Symbol Typ Max Unit Notes

Package Thermal Resistance, 18-pin PDIP (P) θJA 44 — °C/W 1

Package Thermal Resistance, 18-pin SOIC (SO) θJA 57 — °C/W 1

Package Thermal Resistance, 28-pin SPDIP (SP) θJA 42 — °C/W 1

Package Thermal Resistance, 28 -p i n (SOI C ) θJA 49 — °C/W 1

Package Thermal Resistance, 44-pin QFN θJA 28 — °C/W 1

Note 1: Junction to ambient thermal resistance, Theta-ja (θJA) numbers are achieved by package simulations.

dsPIC30F2011/2012/3012/3013

TABLE 20-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS

DC CHARACTERISTICS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Symbol Characteristic Min Typ(1) Max Units Conditions

Operating Voltage(2)

DC10 VDD Supply Voltage 2.5 — 5.5 V Industrial temperature

DC11 VDD Supply Voltage 3.0 — 5.5 V Extended temperat ure

DC12 VDR RAM Data Re te ntion Voltage(3) 1.75 — — V

DC16 VPOR VDD St art Voltage (to ensure

internal Power-on Reset signal) ——VSS V

DC17 SVDD VDD Rise Rate (to ensure

internal Power-on Reset signal) 0.05 — — V/ms 0-5V in 0.1 sec

0-3V in 60 ms

Note 1: “Typ” column data is at 5V, 25°C unle s s otherwise stated. Parameters are for design guidance only and

are not tested.

2: These parameters are characterized but not tested in manufacturing.

3: This is the limit to which VDD can be lowered without losing RAM data.

dsPIC30F2011/2012/3012/3013

TABLE 20-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD)

DC CHARACTERISTICS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Parameter

No. Typical(1) Max Units Conditions

Operating Current (IDD)(2)

DC31a 1.6 3.0 mA 25°C 3.3V 0.128 MIPS

LPRC (512 kHz)

DC31b 1.6 3.0 mA 85°C

DC31c 1.6 3.0 mA 125°C

DC31e 3.6 6.0 mA 25°C 5VDC31f 3.3 6.0 mA 85°C

DC31g 3.2 6.0 mA 125°C

DC30a 3.0 5.0 mA 25°C 3.3V (1.8 MIPS)

FRC (7.37 MHz)

DC30b 3.0 5.0 mA 85°C

DC30c 3.1 5.0 mA 125°C

DC30e 6.0 9.0 mA 25°C 5VDC30f 5.8 9.0 mA 85°C

DC30g 5.7 9.0 mA 125°C

DC23a 9.0 15.0 mA 25°C 3.3V

4 MIPS

DC23b 10.0 15.0 mA 85°C

DC23c 10.0 15.0 mA 125°C

DC23e 16.0 24.0 mA 25°C 5VDC23f 16.0 24.0 mA 85°C

DC23g 16.0 24.0 mA 125°C

DC24a 22.0 33.0 mA 25°C 3.3V

10 MIPS

DC24b 22.0 33.0 mA 85°C

DC24c 22.0 33.0 mA 125°C

DC24e 37.0 56.0 mA 25°C 5VDC24f 37.0 56.0 mA 85°C

DC24g 37.0 56.0 mA 125°C

DC27a 41.0 60.0 mA 25°C 3.3V

20 MIPS

DC27b 40.0 60.0 mA 85°C

DC27d 68.0 90.0 mA 25°C 5VDC27e 67.0 90.0 mA 85°C

DC27f 66.0 90.0 mA 125°C

DC29a 96.0 140.0 mA 25°C 5V 30 MIPS

DC29b 94.0 140.0 mA 85°C

Note 1: Data in “Typi cal” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only

and are not te ste d.

2: The supply current is mainl y a function of the operating voltage and frequency. Other factors such as I/O

pin loading and switching rate, oscillator type, internal code execution pattern and temperature also have

an impact on the current consumption. The test conditions for all IDD measurements are as follows: OSC1

driven with external square wave from rail to rail. All I/O pins are configured as Inputs and pulled to VDD.

MCLR = VDD, WDT, FSCM, LVD and BOR are disabled. CPU, SRAM, Program Memory and Data

Memory are operational. No peripheral modules are operating.

dsPIC30F2011/2012/3012/3013

TABLE 20-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE)

DC CHARACTERISTICS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Parameter

No. Typical(1) Max Units Conditions

Operating Current (IDD)(2)

DC51a 1.3 2.5 mA 25°C 3.3V 0.128 MIPS

LPRC (512 kHz)

DC51b 1.3 2.5 mA 85°C

DC51c 1.2 2.5 mA 125°C

DC51e 3.2 5.0 mA 25°C 5VDC51f 2.9 5.0 mA 85°C

DC51g 2.8 5.0 mA 125°C

DC50a 3.0 5.0 mA 25°C 3.3V (1.8 MIPS)

FRC (7.37 MHz)

DC50b 3.0 5.0 mA 85°C

DC50c 3.0 5.0 mA 125°C

DC50e 6.0 9.0 mA 25°C 5VDC50f 5.8 9.0 mA 85°C

DC50g 5.7 9.0 mA 125°C

DC43a 5.2 8.0 mA 25°C 3.3V

4 MIPS

DC43b 5.3 8.0 mA 85°C

DC43c 5.4 8.0 mA 125°C

DC43e 9.7 15.0 mA 25°C 5VDC43f 9.6 15.0 mA 85°C

DC43g 9.5 15.0 mA 125°C

DC44a 11.0 17.0 mA 25°C 3.3V

10 MIPS

DC44b 11.0 17.0 mA 85°C

DC44c 11.0 17.0 mA 125°C

DC44e 19.0 29.0 mA 25°C 5VDC44f 19.0 29.0 mA 85°C

DC44g 20.0 30.0 mA 125°C

DC47a 20.0 35.0 mA 25°C 3.3V

20 MIPS

DC47b 21.0 35.0 mA 85°C

DC47d 35.0 50.0 mA 25°C 5VDC47e 36.0 50.0 mA 85°C

DC47f 36.0 50.0 mA 125°C

DC49a 51.0 70.0 mA 25°C 5V 30 MIPS

DC49b 51.0 70.0 mA 85°C

Note 1: Data in “Typi cal” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only

and are not tested.

2: Base IIDLE current is measured with Core off, Clock on and all modules turned off.

dsPIC30F2011/2012/3012/3013

TABLE 20-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)

DC CHARACTERISTICS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Parameter

No. Typical(1) Max Units Conditions

Power-Down Current (IPD)(2)

DC60a 0.3 — μA 25°C 3.3V

Base Power-Down Current(3)

DC60b 1.3 30.0 μA 85°C

DC60c 16.0 60.0 μA125°C

DC60e 0.5 — μA 25°C 5VDC60f 3.7 45.0 μA 85°C

DC60g 25.0 90.0 μA125°C

DC61a 6.0 9.0 μA 25°C 3.3V

Watchdog Timer Current: ΔIWDT(3)

DC61b 6.0 9.0 μA 85°C

DC61c 6.0 9.0 μA125°C

DC61e 13.0 20.0 μA 25°C 5VDC61f 12.0 20.0 μA 85°C

DC61g 12.0 20.0 μA125°C

DC62a 4.0 10.0 μA 25°C 3.3V

Timer1 w/32 kHz Crystal: ΔITI32(3)

DC62b 5.0 10.0 μA 85°C

DC62c 4.0 10.0 μA125°C

DC62e 4.0 15.0 μA 25°C 5VDC62f 6.0 15.0 μA 85°C

DC62g 5.0 15.0 μA125°C

DC63a 33.0 53.0 μA 25°C 3.3V

BOR On: ΔIBOR(3)

DC63b 35.0 53.0 μA 85°C

DC63c 19.0 53.0 μA125°C

DC63e 38.0 62.0 μA 25°C 5VDC63f 41.0 62.0 μA 85°C

DC63g 41.0 62.0 μA125°C

DC66a 21.0 40.0 μA 25°C 3.3V

Low-Voltage Detect: ΔILVD(3)

DC66b 26.0 40.0 μA 85°C

DC66c 27.0 40.0 μA125°C

DC66e 25.0 44.0 μA 25°C 5VDC66f 27.0 44.0 μA 85°C

DC66g 29.0 44.0 μA125°C

Note 1: Data in the Typical column is at 5V, 25°C unless otherwise stated. Parameters are for design gu idance

only and are not tested.

2: Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as inputs and

pulled high. LVD, BOR, WDT, etc. are all switched off.

3: The Δ current is the additional current consumed when the module is enabled. Th is current should be

added to the base IPD current.

dsPIC30F2011/2012/3012/3013

TABLE 20-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS

DC CHARACTERISTICS

Stand a rd Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extende d

Param

No. Symbol Characteristic Min Typ(1) Max Units Conditions

VIL Input Low Voltage(2)

DI10 I/O pins:

with Schmitt Trigger buffer VSS —0.2VDD V

DI15 MCLR VSS —0.2VDD V

DI16 OSC1 (in XT, HS and LP modes) VSS —0.2VDD V

DI17 OSC1 (in RC mode)(3) VSS —0.3VDD V

DI18 SDA, SCL VSS —0.3VDD V SM bus disabled

DI19 SDA, SCL VSS — 0.8 V SM bus enabled

VIH Input High Vo ltage(2)

DI20 I/O pins:

with Schmitt Trigger buffer 0.8 VDD —VDD V

DI25 MCLR 0.8 VDD —VDD V

DI26 OSC1 (in XT, HS and LP modes) 0.7 VDD —VDD V

DI27 OSC1 (in RC mode)(3) 0.9 VDD —VDD V

DI28 SDA, SCL 0.7 VDD —VDD V SM bus disabled

DI29 SDA, SCL 2.1 — VDD V SM bus enabled

ICNPU CNXX Pull-up Current(2)

DI30 50 250 400 μAVDD = 5V, VPIN = VSS

IIL Input Leakage Current(2)(4)(5)

DI50 I/O ports — 0.01 ±1 μAVSS ≤ VPIN ≤ VDD,

Pin at high impedance

DI51 Analog inp ut pins — 0.50 — μAVSS ≤ VPIN ≤ VDD,

Pin at high impedance

DI55 MCLR —0.05±5μAVSS ≤ VPIN ≤ VDD

DI56 OSC1 — 0.05 ±5 μAVSS ≤ VPIN ≤ VDD, XT, HS

and LP Osc mode

Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and

are not tested.

2: These parameters are characterized but not tested in manufacturing.

3: In RC oscillator configuration, the OSC1/CLKl pin is a Schmitt Trigger input. It is not recommended that

the dsPIC30F device be driven with an external clock while in RC mode.

4: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified

levels represent normal operating conditions. Higher leakage current may be measured at different input

voltages.

5: Negative current is defined as current sourced by the pin.

dsPIC30F2011/2012/3012/3013

TABLE 20-9: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS

DC CHARACTERISTICS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Symbol Characteristic Min Typ(1) Max Units Conditions

VOL Output Low Voltage(2)

DO10 I/O ports — — 0.6 V IOL = 8.5 mA, VDD = 5V

— — 0.15 V IOL = 2.0 mA, VDD = 3V

DO16 OSC2/CLKO — — 0.6 V IOL = 1.6 mA, VDD = 5V

(RC or EC Osc mode) — — 0.72 V IOL = 2.0 mA, VDD = 3V

VOH Output High Volt a g e(2)

DO20 I/O ports VDD – 0.7 — — V IOH = -3.0 mA, VDD = 5V

VDD – 0.2 — — V IOH = -2.0 mA, VDD = 3V

DO26 OSC2/CLKO VDD – 0.7 — — V IOH = -1.3 mA, VDD = 5V

(RC or EC Osc mode) VDD – 0.1 — — V IOH = -2.0 mA, VDD = 3V

Capacitive Loading Specs

on Output Pins(2)

DO50 COSC2 OSC2/SOSC2 pin — — 15 pF In XTL, XT, HS and LP modes

when external clock is used to

drive OSC1.

DO56 CIO All I/O pins and OSC2 — — 50 pF RC or EC Osc mode

DO58 CBSCL, SDA — — 400 pF In I2C mode

Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and

are not tested.

2: These parameters are characterized but not tested in manufacturing.

dsPIC30F2011/2012/3012/3013

FIGURE 20-1: LOW-VOLTAGE DETECT CHARACTERISTICS

TABLE 20-10: ELECTRICAL CHARACTERISTICS: LVDL

DC CHARACTERISTICS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated )

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Symbol Characteristic(1) Min Typ Max Units Conditions

LV10 VPLVD L VDL V oltage on VDD transition

high-to-low LVDL = 0000(2) ———V

LVDL = 0001(2) ———V

LVDL = 0010(2) ———V

LVDL = 0011(2) ———V

LVDL = 0100 2.50 — 2.65 V

LVDL = 0101 2.70 — 2.86 V

LVDL = 0110 2.80 — 2.97 V

LVDL = 0111 3.00 — 3.18 V

LVDL = 1000 3.30 — 3.50 V

LVDL = 1001 3.50 — 3.71 V

LVDL = 1010 3.60 — 3.82 V

LVDL = 1011 3.80 — 4.03 V

LVDL = 1100 4.00 — 4.24 V

LVDL = 1101 4.20 — 4.45 V

LVDL = 1110 4.50 — 4.77 V

LV15 VLVDIN External LVD input pin

threshold voltage LVDL = 1111 ———V

Note 1: These parameters are characterized but not tested in manufacturing.

2: These values not in usable operating range.

LV10

LVDIF

VDD

(LVDIF set by hardware)

dsPIC30F2011/2012/3012/3013

FIGURE 20-2: BROWN-OUT RESET CHARACTERISTICS

TABLE 20-11: ELECTRICAL CHARACTERISTICS: BOR

DC CHARACTERISTICS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Symbol Characteristic Min Typ(1) Max Units Conditions

BO10 VBOR BOR Voltage(2) on

VDD transition high to

low

BORV = 11(3) — — — V Not in operating

range

BORV = 10 2.6 — 2.71 V

BORV = 01 4.1 — 4.4 V

BORV = 00 4.58 — 4.73 V

BO15 VBHYS —5—mV

Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and

are not tested.

2: These parameters are characterized but not tested in manufacturing.

3: 11 values not in usable operating range.

BO10

RESET (due to BOR)

VDD

(Device in Brown-out Reset)

(Device not in Brown-out Reset)

Power-Up Time-out

BO15

dsPIC30F2011/2012/3012/3013

TABLE 20-12: DC CHARACTERISTICS: PROGRAM AND EEPROM

DC CHARACTERISTICS

Standard Operatin g Conditions: 2.5V to 5.5V

(unless otherwise stated )

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Symbol Characteristic Min Typ(1) Max Units Conditions

Data EEPROM Memory(2)

D120 EDByte Endurance 100K 1M — E/W -40°C ≤ TA ≤ +85°C

D121 VDRW VDD for Read/Write V MIN — 5.5 V Using EECON to Read/Write

VMIN = Minimum operating

voltage

D122 TDEW Erase/Write Cycle Time 0.8 2 2.6 ms RTSP

D123 TRETD Characteristic Retention 40 100 — Year Provided no other specifications

are violated

D124 IDEW IDD During Programming — 10 30 mA Row Erase

Program Flash Memory(2)

D130 EPCell Endurance 10K 100K — E/W -40°C ≤ TA ≤ +85°C

D131 VPR VDD for Read VMIN —5.5VVMIN = Minimum operating

voltage

D132 VEB VDD for Bulk Erase 4.5 — 5.5 V

D133 VPEW VDD for Erase/Write 3.0 — 5.5 V

D134 TPEW Erase/Write Cycle Time 0.8 2 2.6 ms RTSP

D135 TRETD Characteristic Retention 40 100 — Year Provided no other specifications

are violated

D137 IPEW IDD During Programming — 10 30 mA Row Erase

D138 IEB IDD During Programming — 10 30 mA Bulk Erase

Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated.

2: These parameters are characterized but not tested in manufacturing.

dsPIC30F2011/2012/3012/3013

20.2 AC Characteristics and Timing Parameters

The information contained in this section defines dsPIC30F AC characteristics and timing parameters.

TABLE 20-13: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC

FIGURE 20-3: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS

FIGURE 20-4: EXTERNAL CLOCK TIMING

AC CHARACTERISTICS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherw ise state d)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Operating voltage VDD range as described in Section 20.1 “DC

Characteristics”.

VDD/2

VSS

Legend:

RL=464Ω

CL= 50 pF for all pins except OSC2

5 pF for OSC2 output

Load Condition 1 — for all pins except OSC2 Load Condition 2 — for OSC2

OSC1

CLKO

Q4 Q1 Q2 Q3 Q4 Q1

OS20

OS25

OS30 OS30

OS40 OS41

OS31 OS31

dsPIC30F2011/2012/3012/3013

TABLE 20-14: EXTERNAL CLOCK TIMING REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Symbol Characteristic Min Typ(1) Max Units Conditions

OS10 FOSC External CLKN Frequency(2)

(External clocks allowed only

in EC mode)

—

7.5

MHz

EC with 4x PLL

EC with 8x PLL

EC with 16x PLL

Oscillator Frequency(2) DC

0.4

—

7.37

512

7.5

22.5

—

MHz

kHz

MHz

kHz

XTL

XT with 4x PLL

XT with 8x PLL

XT with 16x PLL

HS/2 with 4x PLL

HS/2 with 8x PLL

HS/2 with 16x PLL

HS/3 with 4x PLL

HS/3 with 8x PLL

HS/3 with 16x PLL

FRC internal

FRC internal w/4x PLL

FRC internal w/8x PLL

FRC internal w/16x PLL

LPRC inte rn a l

OS20 TOSC TOSC = 1/FOSC — — — — See parameter OS10

for FOSC value

OS25 TCY Instruction Cycle Time(2)(3) 33 — DC ns See Table 20-17

OS30 TosL,

TosH External Clock(2) in (OSC1)

High or Low Time .45 x

TOSC ——nsEC

OS31 TosR,

TosF External Clock(2) in (OSC1)

Rise or Fall Time — — 20 ns EC

OS40 TckR CLKO Rise Time(2)(4) — — — ns See parameter DO31

OS41 TckF CLKO Fall Time(2)(4) — — — ns See parameter DO32

Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and

are not tested.

2: These parameters are characterized but not tested in manufacturing.

3: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values

are based on characterization data for that particular oscillator type under standard operating conditions

with the device executing code. Exc eeding these specified limits may result in an unstable oscillator

operation and/or higher than expected current consumption. All devices are tested to operate at “min.”

values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the

“Max.” cycle time limit is “DC” (no clock) for all devices.

4: Measurem ents are t ake n in EC or ERC mo des. Th e CLKO signal is measured on the OSC2 pin. CLKO is

low for the Q1-Q2 period (1/2 TCY) and high for the Q3-Q4 period (1/2 TCY).

dsPIC30F2011/2012/3012/3013

TABLE 20-15: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.5 TO 5.5 V)

AC CHARACTERISTICS

Stand a rd Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extende d

Param

No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions

OS50 FPLLI PLL Input Frequency Range(2) 4

5(3)

—

7.5(4)

8.33(3)

7.5(4)

MHz

EC with 4x PLL

EC with 8x PLL

EC with 16x PLL

XT with 4x PLL

XT with 8x PLL

XT with 16x PLL

HS/2 with 4x PLL

HS/2 with 8x PLL

HS/2 with 16x PLL

HS/3 with 4x PLL

HS/3 with 8x PLL

HS/3 with 16x PLL

OS51 FSYS On-Chip PLL Output(2) 1 6 — 120 MHz EC, XT, HS/2, HS/3

modes with PLL

OS52 TLOC PLL Start-up Time (Lock Ti me) — 20 50 μs

Note 1: These parameters are characterized but not tested in manufacturing.

2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and

are not tested.

3: Limited by oscillator frequency range.

4: Limited by device operating frequency range.

TABLE 20-16: PLL JITTER

AC CHARACTERISTICS

Stan da rd Ope r a tin g Conditions: 2.5V to 5. 5 V

(unless otherwise stated )

Operating temperature -40°C ≤ TA ≤ +85°C for Industri al

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Characteristic Min Typ(1) Max Units Conditions

OS61 x4 PLL — 0.251 0.413 % -40°C ≤ TA ≤ +85°C VDD = 3.0 to 3.6V

— 0.251 0.413 % -40°C ≤ TA ≤ +125°C VDD = 3.0 to 3.6V

— 0.256 0.47 % -40°C ≤ TA ≤ +85°C VDD = 4.5 to 5.5V

— 0.256 0.47 % -40°C ≤ TA ≤ +125°C VDD = 4.5 to 5.5V

x8 PLL — 0.355 0.584 % -40°C ≤ TA ≤ +85°C VDD = 3.0 to 3.6V

— 0.355 0.584 % -40°C ≤ TA ≤ +125°C VDD = 3.0 to 3.6V

— 0.362 0.664 % -40°C ≤ TA ≤ +85°C VDD = 4.5 to 5.5V

— 0.362 0.664 % -40°C ≤ TA ≤ +125°C VDD = 4.5 to 5.5V

x16 PLL — 0.67 0.92 % -40°C ≤ TA ≤ +85°C VDD = 3.0 to 3.6V

— 0.632 0.956 % -40°C ≤ TA ≤ +85°C VDD = 4.5 to 5.5V

— 0.632 0.956 % -40°C ≤ TA ≤ +125°C VDD = 4.5 to 5.5V

Note 1: These parameters are characterized but not tested in manufacturing.

dsPIC30F2011/2012/3012/3013

TABLE 20-17: INTERNAL CLOCK TIMING EXAMPLES

Clock

Oscillator

Mode

FOSC

(MHz)(1) TCY (μsec)(2) MIPS(3)

w/o PLL MIPS(3)

w PLL x4 MIPS(3)

w PLL x8 MIPS(3)

w PLL x16

EC 0.200 20.0 0.05 — — —

4 1.0 1.0 4.0 8.0 16.0

10 0.4 2.5 10.0 20.0 —

25 0.16 6.25 — — —

XT 4 1.0 1.0 4.0 8.0 16.0

10 0.4 2.5 10.0 20.0 —

Note 1: Assumption: Oscillator Postscaler is divide by 1.

2: Instruction Execution Cycle Time: TCY = 1/MIPS.

3: Instruction Execution Frequency: MIPS = (FOSC * PLLx)/4 [since there are 4 Q clocks per instruction

cycle].

TABLE 20-18: AC CHARACTERISTICS: INTERNAL FRC ACCURACY

AC CHARACTERISTICS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Characteristic Min Typ Max Units Conditions

Internal FRC Accurac y @ FRC Freq. = 7.37 MHz(1)

OS63 FRC — — ±2.00 % -40°C ≤ TA ≤ +85°C VDD = 3.0-5.5V

— — ±5.00 % -40°C ≤ TA ≤ +125°C VDD = 3.0-5.5V

Note 1: Frequency calibrated at 7.372 MHz ±2%, 25°C and 5V. TUN bits (OSCCON<3:0>) can be used to

compensate for temperature drift.

TABLE 20-19: AC CHARACTERISTICS: INTERNAL LPRC ACCURACY

AC CHARACTERISTICS

Standard Operatin g Conditions: 2.5V to 5.5V

(unless otherwise stated )

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Characteristic Min Typ Max Units Conditions

LPRC @ Freq. = 512 kHz(1)

OS65A -50 — +50 % VDD = 5.0V, ±10%

OS65B -60 — +60 % VDD = 3.3V, ±10%

OS65C -70 — +70 % VDD = 2.5V

Note 1: Change of LPRC frequency as VDD changes.

dsPIC30F2011/2012/3012/3013

FIGURE 20-5: CLKO AND I/O TIMING CHARACTERISTICS

TABLE 20-20: CLKO AND I/O TIMING REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherw ise state d)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Symbol Characteristic(1)(2)(3) Min Typ(4) Max Units Conditions

DO31 TIOR Port output rise time — 7 20 ns

DO32 TIOF Port output fall time — 7 20 ns

DI35 TINP INTx pin high or low time (output) 20 — — n s

DI40 TRBP CNx high or low time (input) 2 TCY ——ns

Note 1: These parameters are asynchronous events not related to any internal clock edges

2: Measurements are taken in RC mode and EC mode where CLKO output is 4 x TOSC.

3: These parameters are characterized but not tested in manufacturing.

4: Data in “Typ” column is at 5V, 25°C unless otherwise stated.

Note: Refer to Figure 20-3 for load conditions.

I/O Pin

(Input)

I/O Pin

(Output)

DI35

Old Value New Value

DI40

DO31

DO32

dsPIC30F2011/2012/3012/3013

FIGURE 20-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP

TIMER TIMING CHARACTERISTICS

TABLE 20-21: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER

AND BROWN-OUT RESET TIMING REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions

SY10 TmcL MCLR Pulse Wid t h (l ow ) 2 — — μs -40°C to +85°C

SY11 TPWRT Power-up Timer Period 2

128

ms -40°C to +85°C, VDD =

User progra mma b le

SY12 TPOR Power On Reset Delay 3 10 30 μs -40°C to +85°C

SY13 TIOZ I/O high impedance from MCLR

Low or Watchdog Timer Reset —0.81.0μs

SY20 TWDT1

TWDT2

TWDT3

Watchdog Timer Time-out Period

(No Prescaler) 1.1

1.2

1.3

2.0

6.6

5.0

4.0

VDD = 2.5V

VDD = 3.3V, ±10%

VDD = 5V, ±10%

SY25 TBOR Brown-out Reset Pulse Width(3) 100 — — μsVDD ≤ VBOR (D034)

SY30 TOST Oscillation Start-up Timer Period — 1024 TOSC ——TOSC = OSC1 period

SY35 TFSCM Fail-Safe Clock Monitor Delay — 500 900 μs -40°C to +85°C

Note 1: These parameters are characterized but not tested in manufacturing.

2: Data in “Typ” column is at 5V, 25°C unless otherwise stated.

3: Refer to Figure 20-2 and Table 20-11 for BO R.

VDD

MCLR

Internal

POR

PWRT

Time-out

OSC

Time-out

Internal

RESET

Watchdog

Timer

RESET

SY11

SY10

SY20

SY13

I/O Pins

SY13

Note: Refer to Figure 20-3 for load conditions.

FSCM

Delay

SY35

SY30

SY12

dsPIC30F2011/2012/3012/3013

FIGURE 20-7: BAND GAP START-UP TIME CHARACTERISTICS

TABLE 20-22: BAND GAP START-UP TIME REQUIREMENTS

AC CHARACTERISTICS

Stand ard Operating Cond ition s: 2.5 V to 5.5V

(unless otherwise st ated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions

SY40 TBGAP Ba nd Gap Start-up Time — 40 65 µs Defined as the time between the

instant that the band gap is enabled

and the moment that the band gap

reference voltage is stable.

RCON<13> bit

Note 1: These parameters are characterized but not tested in manufacturing.

2: Data in “Typ” column is at 5V, 25°C unless otherwise stated.

VBGAP

Enable Band Gap

Band Gap

(see Note)

Stable

Note: Set LVDEN bit (RCON<12>) or FBORPOR<7>set.

SY40

dsPIC30F2011/2012/3012/3013

FIGURE 20-8: TYPE A, B AND C TIMER EXTERNAL CLOCK TIMING CHARACTERISTICS

TABLE 20-23: TYPE A TIMER (TIMER1) EXTERNAL CLOCK TIMING REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Symbol Characteristic Min Typ Max Units Conditions

TA10 TTXH TxCK High Time Synchronous,

no prescaler 0.5 TCY + 20 — — ns Must also meet

parameter TA15

Synchronous,

with prescaler 10 — — ns

Asynchronous 10 — — ns

TA11 TTXL TxCK Low Time Synchronous,

no prescaler 0.5 TCY + 20 — — ns Must also meet

parameter TA15

Synchronous,

with prescaler 10 — — ns

Asynchronous 10 — — ns

TA15 TTXP TxCK Input Period Synchronous,

no prescaler TCY + 10 — — ns

Synchronous,

with prescaler Greater of:

20 ns or

(TCY + 40)/N

— — — N = prescale

value

(1, 8, 64, 256)

Asynchronous 20 — — ns

OS60 Ft 1 SOSC1/T1CK oscil l a to r in pu t

frequency range (oscillator enabled

by setting bit TCS (T1CON, bit 1))

DC — 50 kHz

TA20 TCKEXTMRL Delay from External TxCK Clock

Edge to Timer Increment 0.5 TCY —1.5 TCY —

Note: Timer1 is a Type A.

Note: Refer to Figure 20-3 for load conditions.

Tx11

Tx15

Tx10

Tx20

TMRX OS60

TxCK

dsPIC30F2011/2012/3012/3013

T ABLE 20-24: TYPE B TIMER (TIMER2 AND TIMER4) EXTERNAL CLOCK TIMING REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Symbol Characteristic Min Typ Max Units Conditions

TB10 TtxH TxCK High Time Synchronous,

no prescaler 0.5 TCY + 20 — — ns Must also meet

parameter TB15

Synchronous,

with prescaler 10 — — ns

TB11 TtxL TxCK Low Time Synchronous,

no prescaler 0.5 TCY + 20 — — ns Must also meet

parameter TB15

Synchronous,

with prescaler 10 — — ns

TB15 TtxP TxCK Input Period Synchronous,

no prescaler TCY + 10 — — ns N = prescale

value

(1, 8, 64, 256)

Synchronous,

with prescaler Greater of:

20 ns or

(TCY + 40)/N

TB20 TCKEXTMRL Delay from External TxCK Clock

Edge to Timer Increment 0.5 TCY — 1.5 TCY —

Note: Timer2 and Timer4 are Ty pe B.

T ABLE 20-25: TYPE C TIMER (TIMER3 AND TIMER5) EXTERNAL CLOCK TIMING REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Symbol Characteristic Min Typ Max Units Conditions

TC10 TtxH TxCK High Time Synchronous 0.5 TCY + 20 — — ns Must also meet

parameter TC15

TC11 TtxL TxCK Low Time Synchronous 0.5 TCY + 20 — — ns Must also meet

parameter TC15

TC15 TtxP TxCK Input Period Synchronous,

no prescaler TCY + 10 — — ns N = prescale

value

(1, 8, 64, 256)

Synchronous,

with prescaler Greater of:

20 ns or

(TCY + 40)/N

TC20 TCKEXTMRL Delay from External TxCK Clock

Edge to Timer Increment 0.5 TCY —1.5

TCY —

Note: Timer3 and Timer5 are Type C.

dsPIC30F2011/2012/3012/3013

FIGURE 20-9: INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS

TABLE 20-26: INPUT CAPTURE TIMING REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Symbol Characteristic(1) Min Max Units Conditions

IC10 TccL ICx Input Low Time No Prescaler 0.5 TCY + 20 — ns

With Prescaler 10 — ns

IC11 TccH ICx Input High Time No Prescaler 0.5 TCY + 20 — ns

With Prescaler 10 — ns

IC15 TccP ICx Input Period (2 TCY + 40)/N — ns N = prescale

value (1, 4, 16)

Note 1: These parameters are characterized but not tested in manufacturing.

ICX

IC10 IC11

IC15

Note: Refer to Figure 20-3 for load conditions.

dsPIC30F2011/2012/3012/3013

FIGURE 20-10: OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS

TABLE 20-27: OUTPUT COMPARE MODULE TIMING REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions

OC10 TccF OCx Output Fall Time — — — ns See Parameter DO32

OC11 TccR OCx Output Rise Time — — — ns See Parameter DO31

Note 1: These parameters are characterized but not tested in manufacturing.

2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and

are not tested.

OCx

OC11 OC10

(Output Compare

Note: Refer to Figure 20-3 for load conditions.

or PWM Mode)

dsPIC30F2011/2012/3012/3013

FIGURE 20-11: OC/PWM MODULE TIMING CHARACTERISTICS

TABLE 20-28: SIMPLE OC/PWM MODE TIMING REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions

OC15 TFD Fault Input to PWM I/O

Change ——50ns

OC20 TFLT Fault Input Pulse Width 50 — — ns

Note 1: These parameters are characterized but not tested in manufacturing.

2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and

are not tested.

OCFA/OCFB

OCx

OC20

OC15

dsPIC30F2011/2012/3012/3013

FIGURE 20-12: SPI MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS

TABLE 20-29: SPI MASTER MODE (CKE = 0) TIMING REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions

SP10 TscL SCKX Output Low Time(3) TCY/2 — — ns —

SP11 TscH SCKX Output High Time(3) TCY/2 — — ns —

SP20 TscF SCKX Output Fall Time(4 — — — ns See parameter

DO32

SP21 TscR SCKX Output Rise Time(4) — — — ns See parameter

DO31

SP30 TdoF SDOX Data Output Fall Time(4) — — — ns See parameter

DO32

SP31 TdoR SDOX Data Output Rise T ime(4) — — — ns See parameter

DO31

SP35 TscH2doV,

TscL2doV SDOX Data Output Valid after

SCKX Edge — — 30 ns —

SP40 TdiV2scH,

TdiV2scL Setup Time of SDIX Data Input

to SCKX Edge 20 — — ns —

SP41 TscH2diL,

TscL2diL Hold Time of SDIX Data Input

to SCKX Edge 20 — — ns —

Note 1: These parameters are characterized but not tested in manufacturing.

2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and

are not tested.

3: The minimum clock period for SCK is 100 ns. Therefore, the clock generated in Master mode must not

violate this specification.

4: Assumes 50 pF load on all SPI pins.

SCKx

(CKP = 0)

SCKx

(CKP = 1)

SDOx

SDIx

SP11 SP10

SP40 SP41

SP21

SP20

SP35

SP20

SP21

MSb LSb

BIT 14 - - - - - -1

MSb IN LSb IN

BIT 14 - - - -1

SP30

SP31

Note: Refer to Figure 20-3 for load conditions.

dsPIC30F2011/2012/3012/3013

FIGURE 20-13: SPI MODULE MASTER MODE (CKE =1) TIMING CHARACTERISTICS

TABLE 20-30: SPI MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated )

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions

SP10 TscL SCKX output low time(3) TCY/2 — — ns —

SP11 TscH SCKX output high time(3) TCY/2 — — ns —

SP20 TscF SCKX output fall time(4) — — — ns See parameter

DO32

SP21 TscR SCKX output rise time(4) — — — ns See parameter

DO31

SP30 TdoF SDOX data output fall time(4) — — — ns See parameter

DO32

SP31 TdoR SDOX data output rise ti me (4) — — — ns See parameter

DO31

SP35 TscH2doV,

TscL2doV SDOX data output valid after

SCKX edge ——30ns —

SP36 TdoV2sc,

TdoV2scL SDOX data output setup to

first SCKX edge 30 — — ns —

SP40 TdiV2scH,

TdiV2scL Setup time of SDIX data input

to SCKX edge 20 — — ns —

SP41 TscH2diL,

TscL2diL Hold time of SDIX data input

to SCKX edge 20 — — ns —

Note 1: These parameters are characterized but not tested in manufacturing.

2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and

are not tested.

3: The minimum clock period for SCK is 100 ns. Therefore, the clock generated in master mode must not

violate this specification.

4: Assumes 50 pF load on all SPI pins.

SCKX

(CKP = 0)

SCKX

(CKP = 1)

SDOX

SDIX

SP36

SP30,SP31

SP35

MSb

MSb IN

BIT 14 - - - - - -1

LSb IN

BIT 14 - - - -1

LSb

Note: Refer to Figure 20-3 for load conditions.

SP11 SP10 SP20

SP21

SP20

SP40

SP41

dsPIC30F2011/2012/3012/3013

FIGURE 20-14: SPI MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS

TABLE 20-31: SPI MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

Operating temperature -40°C

≤

+85°C for Industrial

-40

≤

+125°C for Extended

Param

No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions

SP70 TscL SCKX Input Low Time 30 — — ns —

SP71 TscH SCKX Input High Time 30 — — ns —

SP72 TscF SCKX Input Fall T ime(3) —1025ns —

SP73 TscR SCKX Input Rise Time(3) —1025ns —

SP30 TdoF SDOX Data Output Fall Time(3) — — — ns See DO32

SP31 TdoR SDOX Data Output Rise Time(3) — — — ns See DO31

SP35 TscH2doV,

TscL2doV SDOX Data Output Valid after

SCKX Edge ——30ns —

SP40 TdiV2scH,

TdiV2scL Setup Time of SDIX Data Input

to SCKX Edge 20 — — ns —

SP41 TscH2diL,

TscL2diL Hold Time of SDIX Data Input

to SCKX Edge 20 — — ns —

SP50 TssL2scH,

TssL2scL SSX↓ to SCKX↑ or SCKX↓ Input 120 — — ns —

SP51 TssH2doZ SSX↑ to SDOX Output

high impedance(3) 10 — 50 ns —

SP52 TscH2ssH

TscL2ssH SSX after SCK Edge 1.5 TCY

+40 ——ns —

Note 1: These parameters are characterized but not tested in manufacturing.

2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and

are not tested.

3: Assumes 50 pF load on all SPI pins.

SCK

(CKP =

)

SCK

(CKP =

)

SDO

SDI

SP50

SP40 SP41

SP30,SP31 SP51

SP35

SDI

MSb LSb

BIT 14 - - - - - -1

MSb IN BIT 14 - - - -1 LSb IN

SP52

SP73

SP72

SP73

SP71 SP70

Note: Refer to Figure 20-3 for load conditions.

dsPIC30F2011/2012/3012/3013

FIGURE 20-15: SPI MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS

SSX

SCKX

(CKP = 0)

SCKX

(CKP = 1)

SDOX

SDI

SP50

SP60

SDIX

SP30,SP31

MSb BIT 14 - - - - - -1 LSb

SP51

MSb IN BIT 14 - - - -1 LSb IN

SP35

SP52

SP73

SP72

SP73

SP71 SP70

SP40 SP41

Note: Refer to Figure 20-3 for load conditions.

dsPIC30F2011/2012/3012/3013

TABLE 20-32: SPI MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions

SP70 TscL SCKX Input Low Time 30 — — ns —

SP71 TscH SCKX Input High Time 30 — — ns —

SP72 TscF SCKX Input Fall Time(3) —1025ns —

SP73 TscR SCKX Input Rise Time(3) —1025ns —

SP30 TdoF SDOX Data Output Fall T i me (3) — — — ns See parameter

DO32

SP31 TdoR SDOX Data Output Rise Time(3) — — — ns See parameter

DO31

SP35 TscH2doV,

TscL2doV SDOX Data Output Valid after

SCKX Edge — — 30 ns —

SP40 TdiV2scH,

TdiV2scL Setup Time of SDIX Data Input

to SCKX Edge 20 — — ns —

SP41 TscH2diL,

TscL2diL Hold Time of SDIX Data Input

to SCKX Edge 20 — — ns —

SP50 TssL2scH,

TssL2scL SSX↓ to SCKX↓ or SCKX↑ input 120 — — ns —

SP51 TssH2doZ SS↑ to SDOX Output

high impedance(4) 10 — 50 ns —

SP52 TscH2ssH

TscL2ssH SSX↑ after SCKX Edge 1.5 TCY + 40 — — ns —

SP60 TssL2doV SDOX Data Output Valid after

SCKX Edge — — 50 ns —

Note 1: These parameters are characterized but not tested in manufacturing.

2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and

are not tested.

3: The minimum clock period for SCK is 100 ns. Therefore, the clock generated in Master mode must not

violate this specification.

4: Assumes 50 pF load on all SPI pins.

dsPIC30F2011/2012/3012/3013

FIGURE 20-16: I2C™ BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE)

FIGURE 20-17: I2C™ BUS DATA TIMING CHARACTERISTICS (MASTER MODE)

IM31 IM34

SCL

SDA

Start

Condition Stop

Condition

IM30 IM33

Note: Refer to Figure 20-3 for load conditions.

IM11 IM10 IM33

IM11 IM10

IM20

IM26 IM25

IM40 IM40 IM45

IM21

SCL

SDA

Out

Note: Refer to Figure 20-3 for load conditions.

dsPIC30F2011/2012/3012/3013

TABLE 20-33: I2C™ BUS DATA TIMING REQUIREMENTS (MASTER MODE)

AC CHARACTERISTICS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated )

Operatin g te mperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Symbol Characteristic Min(1) Max Units Conditions

IM10 TLO:SCL Clock Low Time 100 kHz mode TCY/2 (BRG + 1) — μs

400 kHz mode TCY/2 (BRG + 1) — μs

1 MHz mode(2) TCY/2 (BRG + 1) — μs

IM11 THI:SCL Clock High Time 100 kHz mode T CY/2 (BRG + 1) — μs

400 kHz mode TCY/2 (BRG + 1) — μs

1 MHz mode(2) TCY/2 (BRG + 1) — μs

IM20 TF:SCL SDA and SCL

Fall Time 100 kHz mode — 300 ns CB is specifie d to be

from 10 to 400 pF

400 kHz mode 20 + 0.1 CB300 ns

1 MHz mode(2) — 100 ns

IM21 TR:SCL SDA and SCL

Rise Time 100 kHz mode — 1000 ns CB is specified to be

from 10 to 400 pF

400 kHz mode 20 + 0.1 CB300 ns

1 MHz mode(2) — 300 ns

IM25 TSU:DAT Data Input

Setup Time 1 00 kHz mode 250 — ns

400 kHz mode 100 — ns

1 MHz mode(2) — — ns

IM26 THD:DAT Data Input

Hold Time 100 kHz mode 0 — ns

400 kHz mode 0 0.9 μs

1 MHz mode(2) — — ns

IM30 TSU:STA Start Condition

Setup Time 1 00 kHz mode TCY/2 (BRG + 1) — μs Only relevant for

Repeated Start

condition

400 kHz mode TCY/2 (BRG + 1) — μs

1 MHz mode(2) TCY/2 (BRG + 1) — μs

IM31 THD:STA Start Condition

Hold Time 100 kHz mode TCY/2 (BRG + 1) — μs After this period the

first clock pulse is

generated

400 kHz mode TCY/2 (BRG + 1) — μs

1 MHz mode(2) TCY/2 (BRG + 1) — μs

IM33 TSU:STO Stop Condition

Setup Time 1 00 kHz mode TCY/2 (BRG + 1) — μs

400 kHz mode TCY/2 (BRG + 1) — μs

1 MHz mode(2) TCY/2 (BRG + 1) — μs

IM34 THD:STO Stop Condition 100 kHz mode TCY/2 (BRG + 1) — ns

Hold Time 400 kHz mode TCY/2 (BRG + 1) — ns

1 MHz mode(2) TCY/2 (BRG + 1) — ns

IM40 TAA:SCL Output Valid

From Clock 100 kHz mode — 3500 ns

400 kHz mode — 1000 ns

1 MHz mode(2) ——ns

IM45 TBF:SDA Bus Free Time 100 kHz mode 4.7 — μs Time the bus must be

free before a new

transmission can start

400 kHz mode 1.3 — μs

1 MHz mode(2) ——μs

IM50 CBBus Capacitive Loading — 400 pF

Note 1: BRG is the value of the I2C Baud Rate Generator . Refer to Section 21. “Inter-Integrated Circuit™ (I2C)”

(DS70068) in the dsPIC30F Family Reference Manua l (DS70046).

2: Maximum pin capacitance = 10 pF for all I2C™ pins (for 1 MHz mode only).

dsPIC30F2011/2012/3012/3013

FIGURE 20-18: I2C™ BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE)

FIGURE 20-19: I2C™ BUS DATA TIMING CHARACTERISTICS (SLAVE MODE)

TABLE 20-34: I2C™ BUS DATA TIMING REQUIREMENTS (SLAVE MODE)

AC CHARACTERISTICS

Standard Operating Conditions: 2.5V to 5.5 V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Symbol Characteristic Min Max Units Conditions

IS10 TLO:SCL Clock Low T ime 100 kHz mode 4.7 — μs Device must ope rate at a

minimum of 1.5 MHz

400 kHz mode 1.3 — μs Device must operate at a

minimum of 10 MHz.

1 MHz mode(1) 0.5 — μs

IS11 THI:SCL Clo ck High Time 100 kHz mode 4.0 — μs Device must operate at a

minimum of 1.5 MHz

400 kHz mode 0.6 — μs Device must operate at a

minimum of 10 MHz

1 MHz mode(1) 0.5 — μs

IS20 TF:SCL SDA and SCL

Fall Time 100 kHz mode — 300 ns CB is specified to be from

10 to 400 pF

400 kHz mode 20 + 0.1 CB300 ns

1 MHz mode(1) —100ns

IS21 TR:SCL SDA and SCL

Rise T i me 100 kHz mode — 1000 ns CB is specified to be from

10 to 400 pF

400 kHz mode 20 + 0.1 CB300 ns

1 MHz mode(1) —300ns

Note 1: Maximum pin capacitance = 10 pF for all I2C™ pins (for 1 MHz mode only).

IS31 IS34

SCL

SDA

Start

Condition Stop

Condition

IS30 IS33

IS30 IS31 IS33

IS11

IS10

IS20

IS26 IS25

IS40 IS40 IS45

IS21

SCL

SDA

Out

dsPIC30F2011/2012/3012/3013

IS25 TSU:DAT Data Input

Setup Time 100 kHz mode 250 — ns

400 kHz mode 100 — ns

1 MHz mode(1) 100 — ns

IS26 THD:DAT Data Input

Hold Time 100 kHz mode 0 — ns

400 kHz mode 0 0.9 μs

1 MHz mode(1) 00.3μs

IS30 TSU:STA Start Condition

Setup Time 100 kHz mode 4.7 — μs Only relevant for Repeated

Start condition

400 kHz mode 0.6 — μs

1 MHz mode(1) 0.25 — μs

IS31 THD:STA Start Condition

Hold Time 100 kHz mode 4.0 — μs After this period the first

clock pulse is generated

400 kHz mode 0.6 — μs

1 MHz mode(1) 0.25 — μs

IS33 TSU:STO Stop Condition

Setup Time 100 kHz mode 4.7 — μs

400 kHz mode 0.6 — μs

1 MHz mode(1) 0.6 — μs

IS34 THD:STO Stop Condition 100 kHz mode 4000 — ns

Hold Time 400 kHz mode 600 — ns

1 MHz mode(1) 250 ns

IS40 TAA:SCL Output Valid

From Clock 100 kHz mode 0 3500 ns

400 kHz mode 0 1000 ns

1 MHz mode(1) 0350ns

IS45 TBF:SDA Bus Free Time 100 kHz mode 4.7 — μs Time the bus must be free

before a new transmission

can start

400 kHz mode 1.3 — μs

1 MHz mode(1) 0.5 — μs

IS50 CBBus Capacitive

Loading — 400 pF

TABLE 20-34: I2C™ BUS DATA TIMING REQUIREMENTS (SLAVE MODE) (CONTINUED)

AC CHARACTERISTICS

Standard Operating Conditions: 2.5V to 5.5 V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extende d

Param

No. Symbol Characteristic Min Max Units Conditions

Note 1: Maximum pin capacitance = 10 pF for all I2C™ pins (for 1 MHz mode only).

dsPIC30F2011/2012/3012/3013

FIGURE 20-20: CAN MODULE I/O TIMING CHARACTERISTICS

TABLE 20-35: CAN MODULE I/O TIMING REQUIREMENTS

AC CHARACTERISTICS

Stand a rd Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extende d

Param

No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions

CA10 TioF Port Output Fall Time — 10 25 ns

CA11 TioR Po rt Output Rise Time — 10 25 ns

CA20 Tcwf Pulse Width to Trigger

CAN Wa ke-up Filt er 500 — — ns

Note 1: These parameters are characterized but not tested in manufacturing.

2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and

are not tested.

CXTX Pin

(output)

CA10 CA11

Old Value New Value

CA20

CXRX Pin

(input)

dsPIC30F2011/2012/3012/3013

TABLE 20-36: 12-BIT ADC MODULE SPECIFICATIONS

AC CHARACTERISTICS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Symbol Characteristic Min. Typ Max. Units Conditions

Device Supply

AD01 AVDD Module VDD Supply Greater of

VDD - 0.3

or 2.7

— Lesser of

VDD + 0.3

or 5.5

AD02 AVSS Module VSS Supply VSS - 0.3 — VSS + 0.3 V

Reference Inputs

AD05 VREFH Reference Voltage High AV SS + 2.7 — AVDD V

AD06 VREFL Reference Voltage Low AV SS —AVDD - 2.7 V

AD07 VREF Absolute Reference

Voltage AVSS - 0.3 — AVDD + 0.3 V

AD08 IREF Current Drain — 200

.001 300

2μA

μAA/D operating

A/D off

Analog Input

AD10 VINH-VINL Full-Scale Input Span VREFL —VREFH VSee Note 1

AD11 VIN Absolute Input Voltage AVSS - 0.3 — AVDD + 0.3 V —

AD12 — Leakage Current — ±0.001 ±0.610 μAV

INL = AVSS = VREFL =

0V, AVDD = VREFH = 5V

Source Impedance =

2.5 kΩ

AD13 — Leakage Current — ±0.001 ±0.610 μAVINL = AVSS = VREFL =

0V, AVDD = VREFH = 3V

Source Impedance =

2.5 kΩ

AD15 RSS Switch Resistance — 3.2K — Ω

AD16 CSAMPLE Sample Capacitor — 18 pF

AD17 RIN Recommended Impedance

of Analog Voltage Source — — 2.5K Ω

DC Accuracy(2)

AD20 Nr Resolution 1 2 data bits bits

AD21 INL Integral Nonlinearity — — <±1 LSb VINL = AVSS = VREFL =

0V, AVDD = VREFH = 5V

AD21A INL Integral Nonlinearity — — <±1 LSb VINL = AVSS = VREFL =

0V, AVDD = VREFH = 3V

AD22 DNL Differential Nonlinearity — — <±1 LSb VINL = AVSS = VREFL =

0V, AVDD = VREFH = 5V

AD22A DNL Differential Nonlinearity — — <±1 LSb VINL = AVSS = VREFL =

0V, AVDD = VREFH = 3V

AD23 GERR Gain Error +1.25 +1.5 +3 LSb VINL = AVSS = VREFL =

0V, AVDD = VREFH = 5V

AD23A GERR Gain Error +1.25 +1.5 +3 LSb VINL = AVSS = VREFL =

0V, AVDD = VREFH = 3V

Note 1: The A/D conversion result never decreases with an increase in the input voltage, and has no missing

codes.

2: Measuremen ts ta ke n w ith external VREF+ and VREF- used as the ADC voltage references.

dsPIC30F2011/2012/3012/3013

AD24 EOFF Offset Error -2 -1.5 -1.25 LSb VINL = AVSS = VREFL =

0V, AVDD = VREFH = 5V

AD24A EOFF Offset Error -2 -1.5 -1.25 LSb VINL = AVSS = VREFL =

0V, AVDD = VREFH = 3V

AD25 — Monotonicity(1) — — — — Guaranteed

Dynamic Performance

AD30 THD Total Harmonic Distortion — -71 — dB

AD31 SINAD Signal to Noise and

Distortion —68—dB

AD32 SFDR Spurious Free Dynamic

Range —83—dB

AD33 FNYQ Input Signal Bandwidth — — 100 kHz

AD34 ENOB Effective Number of Bits 10.95 11.1 — bits

TABLE 20-36: 12-BIT ADC MODULE SPECIFICATIONS (CONTINUED)

AC CHARACTERISTICS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Symbol Characteristic Min. Typ Max. Units Conditions

Note 1: The A/D conversion result never decreases with an increase in the input voltage, and has no missing

codes.

2: Measuremen ts ta ke n w ith external VREF+ and VREF- used as the ADC voltage references.

dsPIC30F2011/2012/3012/3013

FIGURE 20-21: 12-BIT A/D CONVERSION TIMING CHARACTERISTICS

(ASAM = 0, SSRC = 000)

AD55

TSAMP

Clear SAMPSet SAMP

AD61

ADCLK

Instruction

SAMP

ch0_dischrg

ch0_samp

AD60

DONE

ADIF

ADRES(0)

1 2 3 4 5 6 87

1- Software sets ADCON. SAMP to start sampling.

2- Sampling starts after discharge period.

3- Software clears ADCON. SAMP to Start conversion.

4- Sampling ends, conversion sequence starts.

5- Convert bit 11.

9- One TAD for end of conversion.

AD50

eoc

6- Convert bit 10.

7- Convert bit 1.

8- Convert bit 0.

Execution

TSAMP is described in Section 18. “12-bit A/D Converter” in the dsPIC30F Family Reference Manual (DS70046).

dsPIC30F2011/2012/3012/3013

TABLE 20-37: 12-BIT A/D CONVERSION TIMING REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Conditions: 2.7V to 5.5V

(unless otherwise stated)

Operating temperature-40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Symbol Characteristic Min. Typ Max. Units Conditions

Clock Parameters

AD50 TAD A/D Clock Period 33 4 — — ns VDD = 3-5.5V (Note 1)

AD51 tRC A/D Internal RC Oscillator Period 1.2 1.5 1.8 μs

Conversion Rate

AD55 tCONV Conversion Time — 14 TAD ns

AD56a FCNV Throughput Rate — 200 — ksps VDD = VREF = 5V,

Industrial temperature

AD56b FCNV Throughput Rate — 100 — ksps VDD = VREF = 5V,

Extended temperature

AD57 TSAMP Sampling Time 1 TAD —— nsVDD = 3-5.5V source

resistance

RS = 0-2.5 kΩ

Timing Parameters

AD60 tPCS Conversion Start from Sample

Trigger —1 TAD —ns

AD61 tPSS Sample Start from Setting

Sample (SAMP) Bit 0.5 TAD —1.5

TAD ns

AD62 tCSS Conversion Completion to

Sample Start (ASAM = 1)— 0.5 TAD —ns

AD63 tDPU(2) Time to Stabilize Analog Stage

from A/D Off to A/D On ——20μs

Note 1: Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity

performance, especially at elevated temperatures.

2: tDPU is the time required for the ADC module to stabilize when it is turned on (ADCON1<ADON> = 1).

During this time the ADC result is indeterminate.

dsPIC30F2011/2012/3012/3013

NOTES:

dsPIC30F2011/2012/3012/3013

21.0 PACKAGING INFORMATION

21.1 Package Marking Information

XXXXXXXXXXXXXXXXX

YYWWNNN

28-Lead SPDIP Example

XXXXXXXXXXXXXXXXX

18-Lead PDIP Example

XXXXXXXXXXXXXXXXX

YYWWNNN

dsPIC30F3012

0610017

Legend: XX...X Customer-specific information

Y Year code (last dig it of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceabi lity code

Pb-free JEDEC designator for Matte Tin (Sn)

*This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

dsPIC30F2012

0610017

30I/SP

30I/P

18-Lead SOIC Example

YYWWNNN

XXXXXXXXXXXX

0610017

30I/SO

dsPIC30F2011

dsPIC30F2011/2012/3012/3013

21.2 Package Marking Information (Continued)

30F2011

28-Lead SOIC

XXXXXXXXXXXXXXXXXXXX

YYWWNNN

Example

dsPIC30F3013

0610017

XXXXXXXXXX

YYWWNNN

44-Lead QFN

dsPIC

30F3013

0610017

30I/SO

30I/ML

28-Lead QFN-S

XXXXXXX

YYWWNNN

Example

30I/MM

0610017

Example

dsPIC30F2011/2012/3012/3013

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&&255***''54

6&! 7,8.

'!9'&! 7 7: ;

7"')%! 7 <

&  1,

&&  = = 

##44!!   - 

1!&&   = =

"#&"#>#& . - - -

##4>#& .   <

: 9&  <<  

&& 9  - 

9#4!!  <  

69#>#& )  ? 

9*9#>#& )  < 

: *+ 1 = = -

NOTE 1

123

  * ,1

dsPIC30F2011/2012/3012/3013

!"!"#$%&'!"(



  !"#$%&"' ()"&'"!&)&#*&&&#

 +%&,&!&

- '!!#.#&"#'#%!&"!!#%!&"!!!&$#''!#

 '!#&.0

1,2 1!'!&$& "!**&"&&!

.32 %'!("!"*&"&&(%%'&"!!

&&255***''54

6&! 99..

'!9'&! 7 7: ;

7"')%! 7 <

&  1,

: 8&  = = ?

##44!!   = =

&#%%+   = -

: >#& . -1,

##4>#& . 1,

: 9&  1,

,'%@&A   = 

3&9& 9  = 

3&& 9 .3

3& IB = <B

9#4!!   = --

9#>#& ) - = 

#%& DB = B

#%&1&&' EB = B

NOTE 1

123

  * ,1

dsPIC30F2011/2012/3012/3013

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

dsPIC30F2011/2012/3012/3013

)!*!!



  !"#$%&"' ()"&'"!&)&#*&&&#

 +%&,&!&

 '!#&.0

1,2 1!'!&$& "!**&"&&!

&&255***''54

6&! 7,8.

'!9'&! 7 7: ;

7"')%! 7 <

&  1,

&&  = = 

##44!!   - 

1!&&   = =

"#&"#>#& .  - --

##4>#& .  < 

: 9&  - -? 

&& 9  - 

9#4!!  <  

69#>#& )   

9*9#>#& )  < 

: *+ 1 = = -

NOTE 1

  * ,1

dsPIC30F2011/2012/3012/3013

)!"!"#$%&'!"(



  !"#$%&"' ()"&'"!&)&#*&&&#

 +%&,&!&

 '!#&.0

1,2 1!'!&$& "!**&"&&!

.32 %'!("!"*&"&&(%%'&"!!

&&255***''54

6&! 99..

'!9'&! 7 7: ;

7"')%! 7 <

&  1,

: 8&  = = ?

##44!!   = =

&#%%+   = -

: >#& . -1,

##4>#& . 1,

: 9&  1,

,'%@&A   = 

3&9& 9  = 

3&& 9 .3

3& IB = <B

9#4!!  < = --

9#>#& ) - = 

#%& DB = B

#%&1&&' EB = B

NOTE 1

123

  * ,1

dsPIC30F2011/2012/3012/3013

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

dsPIC30F2011/2012/3012/3013

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EXPOSED

PAD

NOTE 1

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NOTE 1

BOTTOM VIEW

TOP VIEW

A3 A1

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dsPIC30F2011/2012/3012/3013

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dsPIC30F2011/2012/3012/3013

APPENDIX A: REVISION HISTORY

Revision D (August 2006)

Previous versions of this data sheet contained

Advance or Preliminary Information. They were

distributed with incomplete characterization data.

This revision reflects these updates:

• Supported I2C Slave Addresses

(see Table 14-1)

• ADC Conversion Clock selectio n to allow

200 kHz sampling rate (see Section 16.0 “12-bit

Analog-to-Digital Converter (ADC) Module”)

• Operating Current (IDD) Specifications

(see Table 20-5)

• Idle Current (IIDLE) Specifications

(see Table 20-6)

• Power-Down Current (IPD) Specifications

(see Table 20-7)

• I/O pin Input Specifications

(see Table 20-8)

• BOR voltage limits

(see Table 20-11)

• Watchdog Timer time-out limits

(see Table 20-21)

Revision E (December 2006)

This revision includes updates to the packaging

diagrams.

Revision F (May 2008)

This revision reflects these updates:

• Added FUSE Configuration Register (FICD)

details (see Section 17.7 “Device Configuration

Registers” and Table 17-8)

• Added Note 2 to Device Configuration Registers

table (Table 17-8)

• Updated Bit 10 in the UART2 Register Map (see

Table 15-2). This bit is unimplemented.

• Electrica l Specificat io ns:

- Resolved TBD values for parameters DO10,

DO16, DO20, and DO26 (see Table 20-9)

- 10-bit High-Speed ADC tPDU timing

parameter (time to stabilize) has been

updated from 20 µs typical to 20 µs maximum

(see Table 20-37)

- Parameter OS65 (Internal RC Accuracy) has

been expanded to reflect multiple Min and

Max values for different temperatures (see

Table 20-19)

- Parameter DC12 (RAM Data Retention

Voltage) has been updated to include a Min

value (see Table 20-4)

- Parameter D134 (Erase/Write Cycle Time)

has been updated to include Min and Max

values and the Typ value has been removed

(see Table 20-12)

- Removed parameters OS62 (Internal FRC

Jitter) and OS64 (Internal FRC Drift) and

Note 2 from AC Characteristics (see

Table 20-18)

- Parameter OS63 (Internal FRC Accuracy)

has been expanded to reflect multiple Min

and Max values for different temperatures

(see Table 20-18)

- Updated Min and Max values and Conditions

for parameter SY11 and updated Min, Typ,

and Max values and Conditions for

parameter SY20 (see Table 20-21)

• Additional minor corrections throughout the

document

dsPIC30F2011/2012/3012/3013

Revision G (November 2010)

This revision includes minor typographical and

formatting changes throughout the data sheet text.

The major chang es are referenced by their respective

section in Table A-1.

TABLE A-1: MAJOR SECTION UPDATES

Section Name Update Description

“High-Performance, 16-Bit Digit a l

Signal Controllers”Added Note 1 to all QFN pin diagrams (see “Pin Diagrams”).

Section 1.0 “Device Overview” Updated the Pinout I/O Descriptions for AVDD and AVSS (see Table 1-1).

Section 17.0 “System Integration” Added a shaded note on OSCTUN functionality in Section 17.2.5 “Fast RC

Oscillator (FRC)”.

Section 20.0 “Electrical

Characteristics” Updated the maximum value for parameter DI19 and the minimum value for

parameter DI29 in the I/O Pin Input Specifications (see Table 20-8).

Removed parameter D136 and updated the m i nimum, typical, maximum,

and conditions for parameters D122 and D134 in the Program and

EEPROM specifications (see Table 20-12).

Renamed parameter AD56 to AD56a and added parameter AD56b to the

12-bit A/D Conversion Timing Requirements (see Table 20-37).

“Product Identification System”Added the “MM” package definition.

dsPIC30F2011/2012/3012/3013

INDEX

Numerics

12-bit Analog-to-Digital Converter (A/D) Module ..............113

A/D....................................................................................113

Aborting a Conversion ..............................................115

ADCHS Register.......................................................113

ADCON1 Register.....................................................113

ADCON2 Register.....................................................113

ADCON3 Register.....................................................113

ADCSSL Register.....................................................113

ADPCFG Register.....................................................113

Configuring Analog Port Pins..............................60, 119

Connection Considerations.......................................119

Conversion Operation...............................................114

Effects of a Reset......................................................118

Operation During CPU Idle Mode.............................118

Operation During CPU Sleep Mode..........................118

Output Formats.........................................................118

Power-Down Modes....................... ..................... ......118

Programming the Sample Trigger.............................115

Result Buffer.................................. ..................... ......114

Sampling Requirements............................................117

Selecting the Conversion Sequence.........................114

AC Characteristics ............................................................160

Load Conditions........................................................160

AC Temperature and Voltage Specifications....................160

ADCSelecting the Conversion Clock................................115

ADC Conversion Speeds..................................................116

Address Generator Units ....................................................43

Alternate Vector Table ........................................................69

Analog-to-Digital Converter. See ADC.

Assembler

MPASM Assembler...................................................146

Automatic Clock Stretch....................................................100

During 10-bit Addressing (STREN = 1).....................100

During 7-bit Addressing (STREN = 1).......................100

Receive Mode...........................................................100

Transmit Mode..........................................................100

Bandgap Start-up Time

Requirements............................................................166

Timing Characteristics ..............................................166

Barrel Shifter.......................................................................27

Bit-Reversed Addressing ....................................................46

Example......................................................................47

Implementation ...........................................................46

Modifier Values Table.................................................47

Sequence Table (16-Entry).........................................47

Block Diagrams

12-bit ADC Functional...............................................113

16-bit Timer1 Module..................................................73

16-bit Timer2...............................................................79

16-bit Timer3...............................................................79

32-bit Timer2/3............................................................78

DSP Engine ................................................................24

dsPIC30F2011............................................................12

dsPIC30F2012............................................................13

dsPIC30F3013............................................................15

External Power-on Reset Circuit...............................131

I2C .............................................................................. 98

Input Capture Mode.................................................... 83

Oscillator System...................................................... 125

Output Compare Mode............................................... 87

Reset System........................................................... 129

Shared Port Structure................................................. 59

SPI.............................................................................. 94

SPI Master/Slave Connection..................................... 95

UART Receiver......................................................... 106

UART Transmitter..................................................... 105

BOR Characteristics......................................................... 158

BOR. See Brown-out Reset.

Brown-out Reset

Characteristics.......................................................... 158

Timing Requirements ............................................... 165

C Compilers

MPLAB C18.............................................................. 146

CAN Module

I/O Timing Characteristics........................................ 181

I/O Timing Requirements.......................................... 181

CLKOUT and I/O Timing

Characteristics.......................................................... 164

Requirements........................................................... 164

Code Examples

Data EEPROM Block Erase....................................... 56

Data EEPROM Block Write.. ...................................... 58

Data EEPROM Read.................................................. 55

Data EEPROM Word Erase ....................................... 56

Data EEPROM Word Write ........................................ 57

Erasing a Row of Program Memory ........................... 51

Initiating a Programming Sequence ........................... 52

Loading Write Latches................................................ 52

Code Protection................................................. ............... 123

Control Registers............................................... ................. 50

NVMADR.................................................................... 50

NVMADRU ................................................................. 50

NVMCON.................................................................... 50

NVMKEY .................................................................... 50

Core Architecture

Overview..................................................................... 19

CPU Architecture Overview................................................ 19

Customer Change Notification Service............................. 205

Customer Notification Service .......................................... 205

Customer Support............................................................. 205

Data Accumulators and Adder/Subtractor.......................... 25

Data Space Write Saturation...................................... 27

Overflow and Saturation............................................. 25

Round Logic ............................................................... 26

Write-Back.................................................................. 26

Data Address Space........................................................... 35

Alignment.................................................................... 38

Alignment (Figure)..................................... ................. 38

Effect of Invalid Memory Accesses (Table) ................ 38

MCU and DSP (MAC Class) Instructions Example.... 37

Memory Map......................................................... 35, 36

Near Data Space........................................................ 39

Software Stack ........................................................... 39

Spaces........................................................................ 38

Width .......................................................................... 38

Data EEPROM Memory...................................................... 55

Erasing ....................................................................... 56

Erasing, Block............................................................. 56

dsPIC30F2011/2012/3012/3013

Erasing, Word .............................................................56

Protection Against Spurious Write ..............................58

Reading.......................................................................55

Write Verify .................................................................58

Writing.........................................................................57

Writing, Block..............................................................57

Writing, Word ..............................................................57

DC Characteristics............................................................150

BOR ..........................................................................158

Brown-out Reset .......................................................158

I/O Pin Input Specifications.......................................156

I/O Pin Output Specifications....................................156

Idle Current (IIDLE) ....................................................153

Low-Voltage Detect...................................................157

LVDL.........................................................................157

Operating Current (IDD).............................................152

Power-Down Current (IPD)........................................154

Program and EEPROM.............................................159

Temperature and Voltage Specifications..................150

Development Support .......................................................145

Device Configuration

Device Configuration Registers

FBORPOR................................................................134

FGS...........................................................................134

FOSC........................................................................134

FWDT........................................................................134

Device Overview...........................................................11, 19

Disabling the UART...........................................................107

Divide Support.....................................................................22

Instructions (Table) .....................................................22

DSP Engine.........................................................................23

Multiplier......................................................................25

Dual Output Compare Match Mode ....................................88

Continuous Pulse Mode..............................................88

Single Pulse Mode......................................................88

Electrical Characteristics

AC.............................................................................160

DC.............................................................................150

Enabling and Setting Up UART

Alternate I/O..............................................................107

Setting Up Data, Parity and Stop Bit Selections .......107

Enabling the UART ...........................................................107

Equations

ADC Conversion Clock .............................................115

Baud Rate.................................................................109

Serial Clock Rate ......................................................102

Errata ....................................................................................9

Exception Sequence

Trap Sources ..............................................................67

External Clock Timing Characteristics

Type A, B and C Timer .............................................167

External Clock Timing Requirements................................161

Type A Timer ............................................................167

Type B Timer ............................................................168

Type C Timer ............................................................168

External Interrupt Requests ................................................70

Fast Context Saving............................................................70

Flash Program Memory.......................................................49

I/O Pin Specifications

Input.......................................................................... 156

Output....................................................................... 156

I/O Ports.............................................................................. 59

Parallel (PIO).............................................................. 59

I2C 10-bit Slave Mode Operation........................................ 99

Reception ................................................................. 100

Transmission ............................................................ 100

I2C 7-bit Slave Mode Operation.......................................... 99

Reception ................................................................... 99

Transmission .............................................................. 99

I2C Master Mode Operation.............................................. 101

Baud Rate Generator ............................................... 102

Clock Arbitration ....................................................... 102

Multi-Master Communication,

Bus Collision and Bus Arbitration..................... 102

Reception ................................................................. 102

Transmission ............................................................ 101

I2C Master Mode Support................................................. 101

I2C Module

Addresses................................................................... 99

Bus Data Timing Characteristics

Master Mode..................................................... 177

Slave Mode....................................................... 179

Bus Data Timing Requirements

Master Mode..................................................... 178

Slave Mode....................................................... 179

Bus Start/Stop Bits Timing Characteristics

Master Mode..................................................... 177

Slave Mode....................................................... 179

General Call Address Support.................................. 101

Interrupts .................................................................. 101

IPMI Support............................................................. 101

Operating Function Description.................................. 97

Operation During CPU Sleep and Idle Modes.......... 102

Pin Configuration........................................................ 97

Programmer’s Model .................................................. 97

Registers .................................................................... 97

Slope Control................................ ............................ 101

Software Controlled Clock Stretching (STREN = 1) . 100

Various Modes............................................................ 97

Idle Current (IIDLE) ............................................................ 153

In-Circuit Serial Programming (ICSP)......................... 49, 123

Input Capture (CAPX) Timing Characteristics.................. 169

Input Capture Module......................................................... 83

Interrupts .................................................................... 84

Input Capture Operation During Sleep and Idle Modes...... 84

CPU Idle Mode ........................................................... 84

CPU Sleep Mode........................................................ 84

Input Capture Timing Requirements................................. 169

Input Change Notification Module....................................... 63

dsPIC30F2012/3013 Register Map (Bits 7-0)............. 63

Instruction Addressing Modes ............................................ 43

File Register Instructions............................................ 43

Fundamental Modes Supported ................................. 43

MAC Instructions ........................................................ 44

MCU Instructions........................................................ 43

Move and Accumulator Instructions............................ 44

Other Instructions ....................................................... 44

Instruction Set

Overview................................................................... 140

Summary .................................................................. 137

Internal Clock Timing Examples....................................... 163

Internet Address ............................................................... 205

dsPIC30F2011/2012/3012/3013

Interrupt Controller

Interrupt Priority ..................................................................66

Traps...........................................................................67

Interrupt Sequence .............................................................69

Interrupt Stack Frame.................................................69

Interrupts.............................................................................65

Load Conditions................................................................160

Low Voltage Detect (LVD) ................................................133

Low-Voltage Detect Characteristics....... ..................... ......157

LVDL Characteristics ........................................................157

Memory Organization..........................................................29

Core Register Map......................................................39

Microchip Internet Web Site........................................ ......205

Modulo Addressing .............................................................44

Applicability.................................................................46

Incrementing Buffer Operation Example.....................45

Start and End Address................................................45

W Address Register Selection....................................45

MPLAB ASM30 Assembler, Linker, Librarian ...................146

MPLAB Integrated Development Environment Software..145

MPLAB PM3 Device Programmer ....................................148

MPLAB REAL ICE In-Circuit Emulator System.................147

MPLINK Object Linker/MPLIB Object Librarian ................146

NVMRegister Map...............................................................53

OC/PWM Module Timing Characteristics..........................171

Operating Current (IDD).....................................................152

Operating Frequency vs Voltage

dsPIC30FXXXX-20 (Extended).................................150

Oscillator

Configurations...........................................................126

Fail-Safe Clock Monitor ....................................128

Fast RC (FRC)..................................................127

Initial Clock Source Selection ...........................126

Low-Power RC (LPRC).....................................127

LP Oscillator Control................................... ......127

Phase Locked Loop (PLL) ................................127

Start-up Timer (OST)........................................126

Operating Modes (Table)..........................................124

System Overview......................................................123

Oscillator Selection ...........................................................123

Oscillator Start-up Timer

Timing Characteristics ..............................................165

Timing Requirements................................................165

Output Compare Interrupts .................................................90

Output Compare Module.....................................................87

Timing Characteristics ..............................................170

Timing Requirements................................................170

Output Compare Operation During CPU Idle Mode............90

Output Compare Sleep Mode Operation ............................90

Packaging Information ......................................................187

Marking.............................................................187, 188

Peripheral Module Disable (PMD) Registers ....................135

Pinout Descriptions.............................................................16

PLL Clock Timing Specifications ...................................... 162

POR. See Power-on Reset.

Port Write/Read Example................................................... 60

PORTB

PORTC

PORTD

PORTF

Power Saving Modes........................................................ 133

Idle............................................................................ 134

Sleep ........................................................................ 133

Sleep and Idle........................................................... 123

Power-Down Current (IPD)................................................ 154

Power-up Timer

Timing Characteristics.............................................. 165

Timing Requirements ............................................... 165

Program Address Space..................................................... 29

Construction ............................................................... 31

Data Access from Program Memory Using

Program Space Visibility..................................... 33

Data Access From Program Memory Using

Table Instructions............................................... 32

Data Access from, Address Generation ..................... 31

Data Space Window into Operation ........................... 34

Data Table Access (LS Word).................................... 32

Data Table Access (MS Byte) .................................... 33

Memory Maps............................................................. 30

Table Instructions

TBLRDH............................................................. 32

TBLRDL.............................................................. 32

TBLWTH............................................................. 32

TBLWTL ............................................................. 32

Program and EEPROM Characteristics............................ 159

Program Counter................................................................ 20

Programmable.................................................................. 123

Programmer’s Model .......................................................... 20

Diagram...................................................................... 21

Programming Operations.................................................... 51

Algorithm for Program Flash....................................... 51

Erasing a Row of Program Memory ........................... 51

Initiating the Programming Sequence ........................ 52

Loading Write Latches................................................ 52

Protection Against Accidental Writes to OSCCON........... 128

Reader Response............................................................. 206

Reset ........................................................................ 123, 129

BOR, Programmable................................................ 131

Brown-out Reset (BOR)............................. ............... 123

Oscillator Start-up Timer (OST)................................ 123

POROperating without FSCM and PWRT................ 131

With Long Crystal Start-up Time ...................... 131

POR (Power-on Reset)............................................. 129

Power-on Reset (POR)............................................. 123

Power-up Timer (PWRT).......................................... 123

Reset Sequence................................................................. 67

Reset Sources............................................................ 67

Reset Sources

Brown-out Reset (BOR)............................. ................. 67

Illegal Instruction Trap................................................ 67

dsPIC30F2011/2012/3012/3013

Trap Lockout...............................................................67

Uninitialized W Register Trap .....................................67

Watchdog Time-out.....................................................67

Reset Timing Characteristics............................................165

Reset Timing Requirements..............................................165

Run-Time Self-Programming (RTSP) .................................49

Simple Capture Event Mode...............................................83

Buffer Operation..........................................................84

Hall Sensor Mode .......................................................84

Prescaler.....................................................................83

Timer2 and Timer3 Selection Mode............................84

Simple OC/PWM Mode Timing Requirements..................171

Simple Output Compare Match Mode.................................88

Simple PWM Mode .............................................................88

Input Pin Fault Protection............................................88

Period..........................................................................89

Software Simulator (MPLAB SIM).....................................147

Software Stack Pointer, Frame Pointer...............................20

CALL Stack Frame......................................................39

SPI Module..........................................................................93

Framed SPI Support ...................................................94

Operating Function Description ..................................93

Operation During CPU Idle Mode ...............................95

Operation During CPU Sleep Mode............................95

SDOx Disable .............................................................94

Slave Select Synchronization .....................................95

SPI1 Register Map......................................................96

Timing Characteristics

Master Mode (CKE = 0)....................................172

Master Mode (CKE = 1)....................................173

Slave Mode (CKE = 1)..............................174, 175

Timing Requirements

Master Mode (CKE = 0)....................................172

Master Mode (CKE = 1)....................................173

Slave Mode (CKE = 0)......................................174

Slave Mode (CKE = 1)......................................176

Word and Byte Communication ..................................94

Status Bits, Their Significance and the Initialization Condition

for

RCON Register, Case 1............................................132

Status Bits, Their Significance and the Initialization Condition

for RCON Register, Case 2 ......................................132

Status Register....................................................................20

Symbols Used in Opcode Descriptions.............................138

System Integration

Table Instruction Operation Summary ................................49

Temperature and Voltage Specifications

AC.............................................................................160

DC.............................................................................150

Timer 2/3 Module................................................................77

Timer1 Module....................................................................73

16-bit Asynchronous Counter Mode ...........................73

16-bit Synchronous Counter Mode .............................73

16-bit Timer Mode.......................................................73

Gate Operation ...........................................................74

Interrupt.......................................................................74

Operation During Sleep Mode ....................................74

Prescaler.....................................................................74

Real-Time Clock .........................................................74

Interrupts.............................................................74

Oscillator Operation............................................74

Timer2 and Timer3 Selection Mode.................................... 88

Timer2/3 Module

16-bit Timer Mode....................................................... 77

32-bit Synchronous Counter Mode............................. 77

32-bit Timer Mode....................................................... 77

ADC Event Trigger...................................................... 80

Gate Operation........................................................... 80

Interrupt ...................................................................... 80

Operation During Sleep Mode.................................... 80

Timer Prescaler ............................ ..................... ......... 80

Timing Characteristics

A/D Conversion

Low-speed (ASAM = 0, SSRC = 000).............. 184

Bandgap Start-up Time............................................. 166

CAN Module I/O........................................................ 181

CLKOUT and I/O ...................................................... 164

External Clock........................................................... 160

I2C Bus Data

Master Mode..................................................... 177

Slave Mode....................................................... 179

I2C Bus Start/Stop Bits

Master Mode..................................................... 177

Slave Mode....................................................... 179

Input Capture (CAPX)............................................... 169

OC/PWM Module...................................................... 171

Oscillator Start-up Timer........................................... 165

Output Compare Module .......................................... 170

Power-up Timer........................................................ 165

Reset ........................................................................ 165

SPI Module

Master Mode (CKE = 0).................................... 172

Master Mode (CKE = 1).................................... 173

Slave Mode (CKE = 0)...................................... 174

Slave Mode (CKE = 1)...................................... 175

Type A, B and C Timer External Clock..................... 167

Watchdog Timer ....................................................... 165

Timing Diagrams

PWM Output Timing ................................................... 89

Time-out Sequence on Power-up

(MCLR Not Tied to VDD), Case 1 ..................... 130

Time-out Sequence on Power-up

(MCLR

Not Tied to VDD), Case 2.................................. 130

Time-out Sequence on Power-up

(MCLR

Tied to VDD)...................................................... 130

Timing Diagrams and Specifications

DC Characteristics - Internal RC Accuracy............... 163

Timing Diagrams.See Timing Characteristics

Timing Requirements

A/D Conversion

Low-speed........................................................ 185

Bandgap Start-up Time............................................. 166

Brown-out Reset....................................................... 165

CAN Module I/O........................................................ 181

CLKOUT and I/O ...................................................... 164

External Clock........................................................... 161

I2C Bus Data (Master Mode) .................................... 178

I2C Bus Data (Slave Mode) ...................................... 179

Input Capture............................................................ 169

Oscillator Start-up Timer........................................... 165

Output Compare Module .......................................... 170

Power-up Timer........................................................ 165

dsPIC30F2011/2012/3012/3013

Reset.........................................................................165

Simple OC/PWM Mode.............................................171

SPI Module

Master Mode (CKE = 0)....................................172

Master Mode (CKE = 1)....................................173

Slave Mode (CKE = 0)......................................174

Slave Mode (CKE = 1)......................................176

Type A Timer External Clock......... ...........................167

Type B Timer External Clock......... ...........................168

Type C Timer External Clock....................................168

Watchdog Timer........................................................165

Timing Specifications

PLL Clock..................................................................162

Trap Vectors .......................................................................69

UART Module

Address Detect Mode ...............................................109

Auto-Baud Support ...................................................109

Baud Rate Generator................................................109

Enabling and Setting Up...........................................107

Framing Error (FERR)...............................................109

Idle Status.................................................................109

Loopback Mode ........................................................109

Operation During CPU Sleep and Idle Modes ..........110

Overview...................................................................105

Parity Error (PERR) ..................................................109

Receive Break...........................................................109

Receive Buffer (UxRXB)...........................................108

Receive Buffer Overrun Error (OERR Bit) ................108

Receive Interrupt.......................................................108

Receiving Data..........................................................108

Receiving in 8-bit or 9-bit Data Mode........................108

Reception Error Handling..........................................108

Transmit Break..........................................................108

Transmit Buffer (UxTXB)...........................................107

Transmit Interrupt......................................................108

Transmitting Data......................................................107

Transmitting in 8-bit Data Mode................................107

Transmitting in 9-bit Data Mode................................107

UART1 Register Map................................................111

UART2 Register Map................................................111

UART Operation

Idle Mode..................................................................110

Sleep Mode...............................................................110

Unit ID Locations...............................................................123

Universal Asynchronous Receiver Transmitter

(UART) Module.........................................................105

Wake-up from Sleep .........................................................123

Wake-up from Sleep and Idle .............................................70

Watchdog Timer

Timing Characteristics ..............................................165

Timing Requirements................................................165

Watchdog Timer (WDT)............................................123, 133

Enabling and Disabling.............................................133

Operation..................................................................133

WWW Address..................................................................205

WWW, On-Line Support .......................................................9

dsPIC30F2011/2012/3012/3013

NOTES:

dsPIC30F2011/2012/3012/3013

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dsPIC30F2011/2012/3012/3013

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DS70139GdsPIC30F2011/2012/3012/3013

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dsPIC30F2011/2012/3012/3013

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