ADVANCE CY14B102L, CY14B102N
2-Mbit (256K x 8/128K x 16) nvSRAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 001-45754 Rev. *A Revised June 27, 2008
Features
■15 ns, 20 ns, 25 ns, and 45 ns access times
■Internally organized as 256K x 8 (CY14B102L) or 128K x 16
(CY14B102N)
■Hands off automatic STORE on power down with only a small
capacitor
■STORE to QuantumTrap™ nonvolatile elements initiated by
software, device pin, or AutoS tore™ on power down
■RECALL to SRAM initiated by software or power up
■Infinite read, write, and recall cycles
■200,000 STORE cycles to QuantumTrap
■20 year data retention
■Single 3V +20%, –10% operation
■Commercial, Industrial an d Automotive temperatures
■48-pin FBGA, 44 and 54-pin TSOP II packages
■Pb-free and RoHS compliance
Functional Description
The Cypress CY14B102L/CY14B102N is a fast static RAM, with
a nonvolatile element in each memory cell. The memory is
organized as 256K words of 8 bits each or 128K words of 16 bits
each. The embedded nonvolatile elements incorporate
QuantumTrap technology, producing the world’s most reliable
nonvolatile memory. The SRAM provides infinite read and write
cycles, while independ ent nonvolatile data resides in the highly
reliable QuantumTrap cell. Data transfers from the SRAM to the
nonvolatile elements (the STORE operation) takes place
automatically at power down. On power up, data is restored to
the SRAM (the RECALL operation) from the nonvolatile memory .
Both STORE and RECALL operations are also available unde r
software control.
A
0
- A
17
Address
WE
OE
CE
V
CC
V
SS
V
CAP
DQ0 - DQ7
HSB
CY14B102L
BHE
BLE
Logic Block Diagram
[1]
[1]
CY14B102N
Note
1. Address A0 - A17 and Data DQ0 - DQ7 for x8 configuration, Add r ess A0 - A16 and Data DQ0 - DQ15 for x16 configuration.
[+] Feedback
ADVANCE CY14B102L, CY14B102N
Document Number: 001-45754 Rev. *A Page 2 of 21
Pinouts Figure 1. Pin Diagram - 48 FBGA (Top Vie w)
Figure 2. Pin Diag ram - 44 TSOP II (Top View)
WE
V
CC
A
11
A
10
V
CAP
A
6
A
0
A
3
CE
NC
NC
DQ0
A
4
A
5
NC
DQ2
DQ3
NC
V
SS
A
9
A
8
OE
V
SS
A
7
NC
NC
NC
A
17
A
2
A
1
NC
V
CC
DQ4
NC
DQ5
DQ6
NC DQ7
NC
A
15
A
14
A
13
A
12
HSB
3
26
5
4
1
D
E
B
A
C
F
G
H
A
16
NC
DQ1
(x8)
(Not to Scale)
NC
[4]
[2] [3]
WE
V
CC
A
11
A
10
V
CAP
A
6
A
0
A
3
CE
DQ10
DQ8
DQ9
A
4
A
5
DQ13
DQ12
DQ14
DQ15
V
SS
A
9
A
8
OE
V
SS
A
7
DQ0
BHE
NC
NC
A
2
A
1
BLE
V
CC
DQ2
DQ1
DQ3
DQ4
DQ5 DQ6
DQ7
A
15
A
14
A
13
A
12
HSB
3
26
5
4
1
D
E
B
A
C
F
G
H
A
16
NC
NC
DQ11
(x16)
(Not to Scale)
[4]
[3]
[2]
Notes
2. Address expansion for 4 Mbit. NC pin not connected to die.
3. Address expansion for 8 Mbit. NC pin not connected to die.
4. Address expansi on for 16 Mbit. NC pin not connected to die.
NC
A
8
NC
NC
V
SS
DQ6
DQ5
DQ4
V
CC
A
13
DQ3
A
12
DQ2
DQ1
DQ0 OE
A
9
CE
NC
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
11
A
7
A
14
A
15
A
16
A
17
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22 23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
A
10
NC
WE
DQ7
HSB
NC
V
SS
V
CC
V
CAP
NC
(x8)
[4]
[2]
[3]
V
SS
DQ6
DQ5
DQ4
V
CC
A
13
DQ3
A
12
DQ2
DQ1
DQ0 BLE
A
9
CE
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
11
A
10
A
14
BHE
OE
A
15
A
16
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22 23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
WE
DQ7
A
0
V
SS
V
CC
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
V
CAP
(x16)
[2]
(Not to Scale)
(Not to Scale)
[+] Feedback
ADVANCE CY14B102L, CY14B102N
Document Number: 001-45754 Rev. *A Page 3 of 21
Figure 3. Pin Diag ram - 54 TSOP II (Top View)
Pinouts (continued)
NC
DQ7
DQ6
DQ5
DQ4 V
CC
DQ3
DQ2
DQ1
DQ0
NC
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
V
CAP
WE
A
8
A
10
A
11
A
12
A
13
A
14
A
15
A
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27 28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48 OE
CE
V
CC
NC
V
SS
NC
A
9
NC NC
NC
NC
NC
NC
54
53
52
51
49
50
HSB
BHE
BLE
DQ15
DQ14
DQ13
DQ12
V
SS
DQ11
DQ10
DQ9
DQ8
(x16)
[4] [2]
[3]
(Not to Scale)
Pin Definitions
Pin Name IO Type Description
A0 – A17 Input Address Inputs. Used to select one of the 262, 144 bytes of the nvSRAM for x8 Configuration.
A0 – A16 Address Inputs. Used to select one of the 131, 072 bytes of the nvSRAM for x16 Config uration.
DQ0 – DQ7 Input/Output Bidirectional Data IO Lines for x8 Configuration. Used as input or output lines depending on
operation.
DQ0 – DQ15 Bidirectional Data IO Lines for x16 Configuration. Used as input or output lines depending on
operation.
WE Input Writ e Enab le Inpu t, Acti ve LOW. When selected LOW, data on the IO pin s is written to the address
location latched by the falling edge of CE.
CE Input Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
OE Input Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read
cycles. IO pins are tri-stated on deasserting OE high.
BHE Input Byte High Enable, Active LOW. Controls DQ15 - DQ8.
BLE Input Byte Low Enable, Active LOW. Controls DQ7 - DQ0.
VSS Ground Ground for the Dev ice. Must be connected to the ground of the system.
VCC Power Supply Power Supply Inputs to the Device.
HSB Input/Output Hardware Store Busy (HSB). When LOW this output indicates that a hardware store is in progress.
When pulled LOW external to the chip it initiates a nonvolatile STORE operation. A weak internal pull
up resistor keeps this pin HIGH if not connected (connection is optional).
VCAP Power Supply AutoStore Cap acitor . Supplies power to the nvSRAM during power loss to store data from the SRAM
to nonvolatile elements.
NC No Connect No Connect. Do not connect this pin to the die.
[+] Feedback
ADVANCE CY14B102L, CY14B102N
Document Number: 001-45754 Rev. *A Page 4 of 21
Device Operation
The CY14B102L/CY14B102N nvSRAM is made up of two
functional components paired in the same physical cell. They are
an SRAM memory cell and a nonvolatile QuantumTrap cell. The
SRAM memory cell operates as a standard fast static RAM. Data
in the SRAM is transferred to the nonvolatile cell (the STORE
operation), or from the nonvolatile cell to the SRAM (the RECALL
operation). Using this unique architecture all cells are stored and
recalled in parallel. During the STORE and RECALL operations
SRAM read and write operations are inhibited. The
CY14B102L/CY14B102N supports infinite reads and writes
similar to a typical SRAM. In addition, it provides infinite RECALL
operations from the nonvolatile cells and up to 200K STORE
operations.
SRAM Read
The CY14B102L/CY14B102N performs a READ cycle when CE
and OE are LOW, and WE and HSB are HIGH. The address
specified on pins A0-17 or A0-16 determines which of the 262, 144
data bytes or 131, 072 words of 16 bits each is accessed. When
the read is initiated by an address transition, the outputs are valid
after a delay of tAA. If the read is initiated by CE or OE, the
outputs are valid at tACE or at tDOE, wh ichever is later. The data
outputs repeatedly respond to address changes within the tAA
access time without the need for transitions on any control input
pins. This remains valid until another address change or until CE
or OE is brought HIGH, or WE or HSB is brought LOW.
SRAM Write
A WRITE cycle is performed whenever CE and WE are LOW and
HSB is HIGH. The address inputs must be stable before entering
the WRITE cycle and must remain stable until either CE or WE
goes high at the end of the cycle. The data on the common IO
pins DQ0–15 are written into the memory if the data is valid t SD
before the end of a WE controlled WRITE or before the end of
an CE controlled WRITE. It is recommended that OE be kept
HIGH during the entire WRITE cycle to avoid data bus contention
on common IO lines. If OE is left LOW, internal circuitry turns off
the output buffers tHZWE after WE goes LOW.
AutoStore Operation
The CY14B102L/CY14B102N stores data to the nvSRAM using
one of the following three storage operations: Hardware Store
activated by HSB, Software Store activated by an address
sequence, and AutoStore on device power down. The AutoS tore
operation is a unique feature of QuantumTrap technology and is
enabled by default on the CY14B102L/CY14B102N.
During a normal operation, the device draws current from VCC to
charge a capacitor connected to the VCAP pin. This stored
charge is used by the chip to perform a single STORE operation.
If the voltage on the VCC pin drops below VSWITCH, the part
automatically disconnects the VCAP pin from VCC. A STORE
operation is initiated with power provided by the VCAP capacitor.
Figure 4 shows the proper connection of the storage capacitor
(VCAP) for automatic store operation. Refer to the section DC
Electrical Characteristics on page 7 for the size of VCAP .
To reduce unnecessary nonvolatile stores, AutoStore and
Hardware Store operations are ignored unless at least one
WRITE operation has taken place since the most recent STORE
or RECALL cycle. Software initiated STORE cycles are
performed regardless of whe ther a WRITE operation has taken
place. Monitor the HSB signal by the system to detect if an
AutoStore cycle is in progress.
Figure 4. AutoStore Mode
Hardware STORE Operation
The CY14B102L/CY14B102N provides the HSB pin for
controlling and acknowled ging the STOR E operations. Use the
HSB pin to request a hardware STORE cycle. When the HSB pin
is driven LOW, the CY14B102L/CY14B102N conditionally
initiates a STORE operation after tDELAY. An actual STORE cycle
only begins if a WRITE to the SRAM took place since the last
STORE or RECALL cycle. The HSB pin also acts as an open
drain driver that is internally driven LOW to indicate a busy
condition while the STORE (initiated by any means) is in
progress.
SRAM READ and WRITE operati ons that are in prog ress when
HSB is driven LOW by any means are given time to complete
before the STORE operation is initiated. After HSB goes LOW,
the CY14B102L/CY14B102N continues SRAM operations for
tDELAY. During tDELAY, multiple SRAM READ operations may take
place. If a WRITE is in progress when HSB is pulled low it is
allowed a time, tDELAY to complete. However , any SRAM WRITE
cycles requested after HSB goes LOW is inhibited until HSB
returns HIGH.
During any STORE operation, regardless of how it was initiated,
the CY14B102L/CY14B102N continues to drive the HSB pin
LOW, releasing it only when the STORE is complete. Upon
completion of the STORE operation, the
CY14B102L/CY14B102N remains disabled until the HSB pin
returns HIGH. Leave the HSB unconnected if it is not used.
0.1uF
Vcc
10kOhm
VCAP
Vcc
WE VCAP
VSS
[+] Feedback
ADVANCE CY14B102L, CY14B102N
Document Number: 001-45754 Rev. *A Page 5 of 21
Hardware RECALL (Power up)
During power up or after any low power condition
(VCC<V
SWITCH), an internal RECALL re quest is latched. When
VCC again exceeds the sense voltage of VSWITCH, a RECALL
cycle is automatically initiated and takes tHRECALL to complete.
Software STORE
Tran sfer data from the SRAM to the nonvolatile memory with a
software address sequence. The CY14B102L/CY14B102N
software STORE cycle is initiated by executing sequential
CE-controlled READ cycles from six specific address locations
in exact order . During the STORE cycle an erase of the previous
nonvolatile data is first performed, followed by a progra m of the
nonvolatile elements. After a STORE cycle is initiated, further
input and output are disabled until the cycle is completed.
Because a sequence of READs from specific addresses is used
for STORE initiation, it is important that no other READ or WRITE
accesses intervene in the sequence. If there are intervening
READ or WRITE accesses, the sequence is aborted and no
STORE or RECALL takes place.
To initiate the software STORE cycle, the following READ
sequence must be performed:
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x8FC0 Initiate STORE Cycle
The software sequence may be clocked with CE controlled
READs or OE controlled READs. After the sixth address in the
sequence is entered, the STORE cycle commences and the chip
is disabled. It is important to use READ cycles and not WRITE
cycles in the sequence , although i t is not necessary that OE be
LOW for a valid sequence. After the tSTORE cycle time is fulfilled,
the SRAM is activated again for the READ and WRITE operation.
Software RECALL
T ransfer the data from the nonvolatile memory to the SRAM with
a software address sequence. A software RECALL cycle is
initiated with a sequence of READ operations in a manner similar
to the software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE controlled READ operatio ns must
be performed:
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x4C63 Initiate RECALL Cycle
Internally , RECALL is a two step procedure. First, the SRAM data
is cleared and then, the nonvolatile information is transferred into
the SRAM cells. After t he tRECALL cycle time, the SRAM is again
ready for READ and WRITE operations. The RECALL operation
does not alter the data in the nonvolatile elements.
Table 1. Mode Selection
CE WE OE A15 - A0 Mode IO Power
H X X X Not Selected Output High Z Standby
L H L X Read SRAM Output Data Active
L L X X Write SRAM Input Data Active
L H L 0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8B45
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore
Disable
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active[5,6,7]
L H L 0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4B46
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoS tore Enable
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active[5,6,7]
Notes
5. The six consecutive address location s must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle.
6. While there are 18/17 address lines on the CY14B102L/CY14B102N, only the lower 16 lines are used to control software modes.
7. IO state depends on the state of OE, BHE, and BLE. The IO table shown assumes OE , BHE, and BLE LOW.
[+] Feedback
ADVANCE CY14B102L, CY14B102N
Document Number: 001-45754 Rev. *A Page 6 of 21
Preventing AutoStore
The AutoStore function is disabled by initiating an AutoStore
disable sequence. A sequence of read ope rations is performed
in a manner similar to the software STORE initiation. To initiate
the AutoStore disa ble sequence, the following sequence o f CE
controlled read operations must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x8B45 AutoSt ore Disable
The AutoStore is re-enabled by initiating an AutoStore enable
sequence. A sequence of read operations is performed in a
manner similar to the software RECALL initiation . To initiate the
AutoStore enable sequence, the following sequence of CE
controlled read operations must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x4B46 AutoSt ore Enable
If the AutoStore function is disabled or re-enabled a manual
STORE operation (hardware or software) must be issued to save
the AutoS tore state through subsequent power down cycles. The
part comes from the factory with AutoStore enabled.
Data Protection
The CY14B102L/CY14B102N protects data from corruption
during low voltage conditi ons by inhib iti ng all externa lly i nitiated
STORE and write operations. The low voltage condition is
detected when VCC < VSWITCH. If the CY14B102L/CY14B102N
is in a write mode (both CE and WE LOW) at pow er up, after a
RECALL or STORE, the write is inhibited until a negative
transition on CE or WE is detected. This protects against
inadvertent writes during pow er u p or br own out conditions.
Noise Considerations
Refer CY Appli c a ti o n Note AN1064.
L H L 0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile Store
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active ICC2[5,6,7]
L H L 0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
Recall
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active[5,6,7]
Table 1. Mode Selection (continued)
CE WE OE A15 - A0 Mode IO Power
[+] Feedback
ADVANCE CY14B102L, CY14B102N
Document Number: 001-45754 Rev. *A Page 7 of 21
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied ............ ... ............................ .–55 °C to +150°C
Supply Voltage on VCC Relative to GND..........–0.5V to 4.1V
Voltage Applied to Outputs
in High-Z State.......................................–0.5V to VCC + 0.5V
Input Voltage.............................................–0.5V to Vcc+0.5V
Tran sient Voltage (<20 ns) on
Any Pin to Ground Potential..................–2.0V to VCC + 2.0V
Package Power Dissipation
Capability (TA = 25°C) ...................................................1.0W
Surface Mount Pb Soldering
Temperature (3 Seconds).......................................... +260°C
Output Short Circuit Current [8]....................................15 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current....... ............................ ... ... .......... > 200 mA
Operating Range
Range Ambient Temperature VCC
Commercial 0°C to +70°C 2.7V to 3.6V
Industrial –40°C to +85°C 2.7V to 3.6V
Automotive –40°C to +125°C 2.7V to 3.6V
DC Electrical Characteristics
Over the Operating Range (VCC = 2.7V to 3.6V)[10]
Parameter Description Test Conditions Min Max Unit
ICC1
Average VCC Current tRC = 15 ns
tRC = 20 ns
tRC = 25 ns
tRC = 45 ns
Dependent on output loading and cycl e rate. V alu es
obtained without output loads. IOUT = 0 mA
Commercial 70
65
65
50
mA
mA
mA
Industrial 75
70
70
52
mA
mA
mA
tRC = 25 ns
tRC = 45 ns
Dependent on output loading and cycl e rate. V alu es
obtained without output loads. IOUT = 0 mA
Automotive 90
75 mA
mA
ICC2 Average VCC Current
during STORE All Inputs Don’t Care, VCC = Max
Average current for duration tSTORE
6mA
ICC3[9] Average VCC Current
at tRC= 200 ns, 3V,
25°C typical
WE > (VCC – 0.2). All other I/P cycling.
Dependent on output loading and cycle rate. Values obtained
without output loads.
35 mA
ICC4 Average VCAP Current
during AutoS tore Cycle All Inputs Don’t Care, VCC = Max
Average current for duration tSTORE 6mA
ISB
VCC Standby Current CE > (VCC – 0.2). All others VIN < 0.2V or > (VCC – 0.2V). Standby
current level after nonvolatile cycle is complete.
Inputs are static. f = 0 MHz.
3mA
IIX
Input Leakage Current
(except HSB)VCC = Max, VSS < VIN < VCC –1 +1 μA
Input Leakage Current
(For HSB)VCC = Max, VSS < VIN < VCC –100 +1 μA
IOZ Off-State Output
Leakage Current VCC = Max, VSS < VIN < VCC, CE or OE > VIH –1 +1 μA
VIH Input HIGH Voltage 2.0 VCC + 0.5 V
VIL Input LOW Voltage Vss – 0.5 0.8 V
VOH Output HIGH Voltage IOUT = –2 mA 2.4 V
VOL Output LOW Voltage IOUT = 4 mA 0.4 V
VCAP Storage Capacitor Between VCAP pin and VSS, 5V Rated 61 8 2 μF
Notes
8. Output s shorted for no more than one second. No more than one output shorted at a time.
9. Typical conditions for the acti ve current shown on the front page of the data sheet are average values at 25°C (room temperature ), and VCC = 3V. Not 100% te sted.
10.The HSB pin has IOUT=-10 uA for VOH of 2.4V.This parameter is characterized but not tested.
[+] Feedback
ADVANCE CY14B102L, CY14B102N
Document Number: 001-45754 Rev. *A Page 8 of 21
AC Test Conditions
Input Pulse Levels....................................................0V to 3V
Input Rise and Fall Times (10% - 90%)........................ <5 ns
Input and Output Timing Reference Levels....................1.5V
Capacitance
The following table lists the capacitance parameters.[11]
Parameter Description Test Conditions Max Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz,
VCC = 0 to 3.0V 7pF
COUT Output Capacitance 7 pF
Thermal Resist ance
The following table lists the thermal resistance pa rameters. [11]
Parameter Description Test Conditions 48-FBGA 44-TSOP II 54-TSOP II Unit
ΘJA Thermal Resistance
(Junction to Ambient) Test conditions follow standard test methods
and procedures for measuring thermal
impedance, in accordance with EIA/JESD51.
28.82 31.11 30.73 °C/W
ΘJC Thermal Resistance
(Junction to Case) 7.84 5.56 6.08 °C/W
AC Test Loads
3.0V
OUTPUT
5 pF
R1
R2
789Ω
3.0V
OUTPUT
30 pF
R1
R2
789Ω
for tri-state specs
577Ω 577Ω
Note
11. These parameters are guaranteed but not tested.
[+] Feedback
ADVANCE CY14B102L, CY14B102N
Document Number: 001-45754 Rev. *A Page 9 of 21
AC Switching Characteristics
The following table lists the AC switching characteristics.
Parameters Description 15 ns 20 ns 25 ns 45 ns Unit
Cypress
Parameters Alt
Parameters Min Max Min Max Min Max Min Max
SRAM Read Cycle
tACE tACS Chip Enable Access Time 15 20 25 45 ns
tRC[12] tRC Read Cycle Time 15 20 25 45 ns
tAA[13] tAA Address Access Time 15 20 25 45 ns
tDOE tOE Output Enable to Data Valid 10 10 12 20 ns
tOHA tOH Output Hold After Address
Change 3333ns
tLZCE[14] tLZ Chip Enable to Output Active 3333ns
tHZCE[14] tHZ Chip Disable to Output Inactive 7 8 10 15 ns
tLZOE[14] tOLZ Output Enable to Output Active0000ns
tHZOE[14] tOHZ Output Disable to Output
Inactive 7 8 10 15 ns
tPU[11] tPA Chip Enable to Power Active 0000ns
tPD[11] tPS Chip Disable to Power Standby 15 20 25 45 ns
tDBE - Byte Enable to Data Valid 10 10 12 20 ns
tLZBE -Byte Enable to Output Active0000ns
tHZBE - Byte Disable to Output Inactive 7 8 10 15 ns
SRAM Write Cycle
tWC tWC W r i te Cycle Ti me 15 20 25 4 5 ns
tPWE tWP Write Pulse Width 10152030ns
tSCE tCW Chip Enable To End of Write 15 15 20 30 ns
tSD tDW Data Setup to End of Write 5 8 10 15 ns
tHD tDH Data Hold After End of Write0000ns
tAW tAW Address Setup to End of Write 10 15 20 30 ns
tSA tAS Address Setup to Start of Write0000ns
tHA tWR Address Hold After End of Write0000ns
tHZWE[14,15] tWZ Write Enable to Output Disable 7 8 10 15 ns
tLZWE[14] tOW Output Active after End of Write3333ns
tBW - Byte Enable to End of Write 15 15 2 0 30 ns
Notes
12.WE must be HIGH during SRAM read cycles.
13.Device is continuously selected with CE and OE both LOW.
14.Measured ±200 mV from steady state output voltage.
15.If WE is LOW when CE goes LOW, the output goes into high impedance state.
[+] Feedback
ADVANCE CY14B102L, CY14B102N
Document Number: 001-45754 Rev. *A Page 10 of 21
AutoStore and Power Up RECALL
Parameters Description CY14B102L/CY14B102N Unit
Min Max
tHRECALL [16] Po we r U p RE CALL Duration 20 ms
tSTORE [17] STORE Cycle Duration 15 ms
VSWITCH Low Voltage Trigger Level 2.65 V
tVCCRISE VCC Rise Time 150 μs
Software Controlled STOR and RECALL Cycle
The following table lists the software controlled STORE and RECALL cycle parameters.[18, 19]
Parameters Description 15ns 20 ns 25ns 45ns Unit
Min Max Min Max Min Max Min Max
tRC STORE/RECALL Initiation Cycle Time 15 20 25 45 ns
tAS Address Setup Time 0 0 0 0 ns
tCW Clock Pulse Width 12 15 20 30 ns
tGHAX Address Hold Time 1 1 1 1 ns
tRECALL RECALL Duration 200 200 200 200 μs
tSS [20, 21] Soft Sequence Processing Time 70 70 70 70 μs
Hardware STORE Cycle
Parameters Description CY14B102L/CY14B102N Unit
Min Max
tDELAY [22] Time allowed to complete SRAM Cycle 1 70 μs
tHLHX Hardware STORE pulse width 15 ns
Notes
16.tHRECALL starts from the time VCC rises above VSWITCH.
17.If an SRAM Write has not taken place since the last nonvolatile cycle, no STORE takes place.
18.The software sequence is clocked with CE controlled or OE controlled reads.
19.The six consecutive addresses must be read in the order listed in the mode selection table. WE must be HIGH during all six consecutive cycles.
20.This is the amount of time it takes to take action on a soft sequence command.Vcc power must remain HIGH to effectively regist er command.
21.Commands such as STORE and RECALL lock out IO un til operation is complete which further increases this time. See the specific command.
22.On a hardware STORE initiation, SRAM operation continues to be enabled for ti me tDELAY to allow read and write cycles to complete.
[+] Feedback
ADVANCE CY14B102L, CY14B102N
Document Number: 001-45754 Rev. *A Page 11 of 21
Switching Waveforms
Figure 5. SRAM Read Cycle #1: Address Controlled[12, 13, 23]
Figure 6. SRAM Read Cycle #2: CE and OE Controlled[12, 23, 25]
tRC
tAA
tOHA
ADDRESS
DQ (DATA OUT) DATA VALID
Notes
23.HSB must remain HIGH during READ and WRITE cycles.
24.CE or WE must be >VIH during address transitions.
25.BHE and BLE are applicable for x16 configuration only.
[+] Feedback
ADVANCE CY14B102L, CY14B102N
Document Number: 001-45754 Rev. *A Page 12 of 21
Figure 7. SRAM Write Cycle #1: WE Controlled[13, 21, 22, 23]
Figure 8. SRAM Write Cycle #2: CE Controlled[13, 21, 22, 23]
Switching Waveforms (continued)
t
WC
t
SCE
t
HA
t
AW
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
ADDRESS
CE
WE
DATA IN
DATA OUT
DATA VALID
HIGH IMPEDANCE
PREVIOUS DATA
BHE , BLE
t
BW
tWC
ADDRESS
tSA tSCE
tHA
tAW
tPWE
tSD tHD
CE
WE
DATA IN
DATA OUT HIGH IMPEDANCE
DATA VALID
BHE , BLE tBW
[+] Feedback
ADVANCE CY14B102L, CY14B102N
Document Number: 001-45754 Rev. *A Page 13 of 21
Figure 9. AutoStore or Power Up RECALL[26]
Figure 10. CE Controlled Software STORE/RECALL Cycle[19]
Switching Waveforms (continued)
V
CC
V
SWITCH
tSTORE tSTORE
tHRECALL tHRECALL
AutoStore
POWER-UP RECALL
Read & Write Inhibited
STORE occurs only
if a SRAM write
has happened
No STORE occurs
without atleast one
SRAM write
tVCCRISE
Note
26.Read and Write cycles are ignored during STORE, RECALL, and while VCC is below VSWITCH.
[+] Feedback
ADVANCE CY14B102L, CY14B102N
Document Number: 001-45754 Rev. *A Page 14 of 21
Figure 11 . OE Controlled Software STOR E/ RECALL Cycle[19]
Figure 12. Hardware STORE Cycle[22]
Figure 13. Soft Sequence Processing[20, 21]
Switching Waveforms (continued)
tRC tRC
ADDRESS # 1 ADDRESS # 6
ADDRESS
tAS tCW
tGHAX tSTORE / tRECALL
DATA VALID
DATA VALID HIGH IMPEDANCE
CE
OE
DQ (DATA)
a
aa
aa
a
a
aa
aa
aa
a
t
SS
t
SS
[+] Feedback
ADVANCE CY14B102L, CY14B102N
Document Number: 001-45754 Rev. *A Page 15 of 21
Ordering Information
Speed
(ns) Ordering Code Package
Diagram Package Type Operating
Range
15 CY14B102L-ZS15XCT 51-85087 44-pin TSOP II Commercial
CY14B102L-ZS15XIT 51-85087 44-pin TSOP II Industrial
CY14B102L-ZS15XI 51-85087 44-pin TSOP II
CY14B102L-BA15XCT 51-85128 48-ball FBGA Commercial
CY14B102L-BA15XIT 51-85128 48-ball FBGA Industrial
CY14B102L-BA15XI 51-85128 48-ball FBGA
CY14B102L-ZSP15XCT 51-85160 54-pin TSOP II Commercial
CY14B102L-ZSP15XIT 51-85160 54-pin TSOP II Ind ustrial
CY14B102L-ZSP15XI 51-85160 54-pin TSOP II
CY14B102N-BA115XCT 51-85128 48-ball FBGA Commercial
CY14B102N-BA15XIT 51-85128 48-ball FBGA Industrial
CY14B102N-BA15XI 51-85128 48-ball FBGA
CY14B102N-ZSP15XCT 51-85160 54-pin TSOP II Commercial
CY14B102N-ZSP15XIT 51-85160 54-pin TSOP II Industrial
CY14B102N-ZSP15XI 51-85160 54-pin TSOP II
20 CY14B102L-ZS20XCT 51-85087 44-pin TSOP II Commercial
CY14B102L-ZS20XIT 51-85087 44-pin TSOP II Industrial
CY14B102L-ZS20XI 51-85087 44-pin TSOP II
CY14B102L-BA20XCT 51-85128 48-ball FBGA Commercial
CY14B102L-BA20XIT 51-85128 48-ball FBGA Industrial
CY14B102L-BA20XI 51-85128 48-ball FBGA
CY14B102L-ZSP20XCT 51-85160 54-pin TSOP II Commercial
CY14B102L-ZSP20XIT 51-85160 54-pin TSOP II Ind ustrial
CY14B102L-ZSP20XI 51-85160 54-pin TSOP II
CY14B102N-BA20XCT 51-85128 48-ball FBGA Commercial
CY14B102N-BA20XIT 51-85128 48-ball FBGA Industrial
CY14B102N-BA20XI 51-85128 48-ball FBGA
CY14B102N-ZSP20XCT 51-85160 54-pin TSOP II Commercial
CY14B102N-ZSP20XIT 51-85160 54-pin TSOP II Industrial
CY14B102N-ZSP20XI 51-85160 54-pin TSOP II
[+] Feedback
ADVANCE CY14B102L, CY14B102N
Document Number: 001-45754 Rev. *A Page 16 of 21
25 CY14B102L-ZS25XCT 51-85087 44-pin TSOP II Commercial
CY14B102L-ZS25XIT 51-85087 44-pin TSOP II Industrial
CY14B102L-ZS25XI 51-85087 44-pin TSOP II
CY14B102L-ZS25XAT 51-85087 44-pin TSOP II Automotive
CY14B102N-BA25XCT 51-85128 48-ball FBGA Commercial
CY14B102L-BA25XIT 51-85128 48-ball FBGA Industrial
CY14B102L-BA25XI 51-85128 48-ball FBGA
CY14B102N-BA25XAT 51-85128 48-ball FBGA Automotive
CY14B102L-ZSP25XCT 51-85160 54-pin TSOP II Commercial
CY14B102L-ZSP25XIT 51-85160 54-pin TSOP II Ind ustrial
CY14B102L-ZSP25XI 51-85160 54-pin TSOP II
CY14B102L-ZSP25XAT 51-85160 54-pin TSOP II Automotive
CY14B102N-BA25XCT 51-85128 48-ball FBGA Commercial
CY14B102N-BA25XIT 51-85128 48-ball FBGA Industrial
CY14B102N-BA25XI 51-85128 48-ball FBGA
CY14B102N-BA25XAT 51-85128 48-ball FBGA Automotive
CY14B102N-ZSP25XCT 51-85160 54-pin TSOP II Commercial
CY14B102N-ZSP25XIT 51-85160 54-pin TSOP II Industrial
CY14B102N-ZSP25XI 51-85160 54-pin TSOP II
CY14B102N-ZSP25XAT 51-85160 54-pin TSOP II Automotive
45 CY14B102L-ZS45XCT 51-85087 44-pin TSOP II Commercial
CY14B102L-ZS45XIT 51-85087 44-pin TSOP II Industrial
CY14B102L-ZS45XI 51-85087 44-pin TSOP II
CY14B102L-ZS45XAT 51-85087 44-pin TSOP II Automotive
CY14B102L-BA45XCT 51-85128 48-ball FBGA Commercial
CY14B102L-BA45XIT 51-85128 48-ball FBGA Industrial
CY14B102L-BA45XI 51-85128 48-ball FBGA
CY14B102L-BA45XAT 51-85128 48-ball FBGA Automotive
CY14B102L-ZSP45XCT 51-85160 54-pin TSOP II Commercial
CY14B102L-ZSP45XIT 51-85160 54-pin TSOP II Ind ustrial
CY14B102L-ZSP45XI 51-85160 54-pin TSOP II
CY14B102L-BA45XAT 51-85128 48-ball FBGA Automotive
CY14B102N-BA45XCT 51-85128 48-ball FBGA Commercial
CY14B102N-BA45XIT 51-85128 48-ball FBGA Industrial
CY14B102N-BA45XI 51-85128 48-ball FBGA
CY14B102N-BA45XAT 51-85128 48-ball FBGA Automotive
CY14B102N-ZSP45XCT 51-85160 54-pin TSOP II Commercial
CY14B102N-ZSP45XIT 51-85160 54-pin TSOP II Industrial
CY14B102N-ZSP45XI 51-85160 54-pin TSOP II
CY14B102N-ZSP45XAT 51-85160 54-pin TSOP II Automotive
All part s are Pb-free. The above table contains Advance information. Please contact your local Cypress sales representative for availability of these parts.
Ordering Information (continued)
Speed
(ns) Ordering Code Package
Diagram Package Type Operating
Range
[+] Feedback
ADVANCE CY14B102L, CY14B102N
Document Number: 001-45754 Rev. *A Page 17 of 21
Part Numbering Nomenclature
Option:
T - Tape & Reel
Blank - Std.
Speed:
15 - 15ns
25 - 25 ns
Data Bus:
L - x8
N - x16 Density:
102 - 2 Mb
Voltage:
B - 3.0V
Cypress
CY 14 B 102 L - ZS P 15 X C T
NVSRAM
14 - Auto Store + Software Store + Hardware Store
Temperature:
C - Commercial (0 to 70°C)
I - Industrial (–40 to 85°C)
Pb-Free
Package:
BA - 48 FBGA
ZS - TSOP II
P - 54 Pin
Blank - 44 Pin 45 - 45 ns
A - Automotive (-40 to +125°C)
20 - 20ns
[+] Feedback
ADVANCE CY14B102L, CY14B102N
Document Number: 001-45754 Rev. *A Page 18 of 21
Package Diagrams
Figure 14. 44-Pin TSOP II
MAX
MIN.
DIMENSION IN MM (INCH)
11.938 (0.470)
PLANE
SEATING
PIN 1 I.D.
44
1
18.517 (0.729)
0.800 BSC
0°-5°
0.400(0.016)
0.300 (0.012)
EJECTOR PIN
R
G
O
K
E
A
X
S
11.735 (0.462)
10.058 (0.396)
10.262 (0.404)
1.194 (0.047)
0.991 (0.039)
0.150 (0.0059)
0.050 (0.0020)
(0.0315)
18.313 (0.721)
10.058 (0.396)
10.262 (0.404)
0.597 (0.0235)
0.406 (0.0160)
0.210 (0.0083)
0.120 (0.0047)
BASE PLANE
0.10 (.004)
22
23
TOP VIEW BOTTOM VIEW
51-85087-*A
[+] Feedback
ADVANCE CY14B102L, CY14B102N
Document Number: 001-45754 Rev. *A Page 19 of 21
Figure 15. 48-Ball FBGA - 6 mm x 10 mm x 1.2 mm
Package Diagrams (continued)
A
1
A1 CORNER
0.75
0.75
Ø0.30±0.05(48X)
Ø0.25 M C A B
Ø0.05 M C
B
A
0.15(4X)
0.21±0.05
1.20 MAX
C
SEATING PLANE
0.53±0.05
0.25 C
0.15 C
A1 CORNER
TOP VIEW BOTTOM VIEW
234
3.75
5.25
B
C
D
E
F
G
H
65
465231
D
H
F
G
E
C
B
A
6.00±0.10
10.00±0.10
A
10.00±0.10
6.00±0.10
B
1.875
2.625
0.36
51-85128-*D
[+] Feedback
ADVANCE CY14B102L, CY14B102N
Document Number: 001-45754 Rev. *A Page 20 of 21
Figure 16. 54-Pin TSOP II
Package Diagrams (continued)
51-85160-**
[+] Feedback
Document Number: 001-45754 Rev. *A Revised June 27, 2008 Page 21 of 21
AutoStore and QuantumTrap are registered trademarks of Simtek Corporation. All products and company names mentioned in this document are the trademarks of their respective holders.
ADVANCE CY14B102L, CY14B102N
© Cypress Semiconductor Corporation, 2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no resp onsibility for the use of any
circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress product s are not warrante d nor intended to be use d for medical,
life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furtherm ore, Cypr ess does no t author ize its products fo r use as critica l
components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (C ypress) and is protected by and subject to worldwide patent pro tectio n (United States and foreig n),
United S t ates copyright laws and international treaty provis ions. Cyp ress he reby gr ant s to l icense e a pers onal, no n-excl usive , non-tr ansfer able license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used on ly in conjunction with a C ypress
integrated circui t as specified in the applicab le agreement. Any r eproduction, mod ification, translati on, compilatio n, or represent ation of this Sour ce Code except a s specified abo ve is prohibit ed without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. C ypress reserves the right to make changes without further notice to the materials described he rein. Cypress d oes not
assume any liabil ity ar ising ou t of the a pplic ation or use o f any pr oduct or circ uit descri bed herein . Cypress d oes not a uthor ize its p roducts fo r use as critical componen ts in life-su pport systems whe re
a malfuncti on or failure may reason ably be expected to res ult in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document History Page
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
Products
PSoC psoc.cypress.com
Clocks & Buffers clocks.cypress.com
Wireless wireless.cypress.com
Memories memory.cypress.com
Image Sensors image.cypress.com
PSoC Solutions
General psoc.cypress.com/solutions
Low Power/Low Voltage psoc.cypress.com/low-power
Precision Analog psoc.cypress.com/precision-analog
LCD Drive psoc.cypress.com/lcd-drive
CAN 2.0b psoc.cypress.com/can
USB psoc.cypress.com/usb
Document Title: CY14B102L/CY14B102N 2-Mbit (256K x 8/128K x 16) nvSRAM
Document Number: 001-45754
REV
.ECN NO. Orig. of
Change Submission
Date Description of Change
** 2470086 GVCH New Data Sheet
*A 2522209 GVCH/
AESA 06/27/2008 Added Automotive temperature Range and 20 ns access speed information in
“Features”.
Added ICC1 for automotive temperature range.
Added ICC1 for tRC=20 ns for both industrial and Co mmercial temperature Grade.
Updated Thermal resistance values for 48-FBGA, 44-TSOP II and 54-TSOP II
Packages.
Added AC Switching Cha racteristics specs for 20 ns access speed.
Added software controlled STORE/RECALL cycle specs for 20 ns access speed.
Updated ordering information and part numbering nomenclature.
Updated data sheet template.
[+] Feedback