SLOS289E − DECEMBER 1999 − REVISED SEPTEMBER 2006
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DHigh Output Drive . . . >300 mA
DRail-To-Rail Output
DUnity-Gain Bandwidth . . . 2.7 MHz
DSlew Rate . . . 1.5 V/µs
DSupply Current . . . 700 µA/Per Channel
DSupply Voltage Range . . . 2.5 V to 6 V
DSpecified Temperature Range:
− TA = 0°C to 70°C . . . Commercial Grade
− TA = −40°C to 125°C . . . Industrial Grade
DUniversal OpAmp EVM
description
The TLV411x single supply operational amplifiers provide output currents in excess of 300 mA at 5 V. This
enables standard pin-out amplifiers to be used as high current buf fers or in coil driver applications. The TLV4110
and TLV4113 come with a shutdown feature.
The TLV411x is available in the ultra small MSOP PowerPAD package, which offers the exceptional thermal
impedance required for amplifiers delivering high current levels.
All TLV411x devices are offered in PDIP, SOIC (single and dual) and MSOP PowerPAD (dual).
FAMILY PACKAGE TABLE
DEVICE
NUMBER OF
PACKAGE TYPES
SHUTDOWN
UNIVERSAL
DEVICE
NUMBER OF
CHANNELS MSOP PDIP SOIC
SHUTDOWN
UNIVERSAL
EVM BOARD
TLV4110 1 8 8 8 Yes
Refer to the EVM
TLV4111 1 8 8 8 — Refer to the EVM
Selection Guide
TLV4112 2 8 8 8 —
Selection Guide
(Lit# SLOU060)
TLV4113 2 10 14 14 Yes
(Lit# SLOU060)
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
VDD = 3 V
IOH − High-Level Output Current − mA
VOH − High-Level Output Voltage − V
TA = 70°C
TA = 25°C
TA = 0°C
TA = −40°C
3.0
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.0 0 50 200100 150 250 300
2.2
2.1
TA = 125°CTA = −40°C
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
VDD = 3 V
IOL − Low-Level Output Current − mA
TA = 70°C
TA = 25°C
TA = 0°C
OL
V − Low-Level Output Voltage − V
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.0 0 50 200100 150 250 300
0.2
0.1
TA = 125°C
Copyright 1999−2006, Texas Instruments Incorporated
!"# $ %&'# "$ (&)*%"# +"#',
+&%#$ %! # $('%%"#$ (' #-' #'!$ '."$ $#&!'#$
$#"+"+ /""#0, +&%# (%'$$1 +'$ # '%'$$"*0 %*&+'
#'$#1 "** (""!'#'$,
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
8
7
6
5
1OUT
1IN−
1IN+
GND
VDD
2OUT
2IN−
2IN+
TLV4112
D, DGN, OR P PACKAGE
(TOP VIEW)
Operational Amplifier
+
−
PowerPAD is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.
SLOS289E − DECEMBER 1999 − REVISED SEPTEMBER 2006
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV4110 AND TLV4111 AVAILABLE OPTIONS
PACKAGED DEVICES
TA
SMALL OUTLINE
MSOP
PLASTIC DIP
TA
SMALL OUTLINE
(D)†‡
SMALL OUTLINE
†
SYMBOL
PLASTIC DIP
(P)
(D)†‡
SMALL OUTLINE
(DGN)†
SYMBOL
(P)
0°C to 70°C
TLV4110CD TLV4110CDGN xxTIAHL TLV4110CP
0°C to 70°CTLV4111CD TLV4111CDGN xxTIAHN TLV4111CP
−40°C to 125°C
TLV4110ID TLV4110IDGN xxTIAHM TLV4110IP
−40
°
C to 125
°
C
TLV4111ID TLV4111IDGN xxTIAHO TLV4111IP
†This package is available taped and reeled. To order this packaging option, add an R suffix to the part
number (e.g., TLV4110CDR).
‡In the SOIC package, the maximum RMS output power is thermally limited to 350 mW; 700 mW peaks
can be driven, as long as the RMS value is less than 350 mW.
TLV4112 AND TLV4113 AVAILABLE OPTIONS
PACKAGED DEVICES
TA
SMALL OUTLINE
MSOP
PLASTIC DIP
TA
SMALL OUTLINE
(D)†‡
SMALL OUTLINE
†
SYMBOL
SMALL OUTLINE
†
SYMBOL
PLASTIC DIP
(P)
(D)†‡
SMALL OUTLINE
(DGN)†
SYMBOL
SMALL OUTLINE
(DGQ)†
SYMBOL
(P)
0°C to 70°C
TLV4112CD TLV4112DGN xxTIAHP — — TLV4112CP
0°C to 70°CTLV4113CD — — TLV4113CDGQ xxTIAHR TLV4113CN
−40°C to 125°C
TLV4112ID TLV4112IDGN xxTIAHQ — — TLV4112IP
−40
°
C to 125
°
C
TLV4113ID — — TLV4113IDGQ xxTIAHS TLV4113IN
†This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLV4112CDR).
‡In the SOIC package, the maximum RMS output power is thermally limited to 350 mW; 700 mW peaks can be driven, as long as the RMS value
is less than 350 mW.
TLV411x PACKAGE PIN OUTS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1OUT
1IN−
1IN+
GND
NC
1SHDN
NC
VDD
2OUT
2IN−
2IN+
NC
2SHDN
NC
(TOP VIEW)
1
2
3
4
8
7
6
5
NC
IN−
IN+
GND
SHDN
VDD
OUT
NC
TLV4110
D, DGN OR P PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
1OUT
1IN−
1IN+
GND
VDD
2OUT
2IN−
2IN+
TLV4112
D, DGN, OR P PACKAGE
(TOP VIEW)
TLV4113
D OR N PACKAGE
NC − No internal connection
1
2
3
4
5
10
9
8
7
6
1OUT
1IN−
1IN+
GND
1SHDN
VDD+
2OUT
2IN−
2IN+
2SHDN
TLV4113
DGQ PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
NC
IN−
IN+
GND
NC
VDD
OUT
NC
TLV4111
D, DGN OR P PACKAGE
(TOP VIEW)
SLOS289E − DECEMBER 1999 − REVISED SEPTEMBER 2006
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VDD (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential input voltage, VID ±VDD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI ±VDD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output current, IO (see Note 2) 800 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous /RMS output current, IO (each output of amplifier): TJ ≤ 105°C 350 mA. . . . . . . . . . . . . . . . . . . .
TJ ≤ 150°C 110 mA. . . . . . . . . . . . . . . . . . . .
Peak output current, IO (each output of amplifier: TJ ≤ 105°C 500 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TJ ≤ 150°C 155 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA: C suffix 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I suffix −40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum junction temperature, TJ 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to GND.
2. To prevent permanent damage the die temperature must not exceed the maximum junction temperature.
DISSIPATION RATING TABLE
PACKAGE θJC
(°C/W) θJA
(°C/W) TA ≤ 25°C
POWER RATING TA = 125°C
POWER RATING
D (8) 38.3 176 710 mW 142 mW
D (14) 26.9 122.3 1022 mW 204.4 mW
DGN (8)‡4.7 52.7 2.37 W 474.4 mW
DGQ (10)‡4.7 52.3 2.39 W 478 mW
P (8) 41 104 1200 mW 240.4 mW
N (14) 32 78 1600 mW 320.5 mW
‡See The Texas Instruments document, PowerPAD Thermally Enhanced Package Application Report (literature nu m be r
SLMA002), for more information on the PowerPAD package. The thermal data was measured on a PCB layout based
on the information in the section entitled Texas Instruments Recommended Board for PowerPAD on page 33 of the before
mentioned document.
recommended operating conditions
MIN MAX UNIT
Supply voltage, VDD 2.5 6 V
Common-mode input voltage range, VICR 0 VDD−1.5 V
Operating free-air temperature, TA
C-suffix 0 70
°C
Operating free-air temperature, TAI-suffix −40 125 °C
V(on)
VDD = 3 V 2.1
Shutdown turn-on/off voltage level§
V(on) VDD = 5 V 3.8
V
Shutdown turn-on/off voltage level§
V(off)
VDD = 3 V 0.9 V
V(off) VDD = 5 V 1.65
§Relative to GND
SLOS289E − DECEMBER 1999 − REVISED SEPTEMBER 2006
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at recommend operating conditions, VDD = 3 V and 5 V (unless otherwise
noted)
dc performance
PARAMETER TEST CONDITIONS TA†MIN TYP MAX UNITS
VIO
Input offset voltage
VIC = VDD/2,
VO = VDD/2 ,
25°C 175 3500
V
VIO Input offset voltage VIC = VDD/2,
RL = 100 Ω,
VO = VDD/2 ,
RS = 50 Ω
Full range 4000 µV
αVIO Offset voltage draft
RL = 100 Ω,
RS = 50 Ω
25°C 3 µV/°C
CMRR
Common-mode rejection ratio
VDD = 3 V,
RS = 50 ΩVIC = 0 to 2 V, 25°C 63
dB
CMRR Common-mode rejection ratio VDD = 5 V,
RS = 50 ΩVIC = 0 to 4 V, 25°C 68 dB
RL=100 Ω
25°C 78 84
VDD = 3 V,
RL=100 ΩFull range 67
VDD = 3 V,
VO(PP)=0 to 1V
RL=10 kΩ
25°C 85 100
AVD
Large-signal differential voltage
VO(PP)=0 to 1V
RL=10 kΩFull range 75
dB
AVD
Large-signal differential voltage
amplification
RL=100 Ω
25°C 88 94 dB
amplification
VDD = 5 V,
RL=100 ΩFull range 75
VDD = 5 V,
VO(PP)=0 to 3V
RL=10 kΩ
25°C 90 110
VO(PP)=0 to 3V
RL=10 kΩFull range 85
†Full range is 0°C to 70°C for C suffix and −40°C to 125°C for I suffix. If not specified, full range is −40°C to 125°C.
input characteristics
PARAMETER TEST CONDITIONS TA†MIN TYP MAX UNITS
25°C 0.3 25
I
IO
Input offset current V
IC
= V
DD
/2 TLV411xC
Full range
50
IIO
Input offset current
VIC = VDD/2
TLV411xI Full range 250
pA
VO = VDD/2,
25°C 0.3 50 pA
I
IB
Input bias current VO = VDD/2,
RS = 50 Ω
TLV411xC
Full range
100
IIB
Input bias current
RS = 50 Ω
TLV411xI Full range 500
ri(d) Differential input resistance 25°C 1000 GΩ
CIC Common-mode input capacitance f = 100 Hz 25°C 5 pF
†Full range is 0°C to 70°C for C suffix and −40°C to 125°C for I suffix. If not specified, full range is −40°C to 125°C.
SLOS289E − DECEMBER 1999 − REVISED SEPTEMBER 2006
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at specified free-air temperature, VDD = 3 V and 5 V (unless otherwise
noted) (continued)
output characteristics
PARAMETER TEST CONDITIONS TA†MIN TYP MAX UNITS
IOH = −10 mA
25°C 2.7 2.97
VDD = 3 V, VIC = VDD/2
IOH = −10 mA Full range 2.7
V
VDD = 3 V, VIC = VDD/2
IOH =−100 mA
25°C 2.6 2.73 V
IOH =−100 mA Full range 2.6
IOH = −10 mA
25°C 4.7 4.96
VOH High-level output voltage IOH = −10 mA Full range 4.7
VOH
High-level output voltage
IOH = −100 mA
25°C 4.6 4.76
VDD = 5 V, VIC = VDD/2 IOH = −100 mA Full range 4.6 V
VDD = 5 V, VIC = VDD/2
25°C 4.45 4.6
V
IOH = −200 mA −40°C to
85°C4.35
IOL = 10 mA
25°C 0.03 0.1
VDD = 3 V and 5 V,
IOL = 10 mA Full range 0.1
VDD = 3 V and 5 V,
VIC = VDD/2
IOL = 100 mA
25°C 0.33 0.4
VOL Low-level output voltage
VIC = VDD/2
IOL = 100 mA Full range 0.55 V
VOL
Low-level output voltage
25°C 0.38 0.6
V
VDD = 5 V, VIC = VDD/2 IOL = 200 mA −40°C to
85°C0.7
IO
Output current‡
Measured at 0.5 V from rail
VDD = 3 V
25°C
±220
mA
IO
Output current‡
Measured at 0.5 V from rail VDD = 5 V 25°C±320 mA
IOS
Short-circuit output current‡
Sourcing
25°C
800
mA
IOS
Short-circuit output current‡
Sinking 25°C800 mA
†Full range is 0°C to 70°C for C suffix and −40°C to 125°C for I suffix. If not specified, full range is −40°C to 125°C.
‡When driving output currents in excess of 200 mA, the MSOP PowerPAD package is required for thermal dissipation.
power supply
PARAMETER TEST CONDITIONS TAMIN TYP MAX UNITS
IDD
Supply current (per channel)
VO = VDD/2
25°C 700 1000
A
IDD Supply current (per channel) VO = VDD/2 Full range 1500 µA
VDD =2.7 to 3.3 V,
No load,
25°C 70 82
PSRR
Power supply rejection ratio (∆VDD / ∆VIO)
VDD =2.7 to 3.3 V,
VIC = VDD/2 V
No load,
Full range 65
dB
PSRR
Power supply rejection ratio (
∆
V
DD
/
∆
V
IO
)
VDD =4.5 to 5.5 V,
No load,
25°C 70 79
dB
VDD =4.5 to 5.5 V,
VIC = VDD/2 V
No load,
Full range 65
†Full range is 0°C to 70°C for C suffix and −40°C to 125°C for I suffix. If not specified, full range is −40°C to 125°C.
SLOS289E − DECEMBER 1999 − REVISED SEPTEMBER 2006
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at specified free-air temperature, VDD = 3 V and 5 V (unless otherwise
noted) (continued)
dynamic performance
PARAMETER TEST CONDITIONS TA†MIN TYP MAX UNITS
GBWP Gain bandwidth product RL=100 ΩCL=10 pF 25°C 2.7 MHz
Vo( ) = 2 V,
VDD = 3 V
25°C 0.8 1.57
SR
Slew rate at unity gain
Vo(pp)
= 2 V,
RL = 100 Ω,
VDD = 3 V Full range 0.55
V/ s
SR Slew rate at unity gain
o(pp)
R
L
= 100
Ω
,
CL = 10 pF
VDD = 5 V
25°C 1 1.57 V/µs
CL = 10 pF
VDD = 5 V Full range 0.7
φMPhase margin
RL = 100 Ω,
CL = 10 pF
25°C
66
Gain margin RL = 100 Ω, CL = 10 pF 25°C16 dB
ts
Settling time
V(STEP)pp = 1 V,
AV = −1,
0.1%
25°C
0.7
µs
t
s
Settling time
AV = −1,
CL = 10 pF,
RL = 100 Ω0.01%
25
°
C
1.3 µ
s
†Full range is 0°C to 70°C for C suffix and −40°C to 125°C for I suffix. If not specified, full range is −40°C to 125°C.
noise/distortion performance
PARAMETER TEST CONDITIONS TAMIN TYP MAX UNITS
VO(pp) = VDD/2 V,
AV = 1 0.025
THD+N Total harmonic distortion plus noise
VO(pp) = VDD/2 V,
R
L
= 100 Ω,
f = 100 Hz
AV = 10 0.035
THD+N
Total harmonic distortion plus noise
RL = 100 Ω,
f = 100 Hz AV = 100
25°C
0.15
Vn
Equivalent input noise voltage
f = 100 Hz
25
°
C
55
nV/√Hz
VnEquivalent input noise voltage f = 10 kHz 10
nV/√Hz
InEquivalent input noise current f = 1 kHz 0.31 fA/√Hz
shutdown characteristics
PARAMETER TEST CONDITIONS TA†MIN TYP MAX UNITS
IDD(SHDN)
Supply current in shutdown mode (per channel)
SHDN = 0 V
25°C 3.4 10
A
IDD(SHDN
)
Supply current in shutdown mode (per channel)
(TLV4110, TLV4113)
SHDN = 0 V
Full range 15 µA
t(ON) Amplifier turn-on time‡
RL = 100 Ω
25°C
1
µs
t(Off) Amplifier turn-off time‡
R
L
= 100
Ω
25
°
C
3.3 µ
s
†Full range is 0°C to 70°C for C suffix and −40°C to 125°C for I suffix. If not specified, full range is −40°C to 125°C.
‡Disable time and enable time are defined as the interval between application of the logic signal to SHDN and the point at which the supply current
has reached half its final value.
SLOS289E − DECEMBER 1999 − REVISED SEPTEMBER 2006
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
VIO Input offset voltage vs Common-mode input voltage 1, 2
CMRR Common-mode rejection ratio vs Frequency 3
VOH High-level output voltage vs High-level output current 4, 6
VOL Low-level output voltage vs Low-level output current 5, 7
ZoOutput impedance vs Frequency 8
IDD Supply current vs Supply voltage 9
kSVR Power supply voltage rejection ratio vs Frequency 10
AVD Differential voltage amplification and phase vs Frequency 11
Gain-bandwidth product vs Supply voltage 12
SR
Slew rate
vs Supply voltage 13
SR Slew rate vs Temperature 14
Total harmonic distortion+noise vs Frequency 15
VnEquivalent input voltage noise vs Frequency 16
Phase margin vs Capacitive load 17
Voltage-follower signal pulse response 18, 19
Inverting large-signal pulse response 20, 21
Small-signal inverting pulse response 22
Crosstalk vs Frequency 23
Shutdown forward and reverse isolation 24
Shutdown supply current vs Free-air temperature 25
Shutdown supply current/output voltage 26
SLOS289E − DECEMBER 1999 − REVISED SEPTEMBER 2006
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 1
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
VICR − Common-Mode Input Voltage − V
VIO − Input Offset Voltage − V
µ
0 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2−0.2
6000
4000
2000
0
−2000
−4000
−6000
VDD = 3 V
TA = 25°C
Figure 2
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
VDD = 5 V
TA = 25°C
VICR − Common-Mode Input Voltage − V
VIO − Input Offset Voltage − V
µ
6000
4000
2000
0
−2000
−4000
−6000
−0.2 0.4 2.21.0 1.6 2.8 3.4 4.0 4.6 5.2
0
Figure 3
COMMON-MODE REJECTION RATIO
vs
FREQUENCY
VDD = 3 V
TA = 25°C
f − Frequency − Hz
100 1 k 1 M10 k 100 k 10 M
CMRR − Common-Mode Rejection Ratio − dB
120
110
100
90
80
70
60
50
40
Figure 4
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
VDD = 3 V
IOH − High-Level Output Current − mA
VOH − High-Level Output Voltage − V
TA = 70°C
TA = 25°C
TA = 0°C
TA = −40°C
3.0
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.0 0 50 200100 150 250 300
2.2
2.1
TA = 125°C
Figure 5
TA = −40°C
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
VDD = 3 V
IOL − Low-Level Output Current − mA
TA = 70°C
TA = 25°C
TA = 0°C
OL
V − Low-Level Output Voltage − V
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.0 0 50 200100 150 250 300
0.2
0.1
TA = 125°C
Figure 6
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
VDD = 5 V
IOH − High-Level Output Current − mA
VOH − High-Level Output Voltage − V
5.0
4.9
4.8
4.7
4.6
4.5
4.4
4.3
4.0 0 50 200100 150 250 300
4.2
4.1
TA = −40°C
TA = 70°C
TA = 25°C
TA = 0°C
TA = 125°C
Figure 7
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
VDD = 5 V
IOL − Low-Level Output Current − mA
TA = −40°C
TA = 125°C
TA = 70°C
TA = 25°C
TA = 0°C
OL
V − Low-Level Output Voltage − V
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.0 0 50 200100 150 250 300
0.2
0.1
Figure 8
OUTPUT IMPEDANCE
vs
FREQUENCY
VDD = 3 & 5 V
TA = 25°C
f − Frequency − Hz
100 1k 10k
0.10
1
10
100
− Output Impedance −ZoΩ
A = 1
A = 100
A = 10
100k 1M 10M
Figure 9
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
AV = 1
VIN = VDD/2 V
VDD − Supply Voltage − V
TA = −40°C
TA = 125°C
TA = 70°C
TA = 25°C
TA = 0°C
DD
I Supply Current − −Aµ
1200
1000
800
600
400
200
001 423 56
SLOS289E − DECEMBER 1999 − REVISED SEPTEMBER 2006
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 10
POWER SUPPLY REJECTION RATIO
vs
FREQUENCY
f − Frequency − Hz
100 1 k 1 M10 k 100 k 10 M
PSRR − Power Supply Rejection Ratio − V
VDD = 3 & 5 V
RF = 1 kΩ
RI = 100 Ω
VIN = 0 V
TA = 25°C
100
90
80
70
60
50
40
30
0
20
10
Figure 11
45
90
135
−45
0
DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE
vs
FREQUENCY
f − Frequency − Hz
100 1 k 1 M10 k 100 k 10 M
− Differential Voltage Amplification − dBAVD
Phase Margin − °
VDD = 3 & 5 V
RL = 100 kΩ
CL = 10 pF
TA = 25°C
PHASE
GAIN
120
100
80
60
40
20
0
−20
−40
Figure 12
GAIN-BANDWIDTH PRODUCT
vs
SUPPLY VOLTAGE
TA = 25°C
RL = 100 Ω
CL = 10 pF
f = 1 kHz
AV =open loop
VDD − Supply Voltage − V
Gain-Bandwidth Product − MHz
2.5 3 4.53.5 4 5 5.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
Figure 13
0.00
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
SLEW RATE
vs
SUPPLY VOLTAGE
AV = 1
RL = 100 Ω
CL = 10 pF
VDD − Supply Voltage − V
SR − Slew Rate − V/
µ
s
SR+
SR−
2.5 3 4.53.5 4 5 5.5 6
Figure 14
0.00
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
−40−25−10 5 20 35 50 65 80 95 110125
SLEW RATE
vs
TEMPERATURE
VDD = 3 & 5 V
AV = 1
RL = 100 Ω
CL = 10 pF
TA − Temperature − °C
SR − Slew Rate − V/
µ
s
SR+
SR−
Figure 15
TOTAL HARMONIC DISTORTION+NOISE
vs
FREQUENCY
f − Frequency − Hz
10 100 100 k1 k 10 k
0.01
0.1
1
10
VDD = 5 V
RL = 100 Ω
VO(PP) = VDD/2
AV = 1, 10, & 100
A = 1
A = 100
A = 10
THD+N −Total Harmonic Distortion + Noise
Figure 16
EQUIVALENT INPUT VOLTAGE NOISE
vs
FREQUENCY
VDD = 3 V
f − Frequency − Hz
10 1 k 10 k 100 k
VDD = 5 V
100
nV/ Hz− Equivalent Input Voltage Noise − Vn
0
60
100
160
20
40
80
120
140
Figure 17
PHASE MARGIN
vs
CAPACITIVE LOAD
VDD = 3 & 5 V
TA = 25°C
Capacitive Load − pF
100 1 k 10 k 100 k
RL = 100
10
Phase Margin − °
RNULL = 0
RNULL = 20
RNULL = 20
RL = 600
RNULL = 0
20
50
70
100
30
40
60
80
90
10
0
SLOS289E − DECEMBER 1999 − REVISED SEPTEMBER 2006
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 18
−2 0 2 4 6 8 10 12 14
VOLTAGE-FOLLOWER
LARGE-SIGNAL PULSE RESPONSE
VDD = 5 V
AV = 1
RL = 100 Ω
CL = 10 pF
TA = 25°C
t − TIME − µs
0
1
2
3
4
0
1
2
3
4
5
− Output Voltage − V
V
O
V
I
− Input Voltage − V
VIN
VO
Figure 19
−0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4
VOLTAGE-FOLLOWER
SMALL-SIGNAL PULSE RESPONSE
VDD = 5 V
AV = 1
RL = 100 Ω
CL = 10 pF
TA = 25°C
VIN = 100 mV
t − TIME − µs
2.4
2.45
2.5
2.55
2.45
2.5
2.55
2.6
− Output Voltage − V
VO
V
I
− Input Voltage − V
VIN
VO
Figure 20
−1012345678
INVERTING LARGE-SIGNAL
PULSE RESPONSE
t − TIME − µs
0
1
2
3
−1
0
2
3
− Output Voltage − V
VOVI− Input Voltage − V
VDD = 5 V
AV = −1
RL = 100 Ω
CL = 50 pF
TA = 25°C
VIN = 2.5 V
VIN
VO
1
−2
4
5
Figure 21
−1012345678
INVERTING LARGE-SIGNAL
PULSE RESPONSE
t − TIME − µs
0
1
2
3
−1
0
2
3
− Output Voltage − V
VOVI− Input Voltage − V
VDD = 5 V
AV = −1
RL = 100 Ω
CL = 50 pF
TA = 25°C
VIN = 2.5 V
VIN
VO
1
−2
4
5
Figure 22
SMALL-SIGNAL INVERTING
PULSE RESPONSE
t − TIME − µs
2.42
2.46
2.5
2.42
2.46
2.5
2.54
2.58
− Output Voltage − V
VO
V
I
− Input Voltage − V
VDD = 5 V
AV = −1
RL = 100 Ω
CL = 50 pF
TA = 25°C
VIN = 2.5 V
VIN
VO
2.54
0 0.2 0.6 1.0 1.4 1.8 2.2 2.6 3.0
Figure 23
CROSSTALK
vs
FREQUENCY
VDD = 3 & 5 V
RL = 100 Ω
All Channels
f − Frequency − Hz
100 1 k 10 k 100 k10
VIN = 4 VPP
VIN = 2 VPP
Crosstalk − dB
−120
−100
−60
−40
−20
0
−80
Figure 24
−160
−140
−120
−100
−80
−60
−40
−20
0
10 100 1 k 10 k 100 k 1 M 10 M
f − Frequency − Hz
Shutdown F/R Isolation − dB
SHUTDOWN FORWARD AND
REVERSE ISOLATION
VDD = 3 and 5 V,
RL = 100 Ω,
CL = 50 pF,
AV = 1.
TA = 25°C
VIN = 0.1 VPP
VIN = 2.5 VPP
Figure 25
0
2
4
6
8
10
12
14
16
−40 −25 −10 5 20 35 50 65 80 95 110 125
− Shutdown Supply Current −
SHUTDOWN SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
IDD
TA − Free-Air Temperature − °C
VDD = 3 and 5 V
VIN = VDD/2,
No Load
µA
SLOS289E − DECEMBER 1999 − REVISED SEPTEMBER 2006
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
0 20 40 60 80 100
SHUTDOWN SUPPLY CURRENT / OUTPUT VOLTAGE
120
− Shutdown Supply Current −
IDD(SD) SHDN − Shutdown Pulse − V
t − Time − µs
4
2
0
6
4
1
2
3
− Output Voltage − VVO
2
0.5
1
1.5
0
VDD = 3 V
AV = 1
RL = 100 Ω
CL = 10 pF
VIN = VDD/2
TA = 25°C
VO
SD
IDD(SD)
µA
0
Figure 26
SLOS289E − DECEMBER 1999 − REVISED SEPTEMBER 2006
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
shutdown function
Two members of the TLV411x family (TLV4110/3) have a shutdown terminal for conserving battery life in
portable applications. When the shutdown terminal is tied low, the supply current is reduced to just nano amps
per channel, the amplifier is disabled, and the outputs are placed in a high impedance mode. In order to save
power in shutdown mode, an external pullup resistor is required, therefore, to enable the amplifier the shutdown
terminal must be pulled high. When the shutdown terminal is left floating, care should be taken to ensure that
parasitic leakage current at the shutdown terminal does not inadvertently place the operational amplifier into
shutdown.
driving a capacitive load
When the amplifier is configured in this manner, capacitive loading directly on the output will decrease the
device’s phase margin leading to high frequency ringing or oscillations. Therefore, for capacitive loads of greater
than 1 n F, i t is recommended that a resistor be placed in series (RNULL) with the output of the amplifier, as shown
in Figure 27. A maximum value of 20 Ω should work well for most applications.
CLOAD
R
F
Input Output
RGRNULL
+
−
RLCL
R
F
Input Outpu
t
RGRNULL
+
−
RL
Snubber
C
(a) (b)
Figure 27. Driving a Capacitive Load
offset voltage
The output offset voltage, (VOO) is the sum of the input offset voltage (VIO) and both input bias currents (IIB) times
the corresponding gains. The following schematic and formula can be used to calculate the output offset
voltage:
VOO +VIO
ǒ
1)ǒRF
RGǓ
Ǔ
"IIB)RS
ǒ
1)ǒRF
RGǓ
Ǔ
"IIB– RF
+
−
VI+
RG
RS
R
F
IIB−
VO
IIB+
Figure 28. Output Offset Voltage Model
SLOS289E − DECEMBER 1999 − REVISED SEPTEMBER 2006
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
_
+
Rnull
RLCL
Figure 29
general power design considerations
When driving heavy loads at high junction temperatures there is an increased probability of electromigration
affecting the long term reliability of ICs. Therefore for this not to be an issue either:
DThe output current must be limited (at these high junction temperatures).
or
DThe junction temperature must be limited.
The maximum continuous output current at a die temperature 150°C will be 1/3 of the current at 105°C.
The junction temperature will be dependent on the ambient temperature around the IC, thermal impedance from
the die to the ambient and power dissipated within the IC.
TJ = TA + θJA × PDIS
Where:
PDIS is the IC power dissipation and is equal to the output current multiplied by the voltage dropped across the
output of the IC.
θJA is the thermal impedance between the junction and the ambient temperature of the IC.
TJ is the junction temperature.
TA is the ambient temperature.
Reducing one or more of these factors results in a reduced die temperature. The 8-pin SOIC (small outline
integrated circuit) has a thermal impedance from junction to ambient of 176°C/W. For this reason it is
recommended that the maximum power dissipation of the 8-pin SOIC package be limited to 350 m W, with peak
dissipation of 700 mW as long as the RMS value is less than 350 mW.
The use of the MSOP PowerPAD dramatically reduces the thermal impedance from junction to case. And with
correct mounting, the reduced thermal impedance greatly increases the IC’ s permissible power dissipation and
output current handling capability. For example, the power dissipation of the PowerPAD is increased to above
1 W. Sinusoidal and pulse-width modulated output signals also increase the output current capability. The
equivalent dc current is proportional to the square-root of the duty cycle:
IDC(EQ) +ICont (duty cycle)
Ǹ
CURRENT DUTY CYCLE
AT PEAK RATED CURRENT EQUIVALENT DC CURRENT
AS A PERCENTAGE OF PEAK
100 100
70 84
50 71
Note that with an operational amplifier, a duty cycle of 70% would often result in the op amp sourcing current
70% of the time and sinking current 30%, therefore, the equivalent dc current would still be 0.84 times the
continuous current rating at a particular junction temperature.
SLOS289E − DECEMBER 1999 − REVISED SEPTEMBER 2006
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
general PowerPAD design considerations
The TLV411x is available in a thermally-enhanced PowerPAD family of packages. These packages are
constructed using a downset leadframe upon which the die is mounted [see Figure 30(a) and Figure 30(b)]. This
arrangement results in the lead frame being exposed as a thermal pad on the underside of the package [see
Figure 30(c)]. Because this thermal pad has direct thermal contact with the die, excellent thermal performance
can be achieved by providing a good thermal path away from the thermal pad.
The PowerPAD package allows for both assembly and thermal management in one manufacturing operation.
During the surface-mount solder operation (when the leads are being soldered), the thermal pad must be
soldered to a copper area underneath the package. Through the use of thermal paths within this copper area,
heat can be conducted away from the package into either a ground plane or other heat dissipating device.
Soldering the PowerPAD to the PCB is always recommended, even with applications that have low-power
dissipation. This provides the necessary thermal and mechanical connection between the lead frame die pad
and the PCB.
The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of
surface mount with mechanical methods of heatsinking.
DIE
Side View (a)
End View (b) Bottom View (c)
DIE
Thermal
Pad
NOTE A: The thermal pad is electrically isolated from all terminals in the package.
Figure 30. Views of Thermally-Enhanced DGN Package
SLOS289E − DECEMBER 1999 − REVISED SEPTEMBER 2006
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
Although there are many ways to properly heatsink the PowerPAD package, the following steps illustrate the
recommended approach.
general PowerPAD design considerations (continued)
1. The thermal pad must be connected to the most negative supply voltage on the device, GND.
2. Prepare the PCB with a top side etch pattern as illustrated in the thermal land pattern mechanical drawings
at the end of this document. There should be etch for the leads as well as etch for the thermal pad.
3. Place five holes in the area of the thermal pad. These holes should be 13 mils in diameter. Keep them small
so that solder wicking through the holes is not a problem during reflow.
4. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. This helps
dissipate the heat generated by the TLV411x IC. These additional vias may be larger than the 13-mil
diameter vias directly under the thermal pad. They can be larger because they are not in the thermal pad
area to be soldered so that wicking is not a problem.
5. Connect all holes to the internal ground plane that is at the same voltage potential as the device GND pin.
6. When connecting these holes to the ground plane, do not use the typical web or spoke via connection
methodology . Web connections have a high thermal resistance connection that is useful for slowing the heat
transfer during soldering operations. This makes the soldering of vias that have plane connections easier.
In this application, however , low thermal resistance is desired for the most efficient heat transfer. Therefore,
the holes under the TLV411x PowerPAD package should make their connection to the internal ground plane
with a complete connection around the entire circumference of the plated-through hole.
7. The top-side solder mask should leave the terminals of the package and the thermal pad area with its five
holes exposed. The bottom-side solder mask should cover the five holes of the thermal pad area. This
prevents solder from being pulled away from the thermal pad area during the reflow process.
8. Apply solder paste to the exposed thermal pad area and all of the IC terminals.
9. With these preparatory steps in place, the TLV41 1 x IC i s simply placed in position and run through the solder
reflow operation as any standard surface-mount component. This results in a part that is properly installed.
For a given θJA, the maximum power dissipation is shown in Figure 31 and is calculated by the following formula:
PD+ǒTMAX–TA
qJA Ǔ
Where: PD= Maximum power dissipation of TLV411x IC (watts)
TMAX= Absolute maximum junction temperature (150°C)
TA= Free-ambient air temperature (°C)
θJA = θJC + θCA
θJC = Thermal coefficient from junction to case
θCA = Thermal coefficient from case to ambient air (°C/W)
SLOS289E − DECEMBER 1999 − REVISED SEPTEMBER 2006
16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
general PowerPAD design considerations (continued)
TJ = 150°C
4
3
2
0
−55 −40 −10 20 35
Maximum Power Dissipation − W
MAXIMUM POWER DISSIPATION
vs
FREE-AIR TEMPERATURE
65 95 125
1
TA − Free-Air Temperature − °C
−25 5 50 80 110
3.5
2.5
1.0
0.5
DGN Package
Low-K Test PCB
θJA = 52.7°C/W
PDIP Package
Low-K Test PCB
θJA = 104°C/W
SOIC Package
Low-K Test PCB
θJA = 176°C/W
NOTE A: Results are with no air flow and using JEDEC Standard Low-K test PCB.
Figure 31. Maximum Power Dissipation vs Free-Air Temperature
The next consideration is the package constraints. The two sources of heat within an amplifier are quiescent
power and output power. The designer should never forget about the quiescent heat generated within the
device, especially multi-amplifier devices. Because these devices have linear output stages (Class A-B), most
of the heat dissipation is at low output voltages with high output currents.
The other key factor when dealing with power dissipation is how the devices are mounted on the PCB. The
PowerPAD devices are extremely useful for heat dissipation. But, the device should always be soldered to a
copper plane to fully use the heat dissipation properties of the PowerPAD. The SOIC package, on the other
hand, is highly dependent on how it is mounted on the PCB. As more trace and copper area is placed around
the device, θJA decreases and the heat dissipation capability increases. The currents and voltages shown in
these graphs are for the total package. For the dual amplifier packages, the sum of the RMS output currents
and voltages should be used to choose the proper package.
SLOS289E − DECEMBER 1999 − REVISED SEPTEMBER 2006
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
macromodel information
Macromodel information provided was derived using Microsim Parts, the model generation software used
with Microsim PSpice. The Boyle macromodel (see Note 3) and subcircuit in Figure 33 are generated using
the TLV411x typical electrical and operating characteristics at TA = 25°C. Using this information, output
simulations of the following key parameters can be generated to a tolerance of 20% (in most cases):
DMaximum positive output voltage swing
DMaximum negative output voltage swing
DSlew rate
DQuiescent power dissipation
DInput bias current
DOpen-loop voltage amplification
DUnity-gain frequency
DCommon-mode rejection ratio
DPhase margin
DDC output resistance
DAC output resistance
DShort-circuit output current limit
NOTE 3: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Integrated Circuit Operational Amplifiers,” IEEE Journal
of Solid-State Circuits, SC-9, 353 (1974).
* TLV4112_5V operational amplifier ”macromodel” subcircuit
* updated using Model Editor release 9.1 on 01/18/00 at 15:50
Model Editor is an OrCAD product.
*
* connections: non−inverting input
* | inverting input
* | | positive power supply
* | | | negative power supply
* | | | | output
* | | | | |
.subckt TLV4112_5V 1 2 3 4 5
*c1 11 12 2.2439E−12
c2 6 7 10.000E−12
css 10 99 454.55E−15
dc 5 53 dy
de 54 5 dy
dlp 90 91 dx
dln 92 90 dx
dp 4 3 dx
egnd 99 0 poly(2) (3,0) (4,0) 0 .5 .5
fb 7 99 poly(5) vb vc ve vlp vln 0
+ 33.395E6 −1E3 1E3 33E6 −33E6
ga 6 0 11 12 168.39E−6
gcm 0 6 10 99 168.39E−12
iss 10 4 dc 13.800E−6
hlim 90 0 vlim 1K
ioff 0 6 dc 75E−9
j1 11 2 10 jx1
J2 12 1 10 jx2
r2 6 9 100.00E3
rd1 3 11 5.9386E3
rd2 3 12 5.9386E3
ro1 8 5 10
ro2 7 99 10
rp 3 4 3.3333E3
rss 10 99 14.493E6
vb 9 0 dc 0
vc 3 53 dc .86795
ve 54 4 dc .86795
vlim 7 8 dc 0
vlp 91 0 dc 300
vln 0 92 dc 300
.model dx D(Is=800.00E−18)
.model dy D(Is=800.00E−18 Rs=1m Cjo=10p)
.model jx1 NJF(Is=150.00E−12 Beta=2.0547E−3 +Vto=−1)
.model jx2 NJF(Is=150.00E−12 Beta=2.0547E−3 + Vto=−1)
.ends
*$
IN− G
D
S
D
S
G
rp
IN+
rd1 rd2 rss egnd fb ro2
ro1
vlim
OUT
ga
ioffgcm
vb
c1
dc
iss
dp
GND
VDD
css
c2
ve de
dlp dln
vlnhlimvlp
10
4
1
11 12
3
53
54
96
8
5
7
91 90 92
vc
99
+
+
+
+
+
+
+
−
−
−
−
−−
−
−+
r2
2
Figure 32. Boyle Macromodel and Subcircuit
PSpice and Parts are trademarks of MicroSim Corporation.
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TLV4110ID ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV4110IDG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV4110IDGNR ACTIVE MSOP-
Power
PAD
DGN 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV4110IDGNRG4 ACTIVE MSOP-
Power
PAD
DGN 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV4110IDR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV4110IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV4110IP ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TLV4110IPE4 ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TLV4111CD ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV4111CDG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV4111CDGN ACTIVE MSOP-
Power
PAD
DGN 8 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV4111CDGNG4 ACTIVE MSOP-
Power
PAD
DGN 8 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV4111ID ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV4111IDG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV4111IDGN ACTIVE MSOP-
Power
PAD
DGN 8 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV4111IDGNG4 ACTIVE MSOP-
Power
PAD
DGN 8 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV4111IDGNR ACTIVE MSOP-
Power
PAD
DGN 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV4111IDGNRG4 ACTIVE MSOP-
Power
PAD
DGN 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV4111IDR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV4111IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV4112CD ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV4112CDG4 ACTIVE SOIC D 8 75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 18-Sep-2008
Addendum-Page 1
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
no Sb/Br)
TLV4112CDGN ACTIVE MSOP-
Power
PAD
DGN 8 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV4112CDGNG4 ACTIVE MSOP-
Power
PAD
DGN 8 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV4112CP ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TLV4112CPE4 ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TLV4112ID ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV4112IDG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV4112IDGN ACTIVE MSOP-
Power
PAD
DGN 8 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV4112IDGNG4 ACTIVE MSOP-
Power
PAD
DGN 8 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV4112IDGNR ACTIVE MSOP-
Power
PAD
DGN 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV4112IDGNRG4 ACTIVE MSOP-
Power
PAD
DGN 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV4112IDR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV4112IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV4112IP ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TLV4112IPE4 ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TLV4113CDGQ ACTIVE MSOP-
Power
PAD
DGQ 10 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV4113CDGQG4 ACTIVE MSOP-
Power
PAD
DGQ 10 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV4113CDGQR ACTIVE MSOP-
Power
PAD
DGQ 10 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV4113CDGQRG4 ACTIVE MSOP-
Power
PAD
DGQ 10 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV4113ID ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV4113IDG4 ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV4113IDGQ ACTIVE MSOP-
Power DGQ 10 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 18-Sep-2008
Addendum-Page 2
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
PAD
TLV4113IDGQG4 ACTIVE MSOP-
Power
PAD
DGQ 10 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV4113IDGQR ACTIVE MSOP-
Power
PAD
DGQ 10 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV4113IDGQRG4 ACTIVE MSOP-
Power
PAD
DGQ 10 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV4113IN ACTIVE PDIP N 14 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TLV4113INE4 ACTIVE PDIP N 14 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLV4113 :
•Enhanced Product: TLV4113-EP
NOTE: Qualified Version Definitions:
•Enhanced Product - Supports Defense, Aerospace and Medical Applications
PACKAGE OPTION ADDENDUM
www.ti.com 18-Sep-2008
Addendum-Page 3
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TLV4110IDGNR MSOP-
Power
PAD
DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TLV4110IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLV4111IDGNR MSOP-
Power
PAD
DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TLV4111IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLV4112IDGNR MSOP-
Power
PAD
DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TLV4112IDGNR MSOP-
Power
PAD
DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TLV4112IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLV4113CDGQR MSOP-
Power
PAD
DGQ 10 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TLV4113IDGQR MSOP-
Power
PAD
DGQ 10 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 12-Dec-2011
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLV4110IDGNR MSOP-PowerPAD DGN 8 2500 358.0 335.0 35.0
TLV4110IDR SOIC D 8 2500 340.5 338.1 20.6
TLV4111IDGNR MSOP-PowerPAD DGN 8 2500 358.0 335.0 35.0
TLV4111IDR SOIC D 8 2500 340.5 338.1 20.6
TLV4112IDGNR MSOP-PowerPAD DGN 8 2500 358.0 335.0 35.0
TLV4112IDGNR MSOP-PowerPAD DGN 8 2500 364.0 364.0 27.0
TLV4112IDR SOIC D 8 2500 340.5 338.1 20.6
TLV4113CDGQR MSOP-PowerPAD DGQ 10 2500 358.0 335.0 35.0
TLV4113IDGQR MSOP-PowerPAD DGQ 10 2500 358.0 335.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 12-Dec-2011
Pack Materials-Page 2
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