Application Report SLUA250 - March 2001 A Power Management Interface Circuit for Telecom Hot Swap with Local DC/DC Conversion Andrew Ripanti Power Distribution and Processing Solutions ABSTRACT Much of the Telecom and Datacom equipment infrastructure operates from a power architecture based on a -48 Vdc distribution bus. This supply level has emerged as a standard and efficient means of distributing power throughout equipment racks, while facilitating alternate source operation from secondary power, such as batteries, when the AC line supply is unavailable. To further improve uptime ratios while meeting the needs of maintenance and reconfiguration, hot swap capability is often incorporated in removable subassembly specification and design. Today, the brains of these communication systems; i.e., microprocessors, DSPs, ASICs, and programmable logic, are evolving to ever-lower operating voltages. Typical integrated circuits run at supply levels of 3.3 V, 2.5 V, and even lower. As this occurs, new devices and modules are being developed to address the functions of hot-swapping the -48 Vdc bus, and subsequent conversion to local regulation levels. These devices provide a high level of integration for the point-of-use power supplies, saving the system designer both design time and critical board space. This application report presents one possible solution to the telecom plug-in power problem, based on a nominal -48 Vdc system bus and a module needing two low-voltage supply outputs. The material includes a detailed design methodology for tailoring the circuit to the specific requirements of the reader's system. The solution is based on two device families offered by Texas Instruments, the UCC3913 and UCC3921 hot swap power manager ICs, and the PT3320 series of integrated switching regulators (ISRs). The document organization is such that some example system requirements are defined, then a step-by-step procedure is presented for determining external component values to set user-programmable features. There is discussion of some optional features. Finally, the circuit operation and performance is further illustrated through scope plots of the circuit's response to various live insertion events, and input and output fault conditions. 1 SLUA250 CONTENTS 1 The Power Transmission Problem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 The Power Management Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 Additional Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4 Performance Evaluation and Sample Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5 Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2 A Power Management Interface Circuit for Telecom Hot Swap with Local DC/DC Conversion SLUA250 1 Introduction 1.1 The Power Transmission Problem Many telecom and datacom systems are configured from subsystem racks and chassis, or boxes, each containing a system host or controller card, one or more power supplies, and various sub-assembly cards performing functions of data processing, data transmission and switching. The interconnect between the different modules is often accomplished with a backplane or motherboard. Power is commonly provided to the various module slots via a -48 Vdc distribution bus. This is an efficient means of supplying power throughout the box for two main reasons: 1. Current bussing requirements are significantly reduced compared to the current levels that would be encountered if power were distributed at the regulation levels of 5.0 V, 3.3 V, or even lower, and 2. System supply voltage droops and spikes of several volts are more easily tolerated by the driven electronics, as significant voltage margin now exists between the power bus and the regulation levels. This configuration, however, creates the need for efficient and cost-effective voltage conversion to the local regulation levels at the points-of-use. The power conversion issue is further complicated when the driven boards are specified to have hot swap or hot plug capability. Simply put, hot swap is the ability to safely insert a module into or remove it from a host system, without first interrupting power to the host. This feature is generally designed in wherever there is a need to replace modules on-the-fly. Such a requirement may be for purposes of repair, reconfiguration, redundancy, or system upgrade. It is also useful in systems with high availability requirements (i.e., high up-time ratios). Finally, hot swap requirements may be included in the target industry specification that is being designed to, such as PCI, Compact PCI, USB, and 1394. Not surprisingly, it has seen significant use in telecom systems. As a highly desirable feature in many applications, hot swap capability also creates several issues that must be addressed in the system design. A number of related phenomena occur with a live insertion or removal event, including contact bounce, arcing between connector pins, and large voltage and current transients. The stresses on the mechanical interface, power supply, and input filter components can produce latent defects leading to intermittent or premature failures. Therefore, a power interface is needed which can safely mitigate these effects. This interface provides protection for both the host and plug-in electronics, data stored or transferred in the system, and any transactions within or between systems. This application note presents one possible solution for hot swapping a -48-Vdc bus, and performing the required DC/DC conversion. The organization is such that the operating parameters are defined, a top-level electrical schematic presented, followed by a detailed procedure for determining component values, description of some optional features, and performance verification. The proposed solution is built around two main device types offered by Texas Instruments (TI). The UCC3921 Hot Swap Power Manager (HSPM) integrated circuit handles the main functions needed for hot swap capability; the conversion is performed using the PT3320 series of integrated switching regulators (ISRs). A Power Management Interface Circuit for Telecom Hot Swap with Local DC/DC Conversion 3 SLUA250 The UCC3921 IC is a floating, negative-voltage hot-swap controller which, in conjunction with an external N-channel FET, provides inrush current limiting, fault timeout, and fault reporting. An on-chip shunt regulator generates the internal supply voltages and the gate drive for the external pass element. Other features include continuous supply current monitoring with electronic circuit breaker, remote enable, and user-programmable duty cycle to limit dissipation in the FET in automatic retry mode. For a complete description of the UCC3921 features and operation, please refer to the device data sheet. The PT3320 is a series of 30-W, isolated DC/DC converter modules designed specifically for 48-V distribution systems. They are complete modules assembled onto a space-saving, PCB-based, vertical- or horizontal-mount SIP package. A wide range of output voltage/current combinations is available from 2 V to 15 V (see Table 1). A wide input voltage operating range (36.0 V to 75.0 V) and high efficiencies make them applicable in numerous distributed power applications. The converters contain an external inhibit function, and remote sense inputs to compensate for any voltage drop from converter output to load. The only external component required for operation is a 330-F electrolytic capacitor. For further information on the full range of 48-V converter products, including the 3-W to 7-W PT4200/4300 and 15-W PT3100 series modules, please visit www.ti.com. Table 1. PT3320 Series of Converters DEVICE NUMBER PT3321 4 OUTPUT VOLTAGE (V) CURRENT (A) 3.3 8 PT3322 5.0 6 PT3323 12.0 2.5 PT3324 15.0 2 PT3325 2.0 8 PT3326 2.5 8 PT3327 1.8 8 PT3328 5.2 6 A Power Management Interface Circuit for Telecom Hot Swap with Local DC/DC Conversion SLUA250 1.2 Design Requirements To illustrate the detailed design steps for using the UCC3921 in a -48 V (or Telecom) system, the following system-level requirements were defined: * Input supply voltage: nominal -48 Vdc, -36 Vdc (min) to -72 Vdc (max) * Output voltage/current: 1.8 Vdc at 6.0 A (max), and 2.5 Vdc at 6.0 A (max) * Isolated outputs * Redundant supply operation (2 sources) * Hot-swap capability * Interface to host ENABLE signal * Fault indication to host * 0_C to 70_C ambient operating temperature * Host VDD supply: 3.3 Vdc A Power Management Interface Circuit for Telecom Hot Swap with Local DC/DC Conversion 5 SLUA250 2 The Power Management Interface 2.1 Electrical Schematic Diagram The electrical schematic for one type of implementation of the power interface specified in the design requirements is shown in Figure 1. Some of the secondary functions are shown here in block form for later discussion. The output voltages are generated from the -48-Vdc input via the PT3326 (2.5 V) and PT3325 (1.8 V) modules[1]. The PT3320 modules are fully isolated, thus eliminating the need for additional transformers. The UCC3921 HSPM resides between the input supply and the VIN pins of the converters. It drives N-channel FET Q1, which switches the low side of the supply (-48 V). The SNS input of the IC monitors the voltage drop across sense resistor R5, so the current load on the 48 V supply is monitored. U2 7 GND 8 9 SD C5 100 F 100 V HOST/ SYSTEM INTERFACE HOST_VDD 2 1 3 UVLO FLT 4 5 6 U1 1 R3 10 k, 1 W 2 3 4 SDFL IMAX VDD CT PL OUT SNS VSS 8 R7 100 k R1 Q2 1.0 M 2N7000 1% +SNS 19 VOUT+ 17 VOUT+ 16 VOUT+ 15 VOUT+ 14 ADJ 18 VOUT- 12 VOUT- 11 VOUT- 10 -SNS 13 +1.8VDC R17 0 C6 330 F 6.3 V PT3325 U3 6 7 5 8 UCC3921 2 C7 100 F 100 V C1 0.1F 1 3 4 C2 1.0F 5 C3 1.0 F VIN- VIN- VIN- 7 9 R2 13 k 1% VIN+ VIN+ VIN+ INH N/C N/C 6 R4 82 k R13 0 VIN+ VIN+ VIN+ INH N/C N/C VIN- VIN- VIN- +SNS 19 VOUT+ 17 VOUT+ 16 VOUT+ 15 VOUT+ 14 ADJ 18 VOUT- 12 VOUT- 11 VOUT- 10 -SNS 13 +2.5VDC C8 330 F 6.3 V LCLRTN PT3326 VIN- F1 D1 3 AG, 2 A MBR3100 -48VDC_N1 F2 D2 3 AG, 2 A MBR3100 -48VDC_N2 R5 0.025 1 W, 1% Q1 IRF530 Figure 1. Top-Level Schematic Diagram for -48 Vdc Hot Swap with DC/DC Conversion 6 A Power Management Interface Circuit for Telecom Hot Swap with Local DC/DC Conversion UDG-00143 SLUA250 Table 2. Hot Swap Power Circuit Signal Descriptions SIGNAL NAME 2.2 DESCRIPTION -48VDC_N1 -48-Vdc input supply no. 1 to the plug-in PCB. -48VDC_N2 -48-Vdc input supply no. 2 to the plug-in PCB. GND Supply common for the two -48 Vdc supplies. This is also intended as the system ground node. HOST_VDD Host or controller VDD node, +3.3 V dc. SD Active low SHUTDOWN input for remote or host control of the module ON/OFF status. FLT Active low FAULT output to the system. +1.8VDC +1.8 V dc power supply output. +2.5VDC +2.5 V dc power supply output. LCLRTN Common local return for the two output supply rails. Detailed Circuit Description The UCC3921 device determines load current levels by monitoring the voltage drop across a low-ohmic value sense resistor, R5, as shown in Figure 1. The device has two distinct current thresholds for defining different modes of operation. The first threshold is the fault current, referred to herein as IFLT. This can be thought of as the circuit breaker trip current. When enabled, and under normal load conditions below the fault current threshold, the UCC3921 OUT pin drives external FET Q1 gate with a nominal 9.5-V source, relative to the VSS node. Q1 is switched on, and completes the low impedance return path from the load (VIN- pins of the ISR's). When the device detects a nominal drop of 50 mV or greater between the SNS and VSS pins, an internal source begins charging an external capacitor connected to the CT pin, essentially generating a time delay before tripping, or opening the supply return path by turning off transistor Q1. However, during this timeout period, the pass FET is still driven as a low-ohmic value switch. If the fault condition is removed prior to timeout, the capacitor is discharged, and supply operation continues uninterrupted. The second threshold is the maximum current that will be sourced to the load by the HSPM circuit, or IMAX. Under heavy overcurrent or short-circuit conditions, the input current to the converter circuit will be clamped at this maximum level. During a live PCB insertion, inrush current caused by charging bulk capacitance (C5 and C7 in Figure 1) will also be limited to this level. The threshold is programmable by using a resistor divider to set the voltage at the U1 IMAX pin. The VDD node provides a ready reference for this divider. In the Figure 1 schematic, this threshold is set by the R1/R2 resistor network. Since the UCC3921 is a current-driven device, it essentially floats from the positive supply input. Resistor R3 sets the biasing supply level for the VDD input. Capacitor C1 provides supply bypassing for U1, and C2, tied to the CT pin, is the timing capacitor. Resistor R7 is an optional component used by the UCC3921 to further limit power dissipation in the pass element, under certain fault conditions, below the limits that are automatically provided by the IC. The detailed procedure for determining component values for the hot swap interface will be shown in Section 2.3, Circuit Design Procedure. For a complete description of the HSPM IC operation and electrical specifications, see the UCC3921 device data sheet. Capacitors C6 and C8 provide the energy storage capability required for proper operation of the PT3320 switcher modules, U2 and U3 respectively. They also provide some output filtering for the DC/DC converters. The 330-F value used is the manufacturer's recommended value. The input capacitors C5 and C7 are used to ensure good power quality to the ISRs. A Power Management Interface Circuit for Telecom Hot Swap with Local DC/DC Conversion 7 SLUA250 Diodes D1 and D2 provide a diode-OR function between the two redundant supply nodes (-48VDC_N1 and -48VDC_N2). If only one supply is present, or if one supply has failed, supply return is still provided by the alternate path. Note that Schottky diodes are used; at least one of these devices is always conducting, so Schottkys are used to minimize the reduction in overall efficiency of the interface. Fuses F1 and F2 provide a one-shot over-current protection in the event of catastrophic failure of the more intelligent protection devices downstream. The PT3320 ISRs feature output short-circuit protection. The UCC3921 features both a programmable current limit, and circuit breaker operation. These provide redundancy to the output protection, and protect against an overcurrent or short-circuit on the primary (VIN) side. Should these devices fail in the right combination, fuses F1 and/or F2 provide a permanent, mechanical interrupt. The block labeled HOST/SYSTEM INTERFACE in Figure 1 is an optional sub-circuit to allow remote ON/OFF control of the plug-in module, and generate a current fault indication back to the host. This block provides the level-translation needed to refer the multifunctional SDFL pin of the UCC3921 to the system common, or GND node. If these features are not needed, implementation of this circuit is not necessary. The block labeled UVLO provides an optional undervoltage lockout (UVLO) function to the startup of the two DC/DC converters. However, the PT3320 regulators incorporate an internal UVLO circuit, the threshold of which is specified to be 33 2.0 Vdc. Since the design specification requires this circuit to operate down to a -36-V supply level, and the maximum ISR UVLO level is just below this voltage, this solution was developed assuming the internal UVLO is to be used. To address a wider range of application requirements, an alternative implementation of an external UVLO circuit is shown in Section 3.3, Optional UVLO Circuit. 2.3 Circuit Design Procedure The following is a sequence of design steps that can be used to determine component values for the configuration circuitry around the hot-swap controller IC. The process takes into consideration the load characteristics, both during startup and under dc operating conditions, and the device parameter specifications. To assist the reader in determining the source and value of the UCC3921-specific variables plugged into the following equations, Appendix I summarizes the key device parameters. 2.3.1 Step 1 - Determine Input Load Current In order to set the fault levels for the HSPM IC, the nominal load current on the input supply must be estimated. Given the operating loads on the two regulated outputs from the design specification, the converter efficiency can be used to estimate the average load on the primary (bus) side. Also, since the PT3320 modules are switching regulators, the peak load is anticipated to occur when the bus potential is at its lowest. From the PT3321 curves shown in the data sheet[2], the efficiency at 6 A for input voltage of 36 V is nearly 80%, decreasing to about 75% at 75 V. Power delivered to the loads, POUT, and subsequently input current to the board, IIN, are estimated from the following equations. P OUT + P O1 ) P O2 + V O1 I LOAD1 ) V O2 I LOAD2 where: 8 A Power Management Interface Circuit for Telecom Hot Swap with Local DC/DC Conversion (1) SLUA250 * VO1 = local regulation level No. 1, +2.5VDC * ILOAD1 = maximum output load on VO1 * VO2 = local regulation level No. 2, +1.8VDC * ILOAD2 = maximum output load on VO2 The input supply current under normal steady-state operation, IIN, can then be estimated from: P I IN + IN + V IN V I IN + O1 h1 P P O1 ) O2 h1 h2 (2) V IN I LOAD1 V IN V ) O2 h2 I LOAD2 (3) V IN where: * PIN = input power delivered to the board * 1, 2 = respective converter efficiencies for outputs 1 and 2 * VIN = the input supply voltage level For reasons detailed in Section 2.3.5, the designer must determine the maximum input current at each of the input voltage extremes. Therefore, two maximum current levels need to be calculated. Defining IIN(max) as the supply current when the bus is at its lowest potential, and IIN(max ) as the supply current when the bus is at its highest potential, then substituting the values from the requirements specification, the input current levels shown in equations 4 and 5 are obtained. Note that equations 4 and 5 are a simplification of equation 3 when the converters are anticipated to be operating at virtually equivalent efficiency points. I IN(max) + I IN(max) + VO1 I LOAD1 ) V O2 h 36 [(2.5 V I LOAD2 (4) V IN(min) 6.0 A) ) (1.8 V (0.8 36 V) 6.0 A)] or I IN(max) + 0.896 A and I IN(max) + I IN(max) + VO1 I LOAD1 ) V O2 h 75 [(2.5 V I LOAD2 (5) V IN(max) 6.0 A) ) (1.8 V (0.75 72 V) 6.0 A)] or I IN(max) + 0.478 A A Power Management Interface Circuit for Telecom Hot Swap with Local DC/DC Conversion 9 SLUA250 These estimates were made considering the dc or average-output currents. For the PT3320 series, the input ripple current is typically less than 0.25 A peak. This is added to the average values to get an approximation of the peak input current under normal operating conditions, to ensure that the HSPM does not trigger due to expected input ripple. The results (rounded to the nearest 10 mA) are: I IN(max) ^ 1.15 A I IN(max) ^ 0.730 A 2.3.2 Step 2 - Set Fault Current Level And Determine Sense Resistor Value The fault current level for the hot swap interface circuit must be selected. This is established by the value of the sense resistor, R5 in the Figure 1 schematic. Since the nominal overcurrent threshold of the UCC3921 is 50 mV, the resistor value can be determined from equation 6. V R5 + FLT + 50 mV + 25 mW I FLT 2.0 A (6) Selecting a nominal fault threshold of 2.0 A provides nearly 100% margin over the anticipated peak operating levels. Some design margin is desirable to provide headroom for any transient peaks on the output supplies, tolerances on the converter efficiency from unit-to-unit, transients on the -48-V supply bus that cause surges in input current, and as an overall guard against nuisance trips. Using the UCC3921 specification values for the overcurrent threshold, and with the sense resistor value fixed, the minimum and maximum current fault levels can be verified using equations 7 and 8. I FLT(min) + I FLT(max) + V FLT(min) R5 + 1.84 A V FLT(max) R5 + 2.14 A (7) (8) where : * VFLT(min) = minimum fault (overcurrent) threshold * VFLT(max) = maximum fault threshold The calculated minimum value, 1.84 A, demonstrates that significant margin is available even with a device at the low end of its specification limit. 10 A Power Management Interface Circuit for Telecom Hot Swap with Local DC/DC Conversion SLUA250 2.3.3 Step 3 - Set IMAX Threshold And Determine IMAX Divider Values The maximum sourcing current level of the hot swap circuit, herein referred to as IMAX, is user programmable, using the IMAX input pin of U1. In an effort to predict performance under worst-case parameter conditions, it is recommended to establish the lower threshold for this maximum sourcing capability, or IMAXMIN. Generally, this will correspond to the IMAX level for a device with a regulator output (VDD) at the specification minimum voltage, taking into account two other sources of variance, the input offset voltage and bias current of the internal linear current amplifier (LCA). For proper device operation, this value should be greater than the calculated maximum fault current, IFLT(max). If a relatively fast rate of input current slewing is allowed, or a large amount of bulk capacitance exists at the input to the plug-in, the IMAX feature can be used to accomplish faster charging of the load capacitance, thus minimizing the startup transient duration. However, if the distribution supply has a slow transient response, minimal output capacitance, or is required to operate near peak capability at the expected system steady-state load, the IMAX level should be selected with these limitations in mind. In addition, under a short-circuit situation, the load current of the affected module(s) will make a step change to this level. For this example, a minimum sourcing level of 4.0 A is used. Figure 2 is a simplified model of the UCC3921 operation when the sense voltage, VSNS, is above the IMAX threshold. During inrush or short-circuit conditions, the HSPM device acts to control the gate of Q1 such that it appears as a constant-current source. The internal LCA will respond to maintain the VSNS node equal to the IMAX reference, (i.e., the drop across the sense resistor equal to the drop across R2.) Therefore, an equation for the sense voltage is generated by writing the loop equation at the linear current amplifier (LCA) inputs (equation 9). VDD R1 3 IBIAS VIMAX 2 LINEAR CURRENT AMPLIFIER + VOS OUTPUT 7 6 5 R2 UCC3921 VSNS RSNS UDG-00141 Figure 2. Model of UCC3921 Linear-Mode Operation A Power Management Interface Circuit for Telecom Hot Swap with Local DC/DC Conversion 11 SLUA250 V SNS + V IMAX * V BIAS " V OS (9) where: * VSNS = the drop across the sense element * VIMAX = the voltage at the 3921 IMAX input pin * VBIAS = the error component developed by the IMAX bias current * VOS = the input offset of the internal LCA Also from Figure 2, the VIMAX DC voltage is given by the R1/R2 divider equation. V IMAX + R2 R1 ) R2 (10) V REF where: * VREF = the internal shunt regulator output, VDD Considering that the bias current flow is into the IMAX pin, the smallest error contribution occurs for a device with negligible bias current, which is approximated here to zero. Then, a special case of equation 9 for the minimum sense voltage in linear mode, is given by equation 11. V SNS(min) + V IMAX(min) * V OS (11) Given that VSNS(min) = IMAXMIN x R5, combining equations 10 and 11, and solving for R2 in terms of R1, yields: R2 + IMAXMIN R5 ) V OS VREF(min) * IMAXMIN R5 * V OS R1 (12) The value for R1 can be set to limit the overall current draw of the divider net; if R1 is set to 1 M, equation 12 then becomes: R2 + (4.0 0.025) ) 15 mV [9.0 * (4.0 0.025) * 15 mV] 1.0 MW or R2 + 12.94 kW The standard 1% value of 13 k was selected for R2. 12 A Power Management Interface Circuit for Telecom Hot Swap with Local DC/DC Conversion (13) SLUA250 With values now selected for resistors R1 and R2, the actual minimum and maximum sourcing current levels is predictable. These values are useful for determining the startup time (ramp-up from 0 V to the dc input level) under different conditions. Equations 14 and 15 are obtained by manipulating equation 12. For the IMAXMAX value, the error contribution from the bias current is included. IMAX MIN + R2 R1)R2 IMAX MAX + 2.3.4 R2 R1)R2 V REF(min) * V OS + 4.02 A R5 V REF(max) ) V OS ) V BIAS + 6.07 A R5 (14) (15) Step 4 - Soft-Start Programming The UCC3921 is easily configured for optional soft-start operation. Without soft-start, when a plug-in is inserted into a live socket, the resultant inrush makes a step change to the IMAX limit, where it becomes clamped for the duration of the transient period. Soft-start operation provides an inrush slew rate control, such that the load charging current is gradually ramped, potentially to the maximum value established by the IMAX pin programming resistors. Soft-start is selectable by installing a capacitor in parallel with the IMAX programming resistor (shown in Figure 1 as capacitor C3.) The feature operates by putting an RC time constant on the voltage ramp at the IMAX pin when the power manager is started. This forces the device to operate in linear mode immediately from Q1 turnon, essentially producing a dynamic IMAX function. For a UVLO-protected load, such as presented by the two ISRs in this solution, the startup voltage ramp to the converter inputs will have two stages. During the first stage of rampup, from turnon until achieving the UVLO threshold, the load appears virtually capacitive to the charging source. This capacitance, CLOAD, is the equivalent capacitance of the input filter capacitors, the converter input capacitance, and any parasitics. Wherever this quantity is used in this document to derive other values, it is approximated as the 200-F value of C5 and C7. For a constant-current source of value IMAX (i.e., no soft-start), the voltage at the converter inputs during this stage, for a charging time of t, is given by equation 16. n INU1(t) + IMAX t C LOAD (16) Once the load charges to the UVLO threshold, VUV, the ISRs are allowed to start up. During this second stage of the voltage ramp, the load capacitance is charged by the sourcing current in excess of the ISR startup load, iL(t). This portion of the ramp-up curve is given by: n INA1(t) + IMAX * iL(t) t * tVUV C LOAD ) V UV A Power Management Interface Circuit for Telecom Hot Swap with Local DC/DC Conversion (17) 13 SLUA250 where: * iL(t) = load startup current * VUV = the UVLO threshold voltage * tVUV = the time to charge the input from 0 V to VUV, from equation 16 When soft-start programming is used, both the input voltage and current waveforms are of interest. Due to the control action of the U1 LCA described above in step 3, we know that the sense voltage tracks the R2 voltage during rampup, which is now the voltage across capacitor C3. Since the output current of the HSPM circuit can be determined from the drop across R5, the following equation for input current to the load is derived: i IN(t) + IMAX *t T 1 * e SS (18) where: * iIN(t) = the charging load on the -48-Vdc supply * SS = the soft-start time constant, given by SS = R2 x C3, in seconds. Since the capacitor charging current is given by equation 18 under this condition, the input voltage profile has an exponential term also. The first stage of the input rampup, prior to startup of the ISRs, is defined by equation 19. n INU(t) + T SS IMAX C LOAD T*t t SS e ) * 1 T SS (19) where: * SS = the soft-start time constant Different criteria may be used for establishing the target slew rate of the hot swap circuit on powerup. However, one overriding requirement is that the input current must be allowed to attain a minimum value prior to the voltage across the input capacitance achieving the UVLO threshold. This minimum level is the current that is demanded by the load. In this case, it is the startup current of the two converters. If the minimum current is not obtained, the active load will begin discharging the input capacitance (C5 and C7 in this case). Some amount of voltage droop may be tolerated by the load, but that is dictated by the complexity and hysteresis of the UVLO circuitry. As a general guideline, be sure to provide sufficient current to avoid any voltage droop. This target current, or set current, is referred to as ISET in the following paragraphs. To simplify what easily becomes a complicated math exercise, assume that the load startup current is constant, or iL(t) = IL. To further simplify, assume that this constant value is in fact the value previously calculated for the peak operating current, or IIN(max). For this example, the minimum current required at load startup, ISET, is set to 5% over this value, or I SET + 1.05 14 I IN(max) + 1.208 A A Power Management Interface Circuit for Telecom Hot Swap with Local DC/DC Conversion (20) SLUA250 Given the voltage ramp profile of equation 19, what is the value of C3 which will ramp the input current to at least ISET by the time the voltage reaches the UVLO threshold? By solving equation 18 for the time t when iIN(t) = ISET, plugging this expression into Eq. 19, and solving for the C3 term, equation 21 is derived. C3 + R2 C * V UV I SET ) IMAX LOAD n I 1 * SET IMAX (21) Examination of equation 18 reveals that the slowest current ramp occurs under minimum sourcing conditions. Substituting IMAXMIN for IMAX in equation 21, and using the minimum specified UVLO threshold (31 V), yields C3 = 2.09 F. Because of the criteria used to establish equation 21, the 2.09-F value represents essentially the maximum size capacitor that should be used in this solution. To demonstrate an alternative, assume that a maximum slew rate requirement of 0.5 A per msec is included in the design specification. The value of the soft-start capacitor, C3, for a given slew rate can be found by taking the derivative of the input current during the startup voltage ramp, given by equation 18. The result is equation 22 . di + IMAX dt T SS e *t T SS (22) Setting di/dt for t = 0 to the maximum slew rate spec, and substituting IMAXMAX for IMAX yields: C3 + R2 IMAX MAX didt) MAX + 0.934 mF (23) As shown in the schematic, a value of 1.0 F was used. 2.3.5 Step 5 - Estimating Ramp TIme The minimum delay to a fault timeout must be long enough to allow charging of the input capacitance at startup. Therefore, an estimate of the total voltage ramp time at module startup is needed. An empirical approach can be taken by bench-testing the interface circuit with the load connected, and measuring the time for the converter input voltage to ramp to the DC input potential. To do this, the fault timer can be defeated by temporarily installing a resistor with a value 1 k in place of capacitor C2. Alternatively, the analysis detailed in this section can be used to better predict the worst-case timing. For the analysis, two possible scenarios exist. 1. Either soft-start is not used, or soft-start reset switch Q2 is not used. For this case, the output voltage equations 16 and 17 apply. 2. Output soft-start is used. The required delay is given by the tCTSS calculation shown in the discussion after Figure 5. For case 1, the HSPM IC operates in fault mode immediately from turn-on, and the minimum delay needed is the total start time. This is given by equations 24 and 25. A Power Management Interface Circuit for Telecom Hot Swap with Local DC/DC Conversion 15 SLUA250 t CT + t ST1X + C LOAD nINA1(t) * VUV IMAX MIN * I L (24) ) t VUVX where: t VUVX + VUV * 0 C LOAD (25) IMAX MIN Solve tCT for VINA1(t) = VIN(max) and VUV = VUV(min). For case 2, soft-start, equation 19 determines the time required to reach the UVLO threshold, designated here as tVUV. Through repeated sampling of the voltage equation, the following values were determined: * tVUVX = 6.89 ms, the time for VIN(t) to reach VUV when IMAX = IMAXMIN * tVUVM = 5.51 ms, the time for VIN(t) to reach VUV when IMAX = IMAXMAX To approximate the worst case startup time, the minimum UVLO threshold of the converters, 31 V, was used as the target voltage level. Due to the tedious nature of sampling the voltage waveforms at different times, it may be useful to create a spreadsheet or use some other software tool to generate a table of values while sweeping the time variable. At time t = tVUV, the load starts up. This defines the transition point between the two equations for the input profile. The second stage of the ramp-up, from VIN(t) = VUV to the dc input level, is given by: n INA(t) + IMAX T SS (26) C LOAD ) IMAX * iL(t) e *t T SS T SS *IMAX t e *t ) IMAX * iL(t) VUV T SS T SS ) t VUV n INUt VUV Figures 3 through 5 show a graphic representation of the input current and voltage waveforms during the transient ramp-up. Plots were produced for sourcing current limit, IMAX, at the nominal, minimum and maximum levels. 16 A Power Management Interface Circuit for Telecom Hot Swap with Local DC/DC Conversion SLUA250 3.0 0 0 3.0 2.5 VNOM(t) -10 2.5 -10 2.0 -20 1.5 -30 1.0 -40 VMAX(t) 2.0 -20 1.5 -30 1.0 -40 0.5 -50 -50 0.5 IMAX(t) INOM(t) 0.0 -60 0 2 4 6 8 t - Time - ms 10 -60 0.0 12 0 2 4 6 8 10 12 t - Time - ms Figure 4. ISR Input Voltage and Current - IMAXNOM Condition Figure 3. ISR Input Voltage and Current - IMAXMAX Condition 3.0 0 2.5 -10 2.0 -20 VMIN(t) 1.5 -30 1.0 -40 -50 0.5 IMIN(t) -60 0.0 0 2 4 6 8 10 12 t - Time - ms Figure 5. ISR Input Voltage and Current - IMAXMIN Condition The selection of a minimum value for the fault timing capacitor, C2, is described in more detail in Section 2.3.7. Since input current greater than the fault level may occur during the turn-on transient, the time delay generated by C2 must be sufficient to allow charging of the input capacitance after plug-in insertion or remote turn on. Therefore, the total duration of the turn-on transient must be known. However, the internal fault timer is not started until the current fault threshold is crossed, so the time for charging current to ramp to the minimum (i.e., worst-case) fault threshold must also be determined. Ultimately, it is the maximum time difference, for a given IMAX value, from fault threshold to the total startup time, which dictates the value of C2. A Power Management Interface Circuit for Telecom Hot Swap with Local DC/DC Conversion 17 SLUA250 Inspection of equation 18 for iIN(t) indicates that the current ramp is independent of the supply voltage, but is directly proportional to the IMAX level of the particular module. So the extremes of the fault timing are determined by rewriting equation 18 to determine the time to reach the IFLT(min) under both the IMAXMIN and IMAXMAX conditions. t FLT + * R2 C3 n 1 * I FLT(min) IMAX (27) and * tFLT(min) = 4.695 ms, the fault time when IMAX = IMAXMAX * tFLT(max) = 7.956 ms, the fault time when IMAX = IMAXMIN These values were calculated with the 1.84 A minimum fault current determined in Section 2.3.2. The total duration of the ramp time must also be estimated. From the startup plots of Figures 3 through 5, it is almost intuitive that this value not only depends on the IMAX tolerance, but is also a function of the UVLO threshold and the input supply level. These voltage curves show that an earlier load turn-on, and a higher voltage to charge to extend the total voltage ramp time. Therefore, in order to use equation 26 to determine the total startup times (tSTM and tSTX), some definitions are needed. First, the worst-case start time calculations should be performed for the maximum input potential, in this case, -72 Vdc. Secondly, the load is assumed to be a constant at the peak input current. But since the bus potential is at its maximum, the current calculated for a -72 Vdc input will be used, or iL(t) = IIN(max ). Lastly, we will define a target DC voltage to be 100mV below the input DC level, or 71.9 V. By sampling equation 26, first setting tVUV = tVUVM while IMAX = IMAXMAX, then for tVUV = tVUVX when IMAX = IMAXMIN, the following startup times were determined: For t = 12.78 ms, VINA(t) = 71.846 V (tSTX; IMAXMIN condition) For t = 9.72 ms, VINA(t) = 71.892 V (tSTM; IMAXMAX condition) The maximum time delay needed to guarantee hot-swap startup when using soft-start, tCTSS, is calculated as: tCTSS = MAX[ (tSTX - tFLT(MAX)), ( tSTM - tFLT(MIN)) ] = 9.72 ms - 4.695 ms = 5.025 ms It is interesting to note that, at least for this solution, the maximum timeout needed occurs under the IMAXMAX condition. Consider one final point regarding soft-start operation. Once capacitor C3 has charged up to its dc level, it will remain charged as long as the board is powered. This means that soft-start operation occurs only at insertion, and is disabled under any other conditions of turn-on, including restart under the fault retry mode of operation, and also from a remote enable using the SD input. Transistor Q2 is added to the circuit to provide a discharge path for C3 whenever the output is turned off. The gate of Q2 is driven by the SDFL node, so that Q2 is turned on whenever U1 asserts the fault output, or SDFL is pulled high externally. The soft-start reset action of Q2 ensures that the HSPM soft-starts each time the output is turned on. 18 A Power Management Interface Circuit for Telecom Hot Swap with Local DC/DC Conversion SLUA250 2.3.6 Step 6 - Set Average Power Limiting For Pass Fet; Determine Power Limiting Resistor Value, R7 The UCC3921 can be configured for either of the two modes of operation during fault conditions, latched mode or retry mode. In retry mode, the device periodically turns on the FET switch Q1 and checks for continued fault conditions. Timing control of this mode is automatically provided by the device. During retry operation, U1 alternately charges C2 with a nominal 36-A internal constant-current source while Q1 is on, then discharges C2 at a nominal 1 A while the output is off. This provides a nominal 2.7% duty cycle. To select retry mode, resistor R4 in the Figure 1 schematic would not be used (left open). In latched mode, once a fault condition times out, the device latches off the pass element. In order to restart the output, either the SDFL pin must be pulled to the shutdown level for > 1 ms, or device power must be cycled. To select latched operation, install resistor R4 as shown. In this mode, the need for power dissipation limiting is essentially negated; therefore, R7 would not be installed. When using the retry feature of the UCC3921, care must be taken not to exceed the dissipation capability of the FET switch. Under normal (non-fault) operating conditions, the FET is fully enhanced by the gate drive, and dissipation in the device is relatively low, assuming an appropriate device has been selected for the application parameters. However, under short-circuit conditions, the full-input potential appears across Q1 while it is on. The power limit function gives the user a means of externally limiting the duty cycle of the external FET switching, further reducing it below the nominal 2.7% level. This is done by sensing the output voltage level, and providing additional charging current for the timing capacitor, through a high-value resistor, based on the output level relative to the VSS node of the device, (i.e., the voltage drop across the FET switch.) The total current now available for charging the timing capacitor, IQ, is now given by equation 28. I Q + I q ) I PL (28) where: * Iq = the device internal charging source, 36-A nominal * IPL = the current through the power limiting resistor In Figure 1, R7, connected to the drain of Q1, is the power limiting resistor. The IRF630 FET selected for this solution comes in the TO-220AB package, rated for a 62_C/W thermal resistance, junction to ambient. Maximum operating junction temperature is specified as 150_C. For the 70_C ambient operating temperature specified in Section 1.2, the average dissipation in Q1 will be limited to 1.0 W as a conservative level. The maximum allowable duty cycle, D, can then be derived from equation 29: D+ P D(avg) IMAX MAX V IN(max) [ 0.23% (29) Since this is significantly less than the HSPM guaranteed maximum of 3.7%, the power limiting function will be used. Because 1/D >> 1, a good approximation of the timing capacitor charge-current contribution required through R7 (IPL in equation 28) is obtained from equation 30: A Power Management Interface Circuit for Telecom Hot Swap with Local DC/DC Conversion 19 SLUA250 I PL + I dq(max) D (30) * I q(min) where: * Idq(MAX) = maximum capacitor discharge current into the U1 CT pin * Iq(MIN) = the minimum charging current sourced from CT Substituting the values from the UCC3921 data sheet for Idq(max) and Iq(min) ,the required power limiting current is determined to be about 634 A. The value of R7 is then found from equation 31: V * V PLIM R7 + IN I PL (31) The obvious worst-case dissipation in the FET occurs when input voltage and drain output current are at their maximum. Therefore, the value of 72 V is substituted for VIN, and the calculated value for R7 is: R7 + 72 V * 5.0 V + 105.7 kW 634 mA (32) A standard 5% value suffices for this function. R7 is set to 100 k. 2.3.7 Step 7 - Determine value for fault timing capacitor C2 The power-limiting current required, and subsequently the value of R7, are determined under worst-case dissipation conditions (e.g., a short-circuit across the input capacitors). However, during a normal startup voltage ramp, input voltage to the ISRs is not shorted, but ramps up according to the appropriate equations. Therefore, the timing current IPL is not a constant under these conditions, but decreases over the period of the input ramp from a maximum value of VIN * VPLIM . R7 Approximating the input transient as a linear ramp, the average current through R7 is estimated from equation 33. I PL(avg) + VDC * VPLIM 2 R7 + VIN(max) * VPLIM 2 (33) R7 Therefore, the minimum value of capacitor C2 needed to ensure startup of the output is: C2 + I q(max) ) I PL(avg) t CT (34) dV CT where: 20 * Iq(max) = maximum charging current sourced from CT * tCT = required fault time delay * dVCT = the delta-V that must be developed across C2 for the UCC3921 to detect a fault A Power Management Interface Circuit for Telecom Hot Swap with Local DC/DC Conversion SLUA250 From the device data sheet, the minimum fault threshold at the CT input pin is given as 2.20 V, and the maximum level for fault reset is 0.57 V. However, for latched mode of operation, only the initial fault timeout is of concern, in which case the voltage at CT is ramping up from 0 V. This allows selection of a slightly smaller value for C2 than if retry mode is used, as shown in equations 35 and 36. For retry mode: C2 + I q(max) ) I PL(avg) t CT VLS * VLR (35) where: * * VLS = the internal fault latch SET threshold VLR = the internal fault latch RESET threshold For latched mode: C2 + I q(max) ) I PL(avg) t CT (36) V LS Since the proposed solution makes use of input current slewing, the tCTSS value calculated in Section 2.3.5 Step 5 - Estimating Ramp TIme is used. Substituting tCT = tCTSS 5 ms, the calculated value of C2 is about 0.88 F, and a standard value of 1.0 F was used in the solution. 2.3.8 Step 8. Set resistor R3 value Resistor R3 is the supply biasing resistor for the UCC3921. The maximum supply current required by the HSPM IC to maintain the internal-shunt-regulator voltage within the data sheet specifications is 2.0 mA. A value of 2.5 mA was used in the development of this solution to provide some margin and bias the IMAX divider network when the supply voltage is at its minimum potential. To provide this minimum bias current, the value of R3 is defined by: R3 + VIN * VREF (37) 0.0025 So, the maximum allowable value of R3 is provided by: VIN(min) * VREF(max) (38) + 36 V * 10.15 V ^ 10 kW 0.0025 0.0025 A At maximum bus potential conditions (-72 V), about 6.64 mA of current could flow through R3 (assuming a 5% tolerance resistor); which is well below the specification maximum of 50 mA. Also, this corresponds to a maximum power dissipation of about 420 mW; therefore, a 1-W-rated resistor is used in this application. R3 + 3 Additional Features The design of the basic power management interface is now complete. The main functions of hot swapping the -48-Vdc input and converting it to local VDD levels is accomplished through the circuitry described previously. However, there are some additional features which can be easily implemented. Two of these functions, which see frequent usage in power management, are presented in the following sections. First, this report describes a host interface to provide a remote shutdown/enable input (SD) and fault indication to the system. Secondly, an inexpensive circuit is shown for shifting the UVLO threshold of the PT332x module. A Power Management Interface Circuit for Telecom Hot Swap with Local DC/DC Conversion 21 SLUA250 3.1 Host Interface to SDFL Pin Pin 1 of the UCC3921 is a three-function pin. The use of a resistive pull-down at this pin to select the fault mode of operation is described in Section 2.3.6, Step 6 -Set Average Power Limiting For Pass Fet; Determine Power Limiting Resistor Value, R7. This pin is also an active-high input for turning off the external FET (shutdown), and provides an output fault indication. However, the signal levels at this pin are referred to the VSS node of the circuit (i.e., the VSS pin of U1). An interface circuit is needed to translate these signals to a system ground reference, and generate the FLT output and the SD input, as shown in the top level schematic. Figure 6 is the Figure 1 diagram redrawn to show the details of one interface implementation. GND U2 SD R10 10 k HOST_VDD R8 10 k 7 R12 62 k 8 9 D3 1N4148 1 C5 100 F 100 V FLT Q4 ZTX553 R9 120 k R11 270 k Q5 ZVN3310A U1 1 2 SDFL IMAX 3 R3 10 k, 1 W 2 UVLO Q3 ZVP3310A VDD 4 CT 8 3 4 VIN- 5 VIN- 6 VIN- R7 100 k PL 7 OUT 6 SNS 5 VSS C3 1.0 F 19 +1.8VDC 17 16 15 14 R17 0 C6 330 F 6.3 V 18 12 11 10 13 U3 7 8 UCC3921 2 C7 100 F 100 V C1 0.1F C2 1.0 F R2 13 k 1% +SNS VOUT+ VOUT+ VOUT+ VOUT+ ADJ VOUT- VOUT- VOUT- -SNS PT3325 9 R1 Q2 1.0 M 2N7000 1% VIN+ VIN+ VIN+ INH N/C N/C 1 3 4 VIN+ VIN+ VIN+ INH N/C N/C VIN- 5 VIN- 6 VIN- R4 82 k R13 0 +SNS VOUT+ VOUT+ VOUT+ VOUT+ ADJ VOUT- VOUT- VOUT- -SNS 19 +2.5VDC 17 16 15 14 18 12 C8 330 F 6.3 V LCLRTN 11 10 13 PT3326 VIN- F1 3 AG, 2 A D1 MBR3100 F2 3 AG, 2 A D2 MBR3100 -48VDC_N1 -48VDC_N2 R5 0.025 1 W, 1% Q1 IRF530 UDG-00143 Figure 6. Schematic Diagram with Host Interface Details The FAULT output translation is comprised of the circuit of R8, R9 and Q5. Under normal operating conditions, U1 sinks a nominal 100 A at pin 1. This keeps the gate of Q5 discharged. With Q5 turned off, R8 applies a pull-up to the HOST_VDD potential at the FLT output, indicating normal operation. During any condition that causes the HSPM device to turn off the gate drive to the FET Q1, the SDFL output attempts to drive to the UCC3921 VDD rail. Device Q5 turns on, and R8 and R9 form a divider on the HOST_VDD to VSS potential. From the divider equation for the fault signal level, the following equation for R9 is derived. R9 + 22 V FLT# HVDD * VSS * VFLT# R8 A Power Management Interface Circuit for Telecom Hot Swap with Local DC/DC Conversion (39) SLUA250 where: * VFLT# = the voltage level of the FLT signal line * HVDD = the voltage level of the system HOST_VDD supply * VSS = the VSS node potential of the plug-in module If the maximum assertion level of FLT, VFLT#(max), is defined to be 0.5 V maximum, then: V FLT#(max) + 0.5 V + 0.5 V * * V SS(min) + 36.2 V , (40) when referenced to the module VSS node, and allowing for about a 300-mV drop across the Schottkys and fuses when the load is not powered. For this condition, the maximum value that should be used in the R9 position is given by equation 41. R9(max) + V FLT#(max) HVDD * VSS(min) * VFLT#(max) R8 (41) Substituting the system values into equation 41, and setting R8 to a nominal 10 k, the resulting R9 value is: R9 + 36.2 V [3.3 V * (* 35.7 V) * 36.2 V] 10 kW ^ 129 kW (42) The next lowest 5% value of 120 k was used for R9. Now, the minimum voltage level for fault assertion can be determined from: V FLT#(min) + + R9 (R8 ) R9) kW 120 130 kW HVDD * VSS(max) ) VSS(max) (43) (3.3 V ) 72 V) * 72V ^ * 2.5V Due to the possibly large signal level below the host or system ground potential, small-signal diode D3 is used as shown in the schematic to clamp the assertion level at about 0.5 V below the GND node. The interface block of circuitry must also provide level-shift of the host shutdown or enable input, SD in the schematic. A brief description of the circuit operation follows. To turn on the HSPM output, the SD input is pulled high by the host controller. Since the Q3 gate is tied to the system GND node, Q3 turns on and provides a strong pull-up on the base of transistor Q4, above the emitter potential. With Q4 off, the internal pull-down at U1 pin 1 is dominant, and the output pulls to a low state. This enables the hot swap controller to turn on the pass FET Q1. When shutdown is asserted (SD pulls low), FET Q3 turns off. Resistor R11 can now pull the Q4 base towards VSS, and Q4 turns on. Q4 now sources sufficient current from the GND potential to overcome the internal pull-down, pulling pin 1 above the shutdown input threshold. The HSPM IC subsequently turns off Q1. A Power Management Interface Circuit for Telecom Hot Swap with Local DC/DC Conversion 23 SLUA250 The use of the two-transistor (Q3/Q4) level shifter as shown in figure 6 provides an additional feature. If at some point the host VDD supply fails while the controlled module is plugged in, the module outputs will be automatically disabled via the HSPM circuit. Loss of the host supply would mean loss of the SD drive to the Q3 source, turning off P-FET Q3. Since the Q4 emitter is tied to the GND node, as opposed to a backplane-side input signal, Q4 is still able to source shutdown current into the SDFL pin. A quick methodology is given here to determine recommended values for resistors R11 and R12. Per the device specification, the SDFL input has a maximum shutdown threshold of (VDD + 1) V. In addition, this pin may sink a maximum of 250 A. Therefore, R11 and R12 must be selected to ensure that PNP transistor Q4 can source a minimum of 250 A while pulling the pin high. Under minimum input supply conditions, the drop across limiting resistor R12 is given by: V R12(min) + * V SS(min) * V EC(max) * V SD(max) (44) Set up this level translator to keep Q4 in saturation under minimum supply conditions. For the ZTX553 transistor, the maximum VCE is specified as -250 mV at a gain of 10. The drop across R12 is: V R12(min) + 35.5 V * 0.25 V * 11 V + 24.25 V (45) Under the same conditions the current consumed by latching resistor R4 is V I R4(max) + SD(max) ^ 141 mA (assuming a 5% tolerance resistor is used). Therefore, the R4 MIN maximum value of R12 that can ensure shutdown control is determined by equation 46. R12(max) + V R12(min) IR4(max) ) ISD(max) + 62 kW (46) The drive current that will be needed, and the value for R11 to provide that current can be found from the following. I B(Q4) u V R12(min) [R12(max) 10] + [(1.05 24.25 V R12) 10] ^ 37 mA (47) and, R11 t + * VR12(min) * 0.6V * * VSS(min) I B(Q4) [* 24.25 V * 0.6 V * (* 35.5 V)] ^ 288 kW 37 mA The closest available 5% tolerance value is 270 k. 24 A Power Management Interface Circuit for Telecom Hot Swap with Local DC/DC Conversion (48) SLUA250 3.2 Alternate Host Interface The interface circuit described in Section 3.1 (Figure 6) would be useful when the ON/OFF control-electronics' biasing supply (the HOST_VDD input) and the control lines are referenced to the GND node. This is also the return line for the two -48 V power busses. However, in a truly isolated system, logic supply returns would not have a common connection with the power section. Therefore, Figure 7 illustrates an optional interface configuration to maintain isolation from the power bus. In the Figure 7 circuit, the return of the two DC/DC converters (LCLRTN) is used as the reference for the I/O signals (SD and FLT). Opto-couplers maintain isolation from the primary side. The pull-up on the FLT line is shown on the plug-in schematic to provide extra detail. However, this pull-up can just as easily be located in the control module or board, eliminating the need for bussing the HOST_VDD to the controlled slot altogether. 1 k SD 1 62 k 5 43 k 2 4N29 ZTX553 4 270 k HOST_VDD ZTX453 TO U1 SDFL 10 k FLT LCLRTN 5 4 1 4N29 2 10 k TO U1 VSS UDG-00147 Figure 7. Alternate Host/System Interface for Isolated Controller 3.3 Optional UVLO Circuit The solution developed through the steps of Section 2.3, Circuit Design Procedure, assumes that the internal UVLO circuit of the PT3320 regulators is used. However, during a live insertion, any current consumed by the load, in this case, the two ISRs, is not available for charging up the input capacitance (C5 and C7). For a given maximum current-sourcing level, as controlled by the UCC3921, faster charging of this load capacitance can be achieved when the source does not have to also supply the regulators and secondary-side load. Therefore, when the operating input supply range allows, or if using different converters, or where large input capacitance exists, it may be desirable to keep the load disabled until the input voltage has achieved a higher potential. One way of doing this is to shift the threshold of the UVLO function upward. A Power Management Interface Circuit for Telecom Hot Swap with Local DC/DC Conversion 25 SLUA250 The Figure 8 schematic shows the details of an undervoltage lockout sub-circuit achieved with a few discrete components. The circuit is driven by the supply voltage across the VIN terminals of U2 and U3. During the input ramp-up transient, diode D4 keeps transistor Q6 off until its breakdown voltage is exceeded. R16 is then able to bias Q7 on, which pulls the converter INH pins to the VIN- potential. This keeps the converter outputs off. Once the converter input voltage exceeds the D4 Zener threshold, D4 conducts, turning on Q6. Q6 acts to pull the Q7 base low, which turns Q7 off. The inhibit control circuitry of the PT3320 modules features a nominal 10-A pull-up. With external transistor Q7 presenting a high impedance, the INH input is internally pulled high, above the enable threshold of 2.5 V, and the converters start up. Using the 39-V Zener diode as shown in the schematic should provide a UVLO function of 39 V to 41 V. U2 7 GND 8 D4 1N5259B 39 V SD R8 10 k D3 1N4148 R9 120 k Q7 ZTX453 2 1 4 VIN- 5 VIN- 6 VIN- Q6 ZTX453 Q4 ZTX553 9 3 R14 10 k Q3 ZVP3310A FLT R15 10 k R11 270 k Q5 ZVN3310A R3 10 k , 1 W R16 510 k R12 62k R10 10 k HOST_VDD C5 100 F 100 V SDFL 2 IMAX 3 VDD 4 CT PL 7 OUT 6 SNS 5 VSS C3 1.0 F 16 15 14 R17 0 C6 330 F 6.3 V 18 12 11 10 13 U3 7 8 UCC3921 2 C7 100 F 100 V C1 0.1 F C2 1.0 F R2 13 k 1% +1.8VDC 17 R7 100 k 8 9 R1 Q2 1.0 M 2N7000 1% 19 PT3325 U1 1 +SNS VOUT+ VOUT+ VOUT+ VOUT+ ADJ VOUT- VOUT- VOUT- -SNS VIN+ VIN+ VIN+ INH N/C N/C 1 3 VIN+ VIN+ VIN+ INH N/C N/C +SNS VOUT+ VOUT+ VOUT+ VOUT+ ADJ VOUT- VOUT- VOUT- -SNS 4 VIN- 5 VIN- 6 VIN- R4 82 k R13 0 19 +2.5VDC 17 16 15 14 18 12 C8 330 F 6.3 V LCLRTN 11 10 13 PT3326 VIN- F1 3 AG, 2 A D1 MBR3100 F2 3 AG, 2 A D2 MBR3100 -48VDC_N1 -48VDC_N2 R5 0.025 1 W, 1% Q1 IRF530 UDG-00146 Figure 8. Complete Detailed Application Circuit 4 Performance Evaluation and Sample Waveforms The oscilloscope plots presented in this section demonstrate the operation of the circuit shown in Figure 8. To obtain these figures, the external UVLO circuit was disabled, so that the DC/DC turn-on is controlled by the on-board UVLO circuit. The HOST_VDD supply was set to a nominal 3.3 V. Unless stated otherwise, the ISR outputs were each loaded at 6.0 A. Generally, the scope channel connections in the plot labels refer to the node names in any of the preceding schematics; IIN refers to input current into the plug-in module. 26 A Power Management Interface Circuit for Telecom Hot Swap with Local DC/DC Conversion SLUA250 Figure 9 shows the input voltage ramp-up and output turn-on following a live insertion event, with the supply voltage at -48 Vdc. In Figures 9 and 10, hot swap was performed with the -48VDC_N1 making last. Both figures demonstrate the smooth ramp of the converter input voltage, (i.e., the voltage across filter capacitors C5 and C7) Figure 10 shows the nearly linear ramp of the inrush current during the voltage ramp. Of particular interest is that the startup delay of the converters (from VIN reaching the UVLO threshold) is such that the outputs do not ramp until after the input ramp is complete. -48VDC_N1 50 V/div VIN = -48 Vdc IMAXNOM VIN- 20 V/div 500 mA -48VDC_N1 50 V/div VIN- 20 V/div 1.8VDC OUT 2 V/div 2.5VDC OUT 2 V/div IIN 1 A/div t - Time - 2.5 ms/div Figure 9. Hot-Swap Startup Sequence t - Time - 2.5 ms/div Figure 10. Hot-Swap Startup Input V/I Profile A Power Management Interface Circuit for Telecom Hot Swap with Local DC/DC Conversion 27 SLUA250 Figures 11, 12, and 13 show the insertion waveforms for a -72 Vdc bus potential, for an HSPM IC operating at the minimum, maximum and nominal sourcing current levels, respectively. -48VDC_N1 50 V/div VIN = -72 Vdc IMAXMIN -48VDC_N1 50 V/div VIN- 50 V/div VIN- 50 V/div IIN 1 A/div IIN 1 A/div t - Time - 2.5 ms/div Figure 11. IMAXMIN Startup Waveforms -48VDC_N1 50 V/div VIN = -72 Vdc IMAXMAX t - Time - 2.5 ms/div Figure 12. IMAXMAX Startup Waveforms VIN = -72 Vdc IMAXNOM VIN- 50 V/div IIN 1 A/div t - Time - 2.5 ms/div Figure 13. IMAXNOM Startup Waveforms Figure 12, at -72 Vdc input and IMAXMAX was generated under conditions closely representing the worst-case scenario for starting up with a fully discharged plug-in (tCTSS determination in Section 2.3.5 Step 5 - Estimating Ramp TIme). The Figure 12 waveforms confirm that the module starts up smoothly even under this condition. Also, it can be seen that at this input potential, with the extension in rampup time, the turn-on of the two converter modules occurs during the input ramp-up transient. 28 A Power Management Interface Circuit for Telecom Hot Swap with Local DC/DC Conversion SLUA250 In order to verify some of the equations used in Section 2.3, Circuit Design Procedure, in determining circuit component values, some theoretical input voltage ramp times and peak inrush levels were calculated using equations 19 and 26, under some sample circuit conditions. These start times and peak currents, shown in the Calculated columns in Table 3, were determined for an HSPM IC operating at its nominal, minimum and maximum current limit thresholds. A nominal ISR UVLO threshold of 33 Vdc was assumed. These values were then checked against measurements obtained from the transient waveforms of Figures 9 through 13, and similar plots. The results are summarized in Table 3. Table 3. Startup Time and Peak Current Comparison SUPPLY VOLTAGE -48 48 Vdc -72 72 Vdc TOTAL STARTUP TIME (ms) PEAK CURRENT (A) CONDITIONS Calculated Measured Calculated Measured 8.825 7.85 2.403 2.26 IMAXNOM 10.05 9.05 2.164 1.90 IMAXMIN 7.67 7.15 2.705 2.48 IMAXMAX 11.13 10.70 2.805 2.66 IMAXNOM 12.685 12.15 2.505 2.26 IMAXMIN 9.66 9.30 3.183 3.0 IMAXMAX Table 3 shows good correlation between the anticipated and actual startup times. In general, the actual ramps were about 1 ms faster at the -48-Vdc input level. The primary factor for this is most likely the delay in ISR output turnon, which means that the use of the maximum input current estimates for IL(t) in equation 24 is overly conservative. For the -72-Vdc input case, the start time estimates are only about 500 s too high; not surprising because at this supply level, the converters do start supplying the load currents prior to the end of the input voltage ramp. The waveform graphics in Figures 14 and 15 demonstrate the startup from SD deassertion. For the Figure 15 plot, the soft-start capacitor C3 was removed to show the transient current clamp at the IMAX level. The nominal current limit obtained is the 4.8-A theoretical value. In addition, the -48VDC_N1 traces demonstrate the extent of the disturbance on the supply bus. At 200 mV/div (Figure 15), the bus transients are only about +600/-100 mV about the steady-state level, even without inrush current slewing. A Power Management Interface Circuit for Telecom Hot Swap with Local DC/DC Conversion 29 SLUA250 VIN = -48 Vdc IMAXNOM CH1 ac Coupled VIN = -48 Vdc IMAXNOM CH1 ac Coupled -48VDC_N1 100 mV/div -48VDC_N1 200 mV/div VIN- 50 V/div VIN- 50 V/div IIN 1 A/div IIN 2 A/div t - Time - 500 s/div t - Time - 1 ms/div Figure 14. Startup from SD Deassertion Figure 15. Startup from SD - No Soft-Start Figure 16 shows another hot swap event at the -48-Vdc supply level, with the time base expanded to view the inrush current ramp under soft-start. Using the 10% and 90% points, the average di/dt obtained with the circuit was determined to be: (2.0 A * 0.222 A) A . ^ 0.27 ms 6.52 ms Recall that capacitor C3 was selected in Step 4 for a maximum slew rate of 0.5 A per ms; therefore, the average di/dt obtained is approximately half that value. -48VDC_N1 50 V/div VIN- 20 V/div t90 t10 VIN = -48 Vdc IMAXNOM t = 6.52 ms IIN 1 A/div t - Time - 1 ms/div Figure 16. Slew Rate Calculation The waveforms in Figures 17 and 18 demonstrate the operation of the FLT output during startup (Figure 17) and shut-down (Figure 18) sequences, when initiated from the SD input. 30 A Power Management Interface Circuit for Telecom Hot Swap with Local DC/DC Conversion SLUA250 SD 5 V/div FLT 1 V/div SD 5 V/div VIN = -48 Vdc IMAXNOM FLT 1 V/div VIN- 50 V/div 2.5VDC OUT 2 V/div VIN- 50 V/div 2.5VDC OUT 2 V/div VIN = -48 Vdc IMAXNOM t - Time - 100 ms/div t - Time - 2.5 ms/div Figure 17. FLT Output Operation During Startup Figure 18. FLT Output Operation During Shutdown Figure 19 shows the circuit response should the HOST_VDD supply be removed or fail. As desired, the pass FET is switched off, and the FLT output is asserted. The input voltage to the ISRs decays in a manner dictated by the load characteristics. There is an initial step drop in voltage, and then, when the input hits the UVLO threshold, the ISRs turn off, and the 200-F bulk capacitance is discharged by leakage only. HOST_VDD 5 V/div VIN = -48 Vdc FLT 1 V/div VIN- 20 V/div t - Time - 100 ms/div Figure 19. Shutdown for HOST_VDD Failure A Power Management Interface Circuit for Telecom Hot Swap with Local DC/DC Conversion 31 SLUA250 The next two scope plots show the circuit's fault response to a short-circuit condition at the DC/DC converter inputs. Figure 20 depicts initial normal steady-state operation with a -48 V dc input supply and about an 800-mA load, from the IIN trace. With the sudden application of a short (see VIN-trace), the HSPM IC clamps the short-circuit current at approximately 4.8 A, times out in about 6 ms, and ultimately latches the pass FET off. Figure 21 shows attempted startup into a short across the VIN terminals of the converters. The input current slews up as programmed, but no voltage develops across the converter inputs (VIN- scale is 1V/div), and the HSPM again times out and latches off. In this case, the total time-out is longer than that shown in Figure 20. Recall that the fault timer does not start until the input current exceeds the nominal 2-A overcurrent threshold. -48VDC_N1 50 V/div FLT 5 V/div VIN = -48 Vdc IMAXNOM VIN = -48 Vdc IMAXNOM VIN- 1 V/div VIN- 20 V/div IIN 1 A/div IIN 2 A/div t - Time - 1 ms/div Figure 20. Short-Circuit at Converter Inputs t - Time - 2.5 ms/div Figure 21. Startup into Shorted ISR Input The scope plots of Figures 22 and 23 demonstrate the short-circuit response of the PT3320 converters. In Figure 22, the module is initially operating steady-state with -48-V input, and a 6-A load on each of the ISR outputs. When a short-circuit is applied to the +1.8 Vdc output, the converter shuts off, then periodically pulses on to test for a continued fault condition (IOUT trace). Because of the voltage step-down, the input current peaks remain below the HSPM overcurrent threshold, and the HSPM does not trigger. Because of this, the second output (+2.5 Vdc, not shown), can continue to operate normally. Applying a short to the +2.5V output produces the corresponding pulsed current response. Figure 23 is a plot of the same fault conditions, but with the power bus at a -36 V potential. 32 A Power Management Interface Circuit for Telecom Hot Swap with Local DC/DC Conversion SLUA250 IIN 1 A/div IIN 1 A/div IOUT 5 A/div IOUT 5 A/div 1.8VDC OUT 2 V/div 1.8VDC OUT 2 V/div t - Time - 1 ms/div Figure 22. Output Short-Circuit Response (-48-V Supply) 5 t - Time - 1 ms/div Figure 23. Output Short-Circuit Response (-36-V Supply) Notes 1. The PT3327 module produces a nominal 1.8 Vdc output voltage. However, the PT332x converters also provide for output voltage adjustment from 90% to 110% of nominal value using an external resistor. Due to sample availability at the time of this study, the 2-V PT3325 unit was used, with output adjustment to 1.8-V using R17 in the Figure 1 schematic. 2. Since only three of the available devices in the series are characterized in the data sheet, the PT3321 curves were used as the closest available output voltage/current match to the modules used in this solution. 6 References 1. UCC3921 Latchable Negative Floating Hot Swap Power Manager; Data Sheet; Texas Instruments Literature No. SLUS207; March 1998 2. PT3320 Series 30-Watt Isolated DC/DC Converter; Data Sheet; Texas Instruments Literature No. SLTS018A; June 2000 3. Adjusting the Output Voltage of the Power Trends' 30W Isolated DC/DC Converter Series, Application Note; Texas Instruments Literature No. SLTS018A 4. Using the Inhibit Function of the Power Trends' 30W Isolated DC/DC Converter Series, Application Note; Texas Instruments Literature No. SLTS018A 5. ISR Input/Output Filters, Application Note; Texas Instruments Literature No. SLTA013A, June 2000 The UCC3921 device parameters used in this document are listed in the Table A-1for quick reference. To aid the user in determining the source of these values, the corresponding data sheet parameter name is shown. For a complete listing of the UCC3921 specifications, the user is referred to the device data sheet. A Power Management Interface Circuit for Telecom Hot Swap with Local DC/DC Conversion 33 SLUA250 Table 4. UCC3921 Hot Swap Power Manager Device Parameters PARAMETER VALUE UNIT Over Op. Temp 46 mV Minimum fault threshold (Overcurrent Comparator) Over Op. Temp 53.5 mV Maximum fault threshold (Overcurrent Comparator) 9.0 V Minimum shunt regulator voltage VREF(NOM) 9.5 V Nominal shunt regulator voltage VREF(MAX) 10.15 V Maximum shunt regulator voltage 15 mV VFLT(MIN) DATA SHEET REF CONDITIONS Overcurrent Threshold VFLT(MAX) VREF(MIN) Regulator Voltage VOS Input Offset Voltage IBIAS LCA Input Bias Iq(MIN) CT Charge Current VIMAX = 100mV VOS of the Linear Current Amplifier (LCA) 30 mV 500 nA Input bias current on the LCA IPL = 0 22 A Minimum CT charge current (overcurrent condition) IPL = 0 50 A Maximum CT charge current (overcurrent condition) VIMAX = 400 mV Iq(MAX) DESCRIPTION Idq(MAX) CT Discharge Current 1.5 A Maximum CT discharge current VLS CT Fault Threshold 2.2 V Minimum Fault Comparator SET threshold VLR CT Reset Threshold 0.57 V Maximum Fault Comparator RESET threshold VPLIM VSENSE Regulator 5.0 V Voltage at PL pin (sink condition) VSD(MAX) Shutdown Threshold VDD + 1 V Maximum shutdown threshold ISD(MAX) Input Current, SDFLTCH 250 A Maximum IIH at SDFL pin 34 A Power Management Interface Circuit for Telecom Hot Swap with Local DC/DC Conversion IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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