UCC3913J - Texas Instruments

Application Report

SLUA250 - March 2001

A Power Management Interface Circuit for Telecom

Hot Swap with Local DC/DC Conversion

Andrew Ripanti Power Distribution and Processing Solutions

ABSTRACT

Much of the Telecom and Datacom equipment infrastructure operates from a power

architecture based on a –48 Vdc distribution bus. This supply level has emerged as a

standard and efficient means of distributing power throughout equipment racks, while

facilitating alternate source operation from secondary power, such as batteries, when the AC

line supply is unavailable. To further improve uptime ratios while meeting the needs of

maintenance and reconfiguration, hot swap capability is often incorporated in removable

subassembly specification and design.

Today, the brains of these communication systems; i.e., microprocessors, DSPs, ASICs, and

programmable logic, are evolving to ever-lower operating voltages. Typical integrated

circuits run at supply levels of 3.3 V, 2.5 V, and even lower. As this occurs, new devices and

modules are being developed to address the functions of hot-swapping the –48 Vdc bus, and

subsequent conversion to local regulation levels. These devices provide a high level of

integration for the point-of-use power supplies, saving the system designer both design time

and critical board space.

This application report presents one possible solution to the telecom plug-in power problem,

based on a nominal –48 Vdc system bus and a module needing two low-voltage supply

outputs. The material includes a detailed design methodology for tailoring the circuit to the

specific requirements of the reader’s system. The solution is based on two device families

offered by Texas Instruments, the UCC3913 and UCC3921 hot swap power manager ICs,

and the PT3320 series of integrated switching regulators (ISRs).

The document organization is such that some example system requirements are defined,

then a step-by-step procedure is presented for determining external component values to set

user-programmable features. There is discussion of some optional features. Finally, the

circuit operation and performance is further illustrated through scope plots of the circuit’s

response to various live insertion events, and input and output fault conditions.

SLUA250

2A Power Management Interface Circuit for Telecom Hot Swap with Local DC/DC Conversion

CONTENTS

1 The Power Transmission Problem 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 The Power Management Interface 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3 Additional Features 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4 Performance Evaluation and Sample Waveforms 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5 Notes 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6 References 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SLUA250

A Power Management Interface Circuit for Telecom Hot Swap with Local DC/DC Conversion

1 Introduction

1.1 The Power Transmission Problem

Many telecom and datacom systems are configured from subsystem racks and chassis, or

boxes, each containing a system host or controller card, one or more power supplies, and

various sub-assembly cards performing functions of data processing, data transmission and

switching. The interconnect between the different modules is often accomplished with a

backplane or motherboard. Power is commonly provided to the various module slots via a

–48 Vdc distribution bus. This is an efficient means of supplying power throughout the box for

two main reasons:

1. Current bussing requirements are significantly reduced compared to the current levels that

would be encountered if power were distributed at the regulation levels of 5.0 V, 3.3 V, or

even lower, and

2. System supply voltage droops and spikes of several volts are more easily tolerated by the

driven electronics, as significant voltage margin now exists between the power bus and

the regulation levels.

This configuration, however, creates the need for efficient and cost-effective voltage conversion

to the local regulation levels at the points-of-use.

The power conversion issue is further complicated when the driven boards are specified to have

hot swap or hot plug capability. Simply put, hot swap is the ability to safely insert a module into

or remove it from a host system, without first interrupting power to the host. This feature is

generally designed in wherever there is a need to replace modules on-the-fly. Such a

requirement may be for purposes of repair, reconfiguration, redundancy, or system upgrade. It is

also useful in systems with high availability requirements (i.e., high up-time ratios). Finally, hot

swap requirements may be included in the target industry specification that is being designed to,

such as PCI, Compact PCI, USB, and 1394. Not surprisingly, it has seen significant use in

telecom systems.

As a highly desirable feature in many applications, hot swap capability also creates several

issues that must be addressed in the system design. A number of related phenomena occur with

a live insertion or removal event, including contact bounce, arcing between connector pins, and

large voltage and current transients. The stresses on the mechanical interface, power supply,

and input filter components can produce latent defects leading to intermittent or premature

failures. Therefore, a power interface is needed which can safely mitigate these effects. This

interface provides protection for both the host and plug-in electronics, data stored or transferred

in the system, and any transactions within or between systems.

This application note presents one possible solution for hot swapping a –48-Vdc bus, and

performing the required DC/DC conversion. The organization is such that the operating

parameters are defined, a top–level electrical schematic presented, followed by a detailed

procedure for determining component values, description of some optional features, and

performance verification.

The proposed solution is built around two main device types offered by Texas Instruments (TI).

The UCC3921 Hot Swap Power Manager (HSPM) integrated circuit handles the main functions

needed for hot swap capability; the conversion is performed using the PT3320 series of

integrated switching regulators (ISRs).

SLUA250

4A Power Management Interface Circuit for Telecom Hot Swap with Local DC/DC Conversion

The UCC3921 IC is a floating, negative-voltage hot-swap controller which, in conjunction with an

external N-channel FET, provides inrush current limiting, fault timeout, and fault reporting. An

on-chip shunt regulator generates the internal supply voltages and the gate drive for the external

pass element. Other features include continuous supply current monitoring with electronic circuit

breaker, remote enable, and user–programmable duty cycle to limit dissipation in the FET in

automatic retry mode. For a complete description of the UCC3921 features and operation,

please refer to the device data sheet.

The PT3320 is a series of 30-W, isolated DC/DC converter modules designed specifically for

48-V distribution systems. They are complete modules assembled onto a space-saving,

PCB-based, vertical- or horizontal-mount SIP package. A wide range of output voltage/current

combinations is available from 2 V to 15 V (see Table 1). A wide input voltage operating range

(36.0 V to 75.0 V) and high efficiencies make them applicable in numerous distributed power

applications. The converters contain an external inhibit function, and remote sense inputs to

compensate for any voltage drop from converter output to load. The only external component

required for operation is a 330-µF electrolytic capacitor. For further information on the full range

of 48-V converter products, including the 3-W to 7-W PT4200/4300 and 15-W PT3100 series

modules, please visit www.ti.com.

Table 1. PT3320 Series of Converters

DEVICE NUMBER

OUTPUT

DEVICE NUMBER VOLTAGE (V) CURRENT (A)

PT3321 3.3 8

PT3322 5.0 6

PT3323 12.0 2.5

PT3324 15.0 2

PT3325 2.0 8

PT3326 2.5 8

PT3327 1.8 8

PT3328 5.2 6

SLUA250

A Power Management Interface Circuit for Telecom Hot Swap with Local DC/DC Conversion

1.2 Design Requirements

To illustrate the detailed design steps for using the UCC3921 in a –48 V (or Telecom) system,

the following system-level requirements were defined:

•Input supply voltage: nominal –48 Vdc, –36 Vdc (min) to –72 Vdc (max)

•Output voltage/current: 1.8 Vdc at 6.0 A (max), and 2.5 Vdc at 6.0 A (max)

•Isolated outputs

•Redundant supply operation (2 sources)

•Hot-swap capability

•Interface to host ENABLE signal

•Fault indication to host

•0_C to 70_C ambient operating temperature

•Host VDD supply: 3.3 Vdc

SLUA250

6A Power Management Interface Circuit for Telecom Hot Swap with Local DC/DC Conversion

2 The Power Management Interface

2.1 Electrical Schematic Diagram

The electrical schematic for one type of implementation of the power interface specified in the

design requirements is shown in Figure 1. Some of the secondary functions are shown here in

block form for later discussion. The output voltages are generated from the –48-Vdc input via the

PT3326 (2.5 V) and PT3325 (1.8 V) modules[1]. The PT3320 modules are fully isolated, thus

eliminating the need for additional transformers. The UCC3921 HSPM resides between the input

supply and the VIN pins of the converters. It drives N-channel FET Q1, which switches the low

side of the supply (–48 V). The SNS input of the IC monitors the voltage drop across sense

resistor R5, so the current load on the 48 V supply is monitored.

UDG–00143

C1 0.1µF

C2 1.0µF

1.0 MΩ

82 kΩ

13 kΩ

1.0 µ F

10 kΩ, 1 W

0.025Ω

1 W, 1%

MBR3100

3 AG, 2 A

MBR3100

3 AG, 2 A

100 kΩ

100µF

100 V

330µF

6.3 V

GND

FLT

HOST_VDD

2N7000

IRF530

SDFL

IMAX

VDD

CT VSS

SNS

OUT

UCC3921

R13

0Ω

VIN+

VIN–

INH

N/C

+SNS

VOUT+

VOUT–

–SNS

ADJ

PT3325

VIN+

VIN–

INH

N/C

+SNS

VOUT+

VOUT–

–SNS

ADJ

PT3326

330µF

6.3 V

100µF

100 V

LCLRTN

R17

0Ω

HOST/

SYSTEM

INTERFACE UVLO

VIN–

+1.8VDC

+2.5VDC

–48VDC_N1

–48VDC_N2

Figure 1. Top-Level Schematic Diagram for –48 Vdc Hot Swap with DC/DC Conversion

SLUA250

A Power Management Interface Circuit for Telecom Hot Swap with Local DC/DC Conversion

Table 2. Hot Swap Power Circuit Signal Descriptions

SIGNAL NAME DESCRIPTION

–48VDC_N1 –48-Vdc input supply no. 1 to the plug-in PCB.

–48VDC_N2 –48-Vdc input supply no. 2 to the plug-in PCB.

GND Supply common for the two –48 Vdc supplies. This is also intended as the system ground node.

HOST_VDD Host or controller VDD node, +3.3 V dc.

SD Active low SHUTDOWN input for remote or host control of the module ON/OFF status.

FLT Active low FAULT output to the system.

+1.8VDC +1.8 V dc power supply output.

+2.5VDC +2.5 V dc power supply output.

LCLRTN Common local return for the two output supply rails.

2.2 Detailed Circuit Description

The UCC3921 device determines load current levels by monitoring the voltage drop across a

low-ohmic value sense resistor, R5, as shown in Figure 1. The device has two distinct current

thresholds for defining different modes of operation. The first threshold is the fault current,

referred to herein as IFLT. This can be thought of as the circuit breaker trip current. When

enabled, and under normal load conditions below the fault current threshold, the UCC3921 OUT

pin drives external FET Q1 gate with a nominal 9.5-V source, relative to the VSS node. Q1 is

switched on, and completes the low impedance return path from the load (VIN– pins of the

ISR’s). When the device detects a nominal drop of 50 mV or greater between the SNS and VSS

pins, an internal source begins charging an external capacitor connected to the CT pin,

essentially generating a time delay before tripping, or opening the supply return path by turning

off transistor Q1. However, during this timeout period, the pass FET is still driven as a

low–ohmic value switch. If the fault condition is removed prior to timeout, the capacitor is

discharged, and supply operation continues uninterrupted.

The second threshold is the maximum current that will be sourced to the load by the HSPM

circuit, or IMAX. Under heavy overcurrent or short-circuit conditions, the input current to the

converter circuit will be clamped at this maximum level. During a live PCB insertion, inrush

current caused by charging bulk capacitance (C5 and C7 in Figure 1) will also be limited to this

level. The threshold is programmable by using a resistor divider to set the voltage at the U1

IMAX pin. The VDD node provides a ready reference for this divider. In the Figure 1 schematic,

this threshold is set by the R1/R2 resistor network.

Since the UCC3921 is a current-driven device, it essentially floats from the positive supply input.

Resistor R3 sets the biasing supply level for the VDD input. Capacitor C1 provides supply

bypassing for U1, and C2, tied to the CT pin, is the timing capacitor. Resistor R7 is an optional

component used by the UCC3921 to further limit power dissipation in the pass element, under

certain fault conditions, below the limits that are automatically provided by the IC.

The detailed procedure for determining component values for the hot swap interface will be

shown in Section 2.3, Circuit Design Procedure. For a complete description of the HSPM IC

operation and electrical specifications, see the UCC3921 device data sheet.

Capacitors C6 and C8 provide the energy storage capability required for proper operation of the

PT3320 switcher modules, U2 and U3 respectively. They also provide some output filtering for

the DC/DC converters. The 330-µF value used is the manufacturer’s recommended value. The

input capacitors C5 and C7 are used to ensure good power quality to the ISRs.

SLUA250

8A Power Management Interface Circuit for Telecom Hot Swap with Local DC/DC Conversion

Diodes D1 and D2 provide a diode–OR function between the two redundant supply nodes

(–48VDC_N1 and –48VDC_N2). If only one supply is present, or if one supply has failed, supply

return is still provided by the alternate path. Note that Schottky diodes are used; at least one of

these devices is always conducting, so Schottkys are used to minimize the reduction in overall

efficiency of the interface.

Fuses F1 and F2 provide a one-shot over-current protection in the event of catastrophic failure

of the more intelligent protection devices downstream. The PT3320 ISRs feature output

short-circuit protection. The UCC3921 features both a programmable current limit, and circuit

breaker operation. These provide redundancy to the output protection, and protect against an

overcurrent or short-circuit on the primary (VIN) side. Should these devices fail in the right

combination, fuses F1 and/or F2 provide a permanent, mechanical interrupt.

The block labeled HOST/SYSTEM INTERFACE in Figure 1 is an optional sub-circuit to allow

remote ON/OFF control of the plug-in module, and generate a current fault indication back to the

host. This block provides the level-translation needed to refer the multifunctional SDFL pin of the

UCC3921 to the system common, or GND node. If these features are not needed,

implementation of this circuit is not necessary.

The block labeled UVLO provides an optional undervoltage lockout (UVLO) function to the

startup of the two DC/DC converters. However, the PT3320 regulators incorporate an internal

UVLO circuit, the threshold of which is specified to be 33 ±2.0 Vdc. Since the design

specification requires this circuit to operate down to a –36-V supply level, and the maximum ISR

UVLO level is just below this voltage, this solution was developed assuming the internal UVLO is

to be used. To address a wider range of application requirements, an alternative implementation

of an external UVLO circuit is shown in Section 3.3, Optional UVLO Circuit.

2.3 Circuit Design Procedure

The following is a sequence of design steps that can be used to determine component values for

the configuration circuitry around the hot-swap controller IC. The process takes into

consideration the load characteristics, both during startup and under dc operating conditions,

and the device parameter specifications. To assist the reader in determining the source and

value of the UCC3921-specific variables plugged into the following equations, Appendix I

summarizes the key device parameters.

2.3.1 Step 1 – Determine Input Load Current

In order to set the fault levels for the HSPM IC, the nominal load current on the input supply

must be estimated. Given the operating loads on the two regulated outputs from the design

specification, the converter efficiency can be used to estimate the average load on the primary

(bus) side. Also, since the PT3320 modules are switching regulators, the peak load is

anticipated to occur when the bus potential is at its lowest.

From the PT3321 curves shown in the data sheet[2], the efficiency at 6 A for input voltage of

36 V is nearly 80%, decreasing to about 75% at 75 V. Power delivered to the loads, POUT, and

subsequently input current to the board, IIN, are estimated from the following equations.

POUT +PO1 )PO2 +ǒVO1 ILOAD1Ǔ)ǒVO2 ILOAD2Ǔ

where:

(1)

SLUA250

A Power Management Interface Circuit for Telecom Hot Swap with Local DC/DC Conversion

•VO1 = local regulation level No. 1, +2.5VDC

• ILOAD1 = maximum output load on VO1

• VO2 = local regulation level No. 2, +1.8VDC

• ILOAD2 = maximum output load on VO2

The input supply current under normal steady-state operation, IIN, can then be estimated from:

IIN +PIN

VIN +

PO1

h1)PO2

VIN

IIN +VO1 ILOAD1

h1 VIN )VO2 ILOAD2

h2 VIN

where:

• PIN = input power delivered to the board

• η1, η2 = respective converter efficiencies for outputs 1 and 2

• VIN = the input supply voltage level

For reasons detailed in Section 2.3.5, the designer must determine the maximum input current

at each of the input voltage extremes. Therefore, two maximum current levels need to be

calculated. Defining IIN(max) as the supply current when the bus is at its lowest potential, and

IIN(max′ ) as the supply current when the bus is at its highest potential, then substituting the

values from the requirements specification, the input current levels shown in equations 4 and 5

are obtained. Note that equations 4 and 5 are a simplification of equation 3 when the converters

are anticipated to be operating at virtually equivalent efficiency points.

IIN(max) +ǒVO1 ILOAD1Ǔ)ǒVO2 ILOAD2Ǔ

h36 VIN(min)

IIN(max) +[(2.5 V 6.0 A))(1.8 V 6.0 A)]

(0.8 36 V)

IIN(max) +0.896 A

and

IIN(maxȀ)+ǒVO1 ILOAD1Ǔ)ǒVO2 ILOAD2Ǔ

h75 VIN(max)

IIN(maxȀ)+[(2.5 V 6.0 A))(1.8 V 6.0 A)]

(0.75 72 V)

IIN(maxȀ)+0.478 A

(2)

(3)

(4)

(5)

SLUA250

10 A Power Management Interface Circuit for Telecom Hot Swap with Local DC/DC Conversion

These estimates were made considering the dc or average-output currents. For the PT3320

series, the input ripple current is typically less than 0.25 A peak. This is added to the average

values to get an approximation of the peak input current under normal operating conditions, to

ensure that the HSPM does not trigger due to expected input ripple. The results (rounded to the

nearest 10 mA) are:

IIN(max) ^1.15 A

IIN(maxȀ)^0.730 A

2.3.2 Step 2 – Set Fault Current Level And Determine Sense Resistor Value

The fault current level for the hot swap interface circuit must be selected. This is established by

the value of the sense resistor, R5 in the Figure 1 schematic. Since the nominal overcurrent

threshold of the UCC3921 is 50 mV, the resistor value can be determined from equation 6.

R5 +VFLT

IFLT +50 mV

2.0 A +25 mW

Selecting a nominal fault threshold of 2.0 A provides nearly 100% margin over the anticipated

peak operating levels. Some design margin is desirable to provide headroom for any transient

peaks on the output supplies, tolerances on the converter efficiency from unit-to-unit, transients

on the –48-V supply bus that cause surges in input current, and as an overall guard against

nuisance trips. Using the UCC3921 specification values for the overcurrent threshold, and with

the sense resistor value fixed, the minimum and maximum current fault levels can be verified

using equations 7 and 8.

IFLT(min) +VFLT(min)

R5 +1.84 A

IFLT(max) +VFLT(max)

R5 +2.14 A

where :

• VFLT(min) = minimum fault (overcurrent) threshold

• VFLT(max) = maximum fault threshold

The calculated minimum value, 1.84 A, demonstrates that significant margin is available even

with a device at the low end of its specification limit.

(6)

(7)

(8)

SLUA250

A Power Management Interface Circuit for Telecom Hot Swap with Local DC/DC Conversion

2.3.3 Step 3 – Set IMAX Threshold And Determine IMAX Divider Values

The maximum sourcing current level of the hot swap circuit, herein referred to as IMAX, is user

programmable, using the IMAX input pin of U1. In an effort to predict performance under

worst-case parameter conditions, it is recommended to establish the lower threshold for this

maximum sourcing capability, or IMAXMIN. Generally, this will correspond to the IMAX level for a

device with a regulator output (VDD) at the specification minimum voltage, taking into account

two other sources of variance, the input offset voltage and bias current of the internal linear

current amplifier (LCA). For proper device operation, this value should be greater than the

calculated maximum fault current, IFLT(max). If a relatively fast rate of input current slewing is

allowed, or a large amount of bulk capacitance exists at the input to the plug-in, the IMAX

feature can be used to accomplish faster charging of the load capacitance, thus minimizing the

startup transient duration. However, if the distribution supply has a slow transient response,

minimal output capacitance, or is required to operate near peak capability at the expected

system steady-state load, the IMAX level should be selected with these limitations in mind. In

addition, under a short-circuit situation, the load current of the affected module(s) will make a

step change to this level. For this example, a minimum sourcing level of 4.0 A is used.

Figure 2 is a simplified model of the UCC3921 operation when the sense voltage, VSNS, is

above the IMAX threshold. During inrush or short-circuit conditions, the HSPM device acts to

control the gate of Q1 such that it appears as a constant-current source. The internal LCA will

respond to maintain the VSNS node equal to the IMAX reference, (i.e., the drop across the sense

resistor equal to the drop across R2.) Therefore, an equation for the sense voltage is generated

by writing the loop equation at the linear current amplifier (LCA) inputs (equation 9).

UDG–00141

3LINEAR

CURRENT

AMPLIFIER

RSNS

IBIAS

VDD

OUTPUT

VIMAX

VSNS

UCC3921

±VOS

Figure 2. Model of UCC3921 Linear-Mode Operation

SLUA250

12 A Power Management Interface Circuit for Telecom Hot Swap with Local DC/DC Conversion

VSNS +VIMAX *VBIAS "VOS

where:

• VSNS = the drop across the sense element

• VIMAX = the voltage at the 3921 IMAX input pin

• VBIAS = the error component developed by the IMAX bias current

• VOS = the input offset of the internal LCA

Also from Figure 2, the VIMAX DC voltage is given by the R1/R2 divider equation.

VIMAX +R2

R1 )R2 VREF

where:

•VREF = the internal shunt regulator output, VDD

Considering that the bias current flow is into the IMAX pin, the smallest error contribution occurs

for a device with negligible bias current, which is approximated here to zero. Then, a special

case of equation 9 for the minimum sense voltage in linear mode, is given by equation 11.

VSNS(min) +VIMAX(min) *VOS

Given that VSNS(min) = IMAXMIN × R5, combining equations 10 and 11, and solving for R2 in

terms of R1, yields:

R2 +ǒIMAXMIN R5Ǔ)VOS

ƪVREF(min) *ǒIMAXMIN R5Ǔ*VOSƫ R1

The value for R1 can be set to limit the overall current draw of the divider net; if R1 is set to

1 MΩ, equation 12 then becomes:

R2 +(4.0 0.025))15 mV

[9.0 *(4.0 0.025)*15 mV] 1.0 MW

R2 +12.94 kW

The standard 1% value of 13 kΩ was selected for R2.

(9)

(10)

(11)

(12)

(13)

SLUA250

A Power Management Interface Circuit for Telecom Hot Swap with Local DC/DC Conversion

With values now selected for resistors R1 and R2, the actual minimum and maximum sourcing

current levels is predictable. These values are useful for determining the startup time (ramp-up

from 0 V to the dc input level) under different conditions. Equations 14 and 15 are obtained by

manipulating equation 12. For the IMAXMAX value, the error contribution from the bias current is

included.

IMAXMIN +ƪR2

R1)R2 VREF(min)ƫ*VOS

R5 +4.02 A

IMAXMAX +ƪR2

R1)R2 VREF(max)ƫ)VOS )VBIAS

R5 +6.07 A

2.3.4 Step 4 – Soft-Start Programming

The UCC3921 is easily configured for optional soft-start operation. Without soft-start, when a

plug-in is inserted into a live socket, the resultant inrush makes a step change to the IMAX limit,

where it becomes clamped for the duration of the transient period. Soft-start operation provides

an inrush slew rate control, such that the load charging current is gradually ramped, potentially

to the maximum value established by the IMAX pin programming resistors.

Soft-start is selectable by installing a capacitor in parallel with the IMAX programming resistor

(shown in Figure 1 as capacitor C3.) The feature operates by putting an RC time constant on the

voltage ramp at the IMAX pin when the power manager is started. This forces the device to

operate in linear mode immediately from Q1 turnon, essentially producing a dynamic IMAX

function.

For a UVLO-protected load, such as presented by the two ISRs in this solution, the startup

voltage ramp to the converter inputs will have two stages. During the first stage of rampup, from

turnon until achieving the UVLO threshold, the load appears virtually capacitive to the charging

source. This capacitance, CLOAD, is the equivalent capacitance of the input filter capacitors, the

converter input capacitance, and any parasitics. Wherever this quantity is used in this document

to derive other values, it is approximated as the 200-µF value of C5 and C7.

For a constant-current source of value IMAX (i.e., no soft-start), the voltage at the converter

inputs during this stage, for a charging time of t, is given by equation 16.

nINU1(t) +IMAX t

CLOAD

Once the load charges to the UVLO threshold, VUV, the ISRs are allowed to start up. During this

second stage of the voltage ramp, the load capacitance is charged by the sourcing current in

excess of the ISR startup load, iL(t). This portion of the ramp-up curve is given by:

nINA1(t) +ƪǒIMAX *iL(t)Ǔ ǒt*tVUVǓƫ

CLOAD )VUV

(14)

(15)

(16)

(17)

SLUA250

14 A Power Management Interface Circuit for Telecom Hot Swap with Local DC/DC Conversion

where:

• iL(t) = load startup current

• VUV = the UVLO threshold voltage

• tVUV = the time to charge the input from 0 V to VUV, from equation 16

When soft-start programming is used, both the input voltage and current waveforms are of

interest. Due to the control action of the U1 LCA described above in step 3, we know that the

sense voltage tracks the R2 voltage during rampup, which is now the voltage across capacitor

C3. Since the output current of the HSPM circuit can be determined from the drop across R5,

the following equation for input current to the load is derived:

iIN(t) +IMAX ȧ

Ȳ1*eǒ*t

TSSǓȧ

where:

•iIN(t) = the charging load on the –48-Vdc supply

•ℑSS = the soft-start time constant, given by ℑSS = R2 × C3, in seconds.

Since the capacitor charging current is given by equation 18 under this condition, the input

voltage profile has an exponential term also. The first stage of the input rampup, prior to startup

of the ISRs, is defined by equation 19.

nINU(t) +

TSS IMAX

CLOAD ȧ

Ȳeǒ*t

TSSǓ)t

TSS *1ȧ

where:

•ℑSS = the soft-start time constant

Different criteria may be used for establishing the target slew rate of the hot swap circuit on

powerup. However, one overriding requirement is that the input current must be allowed to attain

a minimum value prior to the voltage across the input capacitance achieving the UVLO

threshold. This minimum level is the current that is demanded by the load. In this case, it is the

startup current of the two converters. If the minimum current is not obtained, the active load will

begin discharging the input capacitance (C5 and C7 in this case). Some amount of voltage

droop may be tolerated by the load, but that is dictated by the complexity and hysteresis of the

UVLO circuitry. As a general guideline, be sure to provide sufficient current to avoid any voltage

droop. This target current, or set current, is referred to as ISET in the following paragraphs.

To simplify what easily becomes a complicated math exercise, assume that the load startup

current is constant, or iL(t) = IL. To further simplify, assume that this constant value is in fact the

value previously calculated for the peak operating current, or IIN(max). For this example, the

minimum current required at load startup, ISET, is set to 5% over this value, or

ISET +1.05 IIN(max) +1.208 A

(18)

(19)

(20)

SLUA250

A Power Management Interface Circuit for Telecom Hot Swap with Local DC/DC Conversion

Given the voltage ramp profile of equation 19, what is the value of C3 which will ramp the input

current to at least ISET by the time the voltage reaches the UVLO threshold? By solving

equation 18 for the time t when iIN(t) = ISET, plugging this expression into Eq. 19, and solving for

the C3 term, equation 21 is derived.

C3 +*VUV

ȲǒR2

CLOADǓ ǒISET )IMAX ȏnǒ1*ISET

IMAXǓǓȧ

Examination of equation 18 reveals that the slowest current ramp occurs under minimum

sourcing conditions. Substituting IMAXMIN for IMAX in equation 21, and using the minimum

specified UVLO threshold (31 V), yields C3 = 2.09 µF. Because of the criteria used to establish

equation 21, the 2.09-µF value represents essentially the maximum size capacitor that should

be used in this solution.

To demonstrate an alternative, assume that a maximum slew rate requirement of 0.5 A per msec

is included in the design specification. The value of the soft-start capacitor, C3, for a given slew

rate can be found by taking the derivative of the input current during the startup voltage ramp,

given by equation 18. The result is equation 22 .

dt +IMAX

TSS eǒ*t

TSSǓ

Setting di/dt for t = 0 to the maximum slew rate spec, and substituting IMAXMAX for IMAX yields:

C3 +IMAXMAX

ǒR2 ǒdińdt)MAXǓ+0.934 mF

As shown in the schematic, a value of 1.0 µF was used.

2.3.5 Step 5 – Estimating Ramp TIme

The minimum delay to a fault timeout must be long enough to allow charging of the input

capacitance at startup. Therefore, an estimate of the total voltage ramp time at module startup is

needed. An empirical approach can be taken by bench-testing the interface circuit with the load

connected, and measuring the time for the converter input voltage to ramp to the DC input

potential. To do this, the fault timer can be defeated by temporarily installing a resistor with a

value ≤1 kΩ in place of capacitor C2. Alternatively, the analysis detailed in this section can be

used to better predict the worst-case timing.

For the analysis, two possible scenarios exist.

1. Either soft-start is not used, or soft-start reset switch Q2 is not used. For this case, the

output voltage equations 16 and 17 apply.

2. Output soft-start is used. The required delay is given by the tCTSS calculation shown in the

discussion after Figure 5.

For case 1, the HSPM IC operates in fault mode immediately from turn-on, and the

minimum delay needed is the total start time. This is given by equations 24 and 25.

(21)

(22)

(23)

SLUA250

16 A Power Management Interface Circuit for Telecom Hot Swap with Local DC/DC Conversion

tCT +tST1X +CLOAD ǒnINA1(t) *VUVǓ

IMAXMIN *IL)tVUVX

where:

tVUVX +CLOAD ǒVUV *0Ǔ

IMAXMIN

Solve tCT for VINA1(t) = VIN(max) and VUV = VUV(min).

For case 2, soft-start, equation 19 determines the time required to reach the UVLO threshold,

designated here as tVUV. Through repeated sampling of the voltage equation, the following

values were determined:

•tVUVX = 6.89 ms, the time for VIN(t) to reach VUV when IMAX = IMAXMIN

•tVUVM = 5.51 ms, the time for VIN(t) to reach VUV when IMAX = IMAXMAX

To approximate the worst case startup time, the minimum UVLO threshold of the converters,

31 V, was used as the target voltage level. Due to the tedious nature of sampling the voltage

waveforms at different times, it may be useful to create a spreadsheet or use some other

software tool to generate a table of values while sweeping the time variable.

At time t = tVUV, the load starts up. This defines the transition point between the two equations

for the input profile. The second stage of the ramp-up, from VIN(t) = VUV to the dc input level, is

given by:

nINA(t) +ƪTSS

CLOADƫ

ȢIMAX eǒ*t

TSSǓ)ǒIMAX *iL(t)Ǔ t

TSS ȧ

Ȥ*ȧ

ȢIMAX eǒ*tVUV

TSS Ǔ)ǒIMAX *iL(t)Ǔ tVUV

TSS ȧ

ȴ)

nINUǒtVUVǓ

Figures 3 through 5 show a graphic representation of the input current and voltage waveforms

during the transient ramp-up. Plots were produced for sourcing current limit, IMAX, at the

nominal, minimum and maximum levels.

(24)

(25)

(26)

SLUA250

A Power Management Interface Circuit for Telecom Hot Swap with Local DC/DC Conversion

Figure 3. ISR Input Voltage and Current –

IMAXMAX Condition

01224 6 810

–10

–20

–30

–40

–50

–60

3.0

2.5

2.0

1.5

1.0

0.5

0.0

t – Time – ms

IMAX(t)

VMAX(t)

Figure 4. ISR Input Voltage and Current –

IMAXNOM Condition

3.0

2.5

2.0

1.5

1.0

0.5

0.0 01224 6 810

–10

–20

–30

–40

–50

–60

t – Time – ms

INOM(t)

VNOM(t)

Figure 5. ISR Input Voltage and Current –

IMAXMIN Condition

01224 6 810

–10

–20

–30

–40

–50

–60

3.0

2.5

2.0

1.5

1.0

0.5

0.0

t – Time – ms

IMIN(t)

VMIN(t)

The selection of a minimum value for the fault timing capacitor, C2, is described in more detail in

Section 2.3.7. Since input current greater than the fault level may occur during the turn-on

transient, the time delay generated by C2 must be sufficient to allow charging of the input

capacitance after plug-in insertion or remote turn on. Therefore, the total duration of the turn-on

transient must be known. However, the internal fault timer is not started until the current fault

threshold is crossed, so the time for charging current to ramp to the minimum (i.e., worst-case)

fault threshold must also be determined. Ultimately, it is the maximum time difference, for a

given IMAX value, from fault threshold to the total startup time, which dictates the value of C2.

SLUA250

18 A Power Management Interface Circuit for Telecom Hot Swap with Local DC/DC Conversion

Inspection of equation 18 for iIN(t) indicates that the current ramp is independent of the supply

voltage, but is directly proportional to the IMAX level of the particular module. So the extremes of

the fault timing are determined by rewriting equation 18 to determine the time to reach the

IFLT(min) under both the IMAXMIN and IMAXMAX conditions.

tFLT +*R2 C3 ȏnǒ1*IFLT(min)

IMAX Ǔ

and

• tFLT(min) = 4.695 ms, the fault time when IMAX = IMAXMAX

• tFLT(max) = 7.956 ms, the fault time when IMAX = IMAXMIN

These values were calculated with the 1.84 A minimum fault current determined in Section 2.3.2.

The total duration of the ramp time must also be estimated. From the startup plots of Figures 3

through 5, it is almost intuitive that this value not only depends on the IMAX tolerance, but is

also a function of the UVLO threshold and the input supply level. These voltage curves show

that an earlier load turn-on, and a higher voltage to charge to extend the total voltage ramp time.

Therefore, in order to use equation 26 to determine the total startup times (tSTM and tSTX), some

definitions are needed. First, the worst-case start time calculations should be performed for the

maximum input potential, in this case, –72 Vdc. Secondly, the load is assumed to be a constant

at the peak input current. But since the bus potential is at its maximum, the current calculated for

a –72 Vdc input will be used, or iL(t) = IIN(max′ ). Lastly, we will define a target DC voltage to be

100mV below the input DC level, or 71.9 V.

By sampling equation 26, first setting tVUV = tVUVM while IMAX = IMAXMAX, then for tVUV = tVUVX

when IMAX = IMAXMIN, the following startup times were determined:

For t = 12.78 ms, VINA(t) = 71.846 V (tSTX; IMAXMIN condition)

For t = 9.72 ms, VINA(t) = 71.892 V (tSTM; IMAXMAX condition)

The maximum time delay needed to guarantee hot-swap startup when using soft-start, tCTSS, is

calculated as:

tCTSS = MAX[ (tSTX – tFLT(MAX)), ( tSTM – tFLT(MIN)) ]

= 9.72 ms – 4.695 ms = 5.025 ms

It is interesting to note that, at least for this solution, the maximum timeout needed occurs under

the IMAXMAX condition.

Consider one final point regarding soft-start operation. Once capacitor C3 has charged up to its

dc level, it will remain charged as long as the board is powered. This means that soft-start

operation occurs only at insertion, and is disabled under any other conditions of turn-on,

including restart under the fault retry mode of operation, and also from a remote enable using

the SD input. Transistor Q2 is added to the circuit to provide a discharge path for C3 whenever

the output is turned off. The gate of Q2 is driven by the SDFL node, so that Q2 is turned on

whenever U1 asserts the fault output, or SDFL is pulled high externally. The soft-start reset

action of Q2 ensures that the HSPM soft-starts each time the output is turned on.

(27)

SLUA250

A Power Management Interface Circuit for Telecom Hot Swap with Local DC/DC Conversion

2.3.6 Step 6 – Set Average Power Limiting For Pass Fet; Determine Power Limiting

Resistor Value, R7

The UCC3921 can be configured for either of the two modes of operation during fault conditions,

latched mode or retry mode.

In retry mode, the device periodically turns on the FET switch Q1 and checks for continued fault

conditions. Timing control of this mode is automatically provided by the device. During retry

operation, U1 alternately charges C2 with a nominal 36-µA internal constant-current source

while Q1 is on, then discharges C2 at a nominal 1 µA while the output is off. This provides a

nominal 2.7% duty cycle. To select retry mode, resistor R4 in the Figure 1 schematic would not

be used (left open).

In latched mode, once a fault condition times out, the device latches off the pass element. In

order to restart the output, either the SDFL pin must be pulled to the shutdown level for > 1 ms,

or device power must be cycled. To select latched operation, install resistor R4 as shown. In this

mode, the need for power dissipation limiting is essentially negated; therefore, R7 would not be

installed.

When using the retry feature of the UCC3921, care must be taken not to exceed the dissipation

capability of the FET switch. Under normal (non-fault) operating conditions, the FET is fully

enhanced by the gate drive, and dissipation in the device is relatively low, assuming an

appropriate device has been selected for the application parameters. However, under

short-circuit conditions, the full-input potential appears across Q1 while it is on. The power limit

function gives the user a means of externally limiting the duty cycle of the external FET

switching, further reducing it below the nominal 2.7% level. This is done by sensing the output

voltage level, and providing additional charging current for the timing capacitor, through a

high-value resistor, based on the output level relative to the VSS node of the device, (i.e., the

voltage drop across the FET switch.) The total current now available for charging the timing

capacitor, IQ, is now given by equation 28.

IQ+Iq)IPL

where:

•Iq = the device internal charging source, 36-µA nominal

•IPL = the current through the power limiting resistor

In Figure 1, R7, connected to the drain of Q1, is the power limiting resistor.

The IRF630 FET selected for this solution comes in the TO–220AB package, rated for a 62_C/W

thermal resistance, junction to ambient. Maximum operating junction temperature is specified as

150_C. For the 70_C ambient operating temperature specified in Section 1.2, the average

dissipation in Q1 will be limited to 1.0 W as a conservative level. The maximum allowable duty

cycle, D, can then be derived from equation 29:

D+PD(avg)

IMAXMAX VIN(max) [0.23%

Since this is significantly less than the HSPM guaranteed maximum of 3.7%, the power limiting

function will be used. Because 1/D >> 1, a good approximation of the timing capacitor

charge-current contribution required through R7 (IPL in equation 28) is obtained from

equation 30:

(28)

(29)

SLUA250

20 A Power Management Interface Circuit for Telecom Hot Swap with Local DC/DC Conversion

IPL +Idq(max)

D*Iq(min)

where:

• Idq(MAX) = maximum capacitor discharge current into the U1 CT pin

• Iq(MIN) = the minimum charging current sourced from CT

Substituting the values from the UCC3921 data sheet for Idq(max) and Iq(min) ,the required power

limiting current is determined to be about 634 µA. The value of R7 is then found from

equation 31:

R7 +VIN *VPLIM

IPL

The obvious worst-case dissipation in the FET occurs when input voltage and drain output

current are at their maximum. Therefore, the value of 72 V is substituted for VIN, and the

calculated value for R7 is:

R7 +72 V *5.0 V

634 mA+105.7 kW

A standard 5% value suffices for this function. R7 is set to 100 kΩ.

2.3.7 Step 7 – Determine value for fault timing capacitor C2

The power-limiting current required, and subsequently the value of R7, are determined under

worst-case dissipation conditions (e.g., a short-circuit across the input capacitors). However,

during a normal startup voltage ramp, input voltage to the ISRs is not shorted, but ramps up

according to the appropriate equations. Therefore, the timing current IPL is not a constant under

these conditions, but decreases over the period of the input ramp from a maximum value of

ǒVIN *VPLIMǓ

R7 .

Approximating the input transient as a linear ramp, the average current through R7 is estimated

from equation 33.

IPL(avg) +ǒVDC *VPLIMǓ

2 R7 +ǒVIN(max) *VPLIMǓ

2 R7

Therefore, the minimum value of capacitor C2 needed to ensure startup of the output is:

C2 +ƪIq(max) )IPL(avg)ƫ tCT

dVCT

where:

• Iq(max) = maximum charging current sourced from CT

• tCT = required fault time delay

• dVCT = the delta-V that must be developed across C2 for the UCC3921 to detect a fault

(30)

(31)

(32)

(33)

(34)

SLUA250

A Power Management Interface Circuit for Telecom Hot Swap with Local DC/DC Conversion

From the device data sheet, the minimum fault threshold at the CT input pin is given as 2.20 V,

and the maximum level for fault reset is 0.57 V. However, for latched mode of operation, only the

initial fault timeout is of concern, in which case the voltage at CT is ramping up from 0 V. This

allows selection of a slightly smaller value for C2 than if retry mode is used, as shown in

equations 35 and 36.

For retry mode:

C2 +ƪIq(max) )IPL(avg)ƫ tCT

ǒVLS *VLRǓ

where:

•VLS = the internal fault latch SET threshold

•VLR = the internal fault latch RESET threshold

For latched mode:

C2 +ƪIq(max) )IPL(avg)ƫ tCT

VLS

Since the proposed solution makes use of input current slewing, the tCTSS value calculated in

Section 2.3.5 Step 5 – Estimating Ramp TIme is used. Substituting tCT = tCTSS ≅ 5 ms, the calculated

value of C2 is about 0.88 µF, and a standard value of 1.0 µF was used in the solution.

2.3.8 Step 8. Set resistor R3 value

Resistor R3 is the supply biasing resistor for the UCC3921. The maximum supply current

required by the HSPM IC to maintain the internal-shunt-regulator voltage within the data sheet

specifications is 2.0 mA. A value of 2.5 mA was used in the development of this solution to

provide some margin and bias the IMAX divider network when the supply voltage is at its

minimum potential. To provide this minimum bias current, the value of R3 is defined by:

R3 +ǒVIN *VREFǓ

0.0025

So, the maximum allowable value of R3 is provided by:

R3 +ǒVIN(min) *VREF(max)Ǔ

0.0025 +36 V *10.15 V

0.0025 A ^10 kW

At maximum bus potential conditions (–72 V), about 6.64 mA of current could flow through R3

(assuming a 5% tolerance resistor); which is well below the specification maximum of 50 mA.

Also, this corresponds to a maximum power dissipation of about 420 mW; therefore, a 1-W-rated

resistor is used in this application.

3 Additional Features

The design of the basic power management interface is now complete. The main functions of

hot swapping the –48-Vdc input and converting it to local VDD levels is accomplished through

the circuitry described previously. However, there are some additional features which can be

easily implemented. Two of these functions, which see frequent usage in power management,

are presented in the following sections. First, this report describes a host interface to provide a

remote shutdown/enable input (SD) and fault indication to the system. Secondly, an inexpensive

circuit is shown for shifting the UVLO threshold of the PT332x module.

(35)

(36)

(37)

(38)

SLUA250

22 A Power Management Interface Circuit for Telecom Hot Swap with Local DC/DC Conversion

3.1 Host Interface to SDFL Pin

Pin 1 of the UCC3921 is a three-function pin. The use of a resistive pull-down at this pin to

select the fault mode of operation is described in Section 2.3.6, Step 6 –Set Average Power

Limiting For Pass Fet; Determine Power Limiting Resistor Value, R7. This pin is also an active-high

input for turning off the external FET (shutdown), and provides an output fault indication.

However, the signal levels at this pin are referred to the VSS node of the circuit (i.e., the VSS pin

of U1). An interface circuit is needed to translate these signals to a system ground reference,

and generate the FLT output and the SD input, as shown in the top level schematic. Figure 6 is

the Figure 1 diagram redrawn to show the details of one interface implementation.

UDG–00143

C1 0.1µF

C2 1.0 µF

1.0 MΩ

82 kΩ

13 kΩ

1.0 µ F

10 kΩ, 1 W

0.025 Ω

1 W, 1%

MBR3100

3 AG, 2 A

MBR3100

3 AG, 2 A

100 kΩ

100 µF

100 V

330 µF

6.3 V

–48VDC_N1

–48VDC_N2

2N7000

IRF530

SDFL

IMAX

VDD

CT VSS

SNS

OUT

UCC3921

R13

0Ω

VIN+

VIN–

INH

N/C

+SNS

VOUT+

VOUT–

–SNS

ADJ

PT3325

VIN+

VIN–

INH

N/C

+SNS

VOUT+

VOUT–

–SNS

ADJ

PT3326

330 µF

6.3 V

100 µF

100 V

+1.8VDC

+2.5VDC

LCLRTN

R17

0Ω

UVLO

VIN–

GND

FLT

HOST_VDD R12

62 kΩ

R10

10 kΩ

R11

270 kΩ

10 kΩD3

1N4148

120 kΩ

ZVN3310A

ZTX553

ZVP3310A

Figure 6. Schematic Diagram with Host Interface Details

The FAULT output translation is comprised of the circuit of R8, R9 and Q5. Under normal

operating conditions, U1 sinks a nominal 100 µA at pin 1. This keeps the gate of Q5 discharged.

With Q5 turned off, R8 applies a pull-up to the HOST_VDD potential at the FLT output, indicating

normal operation.

During any condition that causes the HSPM device to turn off the gate drive to the FET Q1, the

SDFL output attempts to drive to the UCC3921 VDD rail. Device Q5 turns on, and R8 and R9

form a divider on the HOST_VDD to VSS potential. From the divider equation for the fault signal

level, the following equation for R9 is derived.

R9 +VFLT#

ǒHVDD *VSS *VFLT#Ǔ R8 (39)

SLUA250

A Power Management Interface Circuit for Telecom Hot Swap with Local DC/DC Conversion

where:

•VFLT# = the voltage level of the FLT signal line

•HVDD = the voltage level of the system HOST_VDD supply

•VSS = the VSS node potential of the plug-in module

If the maximum assertion level of FLT, VFLT#(max), is defined to be 0.5 V maximum, then:

VFLT#(max) +0.5 V +0.5 V *ǒ*VSS(min)Ǔ+36.2 V ,

when referenced to the module VSS node, and allowing for about a 300-mV drop across the

Schottkys and fuses when the load is not powered. For this condition, the maximum value that

should be used in the R9 position is given by equation 41.

R9(max) +VFLT#(max)

ǒHVDD *VSS(min) *VFLT#(max)Ǔ R8

Substituting the system values into equation 41, and setting R8 to a nominal 10 kΩ, the resulting

R9 value is:

R9 +36.2 V

[3.3 V *(*35.7 V)*36.2 V] 10 kW^129 kW

The next lowest 5% value of 120 kΩ was used for R9. Now, the minimum voltage level for fault

assertion can be determined from:

VFLT#(min) +ƪǒR9

(R8 )R9)Ǔ ǒHVDD *VSS(max)Ǔƫ)VSS(max)

+ƪǒ120 kW

130 kWǓ (3.3 V )72 V)ƫ*72V ^*2.5V

Due to the possibly large signal level below the host or system ground potential, small-signal

diode D3 is used as shown in the schematic to clamp the assertion level at about 0.5 V below

the GND node.

The interface block of circuitry must also provide level-shift of the host shutdown or enable input,

SD in the schematic. A brief description of the circuit operation follows.

To turn on the HSPM output, the SD input is pulled high by the host controller. Since the Q3 gate

is tied to the system GND node, Q3 turns on and provides a strong pull-up on the base of

transistor Q4, above the emitter potential. With Q4 off, the internal pull-down at U1 pin 1 is

dominant, and the output pulls to a low state. This enables the hot swap controller to turn on the

pass FET Q1.

When shutdown is asserted (SD pulls low), FET Q3 turns off. Resistor R11 can now pull the Q4

base towards VSS, and Q4 turns on. Q4 now sources sufficient current from the GND potential to

overcome the internal pull-down, pulling pin 1 above the shutdown input threshold. The HSPM

IC subsequently turns off Q1.

(40)

(41)

(42)

(43)

SLUA250

24 A Power Management Interface Circuit for Telecom Hot Swap with Local DC/DC Conversion

The use of the two-transistor (Q3/Q4) level shifter as shown in figure 6 provides an additional

feature. If at some point the host VDD supply fails while the controlled module is plugged in, the

module outputs will be automatically disabled via the HSPM circuit. Loss of the host supply

would mean loss of the SD drive to the Q3 source, turning off P-FET Q3. Since the Q4 emitter is

tied to the GND node, as opposed to a backplane-side input signal, Q4 is still able to source

shutdown current into the SDFL pin.

A quick methodology is given here to determine recommended values for resistors R11 and

R12. Per the device specification, the SDFL input has a maximum shutdown threshold of

(VDD + 1) V. In addition, this pin may sink a maximum of 250 µA. Therefore, R11 and R12 must

be selected to ensure that PNP transistor Q4 can source a minimum of 250 µA while pulling the

pin high.

Under minimum input supply conditions, the drop across limiting resistor R12 is given by:

VR12(min) +*VSS(min) *VEC(max) *VSD(max)

Set up this level translator to keep Q4 in saturation under minimum supply conditions. For the

ZTX553 transistor, the maximum VCE is specified as –250 mV at a gain of 10. The drop across

R12 is:

VR12(min) +35.5 V *0.25 V *11 V +24.25 V

Under the same conditions the current consumed by latching resistor R4 is

IR4(max) +VSD(max)

R4MIN ^141 mA (assuming a 5% tolerance resistor is used). Therefore, the

maximum value of R12 that can ensure shutdown control is determined by equation 46.

R12(max) +VR12(min)

ǒIR4(max) )ISD(max)Ǔ+62 kW

The drive current that will be needed, and the value for R11 to provide that current can be found

from the following.

IB(Q4) uVR12(min)

[R12(max) 10]+24.25 V

[(1.05 R12) 10]^37 mA

and,

R11 tƪ*VR12(min) *0.6V *ǒ*VSS(min)Ǔƫ

IB(Q4)

+[*24.25 V *0.6 V *(*35.5 V)]

37 mA^288 kW

The closest available 5% tolerance value is 270 kΩ.

(44)

(45)

(46)

(47)

(48)

SLUA250

A Power Management Interface Circuit for Telecom Hot Swap with Local DC/DC Conversion

3.2 Alternate Host Interface

The interface circuit described in Section 3.1 (Figure 6) would be useful when the ON/OFF

control-electronics’ biasing supply (the HOST_VDD input) and the control lines are referenced to

the GND node. This is also the return line for the two –48 V power busses. However, in a truly

isolated system, logic supply returns would not have a common connection with the power

section. Therefore, Figure 7 illustrates an optional interface configuration to maintain isolation

from the power bus.

In the Figure 7 circuit, the return of the two DC/DC converters (LCLRTN) is used as the

reference for the I/O signals (SD and FLT). Opto-couplers maintain isolation from the primary

side. The pull-up on the FLT line is shown on the plug-in schematic to provide extra detail.

However, this pull-up can just as easily be located in the control module or board, eliminating the

need for bussing the HOST_VDD to the controlled slot altogether.

UDG–00147

270 kΩ

4N29

62 kΩ

43 kΩ

1 kΩ

4ZTX553

4N29

ZTX453

10 kΩ

TO U1 SDFL

TO U1 VSS

10 kΩ

HOST_VDD

FLT

LCLRTN

Figure 7. Alternate Host/System Interface for Isolated Controller

3.3 Optional UVLO Circuit

The solution developed through the steps of Section 2.3, Circuit Design Procedure, assumes

that the internal UVLO circuit of the PT3320 regulators is used. However, during a live insertion,

any current consumed by the load, in this case, the two ISRs, is not available for charging up the

input capacitance (C5 and C7). For a given maximum current-sourcing level, as controlled by

the UCC3921, faster charging of this load capacitance can be achieved when the source does

not have to also supply the regulators and secondary-side load. Therefore, when the operating

input supply range allows, or if using different converters, or where large input capacitance

exists, it may be desirable to keep the load disabled until the input voltage has achieved a higher

potential. One way of doing this is to shift the threshold of the UVLO function upward.

SLUA250

26 A Power Management Interface Circuit for Telecom Hot Swap with Local DC/DC Conversion

The Figure 8 schematic shows the details of an undervoltage lockout sub-circuit achieved with a

few discrete components. The circuit is driven by the supply voltage across the VIN terminals of

U2 and U3. During the input ramp-up transient, diode D4 keeps transistor Q6 off until its

breakdown voltage is exceeded. R16 is then able to bias Q7 on, which pulls the converter INH

pins to the VIN– potential. This keeps the converter outputs off.

Once the converter input voltage exceeds the D4 Zener threshold, D4 conducts, turning on Q6.

Q6 acts to pull the Q7 base low, which turns Q7 off. The inhibit control circuitry of the PT3320

modules features a nominal 10-µA pull-up. With external transistor Q7 presenting a high

impedance, the INH input is internally pulled high, above the enable threshold of 2.5 V, and the

converters start up. Using the 39-V Zener diode as shown in the schematic should provide a

UVLO function of 39 V to 41 V.

UDG–00146

C1 0.1µF

C2 1.0 µF

1.0 MΩ

82 kΩ

13 kΩ

1.0 µ F

10 kΩ, 1 W

0.025 Ω

1 W, 1%

MBR3100

3 AG, 2 A

MBR3100

3 AG, 2 A

100 kΩ

100 µF

100 V C6

330 µF

6.3 V

GND

FLT

HOST_VDD

2N7000

IRF530

SDFL

IMAX

VDD

CT VSS

SNS

OUT

UCC3921

R13

0Ω

VIN+

VIN–

INH

N/C

+SNS

VOUT+

VOUT–

–SNS

ADJ

PT3325

VIN+

VIN–

INH

N/C

+SNS

VOUT+

VOUT–

–SNS

ADJ

PT3326

330 µF

6.3 V

100 µF

100 V

LCLRTN

R17

0Ω

VIN–

ZTX453

R16

510 kΩ

ZTX453

R12

R15

10 kΩ

R14

10 kΩ

1N5259B

39 V

ZTX553

R10

10 kΩ

R11

270 kΩ

10 kΩD3

1N4148

120 kΩ

ZVN3310A

+1.8VDC

+2.5VDC

–48VDC_N1

–48VDC_N2

ZVP3310A

62kΩ

Figure 8. Complete Detailed Application Circuit

4 Performance Evaluation and Sample Waveforms

The oscilloscope plots presented in this section demonstrate the operation of the circuit shown

in Figure 8. To obtain these figures, the external UVLO circuit was disabled, so that the DC/DC

turn-on is controlled by the on-board UVLO circuit. The HOST_VDD supply was set to a nominal

3.3 V. Unless stated otherwise, the ISR outputs were each loaded at 6.0 A. Generally, the scope

channel connections in the plot labels refer to the node names in any of the preceding

schematics; IIN refers to input current into the plug-in module.

SLUA250

A Power Management Interface Circuit for Telecom Hot Swap with Local DC/DC Conversion

Figure 9 shows the input voltage ramp-up and output turn-on following a live insertion event,

with the supply voltage at –48 Vdc. In Figures 9 and 10, hot swap was performed with the

–48VDC_N1 making last. Both figures demonstrate the smooth ramp of the converter input

voltage, (i.e., the voltage across filter capacitors C5 and C7) Figure 10 shows the nearly linear

ramp of the inrush current during the voltage ramp. Of particular interest is that the startup delay

of the converters (from VIN reaching the UVLO threshold) is such that the outputs do not ramp

until after the input ramp is complete.

Figure 9. Hot-Swap Startup Sequence

500 mA

–48VDC_N1

50 V/div

VIN–

20 V/div

1.8VDC OUT

2 V/div

2.5VDC OUT

2 V/div

VIN = –48 Vdc

IMAXNOM

t – Time – 2.5 ms/div

–48VDC_N1

50 V/div

VIN–

20 V/div

IIN

1 A/div

t – Time – 2.5 ms/div

Figure 10. Hot-Swap Startup Input V/I Profile

SLUA250

28 A Power Management Interface Circuit for Telecom Hot Swap with Local DC/DC Conversion

Figures 11, 12, and 13 show the insertion waveforms for a –72 Vdc bus potential, for an HSPM

IC operating at the minimum, maximum and nominal sourcing current levels, respectively.

Figure 11. IMAXMIN Startup Waveforms

t – Time – 2.5 ms/div

VIN = –72 Vdc

IMAXMIN

–48VDC_N1

50 V/div

VIN–

50 V/div

IIN

1 A/div

–48VDC_N1

50 V/div

VIN–

50 V/div

IIN

1 A/div

Figure 12. IMAXMAX Startup Waveforms

t – Time – 2.5 ms/div

VIN = –72 Vdc

IMAXMAX

Figure 13. IMAXNOM Startup Waveforms

–48VDC_N1

50 V/div

VIN–

50 V/div

IIN

1 A/div

VIN = –72 Vdc

IMAXNOM

t – Time – 2.5 ms/div

Figure 12, at –72 Vdc input and IMAXMAX was generated under conditions closely representing

the worst-case scenario for starting up with a fully discharged plug-in (tCTSS determination in

Section 2.3.5 Step 5 – Estimating Ramp TIme). The Figure 12 waveforms confirm that the module

starts up smoothly even under this condition. Also, it can be seen that at this input potential, with

the extension in rampup time, the turn-on of the two converter modules occurs during the input

ramp-up transient.

SLUA250

A Power Management Interface Circuit for Telecom Hot Swap with Local DC/DC Conversion

In order to verify some of the equations used in Section 2.3, Circuit Design Procedure, in

determining circuit component values, some theoretical input voltage ramp times and peak

inrush levels were calculated using equations 19 and 26, under some sample circuit conditions.

These start times and peak currents, shown in the Calculated columns in Table 3, were

determined for an HSPM IC operating at its nominal, minimum and maximum current limit

thresholds. A nominal ISR UVLO threshold of 33 Vdc was assumed. These values were then

checked against measurements obtained from the transient waveforms of Figures 9 through 13,

and similar plots. The results are summarized in Table 3.

Table 3. Startup Time and Peak Current Comparison

SUPPLY

VOLTAGE

TOTAL STARTUP TIME

(ms) PEAK CURRENT

(A) CONDITIONS

VOLTAGE

Calculated Measured Calculated Measured

CONDITIONS

8.825 7.85 2.403 2.26 IMAXNOM

–48 Vdc 10.05 9.05 2.164 1.90 IMAXMIN

Vdc

7.67 7.15 2.705 2.48 IMAXMAX

11.13 10.70 2.805 2.66 IMAXNOM

–72 Vdc 12.685 12.15 2.505 2.26 IMAXMIN

Vdc

9.66 9.30 3.183 3.0 IMAXMAX

Table 3 shows good correlation between the anticipated and actual startup times. In general, the

actual ramps were about 1 ms faster at the –48-Vdc input level. The primary factor for this is

most likely the delay in ISR output turnon, which means that the use of the maximum input

current estimates for IL(t) in equation 24 is overly conservative. For the –72-Vdc input case, the

start time estimates are only about 500 µs too high; not surprising because at this supply level,

the converters do start supplying the load currents prior to the end of the input voltage ramp.

The waveform graphics in Figures 14 and 15 demonstrate the startup from SD deassertion. For

the Figure 15 plot, the soft-start capacitor C3 was removed to show the transient current clamp

at the IMAX level. The nominal current limit obtained is the 4.8-A theoretical value. In addition,

the –48VDC_N1 traces demonstrate the extent of the disturbance on the supply bus. At

200 mV/div (Figure 15), the bus transients are only about +600/–100 mV about the steady-state

level, even without inrush current slewing.

SLUA250

30 A Power Management Interface Circuit for Telecom Hot Swap with Local DC/DC Conversion

Figure 14. Startup from SD Deassertion

–48VDC_N1

100 mV/div

VIN–

50 V/div

IIN

1 A/div

VIN = –48 Vdc

IMAXNOM

CH1 ac Coupled

t – Time – 1 ms/div

Figure 15. Startup from SD – No Soft-Start

–48VDC_N1

200 mV/div

VIN–

50 V/div

IIN

2 A/div

VIN = –48 Vdc

IMAXNOM

CH1 ac Coupled

t – Time – 500 s/div

Figure 16 shows another hot swap event at the –48-Vdc supply level, with the time base

expanded to view the inrush current ramp under soft–start. Using the 10% and 90% points, the

average di/dt obtained with the circuit was determined to be:

(2.0 A *0.222 A)

6.52 ms ^0.27 A

ms .

Recall that capacitor C3 was selected in Step 4 for a maximum slew rate of 0.5 A per ms;

therefore, the average di/dt obtained is approximately half that value.

Figure 16. Slew Rate Calculation

–48VDC_N1

50 V/div

VIN–

20 V/div

IIN

1 A/div

VIN = –48 Vdc

IMAXNOM

t = 6.52 ms

t – Time – 1 ms/div

t10

t90

The waveforms in Figures 17 and 18 demonstrate the operation of the FLT output during startup

(Figure 17) and shut-down (Figure 18) sequences, when initiated from the SD input.

SLUA250

A Power Management Interface Circuit for Telecom Hot Swap with Local DC/DC Conversion

Figure 17. FLT Output Operation During Startup

5 V/div

FLT

1 V/div

VIN–

50 V/div

2.5VDC OUT

2 V/div

VIN = –48 Vdc

IMAXNOM

t – Time – 2.5 ms/div Figure 18.

FLT Output Operation During Shutdown

5 V/div

FLT

1 V/div

VIN–

50 V/div

2.5VDC OUT

2 V/div

VIN = –48 Vdc

IMAXNOM

t – Time – 100 ms/div

Figure 19 shows the circuit response should the HOST_VDD supply be removed or fail. As

desired, the pass FET is switched off, and the FLT output is asserted. The input voltage to the

ISRs decays in a manner dictated by the load characteristics. There is an initial step drop in

voltage, and then, when the input hits the UVLO threshold, the ISRs turn off, and the 200-µF

bulk capacitance is discharged by leakage only.

Figure 19. Shutdown for HOST_VDD Failure

HOST_VDD

5 V/div

1 V/div

VIN–

20 V/div

VIN = –48 Vdc

t – Time – 100 ms/div

FLT

SLUA250

32 A Power Management Interface Circuit for Telecom Hot Swap with Local DC/DC Conversion

The next two scope plots show the circuit’s fault response to a short-circuit condition at the

DC/DC converter inputs. Figure 20 depicts initial normal steady-state operation with a –48 V dc

input supply and about an 800-mA load, from the IIN trace. With the sudden application of a

short (see VIN–trace), the HSPM IC clamps the short-circuit current at approximately 4.8 A,

times out in about 6 ms, and ultimately latches the pass FET off. Figure 21 shows attempted

startup into a short across the VIN terminals of the converters. The input current slews up as

programmed, but no voltage develops across the converter inputs (VIN– scale is 1V/div), and

the HSPM again times out and latches off. In this case, the total time-out is longer than that

shown in Figure 20. Recall that the fault timer does not start until the input current exceeds the

nominal 2-A overcurrent threshold.

Figure 20. Short-Circuit at Converter Inputs

VIN–

20 V/div

5 V/div

IIN

2 A/div

VIN = –48 Vdc

IMAXNOM

t – Time – 1 ms/div

FLT

Figure 21. Startup into Shorted ISR Input

VIN–

1 V/div

–48VDC_N1

50 V/div

IIN

1 A/div

VIN = –48 Vdc

IMAXNOM

t – Time – 2.5 ms/div

The scope plots of Figures 22 and 23 demonstrate the short-circuit response of the PT3320

converters. In Figure 22, the module is initially operating steady-state with –48-V input, and a

6-A load on each of the ISR outputs. When a short-circuit is applied to the +1.8 Vdc output, the

converter shuts off, then periodically pulses on to test for a continued fault condition (IOUT trace).

Because of the voltage step-down, the input current peaks remain below the HSPM overcurrent

threshold, and the HSPM does not trigger. Because of this, the second output (+2.5 Vdc, not

shown), can continue to operate normally. Applying a short to the +2.5V output produces the

corresponding pulsed current response. Figure 23 is a plot of the same fault conditions, but with

the power bus at a –36 V potential.

SLUA250

A Power Management Interface Circuit for Telecom Hot Swap with Local DC/DC Conversion

Figure 22. Output Short-Circuit Response

(–48-V Supply)

5 A/div

1.8VDC OUT

2 V/div

IIN

1 A/div

t – Time – 1 ms/div

IOUT 5 A/div

1.8VDC OUT

2 V/div

IIN

1 A/div

Figure 23. Output Short-Circuit Response

(–36-V Supply)

t – Time – 1 ms/div

IOUT

5 Notes

1. The PT3327 module produces a nominal 1.8 Vdc output voltage. However, the PT332x

converters also provide for output voltage adjustment from 90% to 110% of nominal value

using an external resistor. Due to sample availability at the time of this study, the 2-V

PT3325 unit was used, with output adjustment to 1.8-V using R17 in the Figure 1

schematic.

2. Since only three of the available devices in the series are characterized in the data sheet,

the PT3321 curves were used as the closest available output voltage/current match to the

modules used in this solution.

6 References

1. UCC3921 Latchable Negative Floating Hot Swap Power Manager; Data Sheet; Texas

Instruments Literature No. SLUS207; March 1998

2. PT3320 Series 30–Watt Isolated DC/DC Converter; Data Sheet; Texas Instruments Literature No.

SLTS018A; June 2000

3. Adjusting the Output Voltage of the Power Trends’ 30W Isolated DC/DC Converter Series,

Application Note; Texas Instruments Literature No. SLTS018A

4. Using the Inhibit Function of the Power Trends’ 30W Isolated DC/DC Converter Series,

Application Note; Texas Instruments Literature No. SLTS018A

5. ISR Input/Output Filters, Application Note; Texas Instruments Literature No. SLTA013A, June

2000

The UCC3921 device parameters used in this document are listed in the Table A–1for quick

reference. To aid the user in determining the source of these values, the corresponding data

sheet parameter name is shown. For a complete listing of the UCC3921 specifications, the user

is referred to the device data sheet.

SLUA250

34 A Power Management Interface Circuit for Telecom Hot Swap with Local DC/DC Conversion

Table 4. UCC3921 Hot Swap Power Manager Device Parameters

PARAMETER DATA SHEET REF CONDITIONS VALUE UNIT DESCRIPTION

VFLT(MIN) Overcurrent Threshold Over Op. Temp 46 mV Minimum fault threshold (Overcurrent Comparator)

VFLT(MAX) Over Op. Temp 53.5 mV Maximum fault threshold (Overcurrent Comparator)

VREF(MIN) Regulator Voltage 9.0 V Minimum shunt regulator voltage

VREF(NOM) 9.5 V Nominal shunt regulator voltage

VREF(MAX) 10.15 V Maximum shunt regulator voltage

VOS Input Offset Voltage VIMAX = 100mV ±15 mV VOS of the Linear Current Amplifier (LCA)

VIMAX = 400 mV ±30 mV

IBIAS LCA Input Bias 500 nA Input bias current on the LCA

Iq(MIN) CT Charge Current IPL = 0 22 µA Minimum CT charge current (overcurrent condition)

Iq(MAX) IPL = 0 50 µA Maximum CT charge current (overcurrent condition)

Idq(MAX) CT Discharge Current 1.5 µA Maximum CT discharge current

VLS CT Fault Threshold 2.2 V Minimum Fault Comparator SET threshold

VLR CT Reset Threshold 0.57 V Maximum Fault Comparator RESET threshold

VPLIM VSENSE Regulator 5.0 V Voltage at PL pin (sink condition)

VSD(MAX) Shutdown Threshold VDD + 1 V Maximum shutdown threshold

ISD(MAX) Input Current, SDFLTCH 250 µA Maximum IIH at SDFL pin

IMPORTANT NOTICE

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue

any product or service without notice, and advise customers to obtain the latest version of relevant information

to verify, before placing orders, that information being relied on is current and complete. All products are sold

subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those

pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its products to the specifications applicable at the time of sale in accordance with

TI’s standard warranty . T esting and other quality control techniques are utilized to the extent TI deems necessary

to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except

those mandated by government requirements.

Customers are responsible for their applications using TI components.

In order to minimize risks associated with the customer’s applications, adequate design and operating

safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent

that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other

intellectual property right of TI covering or relating to any combination, machine, or process in which such

products or services might be or are used. TI’s publication of information regarding any third party’s products

or services does not constitute TI’s approval, license, warranty or endorsement thereof.

Reproduction of information in TI data books or data sheets is permissible only if reproduction is without

alteration and is accompanied by all associated warranties, conditions, limitations and notices. Representation

or reproduction of this information with alteration voids all warranties provided for an associated TI product or

service, is an unfair and deceptive business practice, and TI is not responsible nor liable for any such use.

Resale of TI’s products or services with

statements different from or beyond the parameters

stated by TI for

that product or service voids all express and any implied warranties for the associated TI product or service,

is an unfair and deceptive business practice, and TI is not responsible nor liable for any such use.

Also see: Standard Terms and Conditions of Sale for Semiconductor Products. www .ti.com/sc/docs/stdterms.htm

Mailing Address:

Texas Instruments

Post Office Box 655303

Dallas, Texas 75265