AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Document No: AX11015/V1.09/06/14/2011 Features MCU 8-bit pipelined RISC, single cycle per instruction with maximum operating frequency of 100Mhz (100 MIPS) 100% software compatible with standard 8051/80390 4 GPIO ports of 8 bits 2 external interrupt sources with 2 priority levels Support power management unit, programmable watchdog timer, and 3 16-bit timer/counters Debug port for connecting to In-Circuit Emulation (ICE) adaptor 5 channels of programmable counter array On-chip Program and Data Memory Embed 512KB Flash memory, and 16KB SRAM for program code mirroring. The external program memory can grow up to 2MB without bank select Support initial Flash memory programming via UART or ICE adaptor, the so-called In System Programming (ISP) Support reprogrammable boot code and In Application Programming (IAP) to update run-time firmware or boot code through Ethernet or UART (US Patent Pending) Support boot loader to shadow program code on to internal 16KB SRAM and external SRAM for high performance applications Embed 32KB SRAM for data memory, expandable up to 2MB via external SRAM without bank select Buffer Management Innovative-shared memory architecture to allow external program and data memory to share the same SRAM memory chip with flexible memory space allocation Embed DMA engine and memory arbiter. Support 5 DMA channels for high performance data movement needed for network protocol stack processing On-chip 10/100M Fast Ethernet MAC and PHY Integrate IEEE 802.3 10BASE-T/100BASE-TX compatible Fast Ethernet MAC and PHY with dedicated 12KB SRAM for Ethernet packet buffering. Support full-duplex and half-duplex operations. Provide optional MII interface (for HomePNA and HomePlug) Support twisted pair crossover detection and auto-correction (HP Auto-MDIX) Support wakeup via Link-up, Magic packet, Wakeup frame, external input pin or UART TCP/IP Build in TCP/IP accelerator in hardware to improve network transfer throughput. Support IP/TCP/UDP/ICMP/IGMP checksum and ARP in hardware Support TCP, UDP, ICMP, IPv4, DHCP, BOOTP, ARP, DNS, SMTP, SNTP, uPNP, PPPoE and HTTP in software Communication Interface 3 UART interface (with 1 supporting 921.6Kbps and Modem control) Local bus host interface (master or slave mode) Support STMicroelectronics Digiport (10-bit data port) or SPI mode for receiving video data 1 I2C interface (master and slave mode) SPI/Micro wire interface (3 masters or 1 slave mode) 1 1-Wire controller interface (master mode) 10/100 Ethernet PHY interface Support network boot over Ethernet using BOOTP and TFTP Integrate on-chip voltage regulator and require single power supply of 3.3V only Integrate on-chip oscillator and PLL. Require only one 25Mhz crystal to operate Integrate on-chip power-on reset circuit 128-pin LQFP RoHS package Operating temperature: 0 to 70C or -40 to 85C *IEEE is a registered trademark of the Institute of Electrical and Electronic Engineers, Inc. *All other trademarks and registered trademark are the property of their respective holders. Product Description The AX11015, Single Chip Micro-controller with TCP/IP and 10/100M Fast Ethernet MAC/PHY, is a System-on-Chip (SoC) solution which offers a high performance embedded micro-controller and rich communication peripherals for wide varieties of application which need access to the LAN or Internet. With built-in network protocol stack, the AX11015 provides very cost effective networking solution to enable simple, easy, and low cost Internet connection capability for many applications such as consumer electronics, networked home appliances, industrial equipments, security systems, remote data collection equipments, remote control, remote monitoring, and remote management. Always contact ASIX Electronics for possible updates before starting a design. This data sheet contains new products information. ASIX Electronics reserves the rights to modify product specification without notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product. ASIX ELECTRONICS CORPORATION 4F, NO.8, Hsin Ann Rd., HsinChu Science Park, Hsin-Chu City, Taiwan, R.O.C. TEL: 886-3-579-9500 FAX: 886-3-579-9558 http://www.asix.com.tw Release Date: 06/14/2011 AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY In addition to stand-alone application, the AX11015 with popular TCP/IP protocol suite on-chip and built-in local bus host interface, I2C bus, or SPI bus, can be used as network co-processor to offload TCP/IP protocol processing loading from system CPU in an embedded system. Target Applications Figure 1: Target Application Diagram Typical System Block Diagrams Temperature Sensor I2C bus EEPROM Humidity Sensor Rain Gauge Sensor Barometric Pressure Sensor GPIO AX11015 1-Wire bus Relay LED Wind Direction Sensor Magnetic + RJ45 Solar Radiance Sensor Thermocouple Sensor Figure 2: Environment Monitoring or Network Sensor and Remote Control 2 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY RS232 Transceiver UART ZigBee Transceiver I2C bus SPI bus EEPROM AX11015 I2C bus EEPROM AX11015 Magnetic + RJ45 Magnetic + RJ45 Figure 3: Serial to Ethernet Converter Figure 4: ZigBee to Ethernet Converter BlueTooth Transceiver Low Speed PLC Transceiver UART UART or SPI I2C bus I2C EEPROM AX11015 AX11015 EEPROM Magnetic + RJ45 Magnetic + RJ45 Figure 5: BlueTooth to Ethernet Converter Figure 6: Low Speed PLC (Power Line Communication) to Ethernet Converter RS232 Transceiver UART I2C AX11015 EEPROM MII HomePlug PHY AFE + PLC coupling Figure 7: Serial to HomePlug (Power Line Communication) Converter 3 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Image Sensor Lens Motion JPEG or MPEG Encoder DRAM Local bus (master mode) or Digiport or SPI bus Ext. memory bus I2C bus SRAM EEPROM AX11015 Magnetic + RJ45 Figure 8: Network Camera Embedded CPU (ARM, MIPS, x86, PowerPC) TI DSP CPU Local bus (slave mode) or I2C bus or SPI bus Local bus (master mode) I2C bus AX11015 EEPROM I2C bus AX11015 EEPROM Magnetic + RJ45 Magnetic + RJ45 Figure 9: Network Co-processor for Embedded CPU Figure 10: Network Co-processor for DSP CPU Microphone + Speaker Audio Codec Local bus (master mode) I2C bus AX11015 EEPROM Magnetic + RJ45 Figure 11: Audio over Internet 4 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights reserved. DISCLAIMER No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, for any purpose, without the express written permission of ASIX. ASIX may make changes to the product specifications and descriptions in this document at any time, without notice. ASIX provides this document "as is" without warranty of any kind, either expressed or implied, including without limitation warranties of merchantability, fitness for a particular purpose, and non-infringement. Designers must not rely on the absence or characteristics of any features or registers marked "reserved", "undefined" or "NC". ASIX reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Always contact ASIX to get the latest document before starting a design of ASIX products. TRADEMARKS ASIX, the ASIX logo are registered trademarks of ASIX Electronics Corporation. All other trademarks are the property of their respective owners. 5 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Table of Contents 1.0 INTRODUCTION ................................................................................................................. 14 1.1 1.2 1.3 1.4 GENERAL DESCRIPTION ..................................................................................................................................... 14 AX11015 BLOCK DIAGRAM .............................................................................................................................. 14 AX11015 PINOUT DIAGRAM ............................................................................................................................. 15 SIGNAL DESCRIPTION ........................................................................................................................................ 16 2.0 FUNCTION DESCRIPTION................................................................................. 26 2.1 CLOCK GENERATION ......................................................................................................................................... 26 2.2 RESET GENERATION .......................................................................................................................................... 26 2.3 VOLTAGE REGULATOR ...................................................................................................................................... 26 2.4 CPU CORE AND DEBUGGER .............................................................................................................................. 27 2.4.1 CPU Core ................................................................................................................................................. 27 2.4.2 Debugger .................................................................................................................................................. 27 2.5 ON-CHIP FLASH MEMORY ................................................................................................................................. 29 2.6 MEMORY ARBITER AND BOOT LOADER............................................................................................................. 30 2.6.1 Boot Loader .............................................................................................................................................. 32 2.6.2 Memory Arbiter ........................................................................................................................................ 32 2.6.3 Flash Programming Controller ................................................................................................................ 32 2.7 DMA ENGINE .................................................................................................................................................... 33 2.8 INTERRUPT CONTROLLER .................................................................................................................................. 34 2.9 WATCHDOG TIMER ............................................................................................................................................ 35 2.10 POWER MANAGEMENT UNIT ............................................................................................................................. 36 2.10.1 PMM ......................................................................................................................................................... 36 2.10.2 STOP Mode............................................................................................................................................... 36 2.11 TIMERS AND COUNTERS .................................................................................................................................... 37 2.12 UARTS.............................................................................................................................................................. 38 2.12.1 UART 0 and UART 1 ................................................................................................................................ 38 2.12.2 UART 2 ..................................................................................................................................................... 38 2.13 GPIOS ............................................................................................................................................................... 39 2.14 TCP/IP OFFLOAD ENGINE ................................................................................................................................. 40 2.15 10/100M ETHERNET MAC ................................................................................................................................ 41 2.16 10/100M ETHERNET PHY ................................................................................................................................. 42 2.17 PROGRAMMABLE COUNTER ARRAY .................................................................................................................. 43 2.18 I2C CONTROLLER .............................................................................................................................................. 43 2.19 1-WIRE CONTROLLER ........................................................................................................................................ 44 2.20 SPI CONTROLLER .............................................................................................................................................. 45 2.21 LOCAL BUS INTERFACE AND DIGIPORT ............................................................................................................. 46 2.21.1 Local Bus Master Mode ............................................................................................................................ 47 2.21.2 Local Bus Slave Mode .............................................................................................................................. 50 2.21.3 Digiport Mode .......................................................................................................................................... 53 3.0 MEMORY MAP DESCRIPTION................................................................... 55 3.1 I2C CONFIGURATION EEPROM MEMORY MAP ................................................................................................ 55 3.1.1 Length (0x00) ............................................................................................................................................ 56 3.1.2 Flag (0x01) ............................................................................................................................................... 56 3.1.3 Multi-function Pin Setting (0x02~0x03) ................................................................................................... 57 3.1.4 Programmable Output Driving Strength (0x04) ....................................................................................... 59 3.1.5 Node ID (0x06~0x0B) ............................................................................................................................... 60 3.1.6 Maximum Packet Size (0x0C~0x0D) ........................................................................................................ 60 3.1.7 Primary/Secondary PHY Type and PHY ID (0x0E~0x0F) ....................................................................... 60 3.1.8 Pause Frame Low Water and High Water Mark (0x10~0x11) ................................................................. 60 3.1.9 Local Bus Setting (0x12~0x13) ................................................................................................................. 61 3.1.10 TOE TX VLAN Tag (0x14~0x15) .............................................................................................................. 63 6 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 3.1.11 TOE RX VLAN Tag (0x16~0x17).............................................................................................................. 63 3.1.12 TOE ARP Cache Timeout (0x18) .............................................................................................................. 63 3.1.13 TOE Source IP Address (0x19~0x1C) ...................................................................................................... 63 3.1.14 TOE Subnet Mask (0x1D~0x20) ............................................................................................................... 63 3.1.15 TOE L4 DMA Transfer Gap (0x21) .......................................................................................................... 63 3.2 PROGRAM MEMORY MAP .................................................................................................................................. 64 3.3 EXTERNAL DATA (XDATA) MEMORY MAP ...................................................................................................... 65 3.4 INTERNAL DATA MEMORY AND SFR REGISTER MAP ........................................................................................ 65 4.0 DETAILED FUNCTION DESCRIPTION ......................................... 67 4.1 CLOCK GENERATION ......................................................................................................................................... 67 4.2 RESET GENERATION .......................................................................................................................................... 68 4.3 VOLTAGE REGULATOR ...................................................................................................................................... 69 4.4 CPU CORE AND DEBUGGER .............................................................................................................................. 70 4.4.1 CPU Core SFR Register Map ................................................................................................................... 71 4.4.2 CPU Core SFR Register Description ....................................................................................................... 72 4.4.3 Memory Allocation ................................................................................................................................... 73 4.4.4 Performance Improvement ....................................................................................................................... 80 4.4.5 Debugger .................................................................................................................................................. 86 4.5 ON-CHIP FLASH MEMORY ................................................................................................................................. 87 4.6 MEMORY ARBITER & BOOT LOADER ................................................................................................................ 99 4.6.1 Boot Loader .............................................................................................................................................. 99 4.6.2 Memory Arbiter ...................................................................................................................................... 102 4.6.3 Program and Data Memory Address Mapping ...................................................................................... 103 4.6.4 Flash Memory Address Re-mapping for the Lower 16KB Boot Sector .................................................. 105 4.6.5 Flash Memory Access in Program Code Shadow Mode ........................................................................ 108 4.6.6 Flash Programming Controller .............................................................................................................. 109 4.7 DMA ENGINE .................................................................................................................................................. 110 4.7.1 DMA Transfers for Ethernet Packet Receive and Transmit ................................................................... 110 4.7.2 DMA Transfers for Local Bus and Digiport Burst Read and Write ....................................................... 111 4.7.3 Software DMA ........................................................................................................................................ 111 4.7.4 DMA Arbitration ..................................................................................................................................... 117 4.8 INTERRUPT CONTROLLER ................................................................................................................................ 119 4.8.1 Interrupt Controller SFR Register Map .................................................................................................. 119 4.9 WATCHDOG TIMER .......................................................................................................................................... 125 4.9.1 Watchdog SFR Register Map .................................................................................................................. 125 4.9.2 Watchdog Interrupt ................................................................................................................................. 126 4.9.3 Watchdog Timer Reset ............................................................................................................................ 127 4.9.4 Simple Timer ........................................................................................................................................... 127 4.9.5 System Monitor ....................................................................................................................................... 127 4.9.6 Clock Control.......................................................................................................................................... 128 4.9.7 Timed Access Register ............................................................................................................................ 129 4.10 POWER MANAGEMENT UNIT ........................................................................................................................... 130 4.10.1 Power Management Unit SFR Register Map.......................................................................................... 130 4.10.2 Power Management Mode ...................................................................................................................... 131 4.10.3 STOP Mode............................................................................................................................................. 133 4.11 TIMERS AND COUNTERS .................................................................................................................................. 135 4.11.1 Timers 0, 1, 2 Related SFR Register Map............................................................................................... 135 4.11.2 Timer 0, 1 ................................................................................................................................................ 135 4.11.3 Timer 2 .................................................................................................................................................... 142 4.11.4 Millisecond Timer ................................................................................................................................... 144 4.12 UARTS............................................................................................................................................................ 145 4.12.1 UART 0, 1 SFR Register Map ................................................................................................................. 145 4.12.2 UART 0 ................................................................................................................................................... 145 4.12.3 UART 1 ................................................................................................................................................... 149 4.12.4 UART 2 ................................................................................................................................................... 153 4.13 GPIOS ............................................................................................................................................................. 163 4.13.1 GPIO SFR Register Map ........................................................................................................................ 163 7 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 4.14 TCP/IP OFFLOAD ENGINE ............................................................................................................................... 166 4.14.1 TOE SFR Register Map .......................................................................................................................... 169 4.14.2 L2_Engine Function Description............................................................................................................ 170 4.14.3 L3_Engine Function Description............................................................................................................ 176 4.14.4 L4_Engine Function Description............................................................................................................ 178 4.14.5 Packet Buffer Ring in xDATA Memory of 1T 80390 CPU...................................................................... 181 4.14.6 Packet Format in Packet Buffer Ring ..................................................................................................... 184 4.15 10/100M ETHERNET MAC .............................................................................................................................. 194 4.15.1 10/100M Ethernet MAC SFR Register Map ........................................................................................... 195 4.15.2 Ethernet MAC Receive Filtering ............................................................................................................. 196 4.15.3 Ethernet MAC Packet Transmit .............................................................................................................. 201 4.15.4 Ethernet MAC Buffer Management ........................................................................................................ 203 4.15.5 Magic Packet and Wakeup Frame .......................................................................................................... 205 4.16 10/100M ETHERNET PHY ............................................................................................................................... 212 4.16.1 MII Station Management Function ......................................................................................................... 213 4.16.2 10/100M Ethernet PHY SFR Register Map ............................................................................................ 213 4.17 PROGRAMMABLE COUNTER ARRAY ................................................................................................................ 219 4.17.1 Programmable Counter Array SFR Register Map ................................................................................. 219 4.17.2 PCA Timer/Counter ................................................................................................................................ 220 4.17.3 Compare/Capture Modules..................................................................................................................... 221 4.18 I2C CONTROLLER ............................................................................................................................................ 230 4.18.1 I2C Controller SFR Register Map .......................................................................................................... 231 4.18.2 I2C Slave Mode Function Description ................................................................................................... 237 4.19 1-WIRE CONTROLLER ...................................................................................................................................... 239 4.19.1 1-Wire Controller SFR Register Map ..................................................................................................... 239 4.20 SPI CONTROLLER ............................................................................................................................................ 245 4.20.1 SPI SFR Register Map ............................................................................................................................ 247 4.20.2 SPI Slave Mode Function Description.................................................................................................... 253 4.21 LOCAL BUS INTERFACE AND DIGIPORT ........................................................................................................... 257 4.21.1 Local Bus Interface and Digiport SFR Register Map ............................................................................. 260 4.21.2 Local Bus Master Mode .......................................................................................................................... 261 4.21.3 Local Bus Master Mode SFR Register Detailed Description ................................................................. 261 4.21.4 Local Bus Slave Mode ............................................................................................................................ 269 4.21.5 External CPU Register in Local Bus Slave Mode .................................................................................. 269 4.21.6 Local Bus Slave Mode SFR Register Detailed Description .................................................................... 274 4.21.7 Digiport .................................................................................................................................................. 282 4.21.8 Digiport Mode SFR Register Detailed Description ................................................................................ 282 5.0 ELECTRICAL SPECIFICATIONS .......................................................... 288 5.1 DC CHARACTERISTICS .................................................................................................................................... 288 5.1.1 Absolute Maximum Ratings .................................................................................................................... 288 5.1.2 Recommended Operating Condition ....................................................................................................... 288 5.1.3 Leakage Current and Capacitance ......................................................................................................... 289 5.1.4 DC Characteristics of 3.3V I/O Pins ...................................................................................................... 289 5.1.5 DC Characteristics of 3.3V with 5V Tolerant I/O Pins .......................................................................... 289 5.1.6 DC Characteristics of Voltage Regulator ............................................................................................... 290 5.2 POWER CONSUMPTION .................................................................................................................................... 291 5.3 POWER-UP SEQUENCE ..................................................................................................................................... 292 5.4 AC TIMING CHARACTERISTICS ........................................................................................................................ 293 5.4.1 Clock Timing ........................................................................................................................................... 293 5.4.2 External Memory Interface Timing......................................................................................................... 294 5.4.3 I2C Interface Timing............................................................................................................................... 298 5.4.4 SPI Interface Timing ............................................................................................................................... 299 5.4.5 1-Wire Interface Timing.......................................................................................................................... 301 5.4.6 Programmable Counter Array Interface Timing .................................................................................... 304 5.4.7 Timer 0/1/2 Interface Timing .................................................................................................................. 305 5.4.8 Local Bus Interface Timing..................................................................................................................... 306 5.4.9 Digiport Interface Timing ....................................................................................................................... 317 8 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 5.4.10 5.4.11 5.4.12 10/100M Ethernet PHY Interface Timing ............................................................................................... 318 MII Timing .............................................................................................................................................. 319 Station Management Timing ................................................................................................................... 320 6.0 PACKAGE INFORMATION ............................................................................. 321 7.0 ORDERING INFORMATION .......................................................................... 322 8.0 REVISION HISTORY .................................................................................................. 322 List of Figures FIGURE 1: TARGET APPLICATION DIAGRAM ........................................................................................................................ 2 FIGURE 2: ENVIRONMENT MONITORING OR NETWORK SENSOR AND REMOTE CONTROL .................................................... 2 FIGURE 3: SERIAL TO ETHERNET CONVERTER ..................................................................................................................... 3 FIGURE 4: ZIGBEE TO ETHERNET CONVERTER .................................................................................................................... 3 FIGURE 5: BLUETOOTH TO ETHERNET CONVERTER............................................................................................................. 3 FIGURE 6: LOW SPEED PLC (POWER LINE COMMUNICATION) TO ETHERNET CONVERTER.................................................. 3 FIGURE 7: SERIAL TO HOMEPLUG (POWER LINE COMMUNICATION) CONVERTER ............................................................... 3 FIGURE 8: NETWORK CAMERA ............................................................................................................................................ 4 FIGURE 9: NETWORK CO-PROCESSOR FOR EMBEDDED CPU................................................................................................ 4 FIGURE 10: NETWORK CO-PROCESSOR FOR DSP CPU ........................................................................................................ 4 FIGURE 11: AUDIO OVER INTERNET ..................................................................................................................................... 4 FIGURE 12: AX11015 BLOCK DIAGRAM ........................................................................................................................... 14 FIGURE 13: AX11015 PINOUT DIAGRAM .......................................................................................................................... 15 FIGURE 14: TYPICAL DEBUGGER AND HARDWARE ASSISTED DEBUGGER (HAD2) SYSTEM DIAGRAM............................. 28 FIGURE 15: SYSTEMS REQUIRING ONLY 512K BYTES OF PROGRAM FLASH AND 32K BYTES OF DATA MEMORY ............... 30 FIGURE 16: SYSTEMS REQUIRING 512K BYTES PROGRAM FLASH AND OVER 32K BYTES DATA MEMORY......................... 30 FIGURE 17: SYSTEMS REQUIRING OVER 512K BYTES PROGRAM FLASH AND OVER 32K BYTES DATA MEMORY............... 31 FIGURE 18: SYSTEMS REQUIRING 512K BYTES PROGRAM FLASH AND OVER 32K BYTES DATA MEMORY FOR HIGH PERFORMANCE .......................................................................................................................................................... 31 FIGURE 19: FLASH MEMORY PROGRAMMING SYSTEM CONFIGURATION ........................................................................... 33 FIGURE 20: WATCHDOG TIMER BLOCK DIAGRAM............................................................................................................. 35 FIGURE 21: TIMERS 0, 1, AND 2 BLOCK DIAGRAM ............................................................................................................. 37 FIGURE 22: I/O BUFFER OF RXD0 PIN OF UART 0 AND RXD1 PIN OF RXD1 ................................................................... 38 FIGURE 23: THE I/O BUFFER OF GPIO PINS ...................................................................................................................... 39 FIGURE 24: INTERNAL DATA PATH DIAGRAM OF 10/100M ETHERNET MAC, 10/100 ETHERNET PHY, AND MII INTERFACE .................................................................................................................................................................................. 41 FIGURE 25: INTERNAL CONTROL MUX FOR STATION MANAGEMENT INTERFACE .............................................................. 42 FIGURE 26:PROGRAMMABLE COUNTER ARRAY BLOCK DIAGRAM .................................................................................... 43 FIGURE 27: I2C CONTROLLER BLOCK DIAGRAM ............................................................................................................... 44 FIGURE 28: 1-WIRE CONTROLLER BLOCK DIAGRAM ........................................................................................................ 44 FIGURE 29: SPI CONTROLLER BLOCK DIAGRAM ............................................................................................................... 45 FIGURE 30: LOCAL BUS INTERFACE AND DIGIPORT BLOCK DIAGRAM .............................................................................. 46 FIGURE 31: INTERFACING WITH ISA BUS STYLE DEVICES IN LOCAL BUS MASTER MODE ................................................ 48 FIGURE 32: INTERFACING WITH INTEL 80186 BUS STYLE DEVICES IN LOCAL BUS MASTER MODE .................................. 48 FIGURE 33: INTERFACING WITH INTEL 80386 BUS STYLE DEVICES IN LOCAL BUS MASTER MODE .................................. 48 FIGURE 34: INTERFACING WITH MOTOROLA 68000/10 BUS STYLE DEVICES IN LOCAL BUS MASTER MODE .................... 49 FIGURE 35: INTERFACING WITH THE HPI OF TI DSP CHIPS IN LOCAL BUS MASTER MODE............................................... 49 FIGURE 36: INTERFACING WITH SYSTEM CPU WITH ISA BUS STYLE IN LOCAL BUS SLAVE MODE .................................. 50 FIGURE 37: INTERFACING WITH SYSTEM CPU WITH INTEL 80186 LOCAL BUS STYLE IN LOCAL BUS SLAVE MODE ......... 51 FIGURE 38: INTERFACING WITH SYSTEM CPU WITH INTEL 80386 LOCAL BUS STYLE IN LOCAL BUS SLAVE MODE ......... 51 FIGURE 39: INTERFACING WITH SYSTEM CPU WITH MOTOROLA 68000/10 LOCAL BUS STYLE IN LOCAL BUS SLAVE MODE .................................................................................................................................................................................. 51 9 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY FIGURE 40: INTERFACING WITH SYSTEM CPU WITH MOTOROLA 68030/40 LOCAL BUS STYLE IN LOCAL BUS SLAVE MODE .................................................................................................................................................................................. 52 FIGURE 41: INTERFACING WITH SYSTEM CPU WITH RENESAS SH3 LOCAL BUS STYLE IN LOCAL BUS SLAVE MODE ...... 52 FIGURE 42: INTERFACING WITH SYSTEM CPU WITH RENESAS SH4 LOCAL BUS STYLE IN LOCAL BUS SLAVE MODE ...... 52 FIGURE 43: INTERFACING WITH STV0676 IN DIGIPORT PARALLEL MODE ......................................................................... 53 FIGURE 44: INTERFACING WITH STV0684 IN DIGIPORT SPI MODE .................................................................................... 54 FIGURE 45: THE PROGRAM MEMORY MAP OF 1T 80390 CPU CORE (PROGRAM NON-SHADOW MODE) ............................ 64 FIGURE 46: THE PROGRAM MEMORY MAP OF 1T 80390 CPU CORE (PROGRAM SHADOW MODE) .................................... 64 FIGURE 47: THE EXTERNAL DATA MEMORY MAP OF 1T 80390 CPU CORE ..................................................................... 65 FIGURE 48: THE INTERNAL MEMORY MAP OF 1T 80390 CPU CORE ................................................................................. 65 FIGURE 49: AX11015 CLOCK GENERATION BLOCK DIAGRAM ......................................................................................... 67 FIGURE 50: AX11015 RESET GENERATION BLOCK DIAGRAM .......................................................................................... 68 FIGURE 51: AX11015 RESET TIMING DIAGRAM................................................................................................................ 68 FIGURE 52: CPU CORE BLOCK DIAGRAM ......................................................................................................................... 70 FIGURE 53: STACK BYTES ORDER ..................................................................................................................................... 79 FIGURE 54: ON-CHIP FLASH MEMORY BLOCK DIAGRAM .................................................................................................. 87 FIGURE 55: AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART ....................................................................................... 90 FIGURE 56: AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART .................................................................................. 91 FIGURE 57: ERASE SUSPEND/ERASE RESUME FLOWCHART ............................................................................................... 92 FIGURE 58: AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART ................................................................................. 93 FIGURE 59: DATA# POLLING ALGORITHM ......................................................................................................................... 95 FIGURE 60: TOGGLE BIT ALGORITHM................................................................................................................................ 97 FIGURE 61: BOOT LOADER, MEMORY ARBITER & FLASH PROGRAMMING CONTROLLER BLOCK DIAGRAM ..................... 99 FIGURE 62: CPU PROGRAM MEMORY MAP (EXT_PROG_SRAM_EN = 0)................................................................... 103 FIGURE 63: CPU PROGRAM MEMORY MAP (EXT_PROG_SRAM_EN = 1)................................................................... 103 FIGURE 64: CPU PROGRAM MEMORY AND XDATA MEMORY MAP (EXT_PROG_SRAM_EN = 1) ............................. 104 FIGURE 65: CPU PROGRAM MEMORY AND XDATA MEMORY MAP (EXT_PROG_SRAM_EN = 1) ............................. 104 FIGURE 66: CPU PROGRAM MEMORY AND XDATA MEMORY MAP (EXT_PROG_SRAM_EN = 0) ............................. 105 FIGURE 67: FLASH MEMORY ADDRESS WITHOUT RE-MAPPING, FARM BIT = 0 (IN SFR REGISTER CSREPR.2) (DEFAULT) ................................................................................................................................................................................ 106 FIGURE 68: FLASH MEMORY ADDRESS RE-MAPPING ENABLED, FARM BIT = 1 (IN SFR REGISTER CSREPR.2) ............ 106 FIGURE 69: DMA ENGINE BLOCK DIAGRAM................................................................................................................... 110 FIGURE 70: RING-AWARE SOFTWARE DMA EXAMPLE .................................................................................................... 112 FIGURE 71: EXAMPLE: ETHERNET PACKET RECEIVE DMA TRANSFER ONLY (RECEIVING A 1500-BYTE PACKET) .......... 117 FIGURE 72: EXAMPLE: ETHERNET PACKET RECEIVE AND TRANSMIT DMA TRANSFERS SIMULTANEOUSLY (RECEIVING AND TRANSMITTING A 1500-BYTE PACKET) .................................................................................................................... 117 FIGURE 73: EXAMPLE: ETHERNET PACKET RECEIVE AND TRANSMIT AND SOFTWARE DMA TRANSFERS SIMULTANEOUSLY (RECEIVING AND TRANSMITTING A 1500-BYTE PACKET, AND SOFTWARE COPYING A 200-BYTES DATA BLOCK) ...... 118 FIGURE 74: WATCHDOG TIMER BLOCK DIAGRAM........................................................................................................... 125 FIGURE 75: AX11015 OPERATING MODE TRANSITION DIAGRAM ................................................................................... 130 FIGURE 76: TIMER/COUNTER 0, MODE 0: 13-BIT TIMER/COUNTER ................................................................................. 138 FIGURE 77: TIMER/COUNTER 0, MODE 1: 16-BIT TIMER/COUNTER ................................................................................. 138 FIGURE 78: TIMER/COUNTER 0, MODE 2: 8-BIT TIMER/COUNTER WITH AUTO-RELOAD ................................................ 139 FIGURE 79: TIMER/COUNTER 0, MODE 3: TWO 8-BIT TIMERS/COUNTERS ....................................................................... 139 FIGURE 80: TIMER/COUNTER 1, MODE 0: 13-BIT TIMERS/COUNTERS ............................................................................. 140 FIGURE 81: TIMER/COUNTER 1, MODE 1: 16-BIT TIMERS/COUNTERS ............................................................................. 140 FIGURE 82: TIMER/COUNTER 1, MODE 2: 8-BIT TIMER/COUNTER WITH AUTO-RELOAD ................................................ 141 FIGURE 83: TIMER 2 BLOCK DIAGRAM IN TIMER MODE ................................................................................................. 143 FIGURE 84: TIMER 2 BLOCK DIAGRAM AS UART0 BAUD RATE GENERATOR ................................................................ 143 FIGURE 85: UART 0 BLOCK DIAGRAM ........................................................................................................................... 146 FIGURE 86: UART 0, MODE 0 TRANSMIT TIMING DIAGRAM........................................................................................... 147 FIGURE 87: UART 0, MODE 1 TRANSMIT TIMING DIAGRAM........................................................................................... 147 FIGURE 88: UART 0, MODE 2 TRANSMIT TIMING DIAGRAM........................................................................................... 148 FIGURE 89: UART 0, MODE 3 TRANSMIT TIMING DIAGRAM........................................................................................... 148 FIGURE 90: UART 1 BLOCK DIAGRAM ........................................................................................................................... 149 FIGURE 91: UART 1, MODE 0 TRANSMIT TIMING DIAGRAM........................................................................................... 151 FIGURE 92: UART 1, MODE 1 TRANSMIT TIMING DIAGRAM........................................................................................... 151 FIGURE 93: UART1, MODE 2 TRANSMIT TIMING DIAGRAM ........................................................................................... 152 FIGURE 94: UART 1, MODE 3 TRANSMIT TIMING DIAGRAM........................................................................................... 152 10 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY FIGURE 95: UART 2 BLOCK DIAGRAM ........................................................................................................................... 153 FIGURE 96: PORTS PIN LOGIC .......................................................................................................................................... 164 FIGURE 97: DATA REGISTER ACCESSED BY READ-MODIFY-WRITE INSTRUCTIONS ........................................................ 164 FIGURE 98: PORTS WRITE TIMING DIAGRAM .................................................................................................................... 164 FIGURE 99: PORTS READ TIMING DIAGRAM ...................................................................................................................... 164 FIGURE 100: TOE BLOCK DIAGRAM ............................................................................................................................... 166 FIGURE 101: ARP CACHE SRAM MEMORY MAP............................................................................................................ 171 FIGURE 102: THE EXTERNAL DATA (XDATA) MEMORY OF CPU ................................................................................... 181 FIGURE 103: THE CONTENT OF BUFFER DESCRIPTOR PAGE (BDP) ................................................................................. 182 FIGURE 104: EXAMPLE RING STRUCTURE OF RECEIVE PACKET BUFFER RING ................................................................ 183 FIGURE 105: EXAMPLE RING STRUCTURE OF TRANSMIT PACKET BUFFER RING ............................................................. 183 FIGURE 106: ICMP PACKET FORMAT IN RPBR ............................................................................................................... 184 FIGURE 107: IGMP PACKET FORMAT IN RPBR .............................................................................................................. 185 FIGURE 108: UDP PACKET FORMAT IN RPBR ................................................................................................................ 186 FIGURE 109: TCP PACKET FORMAT IN RPBR ................................................................................................................. 188 FIGURE 110: NON-IP-TYPE PACKET FORMAT IN RPBR ................................................................................................... 188 FIGURE 111: ICMP PACKET FORMAT IN TPBR ............................................................................................................... 190 FIGURE 112: IGMP PACKET FORMAT IN TPBR ............................................................................................................... 190 FIGURE 113: UDP PACKET FORMAT IN TPBR ................................................................................................................. 191 FIGURE 114: TCP PACKET FORMAT IN TPBR ................................................................................................................. 193 FIGURE 115: NON-IP-TYPE PACKET FORMAT IN TPBR ................................................................................................... 193 FIGURE 116 10/100M ETHERNET MAC BLOCK DIAGRAM .............................................................................................. 194 FIGURE 117: MULTICAST FILTER ARRAY HASHING ALGORITHM .................................................................................... 198 FIGURE 118: MULTICAST FILTER ARRAY BIT MAPPING .................................................................................................. 199 FIGURE 119: ETHERNET PACKET FORMAT ....................................................................................................................... 201 FIGURE 120: ETHERNET PACKET BUFFER DATA STRUCTURE IN ETHERNET MAC .......................................................... 203 FIGURE 121 TRANSMIT/RECEIVE BUFFER RING STRUCTURE ........................................................................................... 204 FIGURE 122: PAUSE FRAME ............................................................................................................................................. 204 FIGURE 123: EXAMPLE MAGIC PACKET FORMAT ............................................................................................................ 205 FIGURE 124: 10/100M ETHERNET PHY BLOCK DIAGRAM .............................................................................................. 212 FIGURE 125: MII STATION MANAGEMENT FRAME FORMAT............................................................................................ 213 FIGURE 126: PROGRAMMABLE COUNTER ARRAY BLOCK DIAGRAM ............................................................................... 219 FIGURE 127: PCA TIMER/COUNTER ................................................................................................................................ 220 FIGURE 128: PCA CAPTURE MODE ................................................................................................................................. 221 FIGURE 129: PCA SOFTWARE TIMER MODE (COMPARE MODE) ..................................................................................... 222 FIGURE 130: PCA HIGH-SPEED OUTPUT MODE .............................................................................................................. 223 FIGURE 131: PCA PULSE WIDTH MODULATOR MODE .................................................................................................... 224 FIGURE 132: I2C CONTROLLER BLOCK DIAGRAM ........................................................................................................... 230 FIGURE 133: TRANSMITTING DATA TO AN I2C SLAVE DEVICE........................................................................................ 236 FIGURE 134: I2C READ DATA ......................................................................................................................................... 236 FIGURE 135: 1-WIRE CONTROLLER BLOCK DIAGRAM .................................................................................................... 239 FIGURE 136: SPI CONTROLLER BLOCK DIAGRAM ........................................................................................................... 245 FIGURE 137: SPI TIMING DIAGRAM................................................................................................................................. 246 FIGURE 138: COMMAND FRAME FORMAT IN SPI SLAVE MODE....................................................................................... 255 FIGURE 139: LOCAL BUS INTERFACE AND DIGIPORT BLOCK DIAGRAM .......................................................................... 257 FIGURE 140: BYTE-ACCESS TIMING DIAGRAM IN LOCAL BUS MASTER MODE ............................................................... 266 FIGURE 141: REGISTER MAPPING BETWEEN EXTERNAL CPU REGISTER AND INTERNAL SFR REGISTER IN LOCAL BUS SLAVE MODE........................................................................................................................................................... 277 FIGURE 142: EXAMPLE MOTION JPEG IMAGE DATA ...................................................................................................... 285 FIGURE 143: POWER-UP SEQUENCE TIMING DIAGRAM AND TABLE ................................................................................ 292 FIGURE 144: XTL25P CLOCK TIMING DIAGRAM AND TABLE ......................................................................................... 293 FIGURE 145: LB_CLK CLOCK TIMING DIAGRAM AND TABLE ........................................................................................ 293 FIGURE 146: CPU PROGRAM READ AND PROGRAM WRITE TIMING DIAGRAM AND TABLE ............................................ 294 FIGURE 147: CPU DATA READ AND DATA WRITE TIMING DIAGRAM AND TABLE .......................................................... 295 FIGURE 148: DMA DATA READ AND DATA WRITE TIMING DIAGRAM AND TABLE ........................................................ 296 FIGURE 149: BOOT LOADER READING FLASH AND WRITING SRAM TIMING DIAGRAM AND TABLE .............................. 297 FIGURE 150: SPI MASTER CONTROLLER TIMING DIAGRAM AND TABLE ......................................................................... 299 FIGURE 151: SPI SLAVE CONTROLLER TIMING DIAGRAM AND TABLE ............................................................................ 300 FIGURE 152: 1-WIRE RESET PULSE AND PRESENCE PULSE TIMING DIAGRAM AND TABLE ............................................. 301 11 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY FIGURE 153: 1-WIRE WRITE AND READ TIME SLOT TIMING DIAGRAM AND TABLE........................................................ 302 FIGURE 154: 1-WIRE STPZ RESET AND READ WRITE TIMING DIAGRAM AND TABLE ..................................................... 303 FIGURE 155: ECI TIMING DIAGRAM AND TABLE ............................................................................................................. 304 FIGURE 156: CEX[4:0] TIMING DIAGRAM AND TABLE ................................................................................................... 304 FIGURE 157: TM_CK[2:0] TIMING DIAGRAM AND TABLE .............................................................................................. 305 FIGURE 158: TM_GT[2:0] TIMING DIAGRAM AND TABLE .............................................................................................. 305 FIGURE 159: ISA BUS ACCESS TIMING DIAGRAM ........................................................................................................... 306 FIGURE 160: INTEL 80186 BUS ACCESS TIMING DIAGRAM ............................................................................................. 307 FIGURE 161: INTEL 80386 BUS ACCESS TIMING DIAGRAM ............................................................................................. 308 FIGURE 162: MOTOROLA 68000/010 BUS ACCESS TIMING DIAGRAM ............................................................................. 309 FIGURE 163: MOTOROLA 68030/040 BUS ACCESS TIMING DIAGRAM (SLAVE MODE) ..................................................... 310 FIGURE 164: RENESAS SH3/SH4 BUS ACCESS TIMING DIAGRAM (SLAVE MODE)........................................................... 311 FIGURE 165: TI HPI BUS ACCESS TIMING DIAGRAM (MASTER MODE) ........................................................................... 312 FIGURE 166: SLAVE-REQUEST DMA ACCESS TIMING DIAGRAM (LOCAL BUS MASTER MODE ONLY) ........................... 313 FIGURE 167: LOCAL BUS MASTER SYNCHRONOUS MODE TIMING DIAGRAM.................................................................. 315 FIGURE 168: LOCAL BUS SLAVE SYNCHRONOUS MODE TIMING DIAGRAM..................................................................... 316 FIGURE 169: DIGIPORT PARALLEL MODE TIMING DIAGRAM ........................................................................................... 317 FIGURE 170: DIGIPORT SPI MODE TIMING DIAGRAM...................................................................................................... 317 FIGURE 171: 10/100M ETHERNET PHY TRANSMITTER WAVEFORM AND SPEC............................................................... 318 List of Tables TABLE 1: PINOUT DESCRIPTION ......................................................................................................................................... 16 TABLE 2: INTERRUPT CONTROLLER SUMMARY ................................................................................................................. 34 TABLE 3: REFERENCE PIN CONNECTION MAPPING IN LOCAL BUS MASTER MODE ........................................................... 47 TABLE 4: REFERENCE PIN CONNECTION MAPPING IN LOCAL BUS SLAVE MODE .............................................................. 50 TABLE 5: REFERENCE PIN CONNECTION MAPPING IN DIGIPORT MODE ............................................................................. 53 TABLE 6: I2C CONFIGURATION EEPROM MEMORY MAP ................................................................................................ 55 TABLE 7: LOCAL BUS MASTER MODE SETTING................................................................................................................. 62 TABLE 8: LOCAL BUS SLAVE MODE SETTING ................................................................................................................... 63 TABLE 9: THE SFR REGISTER MAP ................................................................................................................................... 66 TABLE 10: CPU CORE SFR REGISTER MAP....................................................................................................................... 71 TABLE 11: ON-CHIP FLASH MEMORY SECTOR STRUCTURE .............................................................................................. 87 TABLE 12: ON-CHIP FLASH MEMORY COMMAND DEFINITIONS ........................................................................................ 89 TABLE 13:WRITE OPERATION STATUS .............................................................................................................................. 94 TABLE 14: ON-CHIP FLASH MEMORY READ PROTECTION ................................................................................................. 98 TABLE 15: BLOCK NUMBER SETTING FOR PROGRAM SHADOW MODE ............................................................................ 101 TABLE 16: SOFTWARE DMA AND MILLISECOND TIMER RELATED SFR REGISTER MAP ................................................. 112 TABLE 17: SOFTWARE DMA AND MILLISECOND TIMER REGISTER MAP......................................................................... 114 TABLE 18: INTERRUPTS FLAG SUMMARY ........................................................................................................................ 119 TABLE 19: INTERRUPT CONTROLLER SFR REGISTER MAP .............................................................................................. 119 TABLE 20: WATCHDOG TIMER SFR REGISTER MAP ........................................................................................................ 125 TABLE 21: WATCHDOG BITS AND ACTIONS .................................................................................................................... 127 TABLE 22: TIMED ACCESS REGISTERS............................................................................................................................. 129 TABLE 23: POWER MANAGEMENT UNIT SFR REGISTER MAP ......................................................................................... 130 TABLE 24: TIMER 0, 1, 2 PIN DESCRIPTION ...................................................................................................................... 135 TABLE 25: TIMERS 0, 1, 2 RELATED SFR REGISTER MAP ................................................................................................ 135 TABLE 26: TIMER 2 MODE OF OPERATION....................................................................................................................... 142 TABLE 27: MILLISECOND TIMER DIVIDER RATIO ............................................................................................................ 144 TABLE 28: UART 0, 1 SFR REGISTER MAP..................................................................................................................... 145 TABLE 29: UART 2 SFR REGISTER MAP ........................................................................................................................ 156 TABLE 30: UART2 INTERRUPT IDENTIFICATION REGISTER............................................................................................. 159 TABLE 31: GENERAL PURPOSE I/O PORTS PINS DESCRIPTION ......................................................................................... 163 TABLE 32: GPIO SFR REGISTER MAP ............................................................................................................................. 163 TABLE 33: READ-MODIFY-WRITE INSTRUCTIONS ........................................................................................................... 163 TABLE 34: TOE OPERATION MODES ............................................................................................................................... 168 TABLE 35: TOE SFR REGISTER MAP .............................................................................................................................. 169 12 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY TABLE 36: TOE REGISTER MAP ...................................................................................................................................... 170 TABLE 37: DA FIELD GENERATION RULE IN TRANSMIT DIRECTION ............................................................................... 172 TABLE 38: L2_ENGINE RX TRUTH TABLE ...................................................................................................................... 173 TABLE 39: L2_ENGINE TX TRUTH TABLE....................................................................................................................... 174 TABLE 40: 10/100M ETHERNET MAC SFR REGISTER MAP ............................................................................................ 195 TABLE 41: 10/100M ETHERNET MAC REGISTER MAP .................................................................................................... 196 TABLE 42: PACKET FILTERING DURING REMOTE-WAKEUP ENABLE MODE .................................................................... 200 TABLE 43: 10/100 ETHERNET PHY SFR REGISTER MAP................................................................................................. 213 TABLE 44: EMBEDDED 10/100M ETHERNET PHY REGISTER MAP .................................................................................. 215 TABLE 45: PROGRAMMABLE COUNTER ARRAY SFR REGISTER MAP .............................................................................. 219 TABLE 46:PCA TIMER/COUNTER INPUT SOURCES AND REFERENCE TIMING TICK .......................................................... 220 TABLE 47: PULSE WIDTH MODULATOR FREQUENCY ...................................................................................................... 224 TABLE 48: PCA MODULE MODES WITHOUT INTERRUPT ENABLED ................................................................................ 227 TABLE 49: PCA MODULE MODES WITH INTERRUPT ENABLED ....................................................................................... 228 TABLE 50: I2C CONTROLLER SFR REGISTER MAP .......................................................................................................... 231 TABLE 51: I2C CONTROLLER REGISTER MAP .................................................................................................................. 232 TABLE 52: REFERENCE COMMAND INSTRUCTIONS IN I2C SLAVE MODE ......................................................................... 237 TABLE 53: 1-WIRE CONTROLLER SFR REGISTER MAP.................................................................................................... 239 TABLE 54: 1-WIRE CONTROLLER REGISTER MAP ........................................................................................................... 240 TABLE 55: SPI CONTROLLER SFR REGISTER MAP .......................................................................................................... 247 TABLE 56: SPI CONTROLLER REGISTER MAP .................................................................................................................. 248 TABLE 57: COMMAND INSTRUCTION IN SPI SLAVE MODE .............................................................................................. 254 TABLE 58: LOCAL BUS INTERFACE AND DIGIPORT SFR REGISTER MAP ......................................................................... 260 TABLE 59: EXTERNAL CPU REGISTER MAP .................................................................................................................... 269 TABLE 60: I2C MASTER CONTROLLER TIMING TABLE .................................................................................................... 298 TABLE 61: I2C SLAVE CONTROLLER TIMING TABLE ....................................................................................................... 298 TABLE 62: ISA BUS ACCESS TIMING TABLE (MASTER MODE) ....................................................................................... 306 TABLE 63: ISA BUS ACCESS TIMING TABLE (SLAVE MODE) .......................................................................................... 306 TABLE 64: INTEL 80186 BUS ACCESS TIMING TABLE (MASTER MODE) .......................................................................... 307 TABLE 65: INTEL 80186 BUS ACCESS TIMING TABLE (SLAVE MODE)............................................................................. 307 TABLE 66: INTEL 80386 BUS ACCESS TIMING TABLE (MASTER MODE) .......................................................................... 308 TABLE 67: INTEL 80386 BUS ACCESS TIMING TABLE (SLAVE MODE)............................................................................. 308 TABLE 68: MOTOROLA 68000/010 BUS ACCESS TIMING TABLE (MASTER MODE) ......................................................... 309 TABLE 69: MOTOROLA 68000/010 BUS ACCESS TIMING TABLE (SLAVE MODE) ............................................................ 309 TABLE 70: MOTOROLA 68030/040 BUS ACCESS TIMING TABLE (SLAVE MODE) ............................................................ 310 TABLE 71: RENESAS SH3/SH4 BUS ACCESS TIMING TABLE (SLAVE MODE) .................................................................. 311 TABLE 72: TI HPI BUS ACCESS TIMING TABLE (MASTER MODE) ................................................................................... 312 TABLE 73: SLAVE-REQUEST DMA ACCESS TIMING TABLE (LOCAL BUS MASTER MODE ONLY) .................................... 314 TABLE 74: LOCAL BUS MASTER SYNCHRONOUS MODE TIMING TABLE .......................................................................... 315 TABLE 75: LOCAL BUS SLAVE SYNCHRONOUS MODE TIMING TABLE ............................................................................. 316 TABLE 76: DIGIPORT PARALLEL MODE TIMING TABLE ................................................................................................... 317 TABLE 77: DIGIPORT SPI MODE TIMING TABLE .............................................................................................................. 317 TABLE 78: 10/100M ETHERNET PHY RECEIVER SPEC .................................................................................................... 318 13 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 1.0 Introduction 1.1 General Description The AX11015, Single Chip Micro-controller with TCP/IP and 10/100M Fast Ethernet MAC/PHY, is a System-on-Chip (SoC) solution which offers a high performance embedded micro-controller and rich communication peripherals for wide varieties of application which need access to the LAN or Internet. With built-in network protocol stack, the AX11015 provides very cost effective networking solution to enable simple, easy, and low cost Internet connection capability for many applications such as consumer electronics, networked home appliances, industrial equipments, security systems, remote data collection equipments, remote control, remote monitoring, and remote management. In addition to stand-alone application, the AX11015 with popular TCP/IP protocol suite on-chip and built-in local bus host interface, I2C bus, or SPI bus, can be used as network co-processor to offload TCP/IP protocol processing loading from system CPU in an embedded system. The AX11015 needs only a 25Mhz crystal to operate and its internal operating frequency is programmable from 25Mhz, 50Mhz, and 100Mhz, depending on system performance and power consumption trade-off. The AX11015 integrates an internal voltage regulator that requires only single power supply of 3.3V to operate, and an internal power-on-reset circuitry that simplifies the external reset circuitry on PCB. The package is 128-pin low-profile LQFP RoHS package and the operating temperature range are 0 to 70C or -40 to 85C. Please refer to ordering information for part number details. 1.2 AX11015 Block Diagram DB_DO DB_CKO DB_DI XROMCE1_N, XPRGWR_N, XPRGRD_N, XRAMCE0_N, XRAMCE1_N, XDATWR_N, XDATRD_N, XADDR[20:0], XDATA[7:0] RXD[2:0], TXD[2:0], CTS, DSR, RI, DCD, RTS, DTR, DE, RE_N P0[7:0], P1[7:0], P2[7:0], P3[7:0] ECI, CEX[4:0] SCL, SDA SCLK, MOSI, MISO, SS[2:0] DQ, STPZ Debugger 1T 8051/80390 Core Watchdog Timer Power Management Unit 3 Timer/Counters Interrupt Controller 512KB Flash Memory 16KB Program SRAM 32KB Data SRAM Local Bus Interface/Digiport (Master/Slave) Memory Arbiter & Boot Loader LA[15:0], LDA[15:0], LCS0_N, LCS1_N, LINT, LALE, LWR_N, LRD_N, LRDY, LUDS_N, LLDS_N, RD_DRQ, RD_DAK, WR_DRQ, WR_DAK DMA Engine 3 UART 32 GPIO TCP/IP Offload Engine 10/100M Ethernet MAC 12KB SRAM 10/100M Ethernet PHY 5 Prog. Counter Array I2C (Master/Slave) SPI (Master/Slave) 1-Wire (Master) 3.3 to 1.8V Regulator TM[2:0]_CK, TM[2:0]_GT, INT[1:0] OSC & PLL & Clock Gen. XTL25P, XTL25N LB_CLK Power-On-Reset & Reset Gen. SYSCK_SEL[1:0], EXT_WKUP Figure 12: AX11015 Block Diagram 14 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights RX_CLK, MRXD[3:0], RX_DV, RX_ER, CRS, COL, TX_CLK, MTXD[3:0], TX_EN, TX_ER, MDC, MDIO TXOP, TXON, RXIP, RXIN, FD_CL_LED, SPD_LED, LNK_LED, RSET_BG RST_N SYS_RSTO_N AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 1.3 AX11015 Pinout Diagram 65 66 67 68 69 70 71 72 73 74 75 76 P30 / LDA8 / TX_CLK P10 / LA0 / MDC VCC18 VCC3R GND3R GND18A TXON TXOP VCC18A RXIN RXIP GND3A VCC3A RSET_BG 77 78 79 80 81 82 83 84 85 86 87 P35 / LDA13 / TX_EN P34 / LDA12 / MTXD3 P14 / LA4 P33 / LDA11 / MTXD2 P13 / LA3 / RE_N VCCK SYS_RSTO_N P32 / LDA10 / MTXD1 P12 / LA2 / DE P31 / LDA9 / MTXD0 P11 / LA1 / MDIO 88 89 90 P36 / LDA14 / TX_ER P15 / LA5 VCCIO 92 91 P16 / LA6 P37 / LDA15 / COL 93 94 95 97 64 98 63 99 62 100 61 101 60 102 59 103 58 104 57 105 56 106 55 107 54 108 53 109 52 ASIX AX11015 110 111 112 113 114 115 51 50 49 48 47 46 116 45 117 44 118 43 119 42 120 41 121 40 122 39 123 38 124 37 125 36 35 126 34 127 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 9 8 TM0_CK / LALE P21 / LDA1 / MRXD0 TM0_GT / LWR_N TM1_CK / LRD_N / CEX1 P22 / LDA2 / MRXD1 TM1_GT / LRDY / CEX2 P23 / LDA3 / MRXD2 TM2_CK / LUDS_N / CEX3 TM2_GT / LLDS_N / CEX4 P24 / LDA4 / MRXD3 P00 / LA8 / RXD2 P25 / LDA5 / RX_DV P01 / LA9 / TXD2 P26 / LDA6 / CRS P02 / LA10 / CTS P03 / LA11 / DSR VCCIO P04 / LA12 / RI VCCK P27 / LDA7 / RX_ER P05 / LA13 / DCD GND DB_DI / LNK_LED DB_CKO / SPD_LED DB_DO / FD_CL_LED 7 6 5 4 2 3 1 10 33 128 SCLK MOSI MISO SS1 / DQ P20 / LDA0 / RX_CLK SS2 / STPZ VCCK LB_CLK RXD0 VCCK XADDR16 XADDR15 XADDR14 TXD0 XADDR13 XADDR12 XADDR11 RXD1 / LCS0_N / ECI XADDR9 XADDR8 TXD1 / LCS1_N / CEX0 XPRGWR_N EXT_WKUP / INT0 SCL SDA XADDR18 INT1 / LINT XADDR7 XADDR6 XADDR5 RST_N XADDR4 XADDR3 XADDR2 XADDR1 VCCK VCCIO SS0 GND 96 GND P17 / LA7 The AX11015 is housed in a 128-pin LQFP package. Figure 13: AX11015 Pinout Diagram 15 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights GND18A XTL25P XTL25N VCC18A XADDR17 VCCK XADDR19 / WR_DRQ VCCIO XADDR20 / WR_DAK GND XADDR10 XDATA7 XDATRD_N XDATA6 SYSCK_SEL1 XDATA5 XRAMCE0_N XDATA4 VCCIO XDATA3 XRAMCE1_N / RD_DAK XDATA2 SYSCK_SEL0 XDATA1 XROMCE1_N / RD_DRQ XDATA0 XPRGRD_N XADDR0 VCCK P07 / LA15 / DTR P06 / LA14 / RTS XDATWR_N AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 1.4 Signal Description The following abbreviations apply to the following pin description table. Please note some I/O pins with multiple signal definitions on the same pin may have different pin attribute in the "Type" column for different signal definition. For example, pin 18 can be defined as P00, LA8 or RXD2. In the case of P00 the Type = B5/T/4m/8m/PU, while in the case of LA8 the Type = O5/4m/8m, and in the case of RXD2 the Type = I5. In other words, the PU (internal pull-up) only takes effective during P00 signal mode, and LA8 or RXD2 signal modes will not have the PU. I18 I3 I5 O18 O3 O5 B3 B5 Input, 1.8V Input, 3.3V Input, 3.3V with 5V tolerant Output, 1.8V Output, 3.3V Output, 3.3V with 5V tolerant Bi-directional I/O, 3.3V Bi-directional I/O, 3.3V with 5V tolerant 4m 8m PU PD P S T AB 4mA driving strength 8mA driving strength Internal Pull-Up (75K) Internal Pull-Down (75K) Power and ground pin Schmitt Trigger Tri-state Analog Bi-directional I/O AO Analog Output Table 1: Pinout Description Pin Name Type Pin No XROMCE1_N O3/4m 40 XRAMCE0_N O3/4m 48 XRAMCE1_N O3/4m 44 XPRGWR_N O3/4m/8m 111 XPRGRD_N O3/4m/8m 38 XDATWR_N O3/4m/8m 33 XDATRD_N O3/4m/8m 52 XADDR [20:0] O3/4m/8m 56, 58, 115, 60, 100, 101, 102, 104, 105, 106, 54, 108, 109, 117, 118, 119, 121, 122, 123, 124, 37 Pin Description External Memory Interface External program Flash memory chip enable, active low. Note that this is a multi-function pin (XROMCE1_N/RD_DRQ), depending on the setting of MI_PSEL bits in I2C EEPROM offset 0x03, see section 3.1.3 for details. External program/data SRAM memory chip enable 0, active low. Note that the addressable space of external SRAM chip using XRAMCE0_N is programmable by the ASCS bits in I2C EEPROM offset 0x01. In other words, this allows users to choose from 64K bytes, 128K bytes, 256K bytes, 512K bytes, or 1024K bytes of SRAM chip whichever is most cost effective. See section 3.1.2 for details. External program/data SRAM memory chip enable 1, active low. Note that this is a multi-function pin (XRAMCE1_N/RD_DAK), depending on the setting of MI_PSEL bits I2C EEPROM offset 0x03, see section 3.1.3 for details. External program Flash memory write enable, active low. Note that the output driving strength is programmable, by MI_ODS bit in I2C EEPROM offset 0x04. See section 3.1.4 for details. External program Flash memory read enable, active low. Note that the output driving strength is programmable, by MI_ODS bit in I2C EEPROM offset 0x04. See section 3.1.4 for details. External program/data SRAM memory write enable, active low. Note that the output driving strength is programmable, by MI_ODS bit in I2C EEPROM offset 0x04. See section 3.1.4 for details. External program/data SRAM memory read enable, active low. Note that the output driving strength is programmable, by MI_ODS bit in I2C EEPROM offset 0x04. See section 3.1.4 for details. External program/data memory address bus. Note that XADDR20 and XADDR19 are multi-function pins (XADDR20/WR_DAK, XADDR19/WR_DRQ), depending on the setting of MI_PSEL bits in I2C EEPROM offset 0x03, see section 3.1.3 for details. The output driving strength is programmable, by MI_ODS bit in I2C EEPROM offset 0x04. See section 3.1.4 for details. 16 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY XDATA [7:0] B3/4m/8m 53, 51, 49, 47, 45, 43, 41, 39 External program/data memory's data bus. The XDATA [6:0] are also being used as chip configuration pins whose value will be latched during chip hardware reset, i.e., RST_N being low (but not software reset or software reboot). Their definition are as follows, Pin Name Pin Definition Description during chip power-on reset XDATA EXT_PROG_S For high performance application, pull up with [0] RAM_EN 10Kohm to enable program shadow mode, which will automatically copy program code from Flash memory to external SRAM before CPU starts running. Pull down with 10Kohm to disable program shadow mode when the external SRAM is only used as data memory or when no external SRAM is used. XDATA LB_MOD Pull up with 10Kohm to set local bus interface to [1] operate in slave mode. If local bus interface is not used, please pull up. Pull down with 10Kohm to set local bus interface to operate in master mode. XDATA SYNC_BUS Pull up with 10Kohm to set local bus interface to [2] operate in synchronous mode where the local bus signals are synchronous with respect to the rising edge of LB_CLK clock. Pull down with 10Kohm to set local bus interface to operate in asynchronous mode. If local bus interface is not used, please pull down. XDATA TEST_SPEEDU Please pull down with 10Kohm for normal [3] P operation. XDATA BURN_FLASH Pull up with 10Kohm to temporarily enable Flash [4] _EN programming via UART0. This will put the CPU in reset state during Flash programming. Pull down with 10Kohm to allow the CPU to run normally after reset and disable Flash programming via UART0. XDATA BURN_FLASH Pull up with 10Kohm when the [5] _921K BURN_FLASH_EN is also pulled up to enable Flash memory programming at higher speed as 921.6Kbps baud rate. When the BURN_FLASH_EN is pulled down, this has no effect. Pull down with 10Kohm when the BURN_FLASH_EN is also pulled up to enable Flash memory programming at normal speed as 115.2Kbps baud rate. When the BURN_FLASH_EN is pulled down, this has no effect. XDATA I2C_BOOT_DI Pull up with 10Kohm if the optional I2C [6] S EEPROM is not used for storing configuration data. Pull down with 10Kohm if the I2C EEPROM is used for storing configuration data. Note that the output driving strength is programmable, by MI_ODS bit in I2C EEPROM offset 0x04. See section 3.1.4 for details. 17 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY DB_DI I5/PU DB_CKO O5/8m DB_DO O5/8m INT [1:0] I5/PU TM[2:0]_CK I5 TM[2:0]_GT I5 P0 [7:0] B5/T/4m/8 m/PU P1 [7:0] B5/T/4m/8 m/PU P2 [7:0] B5/T/4m/8 m/PU P3 [7:0] B5/T/4m/8 m/PU RXD0 TXD0 RXD1 B5/4m/PU O5/4m B5/4m/PU CPU Debugger/Interrupt/Timers/GPIO Interface 30 CPU debugger data input. Note that this is a multi-function pin (DB_DI/LNK_LED), depending on the setting of DBG_PSEL bit in I2C EEPROM offset 0x01, see section 3.1.2 for details. 31 CPU debugger clock output. Note that this is a multi-function pin (DB_CKO/SPD_LED), depending on the setting of DBG_PSEL bit in I2C EEPROM offset 0x01, see section 3.1.2 for details. 32 CPU debugger data output. Note that this is a multi-function pin (DB_DO/FD_CL_LED), depending on the setting of DBG_PSEL bit in I2C EEPROM offset 0x01, see section 3.1.2 for details. 116, 112 Interrupt inputs, active low or falling edge trigger. Note that the INT0 is a dual-function input pin sharing with EXT_WKUP pin. 15, 11, 8 Timer 2, 1, 0 external clock input (only TM0_CK has internal pull-up). Note that these are multi-function pins (TM2_CK/LUDS_N/CEX3, TM1_CK/LRD_N/CEX1, TM0_CK/LALE), depending on the setting of TM_PSEL and UIT_PSEL bits in I2C EEPROM offset 0x03, see section 3.1.3 for details. 16, 13, 10 Timer 2, 1, 0 external gate control input (only TM_GT has internal pull-up). Note that these are multi-function pins (TM2_GT/LLDS_N/CEX4, TM1_GT/LRDY/CEX2, TM0_GT/LWR_N), depending on the setting of TM_PSEL and UIT_PSEL bits in I2C EEPROM offset 0x03, see section 3.1.3 for details. 35, 34, Port 0 general purpose input and output pins. 28, 25, Note that these are multi-function pins (P07/LA15/DTR, P06/LA14/RTS, 23, 22, P05/LA13/DCD, P04/LA12/RI, P03/LA11/DSR, P02/LA10/CTS, 20, 18 P01/LA9/TXD2, P00/LA8/RXD2), depending on the setting of P0_PSEL bits in I2C EEPROM offset 0x02, see section 3.1.3 for details. The output driving strength is programmable, by P0_ODS bit in I2C Configuration EEPROM offset 0x04. See section 3.1.4 for details. 95, 94, Port 1 general-purpose input and output pins. 91, 87, Note that these are multi-function pins (P17/LA7, P16/LA6, P15/LA5, P14/LA4, 85, 81, P13/LA3/RE_N, P12/LA2/DE, P11/LA1/MDIO, P10/LA0/MDC), depending on 79, 77 the setting of P1_PSEL bits in I2C EEPROM offset 0x02, see section 3.1.3 for details. The output driving strength is programmable, by P1_ODS bit in I2C Configuration EEPROM offset 0x04. See section 3.1.4 for details. 27, 21, Port 2 general-purpose input and output pins. 19, 17, Note that these are multi-function pins (P27/LDA7/RX_ER, P26/LDA6/CRS, 14, 12, 9, P25/LDA5/RX_DV, P24/LDA4/MRXD3, P23/LDA3/MRXD2, 5 P22/LDA2/MRXD1, P21/LDA1/MRXD0, P20/LDA0/RX_CLK), depending on the setting of P2_PSEL bits in I2C EEPROM offset 0x02, see section 3.1.3 for details. The output driving strength is programmable, by P2_ODS bit in I2C Configuration EEPROM offset 0x04. See section 3.1.4 for details. 93, 92, Port 3 general-purpose input and output pins. 89, 88, Note that these are multi-function pins (P37/LDA15/COL, P36/LDA14/TX_ER, 86, 82, P35/LDA13/TX_EN, P34/LDA12/MTXD3, P33/LDA11/MTXD2, 80, 78 P32/LDA10/MTXD1, P31/LDA9/MTXD0, P30/LDA8/TX_CLK), depending on the setting of P3_PSEL bits in I2C EEPROM offset 0x02, see section 3.1.3 for details. The output driving strength is programmable, by P3_ODS bit in I2C Configuration EEPROM offset 0x04. See section 3.1.4 for details. UART Interface 98 UART 0 serial receive data. 103 UART 0 serial transmit data. 107 UART 1 serial receive data. Note that this is a multi-function pin (RXD1/LCS0_N/ECI), depending on the setting of UIT_PSEL bits in I2C EEPROM offset 0x03, see section 3.1.3 for details. 18 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY TXD1 O5/4m/8m 110 RXD2 I5 18 TXD2 O5/4m/8m 20 CTS I5 22 DSR I5 23 RI I5 25 DCD I5 28 RTS O5/4m/8m 34 DTR O5/4m/8m 35 DE O5/4m/8m 81 RE_N O5/4m/8m 85 SCL B5/4m/8m/ PU 113 SDA B5/4m/8m/ PU 114 SS0 B5/T/4m 127 UART 1 serial transmit data. Note that this is a multi-function pin (TXD1/LCS1_N/CEX0), depending on the setting of UIT_PSEL bits in I2C EEPROM offset 0x03, see section 3.1.3 for details. The output driving strength is programmable, by PCA_ODS bit in I2C Configuration EEPROM offset 0x04. See section 3.1.4 for details. UART 2 serial receive data. Note that this is a multi-function pin (P00/LA8/RXD2), depending on the setting of P0_PSEL bits in I2C EEPROM offset 0x02, see section 3.1.3 for details. UART 2 serial transmit data. Note that this is a multi-function pin (P01/LA9/TXD2), depending on the setting of P0_PSEL bits in I2C EEPROM offset 0x02, see section 3.1.3 for details. The output driving strength is programmable, by P0_ODS bit in I2C Configuration EEPROM offset 0x04. See section 3.1.4 for details. UART 2 clear to send. Note that this is a multi-function pin (P02/LA10/CTS), depending on the setting of P0_PSEL bits in I2C EEPROM offset 0x02, see section 3.1.3 for details. UART 2 data set ready. Note that this is a multi-function pin (P03/LA11/DSR), depending on the setting of P0_PSEL bits in I2C EEPROM offset 0x02, see section 3.1.3 for details. UART 2 ring indicator. Note that this is a multi-function pin (P04/LA12/RI), depending on the setting of P0_PSEL bits in I2C EEPROM offset 0x02, see section 3.1.3 for details. UART 2 data carriers detect. Note that this is a multi-function pin (P05/LA13/DCD), depending on the setting of P0_PSEL bits in I2C EEPROM offset 0x02, see section 3.1.3 for details. UART 2 request to send. Note that this is a multi-function pin (P06/LA14/RTS), depending on the setting of P0_PSEL bits in I2C EEPROM offset 0x02, see section 3.1.3 for details. The output driving strength is programmable, by P0_ODS bit in I2C Configuration EEPROM offset 0x04. See section 3.1.4 for details. UART 2 data terminal ready. Note that this is a multi-function pin (P07/LA15/DTR), depending on the setting of P0_PSEL bits in I2C EEPROM offset 0x02, see section 3.1.3 for details. The output driving strength is programmable, by P0_ODS bit in I2C Configuration EEPROM offset 0x04. See section 3.1.4 for details. UART 2 transceiver driver output enable. Note that this is a multi-function pin (P12/LA2/DE), depending on the setting of P1_PSEL bits in I2C EEPROM offset 0x02, see section 3.1.3 for details. The output driving strength is programmable, by P1_ODS bit in I2C Configuration EEPROM offset 0x04. See section 3.1.4 for details. UART 2 transceiver receiver output enable, active low. Note that this is a multi-function pin (P13/LA3/RE_N), depending on the setting of P1_PSEL bits in I2C EEPROM offset 0x02, see section 3.1.3 for details. The output driving strength is programmable, by P1_ODS bit in I2C Configuration EEPROM offset 0x04. See section 3.1.4 for details. Serial Interface I2C serial clock line for operating in either master or slave mode. Note that the output driving strength is programmable, by I2C_ODS bit in I2C Configuration EEPROM offset 0x04. See section 3.1.4 for details. I2C serial data line for operating in either master or slave mode. Note that the output driving strength is programmable, by I2C_ODS bit in I2C Configuration EEPROM offset 0x04. See section 3.1.4 for details. SPI slave select 0. This is a tri-stateable output when operating in SPI master mode or an input when operating in SPI slave mode. When operating in SPI master mode, it needs an external pulled-up resistor. 19 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY SS[2:1] O5/T/4m/8 m SCLK B5/T/4m/8 m MISO B5/T/4m/8 m MOSI B5/T/4m/8 m DQ B5/4m/8m STPZ O5/4m/8m ECI CEX [4:0] I5 B5/4m/8m RXIP AB RXIN AB TXOP AB TXON AB 6, 4 SPI slave select 2, 1. These are tri-stateable output (an external pulled-up resistor needed) and used in SPI master mode only. Note that these are multi-function pins (SS2/STPZ, SS1/DQ), depending on the setting of SPI_PSEL bits in I2C EEPROM offset 0x03, see section 3.1.3 for details. The output driving strength is programmable, by SPI_ODS bit in I2C Configuration EEPROM offset 0x04. See section 3.1.4 for details. 1 SPI clock. This is a tri-stateable output when operating in SPI master mode or an input when operating in SPI slave mode. In SPI master mode operating at mode 0 or 2, user should pull low this pin with external resistor, while operating at mode 1 or 3, user should pull up this pin with external resistor. Note that the output driving strength is programmable, by SPI_ODS bit in I2C Configuration EEPROM offset 0x04. See section 3.1.4 for details. 3 SPI master input slave output line. This is used to receive serial data when the SPI controller is configured as SPI master or to transmit serial data when it is configured as SPI slave. When operating in SPI slave mode, this is a tri-stateable output, which needs an external pulled-up resistor. Note that the output driving strength is programmable, by SPI_ODS bit in I2C Configuration EEPROM offset 0x04. See section 3.1.4 for details. 2 SPI master output slave input line. This is used to transmit serial data when the SPI controller is configured as SPI master or to receive serial data when it is configured as SPI slave. When operating in SPI master mode, this is a tri-stateable output, which needs an external pulled-up resistor. Note that the output driving strength is programmable, by the SPI_ODS bit in I2C Configuration EEPROM offset 0x04. See section 3.1.4 for details. 4 1-Wire serial data input and output. This is an open-drain pin, which needs an external pulled-up resistor or a strong pull-up through a PMOS transistor. Note that this is a multi-function pin (SS1/DQ), depending on the setting of SPI_PSEL bits in I2C EEPROM offset 0x03, see section 3.1.3 for details. The output driving strength is programmable, by SPI_ODS bit in I2C Configuration EEPROM offset 0x04. See section 3.1.4 for details. 6 1-Wire strong pull-up is used for device with a stiff power supply for high current application. This is active low. Note that this is a multi-function pin (SS2/STPZ), depending on the setting of SPI_PSEL bits in I2C EEPROM offset 0x03, see section 3.1.3 for details. The output driving strength is programmable, by SPI_ODS bit in I2C Configuration EEPROM offset 0x04. See section 3.1.4 for details. Programmable Counter Array Interface 107 Programmable counter array external clock input. Note that this is a multi-function pin (RXD1/LCS0_N/ECI), depending on the setting of UIT_PSEL bits in I2C EEPROM offset 0x03, see section 3.1.3 for details. 16, 15, Programmable counter array module 4~0 input and output. 13, 11, Note that these are multi-function pins (TM2_GT/LLDS_N/CEX4, 110 TM2_CK/LUDS_N/CEX3, TM1_GT/LRDY/CEX2, TM1_CK/LRD_N/CEX1, TXD1/LCS1_N/CEX0), depending on the setting of UIT_PSEL and TM_PSEL bits in I2C EEPROM offset 0x03, see section 3.1.3 for details. The output driving strength is programmable, by the PCA_ODS bit in I2C Configuration EEPROM offset 0x04. See section 3.1.4 for details. Ethernet PHY Interface 68 Receive differential data input positive pin for 10BASE-T/100BASE-TX in MDI mode or transmit differential data output positive pin in MDIX mode. 69 Receive differential data input negative pin for 10BASE-T/100BASE-TX in MDI mode or transmit differential data output negative pin in MDIX mode. 71 Transmit differential data output positive pin for 10BASE-T/100 BASE-TX in MDI mode or receive differential data input positive pin in MDIX mode. 72 Transmit differential data output negative pin for 10BASE-T/100 BASE-TX in MDI mode or receive differential data input negative pin in MDIX mode. 20 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY RSET_BG AO 65 For Ethernet PHY's internal biasing. Please connect to GND3A through a 12.1Kohm +/-1% resistor. LNK_LED O5/8m 30 Link status LED indicator. This pin drives low continuously when the Ethernet link is up and drives low and high in turn (blinking) when Ethernet PHY is in receiving or transmitting state. Note that this is a multi-function pin (DB_DI/LNK_LED), depending on the setting of DBG_PSEL bit in I2C EEPROM offset 0x01, see section 3.1.2 for details. SPD_LED O5/8m 31 Ethernet speed LED indicator. This pin drives low when the Ethernet PHY is in 100BASE-TX mode and drives high when in 10BASE-T mode. Note that this is a multi-function pin (DB_CKO/SPD_LED), depending on the setting of DBG_PSEL bit in I2C EEPROM offset 0x01, see section 3.1.2 for details. FD_CL_LED O5/8m 32 Full duplex and collision detected LED indicator. This pin drives low when the Ethernet PHY is in full-duplex mode and drives high when in half duplex mode. When in half duplex mode and the Ethernet PHY detects collision, it will be driven low. Note that this is a multi-function pin (DB_DO/FD_CL_LED), depending on the setting of DBG_PSEL bit in I2C EEPROM offset 0x01, see section 3.1.2 for details. MII and Station Management Interface MDC O5/4m/8m/ 77 Station management clock output and the timing reference for MDIO. All data PU transferred on MDIO are synchronized to the rising edge of this clock. The frequency of MDC is 1.5MHz. Note that this is a multi-function pin (P10/LA0/MDC), depending on the setting of P1_PSEL bits in I2C EEPROM offset 0x02, see section 3.1.3 for details. The output driving strength is programmable, by the P1_ODS bit in I2C Configuration EEPROM offset 0x04. See section 3.1.4 for details. MDIO B5/T/4m/8 79 Station management data input/output. Serial data input/output transferred from/to m/PU the PHYs. The transfer protocol conforms to the IEEE 802.3u MII spec. Note that this is a multi-function pin (P11/LA1/MDIO), depending on the setting of P1_PSEL bits in I2C EEPROM offset 0x02, see section 3.1.3 for details. The output driving strength is programmable, by the P1_ODS bit in I2C Configuration EEPROM offset 0x04. See section 3.1.4 for details. RX_CLK I5 5 Receive clock. RX_CLK is received from PHY to provide timing reference for the transfer of MRXD [3:0], RX_DV, and RX_ER signals on receive direction of MII interface. Note that this is a multi-function pin (P20/LDA0/RX_CLK), depending on the setting of P2_PSEL bits in I2C EEPROM offset 0x02, see section 3.1.3 for details. MRXD [3:0] I5 17, 14, Receive data. MRXD [3:0] is driven synchronously with respect to RX_CLK by 12, 9 PHY. Note that these are multi-function pins (P24/LDA4/MRXD3, P23/LDA3/MRXD2, P22/LDA2/MRXD1, P21/LDA1/MRXD0), depending on the setting of P2_PSEL bits in I2C EEPROM offset 0x02, see section 3.1.3 for details. RX_DV I5 19 Receive data valid. RX_DV is driven synchronously with respect to RX_CLK by PHY. It is asserted high when valid data is present on MRXD [3:0]. Note that this is a multi-function pin (P25/LDA5/RX_DV), depending on the setting of P2_PSEL bits in I2C EEPROM offset 0x02, see section 3.1.3 for details. RX_ER I5 27 Receive error. RX_ER is driven synchronously with respect to RX_CLK by PHY. It is asserted high for one or more RX_CLK periods to indicate to the MAC that an error has detected. Note that this is a multi-function pin (P27/LDA7/RX_ER), depending on the setting of P2_PSEL bits in I2C EEPROM offset 0x02, see section 3.1.3 for details. COL I5 93 Collision detected. COL is driven high by PHY when the collision is detected. Note that this is a multi-function pin (P37/LDA15/COL), depending on the setting of P3_PSEL bits in I2C EEPROM offset 0x02, see section 3.1.3 for details. 21 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY CRS I5 TX_CLK I5 MTXD [3:0] O5/4m/8m TX_EN O5/4m/8m TX_ER O5/4m/8m LCS0_N B5/4m LCS1_N O5/4m/8m LALE B5/4m/8m LWR_N B5/4m/8m 21 Carrier sense. CRS is asserted high asynchronously by the PHY when either transmit or receive medium is non-idle. Note that this is a multi-function pin (P26/LDA6/CRS), depending on the setting of P2_PSEL bits in I2C EEPROM offset 0x02, see section 3.1.3 for details. 78 Transmit clock. TX_CLK is received from PHY to provide timing reference for the transfer of MTXD [3:0], TX_EN and TX_ER signals on transmit direction of MII interface. Note that this is a multi-function pin (P30/LDA8/TX_CLK), depending on the setting of P3_PSEL bits in I2C EEPROM offset 0x02, see section 3.1.3 for details. 88, 86, Transmit data. MTXD [3:0] is transitioned synchronously with respect to the rising 82, 80 edge of TX_CLK. Note that these are multi-function pins (P34/LDA12/MTXD3, P33/LDA11/MTXD2, P32/LDA10/MTXD1, P31/LDA9/MTXD0), depending on the setting of P3_PSEL bits in I2C EEPROM offset 0x02, see section 3.1.3 for details. The output driving strength is programmable, by the P3_ODS bit in I2C Configuration EEPROM offset 0x04. See section 3.1.4 for details. 89 Transmit enable. TX_EN is transitioned synchronously with respect to the rising edge of TX_CLK. TX_EN is asserted high to indicate a valid MTXD [3:0]. Note that this a multi-function pin (P35/LDA13/TX_EN), depending on the setting of P3_PSEL bits in I2C EEPROM offset 0x02, see section 3.1.3 for details. The output driving strength is programmable, by the P3_ODS bit in I2C Configuration EEPROM offset 0x04 See section 3.1.4 for details. 92 Transmit coding error. TX_ER is transitioned synchronously with respect to the rising edge of TX_CLK. When asserted high for one or more TX_CLK, the PHY shall emit one or more code-groups that are not part of the valid data or delimiter set somewhere in the frame being transmitted. Note that this a multi-function pin (P36/LDA14/TX_ER), depending on the setting of P3_PSEL bits in I2C EEPROM offset 0x02, see section 3.1.3 for details. The output driving strength is programmable, by the P3_ODS bit in I2C Configuration EEPROM offset 0x04. See section 3.1.4 for details. Local Bus Interface 107 Local bus chip select 0. This is an output when local bus interface is operating in master mode, or an input when local bus interface is in slave mode. Note that this a multi-function pin (RXD1/LCS0_N/ECI), depending on the setting of UIT_PSEL bits in I2C EEPROM offset 0x03, see section 3.1.3 for details. 110 Local bus chip select 1 output, active low. This is used in local bus master mode only. Note that this is a multi-function pin (TXD1/LCS1_N/CEX0), depending on the setting of UIT_PSEL bits in I2C EEPROM offset 0x03, see section 3.1.3 for details. The output driving strength is programmable, by the PCA_ODS bit in I2C Configuration EEPROM offset 0x04. See section 3.1.4 for details. 8 Local bus address latch enable. This is an output when local bus interface is operating in master mode, or an input when local bus interface is in slave mode. Note that this is a multi-function pin (TM0_CK/LALE), depending on the setting of UIT_PSEL bits in I2C EEPROM offset 0x03, see section 3.1.3 for details. The output driving strength is programmable, by the PCA_ODS bit in I2C Configuration EEPROM offset 0x04. See section 3.1.4 for details. 10 Local bus write enable. This is an output when local bus interface is operating in master mode, or an input when local bus interface is in slave mode. Note that this is a multi-function pin (TM0_GT/LWR_N), depending on the setting of UIT_PSEL bits in I2C EEPROM offset 0x03, see section 3.1.3 for details. The output driving strength is programmable, by the PCA_ODS bit in I2C Configuration EEPROM offset 0x04. See section 3.1.4 for details. 22 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY LRD_N B5/4m/8m 11 LINT B5/4m/8m 116 LUDS_N B5/4m/8m 15 LLDS_N B5/4m/8m 16 LRDY B5/4m/8m 13 LA [3:0] B5/4m/8m 85, 81, 79, 77 LA [15:4] O5/4m/8m 35, 34, 28, 25, 23, 22, 20, 18, 95, 94, 91, 87, Local bus read enable. This is an output when local bus interface is operating in master mode, or an input when local bus interface is in slave mode. Note that this is a multi-function pin (TM1_CK/LRD_N/CEX1), depending on the setting of TM_PSEL bits in I2C EEPROM offset 0x03, see section 3.1.3 for details. The output driving strength is programmable, by the PCA_ODS bit in I2C Configuration EEPROM offset 0x04. See section 3.1.4 for details. Local bus interrupt. This is an input when local bus interface is operating in master mode, or an output when local bus interface is in slave mode. Note that this is a multi-function pin (INT1/LINT), depending on the setting of UIT_PSEL bits in I2C EEPROM offset 0x03, see section 3.1.3 for details. The output driving strength is programmable, by the PCA_ODS bit in I2C Configuration EEPROM offset 0x04. See section 3.1.4 for details. Local bus high byte data strobe. This is an output when local bus interface is operating in master mode, or an input when local bus interface is in slave mode. Note that this is a multi-function pin (TM2_CK/LUDS_N/CEX3), depending on the setting of TM_PSEL bits in I2C EEPROM offset 0x03, see section 3.1.3 for details. The output driving strength is programmable, by the PCA_ODS bit in I2C Configuration EEPROM offset 0x04. See section 3.1.4 for details. Local bus low byte data strobe. This is an output when local bus interface is operating in master mode, or an input when local bus interface is in slave mode. Note that this is a multi-function pin (TM2_GT/LLDS_N/CEX4), depending on the setting of TM_PSEL bits in I2C EEPROM offset 0x03, see section 3.1.3 for details. The output driving strength is programmable, by the PCA_ODS bit in I2C Configuration EEPROM offset 0x04. See section 3.1.4 for details. Local bus ready. This is an input when local bus interface is operating in master mode, or an output when local bus interface is in slave mode. Note that this is a multi-function pin (TM1_GT/LRDY/CEX2), depending on the setting of TM_PSEL bits in I2C EEPROM offset 0x03, see section 3.1.3 for details. The output driving strength is programmable, by the PCA_ODS bit in I2C Configuration EEPROM offset 0x04. See section 3.1.4 for details. Local bus address when in non-multiplexed address and data bus mode. When local bus interface is operating in master mode, these are outputs and provide the lower 4 bits of address lines. When local bus interface is in slave mode, these are inputs and provide the 4 address lines. Note that these are multi-function pins (P13/LA3/RE_N, P12/LA2/DE, P11/LA1/MDIO, P10/LA0/MDC), depending on the setting of P1_PSEL bits in I2C EEPROM offset 0x02, see section 3.1.3 for details. The output driving strength is programmable, by P1_ODS bit in I2C Configuration EEPROM offset 0x04. See section 3.1.4 for details. Local bus address when in non-multiplexed address and data bus mode. When local bus interface is operating in master mode, these outputs provide the upper 12 bits of the 16 address lines. When local bus interface is in slave mode, these are not used. Note that these are multi-function pins (P07/LA15/DTR, P06/LA14/RTS, P05/LA13/DCD, P04/LA12/RI, P03/LA11/DSR, P02/LA10/CTS, P01/LA9/TXD2, P00/LA8/RXD2, P17/LA7, P16/LA6, P15/LA5, P14/LA4), depending on the setting of P1_PSEL and P1_PSEL bits in I2C EEPROM offset 0x02, see section 3.1.3 for details. The output driving strength is programmable, by P0_ODS and P1_ODS bits in I2C Configuration EEPROM offset 0x04. See section 3.1.4 for details. 23 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY LDA [15:0] B5/4m/8m 93, 92, 89, 88, 86, 82, 80, 78, 27, 21, 19, 17, 14, 12, 9, 5 RD_DRQ I3 40 RD_DAK O3/4m 44 WR_DRQ I3 58 WR_DAK O3/4m/8m 56 RST_N I5/PU/S 120 SYS_RSTO_ N O5/4m 83 XTL25P O18 63 XTL25N I18 62 Local bus data or local bus address/data. When in non-multiplexed address and data bus mode, this serves as local bus data lines. When in multiplexed address and data bus mode, this serves as local bus address and data lines. Note that when in 8-bit mode local bus data, the LDA [7:0] is used. Note that these are multi-function pins (P37/LDA15/COL, P36/LDA14/TX_ER, P35/LDA13/TX_EN, P34/LDA12/MTXD3, P33/LDA11/MXD2, P32/LDA10/MTXD1, P31/LDA9/MTXD0, P30/LDA8/TX_CLK, P27/LDA7/RX_ER, P26/LDA6/CRS, P25/LDA5/RX_DV, P24/LDA4/MRXD3, P23/LDA3/MRXD2, P22/LDA2/MRXD1, P21/LDA1/MRXD0, P20/LDA0/RX_CLK), depending on the setting of P2_PSEL and P3_PSEL bits in I2C EEPROM offset 0x02, see section 3.1.3 for details. The output driving strength is programmable, by P2_ODS and P3_ODS bits in I2C Configuration EEPROM offset 0x04. See section 3.1.4 for details. DMA read request. Note that this is a multi-function pin (XROMCE1_N/RD_DRQ), depending on the setting of MI_PSEL bit in I2C EEPROM offset 0x03, see section 3.1.3 for details. DMA read acknowledge. Note that this is a multi-function pin (XRAMCE1_N/RD_DAK), depending on the setting of MI_PSEL bit in I2C EEPROM offset 0x03, see section 3.1.3 for details. DMA write request. Note that this is a multi-function pin (XADDR19/WR_DRQ), depending on the setting of MI_PSEL bit in I2C EEPROM offset 0x03, see section 3.1.3 for details. DMA write acknowledge. Note that this is a multi-function pin (XADDR20/WR_DAK), depending on the setting of MI_PSEL bit in I2C EEPROM offset 0x03, see section 3.1.3 for details. The output driving strength is programmable, by MI_ODS bit in I2C EEPROM offset 0x04. See section 3.1.4 for details. Misc. Pins Chip reset input, active low. This is the external reset source used to reset this chip. This input feeds to the internal power-on reset circuitry, which then provides the main reset source of this chip. Chip system reset output, active low. This output reflects the actual reset state of internal CPU. When low the internal CPU is in reset state, when high the CPU is in normal functional state. 25Mhz crystal or oscillator clock output. The recommended reference frequency is 25Mhz +/- 0.005% (i.e. 25Mhz +/- 1250hz). 25Mhz crystal or oscillator clock input. The recommended reference frequency is 25Mhz +/- 0.005% (i.e. 25Mhz +/- 1250hz). 24 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY LB_CLK B5/8m 97 In synchronous mode of Local Bus interface, this pin is used as clock source for the system logic in Local Bus slave mode or as clock output in Local Bus master mode. When used as clock source, the input frequency should be either 25Mhz or 50Mhz (so that the internal timer/counter can work properly). When used as clock output, it provides the operating system clock of this chip to external local bus device. The mode of operation is determined by LB_MOD and SYNC_BUS state during chip hardware reset. LB_MOD Pulled-up SYSCK_SEL[ 1:0] I3 EXT_WKUP I5/PU VCC3R GND3R VCC18 P P P VCCK P VCCIO P GND P VCC18A GND18A VCC3A GND3A P P P P SYNC_BUS LB_CLK Pulled-up The LB_CLK instead of internal 100Mhz PLL is the clock source for operating system clock. In this case, user can provide either 25Mhz or 50Mhz clock input to this pin. Also, the SYSCK_SEL should be set to 00 or 01 accordingly so that the internal timer/counter can work properly. Pulled-down Pulled-up The LB_CLK is a clock output, which provides the operating system clock of this chip to the external local bus device. Pulled-up Pulled-down The LB_CLK is not used. In this case, please add a pulled-up resistor to this pin such that it draws minimum current. 50, 42 Operating system clock frequency selection: 00: Set the operating CPU clock to 25Mhz. 01: Set the operating CPU clock to 50Mhz. 10: Reserved. 11: Set the operating CPU clock to 100Mhz. 112 External remote-wakeup trigger input pin, rising edge. Note that the EXT_WKUP is a dual-function input pin sharing with INT0 pin. On-chip Regulator Pins 75 3.3V power supply to on-chip 3.3V to 1.8V voltage regulator. 74 Ground pin of on-chip 3.3V to 1.8V voltage regulator. 76 1.8V voltage output of on-chip 3.3V to 1.8V voltage regulator. Please add 1uF capacitor between VCC18 and GND3R. Power and Ground Pins 7, 26, 36, Digital core power, 1.8V. 59, 84, 99, 125 24, 46, Digital I/O power, 3.3V. 57, 90, 126 29, 55, Digital ground for core and I/O. 96, 128 61, 70 Analog power for oscillator, PLL, and Ethernet PHY differential I/O pins, 1.8V 64, 73 Analog ground for oscillator, PLL, and Ethernet PHY differential I/O pins. 66 Analog power for bandgap, 3.3V. 67 Analog ground for bandgap. 25 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 2.0 Function Description 2.1 Clock Generation The AX11015 integrates an internal 25Mhz oscillator, which allows the chip to operate cost effectively with just an external 25Mhz crystal. The 25Mhz oscillator provides reference clock to the internal PLL circuit, which generate a free-run 100Mhz clock source for system logic and a 125Mhz clock source for the internal Ethernet PHY use. The operating system clock is derived from the 100Mhz clock source from PLL and is programmable between 25Mhz, 50Mhz, and 100Mhz, based on the setting of SYSCK_SEL [1:0] input pins. The users can trade off between system performance and power consumption to decide the best operating system clock frequency. The AX11015 supports a deep power-down mode (CPU STOP mode) where the internal 25Mhz crystal oscillator and PLL circuit can be completely disabled to consume minimum power. The AX11015 also supports the Power Management Mode (PMM) where the operating system clock frequency is reduced to 1/100 of the original frequency (i.e., 0.25Mhz, 0.5Mhz, and 1Mhz) to reduce power consumption during PMM mode. The AX11015 also has an external clock source input pin called LB_CLK, which can be used as clock source for system logic. This is typically used in synchronous mode of local bus interface where the AX11015 operating as local bus slave mode is a local bus device for the main system CPU. For more details on chip clock configuration and distribution, please refer to section 4.1. 2.2 Reset Generation The AX11015 integrates an internal power-on-reset circuit, which can simplify the external reset circuitry on PCB design. The power-on-reset circuit shall generate a reset pulse to reset system logic after 1.8V core power ramping up to 1.2V (typical threshold). The external hardware reset input pin, RST_N, is fed directly to the input of power-on-reset circuit and can also be used as additional hardware reset source to reset the system logic. If the internal power-on-reset circuit is used as main reset source, user shall connect RST_N pin to a simple RC reset, which shall generate a low level of at least 4 msec intervals after 1.8V core power ramping up to 1.8V to correctly reset the system logic. If the system has a dedicated reset source connecting to RST_N, this reset source shall also generate a low level of at least 4 msec intervals after 1.8V core power ramping up to 1.8V to correctly reset the system logic. The optional system reset output pin, SYS_RSTO_N, is a reset indication signal to be used by users who need to control the reset of peripheral devices working with AX11015 in system. This reset output reflects the actual reset state of internal CPU. For more details on chip reset distribution, please refer to section 4.2 and section 5.3. 2.3 Voltage Regulator The AX11015 contains an internal 3.3V to 1.8V low-dropout-voltage and low-standby-current voltage regulator. The internal regulator provides up to 240mA of driving current for the 1.8V core/analog power of the chip to satisfy the worst-case power consumption scenario. Also for the purpose of lowering power consumption in deep power-down mode or PMM mode, the internal regulator can operate in standby mode to consume less current when the required driving current is less than 30mA. For more details on voltage regulator DC characteristic, please refer to section 5.1.6. 26 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 2.4 CPU Core and Debugger 2.4.1 CPU Core The 1T 8051/80390 CPU core of AX11015 is an ultra high performance, speed optimized, 8-bit embedded controller dedicated for operation with fast (on-chip) and slow (off-chip) memories. The CPU core has been designed with a special concern about performance to power consumption ratio. The CPU core is 100% binary-compatible with the industry standard 8051 8-bit micro-controller. The CPU core can address up to 2 M bytes of linear program space. The CPU core has Pipelined RISC architecture, which can be 10 times faster compared to standard architecture and executes 100 million instructions per second when operating in 100Mhz. The main features of 1T 8051/80390 CPU core are listed below, for more details, please refer to section 4.4. z 100% software compatible with industry standard 8051 z Maximum operating clock frequency of 100M Hz z Pipelined RISC architecture enables to execute instructions 10 times faster compared to standard 8051 21-bit FLAT program addressing mode - 80C390 instructions set 16-bit LARGE program addressing mode - 80C51 instructions set z 24 times faster multiplication z 12 times faster addition z 256 bytes of internal (on-chip) Data Memory z Up to 2M bytes of Program Memory On-chip SRAM used for mirrored program: 0 to 16K bytes On-chip Flash memory used for program: 0 to 512K bytes in FLAT mode Off-chip Flash memory used for program: 512K bytes to 2M bytes in FLAT mode z Up to 2M bytes of External Data Memory On-chip SRAM used for External Data Memory: 0 to 32K bytes Off-chip SRAM used for External Data Memory: 32K bytes to 2M bytes z User programmable Program Memory wait states for wide range of memory speed z User programmable External Data Memory wait states for wide range of memory speed z Dedicated address/data/controlled bus to allow easy and glueless connection to external Flash/SRAM memory 2.4.2 Debugger The Debugger inside AX11015 provides an in-circuit emulator feature and it is used to connect to an external In-Circuit-Emulation (ICE) adaptor board, which manages communication between the Debugger inside AX11015 and the Debug Software on a PC. As shown in Figure 14, the Hardware Assisted Debugger (HAD2) is the ICE adaptor board. The HAD2 is a small hardware adapter that manages communication between the Debugger inside AX11015 and an USB port of the host PC running Debug Software. The USB communication interface to target host PC is at USB Full speed and its power supply comes directly from the USB port. The Debug Software is a Windows based application. It is fully compatible with all existing 8051/80390 C compilers and Assemblers. The Debug Software allows user to work in two major modes: software simulator mode and hardware debugger mode. Those two modes assure software validation in simulation mode and then real-time debugging of developed software inside AX11015 using debugger mode. Once loaded, the program may be observed in Source Window, run at full-speed, single stepped by machine or C level instructions, or stopped at any of the breakpoints. For more detailed description about the Debug Software, please refer to "AX110xx Software User Guide". 27 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Figure 14: Typical Debugger and Hardware Assisted Debugger (HAD2) System Diagram The main features of Debugger inside AX11015 are listed below, z Processor execution control Run, Halt Reset Step into instruction Skip Instruction z Read-write all processor contents Program Counter (PC) Program Memory Internal (direct) Data Memory Special Function Registers (SFRs) External Data Memory z Code execution breakpoints - one real-time PC breakpoint z Hardware execution watch-points Two at Internal (direct) Data Memory Two at Special Function Registers (SFRs) Two at External Data Memory z Hardware watch-points activated at a certain address by any write into memory certain address by any read from memory 28 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY certain address by write into memory a required data certain address by read from memory a required data z Unlimited number of software watch-points Internal (direct) Data Memory Special Function Registers (SFRs) External Data Memory z Unlimited number of software breakpoints - Program Memory (PC) z Automatic adjustment of debug data transfer speed rate between HAD and CPU core z Communication interface - DTAG three wire communication 2.5 On-Chip Flash Memory The AX11015 embeds an on-chip Flash memory of 512K bytes. The main features of the Flash memory are listed below, z Requires only 3.3V power for read, erase and program operations z Fast read access time: 55ns z Command register architecture z z Byte programming time: 9us (typical) Sector Erase (Sector structure 16K Byte x 1, 8K Byte x 2, 32K Byte x1, and 64K Byte x7) Auto Erase (chip & sector) and Auto Program Automatically erase any combination of sectors with Erase Suspend capability Automatically program and verify data at specified address Erase Suspend/Erase Resume z Status Reply z Suspends sector erase operation to read data from, or program data to, any sector that is not being erased, and then resumes the erase operation. Data# Polling & Toggle bit for detection of program and erase operation completion. Sector protection Hardware method to disable any combination of sectors from program or erase operations Temporary sector unprotect allows code changes in previously locked sectors. z 100,000 minimum erase/program cycles z 20 years data retention z Program code download protection in hardware to disable Debugger access for preventing unauthorized program code downloading. For more detailed description, please refer to section 4.5. 29 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 2.6 Memory Arbiter and Boot Loader The external memory interface of AX11015 allows simple and easy connections for up to one external Flash memory chip and two external SRAM chips without any glue logic. The external Flash memory provides additional program code storage for those applications, which require more than 512K bytes of program code size. The external SRAM chips provide data memory expansion for those applications, which require more than 32K bytes of data storage. The external SRAM chips can also function as program code storage in "program code shadow" mode for applications, which require higher performance. The addressable memory space of first external SRAM chip using chip enable pin, XRAMCE0_N, is programmable (via the ASCS bits in I2C Configuration EEPROM offset 0x01, see section 3.1.2 for details), which allows user to choose from 64K bytes, 128K bytes, 256K bytes, 512K bytes, or 1024K bytes of SRAM chip whichever is most cost effective. Depending on system applications and requirements, following scenarios of Flash memory and SRAM configurations can be possibly used, as shown in Figure 15, Figure 16, Figure 17, and Figure 18. No external Flash memory or SRAM chips are needed. AX11015 512KB Program Flash + 32KB Data Memory Figure 15: Systems requiring only 512K bytes of Program Flash and 32K bytes of Data Memory CE# XRAMCE1_N AX11015 CE# XRAMCE0_N WE# XDATWR_N 512KB Program Flash + 32KB Data Memory OE# XDATRD_N A[18:0] XADDR [20:0] 1 or 2 Async. SRAM I/O[7:0] XDATA [7:0] Figure 16: Systems requiring 512K bytes Program Flash and over 32K bytes Data Memory 30 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY XROMCE1_N CE# XPRGWR_N WE# XPRGRD_N OE# AX11015 External Flash Memory A[18:0] Q[7:0] 512KB Program Flash + 32KB Data Memory XRAMCE1_N CE# XRAMCE0_N CE# XDATWR_N WE# XDATRD_N OE# XADDR [20:0] A[18:0] XDATA [7:0] I/O[7:0] 1 or 2 Async. SRAM Figure 17: Systems Requiring over 512K bytes Program Flash and over 32K bytes Data Memory XRAMCE0_N CE# XDATWR_N WE# XDATRD_N OE# XADDR [20:0] A[18:0] XDATA [7:0] I/O[7:0] XRAMCE1_N CE# Async. SRAM #1 First portion of SRAM could be used for program code shadow and remaining for data memory expansion AX11015 WE# 512KB Program Flash + 32KB Data Memory OE# A[18:0] Optional Async. SRAM #2 I/O[7:0] Figure 18: Systems requiring 512K bytes Program Flash and over 32K bytes Data Memory for High Performance 31 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY The memory arbiter and boot loader of AX11015 support three major functions - Boot loader, Memory arbiter, and Flash programming controller, as described in following sections. 2.6.1 Boot Loader The boot loader shall activate right after hardware reset (either power-on-reset or RST_N input) or software reboot command (via SFR register CSREPR). It shall automatically perform copying the program code from Flash memory to on-chip 16KB SRAM for "program code mirroring", and upon enabled (via EXT_PROG_SRAM_EN pin), also automatically perform copying the program code from on-chip/off-chip Flash memory to off-chip SRAM for "program code shadow" mode for high performance applications. The "program code mirroring" allows the program code residing on on-chip Flash memory space 0~16K bytes to be mirrored to on-chip 16Kbytes SRAM before the 1T 80390 CPU starts running. This on-chip 16Kbytes SRAM located at program memory space 0~16K bytes of the 1T 80390 CPU will be used to execute program code with 0 wait state to achieve top performance of 100 MIPS. During time of firmware update via Ethernet or UART, the 16K bytes of mirrored program code on SRAM shall perform Flash write commands to write new firmware into the Flash memory. This allows the program code being executed continuously while the Flash memory is being updated. The "program code shadow" mode allows both the program code residing on on-chip Flash memory space 16K~512K bytes and the program code residing on off-chip Flash memory to be shadowed to off-chip SRAM chips before the 1T 80390 CPU starts running. The off-chip SRAM chips located at program memory space 16K~2M bytes of the 1T 80390 CPU can then be used to execute program code with 0 or 1 wait state. For more details, please refer to section 4.6. 2.6.2 Memory Arbiter The memory arbiter manages Program memory and External Data (xDATA) memory bus access. It arbitrates the access of xDATA memory between 1T 80390 CPU and the Direct Memory Access (DMA) engine, and upon enabling program code shadow, it also redirects the 1T 80390 CPU program access from Flash memory to off-chip SRAM chips. The xDATA memory access could come from 1T 80390 CPU, the DMA from TCP/IP Offload Engine (TOE), and DMA for Local Bus Interface (LBI). The arbitration priority is that, the 1T 80390 CPU's access to Program memory and xDATA memory has the highest priority, the DMA for LBI is given the second priority, and the DMA for TOE is the last. Upon enabling "program code shadow" mode, the memory arbiter shall redirect 1T 80390 CPU's program access from Flash memory to external SRAM chips. Upon enabled, the memory arbiter also allows the external SRAM chips to be used as "program code shadow" and "xDATA memory expansion" purposes at the same time (shared memory architecture), therefore, allowing 1T program code execution as well as xDATA memory expansion capability cost effectively on the same SRAM chips. For more details, please refer to section 4.6. 2.6.3 Flash Programming Controller The Flash programming controller supports In-System-Programming (ISP) for both on-chip Flash memory of AX11015 and off-chip Flash memory on PCB via UART 0 interface of AX11015. When enabled (via BURN_FLASH_EN pin), it allows on-chip/off-chip Flash memory to be programmed by ASIX's Flash Programming utilities software on a PC with a standard RS-232 port, as shown in Figure 19. The link speed of AX11015's UART 0 used for communicating to the PC's RS-232 port can be chosen to be either 921.6K or 115.2K bps (via BURN_FLASH_921K pin). When developing software for AX11015 or manufacturing the system with AX11015 on it, the ASIX's Flash Programming utilities software can provide easy and fast Flash memory update capability. 32 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Running ASIX's Flash Programming utilities software AX11015 UART0 RS232 XCVR Flash Programming Controller COM port On-chip Flash memory Off-chip Flash memory Figure 19: Flash Memory Programming System Configuration During Flash programming process, the Flash Programming Controller (FPC) in AX11015 shall receive commands from Flash Programming utilities software through the UART 0 interface. The commands received are in form of packets from which FPC will decode, execute, and then acknowledge the result back to the software utilities. The command handshaking structure is simple and flexible to simplify the FPC design while at the same time addressing the long programming time, complex programming procedures, command compatibility issues of Flash memory. For more details, please refer to section 4.6. 2.7 DMA Engine The direct memory access (DMA) engine of AX11015 handles External Data (xDATA) memory read and write access for TCP/IP Offload Engine (TOE), Local Bus Interface (LBI) and Digiport, as well as bulk data copy for software DMA. The TOE can receive packets from Ethernet MAC and store them in xDATA memory via DMA write access, or it can transmit packets to Ethernet MAC from xDATA memory via DMA read access. In LBI master mode, it can perform burst data read from external local bus devices and store the data in xDATA memory via DMA write access, or it can perform burst data write to external local bus devices by reading data from xDATA memory via DMA read access. In Digiport parallel or Digiport SPI streaming video receive mode, it can perform burst data read from external STv0676 or STv0684 chips and store the data in xDATA memory via DMA write access In LBI slave mode, it can perform receiving burst data (during external CPU burst write access) and store them in xDATA memory via DMA write access, or it can perform outputting burst data (during external CPU burst read access) by reading out data from xDATA memory via DMA read access. The DMA engine also can support software DMA, which performs bulk data copy from one region of xDATA memory to another region in a timely manner, based on software configuration. The hardware based DMA engine can greatly reduce the time spending in bulk data movement very often needed in network protocol stack processing, and, hence, help achieve better performance on micro-controller computing power. For more details, please refer to section 4.7. 33 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 2.8 Interrupt Controller The interrupt controller of AX11015 supports 2 external interrupt pins, INT0 and INT1, with each having two levels of interrupt priority control. They can be in high or low-level priority group (setting via SFR register IP, EIP). The 2 external interrupt pins can be activated at low level or by a falling edge. As shown in Table 2 below, the interrupt controller also supports various interrupt requests internal to the AX11015, again each having two levels of interrupt priority control. For more details, prefer to section 4.8. Interrupt Sources Function Description Active level Vector Natural Priority INT 0 The external interrupt input pin, INT0 Active low 0x03 or falling edge 1 Timer 0 The internal Timer 0 interrupt request 0x0B 2 INT 1 The external interrupt input pin, INT1 Active low 0x13 or falling edge 3 Timer 1 The internal Timer 1 interrupt request 0x1B 4 UART 0 The internal UART 0 interrupt request 0x23 5 Timer 2 The internal Timer 2 interrupt request 0x2B 6 UART 1 The internal UART 1 interrupt request 0x33 7 INT 2 The internal DMA transfer interrupt request for TOE/LBI/software DMA mode, please set to high priority 0x3B 8 INT 3 The internal programmable counter array interrupt request 0x43 9 INT 4 The internal peripheral interrupt request for TOE, MAC/PHY, LBI, I2C, SPI, 1-Wire, UART2, etc. 0x4B 10 INT 5 The internal software DMA complete and millisecond timer timeout interrupt 0x53 11 INT 6 The wake-up interrupt request (resume from CPU STOP mode) 0x5B 12 0x63 13 Watchdog Internal watchdog interrupt Table 2: Interrupt Controller Summary 34 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 2.9 Watchdog Timer The watchdog timer of AX11015 is a user programmable clock counter that can serve as: z A time-base generator z An event timer z System supervisor As shown in Figure 20, the watchdog timer is driven by the main system clock, which is supplied to a series of dividers. The divider output is selectable, and determines interval between timeouts. When the timeout is reached, an interrupt flag will be set, and if enabled, a reset will occur (to reset CPU core). The interrupt flag will cause an interrupt to occur if its individual enable bit is set and the global interrupt enable is set. The reset and interrupt are discrete functions that may be acknowledged or ignored, together or separately for various applications. For more details, please refer to section 4.9. Figure 20: Watchdog Timer Block Diagram 35 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 2.10 Power Management Unit The power management unit of AX11015 supports two power conservation modes - Power Management Mode (PMM) and STOP mode. 2.10.1 PMM When entering the PMM (via SFR register PCON) from full speed mode, most system logic of AX11015 shall run at slower clock frequency (1/100 of original clock frequency) to reduce power consumption. The PMM is entered and exited by setting the PMM bit (PCON.0) by software. The PMM mode also supports the "switchback" feature using SWB bit (PCON.2). The "switchback" feature of PMM allows the AX11015 to almost immediately return to the full speed mode from PMM, upon acknowledgement of an interrupt or a falling edge on a serial port receiver pin. The following events can trigger AX11015 switchback to full speed mode from PMM: z Receive interrupt on external interrupt pin, INT0 or INT1 z Detect falling-edge transition (start bit) on RXD0 pin of UART 0 or RXD1 pin of UART 1 z Transmit buffer loaded on UART0 or UART1 z Watchdog timer reset In addition, the following events can also trigger AX11015 switchback to full speed mode from PMM, via INT 6: z Receive rising-edge signal on external remote-wakeup trigger input pin, EXT_WKUP, if enabled z Receive Magic packet from Ethernet, if enabled z Receive pre-defined Wakeup frame from Ethernet, if enabled z Detect link-up signal from the embedded Ethernet PHY, if enabled z Detect link-up signal from secondary PHY, if enabled z Detect falling-edge transition (start bit) on RXD2 pin or falling-edge transition on RI pin of UART 2, if enabled 2.10.2 STOP Mode When entering the STOP mode (via SFR register PCON), the main system clock for most system logic of AX11015 shall be completely disabled to further reduce power consumption. The AX11015 supports entering the STOP mode with options of internal 25Mhz crystal oscillator and PLL circuit either still running or completely disabled via TOFFOP bit (Flag.1) in I2C Configuration EEPROM offset 0x01. The lowest power consumption that AX11015 can enter is the STOP mode with 25Mhz crystal oscillator and PLL circuit completely disabled. The software can enter the STOP mode from full speed mode or PMM by setting the STOP bit (PCON.1). After entering the STOP mode, no processing is possible, timers are stopped, and no serial communication is possible. A NOP instruction has to be added after an instruction that sets STOP bit. The NOP is added because of pipelining architecture of 1T 80390 CPU. The CPU operation will be postponed on the instruction that sets the STOP bit. If the STOP mode is entered with 25Mhz oscillator and PLL completely disabled, the STOP mode can be exited in following ways: z Receive rising-edge signal on external remote-wakeup trigger pin, EXT_WKUP, if enabled z Detect falling-edge transition (start bit) on RXD2 pin or falling-edge transition on RI pin of UART 2, if enabled z Receive hardware reset on RST_N pin (CPU operation will resume execution at address 0x00_0000) If the STOP mode is entered with 25Mhz oscillator and PLL still running, the STOP mode can be exited in following ways, depending on software configuration before entering the STOP mode: z Receive rising-edge signal on external remote-wakeup trigger pin, EXT_WKUP, if enabled z Receive Magic packet from Ethernet, if enabled 36 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY z Receive pre-defined Wakeup frame from Ethernet, if enabled z Detect link-up signal from the embedded Ethernet PHY, if enabled z Detect link-up signal from secondary PHY, if enabled z Detect falling-edge transition (start bit) on RXD2 pin or falling-edge transition on RI pin of UART 2, if enabled z Receive hardware reset on RST_N pin (CPU operation will resume execution at address 0x00_0000) Note that above trigger events use the non-clocked interrupt, INT6, to wake up 1T 80390 CPU and to re-enable the main system clock. The clocked interrupts such as the watchdog timer, internal timers, and serial ports (UART0/1) do not operate in STOP mode, therefore, can't be used as a trigger event to wake up from STOP mode. The 1T 80390 CPU operations will resume with the fetching of the interrupt vector associated with the interrupt that caused the exit from STOP mode. When the interrupt service routine will complete, RETI returns the program to the instruction immediately following the one that invoked the STOP mode. For more detailed description, please refer to section 4.10. 2.11 Timers and Counters The AX11015 contains three 16-bit timer/counters, namely, Timer 0, Timer 1, and a fully compatible with the standard 8052 Timer 2, and one dedicated Millisecond Timer which is programmable with 1ms resolution for software use. In the "timer mode", timer registers are incremented every 12 or 4 operating system clock periods when appropriate timer is enabled. In the "counter mode" the timer registers are incremented every falling transition on their corresponding input pins: TM0_CK, TM1_CK, or TM2_CK. The input pins are sampled every operating system clock period. The Timers 0, 1, 2 block diagram is shown in figure below. For more details, please refer to section 4.11. Figure 21: Timers 0, 1, and 2 Block Diagram 37 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 2.12 UARTs The AX11015 contains 3 UART interfaces, namely, UART 0, UART 1, and UART 2. 2.12.1 UART 0 and UART 1 The UART 0 and UART 1 of AX11015 have the same functionality as standard 8051 UARTs. Each is full duplex, meaning it can transmit and receive concurrently. Each is receive double-buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the receive register. UART 0 can operate in following 4 modes: z Mode 0, synchronous mode z Mode 1, 8-bit UART, variable baud rate, Timer 1 or Timer 2 clock source z Mode 2, 9-bit UART, fixed baud rate z Mode 3, 9-bit UART, variable baud rate, Timer 1 or Timer 2 clock source UART 1 can operate in following 4 modes: z Mode 0, synchronous mode z Mode 1, 8-bit UART, variable baud rate, Timer 1 clock source z Mode 2, 9-bit UART, fixed baud rate z Mode 3, 9-bit UART, variable baud rate, Timer 1 clock source The Figure 22 below shows the I/O buffer of RXD0/1 pin of UART 0/1, the RXD0/1 pin is tri-stated when RXD0/1_out is high. For more details, please refer to section 4.12. Weak internal pull-up RXD0_out, RXD1_out UART0, UART1 controller RXD0, RXD1 RXD0_in, RXD1_in Figure 22: I/O Buffer of RXD0 pin of UART 0 and RXD1 pin of RXD1 2.12.2 UART 2 The UART 2 of AX11015 is designed to be maximally compatible with standard 16550. It can communicate with MODEM or other external device (e.g. computer) by using RS-232 protocol. The UART 2 has 16-bytes deep transmit/receive FIFO and its transfer rate can be up to 921600 bps. The UART 2 includes a programmable baud rate generator capable of dividing the operating system clock by (27*N), where N = 1~65535, for generating wide range of baud rate for the internal transmitter/receiver logic. The main features of UART 2 are listed below, 38 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY z 16 bytes deep receive and transfer FIFO z Support up to 921600 bps baud z Detection of bad data in the receiver FIFO z Full-duplex asynchronous channel z Automatic send data control (ASDC) for automatically transmitter/receiver enable control for RS-485 z Modem control functions (CTS, RTS, DSR, DTR, RI and DCD) z Fully programmable serial interface - Even, odd, no parity bit generation and detection - 5, 6, 7, 8 data bit - 1, 1.5, 2 stop bit generation z Line break generation and detection z Internal diagnostic capabilities (loopback controls, break, parity, overrun and framing error) z Transmit, receive, line status, and data set interrupts independently controlled z Complete status reporting capabilities z Remote wakeup by detecting falling-edge transition (start bit) on RXD2 pin or falling-edge transition on RI pin For more details, please refer to section 4.12. 2.13 GPIOs The AX11015 supports four 8-bit bi-directional, open-drain, general purpose input and output ports, namely, P0 [7:0], P1 [7:0], P2 [7:0] and P3 [7:0]. Each port bit can be individually accessed by bit addressable instructions. The driving strength of the GPIO ports is programmable (4mA or 8mA, via I2C Configuration EEPROM offset 0x04, see section 3.1.4 for details). The Figure 23 below shows the I/O buffer of GPIO pins. For example, the P00 pin is tri-stated when P00_out is high. For more details, please refer to section 0. P0[7:0]_out, P1[7:0]_out, P2[7:0]_out, P3[7:0]_out, Internal GPIO registers Weak internal pull-up P0 [7:0], P1 [7:0], P2 [7:0], P3 [7:0] P0[7:0]_in, P1[7:0]_in, P2[7:0]_in, P3[7:0]_in, Figure 23: The I/O Buffer of GPIO Pins 39 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 2.14 TCP/IP Offload Engine The TCP/IP Offload Engine (TOE) of AX11015 supports some network layer 2 to 4 header processing functions in hardware. The layer-2 function of TOE interfaces to Ethernet MAC, while its layer-4 function interfaces to DMA engine for receiving/transmitting network packets to/from xDATA memory of AX11015. The TOE can operate in two different modes - "Non-Transparent" mode and "Transparent" mode. When TOE operating in "Transparent" mode, it supports following features, z VLAN ID filtering for received packets, if enabled z On-the-fly IPv4 packet header checksum check and generation (with or without PPPoE header, RFC2516) z Received packet filtering for IPv4 packets with error header checksum z On-the-fly TCP and UDP segment checksum check and generation z On-the-fly ICMP and IGMP message checksum check and generation z Received packet filtering for TCP/UDP/ICMP/IGMP packets with error checksum When TOE operating in "Non-Transparent" mode, it supports following features, z z z Layer-2 functions (the recognizable packet types are Ethernet II encapsulation (RFC894), IEEE 802.2/802.3 SNAP encapsulation (RFC1042), IEEE 802.2/802.3 encapsulation, and NetWare 802.3 RAW encapsulation) Ethernet MAC frame header parsing and encapsulation, including DA, SA, Length/Type, VLAN Tag fields. ARP Cache: When receiving, automatically learns the source IP address and SA of the received Ethernet MAC frames into ARP Cache SRAM When transmitting, automatically sends out ARP-Request packet when the ARP Cache is not found Upon receiving ARP-Request packet, automatically responds with ARP-Reply packet and updates ARP Cache Upon receiving ARP-Reply packet, automatically updates ARP Cache Software programmable timeout value for ARP Cache Timeout ARP Cache SRAM is software accessible VLAN ID filtering for received packets and VLAN Tag insertion for transmit packets, if enabled Received packet filtering for ARP-Request packet Remove layer 2 header of receive IPv4-type packets before forwarding up to Layer-3 function Append layer 2 header of transmit IPv4-type packets from Layer-3 function before passing down to Ethernet MAC Layer-3 functions: IPv4 header parsing, including version, header length, total length, protocol, header checksum, source IP address, destination IP address fields On-the-fly IPv4 header checksum check and generation (only when without PPPoE header bytes) Received packet filtering for IPv4 packets with version not equal to 4 or error header checksum Received packet filtering for IPv4 packets with wrong destination IP address (not equal to owned IP address, and not equal to broadcast IP address, and not equal to multicast IP address) and wrong source IP address (equal to broadcast IP address, or equal to multicast IP address) Layer 4 functions: On-the-fly TCP and UDP segment checksum check and generation On-the-fly ICMP and IGMP message checksum check and generation 40 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Received packet filtering for TCP/UDP/ICMP/IGMP packets with error checksum For more detailed description on TOE, please refer to section 4.14. 2.15 10/100M Ethernet MAC The 10/100M Ethernet MAC of AX11015 supports 802.3 and 802.3u MAC sub-layer functions as listed below, z MAC frame receive and transmit through MII interface z With dedicated receive buffer of 8K bytes SRAM and transmit buffer of 4K bytes SRAM z Flow-control support in full-duplex mode by monitoring receive buffer usage to compare with high water mark and low water mark for triggering flow control z Received MAC frame CRC check and transmit MAC frame CRC generation z Received packet filtering for broadcast, multicast, unicast, or CRC error MAC frames, etc. if enabled z Support collision-detection, exponential backoff, packet retransmission, and backpressure in half-duplex mode z Support Magic packet, predefined Wakeup frame, and Ethernet PHY linkup remote-wakeup mode. Upon detecting wakeup event, it can awake the AX11015 up from PMM or STOP mode z Provides additional media-independent interface (MII) interface for interfacing external HomePlug PHY or HomePNA PHY functions The 10/100M Ethernet MAC interfaces to both MII interface of the embedded 10/100M Ethernet PHY and the external MII interface I/O pins. The selection between the two MII interfaces is controlled by software. Figure 24 shows the data path diagram of the 10/100M Ethernet MAC, the embedded 10/100M Ethernet PHY, and external MII interface. For more detailed description, please refer to section 4.15. RX 10/100M Ethernet PHY 10/100M Ethernet MAC RXIP/RXIN TXOP/TXON MII Interface I/O: RX_CLK, MRXD [3:0], RX_DV, RX_ER, COL, CRS, TX_CLK, TX MTXD [3:0], TX_EN, TX_ER Figure 24: Internal Data path Diagram of 10/100M Ethernet MAC, 10/100 Ethernet PHY, and MII Interface The 10/100M Ethernet MAC also provides a two-wire, serial interface to connect to a managed PHY device for the purposes of controlling the PHY and gathering status from the PHY. This interface allows communicating with multiple PHY devices at the same time by identifying the managed PHY with 5-bit, unique PHY ID. The PHY ID of the embedded 10/100 Ethernet PHY is being pre-assigned to "1_0000". Figure 25 shows the internal control mux for the station management interface. When doing read, the "mdin" signal will select from embedded 10/100 Ethernet PHY only if PHY ID matches with "1_0000", otherwise, it will always select from external MDIO pin of the AX11015. 41 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 10/100M Ethernet PHY PHY ID = 1_0000 Weak internal pull-up MDC 10/100M Ethernet MAC mdout Weak internal pull-up mdin MDIO Figure 25: Internal Control Mux for Station Management Interface 2.16 10/100M Ethernet PHY The 10/100 Ethernet PHY of AX11015 is compliant with IEEE 802.3 and IEEE 802.3u standards. It contains an on-chip crystal oscillator, PLL-based clock multiplier, and digital phase-locked loop for data/timing recovery. It provides over-sampling mixed-signal transmit drivers complying with 10/100BASE-TX transmit wave-shaping / slew rate control requirements. It has robust mixed-signal loop adaptive equalizer for receiving signal recovery. z Support full-duplex mode, half-duplex mode, and auto-negotiation z Support twisted pair crossover detection and auto-correction (Auto-MDIX) z DSP-based adaptive line equalizer, providing superior immunity to near end crosstalk and inter-symbol interference z Fully compliant with 100BASE-TX, and 10BASE-T PMD level standards (IEEE 802.3u and IEEE 802.3) z DSP-controlled symbol timing recovery circuit z Baseline wander corrective circuits to compensate data dependent offset due to AC coupling transformers z Over-sampling mixed-signal transmit driver complies with 10/100BASE-TX transmit wave-shaping/slew-control requirements For more detailed description, please refer to section 4.16. 42 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 2.17 Programmable Counter Array The programmable counter array (PCA) present on the AX11015 is a special 16-bit timer that has five 16-bit capture/compare modules. It provides more timing capabilities with less CPU intervention than the standard timer/counter. Its advantages include reduced software overhead and improved accuracy. As shown Figure 26 below, the PCA have 6 I/O pins, one external clock input pin, ECI, and five capture/compare signal pins, CEX [4:0]. The PCA consists of a dedicated timer/counter, which serves as the time base for an array of five compare/capture modules. Each of the five modules can be programmed in any of the following modes: rising and/or falling edge capture, software timer, high speed output, and pulse width modulator (PWM). For more details, please refer to section 4.17. The PCA timer/counter uses operating system clock, Timer 0 overflow, and ECI, to generate reference clock for capture/compare modules. The 5 capture/compare modules use CEX [4:0] pins to communicate to external resource. The output driving strength of CEX [4:0] is programmable (4mA or 8mA, by PCA_ODS bit in I2C Configuration EEPROM offset 0x04, see section 3.1.4 for details). PCA related SFR registers Operating system clock Timer 0 overflow PCA Timer/Counter PCA Capture/Compare module ECI CEX4 CEX3 CEX2 CEX1 CEX0 Figure 26:Programmable Counter Array Block Diagram 2.18 I2C Controller The I2C controller of AX11015 supports Standard-mode (100K bps) and Fast-mode (400K bps), but not High-speed mode (3.4M bps) of the standard I2C bus spec. As shown in Figure 27, the I2C controller consists of an I2C master controller to support communication to external I2C devices, an I2C slave controller to support communication to external micro-controller with I2C master, and an I2C boot loader to support communication to external I2C EEPROM being used for storing chip configuration data. The output driving strength of I2C pins, SCL and SDA, is programmable (4mA or 8mA, by I2C_ODS bit in I2C Configuration EEPROM offset 0x04, see section 3.1.4 for details). The I2C master controller is compatible with I2C bus protocol. It provides eight registers to fully control and monitor I2C bus transaction, and it has separate receive and transmit registers to hold data for transactions between AX11015 and the external I2C devices. The I2C master controller also provides arbitration for multi-master operation scenario and reports the arbitration status. Also, the I2C master controller accepts the SCL being extended low by the slow I2C slave devices as additional wait state indication during data or acknowledge cycles. The I2C slave controller allows an external micro-controller with I2C master to communicate with AX11015. It provides an I2C device ID register to allow flexible assignment of AX11015 with any I2C device address for either 7-bit or 10-bit address mode, and can automatically filter I2C bus transactions not belonging to AX11015 in hardware. The I2C slave controller can extend the SCL line low when it needs additional wait state to respond to the external I2C master's bus transaction. The I2C slave controller supports 6 flexible command instructions for the external micro-controller to access the internal registers and memory resources of AX11015. For more details, please refer to section 4.18. 43 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY I2C Boot Loader Weak internal pull-up SCL Weak internal pull-up I2C Master Controller SDA I2C Slave Controller Figure 27: I2C Controller Block Diagram The I2C boot loader is used to load chip configuration data from external I2C EEPROM. It is activated after hardware reset (either power-on-reset or RST_N input) or via the software reload command (via I2CCTR register). The detailed memory map of I2C EEPROM is described in section 3.1. The use of external I2C EEPROM is optional, when not used, the I2C_BOOT_DIS pin should be pulled up during chip hardware reset, in that case, the reset value listed in I2C EEPROM memory map shall be used by this chip by default. 2.19 1-Wire Controller The 1-Wire controller of AX11015 is a master-mode controller that controls the communication with multiple external 1-Wire devices. The data transmissions on 1-Wire bus are bit-asynchronous and half-duplex mode only. The 1-Wire controller provides some registers for software to easily perform reading/writing data from/to the 1-Wire devices without having to deal with time-consuming bus timing and control sequences on 1-Wire bus. It supports Standard mode, Standard - Long line mode, and Overdrive mode to work with various 1-Wire devices. STPZ 1-Wire Master Controller DQ Figure 28: 1-Wire Controller Block Diagram The 1-Wire controller also supports Search ROM Accelerator, which relieves CPU from any single bit operations on the 1-Wire Bus. As shown in Figure 28 above, it also provides a strong pull-up control pin, STPZ, for the case of large loading or long line conditions. The DQ is an open-drain pin, which needs an external pulled-up resistor or a strong 44 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY pull-up through a PMOS transistor. The driving strength of DQ and STPZ is programmable (4mA or 8mA, by SPI_ODS bit in I2C Configuration EEPROM offset 0x04, see section 3.1.4 for details). 2.20 SPI Controller The serial peripheral interface (SPI) controller of AX11015 provides a full-duplex, synchronous serial communication interface (4 wires) to flexibly work with numerous peripheral devices or micro-controller with SPI. As shown in Figure 29, the SPI controller consists of a SPI master controller with 3 slave select pins, SS0, SS1, SS2, to connect up to 3 SPI devices, and a SPI slave controller to support communication with external micro-controller with SPI master. The driving strength of SCLK, MISO, MOSI, SS1, and SS2 is programmable (4mA or 8mA, by SPI_ODS bit in I2C Configuration EEPROM offset 0x04, see section 3.1.4 for details). The SPI master controller supports 4 types of interface timing mode, namely, Mode 0, Mode 1, Mode 2, and Mode 3 to allow working with most SPI devices available. Please refer to section 4.20 for detailed description of the 4 timing modes. It supports variable length of transfer word up to 32 bits per software command or even extended length of transfer word for a long burst transfer by keeping slave select pins active. It supports either MSB or LSB first data transfer, and the operating SPI clock, SCLK, is programmable by software and can be run up to 14 Mhz when operating system clock is at 100MHz. The SPI slave controller allows an external micro-controller with SPI master to communicate with AX11015. It supports 2 types of interface timing mode, namely, mode 0 and mode 3. In slave mode, only MSB first data transfer is supported and only the slave select pin, SS0, is used. The SPI slave controller supports 8 flexible command instructions for the external micro-controller to access the internal registers and memory resources of AX11015. It contains a 16-bytes FIFO to hold receive/transmit data on SPI interface and the SPI clock can be run up to 6 Mhz when operating system clock is at 100MHz. For more details, please refer to section 4.20. SS2 SS1 SS0 SPI Master Controller (with 4-bytes Receive FIFO and 4-bytes Transmit FIFO) SCLK MOSI MISO SPI Slave Controller (with 16-bytes FIFO) Figure 29: SPI Controller Block Diagram 45 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 2.21 Local Bus Interface and Digiport The Local Bus Interface (LBI) is AX11015 high-speed parallel interface used to communicate with external devices or CPU. It supports three modes of operation, namely, Local Bus master mode, Local Bus slave mode, and Digiport mode. Because they share some pins so only one mode can be activated at a time. Figure 30 shows the LBI block diagram and its I/O pins. The mode of operation is based on setting of LB_MOD pin, SYNC_BUS pin, SFR register LMSR, and I2C EEPROM offset 0x12 and 0x13. When operating in Local Bus master mode, the internal 1T 80390 CPU can accesses through the LBI to control or communicate with the external local bus devices up to 2 chip selects, LCS0_N and LCS1_N. When operating in Local Bus slave mode, the external system CPU can control the LBI to communicate with internal 1T 80390 CPU to access the internal registers and memory resources. When operating in Digiport mode (receive only) through LBI, the internal 1T 80390 CPU can receive Motion-JPEG streaming data from external STMicroelectronics STv0676 M-JPEG encoder chip or STv0684 M-JPEG encoder chip. In all three operation modes, the Local Bus contains a memory bridge with 32-bytes FIFO to allow performing burst read/write access through DMA mode to speed up bulk data transfer time. The single read/write access is handled directly by the 1T 80390 CPU in Local Bus master mode or by the external system CPU in the Local Bus slave mode. LBI Master Controller Memory Bridge DMA Engine LCS0_N LCS1_N LALE LWR_N LRD_N LINT LUDS_N LLDS_N LRDY LA [15:0] LDA [15:0] RD_DRQ RD_DAK WR_DRQ WR_DAK LBI Slave Controller LCS0_N LALE LWR_N LRD_N LINT LUDS_N LLDS_N LRDY LA [3:0] LDA [15:0] Digiport Controller LCS0_N LALE LRDY LDA [7:0] (with 32-bytes FIFO) Figure 30: Local Bus Interface and Digiport Block Diagram 46 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 2.21.1 Local Bus Master Mode The main features of Local Bus master mode are listed below, z Support 8-bit or 16-bit data bus width, and support little and big Endian bus swap z Support up to 64K bytes address space and 2 chip select outputs z Support asynchronous or synchronous Local Bus interface with required Local Bus clock output, LB_CLK z Allow internal 1T 80390 CPU to control off-chip low speed local bus devices which are Intel 80186/80386, ISA, Motorola 68000, and TI DSP's HPI (16 bits only) compatible bus style z Support single access as well as programmable burst read or write access up to 256 bytes in one software command. Under the control of internal 1T 80390 CPU, it can support burst read/write access for moving data in to/out of internal CPU's xDATA memory via DMA transfer z Support slave request based DMA access (LCS0_N only) for interfacing with external A/V Codec chip with burst data transfer z Support byte-access for single read/write access command in 16-bit bus width (not supported in burst access command) z Flexible bus style configuration loaded from I2C Configuration EEPROM in offset 0x12 and 0x13 For detailed description of Local Bus master mode, please refer to section 4.21.2. The reference pin connections of AX11015 interfacing with external local bus devices in Local Bus master mode are shown in Table 3, Figure 31, Figure 32, Figure 33, Figure 34 and Figure 35. AX11015 Pin Name LCS[1:0]_N LALE LA [15:4] LA [3] LA [2] LA [1] LA [0] LDA [15:0] LWR_N LRD_N LRDY LUDS_N LLDS_N LINT WR_DRQ WR_DAK RD_DRQ RD_DAK I/O ISA Style O O O O O O O I/O O O I O O I I O I O CS# AEN# SA [15:4] SA [3] SA [2] SA [1] SA [0] SD [15:0] IOW# IOR# IOCHRDY CS# ALE AD [15:0] WR# RD# ARDY CS# ADS# A [15:4] A [3] A [2] A [1] A [0] D [15:0] WR# RD# READY# INT N/A (high) INT WR_DREQ WR_DACK RD_DREQ RD_DACK INT WR_DREQ WR_DACK RD_DREQ RD_DACK N/A (high) Intel 80186 Style Intel 80386 Style Motorola 68000/68010 Style CS# AS# A [15:4] A [3] A [2] A [1] A [0] D [15:0] R/W# DTACK# UDS# LDS# IPL# WR_DREQ WR_DACK RD_DREQ RD_DACK Table 3: Reference Pin Connection Mapping in Local Bus Master Mode 47 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights TI HPI Style HCS# HAS# HCNTL [1] HCNTL [0] HHWIL HD [15:0] HR/W# HRDY# HDS1# HINT# N/A (high) N/A (high) AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY AX11015 Local Bus Master Mode CS# AEN# SA[15:0] SD[15:0] IOW# IOR# IOCHRDY LCS0_N/LCS1_N LALE LA[15:0] LDA[15:0] LWR_N LRD_N LRDY ISA Bus Style Devices INT LINT Figure 31: Interfacing with ISA Bus Style Devices in Local Bus Master Mode AX11015 Local Bus Master Mode CS# ALE AD[15:0] WR# RD# ARDY LCS0_N/LCS1_N LALE LDA[15:0] LWR_N LRD_N LRDY INT LINT Intel 80186 Local Bus Style Devices CDI_REQ (optional) CDI_ACK (optional) CDO_REQ (optional) CDO_ACK (optional) WR_DRQ WR_DAK RD_DRQ RD_DAK Figure 32: Interfacing with Intel 80186 Bus Style Devices in Local Bus Master Mode AX11015 Local Bus Master Mode CS# ADS# A[15:0] D[15:0] WR# RD# READY# LCS0_N/LCS1_N LALE LA[15:0] LDA[15:0] LWR_N LRD_N LRDY Intel 80386 Local Bus Style Devices INT LINT CDI_REQ (optional) CDI_ACK (optional) CDO_REQ (optional) CDO_ACK (optional) WR_DRQ WR_DAK RD_DRQ RD_DAK Figure 33: Interfacing with Intel 80386 Bus Style Devices in Local Bus Master Mode 48 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY AX11015 Local Bus Master Mode CS# AS# A[15:0] D[15:0] R/W# UDS# LDS# DTACK# LCS0_N/LCS1_N LALE LA[15:0] LDA[15:0] LWR_N LUDS_N LLDS_N LRDY IPL# LINT Motorola 68000/10 Local Bus Style Devices CDI_REQ (optional) CDI_ACK (optional) CDO_REQ (optional) CDO_ACK (optional) WR_DRQ WR_DAK RD_DRQ RD_DAK Figure 34: Interfacing with Motorola 68000/10 Bus Style Devices in Local Bus Master Mode AX11015 Local Bus Master Mode LCS0_N/LCS1_N LALE LA[3] LA[2] LA[1] LDA[15:0] LWR_N LUDS_N high LRDY HCS# HAS# HCNTL[1] HCNTL[0] HHWIL HD[15:0] HR/W# HDS1# HDS2# HRDY# TI DSP's HPI HINT# LINT Figure 35: Interfacing with the HPI of TI DSP Chips in Local Bus Master Mode 49 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 2.21.2 Local Bus Slave Mode The main features of Local Bus slave mode are listed below, z Support 8-bit or 16-bit data bus width (in 16-bit data bus width the AX11015 only supports word access and doesn't support byte access), and support little and big Endian bus swap z Require 4-bit address lines and 1 chip select z Support asynchronous or synchronous Local Bus interface with required Local Bus clock input, LB_CLK z Allow external system CPU with Intel 80186/80386, ISA, Motorola 68000/68030, and Renesas SuperH3/4 compatible bus style to communicate with internal 1T 80390 CPU, internal registers, and memory resources z Support single access as well as programmable burst read or write access up to 32 bytes in one software command. Under the control of external system CPU, it can support burst read/write access for moving data out of/in to internal CPU's xDATA memory via DMA transfer z Allow the external system CPU and internal 1T 80390 CPU to exchange data via two unidirectional data ports which allows them to exchange information concurrently z Flexible bus style configuration loaded from I2C Configuration EEPROM in offset 0x12 and 0x13 For detailed description of Local Bus slave mode, please refer to section 4.21.4. The reference pin connections of AX11015 interfacing with external system CPU with various bus styles in Local Bus slave mode are shown in Table 4, Figure 36, Figure 37, Figure 38, Figure 39, Figure 40, Figure 41, and Figure 42. AX11015 Pin Name LCS0_N LALE LA [3:0] LDA [15:0] LWR_N LRD_N LRDY LUDS_N LLDS_N LINT I/O I I I I I I O I I O ISA Style CS# AEN# SA [3:0] SD [15:0] IOW# IOR# IOCHRDY N/A (high) N/A (high) INT Intel Intel 80186 Style 80386 Style CS# ALE N/A (high) AD [15:0] WR# RD# ARDY N/A (high) N/A (high) INT CS# ADS# A [3:0] D [15:0] WR# RD# READY# N/A (high) N/A (high) INT Motorola 68000/10 Style CS# AS# A [3:0] D [15:0] R/W# N/A (high) DTACK# UDS# LDS# IPL# Motorola 68030/40 Style CS# AS# A [3:0] D [31:16] R/W# N/A (high) DSACK# DS# DS# IPL# Renesas SH3 Renesas SH4 CS# N/A (high) A [3:0] D [15:0] WE0# RD# WAIT# N/A (high) WE1# IREQ# CS# N/A (high) A [3:0] D [15:0] WE0# RD# RDY# N/A (high) WE1# IREQ# Table 4: Reference Pin Connection Mapping in Local Bus Slave Mode System CPU with ISA Bus Style LCS0_N LALE LA[3:0]* LDA[15:0] LWR_N LRD_N LRDY CS# AEN# SA[3:0] SD[15:0] IOW# IOR# IOCHRDY AX11015 Local Bus Slave Mode LINT INT *: LA[0] can be connected to low in 16-bit bus width Figure 36: Interfacing with System CPU with ISA Bus Style in Local Bus Slave Mode 50 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY System CPU with Intel 80186 Local Bus Style CS# ALE AD[15:0] WR# RD# ARDY LCS0_N LALE LDA[15:0] LWR_N LRD_N LRDY INT AX11015 Local Bus Slave Mode LINT Figure 37: Interfacing with System CPU with Intel 80186 Local Bus Style in Local Bus Slave Mode System CPU with Intel 80386 Local Bus Style LCS0_N LALE LA[3:0]* LDA[15:0] LWR_N LRD_N LRDY CS# ADS# A[3:0] D[15:0] WR# RD# READY# AX11015 Local Bus Slave Mode LINT INT *: LA[0] can be connected to low in 16-bit bus width. Figure 38: Interfacing with System CPU with Intel 80386 Local Bus Style in Local Bus Slave Mode System CPU with Motorola 68000/10 Local Bus Style CS# AS# A[3:0] D[15:0] R/W# UDS# LDS# DTACK# LCS0_N LALE LA[3:0]* LDA[15:0] LWR_N LUDS_N** LLDS_N LRDY IPL# AX11015 Local Bus Slave Mode LINT *: LA[0] can be connected to low in 16-bit bus width. **: Connect LUDS_N to high in 8-bit bus width. Figure 39: Interfacing with System CPU with Motorola 68000/10 Local Bus Style in Local Bus Slave Mode 51 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY System CPU with Motorola 68030/40 Local Bus Style CS# AS# A[3:0] D[31:16] R/W# DS# LCS0_N LALE LA[3:0]* LDA[15:0]** LWR_N LUDS_N*** LLDS_N LRDY DSACK# IPL# AX11015 Local Bus Slave Mode LINT *: LA[0] can be connected to low in 16-bit bus width. **: Connect D[31:24] to LDA[7:0] in 8-bit bus width. ***: Connect LUDS_N to high in 8-bit bus width. Figure 40: Interfacing with System CPU with Motorola 68030/40 Local Bus Style in Local Bus Slave Mode System CPU with Renesas SH3 Local Bus Style LCS0_N LA[3:0]* LDA[15:0]** LWR_N LLDS_N*** LRD_N LRDY CSx# A[3:0] D[15:0] WE0# WE1# RD# WAIT# AX11015 Local Bus Slave Mode LINT IREQ# *: LA[0] can be connected to low in 16-bit bus width. **: Connect D[7:0] to LDA[7:0] in 8-bit bus width. ***: Connect LLDS_N to high in 8-bit bus width. Figure 41: Interfacing with System CPU with Renesas SH3 Local Bus Style in Local Bus Slave Mode System CPU with Renesas SH4 Local Bus Style LCS0_N LA[3:0]* LDA[15:0]** LWR_N LLDS_N*** LRD_N LRDY CSx# A[3:0] D[15:0] WE0# WE1# RD# RDY# AX11015 Local Bus Slave Mode LINT IREQ# *: LA[0] can be connected to low in 16-bit bus width. **: Connect D[7:0] to LDA[7:0] in 8-bit bus width. ***: Connect LLDS_N to high in 8-bit bus width. Figure 42: Interfacing with System CPU with Renesas SH4 Local Bus Style in Local Bus Slave Mode 52 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 2.21.3 Digiport Mode The Digiport mode of LBI is specially designed to be able to receive compressed streaming video data from STMicroelectronics STv0676 (in Digiport parallel mode) or STv0684 (in Digiport SPI mode) chips directly into internal xDATA memory of 1T 80390 CPU via DMA transfer. When used, the LBI is basically acting as master mode. The main features of Digiport mode are listed below, z When working with STM STv0676 in Digiport parallel mode, after software initiates the DMA command, it can output clock on LALE pin and receive 8-bit streaming data via LDA [7:0] pins and the ready indication from LRDY pin. z When working with STM STv0684 in Digiport SPI mode, after software initiates the DMA command, it can output ready indication on LRDY pin and then start receiving 1-bit streaming data via LDA0. The clock is fed to LALE pin at 24Mhz. The format of Digiport SPI is similar to the SPI Mode 3 (CPHA=1, CPOL=1) z Support automatic SOI (Start of Image, 0xFFD8) and EOI (End of Image, 0xFFD9) bytes detection in receive Motion-JPEG streaming data for both Digiport parallel mode and Digiport SPI mode z Support transparent mode for receiving audio and video mixed streaming in Digiport SPI mode z Support programmable packet size for packetizing the receive Motion JPEG streaming data z Support up to 256-bytes burst read access in each DMA command For detailed description of Digiport mode, please refer to section 4.21.7. The reference pin connections of AX11015 interfacing with STv0676 and STv0684 in Digiport mode are shown in Table 5, Figure 43, and Figure 44. AX11015 Pin Name I/O LCS0_N LALE LDA [7:1] LDA [0] LRDY O O I I I STv0676 Digiport Parallel Bus N/A DP [8] DP [7:1] DP [0] DP[9] I/O I I I I O STv0684 Digiport SPI Bus SFP130 SFP3 N/A (high) SFP2 SFP50 Table 5: Reference Pin Connection Mapping in Digiport Mode DP[8] DP[9] STMicroelectronics STv0676 DP[7:0] FIFO Clk Data Valid Data Output SCL SDA AX11015 LALE LDA[7:0] Digiport Parallel Mode SCL SDA I2C Master Controller LRDY Figure 43: Interfacing with STv0676 in Digiport Parallel Mode 53 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY AX11015 SFP130 SFP3 SFP2 SFP50 SFP51 VD_CS# SCLK MOSI VD_RDY AD_CS# STMicroelectronics STv0684 LCS0_N LALE LDA[0] LRDY SS0 SCLK SFP1 SFP49 MISO AD_RDY Digiport SPI Mode (Video) MOSI MISO SPI Slave Controller (Audio) P37 SFP29 SCL SFP28 SDA I2C Master Controller (Control) Figure 44: Interfacing with STv0684 in Digiport SPI Mode 54 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 3.0 Memory Map Description 3.1 I2C Configuration EEPROM Memory Map The I2C Configuration EEPROM uses a serial EEPROM with I2C interface with at least 128x8 (1K bits), for example, Atmel AT24C01. The 7-bit device address of the I2C Configuration EEPROM should be 1010000b for AX11015. The I2C Configuration EEPROM is used to store some hardware and software default setting for the chip. These setting will be loaded into the chip by the I2C master controller right after the deactivation of chip reset or through software issuing reload command in I2C controller. Table 6 below shows the memory map of I2C Configuration EEPROM. Note that if I2C EEPROM is not used, then I2C_BOOT_DIS pin should be pulled up during chip reset, and the reset value of each offset address listed in this section shall be used by the AX11015 by default. EEPROM Offset Descriptor 0x00 Length 0x01 Flag 0x03~0x02 Multi-function Pin Setting 1 Multi-function Pin Setting 0 0x04 Programmable Output Driving Strength 0x05 Reserved = 0x00 0x0B~0x06 Node ID 5 Node ID 4 Node ID 3 Node ID 2 Node ID 1 Node ID 0 (0x06) 0x0D~0x0C Maximum Packet Size 1 Maximum Packet Size 0 (0x0C) 0x0F~0x0E Secondary PHY Type and PHY ID Primary PHY Type and PHY ID (0x0E) 0x11~0x10 Pause Frame Low Water Mark Pause Frame High Water Mark (0x10) 0x13~0x12 Local Bus Setting 1 Local Bus Setting 0 (0x12) 0x15~0x14 TOE TX VLAN Tag 1 TOE TX VLAN Tag 0 (0x14) 0x17~0x16 TOE RX VLAN Tag 1 TOE RX VLAN Tag 0 (0x16) 0x18 0x1C~0x19 0x20~0x1D TOE ARP Cache Timeout TOE Source IP Address TOE Source IP Address TOE Source IP Address TOE Source IP Address 1 3 2 0 (0x19) TOE Subnet Mask 0 TOE Subnet Mask 3 TOE Subnet Mask 2 TOE Subnet Mask 1 (0x1D) 0x21 TOE L4 DMA Transfer Gap 0x2F~0x22 Reserved for HW future use 0x7F~0x30 Reserved for Software and Driver Settings Table 6: I2C Configuration EEPROM Memory Map 55 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 3.1.1 Length (0x00) This field determines the number of bytes (not including the length byte itself) to be loaded by the I2C master controller from I2C Configuration EEPROM after chip reset. Please set to 0x21. Note that setting any value larger than 0x2F will be changed to 0x2F by I2C master controller, i.e., it will only load the content between 0x00~0x2F for the HW use in that case. 3.1.2 Flag (0x01) 7 Bit Name DBG_PSEL Reset Value 1 6 5 ASCS 111 4 3 ACB 1 2 RCB 1 1 TOFFOP 0 0 F10HD 0 Bit Name 0 F10HD Description Force embedded Ethernet PHY to operate at 10M Half-Duplex mode. 1: Force the embedded Ethernet PHY to operate in 10Mbps half-duplex mode. 0: The embedded Ethernet PHY will base on auto negotiation to determine mode of operation. 1 TOFFOP Turn OFF 25Mhz Oscillator and PLL circuit during STOP mode 1: To turn off the 25Mhz oscillator and PLL circuit to reduce power consumption during Stop mode. 0: To keep 25Mhz Oscillator and PLL circuit free run during Stop mode. 2 RCB Remove CRC Bytes of RX Ethernet packet. 1: Ethernet MAC removes the CRC bytes of received Ethernet packet before forwarding to CPU. 0: The CRC bytes are not removed. 3 ACB Append CRC Bytes of TX Ethernet packet. 1: The CRC byte of transmitted Ethernet packet are generated and appended by the Ethernet MAC. 0: The CRC bytes are not appended. 6:4 ASCS Addressable Space of external SRAM Chip Select pin, "XRAMCE0_N". Value Addressable Space 000 0~64 Kbytes 001 0~128 Kbytes 010 0~256 Kbytes 011 0~512 Kbytes 100 0~1024 Kbytes 101~110 Reserved 111 0~16384 Kbytes 7 DBG_PS CPU Debugger Pin Select. This selects the desired function (CPU debugger pins or Ethernet LED EL pins) of below multi-function pins, which users want to enable. Pin # 30 31 32 DBG_PSEL = 0 DB_DI DB_CKO DB_DO DBG_PSEL = 1 LNK_LED SPD_LED FD_CL_LED 56 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 3.1.3 Multi-function Pin Setting (0x02~0x03) Multi-function Pin Setting 0 (0x02) Bit Name Reset Value Bit Name 1:0 P0_PSEL 3:2 P1_PSEL 5:4 P2_PSEL 7:6 P3_PSEL 7 6 P3_PSEL 00 5 4 P2_PSEL 00 3 2 P1_PSEL 00 1 0 P0_PSEL 00 Description GPIO Port 0 Pin Select. This selects the desired function (port 0, local bus address, or UART2) of below multi-function pins, which users want to enable. Pin # P0_PSEL = 00/01 P0_PSEL = 10 P0_PSEL = 11 18 P00 LA8 RXD2 20 P01 LA9 TXD2 22 P02 LA10 CTS 23 P03 LA11 DSR 25 P04 LA12 RI 28 P05 LA13 DCD 34 P06 LA14 RTS 35 P07 LA15 DTR GPIO Port 1 Pin Select. This selects the desired function (port 1, local bus address, or MII) of below multi-function pins, which users want to enable. Pin # P1_PSEL = 00/01 P1_PSEL = 10 P1_PSEL = 11 77 P10 LA0 MDC 79 P11 LA1 MDIO 81 P12 LA2 DE 85 P13 LA3 RE_N 87 P14 LA4 P14 91 P15 LA5 P15 94 P16 LA6 P16 95 P17 LA7 P17 GPIO Port 2 Pin Select. This selects the desired function (port 2, local bus data, or MII) of below multi-function pins, which users want to enable. Pin # P2_PSEL = 00/01 P2_PSEL = 10 P2_PSEL = 11 5 P20 LDA0 RX_CLK 9 P21 LDA1 MRXD0 12 P22 LDA2 MRXD1 14 P23 LDA3 MRXD2 17 P24 LDA4 MRXD3 19 P25 LDA5 RX_DV 21 P26 LDA6 CRS 27 P27 LDA7 RX_ER GPIO Port 3 Pin Select. This selects the desired function (port 3, local bus data, or MII) of below multi-function pins, which users want to enable. Pin # 78 80 82 86 88 89 92 93 P3_PSEL = 00/01 P30 P31 P32 P33 P34 P35 P36 P37 P3_PSEL = 10 LDA8 LDA9 LDA10 LDA11 LDA12 LDA13 LDA14 LDA15 P3_PSEL = 11 TX_CLK MTXD0 MTXD1 MTXD2 MTXD3 TX_EN TX_ER COL 57 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Multi-function Pin Setting 1 (0x03) Bit Name Reset Value 7 6 SPI_PSEL 00 5 4 TM_PSEL 00 3 2 UIT_PSEL 00 1 0 MI_PSEL 00 Bit Name Description 1:0 MI_PSEL Memory Interface Pin Select. This selects the desired function (either external memory interface or local bus DMA signals) of below multi-function pins, which users want to enable. Pin # MI_PSEL = 00/01/11 MI_PSEL = 10 40 XROMCE1_N RD_DRQ 44 XRAMCE1_N RD_DAK 58 XADDR19 WR_DRQ 59 XADDR20 WR_DAK 3:2 UIT_PSEL UART1, INT1, Timer0 Pin Select. This selects the desired function (UART1/ INT1/Timer0, local bus control signals, or PCA signals) of below multi-function pins, which users want to enable. Pin # UIT_PSEL = 00/01 UIT_PSEL = 10 UIT_PSEL = 11 107 RXD1 LCS0_N ECI 110 TXD1 LCS1_N CEX0 116 INT1 LINT INT1 8 TM0_CK LALE TM0_CK 10 TM0_GT LWR_N TM0_GT 5:4 TM_PSEL Timer1, Timer2 Pin Select. This selects the desired function (Timer1/2, local bus control signals, or PCA signals) of below multi-function pins, which users want to enable. Pin # TM_PSEL = 00/01 TM_PSEL = 10 TM_PSEL = 11 11 TM1_CK LRD_N CEX1 13 TM1_GT LRDY CEX2 15 TM2_CK LUDS_N CEX3 16 TM2_GT LLDS_N CEX4 7:6 SPI_PSEL SPI Pin Select. This selects the desired function (SPI or 1-Wire) of below multi-function pins, which users want to enable. Pin # 4 6 SPI_PSEL = 00/01 SPI_PSEL = 10 SS1 DQ SS2 STPZ SPI_PSEL = 11 Reserved Reserved 58 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 3.1.4 Programmable Output Driving Strength (0x04) Bit Name Reset Value 7 PCA_ODS 0 6 5 SPI_ODS I2C_ODS 0 1 4 3 MI_ODS P3_ODS 1 0 2 P2_ODS 0 1 P1_ODS 0 Bit Name 0 P0_ODS 0 P0_ODS 0 Description GPIO Port 0 Output Driving Strength setting. Note that this setting is independent of P0_PSEL in offset 0x02. 1: Set driving strength to 8mA on P0 [7:0] pins (pin # 18, 20, 22, 23, 25, 28, 34, 35). 0: Set driving strength to 4mA on P0 [7:0] pins. 1 P1_ODS GPIO Port 1 Output Driving Strength setting. Note that this setting is independent of P1_PSEL in offset 0x02. 1: Set driving strength to 8mA on P1 [7:0] pins (pin # 77, 79, 81, 85, 87, 91, 94, 95). 0: Set driving strength to 4mA on P1 [7:0] pins. 2 P2_ODS GPIO Port 2 Output Driving Strength setting. Note that this setting is independent of P2_PSEL in offset 0x02. 1: Set driving strength to 8mA on P2 [7:0] pins (pin # 5, 9, 12, 14, 17, 19, 21, 27). 0: Set driving strength to 4mA on P2 [7:0] pins. 3 P3_ODS GPIO Port 3 Output Driving Strength setting. Note that this setting is independent of P3_PSEL in offset 0x02. 1: Set driving strength to 8mA on P3 [7:0] pins (pin # 78, 80, 82, 86, 88, 89, 92, 93). 0: Set driving strength to 4mA on P3 [7:0] pins. 4 MI_ODS Memory Interface Output Driving Strength setting. Note that this setting is independent of MI_PSEL in offset 0x03. 1: Set driving strength to 8mA on XDATA [7:0], XADDR [20:0], XPRGRD_N, XPRGWR_N, XDATRD_N, and XDATWR_N pins. 0: Set driving strength to 4mA on XDATA [7:0], XADDR [20:0], XPRGRD_N, XPRGWR_N, XDATRD_N, and XDATWR_N pins. 5 I2C_ODS I2C Output Driving Strength setting. 1: Set driving strength to 8mA on SCL, SDA pins (pin # 113, 114). 0: Set driving strength to 4mA on SCL, SDA pins. 6 SPI_ODS SPI Output Driving Strength setting. Note that this setting is independent of SPI_PSEL in offset 0x03. 1: Set driving strength to 8mA on SCLK, MISO, MOSI, SS1, and SS2 pins (pin # 1, 3, 2, 4, 6). 0: Set driving strength to 4mA on SCLK, MISO, MOSI, SS1, and SS2 pins. 7 PCA_ODS PCA Output Driving Strength setting. Note that this setting is independent of UIT_PSEL and TM_PSEL in offset 0x03. 1: Set driving strength to 8mA on CEX [4:0], LINT, LALE, and LWR_N pins (pin # 16, 15, 13, 11, 110, 116, 8, 10). 0: Set driving strength to 4mA on CEX [4:0], LINT, LALE, and LWR_N pins. 59 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 3.1.5 Node ID (0x06~0x0B) The Node ID 5 to Node ID 0 set the default MAC address of this chip. For example, if the MAC address is 01-23-45-67-89-AB, then put Node ID {5, 4, 3, 2, 1, 0} = {0x01, 0x23, 0x45, 0x67, 0x89, 0xAB}. The reset value of Node ID in this ASIC = 0x0000_0000_0000. 3.1.6 Maximum Packet Size (0x0C~0x0D) The Maximum Packet Size 1 and Maximum Packet Size 0 set the maximum Ethernet packet size that can be received from network. If the received Ethernet packet exceeds this number, Ethernet MAC shall truncate it. Note that the Maximum Packet Size field must be even number in bytes and less than or equal to 2500 bytes. For example, if maximum packet size is 1522 bytes, then put Maximum Packet Size {1,0} = {0x05, 0xF2}. The reset value of Maximum Packet Size 1 and 0 in this ASIC = 0x05F2. 3.1.7 Primary/Secondary PHY Type and PHY ID (0x0E~0x0F) Bit Name Reset Value 7 6 PHY Type 000 (primary) 111 (secondary) 5 4 3 2 1 PHY ID 1_0000 (primary) 0_0000 (secondary) 0 Bit Name 4:0 PHY ID Description The PHY ID of PHY. Primary PHY ID: Set to 1_0000 for the embedded Ethernet PHY. Secondary PHY ID: Set to other value than 1_0000 or set to 0_0000 if not used. 7:5 PHY Type PHY Type is defined as follows, 000: IEEE 802.3 10BASE-T/100BAS-TX Ethernet PHY. 001: HomePlug PHY. 100: Special case where the link status of PHY is always reported as link-up. 111: Non-supported PHY. For example, setting "0xE0" in Secondary PHY Type and PHY ID field means that the secondary PHY is not supported. 3.1.8 Pause Frame Low Water and High Water Mark (0x10~0x11) When operating in full-duplex mode, correct setting of this field is very important and can affect the overall packet receive throughput performance in a great deal. The Low Water Mark is the threshold to trigger sending of Pause frame and the High Water Mark is threshold to stop sending of Pause frame. Note that each free buffer count here represents 256 bytes of packet storage space in RX packet buffer SRAM in Ethernet MAC. For now, set Pause Frame Low Water to 0x19 and Pause Frame High Water Mark to 0x1d. Total free buffer count = 32 Stop sending Pause frame when free buffer > High Water Mark (reset value in this ASIC = 0x1d) Start sending Pause frame when free buffer < Low Water Mark (reset value in this ASIC = 0x19) 0 60 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 3.1.9 Local Bus Setting (0x12~0x13) Local Bus Setting 0 (0x12) Bit Name Reset Value 7 LB_W 1 6 BUS_TYPE 0 5 4 ADDR_LATCH 00 3 ENDIAN 0 2 RDY_POL 1 1 INT_POL 1 0 INT_LVL 1 Bit Name 0 INT_LVL 1 2 3 5:4 6 7 Description The trigger type of interrupt signal, "LINT". 1: Edge trigger. 0: Level trigger. INT_POL The active polarity of interrupt signal, "LINT". 1: Active high (if INT_LVL = 0) or Rising Edge (if INT_LVL = 1). 0: Active low (if INT_LVL = 0) or Falling Edge (if INT_LVL = 1) RDY_POL The active polarity of "LRDY" signal. 1: Active high. 0: Active low. ENDIAN The bus Endian type selection when operating in 16-bit bus width (not applicable in 8-bit bus width). 1: Little Endian. The LDA[15:8] and LDA[7:0] will be byte-swapped inside LBI before mapping to LBI's register. 0: Big Endian. The LDA[15:8] and LDA[7:0] will be mapped directly into LBI's register without byte-swap. ADDR_LAT The style of address latch enable for sampling local bus address, LA [15:0] or LDA [15:0]. CH Value Master Mode Slave Mode 00 Active low Active low 01 Active high Address not latched (Address is pass-through). If external CPU has no AS or ALE signal, use pass-through address. 10 Low pulse Low pulse 11 High pulse High pulse BUS_TYPE The bus style of local bus address and data bus. 1: Multiplexed address and data bus. 0: Separated address and data bus. LB_W The data bus width of local bus. 1: 16 bits. 0: 8 bits. Local Bus Setting 1 (0x13) 7 6 5 4 3 2 1 0 Bit AS_LAG CTRL_STYL BYTE_WR BA_ABT DGS_TR DG_SPI DAK_POL DRQ_POL Name 0 0 0 0 0 0 0 0 Reset Value Bit Name Description 0 DRQ_POL The active polarity of local bus DMA Request signals, "WR_DRQ" and "RD_DRQ". 1: Active High. 0: Active Low. 1 DAK_POL The active polarity of local bus DMA Grant signals, "WR_DAK" and "RD_DAK". 1: Active High. 0: Active Low. 2 DG_SPI Digiport in SPI serial format. 1: Enable Digiport in SPI serial format. 0: Enable Digiport in parallel format (8 bits). 3 DGS_TR Digiport SPI mode transparent 1: Digiport SPI transparent mode. 61 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 0: Digiport SPI parser mode (JPEG). 4 BA_ABT The Bus Access Abort enable in local bus slave mode 1: In local bus slave mode, enable the chip to keep the LRDY signal de-asserted when the requested bus read or write access cannot be completed. This is normally used in the CPUs supporting bus access timeout or abort function. 0: The chip will delay the assertion of LRDY signal until the requested bus read or write access can be completed by the chip. This is normally used in CPUs not supporting bus access timeout or abort function. 5 BYTE_W Byte Write enable (not applicable in 8-bit bus width). Some CPU, like Super-H, has more than one R write enable signals for allowing byte write access. 1: Use 2 write enable pins, one for each byte. Note that since only word-access is supported by this chip in 16-bit data width mode, therefore, a successful write command shall have both write enable pins active at the time. 0: Use 1 write enable pin. 6 CTRL_ST The read and write Control signal style. YL 1: Merged write enable and read enable signal. 0: Separated write enable and read enable signals. 7 AS_LAG Address Select signal, LALE, is LAGging behind the read and write enable signals (only for Intel 386 bus). 1: The address select signal is lagging behind the read and write enable signals. 0: The address select signal is not lagging behind the read and write enable signals. The Table 7 below shows the example settings for local bus interface in master mode. Type Bit Name LB_W BUS_TYPE ADDR_LATCH ENDIAN RDY_POL INT_POL INT_LVL Local Bus Setting 0 AS_LAG CTRL_STYL BYTE_WR DAKQ_POL DRQ_POL Local Bus Setting 1 ISA 186 386 68000 TI HPI 0/1 0 00 0 1 1 0/1 0x06 / 0x07 / 0x86 / 0x87 0 0 0 0 0 0x00 0/1 1 11 0 1 1 0 0x76 / 0xF6 0/1 0 10 0 0 1 0 0x22 / 0xA2 0/1 0 00 1 0 0 0 0x08 / 0x88 1 0 10 1/0 0 0 0 0xA0 / 0xA8 0 0 0 0/1 0/1 0x00/01/02/03 1 0 0 0/1 0/1 0x80/81/82/83 0 1 0 0/1 0/1 0x40/41/42/43 0 1 0 0 0 0x40 Table 7: Local Bus Master Mode Setting Table 8 below shows the example settings for local bus interface in salve mode. Type ISA 186 Bit Name LB_W 0/1 0/1 BUS_TYPE 0 1 ADDR_LATCH 00 11 ENDIAN 0 0 RDY_POL 1 1 INT_POL 1 1 INT_LVL 0/1 0 Local Bus 0x06 / 0x07 / 0x76 / 0xF6 Setting 0 0x86 / 0x87 AS_LAG 0 0 386 0/1 0 10 0 0 1 0 0x22 / 0xA2 1 68000/ 68030/ SH3 SH4 68010 68040 0/1 0/1 0/1 0/1 0 0 0 0 00 00 01 01 1 1 0 0 0 0 1 0 0 0 1 1 0 0 0/1 0/1 0x08 / 0x88 0x08 / 0x88 0x16 / 0x17 / 0x12 / 0x13 / 0x96 / 0x97 0x92 / 0x93 0 0 0 0 62 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY CTRL_STYL BYTE_WR Local Bus Setting 1 0 0 0x00 0 0 0x00 0 0 0x80 1 0 0x40 1 0 0x40 0 1 0x20 0 1 0x20 Table 8: Local Bus Slave Mode Setting 3.1.10 TOE TX VLAN Tag (0x14~0x15) This field sets the default value of TOE TX VLAN Tag Register. The reset value in this ASIC = 0x0000. 3.1.11 TOE RX VLAN Tag (0x16~0x17) This field sets the default value of TOE RX VLAN Tag Register. The reset value in this ASIC = 0x0000. 3.1.12 TOE ARP Cache Timeout (0x18) This field sets the default value of TOE ARP Cache Timeout Register. The reset value in this ASIC = 0x00. 3.1.13 TOE Source IP Address (0x19~0x1C) This field sets the default value of TOE Source IP Address Register. The reset value in this ASIC = 0x0000_0000. 3.1.14 TOE Subnet Mask (0x1D~0x20) This field sets the default value of TOE Subnet Mask Register. The reset value in this ASIC = 0x0000_0000. 3.1.15 TOE L4 DMA Transfer Gap (0x21) This field sets the default value of TOE L4 DMA Transfer Gap Register. The reset value in this ASIC = 0x00. 63 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 3.2 Program Memory Map The 1T 80390 CPU core has separated address spaces for program and data memory. The Program Memory, Internal Data Memory, External Data Memory, SFRs areas each has its own address spaces. As shown in below two figures, the CPU core can address up to 2 MB of linear program space without bank select. The CPU core starts execution of program code at location 0x000000 in LARGE mode, after each reset. The CPU core can be then switched to FLAT mode to support 2 M bytes of linear program code space. The case I shows the program code shadow mode is not enabled while the case II shows the program code shadow mode is enabled. Case I: EXT_PROG_SRAM_EN is pulled low during chip hardware reset, the Program non-Shadow mode CPU Program Memory Address 0x1FFFFF External Flash Memory 0x080000 0x07FFFF On-chip 512K Flash Memory 0x004000 0x003FFF On-chip 16KB SRAM 0x000000 The program code residing on external Flash memory will be fetched with wait states defined in SFR register, WTST [2:0]. The program code residing on on-chip Flash memory space (0x004000~0x07FFFF) will be fetched with wait states defined in SFR register, WTST [2:0]. The program code residing on the on-chip 16K bytes SRAM is copied from the on-chip Flash memory space (0x000000~0x003FFF) by the Boot Loader hardware before CPU starts running, so-called "program code mirroring". When CPU executing the program code in this range, it will always fetch from the on-chip SRAM and run at zero wait state (1T). This part of the code is used for BOOT code with system initialization Figure 45: The Program Memory Map of 1T 80390 CPU Core (Program non-Shadow mode) Case II: EXT_PROG_SRAM_EN is pulled high during chip hardware reset, the Program Shadow mode. CPU Program Memory Address 0x1FFFFF External SRAM Memory 0x004000 0x003FFF The program code residing on on-chip Flash memory space (0x0004000~0x07FFFF) and external Flash memory space (0x080000~0x1FFFFF) will be copied to the external SRAM memory by the Boot Loader hardware before CPU starts running, the so-called "program code shadow". When CPU executing the program code in this range, it will fetch from the external SRAM memory with wait states defined in SFR register, WTST [2:0]. The program code residing on the on-chip 16K bytes SRAM is copied from the on-chip Flash memory space (0x000000~0x003FFF) by the Boot Loader hardware before CPU starts running, the so-called "program code mirroring". When CPU executing the program code in this range, it will 0x000000 always fetch from the on-chip SRAM and run at zero wait state (1T). This part of the code is used for BOOT code with system initialization f Map i of 1T 80390 CPU Core (Program Shadow mode) Figure 46: The Program Memory On-chip 16KB SRAM 64 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 3.3 External Data (xDATA) Memory Map The data memory of 1T 80390 CPU core is divided onto 2 M bytes of External Data Memory (on-chip SRAM used 0~32K bytes memory space, off-chip SRAM used 32K~2M bytes memory space) and 256 bytes of Internal Data Memory, plus a 128-bytes of SFR memory area. As shown in below figure, the CPU core can address up to 2M bytes of External Data (xDATA) memory space without bank select. The xDATA memory is accessed by MOVX instructions only. CPU External Data Memory Address 0x1FFFFF 0x008000 0x007FFF 0x000000 External SRAM Memory When CPU accessing xDATA memory space (0x0008000~0x1FFFFF), it will access with wait states defined in SFR register, CKCON [2:0]. On-chip 32KB SRAM The on-chip 32K bytes SRAM occupies the External Data Memory address space (0x000000~0x007FFF). When CPU accessing this range, it will access with wait states defined in SFR register, CKCON [2:0]. Figure 47: The External Data Memory Map of 1T 80390 CPU Core 3.4 Internal Data Memory and SFR Register Map The Figure 48 below shows the Internal Data Memory (256 bytes) and Special Function Register (SFR) map of 1T 80390 CPU core. The lower internal memory consists of four register banks with eight registers each; a bit addressable segment with 128 bits (16 bytes) begins at 0x20, and a scratch pad area with 208 bytes. With the indirect addressing mode, range 0x80 to 0xFF of the highest 128 bytes of the internal memory is addressed. With the direct addressing mode, range 0x80 to 0xFF, the SFR memory area is accessed. Figure 48: The Internal Memory Map of 1T 80390 CPU Core 65 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY The Table 9 below shows the SFR Register Map, note that all registers in the column with Offset+0 are bit addressable. SFR Offset Offset+0 0xF8 EIP 0xF0 B 0xE8 Offset+1 Offset+2 Offset+3 EIE STATUS MXAX TA 0xE0 ACC HS_RTD HS_ID HS_IF 0xD8 WDCON 0xD0 PSW 0xC8 T2CON 0xC0 SCON1 SBUF1 0xB8 IP 0xB0 CCAPM0 Offset+4 HS_LCR Offset+5 Offset+6 Offset+7 HS_MCR HS_LSR HS_MSR Reserved Reserved CCAPM1 CCAPM2 CCAPM3 CCAPM4 OWCIR OWDR RLDL CMOD RLDH CCON TL2 CL TH2 CH SPICIR SPIDR CCAP0H CCAP1H CCAP2H CCAP3H CCAP4H EPCR EPDR P3 CCAP0L CCAP1L CCAP2L CCAP3L CCAP4L MCIR MDR 0xA8 IE 0xA0 P2 LDLR LMSR (M) LSAIER (S) LDHR LCR (M) LSCR (S) DMALR LSR (M) LSSR (S) 0x98 SCON0 SBUF0 DBAR DCIR DDR ACON PISS1R PISS2R 0x90 P1 EIF WTST DPX0 SDSTSR DPX1 I2CCIR I2CDR 0x88 TCON TMOD TL0 TL1 TH0 TH1 CKCON CSREPR 0x80 P0 SP DPL0 DPH0 DPL1 DPH1 DPS PCON DMAMR DMAHR TCIR TDR LDALR (M) LDAHR (M) LDCSR (M) XMWLR (S) XMWHR (S) XMRLR (S) XMRHR (S) Bolded - are 1T-80390 CPU core related registers. Italic - are peripheral functions, such as UART2, SPI, 1-Wire, PCA, Ethernet PHY, Ethernet MAC, TOE, Local Bus Interface, I2C, and software DMA related. Empty - are read-only. Table 9: The SFR Register Map 66 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 4.0 Detailed Function Description 4.1 Clock Generation The figure below shows the clock generation block of AX11015. The embedded PLL block generates the "osclk" (100Mhz) as the main clock source for system logic and 125Mhz for Ethernet PHY use. The internal "phy_pwrdn" signal is used to disable the oscillator, PLL, and Ethernet PHY for maximum power saving. After power-on reset, the "phy_pwrdn" signal is default to `0' to allow clock to oscillate initially. When entering the STOP mode by setting STOP bit (PCON.1), while the TOFFOP bit (Flag.1) in I2C EEPROM is 1, the "phy_pwrdn" signal is asserted to `1' to completely turn off oscillator, PLL, and Ethernet PHY. During this deep power-down mode, to re-enable the oscillator/PLL/system clock, detecting a rising edge on EXT_WKUP pin or detecting a falling-edge transition (start bit) on RXD2 pin or falling-edge transition on RI pin of UART 2 will trigger the "phy_pwrdn" signal to change to "0" and then re-enable the oscillator/PLL back to free run mode. During this process, the internal "system_clk" will be gated until oscillator/PLL clock are stabled enough before it is fed to the system logic. When internal PLL's "osclk" is selected as clock source, the SYSCK_SEL[1:0] decides the operating system clock frequency, where "00" = 25Mhz, "01" = 50Mhz, "11" = 100Mhz. The LB_CLK input pin can be another clock source for the local bus operating in slave and synchronous mode or for the purpose of more accurate baud rate generation for UART0/1/2. In that case, input clock frequency of LB_CLK should be as close to 25/50/100Mhz as possible so that the internal timing function such as PCA and the dedicated Millisecond Timer can still function closely. For example, the possible LB_CLK can be 48Mhz, in that case, the SYSCK_SEL[1:0] should be set to "01" too. phy_pwrdn XTL25P 25Mhz Crystal 125Mhz 100/125Mhz PLL 25Mhz OSC Ethernet PHY XTL25N rx_clk and tx_clk (2.5/25Mhz) to Ethernet MAC osclk (100Mhz) {STOP, PMM}bits /2 Clock off /4 SYSCK_SEL [1:0] LB CLK (LB_MOD & SYNC_BUS) / 100 system_clk (25/50/100Mhz or 2.5/5/10Mhz in PMM) for most system logic except for Ethernet MAC/PHY / 2/4/8 phyrw_clk (12.5Mhz) for Ethernet PHY register access Note: In above figure, lower case signal names represent chip internal signals. Figure 49: AX11015 Clock Generation Block Diagram 67 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights LB_CLK AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 4.2 Reset Generation The Figure 50 below shows the reset generation block of AX11015. The output of power-on-reset generates a reset pulse to reset on-chip Flash memory during power-on. The internal "system_rst_n" signal is used to reset most system logic and its source can come from RST_N pin, power on reset condition, or software reset and reboot command via SFR register CSREPR. The SYS_RSTO_N is an optional reset output pin to be used by peripheral chips. Note: in below figure, the lower case signal names represent chip internal signals. flash_rst_n for on-chip Flash memory RST N Power On Reset por Reset debounce reset_source_n boot_loader_rst_n for Boot Loader SW RBT bit (CSREPR.1) system_rst_n for system logics except for Ethernet PHY SW_RST bit (CSREPR.0) Boot loader shadow complete I2C EEPROM loader load complete SYS_RSTO_N Reset for embedded Ethernet PHY IPRL bit (PCR.2, PHY Control Register) Figure 50: AX11015 Reset Generation Block Diagram VCCK T1 RST_N por T2 T3 osclk T4 reset_source_n boot_loader_rst_n T5 system_rst_n or SYS_RSTO_ N Figure 51: AX11015 Reset Timing Diagram 68 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Symbol Description Min Typ Max Unit T1 RST_N asserting low interval after VCCK ramping up to 1.8V 4 T2 The internal "por" signal asserting low interval after RST_N de-assertion T3 From VCCK rise to 1.8V to first osclk transition 1.2 ms T4 From internal "por" signal de-assertion to de-assertion of internal debounced "reset_source_n" signal. 100 clock s T5 From internal "boot_loader_rst_n" signal de-assertion to internal "system_rst_n" signal or SYS_RSTO_N de-assertion: Internally, this time depends on the program code size which Boot Loader needs to copy to on-chip 16KB SRAM and/or off-chip SRAM, i.e., the bigger the code size, the longer the time it takes before de-asserting "system_rst_n" or SYS_RSTO_N signals. 2.2 ms 3.0 4.3 Voltage Regulator Please refer to section 5.1.6. 69 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights 4.2 us AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 4.4 CPU Core and Debugger The 1T80390 CPU core block diagram is shown within the red line in Figure 52 below. On-chip 16K bytes Program SRAM External Memory Interface for off-chip Flash or SRAM chips On-chip 512K bytes Program Flash Memory Arbiter & Boot Loader On-chip 32K byte Data SRAM 1T 80390 CPU Core Opcode Decoder Program Memory Interface External Data Memory Interface Control Unit Debugger Interface External debug pins interface ALU Internal Data Memory Interface 256 bytes Internal Data Memory SFR Interface SFR Bus for: Memory Arbiter, DMA Engine, Interrupt Controller, Watchdog Timer, Power Management, Timers/Counters, UARTs, GPIO, TOE, Ethernet MAC, Ethernet PHY, PCA, I2C Controller, 1-Wire Controller, SPI Controller, Local Bus Interface Figure 52: CPU Core Block Diagram ALU - Arithmetic Logic Unit performs the arithmetic and logic operations during execution of an instruction. It contains accumulator (ACC), Program Status Word (PSW), (B) registers and related logic such as arithmetic unit, logic unit, multiplier and divider. Opcode Decoder - performs an instruction opcode decoding and the control functions for all other blocks. Control Unit - performs the core synchronization and data flow control. This module is directly connected to Opcode Decoder and manages execution of all micro-controller tasks. Program Memory Interface - contains Program Counter (PC) and related logic. It performs the instructions code fetching from on-chip 512K bytes Program Flash, on-chip 16K byte Program SRAM, or off-chip Program Flash/SRAM via External Memory Interface. The Program Memory can be also written. External Data Memory Interface - contains memory access related registers such as Data Pointer High (DPH), Data Pointer Low (DPL) and Data Pointer eXtended (DPX) registers. It performs the external Program and Data Memory addressing and data transfers. The Program fetch cycle length is programmed by user. 70 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Internal Data Memory Interface - Internal Data Memory interface controls access into the internal 256 bytes data memory. It contains 8-bit Stack Pointer (SP) register and related logic. SFRs Interface - Special Function Registers interface controls access to the special registers. It contains standard 8051/80390 SFR registers and some additional SFR registers specific to this chip. SFR register access (read, written, modified) can use all direct addressing mode instructions. Debugger Interface - provides an in-circuit emulator feature with 3 wires (clock out, data in, data out) interface and is used to connect to an external Hardware Assisted Debugger (HAD2) to communicate with the Debug Software running on PC. 4.4.1 CPU Core SFR Register Map Address 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x8E 0x92 0x93 0x95 0x9D 0xD0 0xE0 0xEA 0xF0 Name SP DPL0 DPH0 DPL1 DPH1 DPS PCON CKCON WTST DPX0 DPX1 ACON PSW ACC MXAX B Description Stack Pointer register Data Pointer 0 register (DPTR0) low byte Data Pointer 0 register (DPTR0) high byte Data Pointer 1register (DPTR1) low byte Data Pointer 1register (DPTR1) high byte Data Pointers Select register Power Configuration register Clock Control register Program Memory Wait States register Data Pointer eXtended 0 register Data Pointer eXtended 1 register Address Control register Program Status Word register Accumulator A register MOVX @Ri eXtended register B register Table 10: CPU Core SFR Register Map The following abbreviations are used in the "Access" column in all SFR register detailed description. Access R/W RO W1 CR R/W1 WO SC PS LL LH Description Software can read or write to the register bit. The register bit is read-only. Software can only write "1" to the register bit. Writing "0" to the register bit has no effect. The register bit will be clear after software reads it. Software can read or write "1" to the register bit. Writing "0" to the register bit has no effect. The register bit is write-only. Self-clearing. Value is permanently set. Latch to Low. Latch to High. 71 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 4.4.2 CPU Core SFR Register Description The 1T 80390 CPU core is fully compatible to the standard 8051 micro-controller, maintains all instruction mnemonics and binary compatibility. The CPU core incorporates some great architectural enhancements, which allow the CPU execution of instructions with high performance. The arithmetic section of the processor performs extensive data manipulation and is comprised of the 8-bit arithmetic logic unit (ALU), an ACC register, B register and PSW register as described below. The ALU performs typical arithmetic operations as: addition, subtraction, multiplication, division and additional operations such as: increment, decrement, BCD-decimal-add-adjust and compare. Within logic unit are performed: AND, OR, Exclusive OR, complement and rotation. The Boolean processor performs the bit operations as: set, clear, complement, jump-if-not-set, jump-if-set-and-clear and move to/from carry. The PSW contains several bits that reflect the current state of the CPU. Accumulator A register (ACC, 0xE0) 7 Bit Name Reset Value 6 5 4 3 2 1 0 2 1 0 ACC 0x00 Bit Name Access 7:0 ACC R/W The Accumulator A register. Description B Register (B, 0xF0) Bit Name Reset Value Bit Name Access 7:0 B R/W 7 6 5 4 3 B 0x00 Description The B register is used during multiply and divide operations. In other cases may be used as normal SFR. Program Status Word Register (PSW, 0xD0) Bit Name Reset Value 7 CY 6 AC 5 F0 4 RS1 3 RS0 2 OV 1 F1 0x00 Bit Name 0 P 1 F1 2 OV 4:3 5 6 7 Access Description R/W Parity flag R/W General purpose flag 1 Overflow flag R/W Register bank select bits RS [1:0] Function description 00 Bank 0, data address 0x00-0x07 RS1, RS0 R/W 01 Bank 1, data address 0x08-0x0F 10 Bank 2, data address 0x10-0x17 11 Bank 3, data address 0x18-0x1F F0 R/W General purpose flag 0 AC R/W Auxiliary carry CY R/W Carry flag 72 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights 0 P AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 4.4.3 Memory Allocation The 1T 80390 CPU core has separated address spaces for program and data memory. The Internal Data Memory, External Data Memory, SFRs and Program Memory areas have their own address spaces. The data memory is divided onto 2 M bytes of External Data Memory (on-chip SRAM used 0~32K bytes memory space, off-chip SRAM used 32K~2M bytes memory space) and 256 bytes of Internal Data Memory, plus a 128-bytes of SFR memory area. Please refer to section 3.2, section 3.3, and section 3.4 for memory map description. Program Memory Allocation The Program Memory is typically used for main code and constants. The 1T 80390 CPU core can support program memory operation in LARGE and FLAT mode. In LARGE mode, the addressable program memory space is located in 0x0000~0xFFFF (64K bytes), while in FLAT mode, the addressable program memory space is located in 0x000000~0x1FFFFF (2M bytes). After each reset, the 1T 80390 CPU core starts execution of program code at location 0x000000 in LARGE mode. The CPU core then can be switched to FLAT mode to support 2M bytes of linear program code space. The user is recommended to operate the 1T 80390 CPU core of AX11015 in FLAT mode to save the troubles of handling code banking. For program memory map description, please refer to section 3.2. The on-chip 16K bytes Program SRAM is located in program memory space 0x000000~0x003FFF. This part of the code is usually for BOOT code with system initialization functions, TFTP or UART, and Flash programming functions. After hardware reset or software reboot via setting SW_RBT bit (CSREPR.1), the Boot Loader will always copy this part of code from the lower 16K bytes space of on-chip 512K bytes Program Flash, before CPU starts running. When the CPU core runs and accesses program memory space between 0x000000~0x003FFF, it will fetch from the on-chip 16K bytes Program SRAM. When accessing beyond 0x003FFF program memory space, it will fetch from the on-chip 512K bytes Program Flash or the external memory chips. Having a separate Program SRAM allows updating firmware on the on-chip Flash memory while the CPU core continues running, to support the so-called In Application Programming (IAP) function. Program Memory Wait-state The program code residing on the on-chip 16K bytes Program SRAM is always fetched and executed by the CPU core without wait state (i.e., 1T). So besides BOOT code, user can consider using program memory space 0x000000~0x003FFF for any timing-critical routines or firmware to yield better CPU performance. The program code residing beyond 0x003FFF address space (on on-chip Flash memory and/or off-chip Flash or SRAM) may require some wait-state cycles depending on operating system clock frequency and whether or not the "program code shadow" mode is enabled. If "program code shadow" mode is not enabled, the program code is running on Flash memory, which need more wait states. If "program code shadow" mode is enabled, the program code is running on SRAM, which needs less wait states. The Program Memory Wait States (WTST) register is used to set user programmable wait state during program memory read and write access cycles. Program Memory Wait States Register (WTST, 0x92) Bit Name Reset Value 7 6 5 Reserved 4 3 2 1 WTST 0x07 73 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights 0 AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Bit Name Access Description Wait States register holds the information about Program Memory access time. The minimal read cycle takes 1 clock period (WTST = 000) and maximal 8 clock periods (WTST = 111). Based on operating system clock frequency, the recommended setting is as below, 2:0 WTST R/W System Clock 25Mhz 50Mhz 100Mhz Program Memory Wait State Setting, WTST [2:0] Program Code Shadow Mode Non-Shadow Mode 000 001 000 011 001 111 7:3 Reserved FLAT/LARGE Mode Switching Switching between LARGE and FLAT modes is performed by appropriate writes into ACON (0x9D) register. ACON is Timed Access protected register and has built in mechanism preventing its accidental writes. To switch between modes the following instructions should be performed: MOV TA, #0xAA; MOV TA, #0x55; MOV ACON, #0x02; Enable write to ACON register Switch to FLAT mode MOV TA, #0xAA MOV TA, #0x55; MOV ACON, #0x00; Enable write to ACON register Switch to LARGE mode or It can be done at any time while software is running. The time elapsed between first, second, and third operation does not matter (any number of Program Wait Sates is allowed). The only correct sequence is required. Any third instruction causes protection mechanism to be turned on. This means that time protected register is opened for write only for single instruction. Reading from such register is never protected. Address Control Register (ACON, 0x9D) 7 Bit Name Reset Value 6 5 4 Reserved AM 2 1 AM 0 Reserved 0x00 Bit Name Access 0 Reserved R/W 1 3 R/W Description Address Mode Control bit. This bit establishes the addressing mode for the 1T80390 CPU core. 0: 16-bit Addressing Mode - LARGE Mode. 1: 24-bit Contiguous Addressing Mode - FLAT Mode. 7: Reserved 2 Please note that some instructions are different for FLAT and LARGE mode. There are: LCALL, ACALL, JMP, LJMP, AJMP, MOVC, MOVX - DPTR related only POP, PUSH, RET Please refer to "AX110xx CPU Core Instruction Set User Guide" for more details. 74 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Program Write Enable Bit The Program Write Enable (PWE) bit (PCON.4) is used to enable/disable program memory write signal activity during MOVX instructions. When PWE bit is set to logic 1, the MOVX @DPTR, A instruction writes data located in accumulator register into program memory addressed by DPTR register (active DPX: DPH: DPL). The MOVX @Rx, A instruction writes data located in accumulator register into program memory addressed by MXAX (bits 23:16), P2 register (bits 15:8) and Rx register (bits 7:0). The bits 23:16 are always equal to 0x00 for LARGE mode (64 KB of CODE). For detailed description of program memory write access to Flash memory, please refer to section 4.6.4 and 4.6.5. Power Configuration Register (PCON, 0x87) Bit Name Reset Value 7 SMOD0 6 SMOD1 5 Reserved 4 PWE 3 RSM 2 SWB 1 STOP 0 PMM 0x00 Bit Name Access 0 PMM R/W 1 STOP R/W 2 SWB R/W 3 RSM R/W 4 PWE R/W 5 6 7 Reserved SMOD1 SMOD0 R/W R/W R/W Description Power Management Mode Enable bit. 1: PMM entered. 0: PMM disabled. STOP mode bit. 1: STOP mode entered. 0: Disabled. Switchback enable. 1: Enabled interrupts and serial ports cause switchback. PMM bit is cleared. 0: Interrupts and serial ports don't affect PMM bit. Regulator Standby Mode. 1: Set the internal 3.3V to 1.8V regulator to operate at standby mode (when the 1.8V current drawn is less than 30mA) for better conversion efficiency. 0: Set the internal 3.3V to 1.8V regulator to full operating mode (when the 1.8V current drawn is more than 30mA) for better conversion efficiency. Program memory Write Enable bit. 1: Enable Program Memory write access signal activity during MOVX instructions. 0: Disabled. UART1 double baud rate bit. UART0 double baud rate bit. Data Memory Allocation The 1T 80390 CPU core can address up to 2M bytes of External Data (xDATA) Memory space without bank select. The xDATA memory is accessed by MOVX instructions only. The on-chip 32K bytes SRAM is located at address space 0x000000~0x007FFF. For address space above 0x007FFF, user will need to add some external SRAM chips for that. Please refer to section 2.6 for external SRAM chip connection and section 3.3 for external data memory map description. Data Memory Wait-state The External Data Memory (applied to both the on-chip 32K bytes SRAM and external SRAM chips) access cycles may need some wait states, depending on operating system clock frequency and the cycle time of external SRAM chips being used. The MD bits (CKCON.2~0) register is used to set user programmable wait state during data memory read and write access cycles. 75 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Clock Control Register (CKCON, 0x8E) 7 Bit Name Reset Value MD 5 T2M WD 4 T1M 3 T0M 2 1 MD 0 0x07 Bit Name Access 2:0 6 Description This adjusts the stretch cycles of XDATWR_N and XDATRD_N signals during MOVX instruction for External Data Memory write and read access cycles. The Minimal read/write pulse length is equal to 1 clock period (MD = 000) and maximal 8 clock periods (MD = 111). The MD bits can be changed any time during program execution. Based on operating system clock frequency and typical SRAM chip with 8ns access time, the R/W recommended setting is as below, Data Memory Wait State Setting, MD Program Code Shadow Mode Non-Shadow Mode 25Mhz 001 001 50Mhz 001 001 100Mhz 001 001 This bit controls the division of the system clock that drives Timer 0. 0: Timer 0 uses a divide-by-12 of the system clock frequency. 1: Timer 0 uses a divide-by-4 of the system clock frequency. This bit controls the division of the system clock that drives Timer 1. 0: Timer 1 uses a divide-by-12 of the system clock frequency. 1: Timer 1 uses a divide-by-4 of the system clock frequency. This bit controls the division of the system clock that drives Timer 2. This bit has no effect when the timer is in baud rate generator mode. 0: Timer 2 uses a divide-by-12 of the system clock frequency. 1: Timer 2 uses a divide-by-4 of the system clock frequency. WD bits select Watchdog timer timeout period. System Clock 3 T0M R/W 4 T1M R/W 5 T2M R/W 7:6 WD R/W Memory Related SFR Registers The following paragraph describes Program Memory, External Data Memory, and Internal Data Memory related SFRs of 1T 80390 CPU core and their functionality. Data Pointer Registers Dual data pointer registers are implemented to speed up data block copying. DPTR0 and DPTR1 are located at four SFR addresses. Active DPTR register is selected by SEL bit of Data Pointer Select (DPS) register. If SEL bit is equal to 0 then DPTR0 (0x83:0x82) is selected otherwise DPTR1 (0x85:0x84). DPH0 (0x83) 7 6 5 4 3 2 DPL0 (0x82) 1 0 7 6 5 4 3 2 1 0 2 1 0 Data Pointer register 0 (DPTR0) DPH1 (0x85) 7 6 5 4 3 2 DPL1 (0x84) 1 0 7 6 5 4 3 Data Pointer register 1 (DPTR1) 76 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Selected data pointer register is used in the following instructions: MOVX @DPTR, A MOVX A, @DPTR MOVC A, @A+DPTR JMP @A+DPTR INC DPTR MOV DPTR, #data16/#data24 Data Pointer 0 Register (DPTR0) High Byte (DPH0, 0x83) Bit Name Reset Value Bit 7:0 7 6 5 4 3 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 SEL DPH0 0x00 Name Access Description DPH0 R/W The high byte of Data Pointer 0 register. Data Pointer 0 Register (DPTR0) Low Byte (DPL0, 0x82) Bit Name Reset Value Bit 7:0 7 6 5 4 3 DPL0 0x00 Name Access Description DPL0 R/W The low byte of Data Pointer 0 register. Data Pointer 1 Register (DPTR1) High Byte (DPH1, 0x85) Bit Name Reset Value Bit 7:0 7 6 5 4 3 DPH1 0x00 Name Access Description DPH1 R/W The high byte of Data Pointer 1 register. Data Pointer 1 Register (DPTR1) Low Byte (DPL1, 0x84) Bit Name Reset Value Bit 7:0 7 6 5 4 3 DPL1 0x00 Name Access Description DPL1 R/W The low byte of Data Pointer 1 register. Data Pointers Select Register (DPS, 0x86) Bit Name Reset Value 7 ID1 6 ID0 5 4 3 TSL Reserved 0x00 77 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Bit Name Access 0 SEL R/W 4:1 Reserved 5 TSL Description Active DPTR register is selected by SEL bit. If SEL bit is equal to 0 then DPTR0 (0x83:0x82) is selected, otherwise DPTR1 (0x85:0x84). Toggle select enable. When set, this bit allows the following DPTR related instructions to toggle the SEL bit following execution of the instruction: INC DPTR MOV DPTR, #data16/#data24 MOVC A, @A+DPTR MOVX @DPTR, A MOVX A, @DPTR R/W When TSL=0, DPTR related instructions will not affect the state of the SEL bit. Increment/decrement function select. See table below. 7:6 ID1, ID0 ID1 0 0 1 1 R/W ID0 0 1 0 1 SEL=0 INC DPTR0 DEC DPTR0 INC DPTR0 DEC DPTR0 SEL=1 INC DPTR1 INC DPTR1 DEC DPTR1 DEC DPTR1 Data Pointer Extended Registers Data Pointer Extended registers DPX0, DPX1, MXAX hold the most significant part of memory address during access to data located above 64 K bytes. Note that DPX1 register is available only with DPTR1 register (DPH1, DPL1). During MOVX instruction using DPTR0/DPTR1 register, the most significant part of address bit [23:16] is always equal to DPX0 (0x93)/DPX1 (0x95) contents. During MOVX instruction using R0 or R1 register, the most significant part of address bit [23:16] is always equal to MXAX (0xEA) contents and address bit [15:8] is always equal to P2 (0xA0) contents. Data Pointer EXtended 0 Register (DPX0, 0x93) 7 Bit Name Reset Value 6 5 4 3 2 1 0 DPX0 0x00 Bit Name Access 7:0 DPX0 Description Data Pointer Extended register DPX0 holds the most significant part of memory address R/W during access to data located above 64 K bytes. During MOVX instruction using DPTR0 register, the most significant part of address bit [23:16] is always equal to DPX0 contents. Data Pointer EXtended 1 Register (DPX1, 0x95) 7 Bit Name Reset Value 6 5 4 3 2 1 Bit Name Access 7:0 DPX1 0 DPX1 0x00 Description Data Pointer Extended register DPX1 holds the most significant part of memory address R/W during access to data located above 64 K bytes. During MOVX instruction using DPTR1 register, the most significant part of address bit [23:16] is always equal to DPX1 contents. 78 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY MOVX @Ri EXtended Register (MXAX, 0xEA) 7 Bit Name Reset Value 6 5 4 3 2 1 0 MXAX 0x00 Bit Name Access 7:0 MXAX Description Data Pointer Extended register MXAX holds the most significant part of memory address during access to data located above 64 K bytes. During MOVX instruction using R0 or R1 R/W register, the most significant part of address bit [23:16] is always equal to MXAX contents and address bit [15:8] is always equal to P2 (0xA0) contents. Stack Pointer The 1T 80390 CPU core in both modes LARGE & FLAT has 8-bit stack pointer called SP (0x81) located in the internal RAM space. It is incremented before data is stored during PUSH and CALL execution and decremented after data is popped during POP, RET and RETI execution. In other words it always points to the last valid stack byte. The SP is accessed as any other SFRs. An example stack bytes order after some CALL instruction is shown in figure below. Figure 53: Stack Bytes Order Stack Pointer Register (SP, 0x81) Bit Name Reset Value Bit 7:0 7 6 5 4 3 2 1 SP 0x07 Name Access SP R/W The Stack Pointer register. Description Internal Data Memory & SFRs Allocation Please refer to section 3.4 Internal Data Memory and SFR Register Map for details. 79 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights 0 AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 4.4.4 Performance Improvement This section presents performance benefits from using 1T 80390 CPU core over standard 8051 families. 8-Bit Arithmetic Functions Addition (a) Immediate data: The following code performs immediate data (constant) addition to an 8-bit register. Rx = Rx + #n Mnemonic Opcode MOV A, Rx E8h - EFh ADD A, #n 24h MOV Rx, A F8h - FFh Sum: 80390 Performance Improvement: Bytes 1 2 1 80C51 cycles 12 12 12 36 1T 80390 cycles 1 2 1 4 9.0 (b) Direct addressing: The following code performs direct addressing addition to an 8-bit register. Rx = Rx + (dir) Mnemonic Opcode MOV A, Rx E8h - EFh ADD A, dir 25h MOV Rx, A F8h - FFh Sum: 80390 Performance Improvement: Bytes 1 2 1 80C51 cycles 12 12 12 36 1T 80390 cycles 1 2 1 4 9.0 (c) Indirect addressing: The following code performs indirect addressing addition to an 8-bit register. Rx = Rx + (@Rx) Mnemonic Opcode MOV A, Rx E8h - EFh ADD A, @Rx 26h - 27h MOV Rx, A F8h - FFh Sum: 80390 Performance Improvement: Bytes 1 1 1 80C51 cycles 12 12 12 36 1T 80390 cycles 1 2 1 4 9.0 (d) Register addressing: The following code performs an 8-bit register-to-register addition. Rx = Rx + Ry Mnemonic Opcode MOV A, Rx E8h - EFh ADD A, @Ry 28h - 2Fh MOV Rx, A F8h - FFh Sum: 80390 Performance Improvement: Bytes 1 1 1 80C51 cycles 12 12 12 36 1T 80390 cycles 1 1 1 3 12.0 80 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Subtraction (a) Immediate data: The following code performs immediate data (constant) subtraction from an 8-bit register. Rx = Rx - #n Mnemonic Opcode MOV A, Rx E8h - EFh SUBB A, #n 24h MOV Rx, A F8h - FFh Sum: 80390 Performance Improvement: Bytes 1 2 1 80C51 cycles 12 12 12 36 1T 80390 cycles 1 2 1 4 9.0 (b) Direct addressing: The following code performs direct addressing subtraction from an 8-bit register. Rx = Rx - (dir) Mnemonic Opcode MOV A, Rx E8h - EFh SUBB A, dir 25h MOV Rx, A F8h - FFh Sum: 80390 Performance Improvement: Bytes 1 2 1 80C51 cycles 12 12 12 36 1T 80390 cycles 1 2 1 4 9.0 (c) Indirect addressing subtraction: The following code performs indirect addressing subtraction from an 8-bit register. Rx = Rx - (@Ry) Mnemonic Opcode MOV A, Rx E8h - EFh SUBB A, @Ry 26h - 27h MOV Rx, A F8h - FFh Sum: 80390 Performance Improvement: Bytes 1 1 1 80C51 cycles 12 12 12 36 1T 80390 cycles 1 2 1 4 9.0 (d) Register addressing subtraction: The following code performs an 8-bit register from register subtraction. Rx = Rx - Ry Mnemonic Opcode MOV A, Rx E8h - EFh SUBB A, Ry 28h - 2Fh MOV Rx, A F8h - FFh Sum: 80390 Performance Improvement: Bytes 1 1 1 80C51 cycles 12 12 12 36 80390 cycles 1 1 1 3 12.0 81 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Multiplication The following code performs the 8-bit registers multiplication. Rx = Rx * Ry Mnemonic Opcode MOV A, Rx E8h - EFh MOV B, Ry 88h - 8Fh MUL AB A4h MOV Rx, A F8h - FFh Sum: 80390 Performance Improvement: Bytes 1 2 1 1 80C51 cycles 12 24 48 12 96 80390 cycles 1 2 2 1 6 16.0 Division The following code performs the 8-bit registers division. Rx = Rx / Ry Mnemonic Opcode MOV A, Rx E8h - EFh MOV B, Ry 88h - 8Fh DIV AB 84h MOV Rx, A F8h - FFh Sum: 80390 Performance Improvement: Bytes 1 2 1 1 80C51 cycles 12 24 48 12 96 80390 cycles 1 2 6 1 10 9.6 16-Bit Arithmetic Functions Addition The following code performs 16-bit addition. The first operand and result are located in registers pair RaRb. Second operand is located in registers pair RxRy. RaRb = RaRb + RxRy Mnemonic Opcode MOV A, Rb E8h - EFh ADD A, Ry 28h - 2Fh MOV Rb, A F8h - FFh MOV A, Ra E8h - EFh ADDC A, Rx 38h - 3Fh MOV Ra, A F8h - FFh Sum: 80390 Performance Improvement: Bytes 1 1 1 1 1 1 80C51 cycles 12 12 12 12 12 12 72 80390 cycles 1 1 1 1 1 1 6 12.0 Subtraction The following code performs 16-bit subtraction. The first operand and result are located in registers pair RaRb. Second operand is located in registers pair RxRy. RaRb = RaRb - RxRy CLR MOV SUBB MOV MOV SUBB Mnemonic C A, Rb A, Ry Rb, A A, RA A, Rx Opcode C3h E8h - EFh 28h - 2Fh F8h - FFh E8h - EFh 98h - 9Fh Bytes 1 1 1 1 1 1 80C51 cycles 12 12 12 12 12 12 82 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights 80390 cycles 1 1 1 1 1 1 AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY MOV Ra, A F8h - FFh Sum: 80390 Performance Improvement: 1 12 84 1 7 12.0 Multiplication The following code performs 16-bit multiplication. The first operand and result are located in registers pair RaRb. Second operand is located in registers pair RxRy. RaRb = RaRb * RxRy Mnemonic Opcode MOV A, Rb E8h - EFh MOV B, Ry 88h - 8Fh MUL AB A4 h MOV Rz, B A8h - AFh XCH A, Rb C8h - CFh MOV B, Rx 88h - 8Fh MUL AB A4h ADD A, Rz 28h - 2Fh XCH A, Ra C8h - CFh MOV B, Ry 88h - 8Fh MUL AB A4h ADD A, Ra 28h - 2Fh MOV Ra, A F8h - FFh Sum: 80390 Performance Improvement: Bytes 1 2 1 2 1 2 1 1 1 2 1 1 1 80C51 cycles 12 24 48 24 12 24 48 12 12 24 48 12 12 312 80390 cycles 1 2 2 3 2 2 2 1 2 2 2 1 1 23 13.6 32-Bit Arithmetic Function Addition The following code performs 32-bit addition. The first operand and result are located in four registers RaRbRcRd. Second operand is located in four registers RvRxRyRz. RaRbRcRd = RaRbRcRd + RvRxRyRz Mnemonic Opcode MOV A,Rd E8h - EFh ADD A, Rz 28h - 2Fh MOV Rd, A F8h - FFh MOV A, Rc E8h - EFh ADDC A, Ry 38h - 3Fh MOV Rc, A F8h - FFh MOV A, Rb E8h - EFh ADDC A, Rx 38h - 3Fh MOV Rb, A F8h - FFh MOV A, Ra E8h - EFh ADDC A, Rv 38h - 3Fh MOV Ra, A F8h - FFh Sum: 80390 Performance Improvement: Bytes 1 1 1 1 1 1 1 1 1 1 1 1 80C51 cycles 12 12 12 12 12 12 12 12 12 12 12 12 144 80390 cycles 1 1 1 1 1 1 1 1 1 1 1 1 12 12.0 83 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Subtraction The following code performs 32-bit subtraction. The first operand and result are located in four registers RaRbRcRd. Second operand is located in four registers RvRxRyRz. RaRbRcRd = RaRbRcRd - RvRxRyRz Mnemonic Opcode CLR C C3h MOV A, Rd E8h - EFh SUBB A, Rz 98h - 9Fh MOV Rd, A F8h - FFh MOV A, Rc E8h - EFh SUBB A, Ry 98h - 9Fh MOV Rc, A F8h - FFh MOV A, Rb E8h - EFh SUBB A, Rx 98h - 9Fh MOV Rb, A F8h - FFh MOV A, Ra E8h - EFh SUBB A, Rv 98h - 9Fh MOV Ra, A F8h - FFh Sum: 80390 Performance Improvement: Bytes 1 1 1 1 1 1 1 1 1 1 1 1 1 80C51 cycles 12 12 12 12 12 12 12 12 12 12 12 12 12 156 80390 cycles 1 1 1 1 1 1 1 1 1 1 1 1 1 13 12.0 Multiplication The following code performs 32-bit multiplication. The first operand and result are located in four registers RaRbRcRd. Second operand is located in four registers RvRxRyRz. RaRbRcRd = RaRbRcRd * RvRxRyRz Mnemonic MOV A, R0 MOV B, R7 MUL AB XCH A, R4 MOV B, R3 MUL AB ADD A, R4 MOV R4, A MOV A, R1 MOV B, R6 MUL AB ADD A, R4 MOV R4, A MOV B, R2 MOV A, R5 MUL AB ADD A, R4 MOV R4, A MOV A, R2 MOV B, R6 MUL AB XCH A, R5 MOV R0, B MOV B, R3 MUL AB ADD A, R5 XCH A, R4 ADDC A, R0 Opcode E8h - EFh 88h - 8Fh A4 h C8h - CFh 88h - 8Fh A4h 28h - 2Fh F8h - FFh E8h - EFh 88h - 8Fh A4h 28h - 2Fh F8h - FFh 88h - 8Fh E8h - EFh A4h 28h - 2Fh F8h - FFh E8h - EFh 88h - 8Fh A4h C8h - CFh A8h - AFh 88h - 8Fh A4h 28h - 2Fh C8h - CFh 38h - 3Fh Bytes 1 2 1 1 2 1 1 1 1 2 1 1 1 2 1 1 1 1 1 2 1 1 2 2 1 1 1 1 80C51 cycles 12 24 48 12 24 48 12 12 12 24 48 12 12 24 12 48 12 12 12 24 48 12 24 24 48 12 12 12 84 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights 80390 cycles 1 2 2 2 2 2 1 1 1 2 2 1 1 2 2 2 1 1 1 2 2 2 3 2 2 1 2 1 AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY ADD A, B 25h MOV R5, A F8h - FFh MOV A, R1 E8h - EFh MOV B, R7 88h - 8Fh MUL AB A4h ADD A, R4 28h - 2Fh XCH A, R5 C8h - CFh ADDC A, B 35h MOV R4, A F8h - FFh MOV A, R3 E8h - EFh MOV B, R6 88h - 8Fh MUL AB A4h MOV R6, A F8h - FFh MOV R1, B A8h - AFh MOV A, R3 E8h - EFh MOV B, R7 88h - 8Fh MUL AB A4h XCH A, R7 C8h - CFh XCH A, B C5h ADD A, R6 28h - 2Fh XCH A, R5 C8h - CFh ADDC A, R1 38h - 3Fh MOV R6, A F8h - FFh CLR A E4h ADDC A, R4 38h - 3Fh MOV R4, A F8h - FFh MOV A, R2 E8h - EFh MUL AB A4h ADD A, R5 28h - 2Fh XCH A, R6 C8h - CFh ADDC A, B 38h - 3Fh MOV R5, A F8h - FFh CLR A E4h ADDC A, R4 38h - 3Fh MOV R4, A F8h - FFh Sum: 80390 Performance Improvement: 2 1 1 2 1 1 1 2 1 1 2 1 1 2 1 2 1 1 2 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 12 12 12 24 48 12 12 12 12 12 24 48 12 24 12 24 48 12 12 12 12 12 12 12 12 12 12 48 12 12 12 12 12 12 12 1248 2 1 1 2 2 1 2 2 1 1 2 2 1 3 1 2 2 2 3 1 2 1 1 1 1 1 1 2 1 2 2 1 1 1 1 99 12.6 Performance Improvement Summary Total performance improvement has been summarized in the table below. It shows the most common used multi-precision arithmetic operation. Function 8-bit addition (immediate data) 8-bit addition (direct addressing) 8-bit addition (indirect addressing) 8-bit addition (register addressing) 8-bit subtraction (immediate data) 8-bit subtraction (direct addressing) 8-bit subtraction (indirect addressing) 8-bit subtraction (register addressing) 8-bit multiplication 8-bit division 16-bit addition 16-bit subtraction 16-bit multiplication 32-bit addition 80C51 cycle 36 36 36 36 36 36 36 36 96 96 72 84 312 144 80390 cycle 4 4 4 3 4 4 4 3 6 10 6 7 23 12 Improvement 9.0 9.0 9.0 12.0 9.0 9.0 9.0 12.0 16.0 9.6 12.0 12.0 13.6 12.0 85 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 32-bit subtraction 32-bit multiplication Average speed improvement: 156 1248 13 99 12.0 12.6 11.12 4.4.5 Debugger Flash Programming The debugger fully supports programming of all Flash memory devices. Such support is assured by configurability of Flash programming algorithm, and supported devices database. New Flash device can be easily added to existing base using build-in editor. The debugger allows user to simply perform in-system programming of its Flash memory without using any external equipment. Flash programming task is performed directly within Debug software, and after uploading of code, it is ready for debugging. Programming time is very short, because of HAD2 support. This feature saves time, and makes usage of debugger very comfortable and flexible. Non-Intrusive System In typical intrusive systems a debugging tool consumes for its own needs some system resources e.g.: part of program space, several cells of RAM memory, ports' pins sometimes system is loosing interrupts or the program code is manipulated to support software breakpoints, and so on. Even simple debugging system consumes the UART and timer resources to support own tasks. These simple 'emulators' cannot provide trace and other advanced debugging functions, while also being very intrusive in the debugging cycle. Imagine trying to debug an interrupt problem while the 'emulator' is manipulating interrupts itself! Developing firmware is all about producing code that is 100% reliable in operation and fully understood in how it will perform in adverse conditions. A real non-intrusive on-chip debugger that assists user in this task is the most important tool user can have. That is the reason why using of non-intrusive systems is so important. The debugger and debug software tools has been designed as a non-intrusive system. Real-time Hardware Debugger Real-time hardware debugger we call for a tool that is able to detect processor internal properties that are not visible outside the processor without any violation of real-time operations. The debugger gives you the chance to track down hidden bugs within the application running with micro-controller. Internal events such as the reading of the SBUF-control register are not mirrored on the external address-data bus. However, by using special logic to detect operations that affect internal resources, debugger gives user ability to track such internal events without any violation of real-time operation. There is no need to use a special external logic for the emulation. 86 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 4.5 On-Chip Flash Memory Block Diagram X/Y Decoder Address latch Program Memory Address from Memory Arbiter Flash Array Command /Data Latch Program Memory Data from Memory Arbiter Program Memory Read/Write control signals from Memory Arbiter Program/Erase High Voltage State Machine Control logic and Figure 54: On-Chip Flash Memory Block Diagram Sector Structure Sector Sector Size Address Range SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 16Kbytes 8Kbytes 8Kbytes 32Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 00000-03FFF 04000-05FFF 06000-07FFF 08000-0FFFF 10000-1FFFF 20000-2FFFF 30000-3FFFF 40000-4FFFF 50000-5FFFF 60000-6FFFF 70000-7FFFF A18 0 0 0 0 0 0 0 1 1 1 1 A17 0 0 0 0 0 1 1 0 0 1 1 Sector Address A16 A15 A14 0 0 0 0 0 1 0 0 1 0 1 X 1 X X 0 X X 1 X X 0 X X 1 X X 0 X X 1 X X A13 X 0 1 X X X X X X X X Table 11: On-Chip Flash Memory Sector Structure Automatic Programming The on-chip Flash memory is byte programmable using the Automatic Programming algorithm. The Automatic Programming algorithm makes system do not need to have time-out sequence nor to verify the data programmed. 87 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Automatic Chip Erase The entire on-chip Flash memory is bulk erased using 10ms erase pulses according to Automatic Chip Erase algorithm. Typical erasure at room temperature is accomplished in less than 4 second. The Automatic Erase algorithm automatically programs the entire array prior to electrical erase. The timing and verification of electrical erase are controlled internally within the Flash memory. Automatic Sector Erase The on-chip Flash memory is sector(s) erasable using Automatic Sector Erase algorithm. The Automatic Sector Erase algorithm automatically programs the specified sector(s) prior to electrical erase. The timing and verification of electrical erase are controlled internally within the Flash memory. An erase operation can erase one sector, multiple sectors, or the entire Flash memory. Automatic Programming Algorithm The Automatic Programming algorithm requires the user to only write program set-up commands (including 2 unlock write cycle and A0H) and a program command (program data and address). The Flash memory automatically times the programming pulse width, provides the program verification, and counts the number of sequences. During a program cycle, the state-machine will control the program sequences and command register will not respond to any command set. A status bit similar to Data# Polling and a status bit toggling between consecutive read cycles, provide feedback to the user as to the status of the programming operation. Refer to write operation status, Table 13, for more information on these status bits. Automatic Erase Algorithm The Automatic Erase algorithm requires the user to write commands to the command register. The Flash memory will automatically pre-program and verify the entire array. Then the Flash memory automatically times the erase pulse width, provides the erase verification, and counts the number of sequences. A status bit toggling between consecutive read cycles provides feedback to the user as to the status of the erasing operation. Register contents serve as inputs to an internal state-machine, which controls the erase and programming circuitry. During write cycles, the command register internally latches address and data needed for the programming and erase operations. During a Sector Erase cycle, the command register will only respond to Erase Suspend command. After Erase Suspend is completed, the Flash memory stays in read mode. After the state machine has completed its task, it will allow the command register to respond to its full command set. Command Definitions Flash memory operations are selected by writing specific address and data sequences into the command register. Writing incorrect address and data values or writing them in the improper sequence will reset the Flash memory to the Read mode. Table 12 defines the valid register command sequences. Note that the Erase Suspend (B0H) and Erase Resume (30H) commands are valid only while the Sector Erase operation is in progress. An erase operation can erase one sector, multiple sectors, or the entire Flash memory. Table 11 indicates the address space that each sector occupies. A "sector address" consists of the address bits required to uniquely select a sector. The writing specific address and data commands or sequences into the command register initiates the Flash memory operations. 88 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Command Bus Cycle Required 1st Bus Cycle Reset Read 1 1 Addr XXXH RA Data F0H RD Program 4 555H AAH Chip Erase 6 555H AAH Sector Erase 6 555H AAH 1 XXXH B0H 1 XXXH 30H Sector Erase Suspend Sector Erase Resume 2nd Bus 3rd Bus 6th Bus 4th Bus Cycle 5th Bus Cycle Cycle Cycle Cycle Addr Data Addr Data Addr Data Addr Data Addr Data 2AA H 2AA H 2AA H 55H 555H A0H 55H 555H 80H 55H 555H 80H PA PD 2AA H 2AA 555H AAH H 555H AAH 55H 55H 555H 10H SA 30H Note: 1. RA=Address of memory location to be read. RD=Data to be read at location RA. 2. PA = Address of memory location to be programmed. PD = Data to be programmed at location PA. SA = Address of the sector to be erased. 3. The software should generate the following address patterns: 555H or 2AAH to Address A11~A0. Address bit A12~A18 = X = Don't care for all address commands except for Program Address (PA) and Sector Address (SA). Write Sequence may be initiated with A12~A18 in either state. Table 12: On-Chip Flash Memory Command Definitions Read Flash Array Data The internal state machine is set for reading array data upon Flash memory power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. The Flash memory remains enabled for read access until the command register contents are altered. The Flash memory is also ready to read array data after completing an Automatic Program or Automatic Erase algorithm. After the Flash memory accepts an Erase Suspend command, the Flash memory enters the Erase Suspend mode. The CPU can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors, the Flash memory outputs status data. After completing a programming operation in the Erase Suspend mode, the CPU may once again read array data with the same exception. See "Erase Suspend/Erase Resume Commands" for more information on this mode. The system must issue the reset command to re-enable the device for reading array data if Q5 (data bit 5) goes high, or while in the auto-select mode. See the "Reset Command" section, next. Reset Command The reset operation is initiated by writing the reset command sequence into the command register. The Flash memory remains enabled for reads until the command register contents are altered. If program-fail or erase-fail happen, the write of F0H will reset the Flash memory to abort the operation. Address bits are don't-care for this command. A valid command must then be written to place the Flash memory in the desired state. Writing the reset command to the Flash memory resets the device to reading array data. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the Flash memory ignores reset commands until the operation is complete. 89 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the Flash memory to reading array data (also applies to programming in Erase Suspend mode). Once programming begins, however, the Flash memory ignores reset commands until the operation is complete. If Q5 (data bit 5) goes high during a program or erase operation, writing the reset command returns the Flash memory to reading array data (also applies during Erase Suspend). Automatic Chip Erase Commands Chip Erase is a six-bus cycle operation. There are two "unlock" write cycles. These followed by writing the set-up command 80H. The second "unlock" write cycles are then followed by the chip erase command 10H. The Automatic Chip Erase does not require the Flash memory to be entirely pre-programmed prior to executing the Automatic Chip Erase. Upon executing the Automatic Chip Erase, the state machine in Flash memory will automatically program and verify the entire Flash memory for an all-zero data pattern. When the Flash memory is automatically verified to contain an all-zero pattern, a self-timed chip erase and verify begin. The erase and verify operations are completed when the data on Q7 (data bit 7) is "1" at which time the Flash memory returns to the Read mode. The software is not required to provide any control or timing during these operations. When using the Automatic Chip Erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array (no erase verification command is required). If the Erase operation was unsuccessful, the data on Q5 (data bit 5) is "1"(see Table 13), indicating the erase operation exceed internal timing limit. Figure 55: Automatic Chip Erase Algorithm Flowchart 90 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Automatic Sector Erase Commands Sector Erase is a six-bus cycle operations. There are two "unlock" write cycles. These followed by writing the set-up command 80H. Two more "unlock" write cycles are then followed by the sector erase command 30H. Sector addresses selected are loaded into internal register on the sixth command. The Automatic Sector Erase does not require the Flash memory to be entirely pre-programmed prior to executing the Automatic Sector Erase Set-up commands and Automatic Sector Erase command. Upon executing the Automatic Sector Erase command, the Flash memory will automatically program and verify the sector(s) memory for an all-zero data pattern. The software is not required to provide any control or timing during these operations. When the sector(s) is automatically verified to contain an all-zero pattern, a self-timed sector erase and verify begin. The erase and verify operations are completed when the data on Q7 (data bit 7) is "1" and the data on Q6 (data bit 6) stops toggling for two consecutive read cycles, at which time the Flash memory returns to the Read mode. The software is not required to provide any control or timing during these operations. When using the Automatic Sector Erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array (no erase verification command is required). Figure 56: Automatic Sector Erase Algorithm Flowchart 91 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Erase Suspend This command only has meaning while the state machine is executing Automatic Sector Erase operation, and therefore will only be responded during Automatic Sector Erase operation. When the Erase Suspend command is written during a sector erase operation, the Flash memory requires a maximum of 20us to suspend the erase operations. However, When the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. After this command has been executed, the command register will initiate erase suspend mode. The state machine will return to read mode automatically after suspend is ready. At this time, state machine only allows the command register to respond to the Read Memory Array, Erase Resume and Program commands. The system can determine the status of the program operation using the Q7 (data bit 7) or Q6 (data bit 6) status bits, just as in the standard program operation. After an erase-suspend operation is complete, the software can once again read array data within non-suspended sectors. Erase Resume This command will cause the command register to clear the suspend state and return back to Sector Erase mode but only if an Erase Suspend command was previously issued. Erase Resume will not have any effect in all other conditions. Another Erase Suspend command can be written after the chip has resumed erasing. The minimum time from Erase Resume to next Erase Suspend is 400us. Repeatedly suspending the device more often may have undetermined effects. Note: Repeatedly suspending the device more often may have undetermined effects. Figure 57: Erase Suspend/Erase Resume Flowchart 92 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Automatic Program Commands To initiate Automatic Program mode, a three-cycle command sequence is required. There are two "unlock" write cycles, followed by writing the Automatic Program command A0H. The program address and data are written next, which in turn initiate the embedded Program Algorithm. Once the Automatic Program command is initiated, the next write causes a transition to an active programming operation. The software is not required to provide further controls or timings. The Flash memory will automatically provide an adequate internally generated program pulse and verify the programmed cell margin. When the embedded Program algorithm is complete, the Flash memory then returns to reading array data and addresses are no longer latched. The Flash memory provides Q2, Q3, Q5, Q6 and Q7 (i.e., data bit 2, 3, 5, 6, and 7) to determine the status of a write operation. If the program operation was unsuccessful, the data on Q5 is "1"(see Table 13), indicating the program operation exceed internal timing limit. The automatic programming operation is completed when the data read on Q6 stops toggling for two consecutive read cycles and the data on Q7 and Q6 are equivalent to data written to these two bits, at which time the Flash memory returns to the Read mode (no program verify command is required). Any commands written to the Flash memory during the embedded Program Algorithm are ignored. Note that a hardware reset on RST_N pin immediately terminates the programming operation. The Byte Program command sequence should be reinitiated once the Flash memory has reset to reading array data, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. Please note that a bit cannot be programmed from a "0" back to a "1". Attempting to do so may halt the operation and set the Q5 to "1", or cause the Data# Polling algorithm to indicate the operation was successful. However, a succeeding read will show that the data is still "0". Only erase operations can convert a "0" to a "1". Figure 58: Automatic Programming Algorithm Flowchart 93 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Write Operation Status The Flash memory provides several bits on data bus to determine the status of a write operation: Q2, Q3, Q5, Q6 and Q7. Table 13 and the following subsections describe the functions of these bits. Q7 and DQ6 each offer a method for determining whether a program or erase operation is complete or in progress. These three bits are discussed first. Status Byte Program in Auto Program Algorithm Auto Erase Algorithm Q7 (Note 1) Q6 Q5 (Note 2) Q3 Q2 Q7# Toggle 0 N/A No Toggle 0 Toggle 0 1 Toggle Erase Erase Suspend Read In Progress Suspended (Erase Suspended Sector) Mode Erase Suspend Read Non-Erase Suspended Sector) Erase Suspend Program 1 No Toggle 0 N/A Toggle Data Data Data Data Data Q7# Toggle 0 N/A N/A Byte Program in Auto Program Algorithm Q7# Toggle 1 N/A No Toggle 0 Toggle 1 1 Toggle Q7# Toggle 1 N/A N/A Exceeded Time Limits Auto Erase Algorithm Erase Suspend Program Note: 1. Q7 and Q2 require a valid address when reading status information. Refer to the appropriate subsection for further details. 2. Q5 switches to '1' when an Auto Program or Auto Erase operation has exceeded the maximum timing limits. See "Q5: Exceeded Timing Limits " for more information. Table 13:Write Operation Status Q7: Data# Polling The Data# Polling bit, Q7, indicates to the software whether an Automatic Algorithm is in progress or completed, or whether the Flash memory is in Erase Suspend. During the Automatic Program algorithm, the Flash memory outputs on Q7 the complement of the datum programmed to Q7. This Q7 status also applies to programming during Erase Suspend. When the Automatic Program algorithm is complete, the device outputs the datum programmed to Q7. The software must provide the program address to read valid status information on Q7. If a program address falls within a protected sector, Data# Polling on Q7 is active for approximately 1 us, then the device returns to reading array data. During the Automatic Erase algorithm, Data# Polling produces a "0" on Q7. When the Automatic Erase algorithm is complete, or if the Flash memory enters the Erase Suspend mode, Data# Polling produces a "1" on Q7. This is analogous to the complement/true datum output described for the Automatic Program algorithm: the erase function changes all the bits in a sector to "1" prior to this, the Flash memory outputs the "complement," or "0". The software must provide an address within any of the sectors selected for erasure to read valid status information on Q7. After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on Q7 is active for approximately 100 us, then the Flash memory returns to reading array data. If not all selected sectors are protected, the Automatic Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. When the software detects Q7 has changed from the complement to true data, it can read valid data at Q7-Q0 on the following read cycles. 94 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Note: 1. VA=Valid address for programming 2. Q7 should be re-checked even Q5="1" because Q7 may change simultaneously with Q5. Figure 59: Data# Polling Algorithm Q6: Toggle BIT I Toggle Bit I on Q6 indicates whether an Automatic Program or Erase algorithm is in progress or complete, or whether the Flash memory has entered the Erase Suspend mode. Toggle Bit I may be read at any address, in the command sequence (prior to the program or erase operation), and during the sector timeout. During an Automatic Program or Erase algorithm operation, successive read cycles to any address cause Q6 to toggle. When the operation is complete, Q6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, Q6 toggles and returns to reading array data. If not all selected sectors are protected, the Automatic Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The software can use Q6 and Q2 together to determine whether a sector is actively erasing or is erase be suspended. When the Flash memory is actively erasing (that is, the Automatic Erase algorithm is in progress), Q6 start toggling. When the Flash memory enters the Erase Suspend mode, Q6 stops toggling. However, the software must also use Q2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use Q7. If a program address falls within a protected sector, Q6 toggles for approximately 2 us after the program command sequence is written, then returns to reading array data. Q6 also toggles during the erase-suspend-program mode and stops toggling once the Automatic Program algorithm is complete. 95 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Q2: Toggle Bit II The "Toggle Bit II" on Q2, when used with Q6, indicates whether a particular sector is actively erasing (that is, the Automatic Erase algorithm is in process), or whether that sector is erase-suspended. Q2 toggles when the software reads at addresses within those sectors that have been selected for erasure. But Q2 cannot distinguish whether the sector is actively erasing or is erase-suspended. Q6, by comparison, indicates whether the Flash memory is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sectors and mode information. Refer to Table 13 to compare outputs for Q2 and Q6. Reading Toggle Bits Q6/ Q2 Whenever the software initially begins reading toggle bit status, it must read Q7-Q0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the software would note and store the value of the toggle bit after the first read. After the second read, the software would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the Flash memory has completed the program or erase operation. The software can read array data on Q7-Q0 on the following read cycle. However, if after the initial two read cycles, the software determines that the toggle bit is still toggling, the software also should note whether the value of Q5 is high (see the section on Q5). If it is, the software should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as Q5 went high. If the toggle bit is no longer toggling, the Flash memory has successfully completed the program or erase operation. If it is still toggling, the Flash memory did not complete the operation successfully, and the software must write the reset command to return to reading array data. The remaining scenario is that software initially determines that the toggle bit is toggling and Q5 has not gone high. The software may continue to monitor the toggle bit and Q5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the software must start at the beginning of the algorithm when it returns to determine the status of the operation. 96 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Note: 1.Read toggle bit twice to determine whether or not it is toggling. 2. Recheck toggle bit because it may stop toggling as Q5 change to "1". Figure 60: Toggle Bit Algorithm Q5: Exceeded Timing Limits Q5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under these conditions Q5 will produce a "1". This time-out condition indicates that the program or erase cycle was not successfully completed. Data# Polling and Toggle Bit are the only operating functions of the device under this condition. If this time-out condition occurs during sector erase operation, it specifies that a particular sector is bad and it may not be reused. However, other sectors are still functional and may be used for the program or erase operation. The Flash memory must be reset to use other sectors. Write the Reset command sequence to the Flash memory, and then execute program or erase command sequence. This allows the software to continue to use the other active sectors in the Flash memory. If this time-out condition occurs during the chip erase operation, it specifies that the entire chip is bad or combination of sectors is bad. If this time-out condition occurs during the byte programming operation, it specifies that the entire sector containing that byte is bad and this sector may not be reused, (other sectors are still functional and can be reused). The time-out condition will not appear if a user tries to program a non-blank location without erasing. Please note that this is not a Flash memory failure condition since the Flash memory was incorrectly used. 97 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Q3: Sector Erase Timer After the completion of the initial sector erase command sequence, the sector erase time-out will begin. Q3 will remain low until the time-out is complete. Data# Polling and Toggle Bit are valid after the initial sector erase command sequence. If Data# Polling or the Toggle Bit indicates the Flash memory has been written with a valid erase command, Q3 may be used to determine if the sector erase timer window is still open. If Q3 is high ("1") the internally controlled erase cycle has begun; attempts to write subsequent commands to the Flash memory will be ignored until the erase operation is completed as indicated by Data# Polling or Toggle Bit. If Q3 is low ("0"), the Flash memory will accept additional sector erase commands. To insure the command has been accepted, the software should check the status of Q3 prior to and following each subsequent sector erase command. If Q3 were high on the second status check, the command may not have been accepted. Erase and Programming Performance Parameter Limits Typ. 0.7 4 9 4.5 Min. Sector Erase Time Chip Erase Time Byte Programming Time Chip Programming Time Erase/Program Cycles Unit Max. 15 32 300 13.5 100,000 sec sec us sec cycles Program Code Read Protection in On-chip Flash Memory When the program code in on-chip Flash memory needs to be protected from unauthorized downloading for copyright protection purpose, the on-chip Flash memory offers a hardware mechanism to support this. The on-chip Flash memory location 0x03FFF in bit 7 is used to enable/disable the on-chip Flash memory read protection. Setting or clearing this bit will not affect normal program code execution by the CPU core. See below Table 14 for detailed description. CPU Debugger Access On-chip Flash Memory Location 0x003FFF Bit 7 = Read Protection Disable bit Bit [6:0] 1 Reserved and put CPU Debugger access is enabled. The program code 0x00 can be downloaded from Flash memory to CPU Debugger software. This setting is usually used during software development in progress. 0 Reserved and put CPU Debugger access is disabled. The program code 0x00 cannot be downloaded from Flash memory to CPU Debugger software. This setting is usually used after the software development is complete and ready for production. Table 14: On-chip Flash Memory Read Protection 98 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 4.6 Memory Arbiter & Boot Loader Figure 61 below shows Memory Arbiter, Boot Loader, and Flash Programming Controller block diagram. Figure 61: Boot Loader, Memory Arbiter & Flash Programming Controller Block Diagram 4.6.1 Boot Loader After power-on reset or software reboot command via setting SW_RBT bit (CSREPR.1), the boot loader will read the Flash memory to load the program code to the internal 16K byte Program SRAM and to the optional external Program SRAM first before allowing CPU core to start running. The setting of EXT_PROG_SRAM_EN pin determines whether the external Program SRAM is present or not and is used to determine whether to load to the external Program SRAM or not. When EXT_PROG_SRAM_EN = 1, indicating the external program SRAM is present, the on-chip Flash memory address location, 0x00_3FFF, in bit [6:0] called "BLOCK_NUMBER" is used to tell the boot loader how many bytes of program code need to be loaded from the Flash memory to the external Program SRAM. Each block number represents 32K bytes of program code data. For example, if program code size is less than 32K Bytes, user shall write 0x01 in "BLOCK_NUMBER" byte. If program code size is between 32-64KB, then put 0x02 in "BLOCK_NUMBER" byte, etc. Note that the internal 16K bytes Program SRAM (boot code) is always loaded by boot loader regardless of the setting of EXT_PROG_SRAM_EN. Note that in on-chip Flash memory address location 0x00_3FFF, the bit 7 is used for program code read protection bit. Please see Table 14 for details. The "BLOCK_NUMBER" byte is also being passed to the memory arbiter to control the address bus conversion of External Memory Interface when the external SRAM chip(s) is used for both program code shadow mode and xDATA memory expansion purposes. 99 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Clock Speed, Software Reset and Ext. Program Memory Select Register (CSREPR, 0x8Fh) Bit Name Reset Value 7 6 SCS [1:0] 00 5 ICD 0 4 PMS 0 3 FAES 0 2 FARM 0 1 SW_RBT 0 0 SW_RST 0 Bit Name Access Description 0 SW_RST R/W1 Software Reset. Setting to "1" to reset all peripheral logics and CPU itself. Upon activated, this bit will be cleared by chip hardware automatically. 1 SW_RBT R/W1 Software Reboot. Setting to "1" to reset and reboot the whole chip including CPU and all peripherals. This step will cause the Boot Loader to redo the program mirroring/shadow step and reload the content of I2C Configuration EEPROM to related registers. Upon activated, this bit will be cleared by chip hardware automatically. 2 FARM R/W Flash Address Re-Mapping. See section 4.6.4 for detailed description. 1: To enable software to gain access to the first 16KB (0x00_0000~0x00_3FFF) of the on-chip Flash memory. After enabled, software can access to the first 16KB of the Flash memory by accessing the program memory space 16K~32K (x00_4000~0x007FFF) which then will be remapped to 0~16K (0x00_0000~0x00_3FFF) address space of on-chip Flash memory by the "Memory Arbiter" hardware. Note that when enabled, the software accessing to the lower 16KB of program memory space is still accessing to the internal 16KB Program SRAM as usual, and the accessing of the 16KB~32KB address space of on-chip Flash memory is temporarily disabled. 0: To disable software accessing the first 16KB of on-chip Flash memory. When disabled, software accessing to the program memory space 16K~32K (0x00_4000 ~ 0x007FFF) would be accessing to the same address space of the on-chip Flash memory without re-mapping (default). Note that when disabled, the software accessing to the first 16KB of program memory space is still accessing to the internal 16KB Program SRAM as usual. 3 FAES R/W Flash Access Enable in Shadow mode. See section 4.6.4 for detailed description. 1: To enable Flash memory access during enabling program code shadow mode. Normally, when an external Program SRAM is being used for program code shadow purpose, in that case, the CPU program read or write accesses to 16KB above (0x00_4000 and above) address space would be directed to the external Program SRAM. When there comes the time that the software needs to read or write the 16KB above address space of the on-chip Flash memory, it needs to set this bit to 1 to be able to gain access to the on-chip Flash memory instead of the external Program SRAM. When enabled, the access of external Program SRAM is temporarily disabled. 0: To disable Flash memory access during enabling program code shadow mode. When program shadow mode is enabled, software accessing of 16KB above (0x00_4000 and above) address space would be the accessing of the external Program SRAM (default). 4 PMS RO Program Memory Shadow. This bit reflects the current setting of input pin EXT_PROG_SRAM_EN. 1: Program shadow mode is enabled, i.e., the program code is run on Program SRAM. 0: Program non-shadow mode, the program code is run on Flash memory. 5 ICD RO I2C Configuration EEPROM is Disabled during boot-up. This bit reflects the current setting of the input pin I2C_BOOT_DISABLE. 1: I2C Configuration EEPROM is disabled during boot, meaning that the I2C controller has not loaded configuration data from I2C EEPROM during reset. 0: I2C Configuration EEPROM is enabled during boot, meaning that the I2C controller has loaded the configuration data from I2C EEPROM during reset. 7:6 SCS [1:0] RO System Clock Select. These bits reflect the current setting of input pin SYSCK_SEL[1:0], which configures the operating system clock frequency. 11: 100 MHz 10: Reserved for test mode 01: 50 MHz 00: 25 MHz 100 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY BLOCK_NUMBER, EXT_PROG_SRA Program SRAM On-chip Flash M_EN pin setting Memory Location 0x003FFF, Bit [6:0] Any value 0 = Shadow mode The on-chip Flash memory's lower 16K bytes disabled program code is mirrored to on-chip 16K bytes Program SRAM. 000_0001 (0x01) 000_0010 (0x02) 000_0011 (0x03) 000_0100 (0x04) 000_1111 (0x0F) 001_0000 (0x10) Bootloader Loading Time (typical) System Clock 100Mhz 50Mhz 25Mhz Time 4.1 ms Any external SRAM chips will be used for xDATA 4.3 ms memory expansion purpose only. 4.9 ms 1 = shadow mode The on-chip Flash memory's lower 16K byte program enabled and code is mirrored to on-chip 16K bytes Program System Time program code is less SRAM. Clock than 32K bytes 100Mhz 8.2 ms The lower 32K bytes range of the external SRAM chip 50Mhz 8.5 ms is used for program code shadow and will be loaded 25Mhz 9.2 ms with on-chip Flash memory's lower 32K bytes program code by Bootloader. The remaining portion of the external SRAM chip is used for xDATA memory expansion purpose. 1 = shadow mode The on-chip Flash memory's lower 16K byte program (8.2ms * 2) at enabled and code is mirrored to on-chip 16K bytes Program 100Mhz program code is less SRAM. than 64K bytes or (8.5ms * 2) at The lower 64K bytes range of the external SRAM chip 50Mhz is used for program code shadow and will be loaded with on-chip Flash memory's lower 64K bytes or (9.2ms * 2) at program code by Bootloader. The remaining portion 25Mhz of the external SRAM chip is used for xDATA memory expansion purpose. 1 = shadow mode The on-chip Flash memory's lower 16K byte program (8.2ms * enabled and code is mirrored to on-chip 16K bytes Program BLOCK_NUMBER program code is less SRAM. ) at 100Mhz than 96K/128K/.../480K The lower 96K/128K/.../480K bytes range of the or (8.5ms * bytes external SRAM chip is used for program code shadow BLOCK_NUMBER and will be loaded with on-chip Flash memory's lower ) at 50Mhz 96K/128K/.../480K bytes program code by Bootloader. The remaining portion of the external or (9.2ms * SRAM chip is used for xDATA memory expansion BLOCK_NUMBER purpose. ) at 25Mhz 1 = shadow mode The on-chip Flash memory's lower 16K byte program enabled and code is mirrored to on-chip 16K bytes Program System Time program code is less SRAM. Clock than 512K bytes 100Mhz 131.2 ms The lower 512K bytes range of the external SRAM 50Mhz 136 ms chip is used for program code shadow and will be 25Mhz 147.2 ms loaded with on-chip Flash memory's lower 512K bytes program code by Bootloader. The remaining portion of the external SRAM chip is used for xDATA memory expansion purpose. Table 15: Block Number Setting for Program Shadow Mode 101 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 4.6.2 Memory Arbiter During normal CPU core access operations, the Memory Arbiter manages the Program and xDATA memory bus access to the embedded program/data memory as well as External Memory Interface and their address conversion. During DMA access, the Memory Arbiter arbitrates the xDATA memory bus access between the CPU core and the DMA engine. When DMA Engine receives DMA requests from TOE initiated DMA, Local Bus/Digiport initiated DMA, or software initiated DMA, it will cause Memory Arbiter to generate an interrupt request to INT2, notifying CPU and software that it needs the ownership of xDATA memory bus in order to perform DMA access on xDATA memory. Within the interrupt service routine (ISR) of INT2, the CPU and software can then grant the DMA request to DMA engine through SFR register DBAR as shown below. Note that the interrupt service routine for INT2 for DMA request should always be stored within the internal Program SRAM region (0x00_0000 ~ 0x00_3FFF) to allow DMA access properly. DMA Bus Arbitration Register (DBAR, 0x9Ah) Bit Name Reset Value 7 BUS_GR 0 6 5 4 3 Reserved 00 2 1 0 BUS_REQ 0 Bit Name Access Description 0 BUS_REQ RO Bus Request. The Memory Arbiter will set this bit to "1" to request to switch the ownership of xDATA memory bus to DMA engine in order to perform DMA transfer. The types of event to trigger this bit being set include Local Bus/Digiport burst transfer, software DMA transfer, and Ethernet packet transmit/receive events. Upon DMA transfer completed, the Memory Arbiter will clear this bit automatically. Note: The interrupt service routine (ISR) of INT2 for DMA transfer in software should keep polling this bit and only after seeing this bit being cleared, then the ISR is allowed to exit. 6:1 Reserved RO 7 BUS_GR W1/R Bus Grant. The CPU or software sets this bit to 1 to grant the ownership of xDATA memory bus to DMA engine allowing the DMA transfer to start. Upon DMA transfer completed, the Memory Arbiter will clear this bit automatically. Note: 1. The interrupt for initiating DMA transfer is being assigned to INT2. Software should set INT2 to high priority to avoid other interrupt sources to intercept the DMA transfer in progress. When the CPU is servicing a high priority interrupt within an ISR while another high priority interrupt is occurring, the CPU will continue servicing the pending ISR until finished. 102 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 4.6.3 Program and Data Memory Address Mapping Figure 62 shows the program memory map when no external program SRAM is used (EXT_PROG_SRAM_EN = 0 in Program Non-Shadow Mode). On left-hand side, it represents the CPU's external program memory address space, where 0x00_0000 ~ 0x07_FFFF address space is reserved for on-chip Flash memory and 0x08_0000 ~ 0x1F_FFFF address space is used by the optional external Flash memory. On right-hand side, it represents the Flash memory's physical address space, where 0x00_0000 ~ 0x07_FFFF is seen on the on-chip Flash and 0x00_0000 ~ 0xF7_FFFF is seen on the optional external Flash memory. CPU's External Program Memory Address Flash Memory's Physical 0x17_FFFF 0x1F_FFFF Optional external Flash 1.5MB 0x00_0000 0x08_0000 0x07_FFFF 0x07_FFFF 512KB On-chip 512KB Flash 0x00_0000 0x00_0000 Figure 62: CPU Program Memory Map (EXT_PROG_SRAM_EN = 0) Figure 63 shows when external Program SRAM chips are being used for program code shadow (EXT_PROG_SRAM_EN = 1 in Program Shadow Mode), the program code size is more than 512KB (BLOCK_NUMBER > 0x10), and there are two external SRAM being used. External SRAM's Physical Address CPU's External Program Memory Address 0x1F_FFFF 0x17_FFFF 2nd external SRAM 1.5MB 0x00_0000 0x08_0000 0x07_FFFF 0x07_FFFF 512KB External 512KB SRAM 0x00_0000 0x00_0000 Figure 63: CPU Program Memory Map (EXT_PROG_SRAM_EN = 1) 103 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Figure 64 shows when an external SRAM is being used for both program code shadow (EXT_PROG_SRAM_EN = 1 in Program Shadow Mode) and xDATA memory expansion. The program code size is 256KB as an example (BLOCK_NUMBER = 0x08) and the xDATA memory expansion is also 256KB. CPU's External Program Memory Address CPU's xDATA Memory Address 0x1F_FFFF 0x1F_FFFF 1.5MB 1.5MB External SRAM's Physical Address 0x03_FFFF 256KB External 512KB SRAM 0x00_0000 0x07_FFFF 0x04 0000 256KB 0x03_FFFF 0x00_0000 On-chip 32KB 0x04_8000 0x04 7FFF 0x00_8000 0x00_7FFF 0x00_0000 Figure 64: CPU Program Memory and xDATA Memory Map (EXT_PROG_SRAM_EN = 1) Figure 65 shows when external SRAM chips are being used for both program code shadow (EXT_PROG_SRAM_EN = 1 in Program Shadow Mode) and xDATA memory expansion. The program code size is 512KB as an example (BLOCK_NUMBER = 0x10) and the xDATA memory expansion is also 512KB. CPU's xDATA Memory Address CPU's External Program Memory Address 0x1F_FFFF 0x1F_FFFF 1.5MB External SRAM's Physical Address 0x07_FFFF 2nd external SRAM 0x00_0000 0x08_0000 0x07 FFFF 0x07_FFFF 512KB 0x00_0000 1.5MB External 512KB SRAM 0x00_0000 0x08_8000 0x08 7FFF 512KB On-chip 32KB 0x00_8000 0x00_7FFF 0x00 0000 Figure 65: CPU Program Memory and xDATA Memory Map (EXT_PROG_SRAM_EN = 1) 104 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Figure 66 shows when an external SRAM is used for xDATA memory expansion (EXT_PROG_SRAM_EN = 0 in Program Non-Shadow Mode). The program code size is 512KB or less and the xDATA memory expansion is also 512KB. CPU's External Program Memory Address CPU's xDATA Memory Address 0x1F_FFFF 0x1F_FFFF 1.5MB Flash Memory's Physical Address 0x08_0000 0x07 FFFF External SRAM's Physical Address 0x07_FFFF 0x07_FFFF 512KB 0x00_0000 1.5MB On-chip 512KB Flash 0x00_0000 External 512KB SRAM 0x00_0000 0x08_8000 0x08 7FFF 512KB On-chip 32KB 0x00_8000 0x00_7FFF 0x00_0000 Figure 66: CPU Program Memory and xDATA Memory Map (EXT_PROG_SRAM_EN = 0) 4.6.4 Flash Memory Address Re-mapping for the Lower 16KB Boot Sector The lower 16KB (0x00_0000 to 0x00_3FFF) of CPU's program memory space is being defined as ROM space to the CPU and the AX11015 embeds a 16KB internal Program SRAM for storing program code of that address space. By default, the CPU program read or program write access to that 16KB space would be accessing the 16KB internal Program SRAM. When there comes the time that the software needs to read or write the lower 16KB (0x00_0000 to 0x00_3FFF) of the on-chip Flash memory, it needs a Flash memory Address Re-mapping mechanism to be able to gain access to the on-chip Flash memory instead of the on-chip 16KB Program SRAM. Following section describes proper software procedures to perform read/write access to the lower 16KB of on-chip Flash memory. 105 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY CPU's Program Memory Address On-chip Flash Memory Physical Address 0x07_FFFF 0x07_FFFF Runtime code 0x00_8000 0x00 7FFF 0x00_4000 0x00_3FFF 0x00_0000 16K~32KB 16K Boot Sector Address mapping directly Program code mirrored 16K~32KB 16KB internal Prog. SRAM 0x00_8000 0x00 7FFF 0x00_4000 0x00_3FFF 0x00_0000 Figure 67: Flash Memory Address Without Re-Mapping, FARM bit = 0 (in SFR register CSREPR.2) (default) On-chip Flash Memory Physical Address 0x07_FFFF CPU's Program Memory Address 0x07_FFFF Runtime code 0x00_8000 0x00 7FFF 0x00_4000 0x00_3FFF 0x00_0000 16K~32KB 16K Boot Sector Disabled temporarily Flash address re-mapping Program code mirrored 16K~32KB 16KB internal Prog. SRAM 0x00_8000 0x00 7FFF 0x00_4000 0x00_3FFF 0x00_0000 Figure 68: Flash Memory Address Re-Mapping Enabled, FARM bit = 1 (in SFR register CSREPR.2) 106 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Case 1: Programming procedure to read the lower 16KB of on-chip Flash memory (only applies to Program Non-Shadow mode, EXT_PROG_SRAM_EN = 0) Step 1: Software first writes FARM bit = 1 (CSREPR.2, 0x8F), to enable Flash memory address re-mapping mechanism. Step 2: Reading any program address space 16K~32K (0x00_4000~0x007FFF) will be remapped to the 0K~16K (0x00_0000~0x00_3FFF) address space of the Flash memory. Therefore, the memory content of lower 16KB of the on-chip Flash memory can now be accessed. Note that the accessing of the 16KB~32KB address space of on-chip Flash memory is temporarily disabled after step 1. Step 3: After done with accessing the lower 16KB of on-chip Flash memory, the software then writes FARM bit = 0 (CSREPR.2), to disable Flash memory address re-mapping mechanism. Now the access of program address space 16KB~32KB would revert back to the same address space of the on-chip Flash memory as usual, and the accessing of 0K~16K (0x00_0000~0x00_3FFF) address space of the Flash memory is disabled again. Case 2: Programming procedure to write the lower 16KB of on-chip Flash memory (only applies to Program Non-Shadow mode, EXT_PROG_SRAM_EN = 0) Step 1: Software first writes PWE bit = 1 (PCON.4, 0x87), to enable program write in CPU. Step 2: Software writes FARM bit = 1 (CSREPR.2, 0x8F), to enable Flash memory address re-mapping mechanism. Now accessing the 0K~16K (0x00_0000~0x00_3FFF) address space of the Flash memory would come from software accessing the program address space 16K~32K (0x00_4000~0x007FFF). Step 3: Programming sequence for performing "Sector Erase" commands for on-Flash memory: 1. Write (0x4000 + 0x555) = 0xAA 2. Write (0x4000 + 0x2AA) = 0x55 3. Write (0x4000 + 0x555) = 0x80 4. Write (0x4000 + 0x555) = 0xAA 5. Write (0x4000 + 0x2AA)= 0x55 6. Write (0x4000 + 0x000) = 0x30 7. Repeatedly read (0x4000 + 0x3FFF). If equal to 0xFF, the Sector Erase command is completed. Step 4: Programming sequence for performing "Byte Program" commands for on-Flash memory: 1. Write (0x4000 + 0x555) = 0xAA 2. Write (0x4000 + 0x2AA) = 0x55 3. Write (0x4000 + 0x555) = 0xA0 4. Write (0x4000 + PA) = PD (where PA: any 0~16KB of on-chip Flash memory address to be programmed, PD: write data) 5. Repeatedly read (0x4000 + PA). If equal to PD, then the "Byte Program" command is completed. Step 5: Software writes FARM bit = 0 (CSREPR.2), to disable Flash memory address re-mapping. Step 6: Software writes PWE bit = 0 (PCON.4), to disable program write in CPU. 107 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Case 3: Programming procedure to write 16KB above address space of on-chip Flash memory (only applies to Program Non-Shadow mode, EXT_PROG_SRAM_EN = 0) Step 1: Software first writes PWE bit = 1 (PCON.4, 0x87), to enable program write in CPU. Step 2: Software writes FARM bit = 1 (CSREPR.2, 0x8F), to enable Flash memory address re-mapping mechanism. Step 3: Programming sequence for enabling "Byte Program" command for on-Flash memory: 1. Write (0x4000 + 0x555) = 0xAA 2. Write (0x4000 + 0x2AA) = 0x55 3. Write (0x4000 + 0x555) = 0xA0 Step 4: Software writes FARM bit = 0 (CSREPR.2), to disable Flash memory address re-mapping mechanism. Step 5: Now perform the actual byte write command. 1. Write PA = PD (where PA: any 16KB above Flash memory address to be programmed, PD: write data) 2. Repeatedly read PA. If equal to PD, then the Program command is completed. Step 6: Software writes PWE bit = 0 (PCON.4), to disable program write in CPU. 4.6.5 Flash Memory Access in Program Code Shadow Mode When an external program SRAM is being used for program code shadow purpose, in that case, the CPU program read or program write access to 16KB above (0x00_4000 and above) address space would be the accessing of the external SRAM. When there comes the time that the software needs to read or write the 16KB above address space of the on-chip Flash memory, it needs a Flash memory Address Un-shadowed mechanism to be able to gain access to the on-chip Flash memory instead of the external SRAM. Case 1: Programming procedure to read the lower 16KB of on-chip Flash memory (only applies to shadow mode, EXT_PROG_SRAM_EN = 1) Same as the case 1 in Program Non-Shadow mode, except that in step 1 the software first changes WTST to Non-Shadow Mode value, then writes FARM bit = 1 (CSREPR.2) and FAES bit = 1 (CSREPR.3), to temporarily enable Flash memory access and disable the external Program SRAM access. When done, in step 3 the software should clear both FARM and FAES bits in CSREPR register, and then revert the WTST back to Program Shadow Mode value. Case 2: Programming procedure to write the lower 16KB of on-chip Flash memory (only applies to shadow mode, EXT_PROG_SRAM_EN = 1) Same as the case 2 in Program Non-Shadow mode, except that in step 2, the software first changes WTST to Non-Shadow Mode value, then writes FARM bit = 1 (CSREPR.2) and FAES bit = 1 (CSREPR.3), to temporarily enable Flash memory access and disable the external Program SRAM access. When done, in step 5 the software should clear both FARM and FAES bits in CSREPR register, and then revert the WTST back to Program Shadow Mode value. 108 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Case 3: Programming procedure to write 16KB above address space of on-chip Flash memory (only applies to shadow mode, EXT_PROG_SRAM_EN = 1) Step 1: Software first writes PWE bit = 1 (PCON.4), to enable program write in CPU. Step 2: Software changes WTST to Non-Shadow Mode value, writes FARM bit = 1 (CSREPR.2) and FAES bit = 1 (CSREPR.3), to enable Flash memory address re-mapping mechanism, and temporarily enable Flash memory access and disable the external Program SRAM access Step 3: Programming sequence for enabling "Byte Program" command for on-Flash memory: 1. Write (0x4000 + 0x555) = 0xAA 2. Write (0x4000 + 0x2AA) = 0x55 3. Write (0x4000 + 0x555) = 0xA0 Step 4: Software writes FARM bit = 0 (CSREPR.2), to disable Flash memory address re-mapping mechanism. Step 5: Now perform the actual byte write command. 1. Write PA = PD (where PA: any 16KB above of Flash memory address to be programmed, PD: write data) 2. Repeatedly read PA. If equal to PD, the Program command is completed. Step 6: Software writes FAES bit = 0 (CSREPR.3), to disable Flash memory access and re-enable the external Program SRAM access in program code shadow mode, and then revert the WTST back to Program Shadow Mode value. Step 7: Software writes PWE bit = 0 (PCON.4), to disable program write in CPU. 4.6.6 Flash Programming Controller When asserting chip reset (via RST_N pin) to AX11015 and also asserting "BURN_FLASH_EN" pin to high, the AX11015 will enter into Flash memory programming enabled mode. Upon enabled, the Flash programming controller can start receiving command packets from Flash Programming utilities through the RXD0 pin of UART0, decoding the packets, passing the decoded command to perform on-chip and off-chip Flash memory erase/programming tasks, and then returning the acknowledgement packets with the result back to Flash Programming utilities running on a PC. The Flash programming controller is responsible for generating the waveform for Flash memory access. The Flash programming speed via UART0 can support two speeds, 115.2 Kbps (BURN_FLASH_912K pin set to low) and 921.6Kbps (BURN_FLASH_912K pin set to high). Note that during Flash programming enabled mode, the internal CPU core is not running. Therefore, after Flash programming is completed, another chip reset (via RST_N pin) should be applied to AX11015 without asserting "BURN_FLASH_EN" pin to allow CPU to start running normally. 109 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 4.7 DMA Engine As shown in figure below, the DMA engine supports direct External Data (xDATA) Memory read and write access without CPU intervention for the TCP/IP Offload Engine (TOE), Local Bus Interface (LBI) and Digiport, as well as bulk data copy for software DMA. 1T 80390 CPU Core Software DMA Controller TOE Memory Arbiter Ethernet MAC DMA Arbiter Local Bus / Digiport xDATA Memory Figure 69: DMA Engine Block Diagram 4.7.1 DMA Transfers for Ethernet Packet Receive and Transmit Packet Receive During normal Ethernet packet receive process, the Ethernet MAC shall forward the received packets from its receive buffer to TOE receive block which then moves and stores the received packets into xDATA memory via DMA write access. The received packets will be stored in "Receive Packet Buffer Ring" region of xDATA memory being defined by software during initialization. See section 4.14 for more detailed description. During this process, the DMA arbiter will receive DMA request from TOE receive block and then it will trigger the Memory Arbiter to generate an interrupt to CPU on INT2 to notify CPU the pending DMA request from TOE receive block and waiting for CPU to grant it. After CPU grants it, if the received packet size is more than 256 bytes, it will be executed in several transfers, with maximum of 256 bytes per transfer. For example, as shown in Figure 71, for a 1500 bytes Ethernet packet, it will take up to 6 DMA transfers to finish moving it into "Receive Packet Buffer Ring" region of xDATA memory. The gap between each transfer is programmable by TL4DGR register, see section 4.14 for more details. In DMA write access case, each byte will take (CKCON[2:0] +2) operating system clocks to write into xDATA memory, where CKCON is SFR register offset 0x8E. 110 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Packet Transmit In normal Ethernet packet transmit process, the software first prepares the to-be-transmitted packets and stores them in the "Transmit Packet Buffer Ring" region of xDATA memory being defined by software during initialization. The software then configures the TL4CMR [SP] bit to initiate the packet transmit process in TOE transmit block for moving packets to Ethernet MAC transmit buffer. Please Refer to section 4.14 for more details. Now the TOE transmit block will send DMA request to DMA arbiter which again will trigger the Memory Arbiter to generate an interrupt to CPU on INT2 to notify CPU the pending DMA request from TOE transmit block and waiting for CPU to grant it. After CPU grants it, if the to-be-transmitted packet size is more than 256 bytes, it will be executed in several transfers, with maximum of 256 bytes per transfer. For example, for a 1518 bytes Ethernet packet, it will take up to 6 DMA transfers to finish moving it out of "Transmit Packet Buffer Ring" region of xDATA memory. The gap between each transfer is programmable by TL4DGR register. During this DMA read access case, each byte will take (CKCON[2:0] +2) operating system clocks to read from xDATA memory, where CKCON is SFR register offset 0x8E. 4.7.2 DMA Transfers for Local Bus and Digiport Burst Read and Write In Local Bus Interface (LBI) master mode, the software can perform burst read from the external local bus devices and store the read-data in xDATA memory via DMA write access, or it can perform burst write to external local bus devices by reading the write-data from xDATA memory via DMA read access. When the software initiates a burst read or burst write access on LBI via SFR register LCR (0xA2), the LBI will send the DMA request to DMA arbiter which will trigger the Memory Arbiter to generate an interrupt to CPU on INT2 to notify CPU the pending DMA request from LBI and waiting for CPU to grant it. After CPU grants it, if the burst read/write size is over 32 bytes, it will be executed in several transfers, with maximum of 32 bytes per transfer. For example, for a 256 bytes burst read on LBI, it would take 8 DMA write transfer to complete. In Digiport parallel or Digiport SPI streaming video receive mode, the software can perform burst read from external STv0676 or STv0684 chips and store the streaming video data in xDATA memory via DMA write access. When the software initiates a burst read access on Digiport parallel or Digiport SPI interface via SFR register LCR (0xA2), the Digiport controller will send the DMA request to DMA arbiter which will trigger the Memory Arbiter to generate an interrupt to CPU on INT2 to notify CPU the pending DMA request from Digiport controller and waiting for CPU to grant it. After CPU grants it, if the burst read size is over 32 bytes, it will be executed in several transfers, with maximum of 32 bytes per transfer. For example, for a 256 bytes burst read on LBI, it would take 8 DMA write transfer to complete. In LBI slave mode, the LBI can perform receiving burst data (during external system CPU initiating a burst write access on LBI) and store them in xDATA memory via DMA write access, or it can perform outputting burst data (during external system CPU initiating a burst read access on LBI) by reading out data from xDATA memory via DMA read access. When external system CPU initiates burst read or burst write access via CR register (0x0A, seen from LBI slave mode), the Local Bus Slave controller will send the DMA request to DMA arbiter which will trigger the Memory Arbiter to generate an interrupt to CPU on INT2 to notify CPU the pending DMA request from LBI and waiting for CPU to grant it. Each burst transfer in Local Bus slave mode can be up 32 bytes, therefore, the DMA transfer size is also up to 32 bytes. 4.7.3 Software DMA The software DMA can perform bulk data copy from one region of xDATA memory to another region in a timely manner, based on software configuration. This hardware based software DMA controller can greatly reduce the time spending in bulk data movement very often needed in network protocol stack processing, and, hence, help achieve better performance on micro-controller computing power. If software DMA transfer size is more 128 bytes, it will be executed in several transfers, with maximum of 128 bytes per transfer. For example, to copy 512 bytes data from one region to another region of xDATA memory, it will take 4 DMA transfers to complete. The gap between each transfer is programmable by TL4DGR register. When software DMA transfer involves copying one Ethernet packet from the "Receive Packet Buffer Ring (RPBR)" to the software's application buffer area or from the software's application buffer area to the "Transmit Packet Buffer Ring (TPBR)", in that case, the software DMA controller has been designed with "ring-aware" architecture and can deal with the ring structure of RPBR and TPBR automatically, particularly, the buffer ring wrap-around issue. 111 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY For example, when copying a packet from RPBR to software's application buffer area, if the packet data happens to across the ring boundary, (i.e., the packet data starts at the last few pages of the ring and wraps around to the first few pages of the ring), the software DMA controller will automatically make sure the packet data is retrieved from the ring structure of RPBR without having the software to worry about the packet crossing RPBR ring boundary issue and having to perform this software DMA in two times to take care of the boundary issue. The same applies to the case when the software needs to move an Ethernet packet from software's application buffer area into TBPR, and software doesn't have to worry about packet data crossing TPBR ring boundary. However, please note that the software DMA controller do not have the knowledge of data structure of software's application buffer area, therefore, it cannot deal with the ring boundary crossing issue for software's application buffer area. It's software's responsibility to cover its buffer area wrap-around scenario when software initiates such DMA transfer. Because for non-RPBR and non-TPBR types of DMA transfers, the software DMA controller can only increase DMA source address or target address linearly after each byte transferred, therefore, it can not adjust these address for the ring type of data structure in software's application buffer area in xDATA memory. Software application buffer area RPBR (256 byte per page) MAC-RX Buffer Ring (256 byte per page) 3 4 4 3 1 1 2 2 Software DMA: copying one packet (4 pages long) from RPBR into software's buffer area TOE packet receive DMA: moving one packet (4 pages long) from MAC-RX into RPBR Figure 70: Ring-aware Software DMA Example Software DMA and Millisecond Timer Related SFR Register Map Address 0x9B 0x9C 0x94 Name DCIR Description DMA Command Index Register is used to indicate the address of to-be-accessed register listed in Table 17. DDR DMA Data Register is used to read data from or write data to the specific register provided by DCIR. SDSTSR Software DMA and Millisecond Timer Status Register Table 16: Software DMA and Millisecond Timer Related SFR Register Map DMA Command Index Register (DCIR, 0x9B) 7 Bit Name Reset Value 6 5 4 3 2 1 RI 0x00 Bit Name Access Description 112 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights 0 AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY [7:0] RI WO Register Index. Value Description 0x00~0x0f Indicate to access which of the Software DMA and Millisecond Timer registers listed in Table 17. 0xff Command Abort DMA Data Register (DDR, 0x9C) 7 Bit Name Reset Value 6 5 4 3 2 1 0 DR 0x00 Bit Name Access [7:0] DR Description Data Register is used to write data to or read data from Software DMA and Millisecond R/W Timer registers. Software DMA and Millisecond Timer Status Register (SDSTSR, 0x94) 7 Bit Name Reset Value 6 5 4 3 2 Reserved 1 STT 0 SDC 0x00 Bit Name Access 0 SDC CR 1 STT CR 7:2 Reserved Description The Software DMA transfer is Completed. When reading "1", this bit indicates that the software DMA transfer requested via SDCSR has been completed. The Millisecond Timer has Timed out. When reading "1", this bit indicates that the Millisecond Timer has reached the timeout value being set in MSTR register. Software DMA and Millisecond Timer Register Indirect Access Method Software shall use indirect access method through DCIR and DDR registers to read or write the Software DMA and Millisecond Timer register listed in Table 17 below. Read a register from Software DMA and Millisecond Timer: Step 1. Write DCIR: Software indicates the Software DMA or Millisecond Timer register address to be accessed as the data and write it to the SFR register DCIR. Step 2. Read DDR: Software then read SFR register DDR. The data read from DDR is the Software DMA or Millisecond Timer register data indicated in step 1. Keep reading from DDR if the Software DMA or Millisecond Timer registers have more than one byte, in that case, the first byte being read back is LSB byte. Write a register to Software DMA and Millisecond Timer: Step 1. Write DDR: Software writes the data you want to write into Software DMA or Millisecond Timer registers to the SFR register DDR. Keep writing to DDR if the Software DMA or Millisecond Timer registers have more than one byte, in that case, the first byte being written should be LSB byte. Step 2. Write DCIR: After writing Software DMA or Millisecond Timer register data to DDR, software then indicates the target Software DMA or Millisecond Timer register address as data and write it to DCIR. 113 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Software DMA and Millisecond Timer Register Map Address 0x00 0x02 0x06 0x0A 0x0C Register Name SDCSR SDSSAR SDTSAR SDBCR MSTR Description Software DMA Command Status Register Software DMA Source Starting Address Register (24 bits) Software DMA Target Starting Address Register (24 bits) Software DMA Byte Count Register (16 bits) Millisecond Timer Register (10 bits) Table 17: Software DMA and Millisecond Timer Register Map Software DMA Command Status Register (SDCSR, 0x00) Bit Name Reset Value 7 6 EI_SDC Reserved 00 5 TAIT 0 4 SAIR 0 3 Reserved 0 2 DMAERR 0 1 FS 0 0 GO 0 Bit Name 0 GO 1 2 Access Description W1/R Software sets GO bit to "1" to initiates the "software DMA transfer" which facilitates copying a block of data from the specified range of xDATA Memory to another specified range of xDATA Memory. This bit will remain "1" while the DMA transfer is still in progress and will be cleared automatically after the requested DMA transfer is completed or stopped by software via FS bit. Note: Software can only write "1" to this bit and can't write "0". FS W1/R Force to Stop the software DMA transfer in progress. This bit will remain "1" while the software DMA controller is trying to stop the DMA transfer and will be cleared automatically after software DMA controller is completely stopped. DMAERR CR DMA Error indication. When reading back a "1", it indicates that the requested software DMA has encountered error and can't be finished. The condition that causes DMA error could be that, for example: - The value of SDBCR register = 0 byte - Or the value of target memory address, SDTSAR register is equal to the value of source memory address, SDSSAR register - Or the memory address range of target (SDTSAR + SDBCR) is overlapping with the memory address range of the source (SDSSAR + SDBCR). - If SAIR bit is set and SDSSAR is not in the range of RSPP and REPP. - If TAIT bit is set and SDTSAR is not in the range of TSPP and TEPP. 3 4 Reserved SAIR 5 TAIT 6 7 Reserved EI_SDC W1/R Source Address Is in RPBR. Software sets SAIR to "1" at the same time as setting GO bit to "1" to indicate that the requested DMA involves copying packet data from RPBR to the target location. This way the software DMA controller will base on the ring structure of RPBR to locate the source data and will wrap around the ring of RPBR when the last page of the ring is hit. This bit will remain "1" while the DMA transfer is still in progress and will be cleared automatically after the requested DMA transfer is completed or stopped by software via FS bit. W1/R Target Address Is in TPBR. Software sets TAIT to "1" at the same time as setting GO bit to "1" to indicate that the requested DMA involves copying packet data from source location to TPBR. This way the software DMA controller will base on the ring structure of TPBR to write the data and will wrap around the ring of TPBR when the last page of the ring is hit. This bit will remain "1" while the DMA transfer is still in progress and will be cleared automatically after the requested DMA transfer is completed or stopped by software via FS bit. R/W Enable Interrupt whenever the requested Software DMA is Completed. The interrupt is asserted on INT 5. 114 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Software DMA Source Starting Address Register (SDSSAR, 0x02) Bit Name 7 6 5 4 3 S_ADDR 0 S_ADDR 1 S_ADDR 2 0x00_0000 Reset Value 2 1 0 Bit Name Access Description 7:0 S_ADDR 0 R/W The Source starting Address for software DMA transfer. This is the 24-bit starting 15:8 S_ADDR 1 address of the source memory block to be copied from in CPU's xDATA Memory. 23:16 S_ADDR 2 Software DMA Target Starting Address Register (SDTSAR, 0x06) Bit Name 7 6 5 4 3 T_ADDR 0 T_ADDR 1 T_ADDR 2 0x00_0000 Reset Value Bit Name 7:0 T_ADDR 0 15:8 T_ADDR 1 23:16 T_ADDR 2 2 1 0 Access Description R/W The Target starting Address for software DMA transfer. This is the 24-bit starting address of target memory block to be copied to in CPU's xDATA Memory. Software DMA Byte Count Register (SDBCR, 0x0A) Bit Name 7 6 5 4 3 B_CNT 0 B_CNT 1 0x0000 Reset Value 2 1 0 Bit Name Access Description 7:0 B_CNT 0 R/W The block of data in terms of bytes the software DMA transfer is to be copied from source 15:8 B_CNT 1 memory address to target memory address. Note that if the byte count is greater than 128 bytes, then the software DMA transfer will be executed in separate transfer with 128 bytes per transfer until all the requested bytes are copied to the target memory block. Millisecond Timer Register (MSTR, 0x0C) Bit Name 7 EI_STT Reset Value 6 5 4 3 2 MS_TMR 0 Reserved RS_TMR ST_TMR Reserved 0x0001 1 0 MS_TMR 1 Bit 7:0 9:8 Name Access Description MS_TMR 0 R/W Millisecond Timer Timeout value. Each count is about 1 msec in time. For example, MS_TMR 1 0x001 = 1 msec. 0x002 = 2 msec. The maximum timeout is 1024 msec. Whenever the Million-Second Timer reaches the timeout value being set here, the timer will reset to 0 to restart the timer all over again. And if the EI_STT register is enabled, it will also generate an interrupt on INT5 to CPU. 11:10 Reserved 12 ST_TMR R/W Setting the ST_TMR bit to "1" to enable the Millisecond Timer to start counting. 115 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 13 RS_TMR 14 15 Reserved EI_STT R/W1 Setting the RS_TMR bit to "1"to reset the Millisecond Timer to 0 and this bit will then be cleared to "0" by hardware automatically. R/W R/W Enable Interrupt whenever the Millisecond Timer reaches the timeout value being set in MS_TMR 1,0 register. The interrupt is asserted on INT 5. Software DMA Programming Procedure Software needs to use indirect access procedure to read or write the specific Software DMA or Millisecond Timer registers through SFR registers, DCIR (0x9B) and DDR (0x9C). Following describes how to initiate a Software DMA transfer. 1. Software first writes to DDR register with data of S_ADDR 0 for SDSSAR. 2. Software writes to DDR register with data of S_ADDR 1 for SDSSAR. 3. Software writes to DDR register with data of S_ADDR 2 for SDSSAR. 4. Software writes to DCIR register with data of 0x02 (the address of SDSSAR) ----------------------------------------------------------------------------------------------------5. Software writes to DDR register with data of T_ADDR 0 for SDTSAR. 6. Software writes to DDR register with data of T_ADDR 1 for SDTSAR. 7. Software writes to DDR register with data of T_ADDR 2 for SDTSAR. 8. Software writes to DCIR register with data of 0x06 (the address of SDTSAR) ----------------------------------------------------------------------------------------------------9. Software writes to DDR register with data of B_CNT 0 for SDBCR. 10. Software writes to DDR register with data of B_CNT 1 for SDBCR. 11. Software writes to DCIR register with data of 0x0A (the address of SDBCR) ----------------------------------------------------------------------------------------------------12. Software then writes to DDR register with data of SDCSR (e.g. set GO = 1, FS = 0). 13. Software then writes to DCIR register with data of 0x00 (the address of SDCSR) ----------------------------------------------------------------------------------------------------14. Now software can wait for a while or wait for the interrupt to verify if the requested software DMA transfer is completed by software DMA controller or not. 15. Software first writes to DCIR register with data of 0x00 (the address of SDCSR). 16. Software then reads from DDR register with data of SDCSR. If the GO bit is still "1", then the DMA operation is still in progress. Until software reads "0" on GO bit, it indicates that the DMA operation is completed. ----------------------------------------------------------------------------------------------------17. If software reads back a "1" on DMAERR bit, that means that an error has occurred during the software DMA transfer. At this point, the software has to force to stop the unfinished DMA by setting the FS bit to "1" in order to clear the GO bit. 18. Software then writes to DDR register with data of SDCSR (e.g. set FS = 1). 19. Software then writes to DCIR register with data of 0x00 (the address of SDCSR) 116 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 4.7.4 DMA Arbitration The DMA arbiter arbitrates the simultaneous DMA requests that come from Ethernet packet receive, Ethernet packet transmit, Local Bus/Digiport burst read or burst write, and software DMA. If Local Bus, TOE, and software DMA all request DMA transfers at the same time, the Local Bus's DMA request will be granted first. Also, the Local Bus burst read/write transfer will always take higher priority over software DMA transfer or DMA transfers for Ethernet packet transmit/receive, which means it can intercept the later two cases when all three DMA requests are pending at the same. For example, if the software DMA transfer is in progress, and the DMA arbiter later also receives the Local Bus DMA request for burst read/write transfer, it will put the software DMA on-hold and switch the CPU's xDATA memory bus ownership from software DMA to Local Bus to allow Local Bus DMA to start immediately. Note that each Local Bus DMA transfer is only up to 32 bytes in a chunk. When Local Bus DMA request is absent, among software DMA, DMA for Ethernet packet receive, DMA for Ethernet packet transmit, the arbitration rules are as follows: z Software DMA transfer has priority over DMA transfers for Ethernet packet receive and packet transmit. z Between DMA transfer for packet receive and packet transmit, it is round-robin fashion. DMA Gap 256 B DMA Gap DMA Gap 256 B 256 B DMA Gap (setting by TL4DGR register) DMA Gap 256 B 256 B 220 B Time Figure 71: Example: Ethernet Packet Receive DMA Transfer Only (receiving a 1500-byte packet) DMA Gap RX TX 256 B DMA Gap DMA Gap 256 B 256 B DMA Gap DMA Gap (setting by TL4DGR register) 256 B 256 B 256 B Time Figure 72: Example: Ethernet Packet Receive and Transmit DMA Transfers Simultaneously (receiving and transmitting a 1500-byte packet) 117 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY DMA Gap RX TX DMA Gap DMA Gap DMA Gap DMA Gap (setting by TL4DGR register) 256 B 256 B 256 B 256 B SW 128 B 72 B Software initiates software DMA transfer at this point Time Resume RX/TX DMA after software DMA finished. Figure 73: Example: Ethernet Packet Receive and Transmit and software DMA Transfers Simultaneously (receiving and transmitting a 1500-byte packet, and software copying a 200-bytes data block) 118 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 4.8 Interrupt Controller The interrupt controller of AX11015 supports 2 external interrupt pins, INT0 and INT1, each having two levels of interrupt priority control. They can be in high or low-level priority group (set via SFR register IP and EIP). The INT0 and INT1 external interrupt pins can be either low-level trigger or falling-edge trigger. Also, the interrupt controller supports various interrupt requests internal to the AX11015, again each having two levels of interrupt priority control. The interrupts flag summary is as shown in Table 18 below. Each interrupt vector can be individually enabled or disabled by setting or clearing a corresponding bit in the SFR register IE (0xA8) and EIE (0xE8). The IE contains global interrupt system disable/enable bit called EA bit (IE.7), which has to be set in order to enable individual interrupt requests listed in Table 18. Function Interrupt Flag IE0 The external interrupt input pin, INT0 Active Flag resets Vector Natural (level/edge) priority Low/Falling Hardware 0x03 1 TF0 The internal Timer 0 interrupt request Hardware 0x0B 2 IE1 The external interrupt input pin, INT1 Low/Falling Hardware 0x13 3 TF1 The internal Timer 1 interrupt request - Hardware 0x1B 4 TI0 & RI0 The internal UART 0 interrupt request - Software 0x23 5 The internal Timer 2 interrupt request - Software 0x2B 6 TI1 & RI1 The internal UART 1 interrupt request - Software 0x33 7 TF2 - INT2F The internal DMA transfer interrupt request for TOE/LBI/ software DMA mode, please set to high priority - Hardware 0x3B 8 INT3F The internal programmable counter array interrupt request - Hardware 0x43 9 INT4F The internal peripheral interrupt request for TOE, MAC/PHY, LBI, I2C, SPI, 1-Wire, UART2, etc. - Hardware 0x4B 10 INT5F The internal software DMA complete and millisecond timer timeout interrupt - Software 0x53 11 INT6F The wake-up interrupt request (resume from CPU STOP mode) - Software 0x5B 12 WDIF Internal watchdog interrupt - Software 0x63 13 Table 18: Interrupts Flag Summary 4.8.1 Interrupt Controller SFR Register Map Address 0xA8 0xB8 0x88 0x98 0xC0 0xE8 0xF8 0x91 0x9E 0x9F Name IE IP TCON SCON0 SCON1 EIE EIP EIF PISS1R PISS2R Description Interrupt Enable Register Interrupt Priority Register Timer 0,1 Configuration Register UART 0 Configuration Register UART 1 Configuration Register Extended Interrupt Enable Register Extended Interrupt Priority Register Extended interrupt Flag Register Peripheral Interrupt Status Summary 1 Register Peripheral Interrupt Status Summary 2 Register Table 19: Interrupt Controller SFR Register Map 119 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Interrupt Enable Register (IE, 0xA8) Bit Name Reset Value Bit Name 7 EA 6 ES1 5 ET2 4 ES0 3 ET1 2 EX1 1 ET0 0 EX0 2 PX1 1 PT0 0 PX0 0x00 Access 0 EX0 R/W 1 ET0 R/W 2 EX1 R/W 3 ET1 R/W 4 ES0 R/W 5 ET2 R/W 6 ES1 R/W 7 EA R/W Description Enable INT0 interrupt. 1: Enabled. 0: Disabled. Enable Timer 0 interrupt. 1: Enabled. 0: Disabled. Enable INT1 interrupt. 1: Enabled. 0: Disabled. Enable Timer 1 interrupt. 1: Enabled. 0: Disabled. Enable UART0 interrupt. 1: Enabled. 0: Disabled. Enable Timer 2 interrupt. 1: Enabled. 0: Disabled. Enable UART1 interrupt. 1: Enabled. 0: Disabled. Enable global interrupt. 1: Enabled. 0:Disabled. Interrupt Priority Register (IP, 0xB8) Bit Name Reset Value Bit Name 7 Reserved 6 PS1 5 PT2 4 PS0 3 PT1 0x00 Access 0 PX0 R/W 1 PT0 R/W 2 PX1 R/W 3 PT1 R/W 4 PS0 R/W 5 PT2 R/W Description INT0 priority level control. 1: High level. 0: Low level. Timer 0 priority level control. 1: High level. 0: Low level. INT1 priority level control. 1: High level. 0: Low level. Timer 1 priority level control. 1: High level. 0: Low level. UART0 priority level control. 1: High level. 0: Low level. Timer 2 priority level control. 120 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 6 PS1 R/W 7 Reserved 1: High level. 0: Low level. UART1 priority level control. 1: High level. 0: Low level. In TCON register, all of bits that generate interrupts can be set or cleared by software, with the same result as if they had been set or cleared by hardware. That is, interrupts can be generated or pending interrupts can be cancelled by software. The only exceptions are the request flags IE0 bit (TCON.1) and IE1 bit (TCON.3). If the external interrupt pin INT0 or INT1 is programmed to be level activated, IE0 and lE1 are controlled by the external source via pin INT0 and INT1, respectively. Thus, writing a one to these bits will not set the request flag IE0 and/or lE1. The same exception also applies to INT5F and INT6F. Timer 0,1 Register (TCON, 0x88) 7 TF1 Bit Name Reset Value 6 TR1 5 TF0 4 TR0 3 IE1 2 IT1 1 IE0 0 IT0 0x00 Bit Name Access 0 IT0 R/W 1 IE0 RO 2 IT1 R/W 3 IE1 RO 4 TR0 R/W 5 TF0 R/W 6 TR1 R/W 7 TF1 R/W Description INT0 level or edge sensitivity. 1: Edge triggered. 0: Level triggered. INT0 interrupt flag. This bit is cleared by hardware automatically when CPU branches to interrupt routine. INT1 level or edge sensitivity. 1: Edge triggered. 0: Level triggered. INT1 interrupt flag. This bit is cleared by hardware automatically when CPU branches to interrupt routine. Timer 0 run control bit. 1: Enabled. 0: Disabled. Timer 0 interrupt (overflow) flag. This bit is cleared by hardware when CPU branches to interrupt routine. Timer 1 run control bit. 1: Enabled. 0: Disabled. Timer 1 interrupt (overflow) flag. This bit is cleared by hardware when CPU branches to interrupt routine. UART0 Configuration Register (SCON0, 0x98) 7 SM00 Bit Name Reset Value 6 SM01 5 SM02 4 REN0 3 TB08 2 RB08 1 TI0 0x00 Bit Name Access 0 RI0 1 TI0 0 RI0 Description UART0 receive interrupt flag, set by hardware after completion of a serial reception. Must be R/W cleared by software. UART0 transmit interrupt flag, set by hardware after completion of a serial transfer. Must be R/W cleared by software. 121 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 2 RB08 R/W 3 TB08 R/W 4 5 6 7 REN0 SM02 SM01 SM00 R/W R/W R/W R/W In Modes 2 and 3 it is the 9th data bit received. In Mode 1, if SM02 is 0, RB08 is the stop bit. In Mode 0 this bit is not used. The 9th transmitted data bit in Modes 2 and 3. Set or cleared by the CPU, depending on the function it performs (parity check, multiprocessor communication etc.). If set, enables serial reception on UART0. Cleared by software to disable reception. Enables a multiprocessor communication feature. Sets baud rate. Sets baud rate. UART1 Configuration Register (SCON1, 0xC0) 7 SM10 Bit Name Reset Value Bit Name 6 SM11 5 SM12 4 REN1 3 TB18 2 RB18 1 TI1 0 RI1 0x00 Access 0 RI1 R/W 1 TI1 R/W 2 RB18 R/W 3 TB18 R/W 4 5 6 7 REN1 SM12 SM11 SM10 R/W R/W R/W R/W Description UART1 receive interrupt flag, set by hardware after completion of a serial reception. Must be cleared by software. UART1 transmit interrupt flag, set by hardware after completion of a serial transfer. Must be cleared by software. In Modes 2 and 3 it is the 9th data bit received. In Mode 1, if SM12 is 0, RB18 is the stop bit. In Mode 0 this bit is not used. The 9th transmitted data bit in Modes 2 and 3. Set or cleared by the CPU, depending on the function it performs (parity check, multiprocessor communication etc.). If set, enables serial reception on UART1. Cleared by software to disable reception. Enables a multiprocessor communication feature. Sets baud rate. Sets baud rate. Extended Interrupt Enable Register (EIE, 0xE8) 7 Bit Name Reset Value 6 Reserved Bit Name Access 0 ENIT2 R/W 1 ENIT3 R/W 2 EINT4 R/W 3 EINT5 R/W 4 EINT6 R/W 5 EWDI 4 3 EINT6 EINT5 0x00 2 EINT4 1 EINT3 0 EINT2 Description Enable INT2 interrupt for the DMA transfer interrupt request, which comes from the Memory Arbiter for the TOE/LBI/software DMA mode. 1: Enabled. 0: Disabled. Enable INT3 interrupt for the programmable counter array interrupt request. 1: Enabled. 0: Disabled. Enable INT4 interrupt for the peripheral interrupt requests, which may be generated by TOE, MAC/PHY, LBI, I2C, SPI, 1-Wire, and UART2 modules. 1: Enabled. When enabled, the summary of these peripheral interrupts are given in SFR register, PISS1R (0x9E) and PISS2R (0x9F). 0: Disabled. Enable INT5 interrupt for the internal software DMA complete and millisecond timer timeout interrupt. 1: Enabled. 0: Disabled. Enable INT6 interrupt for the wake-up interrupt request (when resuming from CPU STOP mode). 1: Enabled. 122 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 5 EWDI 0: Disabled. Enable Watchdog interrupt. R/W 1: Enabled. 0: Disabled. 7:6 Reserved Extended Interrupt Priority Register (EIP, 0xF8) 7 Bit Name Reset Value 6 Reserved Bit Name Access 0 PINT2 R/W 1 PINT3 R/W 2 PINT4 R/W 3 PINT5 R/W 4 PINT6 R/W 5 PWDI R/W 5 PWDI 4 3 PINT6 PINT5 0x00 2 PINT4 1 PINT3 0 PINT2 Description INT2 priority level control for DMA transfer interrupt request for TOE/LBI/software DMA mode. Please set to high priority. 1: High level. 0: Low level. INT3 priority level control for the internal programmable counter array interrupt request. 1: High level. 0: Low level. INT4 priority level control for the peripheral interrupt requests, which may be generated by TOE, MAC/PHY, LBI, I2C, SPI, 1-Wire, and UART2 modules. 1: High level. 0: Low level. INT5 priority level control for the internal software DMA complete and millisecond timer timeout interrupt request. 1: High level. 0: Low level. INT6 priority level control for the wake-up interrupt request. 1: High level. 0: Low level. Watchdog priority level control. 1: High level. 0: Low level. 7:6 Reserved Extended Interrupt Flag Register (EIF, 0x91) 7 Bit Name Reset Value Bit Name 0 INT2F 1 INT3F 2 INT4F 3 INT5F 4 INT6F 6 Reserved 5 4 3 INT6F INT5F 0x00 2 INT4F 1 INT3F Access 0 INT2F Description INT2 interrupt flag for the DMA transfer interrupt request, which comes from the Memory RO Arbiter for the TOE/LBI/software DMA mode. This bit is cleared by hardware automatically when CPU branches to interrupt routine. INT3 interrupt flag for the programmable counter array interrupt request. This bit is cleared RO by hardware automatically when CPU branches to interrupt routine. INT4 interrupt flag for the peripheral interrupt requests, which may be generated by TOE, RO MAC/PHY, LBI, I2C, SPI, 1-Wire, and UART2 modules. This bit is cleared by hardware automatically when CPU branches to interrupt routine. INT5 interrupt flag for the internal software DMA complete and millisecond timer timeout R/W interrupt. This bit must be cleared by software within interrupt routine. INT6 interrupt flag for the wake-up interrupt request (when resuming from CPU STOP R/W mode). This bit must be cleared by software within interrupt routine. 7:5 Reserved 123 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY The on-chip peripheral modules such as TOE, Ethernet MAC, Ethernet PHY, Local Bus Interface, I2C, SPI, 1-Wire, and UART2 share the same interrupt request, INT4. The interrupt requests generated by these modules are first being merged (OR'ed) together to generate one single interrupt signal on INT4 to CPU. When CPU receives interrupt(s) on INT4, the software within interrupt routine can read SFR register, PISS1R and PISS2R to identify the source of pending interrupt(s) is coming from which module(s) and then base on the status provided here to further read the interrupt status register of each modules, corresponding to the bit being flagged. Peripheral Interrupt Status Summary 1 Register (PISS1R, 0x9Eh) 7 Bit Reserved Name 0 Reset Value 6 I2C_INT 0 5 SPI_INT 0 4 OW_INT 0 3 TOE_INT 0 2 ETH_INT 0 1 LB_EINT 0 0 LB_INT 0 Bit Name Access Description 0 LB_INT RO Reading "1" indicates that the Local Bus Interface has pending interrupt. 1 LB_EINT RO Reading "1" indicates that the Local Bus Interface has pending external interrupt generated by external local bus devices through LINT pin (only valid in local bus master mode). 2 ETH_INT RO Reading "1" indicates that the Ethernet MAC/PHY has pending interrupt. 3 TOE_INT RO Reading "1" indicates that the TOE has pending interrupt. 4 OW_INT RO Reading "1" indicates that the 1-Wire controller has pending interrupt. 5 SPI_INT RO Reading "1" indicates that the SPI controller has pending interrupt. 6 I2C_INT RO Reading "1" indicates that the I2C controller has pending interrupt. 7 Reserved Peripheral Interrupt Status Summary 2 Register (PISS2R, 0x9Fh) Bit Name Reset Value 7 6 5 4 Reserved 00 3 2 Bit Name 0 UART2_INT 7:1 Reserved Access Description RO Reading "1" indicates that the UART 2 has pending interrupt. 1 124 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights 0 UART2_INT 0 AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 4.9 Watchdog Timer The watchdog timer of AX11015 is a user programmable clock counter that can serve as: z A time-base generator z An event timer z System supervisor As shown in Figure 74, the watchdog timer is driven by the operating system clock, which is supplied to a series of dividers. The divider output is selectable, and determines interval between timeouts. When the timeout is reached, an interrupt flag will be set, and if enabled, a reset will occur (to reset CPU core). The interrupt flag will cause an interrupt to occur if enabled. The reset and interrupt are discrete functions that may be acknowledged or ignored, together or separately for various applications. Figure 74: Watchdog Timer Block Diagram 4.9.1 Watchdog SFR Register Map The watchdog timer has several SFR bits that contribute to its operation. It can be enabled to function as either a reset source, interrupt source, software polled timer or any combination of the three. Both the reset and interrupt have status flags. The watchdog also has a bit that restarts the timer. Address Name 0xE8 EIE Extended Interrupt Enable Register 0xF8 EIP Extended Interrupt Priority Register 0xA8 IE Interrupt Enable register. 0xD8 WDCON Watchdog Control register. 0x8E CKCON Clock Control register. Description Table 20: Watchdog Timer SFR Register Map 125 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY A summary table showing the bit locations of SFR register used for watchdog function is below. Register EIE EIP CKCON WDCON Bit name EWDI PWDI WD[1:0] RWT EWT WTRF WDIF Bit position EIE.5 EIP.5 CKCON.7-6 WDCON.0 WDCON.1 WDCON.2 WDCON.3 Description Enable Watchdog Timer Interrupt. Priority of Watchdog Timer Interrupt. Watchdog Interval Reset Watchdog Timer Enable Watchdog Timer Reset Watchdog Timer Reset flag Watchdog Interrupt flag 4.9.2 Watchdog Interrupt The watchdog interrupt can be turned on/off by EIE register, and set into high/low priority group by EIP register. Please refer to section 4.8 for details. Upon enabled, the watchdog interrupt flag is reported in WDIF bit (WDCON.3). This bit that generates interrupts can be set or cleared by software, with the same result as if they had been set or cleared by hardware. That is, interrupts can be generated or pending interrupts can be cancelled by software. Watchdog Control Register (WDCON, 0xD8) 7 Bit Name Reset Value 6 5 Reserved 4 3 WDIF 2 WTRF 1 EWT 0 RWT 0x00 Bit Name Access 0 RWT R/W 1 EWT R/W 2 WTRF R/W 3 WDIF R/W Description Reset Watchdog Timer. 1: Setting RWT resets the watchdog timer count. Timed Access procedure must be used to set this bit before the watchdog timer expires, or a watchdog timer reset and/or interrupt will be generated if enabled. 0: After software sets this bit, the hardware will automatically clear it. Enable Watchdog Timer Reset. The reset of CPU by watchdog timer is controlled by this bit. This bit has no effect on the ability of the watchdog timer to generate a watchdog interrupt. Timed Access procedure must be used to modify this bit. 1: Watchdog timer timeout resets CPU. 0: Watchdog timer timeout doesn't reset CPU. Watchdog Timer Reset Flag. 1: When set by hardware, indicates that a watchdog timer reset has occurred. Set by software do not generate a watchdog timer reset. 0: It is cleared by chip reset pin, RST_N, but otherwise must be cleared by software. The watchdog timer has no effect on this bit, when EWT bit is cleared. Watchdog Interrupt Flag. 1: WDIF in conjunction with the Enable Watchdog Interrupt bit (EIE.5), and EWT, indicates if a watchdog timer event has occurred and what action should be taken. Setting WDIF in software will generate a watchdog interrupt if enabled. Timed access registers procedure can be used to modify this bit. 0: This bit must be cleared by software before exiting the interrupt service routine, or another interrupt is generated. 7:4 Reserved A Watchdog timeout reset will not disable the Watchdog Timer, but restarts the timer. In general, software should set the Watchdog to whichever state is desired, just to be certain of its state. 126 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Table below summarizes Watchdog Control bits and taken operation concerned to theirs values. EWT X 0 0 EWDI X 0 1 1 0 1 1 WDIF Result 0 No watchdog event. 1 Watchdog time-out has expired. No interrupt has been generated. 1 Watchdog interrupt has occurred. Watchdog time-out has expired. No interrupt has been generated. Watchdog timer 1 reset will occur in 512 clock periods (of operating system clock) if RWT is not strobed. Watchdog interrupt has occurred. Watchdog timer reset will occur in 512 clock periods 1 (of operating system clock) if RWT is not set using Timed Access procedure. Table 21: Watchdog Bits And Actions 4.9.3 Watchdog Timer Reset The Watchdog Timer Reset function works as follows. After initializing the correct timeout interval, software first restarts the Watchdog using RWT bit (WDCON.0) and then enables the reset mode by setting the EWT bit (WDCON.1). At any time prior to reaching its user selected terminal value, software can set the RWT bit (WDCON.0). If RWT is set before the timeout is reached, the timer will start over. If the timeout is reached without RWT bit being set, the Watchdog will reset the CPU. Hardware will automatically clear RWT after software sets it. When the reset occurs, the WTRF bit (WDCON.2) will automatically be set to indicate the cause of the reset, however software must clear this bit manually. A Watchdog timeout reset will not disable the Watchdog Timer, but restarts the timer. In general, software should set the Watchdog to whichever state is desired, just to be certain of its state. 4.9.4 Simple Timer The Watchdog Timer is a free running timer. When used as a simple timer with both the reset (EWT=0, WDCON.1) and interrupt functions disabled (EWDI=0, EIE.5), the timer will continue to set the Watchdog Interrupt flag each time the timer completes the selected timer interval as programmed by WD[1:0] bits (CKCON.7-6). Restarting the timer using the RWT bit (WDCON.0), allows software to use the timer in a polled timeout mode. The WDIF bit is cleared by software or any reset. The Watchdog Interrupt is also available for applications that do not need a true Watchdog Reset but simply a very long timer. The interrupt is enabled using the EWDI bit (EIE.5). When the timeout occurs, the Watchdog Timer will set the WDIF bit (WDCON.3), and an interrupt will occur if the global interrupt enable, EA bit (IE.7) is set. A potential Watchdog Reset is executed 512 clocks after setting of WDIF flag. The WDIF flag indicates the source of the interrupt, and software must clear WDIF flag. Proper use of the Watchdog Interrupt with the Watchdog Reset allows interrupt software to survey the system for errant conditions. 4.9.5 System Monitor When using the Watchdog Timer as a system monitor, the Watchdog Reset function should be used. If the Interrupt function were used, the purpose of the watchdog would be defeated. For example, assume the system is executing errant code prior to the Watchdog Interrupt. The interrupt would temporarily force the system back into control by vectoring the CPU to the interrupt service routine. Restarting the Watchdog and exiting by an RETI or RET, would return the processor to the lost position prior to the interrupt. By using the Watchdog Reset function, the CPU is restarted from the beginning of the program, and therefore placed into a known state. 127 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 4.9.6 Clock Control The Watchdog timeout selection is made using WD[1:0] bits in Clock control register, CKCON (0x8E), which select Watchdog timer timeout period. The Watchdog is clocked directly from operating system clock, and PMM mode directly affects its timeout period. It is increased 100 times slower when the CPU is in PMM mode (because operating system clock is running 1/100 of original frequency in PMM). This allows the watchdog period to remain synchronized with device operation. Number of clocks needed for timeout does not depend on PMM, and is constant as shown in table in below register. The Watchdog has four timeout selections based on the operating system clock frequency. The selections are a pre-selected number of clocks. Therefore, the actual timeout interval is dependent on the operating system clock frequency. Note that the periods shown above are for the interrupt events. The Reset, when enabled, is generated 512 clocks later regardless of whether the interrupt is used. Therefore, the actual Watchdog timeout period is the number shown above plus 512 clocks (of operating system clock). Clock Control Register (CKCON, 0x8E) 7 Bit Name Reset Value MD 5 T2M 4 T1M 3 T0M 2 1 MD Description This adjusts the stretch cycles of XDATWR_N and XDATRD_N signals during MOVX instruction for External Data Memory write and read access cycles. The Minimal read/write pulse length is equal to 1 clock period (MD = 000) and maximal 8 clock periods (MD = 111). The MD bits can be changed any time during program execution. Based on operating system clock frequency and typical SRAM chip with 8ns access time, the R/W recommended setting is as below, Data Memory Wait State Setting, MD Program Code Shadow Mode Non-Shadow Mode 25Mhz 001 001 50Mhz 001 001 100Mhz 001 001 This bit controls the division of the system clock that drives Timer 0. R/W 1: Timer 0 uses a divide-by-4 of the operating system clock frequency. 0: Timer 0 uses a divide-by-12 of the operating system clock frequency. This bit controls the division of the system clock that drives Timer 1. R/W 1: Timer 1 uses a divide-by-4 of the operating system clock frequency. 0: Timer 1 uses a divide-by-12 of the operating system clock frequency. This bit controls the division of the system clock that drives Timer 2. This bit has no effect when the timer is in baud rate generator mode. R/W 1: Timer 2 uses a divide-by-4 of the operating system clock frequency. 0: Timer 2 uses a divide-by-12 of the operating system clock frequency. WD bits select Watchdog timer timeout period. WD Watchdog Interval Number of Clocks System Clock 3 T0M 4 T1M 5 T2M 7:6 WD 0 0x07 Bit Name Access 2:0 6 WD R/W 00 217 01 2 20 1048576 2 23 8388608 2 26 67108864 10 11 131072 128 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 4.9.7 Timed Access Register Timed Access registers have built in mechanism preventing them from accidental writes. TA is located at 0xEB SFR address. To do a correct write to such register the following sequence has to be applied: MOV TA, #0xAA MOV TA, #0x55 ; Any direct addressing instruction writing timed access register. The time elapsed between first, second, and third operation does not matter (any number of Program Wait Sates is allowed). The only correct sequence is required. Any third instruction causes protection mechanism to be turned on. This means that time protected register is opened for write only for single instruction. Reading from such register is never protected. Timed Access registers are listed in table below. Register name WDCON (0xD8) ACON (0x9D) Description Watchdog Configuration. Address Control register. Table 22: Timed Access Registers 129 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 4.10 Power Management Unit The figure below shows 3 possible modes of operation of AX11015. The Full Speed mode is when the operating system clock is running at full clock rate (i.e., 25Mhz, 50Mhz, or 100Mhz, depending on SYSCK_SEL[1:0] setting). The PMM (Power Management Mode) is when the operating system clock is running at 1/100 of full clock rate. The STOP mode is when the operating system clock is turned off and the CPU is in complete stop mode. For typical power consumption of AX11015 in these operating modes, please refer to section 5.2. 1 Reset 2 Full Speed 6 3 7 PMM Mode 5 STOP Mode 4 Symbol Description 1 Reset condition puts the chip in Full Speed mode after the reset removal. 2 Software sets PMM bit = 1 (PCON.0) with SWB bit = 1 or 0 (PCON.2) to enter the PMM mode with switchback enabled or disabled. 3 See section 4.10.2 for detailed description. 4, 6 Software sets STOP bit = 1 (PCON.1) to enter STOP mode. 5,7 See section 4.10.3 for detailed description. Figure 75: AX11015 Operating Mode Transition Diagram 4.10.1 Power Management Unit SFR Register Map Address Name 0x87 PCON Power Configuration Register. 0xE9 STATUS Status Register. Description Table 23: Power Management Unit SFR Register Map 130 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 4.10.2 Power Management Mode The Power Management Mode (PMM) feature allows software dynamically matches operating frequency and current consumption with the need for processing power. Instead of the full clock rate provided to the CPU core and most system logic, the PMM mode tells the clock generation block to divide the operating system clock frequency by 100 to operate the chip in reduced speed to conserve power. The Switchback feature allows the CPU almost immediately returning to full speed mode upon acknowledgment of an external interrupt or a falling edge on a serial port receiver pin, RXD0/RXD1 of UART0/UART1. Additionally, CPU operating in PMM would normally be unable to sample an incoming serial transmission and properly receive it. The switchback feature allows the CPU to return to full speed operation in time to receive incoming serial port data and process interrupts with no loss in performance. STATUS (0xE9) register is incorporated to prevent the software from accidentally reducing the clock rate during the servicing of an external interrupt or serial port activity. This register can be interrogated to determine if a high priority, or low priority interrupt is in progress, or if serial port activity is occurring. Based on this information the software can delay or reject a planned change in the clock divider rate in clock generation block of AX11015. STATUS Register (STATUS, 0xE9) Bit Name Reset Value 7 Reserved Bit Access Name 0 SPRA0 RO 1 SPTA0 RO 2 SPRA1 RO 3 SPTA1 RO 4 Reserved 5 LIP RO 6 HIP RO 7 Reserved 6 HIP 5 LIP 4 Reserved 3 SPTA1 0x00 2 SPRA1 1 SPTA0 0 SPRA0 Description UART0 receiver activity status. 1: UART0 receiver active. 0: UART0 receiver inactive. UART0 transmitter activity status. 1: UART0 transmitter active. 0: UART0 transmitter inactive. UART1 receiver activity status. 1: UART1 receiver active. 0: UART1 receiver inactive. UART1 transmitter activity status. 1: UART1 transmitter active. 0: UART1 transmitter inactive. Low Priority (LP) interrupt status. 1: LP interrupt progressing. 0: no LP interrupt. High Priority (HP) interrupt status. 1: HP interrupt progressing. 0: no HP interrupt. When PMM is invoked via setting PMM bit (PCON.0), it controls the clock generation block to divide the operating system clock frequency by 100. Note that all internal functions, on-chip timers (including serial port baud rate generation), watchdog timer, millisecond timer, and software timing loops will run at the reduced speed. In addition, use of the switchback feature is possible to affect a return from PMM to the full speed mode. This allows both hardware and software to cause an exit from PMM. It is the responsibility of the software to test for UART activity before attempting to change speed, as a modification of the operating system clock during a UART operation will corrupt the data. In general, it is not possible to generate standard baud rates while in PMM, and the user is advised to avoid PMM or use the Switchback feature if UART operation is desired. 131 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Power Configuration Register (PCON, 0x87) Bit Name Reset Value 7 SMOD0 6 SMOD1 5 Reserved 4 PWE 3 RSM 2 SWB 1 STOP 0 PMM 0x00 Bit Name Access 0 PMM R/W 1 STOP R/W 2 SWB R/W 3 RSM R/W 4 PWE R/W 5 6 7 Reserved SMOD1 SMOD0 R/W R/W R/W Description Power Management Mode Enable bit. 1: PMM entered. 0: PMM disabled. STOP mode bit. 1: STOP mode entered. 0: Disabled. Switchback enable. 1: Enabled interrupts and serial ports cause switchback. PMM bit is cleared. 0: Interrupts and serial ports don't affect PMM bit. Note that after leaving PMM mode, the software shall also clear this bit. Regulator Standby Mode. 1: Set the internal 3.3V to 1.8V regulator to operate at standby mode (when the 1.8V current drawn is less than 30mA) for better conversion efficiency. 0: Set the internal 3.3V to 1.8V regulator to full operating mode (when the 1.8V current drawn is more than 30mA) for better conversion efficiency. Program memory Write Enable bit. 1: Enable Program Memory write access signal activity during MOVX instructions. 0: Disabled. UART1 double baud rate bit. UART0 double baud rate bit. Switchback Feature The Switchback feature solves one of the most vexing dilemmas faced by power conscious systems. Many applications are unable to use STOP mode because they require constant computation. The feature allows a system to operate at a relatively slow speed, and burst to a faster mode when required by an external event. Enable this feature by setting the SWB bit (PCON.2), a qualified interrupt (interrupt which has occurred and been acknowledged) or serial port reception or transmission cause the CPU to return to full speed mode. An interrupt must be enabled and not blocked by a higher priority interrupt. Software should manually return the CPU to PMM after the event is completed. The following events can trigger AX11015 switchback to full speed mode from PMM: 1. Receive interrupt on external interrupt pin, INT0 or INT1 if enabled in EX0 bit (IE.0) or EX1 bit (IE.2) 2. Detect falling-edge transition (start bit) on RXD0 pin of UART0 or RXD1 pin of UART1 if enabled in REN0 bit (SCON0.4) or REN1 bit (SCON1.4). 3. Transmit buffer loaded in UART0 or UART1. 4. Watchdog timer reset. In addition, the following events can also trigger AX11015 switchback to full speed mode from PMM, via INT 6: 1. Receive rising-edge signal on external remote-wakeup trigger input pin, EXT_WKUP, if enabled in EPWT bit (SPWIE.5). 2. Receive Magic packet from Ethernet, if enabled in RWMP bit (SPWIE.4). 3. Receive pre-defined Wakeup frame from Ethernet, if enabled in MWFE bit (SPWIE.6) and EWFF0/1 bit (WFCR.0/2). 4. Detect link-up signal from the embedded Ethernet PHY, if enabled in PPLWE bit (SPWIE.0). 132 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 5. Detect link-up signal from secondary PHY, if enabled in SPLWE bit (SPWIE.2). 6. Detect falling-edge transition (start bit) on RXD2 pin or falling-edge transition on RI pin of UART 2, if enabled in WE bit (HSIER.4, 0xE2). In the case of a UART0/1-initiated switchback, the switchback is not generated by the associated interrupt. This is because the AX11015 operating in PMM will not be able correctly receiving a byte of data to generate an interrupt. Instead, Switchback is generated by a UART0/1 reception on the falling edge associated with the start bit, if the associated receiver enable bit (SCON0.4 or SCON1.4) is set. For UART transmissions, a switchback is generated when the UART0/1 buffer is loaded. This ensures the CPU will be operating in full speed mode when the data is being transmitted, and eliminates the need for a write to the PMM bit (PCON.0) to exit PMM before transmitting. The Switchback feature is unaffected by the state of the serial port interrupt flags. Switchback Feature Timing The timing of the Switchback is dependent on the source. Interrupt-initiated (such as INT0, INT1, INT6) switchbacks will occur at the start of the first cycle following the event initiating the Switchback. If the current instruction in progress is a write to the IE, IP, EIE, or EIP registers, interrupt processing will be delayed until the completion of the following instruction. UART-initiated (such as UART0/1) switchbacks occur at the start of the instruction following the MOV that loads SBUF0 or SBUF1. UART-initiated (such as UART0/1) switchbacks occur during the cycle in which the falling edge was detected. There are a few points that must be considered when using a serial port reception to generate Switchback. Under normal circumstances, noise on the line or an aborted transmission would cause the serial port to timeout and the data to be ignored. This presents a problem if the Switchback is used, however, because Switchback would occur but there is no indication to the system that one has occurred. If PMM and serial port Switchback functions are used in a noisy environment, the user is advised periodically checking if AX11015 has accidentally exited PMM. A similar problem can occur if multiprocessor communication protocols are used in conjunction with PMM. The problem is that an invalid address that should be ignored by a particular processor will still generate Switchback. As a result, it is not recommended to use a multiprocessor communication scheme in conjunction with PMM. If the system power considerations will allow for an occasional erroneous Switchback, a polling scheme can be used to place the AX11015 back into PMM. 4.10.3 STOP Mode The STOP mode is the lowest power state that the AX11015 can enter. This is achieved by cutting off the clock feeding to the CPU core and the peripheral logics. When entering the STOP mode, the TOFFOP bit (Flag.1) in I2C EEPROM determines whether the 25Mhz oscillator and internal PLL will be disabled or not during STOP mode. When AX11015 is running in Full Speed or PMM mode, software can enter STOP mode by setting STOP bit (PCON.1). If the STOP mode is entered with 25Mhz oscillator and PLL completely disabled (TOFFOP bit (Flag.1)= 1), the STOP mode can be exited in following ways: 1. Receive rising-edge signal on external remote-wakeup trigger pin, EXT_WKUP, if enabled in EPWT bit (SPWIE.5). 2. Detect falling-edge transition (start bit) on RXD2 pin or falling-edge transition on RI pin of UART 2, if enabled in WE bit (HSIER.4). 3. Receive hardware reset on RST_N pin (CPU operation will resume execution at address 0x00_0000). Please note that if software sets both EPWT bit (SPWIE.5) and WE bit (HSIER.4, 0xE2) to "0" prior to entering STOP mode while the TOFFOP bit = 1, then the chip can not be awaked by any event at all and only the hardware chip reset can remove the chip from STOP mode back to normal functional mode. If the STOP mode is entered with 25Mhz oscillator and PLL still running (TOFFOP bit (Flag.1) = 0), the STOP mode can be exited in following ways, depending on software configuration before entering the STOP mode: 133 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 1. Receive rising-edge signal on external remote-wakeup trigger pin, EXT_WKUP, if enabled in EPWT bit (SPWIE.5). 2. Receive Magic packet from Ethernet, if enabled in RWMP bit (SPWIE.4). 3. Receive pre-defined Wakeup frame from Ethernet, if enabled in MWFE bit (SPWIE.6) and EWFF0/1 bit (WFCR.0/2). 4. Detect link-up signal from the embedded Ethernet PHY, if enabled in PPLWE bit (SPWIE.0). 5. Detect link-up signal from secondary PHY, if enabled in SPLWE bit (SPWIE.2). 6. Detect falling-edge transition (start bit) on RXD2 pin or falling-edge transition on RI pin of UART 2, if enabled in WE bit (HSIER.4). 7. Receive hardware reset on RST_N pin (CPU operation will resume execution at address 0x00_0000). Example Programming Procedure Case 1: Using a rising-edge signal on EXT_WKUP pin to awake up the chip, the software shall: 1. Enable wakeup interrupt by setting EPWT bit (SPWIE.5) and EINT6 bit (EIE.4), disable Ethernet PHY to reduce power consumption by setting PHY register's Power-Down bit (BMCR.11), and stop oscillator and PLL during STOP mode by setting TOFFOP bit (Flag.1) = 1. 2. Then set STOP bit (PCON.1) to enter STOP mode. Now the system clock will be turned off and the oscillator and PLL will be stopped too. 3. Upon detecting a rising-edge on EXT_WKUP pin, the oscillator and PLL will first resume running and the clock generation block will re-enable the system clock after it is stabled enough, and then the INT 6 will be asserted to notify CPU. Case 2: Using receiving Magic packet or Wakeup frame to awake up the chip, the software shall: 1. Enable wakeup interrupt by having RWMP bit (SPWIE.4) or MWFE bit (SPWIE.6), keep Ethernet PHY power-on to allow receiving Ethernet packet by clearing PHY register's Power-Down bit (BMCR.11), keep oscillator and PLL running by setting TOFFOP bit (Flag.1) = 0. 2. If Wakeup frame wakeup event is used, also define the Wakeup frame pattern in related registers. 3. Then set STOP bit (PCON.1) to enter STOP mode. Now the system clock will be turned off while oscillator and PLL keeps on running. 4. Upon receiving Magic packet or Wakeup frame from Ethernet, the clock generation block will re-enable the system clock and then the INT 6 will be asserted to notify CPU. Case 3: Using the link-up event of the embedded Ethernet PHY to awake up the chip, the software shall: 1. Enable wakeup interrupt by setting PPLWE bit (SPWIE.0) and EINT6 bit (EIE.4), keep Ethernet PHY power-on to allow link-up detection by clearing PHY register's Power-Down bit (BMCR.11), keep oscillator and PLL running by setting TOFFOP bit (Flag.1) = 0. 2. Then set STOP bit (PCON.1) to enter STOP mode. Now the system clock will be turned off while oscillator and PLL keeps on running. 3. Upon detecting the link-up event on embedded Ethernet PHY, the clock generation block will re-enable the system clock and then the INT 6 will be asserted to notify CPU. 134 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 4.11 Timers and Counters The AX11015 contains three 16-bit timer/counters, namely, Timer 0, Timer 1, and a fully compatible with the standard 8052 Timer 2, and one dedicated Millisecond Timer which is programmable with 1ms resolution for software use. In the "timer mode", timer registers are incremented every 12 or 4 operating system clock periods when appropriate timer is enabled. In the "counter mode" the timer registers are incremented every falling transition on their corresponding input pins: TM0_CK, TM1_CK, or TM2_CK. The input pins are sampled every operating system clock period. The following table shows Timer 0, 1, 2 pin description. All pins are input direction and no three-state output pin. Pin TM0_CK TM0_GT I/O I Polarity Falling I High TM1_CK TM1_GT I Falling I High TM2_CK TM2_GT I I Falling High Description Timer 0 external clock input Timer 0 clock input gate control input to facilitate pulse width measurements. Timer 1 external clock input Timer 1 clock input gate control input to facilitate pulse width measurements. Timer 2 external clock input Timer 2 clock input gate control input. Table 24: Timer 0, 1, 2 Pin Description 4.11.1 Timers 0, 1, 2 Related SFR Register Map Address 0x89 0x88 0x8E 0x8A 0x8C 0x8B 0x8D 0xA8 0xB8 0xC8 0xCA 0xCB 0xCC 0xCD Name TMOD TCON CKCON TL0 TH0 TL1 TH1 IE IP T2CON RLDL RLDH TL2 TH2 Description Timer 0,1 Control Mode Register. Timer 0,1 Configuration Register. Clock Control Register. Timer 0 Low Byte Register. Timer 0 High Byte Register. Timer 1 Low Byte Register. Timer 1 High Byte Register. Interrupt Enable Register. Interrupt Priority Register. Timer 2 Configuration Register. Timer 2 Reload Low Byte Register. Timer 2 Reload High Byte Register. Timer 2 Low Byte Register. Timer 2 High Byte Register. Table 25: Timers 0, 1, 2 Related SFR Register Map 4.11.2 Timer 0, 1 Timer 0 and Timer 1 are fully compatible with the standard 8051 timers. Each timer consists of two 8-bit registers, and they are TH0 (0x8C), TL0 (0x8A), TH1 (0x8D), and TL1 (0x8B). Timers 0 and Timer 1 work in the same four modes, namely, Mode 0, Mode 1, Mode 2, and Mode 3, as described in following TMOD register description. 135 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Timer 0, 1 Control Mode Register (TMOD, 0x89) Bit Name Reset Value 7 GATE 6 CT 5 M1 4 M0 3 GATE 2 CT 1 M1 0 M0 0x00 Bit Name Access Description Timer 0 mode select bits. The table below shows the 4 operating modes of Timer 0. Mode M1 M0 Timer 0 Operating Mode Description TH0 operates as 8-bit timer/counter with a divide by 32 prescaler 0 0 0 served by lower 5-bit of TL0. 1:0 M1, M0 R/W 1 0 1 16-bit timer/counter. TH0 and TL0 are cascaded. 2 1 0 TL0 operates as 8-bit timer/counter with 8-bit auto-reload by TH0. TL0 is configured as 8-bit timer/counter controlled by the standard 3 1 1 Timer 0 bits. TH0 is an 8-bit timer controlled by the Timer 1 control bits. Timer 1 holds its count. Timer 0 Counter or Timer select bit. 2 CT R/W 1: Counter mode, Timer 0 clock source from TM0_CK pin. 0: Timer mode, internally clocked. Timer 0 Gating control. 1: Timer 0 enabled while TM0_GT pin is high and TR0 control bit (TCON.4) is set, to 3 GATE R/W facilitate pulse width measurements. 0: Timer 0 enabled while TR0 control bit (TCON.4) is set. Timer 1 mode select bits. The table below shows the 4 operating modes of Timer 1. Mode M1 M0 Timer 1 Operating Mode Description TH1 operates as 8-bit timer/counter with a divide by 32 prescaler 0 0 0 served by lower 5-bit of TL1. 5:4 M1, M0 R/W 1 0 1 16-bit timer/counter. TH1 and TL1 are cascaded. 2 1 0 TL1 operates as 8-bit timer/counter with 8-bit auto-reload by TH1. TL0 is configured as 8-bit timer/counter controlled by the standard 3 1 1 Timer 0 bits. TH0 is an 8-bit timer controlled by the Timer 1 control bits. Timer 1 holds its count. Timer 1 Counter or Timer select bit. 6 CT R/W 1: Counter mode, Timer 1 clock source from TM1_CK pin. 0: Timer mode, internally clocked. Timer 1 Gating control. 1: Timer 1 enabled while TM1_GT pin is high and TR1 control bit (TCON.6) is set, to 7 GATE R/W facilitate pulse width measurements. 0: Timer 1 enabled while TR1 control bit (TCON.6) is set. Timer 0, 1 Configuration Register (TCON, 0x88) Bit Name Reset Value 7 TF1 6 TR1 5 TF0 4 TR0 3 IE1 2 IT1 1 IE0 0 IT0 0x00 Bit Name Access Description 0 IT0 R/W INT0 level or edge sensitivity. 0: Level triggered. 1: Edge triggered. INT0 interrupt flag. This bit is cleared by hardware automatically when CPU branches to 1 IE0 RO interrupt routine. 2 IT1 R/W INT1 level or edge sensitivity. 0: Level triggered. 1: Edge triggered. INT1 interrupt flag. This bit is cleared by hardware automatically when CPU branches to 3 IE1 RO interrupt routine. 4 TR0 R/W Timer 0 run control bit. 1: Enabled. 0: Disabled. 136 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 5 TF0 6 TR1 7 TF1 Timer 0 interrupt (overflow) flag. This bit is cleared by hardware when CPU branches to interrupt routine. R/W Timer 1 run control bit. 1: Enabled. 0: Disabled. Timer 1 interrupt (overflow) flag. This bit is cleared by hardware when CPU branches to RO interrupt routine. RO In the "timer mode", timer registers are incremented every 12 or 4 operating system clock periods, configured by T0M and T1M bits (CKCON.3~4). The Timer 0 and Timer 1 interrupt enable registers are ET0 bit (IE.1, 0xA8) and ET1 bit (IE.3), respectively, and their interrupt priority registers are PT0 bit (IP.1) and PT1 bit (IP.3), respectively. The Timer 0 and Timer 1 interrupt (overflow) flag are TF0 bit (TCON.5) and TF1 (TCON.7), respectively. Please refer to section 4.8 for details. Clock Control Register (CKCON, 0x8E) 7 Bit Name Reset Value MD 5 T2M 4 T1M 3 T0M 2 1 MD Description This adjusts the stretch cycles of XDATWR_N and XDATRD_N signals during MOVX instruction for External Data Memory write and read access cycles. The Minimal read/write pulse length is equal to 1 clock period (MD = 000) and maximal 8 clock periods (MD = 111). The MD bits can be changed any time during program execution. Based on operating system clock frequency and typical SRAM chip with 8ns access time, the R/W recommended setting is as below, Data Memory Wait State Setting, MD Program Code Shadow Mode Non-Shadow Mode 25Mhz 001 001 50Mhz 001 001 100Mhz 001 001 This bit controls the division of the system clock that drives Timer 0. R/W 1: Timer 0 uses a divide-by-4 of the operating system clock frequency. 0: Timer 0 uses a divide-by-12 of the operating system clock frequency. This bit controls the division of the system clock that drives Timer 1. R/W 1: Timer 1 uses a divide-by-4 of the operating system clock frequency. 0: Timer 1 uses a divide-by-12 of the operating system clock frequency. This bit controls the division of the system clock that drives Timer 2. This bit has no effect when the timer is in baud rate generator mode. R/W 1: Timer 2 uses a divide-by-4 of the operating system clock frequency. 0: Timer 2 uses a divide-by-12 of the operating system clock frequency. WD bits select Watchdog timer timeout period. WD Watchdog Interval Number of Clocks System Clock 3 T0M 4 T1M 5 T2M 7:6 WD 0 0x07 Bit Name Access 2:0 6 WD R/W 00 217 01 2 20 1048576 2 23 8388608 2 26 67108864 10 11 131072 137 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Timer 0 - Mode 0 In this mode, the Timer 0 register is configured as a 13-bit register. As the count rolls over from all 1s to all 0s, Timer 0 interrupt flag TF0 is set. The counted input is enabled to the Timer 0 when TCON.4 = 1 and either TMOD.3 = 0 or TM0_GT = 1. (Setting TMOD.3 = 1 allows the Timer 0 to be controlled by external input TM0_GT0, to facilitate pulse width measurements). The 13-bit register consists of all 8 bits of TH0 and the lower 5 bits of TL0. The upper 3 bits of TL0 are indeterminate and should be ignored. Figure 76: Timer/Counter 0, Mode 0: 13-Bit Timer/Counter Timer 0 - Mode 1 Mode 1 is the same as Mode 0, except that the timer register is running with all 16 bits. Mode 1 is shown in figure below. Figure 77: Timer/Counter 0, Mode 1: 16-Bit Timer/Counter 138 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Timer 0 - Mode 2 Mode 2 configures the timer register as an 8-bit counter (TL0) with automatic reloads, as shown in figure below. Overflow from TL0 not only sets TF0, but also reloads TL0 with the contents of TH0, which is loaded by software. The reload leaves TH0 unchanged. Figure 78: Timer/Counter 0, Mode 2: 8-Bit Timer/Counter With Auto-Reload Timer 0 - Mode 3 Timer 0 in Mode 3 establishes TL0 and TH0 as two separate counters. The logic for Mode 3 on Timer 0 is shown in figure below. TL0 uses the Timer 0 control bits: CT, GATE, TR0, TM0_GT and TF0. TH0 is locked into a timer function and uses the TR1 and TF1 flags from Timer 1 and controls Timer 1 interrupt. Mode 3 is provided for applications requiring an extra 8-bit timer/counter. When Timer 0 is in Mode 3, Timer 1 can be turned off by switching it into its own Mode 3, or can still be used by the serial channel (UART0/1) as a baud rate generator, or in any application where interrupt from Timer 1 is not required. Figure 79: Timer/Counter 0, Mode 3: Two 8-Bit Timers/Counters 139 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Timer 1 - Mode 0 In this mode, the Timer 1 register is configured as a 13-bit register. As the count rolls over from all 1s to all 0s, Timer 1 interrupt flag TF1 is set. The counted input is enabled to the Timer 1 when TCON.6 = 1 and either TMOD.6 = 0 or TM1_GT = 1. (Setting TMOD.7 = 1 allows the Timer 1 to be controlled by external input TM1_GT, to facilitate pulse width measurements). The 13-bit register consists of all 8 bits of TH1 and the lower 5 bits of TL1. The upper 3 bits of TL1 are indeterminate and should be ignored. Figure 80: Timer/Counter 1, Mode 0: 13-Bit Timers/Counters Timer 1 - Mode 1 Mode 1 is the same as Mode 0, except that the timer register is running with all 16 bits. Mode 1 is shown in figure below. Figure 81: Timer/Counter 1, Mode 1: 16-Bit Timers/Counters 140 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Timer 1 - Mode 2 Mode 2 configures the timer register as an 8-bit counter (TL1) with automatic reloads, as shown in figure below. Overflow from TL1 not only sets TF1, but also reloads TL1 with the contents of TH1, which is loaded by software. The reload leaves TH1 unchanged. Figure 82: Timer/Counter 1, Mode 2: 8-Bit Timer/Counter With Auto-Reload Timer 1 - Mode 3 Timer 1 in Mode 3 is held counting. The effect is the same as setting TR1=0. 141 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 4.11.3 Timer 2 Timer 2 is fully compatible with the standard 8052 Timer 2. Totally five SFR control the Timer 2 operation: TH2/TL2 (0xCD/0xCC) counter registers, RLDH/RLDL (0xCB/0xCA) capture registers and T2CON (0xC8) control register. Timer 2 works in the three modes selected by T2CON bits as shown in Table 26 below. RCLK, CPRL2 TR2 TCLK 0 0 1 0 1 1 1 X X X 1 0 Timer 2 Operating Mode Description 16-bit auto-reload mode. The Timer 2 overflow sets TF2 bit and the TH2, TL2 registers are reloaded 16-bit value from RLDH, RLDL. 16-bit capture mode. The Timer 2 overflow sets TF2 bit. When the EXEN2=1 the TH2, TL2 register values are stored into RLDH, RLDL while falling edge is detected on TM2_GT pin. Baud rate generator for the UART0 interface. Timer 2 is off. Table 26: Timer 2 Mode of Operation Timer 2 Configuration Register (T2CON, 0xC8) Bit Name Reset Value 7 TF2 Bit Name Access Description Capture/reload select. 1: TM2_GT pin falling edge causes capture to occur when EXEN2=1. 0: Automatic reload occurs: on Timer 2 overflow or falling edge of TM2_GT pin when EXEN2=1. When RCLK or TCLK is set this bit is ignored and automatic reload on Timer 2 overflow is forced. Timer/counter select. 1: External event counter. Clock source is TM2_CK pin. 0: Timer internally clocked. Start/stop Timer 2. 1: Start. 0: Stop. Enable TM2_GT pin functionality. 1: Allows capture or reload as a result of TM2_GT pin falling edge. 0: Ignore T2EX events. Transmit clock enable. 1: UART0 transmitter is clocked by Timer 2 overflow pulses. 0: UART0 transmitter is clocked by Timer 1 overflow pulses. Receive clock enable. 1: UART0 receiver is clocked by Timer 2 overflow pulses. 0: UART0 receiver is clocked by Timer 1 overflow pulses. Falling edge indicator on TM2_GT pin when EXEN2=1. Must be cleared by software. Timer 2 interrupt (overflow) flag. Must be cleared by software. The flag will not be set when either RCLK or TCLK is set. 0 CPRL2 R/W 1 CT2 R/W 2 TR2 R/W 3 EXEN2 R/W 4 TCLK R/W 5 RCLK R/W 6 EXF2 R/W 7 TF2 R/W 6 EXF2 5 RCLK 4 TCLK 3 EXEN2 0x00 2 TR2 1 CT2 0 CPRL2 The Timer 2 interrupt enable register is ET2 bit (IE.5, 0xA8) and its interrupt priority register is PT2 bit (IP.5, 0xB8). The Timer 2 interrupt (overflow) flag is TF2 bit (T2CON.7). The TF2 bit that generates interrupts can be set or cleared by software, with the same result as if they had been set or cleared by hardware. That is, interrupts can be generated or pending interrupts can be cancelled by software. Please refer to section 4.8 for details. 142 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Timer 2 in Timer Mode Timer 2 related bits are shown in Figure 83 below. The timer register can be clocked by the external TM2_CK pin or internal operating system clock. If internal operating system clock is used, it can be incremented every 12 or 4 operating system clock periods, configured by T2M bit (CKCON.5, 0x8E). Figure 83: Timer 2 Block Diagram In Timer Mode Timer 2 in UART0 Baud Rate Generator Mode Interrupt is also generated at falling edge of TM2_GT pin, while EXEN2 bit is set. This interrupt doesn't set TF2 flag, but EXF2 only and used 0x2B vector. Please see Figure 84 below. Figure 84: Timer 2 Block Diagram As UART0 Baud Rate Generator 143 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 4.11.4 Millisecond Timer The dedicated Millisecond Timer can be used as a coarse timing reference in software programming (such as TCP/IP protocol stack processing) and is programmable with 1ms resolution. The timeout period can be programmed from 1ms to 1024ms. When Millisecond Timer times out, upon enabled, an interrupt on INT5 will be generated to CPU. The INT5 is shared with Software DMA transfer. For detailed register description related to Millisecond Timer, please refer to section 4.7.3, on Millisecond Timer Register, MSTR (0x0C). The divider ratio of internal 1ms timing pulse in Millisecond Timer is generated based on the setting of SYSCK_SEL[1:0] pins, which also determine the operating system clock frequency. SYSCK_SEL [1:0] Setting 00 01 11 10 Clock Divider Ratio for Description Internal 1ms Timing Pulse 25,000 This sets the operating system clock frequency to be 25Mhz (if internal osclk is used as main clock source) or close to 25Mhz (if LB_CLK is used as clock source). Please note that if LB_CLK input pin is used as clock source, e.g., input frequency = 24Mhz, then the 1ms timing pulse will be about 1.04ms instead. 50,000 This sets the operating system clock frequency to be 50Mhz (if internal osclk is used as main clock source) or close to 50Mhz (if LB_CLK is used as clock source). Please note that if LB_CLK input pin is used as clock source, e.g., input frequency = 48Mhz, then the 1ms timing pulse will be about 1.04ms instead. 100,000 This sets the operating system clock frequency to be 100Mhz (if internal osclk is used as main clock source) or close to 100Mhz (if LB_CLK is used as clock source). Please note that if LB_CLK input pin is used as clock source, e.g., input frequency = 96Mhz, then the 1ms timing pulse will be about 1.04ms instead. Reserved Reserved. Table 27: Millisecond Timer Divider Ratio 144 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 4.12 UARTs AX11015 supports 3 UART interfaces, namely, UART 0, UART 1, and UART 2. The UART 0 and UART 1 have the same functionality as standard 8051 UARTs. Each is full duplex, meaning it can transmit and receive concurrently. Each is receive double-buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the receive register. The UART 2 is designed to be maximally compatible with standard 16550. It can communicate with MODEM or other external device (e.g. computer) by using RS-232 protocol. The UART 2 has 16-bytes deep transmit/receive FIFO and its transfer rate can be up to 921600 bps. 4.12.1 UART 0, 1 SFR Register Map Address 0x98 0x99 0x87 0xA8 0xB8 0xC0 0xC1 Name SCON0 SBUF0 PCON IE IP SCON1 SBUF1 Description UART 0 Configuration Register. UART 0 Buffer Register. Power Configuration Register. Interrupt Enable Register. Interrupt Priority Register. UART 1 Configuration Register. UART 1 Buffer Register. Table 28: UART 0, 1 SFR Register Map 4.12.2 UART 0 The UART 0 has the same functionality as a standard 8051 UART 0. The UART 0 serial port is full duplex, receive double-buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the receive register. The UART 0 can operate in 4 modes: one synchronous and three asynchronous modes. z Mode 0, synchronous mode z Mode 1, 8-bit UART, variable baud rate, Timer 1 or Timer 2 clock source z Mode 2, 9-bit UART, fixed baud rate z Mode 3, 9-bit UART, variable baud rate, Timer 1 or Timer 2 clock source Mode 2 and 3 has a special feature for multiprocessor communications. The feature is enabled by setting SM02 bit in SCON0 register. The master processor first sends out an address byte, which identifies the target slave. An address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte. With SM02 = 1, no slave will be interrupted by a data byte. An address byte will interrupt all slaves. The addressed slave will clear its SM02 bit and prepare to receive the data bytes that will be coming. The slaves that were not being addressed leave their SM02 set and ignoring the incoming data. The UART 0 related registers are: SBUF0 (0x99), SCON0 (0x98), PCON (0x87), IE (0xA8) and IP (0xB8). The UART0 data buffer (SBUF0) consists of two separate registers: transmit and receive registers. A data writes into the SBUF0 sets this data in UART0 output register and starts a transmission. A data reads from SBUF0, reads data from the UART0 receive register. Writing to SBUF0 loads the transmit register, and reading SBUF0 reads a physically separate receive register. 145 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Figure 85: UART 0 Block Diagram UART 0 Configuration Register (SCON0, 0x98) Bit Name Reset Value Bit Name Access 0 RI0 R/W 1 TI0 R/W 2 RB08 R/W 3 TB08 R/W 4 REN0 5 SM02 6 SM01 R/W R/W 7 SM00 R/W 7 SM00 6 SM01 5 SM02 4 REN0 3 TB08 0x00 2 RB08 1 TI0 0 RI0 Description Receive interrupt flag, set by hardware after completion of a serial reception. Must be cleared by software. Transmit interrupt flag, set by hardware after completion of a serial transfer. Must be cleared by software. In Modes 2 and 3 it is the 9th data bit received. In Mode 1, if SM02 is 0, RB08 is the stop bit. In Mode 0 this bit is not used. The 9th transmitted data bit in Modes 2 and 3. Set or cleared by the CPU, depending on the function it performs (parity check, multiprocessor communication etc.) If set, enables serial reception. Cleared by software to disable reception. Enables a multiprocessor communication feature. Sets baud rate. Mode SM00 SM01 Description UART 0 Baud Rate 0 0 0 Shift register Fsys_clk/12 8-bit UART Variable. SMOD0 bit (PCON.7) Baud Rate 0 T1ov/32 or T2ov/16 1 0 1 1 T1ov/16 or T2ov/16 T1ov is Timer 1 overflow rate, and T2ov is Timer 2 overflow rate. 9-bit UART SMOD0 bit (PCON.7) Baud Rate 2 1 0 0 Fsys_clk//64 1 Fsys_clk/32 3 1 1 9-bit UART Variable, same as Mode 1 above Note: Fsys_clk is operating system clock frequency. 146 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY The UART 0 interrupt enable register is ES0 bit (IE.4, 0xA8) for both RI0 and TI0 interrupt flags in SCON0. Its interrupt priority register is PS0 bit (IP.4, 0xB8). The RI0 and TI0 bits that generates interrupts can be set or cleared by software, with the same result as if they had been set or cleared by hardware. That is, interrupts can be generated or pending interrupts can be cancelled by software. Please refer to section 4.8 for details. UART 0 Buffer Register (SBUF0, 0x99) 7 Bit Name Reset Value Bit Name 7:0 SB0 6 5 4 3 2 1 0 SB0 0x00 Access R/W Description A data writes into the SBUF0 sets this data in UART0 output register and starts a transmission. A data reads from SBUF0, reads data from the UART0 receive register. Mode 0, Synchronous Mode Pin RXD0 serves as input and output. TXD0 output is a shift clock. The baud rate is fixed at 1/12 of the operating system clock frequency. Eight bits are transmitted with LSB first. Reception is initialized by setting the flags in SCON0 as follows: RI0 = 0 and REN0 = 1. Figure 86: UART 0, Mode 0 Transmit Timing Diagram Mode 1, 8-bit UART, Variable Baud Rate, Timer 1 or Timer 2 Clock Source Pin RXD0 serves as input, and TXD0 serves as serial output. 10 bits are transmitted: a start bit (always 0), 8 data bits (LSB first), and a stop bit (always 1). On receive, a start bit synchronizes the transmission, 8 data bits are available by reading SBUF0, and stop bit sets the flag RB08 in the SFR register SCON0. The baud rate is variable and depends from Timer 1 or Timer 2 mode. To enable Timer 2 clocking set the TCLK, RCLK bits located in T2CON (0xC8) register. Figure 87: UART 0, Mode 1 Transmit Timing Diagram 147 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Mode 2, 9-bit UART, Fixed Baud Rate This mode is similar to Mode 1 with two differences. The baud rate is fixed at 1/32 or 1/64 of operating system clock frequency, and 11 bits are transmitted or received: a start bit (0), 8 data bits (LSB first), a programmable 9th bit, and a stop bit (1). The 9th bit can be used to control the parity of the UART0 interface: at transmission, bit TB08 in SCON0 is output as the 9th bit, and at receive, the 9th bit affects RB08 in SCON0. Figure 88: UART 0, Mode 2 Transmit Timing Diagram Mode 3, 9-bit UART, Variable Baud Rate, Timer 1 or Timer 2 Clock Source The only difference between Mode 2 and Mode 3 is that the baud rate is a variable in Mode 3. When REN0 = 1 data receiving is enabled. The baud rate is variable and depends from Timer 1 or Timer 2 mode. To enable Timer 2 clocking set the TCLK, RCLK bits located in T2CON (0xC8) register. Figure 89: UART 0, Mode 3 Transmit Timing Diagram 148 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 4.12.3 UART 1 The UART1 has the same functionality as a standard 8051 UART1. The UART 1 serial port is full duplex, receive double-buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the receive register. The UART 1 can operate in 4 modes: one synchronous and three asynchronous modes. z Mode 0, synchronous mode z Mode 1, 8-bit UART, variable baud rate, Timer 1 clock source z Mode 2, 9-bit UART, fixed baud rate z Mode 3, 9-bit UART, variable baud rate, Timer 1 clock source Mode 2 and 3 has a special feature for multiprocessor communications. The feature is enabled by setting SM12 bit in SCON1 register. The master processor first sends out an address byte, which identifies the target slave. An address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte. With SM12 = 1, no slave will be interrupted by a data byte. An address byte will interrupt all slaves. The addressed slave will clear its SM12 bit and prepare to receive the data bytes that will be coming. The slaves that were not being addressed leave their SM12 set and ignoring the incoming data. The UART1 related registers are: SBUF1 (0xC1), SCON1 (0xC0), PCON (0x87), IE (0xA8) and IP (0xB8). The UART1 data buffer (SBUF1) consists of two separate registers: transmit and receive registers. A data writes into the SBUF1 sets this data in UART1 output register and starts a transmission. A data reads from SBUF1, reads data from the UART1 receive register. Writing to SBUF1 loads the transmit register, and reading SBUF0 reads a physically separate receive register. Figure 90: UART 1 Block Diagram 149 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY UART 1 Configuration register (SCON1, 0xC0) Bit Name Reset Value 7 SM10 Bit Name Access 0 RI1 R/W 1 TI1 R/W 2 RB18 R/W 3 TB18 R/W 4 5 6 REN1 SM12 SM11 R/W R/W 7 SM10 R/W 6 SM11 5 SM12 4 REN1 3 TB18 0x00 2 RB18 1 TI1 0 RI1 Description Receive interrupt flag, set by hardware after completion of a serial reception. Must be cleared by software. Transmit interrupt flag, set by hardware after completion of a serial transfer. Must be cleared by software. In Modes 2 and 3 it is the 9th data bit received. In Mode 1, if SM12 is 0, RB18 is the stop bit. In Mode 0 this bit is not used. The 9th transmitted data bit in Modes 2 and 3. Set or cleared by the CPU, depending on the function it performs (parity check, multiprocessor communication etc.) If set, enables serial reception. Cleared by software to disable reception. Enables a multiprocessor communication feature Sets baud rate Mode SM10 SM11 Description UART 0 Baud Rate 0 0 0 Shift register Fsys_clk/12 8-bit UART Variable. SMOD1 bit (PCON.6) Baud Rate 1 0 1 0 T1ov/32 1 T1ov/16 T1ov is Timer 1 overflow rate. 9-bit UART SMOD1 bit (PCON.6) Baud Rate 2 1 0 0 Fsys_clk//64 1 Fsys_clk/32 3 1 1 9-bit UART Variable, same as Mode 1 above Note: Fsys_clk is operating system clock frequency. The UART 1 interrupt enable register is ES1 bit (IE.6, 0xA8) for both RI1 and TI1 interrupt flags in SCON1. Its interrupt priority register is PS1 bit (IP.6, 0xB8). The RI1 and TI1 bits that generates interrupts can be set or cleared by software, with the same result as if they had been set or cleared by hardware. That is, interrupts can be generated or pending interrupts can be cancelled by software. Please refer to section 4.8 for details. UART 1 Buffer Register (SBUF1, 0xC1) 7 Bit Name Reset Value 6 5 4 3 2 1 Bit Name Access 7:0 SB1 0 SB1 0x00 Description A data writes into the SBUF1 sets this data in UART1 output register and starts a R/W transmission. A data reads from SBUF1, reads data from the UART1 receive register. 150 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Mode 0, Synchronous Mode Pin RXD1 serves as input and output. TXD1 output is a shift clock. The baud rate is fixed at 1/12 of the operating system clock frequency. Eight bits are transmitted with LSB first. Reception is initialized by setting the flags in SCON1 as follows: RI1 = 0 and REN1 = 1. Figure 91: UART 1, Mode 0 Transmit Timing Diagram Mode 1, 8-bit UART, Variable Baud Rate, Timer 1 Clock Source Pin RXD1 serves as input, and TXD1 serves as serial output. 10 bits are transmitted: a start bit (always 0), 8 data bits (LSB first), and a stop bit (always 1). On receive, a start bit synchronizes the transmission, 8 data bits are available by reading SBUF1, and stop bit sets the flag RB18 in the SCON1. The baud rate is variable and depends from Timer 1. Figure 92: UART 1, Mode 1 Transmit Timing Diagram 151 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Mode 2, 9-bit UART, Fixed Baud Rate This mode is similar to Mode 1 with two differences. The baud rate is fixed at 1/32 or 1/64 of CLK clock frequency, and 11 bits are transmitted or received: a start bit (0), 8 data bits (LSB first), a programmable 9th bit, and a stop bit (1). The 9th bit can be used to control the parity of the UART 1 interface: at transmission, bit TB18 in SCON1 is output as the 9th bit, and at receive, the 9th bit affects RB08 in SCON1. Figure 93: UART1, Mode 2 Transmit Timing Diagram Mode 3, 9-bit UART, Variable Baud Rate, Timer 1 Clock Source The only difference between Mode 2 and Mode 3 is that the baud rate is a variable in Mode 3. When REN1=1 data receiving is enabled. The baud rate is variable and depends from Timer 1. Figure 94: UART 1, Mode 3 Transmit Timing Diagram 152 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 4.12.4 UART 2 The UART 2 of AX11015 is designed to be maximally compatible with standard 16550. It provides serial communication capabilities, which allow communication with modem or other external device (e.g. computer) by using RS232 protocol. It contains 16-bytes deep transmit FIFO and receive FIFO and its transfer rate can be up to 921600 bps. It includes a programmable baud rate generator capable of dividing the operating system clock by (27*N), where N = 1~65535, for generating wide range of baud rate for the internal transmitter/receiver logic. Divisor Latch Registers Baud Generator Logic Line Control Register Line Status Register ReceiveLogic Receive - Shift Register RXD2 Receiver FIFO (16 bytes) FIFO Control Register Transmitter FIFO (16 bytes) Trans - Shift Register SFR BUS DE TransLogic Interrupt ID Register Interrupt Enable Register RE_N TXD2 Interrupt Logic RTS CTS Modem Status Register Modem Control Register Modem Status Register DTR DSR DCD RI INT_O Figure 95: UART 2 Block Diagram 153 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY The main features of UART 2 are listed below, z 16 bytes deep receive and transfer FIFO z Support up to 921600 bps baud z Detection of bad data in the receiver FIFO z Full-duplex asynchronous channel z Automatic send data control (ASDC) for automatically transmitter/receiver enable control for RS-485 z Modem control functions (CTS, RTS, DSR, DTR, RI and DCD) z Fully programmable serial interface - Even, odd, no parity bit generation and detection - 5, 6, 7, 8 data bit - 1, 1.5, 2 stop bit generation z Line break generation and detection z Internal diagnostic capabilities (loopback controls, break, parity, overrun and framing error) z Transmit, receive, line status, and data set interrupts independently controlled z Complete status reporting capabilities z Remote wakeup by detecting falling-edge transition (start bit) on RXD2 pin or falling-edge transition on RI pin Wakeup Function The UART 2 supports remote wakeup function. Upon detecting wakeup signals, it can wake up the CPU of AX11015 from PMM or STOP mode (with or without OSC/PLL turned off). The wakeup signals can be either a falling-edge transition (start bit) on RXD2 pin when receiving a byte of serial data or a falling-edge transition on RI pin from a modem ring signal. Note that because baud rate of UART 2 can be incorrect during PMM or STOP mode, therefore, the receiver FIFO normally requires a reset after wakeup to ensure proper operation. Upon detecting the wakeup signal, normally the system clock may need some time to become stable, so the UART 2 may not be able to receive serial data properly during this time period. Following describes the timing requirements for awaking from PMM and STOP modes. 154 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Case 1: Wakeup from STOP mode with 25Mhz oscillator and PLL completely stopped During this STOP mode with OSC/PLL stopped, the first receive serial data byte on RXD2 or a low pulse on RI is being used as wakeup event to awake up the CPU and will not be received correctly into receiver FIFO. To correctly receive the 2nd serial data byte on RXD2, it should be separated by at least 100us (operating system clock = 100Mhz), 200us (operating system clock = 50Mhz), or 400us (operating system clock = 25Mhz), respectively, from the first wakeup byte. Because after detecting the wakeup events, the internal system clock will need abovementioned time frame to resume running (to allow the internal OSC/PLL to become stabilized), any RXD2 activity within the mentioned time range will not be received properly. Also, after awaking up the CPU, the software should generate a FIFO reset command to reset the receiver FIFO via RFR bit (HS_FCR.1) after the first wakeup byte has been completely received through. Symbol Description 1 Falling-edge transition of the wakeup signal to the CPU leaving STOP mode. Operating System Clock 100 Mhz 50 Mhz 25 Mhz 2 The CPU leaving STOP mode to the time software should generate receiver FIFO reset to allow the wakeup byte to be completely received through. 3 The time software should generate receiver FIFO reset to the UART 2 ready to receive data. Note: 1. The byte time is the time period to receive one serial data byte. Min Typ Max Unit 100 200 400 3 us us us byte time (1) 10 system clocks Case 2: Wakeup from STOP mode with 25Mhz oscillator and PLL still running Symbol Description 1 Falling-edge transition of the wakeup signal to the CPU leaving STOP mode. Operating System Clock 100 Mhz 50 Mhz 25 Mhz 2 The CPU leaving STOP mode to the time software should generate receiver FIFO reset to allow the wakeup byte to be completely received through. 3 The time software should generate receiver FIFO reset to the UART 2 ready to receive data. Note: 1. The byte time is the time period to receive one serial data byte. Min Typ Max Unit 100 200 400 3 ns ns ns byte time (1) 10 system clocks Case 3: Wakeup from PMM mode with switchback enabled Symbol Description 1 Falling-edge transition of the wakeup signal to the CPU leaving PMM mode. 2 Operating System Clock 100 Mhz 50 Mhz 25 Mhz The CPU leaving PMM mode to the time software should generate receiver FIFO reset to allow the wakeup byte to be completely received through. 3 The time software should generate receiver FIFO reset to the UART 2 ready to receive data. Note: 1. The byte time is the time period to receive one serial data byte. Min Typ Max Unit 5 10 20 3 us us us byte time (1) 10 system clocks 155 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY UART 2 SFR Register Map Addres Name Access s 0xE1 HS_RTD HS_RBR RO 0xE1 HS _THR WO 0xE1 HS _DLLR R/W Description Receiver Buffer Register: Receiver FIFO output. Transmitter Holding Register: Transmit FIFO input. Divisor Latch Low Register: The LSB of the Divisor Latch Register. This register can be accessed after setting the 7th(DLAB) bit of the Line Control Register to 1. 0xE2 HS_ID HS _IER R/W Interrupt Enable Register: Enable/Mask Interrupts generated by UART. 0xE2 HS _DLHR R/W Divisor Latch High Register: The MSB of the Divisor Latch Register. This register can be accessed after setting the 7th(DLAB) bit of the Line Control Register to 1. 0xE3 HS_IF HS _IIR R Interrupt Identification Register: Get interrupt information. 0xE3 HS _FCR W FIFO Control Register: Control FIFO options. 0xE4 HS _LCR R/W Line Control Register: Control connection. 0xE5 HS _MCR W Modem Control Register: Control modem. 0xE6 HS _LSR R Line Status Register: Status information. 0xE7 HS _MSR R Modem Status Register: Modem Status. Note: The Divisor Latch Register is 16-bit register. It can be accessed after setting the 7th(DLAB) bit of the Line Control Register to 1. After finish setting Divisor Latch Register, please set the 7th(DLAB) bit of the Line Control Register to 0. Table 29: UART 2 SFR Register Map HS Receive Buffer Register (HS_RBR, 0xE1) 7 Bit Name Reset Value Bit 7:0 Name RBR 6 5 4 3 2 1 0 2 1 0 2 1 0 RBR 0x00 Access RO Description Receive Buffer Register only active at Reading. HS Transmit Holding Register (HS THR, 0xE1) 7 Bit Name Reset Value Bit 7:0 Name THR 6 5 4 3 THR 0x00 Access WO Transmit Holding Register. Description HS Divisor Latch Low Register (HS DLLR, 0xE1) 7 Bit Name Reset Value Bit 6 5 4 3 DLLR 0x00 Name Access 7:0 DLLR Description The LSB (7:0 bits) of the Divisor Latch Register. This register can be accessed after setting the 7th bit of LCR to `1'. You should set this bit to `0' after finish setting the divisor latches. R/W Divisor Latch Register is a 2 bytes register. The HS_DLHR (Divisor Latch High Register) register in conjunction with HS_DLLR (Divisor Latch Low Register) forms a 16-bit Divisor Latch Register that contains the baud rate divisor for the UART 2. The internal counter starts 156 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY to work when the LSB of Divisor Latch Register is written, so when setting the divisor, write the MSB first and the LSB last. The output baud rate is equal to the operating system clock frequency divided by (27 times the value of the baud rate divisor), shown as follows. Operating System Clock Frequency Baud Rate = 27 * Divisor Latch Register Following is suggested Divisor Latch Register value for different baud rate, Baud Rate 921600 115200 57600 38400 19200 9600 7200 4800 3600 Operating System Clock = 25 Mhz Divisor Latch Register Actual Baud 0x0001 925926 0x0008 115741 0x0010 57870 0x0018 38580 0x0030 19290 0x0060 9645 0x0081 7178 0x00c1 4798 0x0101 3603 Tolerance % 0.47% 0.47% 0.47% 0.47% 0.47% 0.47% 0.31% 0.05% 0.08% Baud Rate 921600 115200 57600 38400 19200 9600 7200 4800 3600 Operating System Clock = 50 Mhz Divisor Latch Register Actual Baud 0x0002 925926 0x0010 115741 0x0020 57870 0x0030 38580 0x0060 19290 0x00c1 9595 0x0101 7206 0x0182 4798 0x0202 3603 Tolerance % 0.47% 0.47% 0.47% 0.47% 0.47% 0.05% 0.08% 0.05% 0.08% Baud Rate 921600 115200 57600 38400 19200 9600 7200 4800 3600 Operating System Clock = 100 Mhz Divisor Latch Register Actual Baud 0x0004 925926 0x0020 115741 0x0040 57870 0x0060 38580 0x00c1 19190 0x0182 9595 0x0202 7206 0x0304 4798 0x0405 3599 Tolerance % 0.47% 0.47% 0.47% 0.47% 0.05% 0.05% 0.08% 0.05% 0.02% 157 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY HS Interrupt Enable Register (HS IER, 0xE2) 7 Bit Name Reset Value 6 Reserved Bit Name Access 0 RDI R/W 1 THRI R/W 2 RLSI R/W 3 MSI R/W 4 WE RW 5 WS CR 5 WS 4 WE 3 MSI 0x00 2 RLSI 1 THRI 0 RDI Description Received Data available interrupt. 1: Enabled. 0: Disabled. Transmitter Holding Register empty Interrupt. 1: Enabled. 0: Disabled. Receiver Line Status Interrupt. 1: Enabled. 0: Disabled. Modem Status Interrupt. 1: Enabled. 0: Disabled. Wakeup Enable to wakeup the CPU from PMM or STOP mode. Whenever RXD2 or RI pin become active (high to low transition), the UART 2 will generate interrupt to INT 6 to wakeup the CPU (and to re-enable OSC/PLL and system clock). 1: Enabled. 0: Disabled. Wakeup Status. 1: When reading back "1", this bit indicate that the CPU is awaked up by UART 2. 0: This bit will be cleared automatically after software reads it. 7:6 Reserved HS Divisor Latch High Register (HS DLHR, 0xE2) Bit Name Reset Value Bit 7:0 Name DLHR 7 6 5 4 3 2 1 DLHR 0x00 Access Description R/W The MSB (15:8 bits) of the Divisor Latch Register. See HS_DLLR for details. 158 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights 0 AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY HS Interrupt Identification Register (HS IIR, 0xE3) 7 Bit Name Reset Value 6 5 Reserved 1 0 1 4 0 3 BIT3 0 2 BIT2 0 1 BIT1 0 0 BIT0 1 Bit Name Access Description 0 BIT0 RO Please see Table 30 below for more description. 1 BIT1 RO 2 BIT2 RO 3 BIT3 RO 4 RO Always 0. 5 RO Always 0. Reserved 6 RO Always 1. 7 RO Always 1. Bit3 Bit2 Bit1 Bit0 Priorit Interrupt Type y 0 0 0 1 st 0 1 1 0 1 0 1 0 0 2nd 1 1 0 0 2nd 0 0 1 0 3rd 0 0 0 0 4th Interrupt Source Interrupt Reset Control None Receiver Line Status Receiver Data available Timeout Indication None Parity, Overrun or Framing errors or Reading the Line Status Break Interrupt Register FIFO trigger level reached FIFO drops below trigger level There's at least 1 character in the Reading from the FIFO FIFO but no character has been (Receiver Buffer Register) input to the FIFO or read from it for the last 4 Char times Transmitter Transmitter Holding Register Empty Writing to the Transmitter Holding Holding Register (HS_THR) Register empty or reading HS_IIR Modem Status CTS, DSR, RI or DCD Reading the Modem status register (HS_MSR) Table 30: UART2 Interrupt Identification Register HS FIFO Control Register (HS FCR, 0xE3) Bit Name Reset Value Bit 0 7 6 FITL 5 4 3 Reserved 1100_0001 2 TFR 1 RFR Name FIFOE 0 FIFOE Access Description WO This UART only supports FIFO mode, so always write 1 to this bit. Writing 1 to this bit clears the Receiver FIFO and resets its logic. But it doesn't clear the 1 RFR W1 shift register, receiving of the current character continues. This bit will be cleared by chip hardware automatically. Writing 1 to this bit clears the Transmitter FIFO and resets its logic. The shift register is 2 TFR W1 not cleared, transmitting of the current character continues. This bit will be cleared by chip hardware automatically. 5:3 Reserved WO FIFO Trigger level: Define the Receiver FIFO interrupt level. `00': 1 byte. 7:6 FITL WO `01': 4 bytes. `10': 8 bytes. `11': 14 bytes. 159 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY HS Line Control Register (HS LCR, 0xE4) 7 DLAB 0 Bit Name Reset Value Bit Name Access 0:1 NBPC R/W 2 NSB R/W 3 PE R/W 4 EPS R/W 5 SPB R/W 6 BCB R/W 7 DLA B R/W 6 BCB 0 5 SPB 0 4 EPS 0 3 PE 0 2 NSB 0 1 0 NBPC 11 Description The number of bits per character in each transmitted or received serial character. `00': 5 bits. `01': 6 bits. `10': 7 bits. `11': 8 bits. Specify the number of generated stop bits. Note that the receiver always checks the first stop bit only. 1: 1.5 stop bits when 5-bit character length selected and 2 bits otherwise. 0: 1 stop bit. Parity Enable. 1: Parity bit is generated on each outgoing character and is checked on each incoming one. 0: No parity. Even Parity select 1: Even number of logic 1 is transmitted in each word. 0: Odd number of logic1 is transmitted and checked in each word (data and parity combined). In other words, if the data has an even number of logic 1 in it, then the parity bit is logic 1. Stick Parity bit. 1: If bits 3 and 4 are logic 1, the parity bit is transmitted and checked as logic 0. If bit 3 is logic 1 and bit 4 is logic 0 then the parity bit is transmitted and checked as logic 1. 0: Stick Parity disabled. Break Control bit. 1: The serial out is forced into logic 0 (break state). 0: Break is disabled. Divisor Latch Access bit. 1: The divisor latches can be accessed. 0: The normal registers are accessed. HS Modem Control Register (HS MCR, 0xE5) 7 6 DEREC Bit Name Reset Value Bit Name Access 0 DTR WO 1 RTS WO 2 3 OUT1 OUT2 WO WO 4 LOOPB WO 5 Reserved 4 LOOPB 3 OUT2 0x00 2 OUT1 1 RTS 0 DTR Description Data Terminal Ready (DTR) Signal Control. 1: DTR will output logic 0. 0: DTR will output logic 1. Request To Send (RTS) signal control. 1: RTS will output logic 0. 0: RTS will output logic 1. Out1. In Loopback mode, connected to Ring Indicator (RI) signal input. Out2. In Loopback mode, connected to Data Carrier Detect (DCD) signal input. Loopback mode. 1: Loopback mode. When in loopback mode, the serial output signal (TXD2) is set to logic 1. The signal of the transmitter shift register is internally connected to the input of the receiver shift register. 160 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY The following connections are made during loopback mode: DTR I DSR RTS I CTS Out1 I RI Out2 I DCD 0: Normal operation. 5 Reserved Transceiver Driver Enable (DE pin) and Receiver Enable Control (RE_N pin): DEREC Mode 00 Sleep 01 Single Twisted Half Duplex 7:6 DEREC WO 10 DE pin RE_N pin DE keeps output logic 0 RE_N keeps output logic 1 Pair In this mode DE will RE_N will output logic 1 automatically output whenever transmitting data logic 1 whenever TX and output logic 0 when it FIFO is non-empty is not transmitting. Single Twisted Pair In this mode DE will RE_N keeps output logic 0 Half Duplex or Double automatically output Twisted Pair Full logic 1 whenever TX Duplex (Slave) FIFO is non-empty 11 Double Twisted Pair DE keeps output logic 1 RE_N keeps output logic 0 Full Duplex (Master) Note: The DE pin is high active, and RE_N pin is low active. HS Line Status Register (HS LSR, 0xE6) 7 FERR 0 Bit Name Reset Value Bit Name Access 0 DR RO 1 OE CR 2 PE CR 3 FE CR 4 BI CR 6 TEMT 0 5 THRE 0 4 BI 0 3 FE 0 2 PE 0 1 OE 0 0 DR 0 Description Data Ready (DR) indicator. 1: At least one character has been received and is in the FIFO. 0: No characters in the FIFO. Overrun Error (OE) indicator. 1: If the FIFO is full and another character has been received in the receiver shift register. If another character is starting to arrive, it will overwrite the data in the shift register but the FIFO will remain intact. The bit is cleared upon reading from the register. This will generates Receiver Line Status interrupt. 0: No overrun state. Parity Error (PE) indicator. 1: The character that is currently at the top of the FIFO has been received with parity error. The bit is cleared upon reading from the register. This will generate Receiver Line Status interrupt. 0: No parity error in the current character. Framing Error (FE) indicator. 1: The received character at the top of the FIFO did not have a valid stop bit. Of course, generally, it might be that all the following data is corrupted. The bit is cleared upon reading from the register. This will generate Receiver Line Status interrupt. 0: No framing error in the current character. Break Interrupt (BI) indicator 1: A break condition has been reached in the current character. The break occurs when the line is held in logic 0 for a time of one character (start bit + data + parity + stop bit). In that case, one zero character enters the FIFO and the UART2 waits for a valid start bit to receive next character. The bit is cleared upon reading from the register. This will generate Receiver Line Status interrupt. 161 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 5 THRE RO 6 TEMT RO 7 FERR CR 0: No break condition in the current character. Transmit FIFO is empty. 1: The transmitter FIFO is empty. This will generate Transmitter Holding Register Empty interrupt. The bit is cleared when data is being written to the transmitter FIFO. 0: Otherwise. Transmitter Empty indicator. 1: Both the transmitter FIFO and transmitter shift register are empty. The bit is cleared when data is being written to the transmitter FIFO. 0: Otherwise. 1: At least one parity error, framing error or break indications have been received and are inside the FIFO. The bit is cleared upon reading from the register. 0: Otherwise. HS Modem Status Register (HS MSR, 0xE7) 7 DCD 0 Bit Name Reset Value Bit Name Access 0 DCTS CR 1 DDSR CR 2 TERI CR 3 DDCD CR 4 5 6 7 CTS DSR RI DCD RO RO RO RO 6 RI 0 5 DSR 0 4 CTS 0 3 DDCD 0 2 TERI 0 1 DDSR 0 Description Delta Clear To Send (DCTS) indicator. 1: The CTS line has changed its state. Delta Data Set Ready (DDSR) indicator. 1: The DSR line has changed its state. Trailing Edge of Ring Indicator (TERI) detector. 1: The RI line has changed its state from low to high state. Delta Data Carrier Detect (DDCD) indicator. 1: The DCD line has changed its state. Complement of the CTS input or equals to RTS in Loopback mode. Complement of the DSR input or equals to DTR in Loopback mode. Complement of the RI input or equals to Out1 in Loopback mode. Complement of the DCD input or equals to Out2 in Loopback mode. 162 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights 0 DCTS 0 AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 4.13 GPIOs The AX11015 supports four 8-bit bi-directional, open-drain, general purpose input and output ports, namely, P0 [7:0], P1 [7:0], P2 [7:0] and P3 [7:0]. Each port bit can be individually accessed by bit addressable instructions. The driving strength of the GPIO ports is programmable (4mA or 8mA, via I2C Configuration EEPROM offset 0x04, see section 3.1.4 for details). The Table 31 below shows GPIO pin list. Pin P07 ~ P00 P17 ~ P10 P27 ~ P20 P37 ~ P30 I/O Polarity Ref. Clock B Operating system clock B Operating system clock B Operating system clock B Operating system clock Description Port 0 input/output, bi-directional pins. Port 1 input/output, bi-directional pins. Port 2 input/output, bi-directional pins. Port 3 input/output, bi-directional pins. Table 31: General Purpose I/O Ports Pins Description 4.13.1 GPIO SFR Register Map Address 0x80 0x90 0xA0 0xB0 Name P0 P1 P2 P3 Description Port0 Register. Port1 Register. Port2 Register. Port3 Register. Table 32: GPIO SFR Register Map Read and write accesses to the I/O ports are performed via their corresponding SFRs, namely, P0 (0x80), P1 (0x90), P2 (0xA0), and P3 (0xB0). Some port-reading instructions read the data register and others read the port's pin. The "Read-Modify-Write" instructions are directed to the data registers and are shown below. All the other instructions used to read a port exclusively read the port's pin. Instruction ANL ORL XRL JBC CPL INC, DEC DJNZ MOV Px.y, C CLR Px.y SETB Px.y Function description Logic AND. Logic OR. Logic eXclusive OR. Jump if bit is set and clear. Complement bit. Increment, decrement byte. Decrement and jump if not zero. Move carry bit to bit y of port x. Clear bit y of port x. Set bit y of port x. Table 33: Read-Modify-Write instructions 163 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY The port's pin logic and timing diagrams are shown in figures below. Px.y out Px.y Px.y in Figure 96: Ports Pin Logic Figure 97: Data Register Accessed by Read-Modify-Write Instructions Px Figure 98: Ports write timing diagram Px Figure 99: Ports read timing diagram 164 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Port0 Register (P0, 0x80) Bit Name Reset Value Bit Name 7:0 P0.[7:0] 7 P0.7 6 P0.6 5 P0.5 4 P0.4 3 P0.3 2 P0.2 1 P0.1 0 P0.0 2 P1.2 1 P1.1 0 P1.0 2 P2.2 1 P2.1 0 P2.0 2 P2.2 1 P2.1 0 P2.0 0xFF Access Description Write 1 then P0.y is tri-state. Write 0 then P0.y is low. R/W If P0.y is tri-state and P0.y_in = 0, then read P0.y is 0. If P0.y is tri-state and P0.y_in = 1, then read P0.y is 1. Port1 Register (P1, 0x90) Bit Name Reset Value Bit Name 7:0 P1.[7:0] 7 P1.7 6 P1.6 5 P1.5 4 P1.4 3 P1.3 0xFF Access Description Write 1 then P1.y is tri-state. Write 0 then P1.y is low. R/W If P1.y is tri-state and P1.y_in = 0, then read P1.y is 0. If P1.y is tri-state and P1.y_in = 1, then read P1.y is 1. Port2 Register (P2, 0xA0) Bit Name Reset Value Bit Name 7:0 P2.[7:0] 7 P2.7 6 P2.6 5 P2.5 4 P2.4 3 P2.3 0xFF Access Description Write 1 then P2.y is tri-state. Write 0 then P2.y is low. R/W If P2.y is tri-state and P2.y_in = 0, then read P2.y is 0. If P2.y is tri-state and P2.y_in = 1, then read P2.y is 1. Port3 Register (P3, 0xB0) Bit Name Reset Value Bit Name 7:0 P3.[7:0] 7 P2.7 6 P2.6 5 P2.5 4 P2.4 3 P2.3 0xFF Access Description Write 1 then P3.y is tri-state. Write 0 then P3.y is low. R/W If P3.y is tri-state and P3.y_in = 0, then read P3.y is 0. If P3.y is tri-state and P3.y_in = 1, then read P3.y is 1. 165 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 4.14 TCP/IP Offload Engine The TCP/IP Offload Engine (TOE) of AX11015 supports some network layer 2 to 4 header processing functions in hardware. The TOE block diagram is shown in below Figure 100. The TOE can operate in two different modes "Non-Transparent" mode and "Transparent" mode. DMA Engine TCP/UDP/ICMP/IGMP Header Parsing, Chksum Chk and Packet Filtering TCP/UDP/ICMP/IGMP Chksum Gen SFR registers SFR Bus IPv4 Header Parsing, Chksum Chk and Packet Filtering IPv4 Chksum Gen MAC Frame Header Encapsulation. ARP Cache MAC Frame Header Parser L4_Engine L3_Engine L2_Engine 10/100 Ethernet MAC Figure 100: TOE Block Diagram When TOE operating in "Transparent" mode, the L2_Engine is in transparent mode where hardware processing Ethernet MAC header is disabled. It supports following features, z VLAN ID filtering for received packets, if enabled z On-the-fly IPv4 packet header checksum check and generation (with or without PPPoE header, RFC2516) z Received packet filtering for IPv4 packets with error header checksum z On-the-fly TCP and UDP segment checksum check and generation z On-the-fly ICMP and IGMP message checksum check and generation z Received packet filtering for TCP/UDP/ICMP/IGMP packets with error checksum 166 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY When TOE operating in "Non-Transparent" mode, L2_Engine is actively processing Ethernet MAC header. It supports following features, z z z Layer-2 functions (the recognizable packet types are Ethernet II encapsulation (RFC894), IEEE 802.2/802.3 SNAP encapsulation (RFC1042), IEEE 802.2/802.3 encapsulation, and NetWare 802.3 RAW encapsulation) Ethernet MAC frame header parsing and encapsulation, including DA, SA, Length/Type, VLAN Tag fields. ARP Cache: When receiving, automatically learns the source IP address and SA of the received Ethernet MAC frames into ARP Cache SRAM When transmitting, automatically sends out ARP-Request packet when the ARP Cache is not found Upon receiving ARP-Request packet, automatically responds with ARP-Reply packet and updates ARP Cache Upon receiving ARP-Reply packet, automatically updates ARP Cache Software programmable timeout value for ARP Cache Timeout ARP Cache SRAM is software accessible VLAN ID filtering for received packets and VLAN Tag insertion for transmit packets, if enabled Received packet filtering for ARP-Request packet Remove layer 2 header of receive IPv4-type packets before forwarding up to Layer-3 function Append layer 2 header of transmit IPv4-type packets from Layer-3 function before passing down to Ethernet MAC Layer-3 functions: IPv4 header parsing, including version, header length, total length, protocol, header checksum, source IP address, destination IP address fields On-the-fly IPv4 header checksum check and generation (only when without PPPoE header bytes) Received packet filtering for IPv4 packets with version not equal to 4 or error header checksum Received packet filtering for IPv4 packets with wrong destination IP address (not equal to owned IP address, and not equal to broadcast IP address, and not equal to multicast IP address) and wrong source IP address (equal to broadcast IP address, or equal to multicast IP address) Layer 4 functions: On-the-fly TCP and UDP segment checksum check and generation On-the-fly ICMP and IGMP message checksum check and generation Received packet filtering for TCP/UDP/ICMP/IGMP packets with error checksum There are 5 different types of frame encapsulation that can be received from Ethernet MAC, namely, Ethernet II encapsulation (RFC894), IEEE 802.2/802.3 SNAP encapsulation (RFC1042), IEEE 802.2/802.3 encapsulation, NetWare 802.3 RAW encapsulation, and PPPoE encapsulation (RFC2516). In the first 4 encapsulation types there can be with or without VLAN Tag bytes. Therefore, this makes up total of 9 different encapsulation frame formats that can be received through TOE. Internal to TOE, it classifies packets into two types, "IP-type" packet and "Non-IP-type" packet. The "IP-type" packets are those with IPv4 header in it and are most commonly used in TCP/IP protocol stack. They include IP, TCP, UDP, ICMP, and IGMP packets, etc. In its layer 2 header, they may use Ethernet II encapsulation (RFC894), IEEE 802.2/802.3 SNAP encapsulation (RFC1042), or with addition PPPoE header (RFC2516). The "Non-IP-type" packets are those without IPv4 header, such as IPX, IPv6, ARP-Request, ARP-Reply, NETBIOS packets, etc. 167 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY When sending or receiving "IP-type" packets, the TOE can process the header information. When sending or receiving "Non-IP-type" packets, the TOE will bypass those packets and have software do the header processing jobs. Software configures xDATA memory of 1T 80390 CPU with two logical buffer rings, one buffer ring called Receive Packet Buffer Ring (RPBR) and another called Transmit Packet Buffer Ring (TPBR). When TOE receives packets from Ethernet MAC's receive buffer, the L2_Engine shall examine Ethernet header of the packet, the L3/L4_Engine will examine the packet's IPv4 header, validate the IP/TCP/UDP/ICMP/IGMP checksum and then en-queue the packet into RPBR via DMA transfer. Software will then be able to retrieve the packets out of the RPBR for further processing. On transmit direction, software first en-queues the packet into TPBR, it then instructs TOE to de-queue the packet out of TPBR via DMA transfer and move it to Ethernet MAC's transmit buffer. During this process, the TOE will calculate the IP/TCP/UDP/ICMP/IGMP checksum and append the Ethernet MAC header for the transmit packets. Following table summarizes how different packets are being processed in TOE. L2 Engine in Packet Type TOE Operation Transparent Mode IP-type Packets TOE retains Ethernet MAC header when receive or transmit and software can receive full packet data of receive packet. Software processes layer-2, layer-3, and layer-4 headers of the packets, but TOE performs IP/TCP/UDP/ICMP/IGMP checksum check and generation for packets with RFC894, RFC1042, and RFC2516 frame format. Packets treated as "IP-type" are: IP, TCP, UDP, ICMP, IGMP packets with RFC894 or RFC1042 frame format (with or without VLAN tag), or with PPPoE header (Eth Type = 8864, RFC2156). Non-IP-type Packets TOE bypasses processing these packets and retains Ethernet MAC header when receive or transmit. Software can receive full packet data of received packet and should process packet headers of transmit and receive packets. Packets treated as "Non-IP-type" are: IPX, IPv6, NETBIOS, ARP packets, or packets with PPPoE header (Eth Type = 8863). Non-Transparent Mode IP-type Packets TOE maintains the ARP function and processes ARP-Request and ARP-Reply packets. TOE strips out Ethernet MAC header when receive and appends Ethernet MAC header when transmit. Software processes layer-3 and layer-4 headers of the packets, but TOE performs IP/TCP/UDP/ICMP/IGMP checksum check and generation for packets with RFC894 and RFC1042 frame format. Packets treated as "IP-type" are: IP, TCP, UDP, ICMP, IGMP packets with RFC894 or RFC1042 frame format (with or without VLAN tag), and ARP-Request and ARP-Reply packets. Non-IP-type Packets TOE bypasses processing these packets and retains Ethernet MAC header when receive or transmit. Software can receive full packet data of received packet and should process packet headers of transmit and receive packets. Packets treated as "Non-IP-type" are: IPX, IPv6, NETBIOS, or packets with PPPoE header (Eth Type = 8863 or 8864). Table 34: TOE Operation Modes 168 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 4.14.1 TOE SFR Register Map Address 0xAE 0xAF Name TCIR TDR Description TOE Command Index Register is used to indicate the address of to-be accessed TOE register. TOE Data Register is used to read data from or write data to specified TOE register. Table 35: TOE SFR Register Map TOE Command Index Register (TCIR, 0xAE) Bit Name Reset Value 7 6 5 4 3 2 1 0 TCIR 0x00 Bit Name Access Description 7:0 TCIR WO Indicate which of the TOE register as listed in Table 36 is to be accessed. TOE Data Register (TDR, 0xAF) Bit Name Reset Value 7 6 5 4 3 2 1 0 TDR 0x00 Bit Name Access Description 7:0 TDR R/W Data Register is used to write data to or read data from the TOE registers. TOE Register Indirect Access Method Software shall use indirect access method through TCIR and TDR registers to do read and write access to the TOE registers as listed in Table 36 below. Read a register from TOE: Step 1. Write TCIR: Software indicates the TOE register address to be accessed as the data and write it to the SFR register TCIR. Step 2. Read TDR: Software then read SFR register TDR. The data read from TDR is the TOE register data indicated in step 1. Keep reading from TDR if the TOE registers have more than one byte, in that case, the first byte being read back is LSB byte. Write a register to TOE: Step 1. Write TDR: Software writes the data you want to write into TOE registers to the SFR register TDR. Keep writing to TDR if the TOE registers have more than one byte, in that case, the first byte being written should be LSB byte. Step 2. Write TCIR: After writing TOE register data to TDR, software then indicates the target TOE register address as data and write it to TCIR. Note: While software is reading or writing TOE Registers during a sequence of SFR accesses, software can abort that process by writing TCIR with 0xFF. 169 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY TOE Register Map Address Register Name 0x00 0x01 0x02 0x04 0x06 0x07 0x08 0x0E TL2CR Reserved TRVTR TTVTR TACSR TACAR TACDR TACTR 0x10 0x14 0x18 0x1C TSIAR TSMR TDGIAR TCSR 0x20 0x21 0x22 0x24 TL4CR TL4CMR TL4BDPR TL4DGR 0x30 0x31 TSR TIER Description Layer 2 Related TOE L2 Control Register TOE RX VLAN Tag Register (16 bits) TOE TX VLAN Tag Register (16 bits) TOE ARP Cache Command Status Register TOE ARP Cache Address Register TOE ARP Cache Data Register (48 bits) TOE ARP Cache Timeout Register Layer 3 Related TOE Source IP Address Register (32 bits) TOE Subnet Mask Register (32 bits) TOE Default Gateway IP Address Register (32 bits) TOE Checksum Status Register Layer 4 Related TOE L4 Control Register TOE L4 Command Register TOE L4 BDP pointer Register (16 bits) TOE L4 DMA Transfer Gap Register Interrupt and Status Related TOE Status Register TOE Interrupt Enable Register Table 36: TOE Register Map 4.14.2 L2_Engine Function Description ARP Cache The ARP Cache SRAM as shown in Figure 101 supports up to 128 entries. Each entry stores the one-to-one mapping information of IP address and its associated MAC address. There is a timer value stored in each entry, which is used for cache timeout purpose. When this timer value reaches a predefined value set by software in TACTR register, it will cause the entry to be flushed out and become invalid (by making the "valid" bit to `0'). When L2_Engine operates in Non-Transparent mode, the ARP Cache Arbiter arbitrates access request to ARP Cache SRAM among software, the Cache timeout timer, during receiving packet, and during sending out packet. Software can write or read to ARP Cache SRAM to create or delete a static entry, which will never time out. The Cache timeout timer is used to flush out the dynamic entries in the Cache SRAM whenever the entries are not being refreshed for a predefined time period. This timeout period is software programmable. When receiving an "IP-type" packet from Ethernet MAC, the ARP Cache SRAM will be accessed once to refresh the timer for the entry corresponding to the received source IP address of the packet. When sending out an "IP-type" packet, the ARP Cache SRAM will be accessed once to retrieve the destination MAC address of the transmit packet, based on the destination IP address provided by L3 Engine. Note that when transmitting "Non-IP-type" packets, software should provide full MAC header in the packet and should not rely on L2_Engine to search into ARP Cache SRAM. In fact, these types of packet contain no valid destination IP address. 170 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY The ARP Cache SRAM supports up to 128 entries. Its address has [7:0] bits, within which the [7:1] bits are the Hash Key for indexing the 128 entries. The Hash Key is first generated based on "Linear Addressing" mode by using the lower 7 bits of the given IP address. Hash Key [7:1] bit = IP address [6:0] If the hash collision occurs, then the "XOR Addressing" mode is used next. The XOR Addressing mode is calculated as follows, Hash Key [7] bit = IP address [31] ^ [23] ^ [15] ^ [7] Hash Key [6] bit = IP address [30] ^ [22] ^ [14] ^ [6] Hash Key [5] bit = IP address [29] ^ [21] ^ [13] ^ [5] Hash Key [4] bit = IP address [28] ^ [20] ^ [12] ^ [4] Hash Key [3] bit = IP address [27] ^ [19] ^ [11] ^ [3] Hash Key [2] bit = IP address [26] ^ [18] ^ [10] ^ [2] Hash Key [1] bit = IP address [25] ^ [17] ^ [9] ^ [1] Entry #0 valid static 500ms_timer [45:32] ip_addr [31:0] mac_addr [47:0] Entry #127 valid static 500ms_timer [45:32] ip_addr [31:0] mac_addr [47:0] Note: 1. The "valid" bit indicates that the entry is valid. 2. The "static" bit means the entry is a static and fixed entry, which will not get expired. When software needs to configure the static ARP cache, set this bit to "1". 3. The "500ms_timer" field is the number of count the 500ms ARP Cache Timeout Timer has ticked so far. This counter number is increased by "1" on every 500ms. 4. The "ip_addr" field is the IP address values. 5. The "mac_addr" field is the MAC address values. Figure 101: ARP Cache SRAM Memory Map ARP Request and ARP Reply Packet Processing When L2_Engine operates in Non-Transparent mode, upon receiving an ARP Request packet from Ethernet MAC with "Target IP address" matching with IP address of this chip set in TSIAR, the L2_Engine will automatically reply with ARP-Reply packet. At the same time, it will use the "Sender Ethernet address" and "Sender IP address" in the received ARP packet to update the entry for this packet in ARP Cache SRAM. When receiving an ARP Reply packet from Ethernet MAC, the L2_Engine will save the "Sender Ethernet address" and "Sender IP address" and then update the entry for this packet in ARP Cache SRAM. 171 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY IP Address Translation Upon receiving "IP-type" packets, ARP-Request and ARP-Reply packets from Ethernet MAC, the L2_Engine will use the packet's source IP address if the IP address is within the same subnet. Otherwise, if it is not within the same sub-net (by comparing with the subnet mask) and the default gateway's IP address != 0.0.0.0 (provided in TDGIAR), then it will use the default gateway's IP address to generate the Hash Key for looking up ARP Cache SRAM. This can conserve the ARP Cache entry usage. When transmitting "IP-type" packets to Ethernet MAC, the L2_Engine will check the destination IP address of the packet based on following rules to generate correct DA field of Ethernet MAC header. If the look-up fails two times, meaning the entry for the given destination IP address does not exist, the packet will be discarded and this event will be reported to software and an ARP-Request packet will be sent out automatically instead. Destination IP Address DA Field Generation Rule If equal to broadcast destination IP address Use DA = FFFF_FFFF_FFFF without looking up to the ARP Cache SRAM. If equal to multicast IP address Use DA={01005e, {0, Dest_IP[22:0]}} without looking up to the ARP Cache SRAM. If equal to unicast IP address Use the packet's destination IP address to look up to ARP Cache SRAM if the IP address is within the same subnet. Otherwise, if it is not within the same sub-net (by comparing with the subnet mask) and the default gateway's IP address != 0.0.0.0 (provided in TDGIAR), then use the default gateway's IP address to look up to ARP Cache SRAM. Table 37: DA Field Generation Rule in Transmit Direction TOE L2 Control Register (TL2CR, 0x00) 7 6 5 4 3 2 1 0 TX_SO TX_SNAP_ TX_TRANS TX_VLAN_ RX_SO Reserved RX_TRANS RX_VLAN_ EN EN EN 0 0 0 0 0 0 0 0 Reset Value Bit Name Bit Name Access Description 0 RXVLAN R/W RX VLAN Enable. _EN 1: Setting "1" enables the receiving of VLAN-tagged frame on L2_Engine RX direction, when the TCI byte of received VLAN-tagged frame is matched with TRVTR register and the ETPID is equal 8100 (hex). 0: Setting "0" causes all VLAN-tagged frame to be discarded by L2_Engine. 1 RX_TRAN R/W RX Transparent. S 1: Setting "1" enables the transparent mode on L2_Engine RX direction, which allows entire MAC frame of "IP-type" packets and ARP packets to be passed up to software. 0: Setting "0" enables L2_Engine function and causes the MAC frame header of "IP-type" packets and ARP-Request packets to be removed by L2_Engine and not being passed up to software. 2 Reserved R/W For normal operation, set to "0". 3 RX_SO R/W RX Start Operating. 1: Setting "1" enables the operation of RX path of L2/L3/l4 Engine. 0: Setting "0" disables the operation of RX path of L2/L3/l4 Engine. 4 TXVLAN_ R/W TX VLAN Enable. EN 1: Setting "1" enables the VLAN Tag byte insertion on L2_Engine TX direction, and the content in TTVTR register is used to fill in the TCI bytes of transmitted VLAN-tagged frame. 172 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 5 TX_TRAN S 6 TX_SNAP _EN 7 TX_SO 0: Setting "0" disables VLAN Tag byte insertion. R/W TX Transparent. 1: Setting "1" enables the transparent mode on L2_Engine TX direction, which means the software is responsible for inserting MAC header for "IP-type" packets and generating ARP packets. 0: Setting "0" enables L2_Engine function, which allows L2_Engine to insert Ethernet MAC header for IP-type packets. R/W 1: Setting "1" enables 802.2/802.3 SNAP encapsulation (RFC1042) mode on L2_Engine TX direction. 0: Disables SNAP encapsulation on L2_Engine TX direction. R/W TX Start Operating. 1: Setting "1" enables the operation of TX path of L2/L3/l4 Engine. 0: Disables the operation of TX path of L2/L3/l4 Engine. Following is the truth table of L2_Engine RX settings and its behavior. Bit Settings Resultant Packet Receive Conditions RX_TR RX_VL When receiving packets of Ethernet II, When receiving packets of Ethernet II, ANS AN_EN SNAP, or Non-IP-type without VLAN Tag SNAP, or Non-IP-type with VLAN Tag 0 0 The "IP-type" packets will be received but All 3 types of packet will be dropped. the L2 header will be removed before passing up to software. 0 1 1 0 1 1 The "non-IP-type" packets will be received and full packet will be passed up to software. The "IP-type" packets will be received but The "IP-type" packets with ETPID = 8100 and the L2 header will be removed before passing TCI byte of received VLAN-tagged frame up to software. matching with TRVTR register or with VID = 0x000 will be received, but the L2 header will The "non-IP-type" packets will be received be removed before passing up to software. and full packet will be passed up to software. The "non-IP-type" packets with ETPID = 8100 and TCI byte of received VLAN-tagged frame matching with TRVTR register or with VID = 0x000 will be received and full packet will be passed up to software. Packets with other TCI byte values will be dropped. All 3 types of packet will be received and the All 3 types of packet will be dropped. full packet will be passed up software. All 3 types of packet will be received and the Packets with ETPID = 8100 and TCI byte of full packet will be passed up software. received VLAN-tagged frame matching with TRVTR register or with VID = 0x000 will be received, and the full packet will be passed to software. Packet with other TCI byte values will be dropped. Table 38: L2_Engine RX Truth Table 173 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Following is the truth table of L2_Engine TX settings and its behavior. Bit Settings Resultant Packet Transmit Conditions TX_TR TX_VLA TX_SNAP ANS N_EN _EN 0 0 0 Send IP-type packets with Ethernet II without VLAN Tag and without SNAP. Send Non-IP transparently. 0 0 1 Send IP-type packets with Ethernet II with SNAP, but without VLAN Tag. Send Non-IP transparently. 0 1 0 Send IP-type packets with Ethernet II with VLAN Tag (ETPID = 8100 and TCI byte = TTVTR), but without SNAP. Send Non-IP transparently. 0 1 1 Send IP-type packets with Ethernet II with VLAN (ETPID = 8100 and TCI byte = TTVTR), and with SNAP. Send Non-IP transparently. 1 0 0 Send IP-type packets with Ethernet II transparently. Software is responsible for adding the Ethernet II header for every transmitted packet. Send Non-IP transparently. 1 0 1 Send IP-type packets with Ethernet with SNAP transparently. Software is responsible for adding the Ethernet II and SNAP header for every transmitted packet. Send Non-IP transparently. 1 1 0 Send IP-type packets with Ethernet with VLAN transparently. Software is responsible for adding the Ethernet II and VLAN header for every transmitted packet. Send Non-IP transparently. 1 1 1 Send IP-type packets with Ethernet with VLAN and SNAP transparently. Software is responsible for adding the Ethernet II, VLAN, and SNAP header for every transmitted packet. Send Non-IP transparently. Table 39: L2_Engine TX Truth Table TOE RX VLAN Tag Register (TRVR, 0x02) Bit Name Reset Value 7 6 5 4 TCI 0 3 2 1 0 Reserved TCI 1 Reset value is determined by the I2C EEPROM Bit Name Access Description 7:0 TCI 0 R/W The TCI 1~0 represents the VLAN ID of Tag Control Information bytes of VLAN-tagged 11:8 TCI 1 frame. When setting RX_VLAN_EN bit (TL2CR.0) to "1", the content in this register is used to compare against TCI byte of received VLAN-tagged frame. Only when matched, the received VLAN-tagged frame is passed up to software. Note that a special case of VID = 0x000 in received VLAN-tagged frame will also be passed up to software. 174 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY TOE TX VLAN Tag Register (TTVTR, 0x04) 7 Bit Name 6 Reset Value 5 4 3 2 TCI 0 TCI 1 Reset value is determined by the I2C EEPROM 1 0 Bit Name Access Description 7:0 TCI 0 R/W The TCI 1~0 represents the Tag Control Information bytes of VLAN-tagged frame. When 15:8 TCI 1 TX_VLAN_EN bit (TL2CR.4) = "1", the content in this register is used to insert the TCI byte of transmitted VLAN-tagged frame. TOE ARP Cache Command Status Register (TACSR, 0x06) Bit Name Reset Value 7 6 Bit Name Access 0 READ R/W 1 GO W1/R 5 4 Reserved 00_0000 3 2 1 GO 0 0 READ 1 Description 1: Setting READ bit to "1" indicates to read from ARP Cache SRAM. 0: Setting to "0"indicates to write to ARP Cache SRAM. 1: Setting GO to "1" initiates the ARP Cache SRAM read or write access request to the internal Cache SRAM arbiter. This bit will remain "1" while the access request is still in progress. 0: Arbiter hardware automatically clears this bit after current access request is completed. TOE ARP Cache Address Register (TACAR, 0x07) 7 Bit Name Reset Value Bit Name 7:0 SRAM_ADDR 6 5 4 3 SRAM_ADDR 0x00 2 1 0 1 0 Access Description R/W The read or write address of the ARP Cache SRAM. TOE ARP Cache Data Register (TACDR, 0x08) Bit Name 7 6 5 4 3 CACHE_DATA 0 CACHE_DATA 1 CACHE_DATA 2 CACHE_DATA 3 CACHE_DATA 4 CACHE_DATA 5 0x0000_0000_0000 Reset Value 2 Bit Name Access Description 7:0 CACHE_DATA R/W The CACHE_DATA 5~0 is the content of the ARP Cache SRAM where ... 0 CACHE_DATA 5 represents bit 47~40 of the ARP Cache SRAM while 47:40 ... CACHE_DATA 0 represents bit 7~0. When writing to the ARP Cache SRAM, CACHE_DATA software needs to first write desired data into this register before issuing TACSR 5 register. When reading from the ARP Cache SRAM, software first issues TACSR register and then retrieves the SRAM data from this register. 175 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY TOE ARP Cache Timeout Register (TACTR, 0x0E) 7 Bit Name Reset Value Bit Name 7:0 ARP_TIMEOUT 6 5 4 3 2 ARP_TIMEOUT Reset value is determined by the I2C EEPROM 1 0 Access Description R/W Software setting of ARP cache timeout value. Each count is about 8 sec in time. For example, 0x01 = 8 sec. 0x02 = 16 sec. The maximum timeout is 2040 sec which is 34 min. 4.14.3 L3_Engine Function Description The L3_Engine parses IPv4 header in received packets, recalculates the checksum of IPv4 header and compares it with received checksum bytes. The packets with wrong IP header checksum can be discarded by this block. The block also calculates and inserts the checksum for the transmitted IP header. When L2_Engine in Non-Transparent mode, the L3 Engine will discard following received IP-type packets: z Ethernet Type = 0800 but IP version != 4 z IP header checksum error z Wrong destination IP address (not equal to source IP address of this chip in TSIAR register, and not equal to broadcast IP address, and not equal to multicast IP address). The valid broadcast IP in destination IP address fields are: z Limited broadcast: 255.255.255.255 Net-directed broadcast for class A: 0 + Net_ID (7 bits) + Host_ID (24 bits), where Host_ID = All ones Net-directed broadcast for class B: 10 + Net_ID (14 bits) + Host_ID (16 bits), where Host_ID = All ones. Net-directed broadcast for class C: 110 + Net_ID (21 bits) + Host_ID (8 bits), where Host_ID = All ones. Subnet-directed broadcast: Net_ID + Subnet_ID + Host_ID, where Subnet_ID is a specific number and Host_ID = All ones. All subnet-directed broadcast: Net_ID + Subnet_ID + Host_ID, where Subnet_ID = All ones, and Host_ID = All ones. Wrong source IP address (equal to broadcast IP address, or equal to multicast IP address) TOE Source IP Address Register (TSIAR, 0x10) Bit Name Reset Value 7 6 5 4 3 2 IP_ADDR 0 IP_ADDR 1 IP_ADDR 2 IP_ADDR 3 Reset value is determined by the I2C EEPROM 1 0 Bit Name Access Description 7:0 IP_ADDR 0 R/W The IP_ADDR 3~0 is the IP address of this device where IP_ADDR 3 represents bit ... ... 31~24 of IP address while IP_ADDR 0 represents bit 7~0. 31:24 IP_ADDR 3 176 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY TOE Subnet Mask Register (TSMR, 0x14) 7 Bit Name 6 5 4 3 2 SUBNET_MASK 0 SUBNET_MASK 1 SUBNET_MASK 2 SUBNET_MASK 3 Reset value is determined by the I2C EEPROM Reset Value Bit 7:0 ... 31:24 1 0 Name Access Description SUBNET_MASK 0 R/W The SUBNET_MASK 3~0 is the IP subnet mask of this device where ... SUBNET_MASK 3 represents bit 31~24 of subnet mask while SUBNET_MASK 3 SUBNET_MASK 0 represents bit 7~0. TOE Default Gateway IP Address Register (TDGIAR, 0x18) 7 Bit Name 6 5 Reset Value Bit 7:0 ... 31:24 4 3 GATEWAY_IP 0 GATEWAY_IP 1 GATEWAY_IP 2 GATEWAY_IP 3 0x0000_0000 2 1 0 Name Access Description GATEWAY_IP 0 R/W The GATEWAY_IP 3~0 is the default gateway's IP address of this device. ... The GATEWAY_IP 3 represents the bit 31~24 of the default gateway's IP GATEWAY_IP 3 address while GATEWAY_IP 0 represents bit 7~0. TOE Checksum Status Register (TCSR, 0x1C) Bit Name Reset Value Bit Name 0 L3CSER 3:1 Reserved 4 L4CSER 7 6 Reserved 000 5 4 L4CSER 0 3 2 Reserved 000 1 0 L3CSER 0 Access Description CR L3 CheckSum ERror. 1: When reading "1", this bit indicates that there is at least one received packet with its IP header checksum error. 0: No IP header checksum error is found so far. CR L4 CheckSum ERror. 1: When reading "1", this bit indicates that there is at least one received packet with its TCP or UDP or ICMP or IGMP packet checksum error. 0: No TCP or UDP or ICMP or IGMP packet checksum error is found so far. 7:5 Reserved 177 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 4.14.4 L4_Engine Function Description The L4_Engine parses the TCP/ UDP/ICMP/IGMP header of received packets, recalculates checksum of received packet and then compares with received checksum. The packets with wrong checksum can be discarded by this block. This block also calculates and inserts the TCP/UDP/ICMP/IGMP checksum for the transmitted packets. TOE L4 Control Register (TL4CR, 0x20) Bit Name Reset Value 7 6 5 4 Reserved 0000 3 ETCB 0 2 ERCB 0 1 EHCI 1 0 DPCE 1 Bit Name 0 DPCE Access Description R/W Drop Packet with Checksum Error. 1: Setting "1" enables TCP/UDP/ICMP/IGMP packet with checksum error to be dropped by L4 Engine. 0: Setting "0" allows those packets with checksum error to be received into RPBR. 1 EHCI R/W Enable Hardware Checksum Insertion. 1: Setting "1" enables hardware to generate and insert the Layer 3 and Layer 4 checksum fields for transmitted TCP/UDP/ICMP/IGMP packet. 0: Disables checksum insertion. 2 ERCB R/W Enable Receive packet to Cross RPBR Boundary. 1: Setting "1" enables receive packets to be stored in buffer pages crossing REPP boundary in RPBR, which allows the packet storing in xDATA memory as a ring fashion, i.e., non-contiguous memory range. Please refer to section 4.14.5 for RPBR description. 0: Setting "0" indicates that the receive packets are always stored in xDATA memory as non-ring fashion, i.e., contiguous memory range. 3 ETCB R/W Enable Transmit packet to Cross TPBR Boundary. 1: Setting "1" enables transmit packets to be stored in buffer pages crossing TEPP boundary in TPBR, which allows the packet storing in xDATA memory as a ring fashion, i.e., non-contiguous memory range. Please refer to section 4.14.5 for TPBR description. 0: Setting "0" to indicate that the transmit packets are always stored in xDATA memory as non-ring fashion, i.e., contiguous memory range. 7:4 Reserved R/W TOE L4 Command Register (TL4CMR, 0x21) Bit Name Reset Value 7 6 Reserved 5 4 SP 3 2 Reserved 1 0 RPR 0x00 Bit Name 0 RPR Access Description W1/R Resume Packet Receive. 1: Software can set this bit to "1" to resume the packet receive process on the entire RX direction of TOE. This is normally used after the entire RX direction of TOE is halted due to RPBR full condition and the software has de-queued some packets in a previously full RPBR. 0: This bit will be cleared to "0" after the L4 resumes packet receiving process. 3:1 Reserved R/W 4 SP W1/R Send Packet. 1: Setting this bit "1" tells the L3/L4 Engine to de-queue one packet from the TPBR based on the BDP in TL4BDPR register. This bit will remain "1" until the L4 Engine completes sending out the packet. 0: L4 Engine when done transmitting will clear this bit to "0" automatically. 7:5 Reserved R/W 178 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY TOE L4 BDP Pointer Register (TL4BDPR, 0x22) 7 Bit Name 6 5 4 BDPP 0 BDPP 1 0x0000 Reset Value Bit 7:0 15:8 Name BDPP 0 BDPP 1 3 2 1 0 Access Description R/W Software shall configure this register with the BDP pointer of the packet buffer ring so that when a packet is received or transmitted, the L4 Engine knows where the RPBR or TPBR in CPU's xDATA Memory. Please refer to section 4.14.5 for BDP description. TOE L4 DMA Transfer Gap Register (TL4DGR, 0x24) Bit Name Reset Value 7 6 5 4 3 2 DMA_GAP Reset value is determined by the I2C EEPROM 1 0 Bit Name Access Description 7:0 DMA_GA R/W Software setting of time gap between each 256 bytes of DMA write/read transfer during P packet receive or transmit. Each count is 64 system clocks. For example, 0x01 = 64 system clocks. 0x02 = 128 system clocks. The maximum time gap is 16320 system clocks. TOE Status Register (TSR, 0x30) Bit Name Reset Value 7 Reserved 6 CSP 5 TPBRE 4 ACNF 3 Reserved 0x00 2 RPBRF 1 RPBRNE Bit Name 0 ACHC 1 2 3 4 5 0 ACHC Access Description CR ARP Cache Hashing Collision. 1: When reading "1", this bit indicates that the keys (after both Linear Addressing and XOR Addressing schemes are used as search key) being used to hash the ARP Cache SRAM have returned with result that the entries are pre-occupied by other IP address. 0: No ARP Cache hash collision. RPBRNE CR RX Packet Buffer Ring is Not Empty. 1: When reading "1", this bit indicates that there is at least one packet being stored in RPBR. 0: RPBR is empty. RPBRF CR RX Packet Buffer Ring is Full. 1: When reading "1", this bit indicates that the RPBR in TL4BDPR register has encountered buffer full condition. Most likely reason is that the L3/L4 Engine is receiving a packet into RPBR and there are no enough free pages to store the received packet. 0: RPBR is not full. Reserved R ACNF CR ARP Cache Not Found. 1: When reading "1", this bit indicates that the destination MAC address of the packet currently being sent can not be found in ARP Cache SRAM (after both Linear Addressing and XOR Addressing schemes are used as search key) and an ARP-Request packet has been sent out instead. 0: Normal status. TPBRE CR TX Packet Buffer Ring is Empty. 179 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 6 CSP 7 Reserved CR 1: When reading "1", this bit indicates that TPBR in TL4BDPR register is empty. Most likely reason is that the software has not stored any packets in TPBR before setting the SP bit (TL4CMR.4) to ask L4 Engine to send out one packet. 0: TPBR is not empty. L4/L3 Engine has Completed sending out one Packet on TX. 1: When reading "1", after software sets the "SP" bit (TL4CMR.4), this bit indicates that the L4/L3 Engine has completed sending out one packet on TX. 0: TOE TX is still sending packet or in idle state. R TOE Interrupt Enable Register (TIER, 0x31) 7 6 5 4 Bit Reserved EI_CSP EI_TPBRE EI_ACNF Name Reset Value 3 Reserved 0x00 2 EI_RPBRF 1 0 EI_RPBRNE EI_ACHC Bit Name 0 EI_ACHC Access Description R/W Enable Interrupt whenever there is ARP Cache Hashing Collision. 1: Enables generating interrupt to INT4 whenever ACHC flag is set. 0: Disables interrupt. 1 EI_RPBRNE R/W Enable Interrupt when RPBR is Not Empty. 1: Enables generating interrupt to INT4 whenever RPBRNE flag is set. 0: Disables interrupt. 2 EI_RPBRF R/W Enable Interrupt when RPBR is Full. 1: Enables generating interrupt to INT4 whenever RPBRF flag is set. 0: Disables interrupt. 3 Reserved R/W 4 EI_ACNF R/W Enable Interrupt whenever there is ARP Cache Not Found. 1: Enables generating interrupt to INT4 whenever ACNF flag is set. 0: Disables interrupt. 5 EI_TPBRE R/W Enable Interrupt for TPBR Empty condition. 1: Enables generating interrupt to INT4 whenever TPBRE flag is set. 0: Disables interrupt. 6 EI_CSP R/W Enable Interrupt whenever L4/L3 Engine completes sending out one packet on TX. 1: Enables generating interrupt to INT4 whenever CSP flag is set. 0: Disables interrupt. 7:6 Reserved R/W 180 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 4.14.5 Packet Buffer Ring in xDATA Memory of 1T 80390 CPU During software initialization, software is responsible for partitioning the CPU xDATA memory into several logical memory pages (in terms of 256 bytes boundary). The packet buffer ring requires 1 Buffer Descriptor Page and 2 Packet Buffer Rings each having N pages (one Receive Packet Buffer Ring and one Transmit Packet Buffer Ring). This is as shown in Figure 102 below. The Buffer Descriptor Page is used for storing buffer pointers. The RX/TX Packet Buffer Rings are used for storing actual packet data in a circular buffer fashion. Software shall configure Start Page Pointer and End Page Pointer of both RX and TX Packet Buffer Rings in Buffer Descriptor Page, to indicate the boundary of the two packet buffer rings. 0x00_0000 0x00_00FF 0x00_0100 0x00_01FF 0x00_0200 Memory Pages used as RX and TX Packet Buffer 0x00_02FF 0x??_??00 Buffer Descriptor Page (BDP), 1 page = 256 bytes space 0x??_??FF Buffer Descriptor Page Pointer (BDPP) RX Start Page Pointer (RSPP) Receive Packet Buffer Ring (RPBR), N pages = Nx256 bytes space 0x??_??00 0x??_??FF Memory space for misc. software variables Transmit Packet Buffer Ring (TPBR), N pages = Nx256 bytes space RX End Page Pointer (REPP) TX Start Page Pointer (TSPP) TX End Page Pointer (TEPP) Figure 102: The External Data (xDATA) Memory of CPU The detailed pointer definition in BDP page is shown in Figure 103. Software should initialize these pointers prior to enabling TOE to active mode. During normal operation, some pointer fields are being updated by software and some are being updated by L4_Engine. The RPBR and TPBR packet buffer area can operate in a ring fashion or non-ring fashion. This is programmable by software via ERCB bit (TL4CR.2) and ETCB bit (TL4CR.3). Using ring fashion allows xDATA memory use more efficient but may require slightly more complex software driver code. Using non-ring fashion makes software driver code slightly simpler but may waste memory. The two examples of RPBR and TPBR operating in ring fashion are shown in Figure 104 and Figure 105. The detailed pointer and data structure of RPBR and TPBR is described in section 4.14.6. 181 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Offset 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C BDP No Reserved RSPP [15:8] RSPP [7:0] REPP [15:8] REPP [7:0] RHPR [15:8] RHPR [7:0] RTPR [15:8] RTPR [7:0] RFP [7:0] Reserved 0x7F 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A TSPP [15:8] TSPP [7:0] TEPP [15:8] TEPP [7:0] THPR [15:8] THPR [7:0] TTPR [15:8] TTPR [7:0] TFP [7:0] Reserved 128 bytes Reserved 128 bytes Reserved 0xFF Offset 0x00 0x02~03 0x04~05 0x06~07 0x08~09 0x0A 0x80~81 0x82~83 0x84~85 0x86~87 0x88 Name Description BDP No The number of this Buffer Descriptor Page. This number is filled by the software to identify the BDP in the CPU's xDATA memory. RSPP RX Start Page Pointer of RX Packet Buffer Ring (RPBR), indicating the beginning page of the RPBR in the xDATA memory. REPP RX End Page Pointer of RPBR, indicating the ending page of RPBR in the xDATA memory. RHPR RX Head Pointer of RPBR, pointing to the first page of first packet in RPBR. Initial value = RSPP. During packet receive process, software shall always de-queue the packet pointed by RHPR and then update RHPR to point to next packet once done de-queuing one packet. RTPR RX Tail Pointer of RPBR, pointing to the next empty page in RPBR. Initial value = RSPP. During packet receive process, the L4_Engine shall update RTPR whenever successfully en-queuing one packet into RPBR. The empty buffer ring condition is indicated by having RTPR = RHPR. RFP The number of Free Pages remains available in RPBR. Initial value = REPP - RSPP. During packet receive process, the L4_Engine will decrease this value by the page count of the packet currently being en-queued, while software will increase this value by the page count of the packet currently being de-queued. TSPP TX Start Page Pointer of TX Packet Buffer Ring (TPBR), indicating the beginning page of the TPBR in the xDATA memory. TEPP TX End Page Pointer of TPBR, indicating the ending page of TPBR in the xDATA memory. THPR TX Head Pointer of TPBR, pointing to the first page of first packet in TPBR. Initial value = TSPP. During packet transmit process, the L4_Engine shall de-queue the packet pointed by THPR in TPBR and then update THPR to point to next packet once done de-queuing one packet. TTPR TX Tail Pointer of TPBR, pointing to the next empty page in TPBR. Initial value = TSPP. During packet transmit process, software shall update TTPR after en-queuing one packet into TPBR. The empty buffer ring condition is indicated by having TTPR = THPR. TFP The number of Free Pages remains available in TPBR. Initial value = TEPP - TSPP. During packet transmit process, software will decrease this value by page count of the packet currently being en-queued while L4_Engine will increase this value by the page count of the packet currently being de-queued. Figure 103: The Content of Buffer Descriptor Page (BDP) 182 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Example Software Behavior Example L4_Engine Behavior Assume packet #1 with 6 pages long is en-queued by the L4_Engine, the L4_Engine puts packet #1's NPR = 0x0027 and RTPR = 0x0027. This packet is stored at page pointed by initial RTPR = 0x0021. Assume packet #2 with 3 pages long is en-queued by the L4_Engine, the L4_Engine puts packet #2's NPR = 0x002A, and RTPR = 0x002A. NPR [15:8] NPR [7:0] Initially, software sets RSPP = 0x0021, RHPR = 0x0021, and RTPR = 0x0021. Some Control Fields Packet Data NPR [15:8] NPR [7:0] Some Control Fields When RTPR is not equal to RHPR (meaning some packets are in the RPBR), software can start de-queuing the packet pointed by RHPR. Once done, software updates RHPR = NPR of packet #1. Packet Data After software de-queues packet #2, it updates RHPR = NPR of packet #2. Since RTPR now is equal to RHPR, this means that packet #2 is the last packet in the buffer ring, and the RPBR will become empty after de-queuing packet #2. After the L4_Engine en-queues 2 received packets into RPBR, we shall see RTPR = 0x002A. Initially, software set REPP = 0x002F The size of RX Packet Buffer Ring = REPP- RSPP = 15 pages or 15x256 = 3840 bytes. Figure 104: Example Ring Structure of Receive Packet Buffer Ring Example SW Behavior Initially, assume SW sets TSPP = 0x0030, THPR = 0x0030, and TTPR = 0x0030. Assume packet #1 with 6 pages long is en-queued by software, so software shall put packet #1's NPR = 0x0036, and TTPR = 0x0036. (This packet is stored at the page pointed by initial TTPR = 0x0030) Assuming packet #2 with 3 pages long is en-queued by software, so software shall put packet #2's NPR = 0x0039, and TTPR = 0x0039. NPR [15:8] NPR [7:0] Some Control Fields Example L4_Engine Behavior Packet Data NPR [15:8] NPR [7:0] Some Control Fields After software en-queues one packet, it can tell the L4_Engine to start de-queuing the packet pointed by THPR. After sending packet #1, the L4_Engine will update THPR = NPR of packet #1. Packet Data After software en-queues packet #2, it can tell the L4_Engine to start de-queuing the packet pointed by NPR of packet #1. After sending packet #2, the L4_Engine will update the THPR to point to the next packet. After software en-queues 2 transmitted packets into TPBR, we shall see TTPR = 0x0039. Software sets TEPP = 0x003F The size of TX Packet Buffer Ring = TEPP- TSPP = 16 pages or 16x256 = 4096 bytes. Figure 105: Example Ring Structure of Transmit Packet Buffer Ring 183 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 4.14.6 Packet Format in Packet Buffer Ring Receive Packet Buffer Ring In TOE RX direction, the L4_Engine is responsible for en-queuing the received packets into RPBR while software is responsible for de-queuing the received packets out of the RPBR. The packets in the ring are linked together via Next Pointer (NPR) field in each packet as shown below. The DMA transfer mechanism is used to move received packets from Ethernet MAC receive buffer through TOE to RPBR. Below Figure 106 to Figure 110 show the different packet format in RPBR. 1. ICMP Packet Format in RPBR L2_Engine in Non-Transparent Mode Offset 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A + n 0x1B + n 0x1C + n 0x1D + n 0x1E + n NPR [15:8] NPR [7:0] PCB, BPBB, Lgth [11:8] Length [7:0] Protocol = 01 Reserved Version, Header Length TOS Total Length [15:8] Total Length [7:0] Identification [15:8] Identification [7:0] Flag, Frag. Offset [12:8] Frag Offset [7:0] TTL Protocol Header Checksum [15:8] Header Checksum [7:0] Source IP [31:24] Source IP [23:16] Source IP [15:8] Source IP [7:0] Dest. IP [31:24] Dest. IP [23:16] Dest. IP [15:8] Dest. IP [7:0] IP Option (n bytes) Type [7:0] Code [7:0] ICMP Checksum [15:8] ICMP Checksum [7:0] Data Offset Bit 0x00 0x01 0x02 0x02 7:0 7:0 7 6:4 0x02 0x03 0x04 IP header ICMP header L2_Engine in Transparent Mode Offset 0x00 0x01 0x02 0x03 0x04 0x05 0x06~0B 0x0C~11 0x12~13 0x14~17 0x14~1B 0x14~1F 0x14~1B 0x14 / 18 / 1C / 20 0x15 / 19 / 1D / 21 0x16~17 / 1A~1B / 1E~1F / 22~23 0x18~19 / 1C~1D / 20~21 / 24~25 0x1A / 1E / 22 / 26 0x1B / 1F / 23 / 27 0x1C / 20 / 24 / 28 0x1D / 21 / 25 / 29 0x1E~1F / 22~23 / 26~27 / 2A~2B 0x20~23 / 24~27 / 28~2B / 2C~2F 0x24~27 / 28~2B / 2C~2F / 30~33 0x28+n / 2C+n / 30+n / 34+n 0x29+n / 2D+n / 31+n / 35+n 0x2A+n / 2E+n / 32+n / 36+n 0x2B+n / 2F+n / 33+n / 37+n 0x2C+n / 30+n / 34+n / 38+n NPR [15:8] NPR [7:0] PCB, BPBB, Lgth [11:8] Length [7:0] Protocol = 01 Reserved DA SA Length/Etype if VLAN (4 bytes) or if SNAP (8 bytes) or if SNAP+VLAN (12 bytes) or if PPPoE header (8 bytes) Version, Header Length TOS Total Length Identification Flag, Frag. Offset [12:8] Frag Offset [7:0] TTL Protocol Header Checksum Source IP Dest. IP IP Option (n bytes) Type [7:0] Code [7:0] ICMP Checksum [15:8] ICMP Checksum [7:0] Data ICMP payload Field Name Layer 2 header IP header ICMP header ICMP payload Description NPR [15:8] NPR [7:0] PCB BPBB The Next Pointers of RPBR: The NPR field indicates the first page of the next packet in the RPBR. When TL4CR[ERCB] = 1, the PCB flag indicates that this Packet Crosses the packet buffer ring Boundary. In that case, when PCB flag is "1", BPBB[2:0] field indicates the # of Buffer Pages being used for this packet Before REPP Boundary. When PCB flag is "0", BPBB field is undefined. When TL4CR[ERCB] = 0, PCB and BPBB are undefined. 3:0 Length [11:8] The Length field indicates the total length in bytes from (Version, Header Length) field 7:0 Length [7:0] to Data field in Non-Transparent mode, or from DA field to Data field in Transparent mode. 7:0 Protocol The Protocol = 0x01 indicating that the packet is an ICMP packet Figure 106: ICMP Packet Format in RPBR 184 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 2. IGMP Packet Format in RPBR L2_Engine in Non-Transparent Mode Offset 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A + n 0x1B + n 0x1C + n 0x1D + n 0x1E + n NPR [15:8] NPR [7:0] PCB, BPBB, Lgth [11:8] Length [7:0] Protocol = 02 Reserved Version, Header Length TOS Total Length [15:8] Total Length [7:0] Identification [15:8] Identification [7:0] Flag, Frag. Offset [12:8] Frag Offset [7:0] TTL Protocol Header Checksum [15:8] Header Checksum [7:0] Source IP [31:24] Source IP [23:16] Source IP [15:8] Source IP [7:0] Dest. IP [31:24] Dest. IP [23:16] Dest. IP [15:8] Dest. IP [7:0] IP Option (n bytes) Version [3:0], Type [3:0] Unused [7:0] IGMP Checksum [15:8] IGMP Checksum [7:0] Data Offset Bit Field Name 0x00 0x01 0x02 0x02 0x02 0x03 0x04 7:0 7:0 7 6:4 3:0 7:0 7:0 NPR [15:8] NPR [7:0] PCB BPBB Length [11:8] Length [7:0] Protocol IP header IGMP header L2_Engine in Transparent Mode Offset 0x00 0x01 0x02 0x03 0x04 0x05 0x06~0B 0x0C~11 0x12~13 0x14~17 0x14~1B 0x14~1F 0x14~1B 0x14 / 18 / 1C / 20 0x15 / 19 / 1D / 21 0x16~17 / 1A~1B / 1E~1F / 22~23 0x18~19 / 1C~1D / 20~21 / 24~25 0x1A / 1E / 22 / 26 0x1B / 1F / 23 / 27 0x1C / 20 / 24 / 28 0x1D / 21 / 25 / 29 0x1E~1F / 22~23 / 26~27 / 2A~2B 0x20~23 / 24~27 / 28~2B / 2C~2F 0x24~27 / 28~2B / 2C~2F / 30~33 0x28+n / 2C+n / 30+n / 34+n 0x29+n / 2D+n / 31+n / 35+n 0x2A+n / 2E+n / 32+n / 36+n 0x2B+n / 2F+n / 33+n / 37+n 0x2C+n / 30+n / 34+n / 38+n NPR [15:8] NPR [7:0] PCB, BPBB, Lgth [11:8] Length [7:0] Protocol = 02 Reserved DA SA Length/Etype if VLAN (4 bytes) or if SNAP (8 bytes) or if SNAP+VLAN (12 bytes) or if PPPoE header (8 bytes) Version, Header Length TOS Total Length Identification Flag, Frag. Offset [12:8] Frag Offset [7:0] TTL Protocol Header Checksum Source IP Dest. IP IP Option (n bytes) Version [3:0], Type [3:0] Unused [7:0] IGMP Checksum [15:8] IGMP Checksum [7:0] Data IGMP payload Description Same as description for ICMP packet. Same as description for ICMP packet. Same as description for ICMP packet. The Protocol = 0x02 indicating that the packet is an IGMP packet Figure 107: IGMP Packet Format in RPBR 185 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights Layer 2 header IP header IGMP header IGMP payload AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 3. UDP Packet Format in RPBR L2-Engine in Non-Transparent Mode Offset 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A + n 0x1B + n 0x1C + n 0x1D + n 0x1E + n 0x1F + n 0x20 + n 0x21 + n 0x22 + n NPR [15:8] NPR [7:0] PCB, BPBB, Lgth [11:8] Length [7:0] Protocol = 11 Data Offset [7:0] Version, Header Length TOS Total Length [15:8] Total Length [7:0] Identification [15:8] Identification [7:0] Flag, Frag. Offset [12:8] Frag Offset [7:0] TTL Protocol Header Checksum [15:8] Header Checksum [7:0] Source IP [31:24] Source IP [23:16] Source IP [15:8] Source IP [7:0] Dest. IP [31:24] Dest. IP [23:16] Dest. IP [15:8] Dest. IP [7:0] IP Option (n bytes) Source Port [15:8] Source Port [7:0] Dest. Port [15:8] Dest. Port [7:0] UDP Length [15:8] UDP Length [7:0] UDP Checksum [15:8] UDP Checksum [7:0] IP header L2-Engine in Transparent Mode Offset 0x00 0x01 0x02 0x03 0x04 0x05 0x06~0B 0x0C~11 0x12~13 0x14~17 0x14~1B 0x14~1F 0x14~1B 0x14 / 18 / 1C / 20 0x15 / 19 / 1D / 21 0x16~17 / 1A~1B / 1E~1F / 22~23 0x18~19 / 1C~1D / 20~21 / 24~25 0x1A / 1E / 22 / 26 0x1B / 1F / 23 / 27 0x1C / 20 / 24 / 28 0x1D / 21 / 25 / 29 0x1E~1F / 22~23 / 26~27 / 2A~2B 0x20~23 / 24~27 / 28~2B / 2C~2F 0x24~27 / 28~2B / 2C~2F / 30~33 0x28+n / 2C+n / 30+n / 34+n UDP header 0x2E+n / 32+n / 36+n / 3A+n 0x2F+n / 33+n / 37+n / 3B+n 0x30+n / 34+n / 38+n / 3C+n UDP payload Data Offset Bit Field Name 0x00 0x01 0x02 0x02 0x02 0x03 0x04 0x05 7:0 7:0 7 6:4 3:0 7:0 7:0 7:0 NPR [15:8] NPR [7:0] PCB BPBB Length [11:8] Length [7:0] Protocol Data Offset NPR [15:8] NPR [7:0] PCB, BPBB, Lgth [11:8] Length [7:0] Protocol = 11 Data Offset [7:0] DA SA Length/Etype if VLAN (4 bytes) or if SNAP (8 bytes) or if SNAP+VLAN (12 bytes) or if PPPoE header (8 bytes) Version, Header Length TOS Total Length Identification Flag, Frag. Offset [12:8] Frag Offset [7:0] TTL Protocol Header Checksum Source IP Dest. IP IP Option (n bytes) Source Port [15:8] Source Port [7:0] Dest. Port [15:8] Dest. Port [7:0] UDP Length [15:8] UDP Length [7:0] UDP Checksum [15:8] UDP Checksum [7:0] Data Layer 2 header IP header UDP header UDP payload Description Same as description for ICMP packet. Same as description for ICMP packet. Same as description for ICMP packet. The Protocol = 0x11 indicating that the packet is an UDP packet The Data Offset field indicates the address offset of where the first UDP payload byte is located. For example, if without IP Option field, this field normally is 28 (dec) for Non-Transparent or 42 (dec) for Transparent without VLAN/SNAP/PPPoE. Therefore, the real memory address of first UDP payload byte = the real memory address of Data Offset field + the value of Data Offset + 1. Figure 108: UDP Packet Format in RPBR 186 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 4. TCP Packet Format in RPBR L2-Engine in Non-Transparent Mode Offset 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A + n 0x1B + n 0x1C + n 0x1D + n 0x1E + n 0x1F + n 0x20 + n 0x21 + n 0x22 + n 0x23 + n 0x24 + n 0x25 + n 0x26 + n 0x27 + n 0x28 + n 0x29 + n 0x2A + n 0x2B + n 0x2C + n 0x2D + n NPR [15:8] NPR [7:0] PCB, BPBB, Lgth [11:8] Length [7:0] Protocol = 06 Data Offset [7:0] Version, Header Length TOS Total Length [15:8] Total Length [7:0] Identification [15:8] Identification [7:0] Flag, Frag. Offset [12:8] Frag Offset [7:0] TTL Protocol Header Checksum [15:8] Header Checksum [7:0] Source IP [31:24] Source IP [23:16] Source IP [15:8] Source IP [7:0] Dest. IP [31:24] Dest. IP [23:16] Dest. IP [15:8] Dest. IP [7:0] IP Option (n bytes) Source Port [15:8] Source Port [7:0] Dest. Port [15:8] Dest. Port [7:0] Sequence # [31:24] Sequence # [23:16] Sequence # [15:8] Sequence # [7:0] Acknowledge # [31:24] Acknowledge # [23:16] Acknowledge # [15:8] Acknowledge # [7:0] Header Length, Rsved Rsved, U,A,P,R,S,F Window Size [15:8] Window Size [7:0] TCP Checksum [15:8] TCP Checksum [7:0] Urgent Pointer [15:8] Urgent Pointer [7:0] TCP Option (m bytes) 0x2E+n+m Data Offset Bit 0x00 0x01 0x02 0x02 0x02 0x03 7:0 7:0 7 6:4 3:0 7:0 IP header L2-Engine in Transparent Mode Offset 0x00 0x01 0x02 0x03 0x04 0x05 0x06~0B 0x0C~11 0x12~13 0x14~17 0x14~1B 0x14~1F 0x14~1B 0x14 / 18 / 1C / 20 0x15 / 19 / 1D / 21 0x16~17 / 1A~1B / 1E~1F / 22~23 0x18~19 / 1C~1D / 20~21 / 24~25 0x1A / 1E / 22 / 26 0x1B / 1F / 23 / 27 0x1C / 20 / 24 / 28 0x1D / 21 / 25 / 29 0x1E~1F / 22~23 / 26~27 / 2A~2B 0x20~23 / 24~27 / 28~2B / 2C~2F 0x24~27 / 28~2B / 2C~2F / 30~33 0x28+n / 2C+n / 30+n / 34+n TCP header 0x38+n / 3C+n / 40+n / 44+n 0x39+n / 3D+n / 41+n / 45+n 0x3C+n+m / 40+n+m / 44+n+m / 48+n+m NPR [15:8] NPR [7:0] PCB, BPBB, Lgth [11:8] Length [7:0] Protocol = 06 Data Offset [7:0] DA SA Length/Etype if VLAN (4 bytes) or if SNAP (8 bytes) or if SNAP+VLAN (12 bytes) or if PPPoE header (8 bytes) Version, Header Length TOS Total Length Identification Flag, Frag. Offset [12:8] Frag Offset [7:0] TTL Protocol Header Checksum Source IP Dest. IP IP Option (n bytes) Source Port [15:8] Source Port [7:0] Dest. Port [15:8] Dest. Port [7:0] Sequence # [31:24] Sequence # [23:16] Sequence # [15:8] Sequence # [7:0] Acknowledge # [31:24] Acknowledge # [23:16] Acknowledge # [15:8] Acknowledge # [7:0] Header Length, Rsved Rsved, U,A,P,R,S,F Window Size [15:8] Window Size [7:0] TCP Checksum [15:8] TCP Checksum [7:0] Urgent Pointer [15:8] Urgent Pointer [7:0] TCP Option (m bytes) Data TCP payload Field Name Description NPR [15:8] Same as description for ICMP packet. NPR [7:0] Same as description for ICMP packet. PCB BPBB Length [11:8] Same as description for ICMP packet. Length [7:0] 187 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights Layer 2 header IP header TCP header TCP payload AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 0x04 0x05 7:0 Protocol 7:0 Data Offset The Protocol = 0x06 indicating that the packet is an TCP packet The Data Offset field indicates the address offset of where the first TCP payload byte is located. For example, if without IP Option field and TCP Option field, this field normally is 40 (dec) for Non-transparent or 54 (dec) for Transparent without VLAN/SNAP/PPPoE. Therefore, the real memory address of first TCP payload byte = the real memory address of Data Offset field + the value of Data Offset + 1. Figure 109: TCP Packet Format in RPBR 5. Non-IP-type Packet Format in RPBR NPR [15:8] NPR [7:0] PCB, BPBB, Lgth [11:8] Length [7:0] Protocol = FF Reserved DA [47:40] ... DA [7:0] SA [47:40] ... SA [7:0] .... Data Offset Bit 0x00 0x01 0x02 0x02 0x02 0x03 0x04 7:0 7:0 7 6:4 3:0 7:0 7:0 Protocol = FF indicates this as a "Non-IP-type" packet Full MAC frame without CRC bytes Field Name NPR [15:8] NPR [7:0] PCB BPBB Length [11:8] Length [7:0] Protocol Description Same as description for ICMP packet. Same as description for ICMP packet. The Length field indicates the total length in bytes from DA field to Data field regardless it's either in Non-transparent or Transparent mode. When in L2 Engine Non-Transparent mode, the following packet encapsulation will be treated as "Non-IP-type" packet by TOE RX (i.e., the Protocol field will be put with 0xFF), z z z z IEEE 802.2/802.3 Encapsulation (BPDU/GMRP/GVRP, NETBIOS, IPX) NetWare 802.3 RAW Encapsulation (IPX) IPv6 Packet (Etype = 0x86DD) PPPoE frame (if Etype = 0x8863 or if Etype = 0x8864) When in L2 Engine Transparent mode, the following packet encapsulation will be treated as "Non-IP-type" packet by TOE RX (i.e., the Protocol field will be put with 0xFF), z z z z IEEE 802.2/802.3 Encapsulation (BPDU/GMRP/GVRP, NETBIOS, IPX) NetWare 802.3 RAW Encapsulation (IPX) IPv6 Packet (Etype = 0x86DD) PPPoE frame (if Etype = 0x8863) or (if Etype = 0x8864 and Protocol !== 0021) Figure 110: Non-IP-type Packet Format in RPBR 188 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Transmit Packet Buffer Ring In TOE TX direction, software is responsible for en-queuing the transmitted packets into TPBR while the L4_Engine is responsible for de-queuing the transmitted packets out of the TPBR. The packets in the ring are linked together via Next Pointer (NPR) field in each packet as shown below. The DMA transfer mechanism is used to move transmitted packets from TPBR through TOE to Ethernet MAC transmit buffer. Below Figure 111 to Figure 115 shows the packet format in TPBR. 1. ICMP Packet Format in TPBR L2-Engine in Non-Transparent Mode Offset 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A + n 0x1B + n 0x1C + n 0x1D + n 0x1E + n NPR [15:8] NPR [7:0] Length [15:8] Length [7:0] Protocol = 01 Reserved = 00 Version, Header Length TOS Total Length [15:8] Total Length [7:0] Identification [15:8] Identification [7:0] Flag, Frag. Offset [12:8] Frag Offset [7:0] TTL Protocol Header Checksum = 00 Header Checksum = 00 Source IP [31:24] Source IP [23:16] Source IP [15:8] Source IP [7:0] Dest. IP [31:24] Dest. IP [23:16] Dest. IP [15:8] Dest. IP [7:0] IP Option (n bytes) Type [7:0] Code [7:0] ICMP Checksum = 00 ICMP Checksum = 00 Data Offset Bit 0x00 0x01 0x02 0x03 7:0 7:0 7:0 7:0 IP header ICMP header L2-Engine in Transparent Mode Offset 0x00 0x01 0x02 0x03 0x04 0x05 0x06~0B 0x0C~11 0x12~13 0x14~17 0x14~1B 0x14~1F 0x14~1B 0x14 / 18 / 1C / 20 0x15 / 19 / 1D / 21 0x16~17 / 1A~1B / 1E~1F / 22~23 0x18~19 / 1C~1D / 20~21 / 24~25 0x1A / 1E / 22 / 26 0x1B / 1F / 23 / 27 0x1C / 20 / 24 / 28 0x1D / 21 / 25 / 29 0x1E~1F / 22~23 / 26~27 / 2A~2B 0x20~23 / 24~27 / 28~2B / 2C~2F 0x24~27 / 28~2B / 2C~2F / 30~33 0x28+n / 2C+n / 30+n / 34+n 0x29+n / 2D+n / 31+n / 35+n 0x2A+n / 2E+n / 32+n / 36+n 0x2B+n / 2F+n / 33+n / 37+n 0x2C+n / 30+n / 34+n / 38+n NPR [15:8] NPR [7:0] Length [15:8] Length [7:0] Protocol = 01 PPPoE, Reserved[6:0] DA SA Length/Etype if VLAN (4 bytes) or if SNAP (8 bytes) or if SNAP+VLAN (12 bytes) or if PPPoE header (8 bytes) Version, Header Length TOS Total Length Identification Flag, Frag. Offset [12:8] Frag Offset [7:0] TTL Protocol Header Chksum = 0000 Source IP Dest. IP IP Option (n bytes) Type [7:0] Code [7:0] ICMP Checksum = 00 ICMP Checksum = 00 Data ICMP payload Field Name Description NPR [15:8] NPR [7:0] Length [11:8] Length [7:0] The Next Pointers of TPBR: The NPR field indicates the first page of the next packet in the TPBR. The Length field indicates the total length in bytes from (Version, Header Length) field to Data field in Non-Transparent mode, or from DA field to Data field in Transparent mode. 0x04 7:0 Protocol The Protocol = 0x01 indicating that the packet is an ICMP packet. 0x05 7 PPPoE Set PPPoE flag to 1 when PPPoE header (8 bytes) is present in the packet format. 0x14~ 7:0 VLAN or If VLAN Tag (4 bytes) is present, the TL2CR[TX_VLAN_EN] should also be set to 1 to SNAP or allow TOE to operate properly. VLAN+SNAP If SNAP header (8 bytes) is present, the TL2CR[TX_SNAP_EN] should also be set to 1 or to allow TOE to operate properly. PPPoE Header If both VLAN Tag (4 bytes) and SNAP header (8 bytes) are present, the TL2CR[TX_VLAN_EN and TX_SNAP_EN] should also be set to 1 to allow TOE to 189 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights Layer 2 header IP header ICMP header ICMP payload AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY operate properly. If PPPoE header (8 bytes) is present, the above PPPoE flag should also be set to 1 and TL2CR[TX_SNAP_EN] should be cleared to 0 to allow TOE to operate properly. Figure 111: ICMP Packet Format in TPBR 2. IGMP Packet Format in TPBR L2-Engine in Non-Transparent Mode Offset 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A + n 0x1B + n 0x1C + n 0x1D + n 0x1E + n NPR [15:8] NPR [7:0] Length [15:8] Length [7:0] Protocol = 02 Reserved = 00 Version, Header Length TOS Total Length [15:8] Total Length [7:0] Identification [15:8] Identification [7:0] Flag, Frag. Offset [12:8] Frag Offset [7:0] TTL Protocol Header Checksum = 00 Header Checksum = 00 Source IP [31:24] Source IP [23:16] Source IP [15:8] Source IP [7:0] Dest. IP [31:24] Dest. IP [23:16] Dest. IP [15:8] Dest. IP [7:0] IP Option (n bytes) Version [3:0], Type [3:0] Unused [7:0] IGMP Checksum = 00 IGMP Checksum = 00 Data Offset Bit Field Name 0x00 0x01 0x02 0x03 0x04 0x05 0x14~ 7:0 7:0 7:0 7:0 7:0 7 7:0 NPR [15:8] NPR [7:0] Length [11:8] Length [7:0] Protocol PPPoE VLAN or SNAP or VLAN+SNAP or PPPoE Header IP header IGMP header L2-Engine in Transparent Mode Offset 0x00 0x01 0x02 0x03 0x04 0x05 0x06~0B 0x0C~11 0x12~13 0x14~17 0x14~1B 0x14~1F 0x14~1B 0x14 / 18 / 1C / 20 0x15 / 19 / 1D / 21 0x16~17 / 1A~1B / 1E~1F / 22~23 0x18~19 / 1C~1D / 20~21 / 24~25 0x1A / 1E / 22 / 26 0x1B / 1F / 23 / 27 0x1C / 20 / 24 / 28 0x1D / 21 / 25 / 29 0x1E~1F / 22~23 / 26~27 / 2A~2B 0x20~23 / 24~27 / 28~2B / 2C~2F 0x24~27 / 28~2B / 2C~2F / 30~33 0x28+n / 2C+n / 30+n / 34+n 0x29+n / 2D+n / 31+n / 35+n 0x2A+n / 2E+n / 32+n / 36+n 0x2B+n / 2F+n / 33+n / 37+n 0x2C+n / 30+n / 34+n / 38+n NPR [15:8] NPR [7:0] Length [15:8] Length [7:0] Protocol = 02 PPPoE, Reserved[6:0] DA SA Length/Etype if VLAN (4 bytes) or if SNAP (8 bytes) or if SNAP+VLAN (12 bytes) or if PPPoE header (8 bytes) Version, Header Length TOS Total Length Identification Flag, Frag. Offset [12:8] Frag Offset [7:0] TTL Protocol Header Chksum = 0000 Source IP Dest. IP IP Option (n bytes) Version [3:0], Type [3:0] Unused [7:0] IGMP Checksum = 00 IGMP Checksum = 00 Data IGMP payload Description Same as description for ICMP packet. Same as description for ICMP packet. The Protocol = 0x02 indicating that the packet is an IGMP packet. Same as description for ICMP packet. Same as description for ICMP packet. Figure 112: IGMP Packet Format in TPBR 190 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights Layer 2 header IP header IGMP header IGMP payload AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 3. UDP Packet Format in TPBR L2-Engine in Non-Transparent Mode Offset 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A + n 0x1B + n 0x1C + n 0x1D + n 0x1E + n 0x1F + n 0x20 + n 0x21 + n 0x22 + n NPR [15:8] NPR [7:0] Length [15:8] Length [7:0] Protocol = 11 Reserved = 00 Version, Header Length TOS Total Length [15:8] Total Length [7:0] Identification [15:8] Identification [7:0] Flag, Frag. Offset [12:8] Frag Offset [7:0] TTL Protocol Header Checksum = 00 Header Checksum = 00 Source IP [31:24] Source IP [23:16] Source IP [15:8] Source IP [7:0] Dest. IP [31:24] Dest. IP [23:16] Dest. IP [15:8] Dest. IP [7:0] IP Option (n bytes) Source Port [15:8] Source Port [7:0] Dest. Port [15:8] Dest. Port [7:0] UDP Length [15:8] UDP Length [7:0] UDP Checksum = 00 UDP Checksum = 00 Data Offset Bit Field Name 0x00 0x01 0x02 0x03 0x04 0x05 0x14~ 7:0 7:0 7:0 7:0 7:0 7 7:0 NPR [15:8] NPR [7:0] Length [11:8] Length [7:0] Protocol PPPoE VLAN or SNAP or VLAN+SNAP or PPPoE Header IP header L2-Engine in Transparent Mode Offset 0x00 0x01 0x02 0x03 0x04 0x05 0x06~0B 0x0C~11 0x12~13 0x14~17 0x14~1B 0x14~1F 0x14~1B 0x14 / 18 / 1C / 20 0x15 / 19 / 1D / 21 0x16~17 / 1A~1B / 1E~1F / 22~23 0x18~19 / 1C~1D / 20~21 / 24~25 0x1A / 1E / 22 / 26 0x1B / 1F / 23 / 27 0x1C / 20 / 24 / 28 0x1D / 21 / 25 / 29 0x1E~1F / 22~23 / 26~27 / 2A~2B 0x20~23 / 24~27 / 28~2B / 2C~2F 0x24~27 / 28~2B / 2C~2F / 30~33 0x28+n / 2C+n / 30+n / 34+n UDP header 0x2E+n / 32+n / 36+n / 3A+n 0x2F+n / 33+n / 37+n / 3B+n 0x30+n / 34+n / 38+n / 3C+n UDP payload NPR [15:8] NPR [7:0] Length [15:8] Length [7:0] Protocol = 11 PPPoE, Reserved[6:0] DA SA Length/Etype if VLAN (4 bytes) or if SNAP (8 bytes) or if SNAP+VLAN (12 bytes) or if PPPoE header (8 bytes) Version, Header Length TOS Total Length Identification Flag, Frag. Offset [12:8] Frag Offset [7:0] TTL Protocol Header Chksum = 0000 Source IP Dest. IP IP Option (n bytes) Source Port [15:8] Source Port [7:0] Dest. Port [15:8] Dest. Port [7:0] UDP Length [15:8] UDP Length [7:0] UDP Checksum = 00 UDP Checksum = 00 Data Description Same as description for ICMP packet. Same as description for ICMP packet. The Protocol = 0x11 indicating that the packet is an UDP packet. Same as description for ICMP packet. Same as description for ICMP packet. Figure 113: UDP Packet Format in TPBR 191 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights Layer 2 header IP header UDP header UDP payload AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 4. TCP Packet Format in TPBR L2-Engine in Non-Transparent Mode Offset 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A + n 0x1B + n 0x1C + n 0x1D + n 0x1E + n 0x1F + n 0x20 + n 0x21 + n 0x22 + n 0x23 + n 0x24 + n 0x25 + n 0x26 + n 0x27 + n 0x28 + n 0x29 + n 0x2A + n 0x2B + n 0x2C + n 0x2D + n NPR [15:8] NPR [7:0] Length [15:8] Length [7:0] Protocol = 06 Reserved = 00 Version, Header Length TOS Total Length [15:8] Total Length [7:0] Identification [15:8] Identification [7:0] Flag, Frag. Offset [12:8] Frag Offset [7:0] TTL Protocol Header Checksum = 00 Header Checksum = 00 Source IP [31:24] Source IP [23:16] Source IP [15:8] Source IP [7:0] Dest. IP [31:24] Dest. IP [23:16] Dest. IP [15:8] Dest. IP [7:0] IP Option (n bytes) Source Port [15:8] Source Port [7:0] Dest. Port [15:8] Dest. Port [7:0] Sequence # [31:24] Sequence # [23:16] Sequence # [15:8] Sequence # [7:0] Acknowledge # [31:24] Acknowledge # [23:16] Acknowledge # [15:8] Acknowledge # [7:0] Header Length, Rsved Rsved, U,A,P,R,S,F Window Size [15:8] Window Size [7:0] TCP Checksum = 00 TCP Checksum = 00 Urgent Pointer [15:8] Urgent Pointer [7:0] TCP Option (m bytes) 0x2E+n+m Data Offset Bit 0x00 0x01 0x02 0x03 0x04 0x05 7:0 7:0 7:0 7:0 7:0 7 IP header L2-Engine in Transparent Mode Offset 0x00 0x01 0x02 0x03 0x04 0x05 0x06~0B 0x0C~11 0x12~13 0x14~17 0x14~1B 0x14~1F 0x14~1B 0x14 / 18 / 1C / 20 0x15 / 19 / 1D / 21 0x16~17 / 1A~1B / 1E~1F / 22~23 0x18~19 / 1C~1D / 20~21 / 24~25 0x1A / 1E / 22 / 26 0x1B / 1F / 23 / 27 0x1C / 20 / 24 / 28 0x1D / 21 / 25 / 29 0x1E~1F / 22~23 / 26~27 / 2A~2B 0x20~23 / 24~27 / 28~2B / 2C~2F 0x24~27 / 28~2B / 2C~2F / 30~33 0x28+n / 2C+n / 30+n / 34+n TCP header 0x38+n / 3C+n / 40+n / 44+n 0x39+n / 3D+n / 41+n / 45+n 0x3C+n+m / 40+n+m / 44+n+m / 48+n+m Data TCP payload Field Name NPR [15:8] NPR [7:0] Length [11:8] Length [7:0] Protocol PPPoE NPR [15:8] NPR [7:0] Length [15:8] Length [7:0] Protocol = 06 PPPoE, Reserved[6:0] DA SA Length/Etype if VLAN (4 bytes) or if SNAP (8 bytes) or if SNAP+VLAN (12 bytes) or if PPPoE header (8 bytes) Version, Header Length TOS Total Length Identification Flag, Frag. Offset [12:8] Frag Offset [7:0] TTL Protocol Header Chksum = 0000 Source IP Dest. IP IP Option (n bytes) Source Port [15:8] Source Port [7:0] Dest. Port [15:8] Dest. Port [7:0] Sequence # [31:24] Sequence # [23:16] Sequence # [15:8] Sequence # [7:0] Acknowledge # [31:24] Acknowledge # [23:16] Acknowledge # [15:8] Acknowledge # [7:0] Header Length, Rsved Rsved, U,A,P,R,S,F Window Size [15:8] Window Size [7:0] TCP Checksum = 00 TCP Checksum = 00 Urgent Pointer [15:8] Urgent Pointer [7:0] TCP Option (m bytes) Description Same as description for ICMP packet. Same as description for ICMP packet. The Protocol = 0x06 indicating that the packet is a TCP packet. Same as description for ICMP packet. 192 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights Layer 2 header IP header TCP header TCP payload AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 0x14~ 7:0 VLAN or Same as description for ICMP packet. SNAP or VLAN+SNAP or PPPoE Header Figure 114: TCP Packet Format in TPBR 5. Non-IP-type Packet Format in TPBR NPR [15:8] NPR [7:0] Length [15:8] Length [7:0] Protocol = FF Reserved = 00 DA [47:40] ... DA [7:0] SA [47:40] ... SA [7:0] .... Data Offset Bit 0x00 0x01 0x02 0x02 0x02 0x03 0x04 7:0 7:0 7 6:4 3:0 7:0 7:0 Protocol = FF indicates this as a Non-IP-type packet Full MAC frame without CRC bytes Field Name NPR [15:8] NPR [7:0] PCB BPBB Length [11:8] Length [7:0] Protocol Description Same as description for ICMP packet. Same as description for ICMP packet. The Length field indicates the total length in bytes from DA field to Data field regardless it's either in non-transparent or transparent mode. When in L2 Engine Non-Transparent mode, the following packet encapsulation should be treated as Non-IP-type packet by software, i.e., software should put the Protocol field = 0xFF, z z z z IEEE 802.2/802.3 Encapsulation (BPDU/GMRP/GVRP, NETBIOS, IPX) NetWare 802.3 RAW Encapsulation (IPX) IPv6 Packet (Etype = 0x86DD) PPPoE frame (if Etype = 0x8863 or if Etype = 0x8864) When in L2 Engine Transparent mode, the following packet encapsulation should be treated as Non-IP-type packet by software, i.e., software should put the Protocol field = 0xFF, z z z z IEEE 802.2/802.3 Encapsulation (BPDU/GMRP/GVRP, NETBIOS, IPX) NetWare 802.3 RAW Encapsulation (IPX) IPv6 Packet (Etype = 0x86DD) PPPoE frame (if Etype = 0x8863) or (if Etype = 0x8864 and Protocol !== 0021) Figure 115: Non-IP-type Packet Format in TPBR 193 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 4.15 10/100M Ethernet MAC The 10/100 Ethernet MAC core block diagram is shown in Figure 116 below. It supports 802.3 and 802.3u MAC sub-layer functions as listed below, z Ethernet MAC frame receive and transmit through MII interface z With dedicated receive buffer of 8K bytes SRAM and transmit buffer of 4K bytes SRAM z Flow-control support in full-duplex mode by monitoring receive buffer usage to compare with high water mark and low water mark for triggering flow control z Received MAC frame CRC check and transmit MAC frame CRC generation z Received packet filtering for broadcast, multicast, unicast, or CRC error MAC frames, etc. if enabled z Support collision-detection, exponential backoff, packet retransmission, and backpressure in half-duplex mode z Support Magic packet, predefined Wakeup frame, and Ethernet PHY linkup remote-wakeup mode. Upon detecting wakeup event, it can awake the AX11015 up from PMM or STOP mode z Provides additional media-independent interface (MII) interface for interfacing external HomePlug PHY or HomePNA PHY functions The 10/100M Ethernet MAC interfaces to both MII interface of the embedded 10/100M Ethernet PHY and the external MII interface I/O pins. The selection between the two MII interfaces is controlled by software via PCR (0x22) register. Receiver Buffer Memory 8K bytes TOE RX SFR Bus Wakeup Function MAC Registers I2C EEPROM settings TOE TX MII RX Interface MAC Receive Logic STA MAC Transmit Logic Transmit Buffer Memory 4K bytes Figure 116 10/100M Ethernet MAC Block Diagram 194 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights Interrupt MDC, MDIO MII TX Interface AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 4.15.1 10/100M Ethernet MAC SFR Register Map Address Name Description 0xB6 MCIR MAC Command Index Register is used to indicate the address of Ethernet MAC registers. 0xB7 MDR MAC Data Register is used to read data from or write data to the specified Ethernet MAC register. Table 40: 10/100M Ethernet MAC SFR Register Map MAC Command Index Register (MCIR, 0xB6) Bit Name Reset Value 7 6 5 4 3 2 1 0 MCIR 0x00 Bit Name Access Description 7:0 MCIR WO Indicate which of the Ethernet MAC register as listed in Table 41 is to be accessed. MAC Data Register (MDR, 0xB7) Bit Name Reset Value 7 6 5 4 3 2 1 0 MDR 0x00 Bit Name Access Description 7:0 MDR R/W Data Register is used to write data to or read data from the Ethernet MAC registers. 10/100M Ethernet MAC Register Indirect Access Method Software shall use indirect access method through MCIR and MDR registers to do read and write access to the 10/100M Ethernet MAC registers as listed in Table 41 below. Read a register from 10/100M Ethernet MAC: Step 1. Write MCIR: Software indicates the MAC register address to be accessed as the data and write it to the SFR register MCIR. Step 2. Read MDR: Software then read SFR register MDR. The data read from MDR is the MAC register data indicated in step 1. Keep reading from MDR if the MAC registers have more than one byte, in that case, the first byte being read back is LSB byte. Write a register to 10/100M Ethernet MAC: Step 1. Write MDR: Software writes the data you want to write into MAC registers to the SFR register MDR. Keep writing to MDR if the MAC registers have more than one byte, in that case, the first byte being written should be LSB byte. Step 2. Write MCIR: After writing MAC register data to MDR, software then indicates the target MAC register address as data and write it to MCIR. Note: While software is reading or writing Ethernet MAC Registers during a sequence of SFR accesses, software can abort that process by writing MCIR with 0xFF. 195 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 10/100 Ethernet MAC Core Register Map Address 0x00 0x02 0x0A 0x0C 0x10 0x16 0x1E 0x20 0x22 0x24 0x26 0x28 0x30 0x32 0x36 0x38 0x3A 0x40 0x44 0x46 0x48 0xFF Register Name RTSCR RTSDR RCR IPGCR MACAR MFA TR MSMR PCR SPWIE PLCIE WPLS WFCR WFBM0 WFCRC0 WFOS0 WFLB0 WFBM1 WFCRC1 WFOS1 WFLB1 Description RX/TX SRAM Command Register RX/TX SRAM Data Register RX Control Register IPG Control Register MAC Address Register Multicast Filter Array Test Register Medium Status and Mode Register PHY Control Register STOP and PMM Wakeup Interrupt Enable Register PHY Link Change Interrupt Enable Register Wakeup and PHY Link Status Register Wakeup Frame Command Register Wakeup Frame Byte Mask 0 Register Wakeup Frame CRC 0 Register Wakeup Frame Offset 0 Register Wakeup Frame Last Byte 0 Register Wakeup Frame Byte Mask 1 Register Wakeup Frame CRC 1 Register Wakeup Frame Offset 1 Register Wakeup Frame Last Byte 1 Register Command Abort Table 41: 10/100M Ethernet MAC Register Map 4.15.2 Ethernet MAC Receive Filtering The address filtering logic compares the Destination Address field (first 6 bytes of the received packet) to the Ethernet MAC address registers (MACAR) of AX11015. If any one of the six bytes does not match the pre-programmed MACAR registers, the Ethernet MAC Receive Logic rejects the packet. This is for unicast address filtering. All multicast destination addresses are filtered using a hashing algorithm. See following description. If the multicast address indexes a bit that has been set in the filter bit array of the "Multicast Filter Array", the packet is accepted. Otherwise the Ethernet MAC rejects it. Each destination address is also checked for all 1's, which is the reserved broadcast address. Unicast Packet Filtering The MAC address registers (MACAR) are used to compare the destination address (DA[47:0]) of incoming packets for rejecting or accepting packets. Comparisons are performed on a byte wide basis. The bit assignment shown below relates the sequence in NODE_ADDR_0 - NODE_ADDR_5 registers to the bit sequence of the received packet. NODE_ADDR_0 NODE_ADDR_1 NODE_ADDR_2 NODE_ADDR_3 NODE_ADDR_4 NODE_ADDR_5 D7 D6 D5 D4 D3 D2 D1 D0 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 DA15 DA14 DA13 DA12 DA11 DA10 DA9 DA8 DA23 DA22 DA21 DA20 DA19 DA18 DA17 DA16 DA31 DA30 DA29 DA28 DA27 DA26 DA25 DA24 DA39 DA38 DA37 DA36 DA35 DA34 DA33 DA32 DA47 DA46 DA45 DA44 DA43 DA42 DA41 DA40 Note: The bit sequence of the received packet is DA0, DA1, ..., DA7, DA8, ...., DA47. 196 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY MAC Address Register (MACAR, 0x10) 7 Bit 6 NAME Reset Value Bit 7:0 ... 47:40 Name NODE_ADDR 0 ... NODE_ADDR 5 Access R/W 5 4 3 2 NODE_ADDR 0 NODE_ADDR 1 NODE_ADDR 2 NODE_ADDR 3 NODE_ADDR 4 NODE_ADDR 5 Reset value is determined by the I2C EEPROM 1 0 Description The NODE_ADDR 5~0 is the MAC address of this device where NODE_ADDR 0 represents bit 7~0 of MAC address while NODE_ADDR 5 represents bit 47~40. RX Control Register (RCR, 0x0A) 7 SO 0 Bit Name Reset Value Bit Name Access 0 PRO R/W 1 AMALL R/W 2 SEP R/W 3 AB R/W 4 AM R/W 5 AP R/W 6 AC R/W 7 SO R/W 6 AC 1 5 AP 0 4 AM 1 3 AB 1 2 SEP 0 1 AMALL 0 0 PRO 0 Description PRO: PACKET_TYPE_PROMISCUOUS. 1: All frames received by the Ethernet MAC are forwarded up toward the CPU. 0: Disabled (default). AMALL: PACKET_TYPE_ALL_MULTICAST. 1: All multicast frames received by the Ethernet MAC are forwarded up toward the CPU, not just the frames whose scrambling result of DA matching with multicast address list provided in Multicast Filter Array Register. 0: Disabled. This only allows multicast frames whose scrambling result of DA field matching with multicast address list provided in Multicast Filter Array Register to be forwarded up toward the CPU (default). SEP: Save Error Packet. 1: Received packets with CRC error are saved and forwarded to the CPU anyway. 0: Received packets with CRC error are discarded automatically without forwarding to the CPU (default). AB: PACKET_TYPE_BROADCAST. 1: All broadcast frames received by the Ethernet MAC are forwarded up toward the CPU (default). 0: Disabled. AM: PACKET_TYPE_MULTICAST. 1: All multicast frames whose scrambling result of DA matching with multicast address list are forwarded up to the CPU (default). 0: Disabled. AP: Accept Physical Address from Multicast Filter Array. 1: Allow unicast packets to be forwarded up toward CPU if the lookup of scrambling result of DA is found within multicast address list defined in Multicast Filter Array Register. 0: Disabled, that is, unicast packets filtering are done without regarding multicast address list. This only allows unicast packets matching with MACAR register to be accepted (default). AC: Reserved bit. For normal operation, please always write 1 to this bit. SO: Start Operation of Ethernet MAC. 1: start operation. 0: stop operation and reset Ethernet MAC packet buffer (default). 197 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Following is the truth table about unicast packet filtering condition. DA Matching MACAR? PRO bit Broadcast or Multicast Packet? Unicast Packet Filtered by Ethernet MAC? No 0 No Yes No 1 No No Yes (see Note below) 0 No No Note: DA Matching MACAR including following two cases: 1. Destination Address field of incoming packets matches with MACAR. 2. When AP (RCR.5) is set to 1and the scrambling result of DA is found within multicast address list. Multicast Packet Filtering As shown in Figure 117 below, the Multicast Filter Array (MFA) provides filtering of multicast addresses hashed through the CRC logic. All Destination Address field are fed through the 32 bits CRC generation logic and as the last bit of the Destination Address field enters the CRC, the 6 most significant bits of the CRC generator are latched. These 6 bits are then decoded by a 1 to 64 decoder to index a unique filter bit (FB0-63) in the Multicast Filter Array. If the filter bit selected is set, the multicast packet is accepted. The system designer would use a program to determine which filter bits to set in the multicast registers. All multicast filter bits that correspond to Multicast Filter Array Registers accepted by the node are then set to one. To accept all multicast packets all of the registers are set to all ones. Note that received Pause Frames are always filtered by Ethernet MAC regardless of MFA setting. 48 bits DA field (DA[40] = 1 indicating a multicast DA) 32-bit CRC Generator CRC [31:26] 1 to 64 bit decoder Index to MFA Multicast Filter Array Selected bit: 0: Reject the multicast packet 1: Accept the multicast packet Figure 117: Multicast Filter Array Hashing Algorithm Example: If the accepted multicast packet's destination address Y is found to hash to the value 32 (0x20), then FB32 in MA4 should be initialized to "1". This will allow the Ethernet MAC to accept any multicast packet with the destination address Y. Although the hashing algorithm does not guarantee perfect filtering of multicast address, it will perfectly filter up to 64 logical address filters if these addresses are chosen to map into unique locations in the multicast filter. Note: The LSB bit of received packet's first byte being "1" signifies a Multicast Address. 198 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY D7 FB7 FB15 FB23 FB31 FB39 FB47 FB55 FB63 MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 D6 FB6 FB14 FB22 FB30 FB38 FB46 FB54 FB62 D5 FB5 FB13 FB21 FB29 FB37 FB45 FB53 FB61 D4 FB4 FB12 FB20 FB28 FB36 FB44 FB52 FB60 D3 FB3 FB11 FB19 FB27 FB35 FB43 FB51 FB59 D2 FB2 FB10 FB18 FB26 FB34 FB42 FB50 FB58 D1 FB1 FB9 FB17 FB25 FB33 FB41 FB49 FB57 D0 FB0 FB8 FB16 FB24 FB32 FB40 FB48 FB56 Figure 118: Multicast Filter Array Bit Mapping Multicast Filter Array (MFA, 0x16) 7 Bit NAME Reset Value Bit 7:0 ... 63:56 6 5 4 3 MA 0 MA 1 MA 2 MA 3 MA 4 MA 5 MA 6 MA 7 0x0000_0000_0000_0000 2 1 0 Name Access Description MA 0 R/W The MA 7~0 is the multicast address bit map used by multicast frame filtering block ... where MA 0 represents bit 7~0 while MA 7 represents bit 63~56. For example. MA 7 DA = 81 81 81 81 81 81 81 CRC32 {crc31, 30,29,28,27,26} Address [5:0]=0x1A MFA [63:0] = 0000_0000_0400_0000 Following is the truth table about multicast packet filtering condition. PRO bit AMALL bit AM bit Pass Hashing Algorithm? Multicast Packet Filtered by Ethernet MAC? 0 0 0 0 Yes 0 0 0 1 Yes 0 0 1 0 Yes 0 0 1 1 No 0 1 0/1 0/1 No 1 0/1 0/1 0/1 No Note: Passing Hashing Algorithm means that the selected bit in MFA of CRC-32 result is set to "1". 199 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Broadcast Packet Filtering The broadcast filtering logic compares the Destination Address field (first 6 bytes of the received packet) to all 1's, that is, the values are "FFFF_FFFF_FFFF" in Hex format. If any bit of the six bytes does not equal to 1's, the Ethernet MAC rejects the packet if both unicast and multicast receive condition are not met. Following is a truth table about broadcast packet filtering condition. PRO bit AB bit Broadcast Packet? 0 1 Yes 0 0 Yes 1 0/1 Yes Broadcast Packet Filtered by Ethernet MAC? No Yes No CRC-Error Packet Filtering Normally, all the packets received with CRC error will be rejected by Ethernet MAC. When SEP bit (RCR.2) is enabled the packet with CRC error will be received and forwarded to CPU. Packet Filtering During Remote-Wakeup Enable Mode When CPU entering STOP or PMM mode with the remote wakeup function being enabled, the packet receive function of Ethernet MAC will be disabled and all the packets received will be filtered. The Magic Packet wakeup function is enabled by RWMP bit (SPWIE.4). The external pin, EXT_WKUP, wakeup function is enabled by EPWT bit (SPWIE.5). The Microsoft Wakeup Frame wakeup Function can be enabled by MWFE bit (SPWIE.6) and WFCR bit 0 or 2. Following is the truth table about packet filtering condition during remote-wakeup enable mode. RWMP bit EPWT bit EWFF0 bit EWFF1 bit Received Packet (SPWIE.4) (SPWIE.5) (WFCR.0) (WFCR.2) Type? 0 0 0 0 Any packets but Magic Packet 0 0 0 0 Magic Packet 1 0 0 0 Any packets but Magic Packet 1 0 0 0 Magic packet 0 0 1 0 0 0 0 0 10, 01, or 11 1 1 10, 01, or 11 1 1 10, 01, or 11 10, 01, or 11 Packet Filtered by Ethernet MAC? Based on unicast, multicast, and broadcast filtering rule No CPU not in STOP/PMM mode -> No. CPU in STOP/PMM mode -> Yes. CPU not in STOP/PMM mode -> No. CPU in STOP/PMM mode -> Yes and the CPU will be awaked up. Any packets No Any packets but CPU not in STOP/PMM mode -> No. Wakeup Frame CPU in STOP/PMM mode -> Yes. Microsoft Wakeup CPU not in STOP/PMM mode -> No. Frame CPU in STOP/PMM mode -> Yes and the CPU will be awaked up. Any packets but CPU not in STOP/PMM mode -> No. Magic Packet and CPU in STOP/PMM mode -> Yes. Wakeup Frame Magic Packet or CPU not in STOP/PMM mode -> No. Wakeup Frame CPU in STOP/PMM mode -> Yes and the CPU will be awaked up. Table 42: Packet Filtering During Remote-Wakeup Enable Mode Note that when the primary or secondary PHY linkup wakeup function is enabled, it normally means the Ethernet PHY link is down during PMM or STOP mode. Therefore, there will be no packets coming in to Ethernet MAC from the Ethernet PHY so the packet filtering is meaningless here. 200 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 4.15.3 Ethernet MAC Packet Transmit Preamble, Sync, Padding and CRC When transmitting the Ethernet packets, the Ethernet MAC will automatically append the preamble and sync byte at the beginning of the packet. It will also generate the padding bytes (if transmitted packet size is less than 60 bytes) and the 4 bytes CRC field at the end of the packet (if ACB bit in Flag byte in I2C EEPROM is enabled). The minimum size of an Ethernet packet without preamble is 64 bytes. Preamble Synch Destination Address Source Address Length/Type Data + Padding (if needed) CRC 7 bytes 1 byte 6 bytes 6 bytes 2 bytes Min 46 bytes 4 bytes Figure 119: Ethernet Packet Format Collision During transmission when operating in half duplex mode, the Ethernet MAC monitors the collision signal from Ethernet PHY to determine if a collision has occurred. If a collision is detected, the Ethernet MAC will reset the FIFO and restore the transmit pointers for retransmission of the packet based on exponential backoff algorithm. If 15 retransmissions each result in a collision, the transmission will be aborted and the transmitted packet is discarded after 16 transmission attempts. Medium Status and Mode Register (MSMR, 0x20) 7 RFC 1 Bit Name Reset Value Bit Name Access 0 SM R/W 1 BPC R/W 2 RE R/W 3 PF R/W 4 TFC R/W 5 FD R/W 6 PS 1 5 FD 1 4 TFC 1 3 PF 0 2 RE 0 1 BPC 0 0 SM 0 Description SM: Super Mac support. 1: Enable Super Mac to shorten exponential back-off time during each transmit retries. 0: Disabled (default). BPC: Backpressure Continuously. 1: When TFC bit = 1, setting this bit enables backpressure on TX direction "continuously" during RX buffer full condition in half duplex mode. 0: When TFC bit = 1, setting this bit enable backpressure on TX direction "intermittently" during RX buffer full condition in half duplex mode (default). RE: Receive Enable. 1: Enable RX path of the Ethernet MAC. 0: Disabled (default). PF: Check only "length/type" field for Pause Frame. 1: Enable, i.e., Pause frame is identified only based on L/T filed. 0: Disabled, i.e., Pause frames are identified based on both DA and L/T fields (default). TFC: TX Flow Control enable. 1: Enable transmitting pause frame on TX direction in full duplex mode or enable transmitting jam pattern on TX direction in half duplex mode during RX buffer's free buffer less than low water mark setting (default). 0: Disabled. FD: Full Duplex mode 1: Full Duplex mode (default). 0: Half Duplex mode. 201 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 6 PS R/W 7 RFC R/W PS: Port Speed in Ethernet MAC. 1: 100 Mbps (default). 0: 10 Mbps. RFC: RX Flow Control enable. 1: Enable receiving pause frame on RX direction during full duplex mode (default). 0: Disabled. IPG Control Register (IPGCR, 0x0C) 7 CPEF Reserve d Reserve d Bit NAME 6 5 4 2 1 0 IPG 2 0x12_0C_95 Reset Value Bit Name Access 6:0 IPG 0 7 3 IPG 0 IPG 1 Description IPG 0 [6:0]: Inter Packet Gap for back-to-back transfer on TX direction in Ethernet MAC (default = 15h). R/W CPEF R/W 14:8 IPG 1 22:16 IPG 2 R/W R/W Capture Effective setting in half duplex operation. 1: To shorten backoff time for 2nd collision retransmission in half duplex mode (default). 0: Normal exponential backoff time is used for 2nd collision retransmission in half duplex mode. IPG1 [6:0]: IPG part1 value (default = 0Ch). Bit 15 is reserved. IPG2 [6:0]: IPG part1 value + part2 value (default = 12h). Bit 23 is reserved. Test Register (TR, 0x1E) 7 Bit Name Reset Value Bit Name 6 5 Reserved 4 00_0000 Access 0 LDRND R/W 1 CRC_ER CR 3 ABORT 2 Reserved 1 CRC_ER 0 0 LDRND 0 Description LDRND: Load Random number into Ethernet MAC's exponential back-off timer. User writes a "1" to enable loading a small random number into MAC's back-off timer to shorten the back-off duration in each retry after collision. This register is used for test purpose. Default value = 0. This bit will be `1' whenever receiving packets with CRC error. This bit will be clear after software reads it. 2 Reserved 3 ABORT CR In half duplex mode, this bit will be `1' whenever the transmitted frame has been aborted and dropped by Ethernet MAC after 15 retransmission attempts. This bit is not used in full duplex mode. 7: Reserved 4 202 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 4.15.4 Ethernet MAC Buffer Management Receive/Transmit Packet Buffer SRAM Map The Ethernet MAC embeds a dedicated 8K bytes SRAM for its Receive Packet Buffering and a dedicated 4K bytes SRAM for its Transmit Packet Buffering. The RX Packet Buffer is divided into 32 pages while the TX Packet Buffer is divided into 16 pages. Each page has 256 bytes of storage space. Figure 120 shows the data structure of the Packet Buffer memory. The first 8 bytes preceding each Ethernet packets are status bytes. After the 8 status bytes is the Ethernet packet DA, SA, LT fields, etc. Both Receive and Transmit Packet Buffer memory can be access via RTSCR and RTSDR registers described below. Note that these two registers are used only for debug purpose and normal packet receive/transmit should be accessed through TOE as described in section 4.14. bit 0 bit 63 0 31 Page 0 0 31 Page 1 NPR [15:0] WPR [15:0] Length[15:0] DA[47:0] SA[31:0] ~Length[15:0] SA[47:32] L/T[15:0] Payload 0 NPR: Indicates the starting page of the next Ethernet frame. WPR: Indicates the end page of the current frame. Length: Length of the current Ethernet frame, including CRC field. ~Length: Bitwise negation of Length field. Page 31 or 16 Figure 120: Ethernet Packet Buffer Data Structure in Ethernet MAC Rx/Tx SRAM Command Register (RTSCR, 0x00) Bit Name 7 READ 6 GO 5 4 TX Reset Value 3 ADDR[7:0] Reserved 0x0000 2 1 0 ADDR[9:8] Bit Name Access Description 7:0 The read/write address {ADDR [9:8], ADDR [7:0]} of RX Packet SRAM. ADDR R/W 9:8 The read/write address {ADDR [8], ADDR [7:0]} of TX Packet SRAM. RAM selection. 0: indicates to read/write to RX Packet SRAM. 13 TX R/W 1: indicates to read/write to TX Packet SRAM. [4:2] Reserved Setting GO bit to "1" to initiates the SRAM read or write access request to the internal SRAM arbiter. This bit will remain "1" while the access request is still in progress and be 14 GO R/W1 cleared automatically by arbiter after current access request is completed. Note: software can only write"1" to this bit and can't write"0". Setting READ bit to "1" indicates to read from SRAM. Setting READ bit to "0" indicates to 15 READ R/W write to SRAM. 203 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Rx/Tx SRAM Data Register (RTSDR, 0x02) 7 Bit Name 6 5 Reset Value Bit Name Access 7:0 BUFFER_DATA 0 ... ... 63:56 BUFFER_DATA 7 R/W 4 3 BUFFER_DATA 0 BUFFER_DATA 1 BUFFER_DATA 2 BUFFER_DATA 3 BUFFER_DATA 4 BUFFER_DATA 5 BUFFER_DATA 6 BUFFER_DATA 7 0x0000_0000_0000_0000 2 1 0 Description The BUFFER_DATA 7~0 is the content of the RX or TX SRAM where BUFFER_DATA 0 represents bit 7~0 of the SRAM while BUFFER_DATA 7 represents bit 63~56. When writing to the SRAM, software needs to first write desired data into this register before issuing RTSCR register. When reading from the SRAM, software first issues RTSCR register and then retrieves the SRAM data from this register. Flow Control in Full Duplex Mode Flow Control on RX Direction Flow control in RX direction is used to avoid RX packet buffer being overflowed in full-duplex mode, it's enabled by TFC and FD bit (MSMR bit 4,5). The Ethernet MAC uses a Buffer Ring structure to store the received packets (see Figure 121) and maintain a Free Buffer Counter (FBC). The FBC is counting the free memory pages. When flow control is enabled, the Ethernet MAC will send out Pause ON frame to notify the other end to stop sending packets when its FBC is less than "Low Water Mark" being defined in I2C EEPROM offset 0x11. The format of the Pause Frame is shown in Figure 122. The Ethernet MAC will send out Pause OFF frame when its FBC is over "High Water Mark" being defined in I2C EEPROM offset 0x10. Figure 121 Transmit/Receive Buffer Ring Structure DA = SA= L/T= 0180_C200_0001 0000_0000_0000 DA = SA= 0180_C200_0001 0000_0000_0000 Pause Time Padding 8808 0001 FF00 Pause On Frame L/T= Pause Time Padding 8808 0001 0000 Pause OFF Frame Figure 122: Pause Frame 204 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Flow Control on TX Direction When enabled RFC bit (MSMR.7) in full duplex mode, the Ethernet MAC will stop sending packets out towards the other end, upon receiving the Pause ON Frame. It will resume transmitting packets after the pause timer times out. The duration of this pause timer is specified in the received packet's Pause Time Field. The Ethernet MAC can recognize either one of the following conditions as a Pause Frame: z Destination Address field equals to the multicast address, 01-80-C2-00-00-01, and Length/Type Field = 0x8808 z Length/Type Field = 0x8808 Above condition is determined by PF bit (MSMR.3). Backpressure in Half Duplex Mode The backpressure mechanism is used to avoid RX packet buffer being overflowed in half-duplex mode, it's enabled by TFC bit (MSMR.4). When backpressure mechanism is enabled, the Ethernet MAC will send out Jam pattern to force collision and force the other end to backoff from current transmission when its FBC is less than "Low Water Mark". The format of this Jam pattern consists of 16 bytes of 0x55. 4.15.5 Magic Packet and Wakeup Frame When the PMM or STOP mode is invoked, the CPU can be awaked up by two types of Ethernet frame - Magic Packet or Microsoft Wakeup Frame. Note that during these two types of packet remote wakeup mode, the Ethernet PHY shall not be set in reset or power down mode in BMCR register to allow Ethernet packet reception. Magic Packet Wakeup Function Magic Packet is an easy and simple MAC layer Ethernet frame used to awake up the AX11015. Setting RWMP bit (SPWIE.4) prior to entering STOP or PMM mode can enable Magic Packet Wakeup Function. Once the Ethernet MAC has been put into the Magic Packet wakeup enable mode, it monitors all incoming frames for a specific data sequence. This sequence can be located anywhere after the Length/Type field but is preceded by a synchronization stream (6 bytes of 0xFF). The data sequence is 16 iterations of the MAC address of this chip. See Figure 123 below. When Ethernet MAC detects this type of packet, it will generate interrupt on INT6 to awake up the CPU and report this wakeup event in WPLS register. Assume the MAC address of this chip is "00123456789A". DA SA L/T Payload 00123456789a xxxxxxxxxxxx 0800 xxxx_FFFFFFFFFFFF_00123456789a_00123456789a_00123456789a_001234 56789a_00123456789a_00123456789a_00123456789a_00123456789a_00123 456789a_00123456789a_00123456789a_00123456789a_00123456789a_0012 3456789a_00123456789a_00123456789a_xxxxxxxx Figure 123: Example Magic Packet Format Wakeup Frame Wakeup Function. Wakeup Frame is used to awake up the AX11015 from receiving a more complex Ethernet frame, which can be defined with specific TCP/IP header and payload pattern. User can define the pattern of this wakeup frame and set MWFE bit (SPWIE.6) and either EWFF0 or WSFF1 bit in WFCR register to enable this Wakeup Frame wakeup function prior to entering STOP or PMM mode. Once enabled, the Ethernet MAC monitors all incoming frames for this user-defined pattern. If matched, the Ethernet MAC will generate interrupt on INT6 to awake up the CPU and report this wakeup event in WPLS register. There are two filter sets supported in the Ethernet MAC, which can define two different patterns of Wakeup Frame. The filter set consists of Wakeup Frame Command Register, Wakeup Frame Byte Mask Register, Wakeup Frame CRC Register, Wakeup Frame Offset Register, and Wakeup Frame Last Byte Register. Also, if a more complex pattern of Wakeup Frame is needed, user can choose to cascade the two filter sets into one and specify a longer pattern for Wakeup Frame matching. 205 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY STOP and PMM Wakeup Interrupt Enable Register (SPWIE, 0x24) 7 Reserved 0 Bit Name Reset Value Bit Name 6 MWFE 0 5 EPWT 0 4 RWMP 0 3 Reserved 0 2 1 SPLWE Reserved 0 0 0 PPLWE 0 Access 0 PPLWE Description PPLWE: Primary PHY Linkup Wakeup Enable Register R/W 1: Enable Interrupt 0: Disable Interrupt (Default) 1 Reserved 2 SPLWE R/W SPLWE: Secondary PHY Linkup Wakeup Enable Register 1: Enable Interrupt 0: Disable Interrupt (Default) 3 Reserved 4 RWMP 5 EPWT 6 MWFE RWMP: Remote Wakeup trigger by Magic Packet. 1: Enable. 0: Disabled (default). EPWT: External Pin Wakeup trigger R/W 1: Enable 0: Disabled (default). MWFE: Microsoft Wakeup Frame Enable Register R/W 1: Enable 0: Disabled (default). R/W 7 Reserved Note: 1. The CPU can be awaked up by various wakeup events if software enables this register. Upon enabled, the wakeup events will trigger the INT 6 of the CPU. 2. After the CPU awakes up, software can read WPLS register to identify the source of wakeup events. PHY Link Change Interrupt Enable Register (PLCIE, 0x26) 7 Bit Name Reset Value Bit Name 0 PLCIE 1 Reserved 2 SLCIE 6 5 Reserved 0 4 3 2 SLCIE 0 1 Reserved 0 0 PLCIE 0 Access Description PLCIE: Primary PHY Link Change Interrupt Enable Register. R/W 1:Enable Primary PHY Interrupt. 0:Disable Primary PHY Interrupt (Default). R/W SLCIE: Second PHY Link Change Interrupt Enable Register. 1:Enable Second PHY Interrupt. 0:Disable Second PHY Interrupt (Default). 7:3 Reserved Note: 1. The Ethernet MAC will check the link status of both primary and secondary Ethernet PHY for every 200ms, if the link status is changed and above PLCIE is also enabled, an interrupt on INT 4 is generated to CPU (both link-up or link-down transition can cause an interrupt to be generated) 2. After the CPU is interrupted, the software can read WPLS register on PPLSCR, PPLSR, SPLSCR, and SPLSR bits to learn about the latest link status. Wakeup and PHY Link Status Register (WPLS, 0x28) 206 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 7 Bit Reserved Name 0 Reset Value Bit Name Access 0 PPLSCR 1 CR PPLSR R 2 SPLSCR CR 3 SPLSR R 4 MPSR CR 5 EWPSR CR 6 MWFSR CR 6 MWFSR 0 5 EWPSR 0 4 MPSR 0 3 SPLSR 0 2 SPLSCR 0 1 PPLSR 0 0 PPLSCR 0 Description PPLSR: Primary PHY Link Status Changed Register. 1: Whenever Primary PHY's Link status changed, this bit will be set to 1. 0: This bit will be cleared after software reads it. PPLSR: Primary PHY Link Status Register. 1: The link status of Primary PHY is link-up. 0: The link status of Primary PHY is link-down. SPLSR: Secondary PHY Link Status Changed Register. 1: Whenever Secondary PHY's Link status changed, this bit will be set to 1. 0: This bit will be cleared after software reads it. SPLSR: Secondary PHY Link Status Register. 1: The link status of Secondary PHY is link-up. 0: The link status of Secondary PHY is link-down. MPSR: Magic Packet Status Register. 1: Whenever Ethernet MAC receives Magic Packet and awakes up the CPU. 0: This bit will be cleared after software reads it. EWPSR: External Wakeup Pin Status Register. 1: Whenever user triggers the external wakeup pin, EXT_WKUP, and awakes up the CPU. 0: This bit will be cleared after software reads it. MWFSR: Microsoft Wakeup Frame Status Register. 1: Whenever Ethernet MAC receives Microsoft Wakeup Frame and awakes up the CPU. 0: This bit will be cleared after software reads it. 7 Reserved Note: 1. Both SPWIE and PLCIE use WPLS register to report status, the software should read this register after receiving INT 6 or INT 4. Wakeup Frame Command Register (WFCR, 0x30) 7 Bit Name Reset Value Bit Name Access 0 EWFF0 RW 1 EUM0 RW 2 EWFF1 RW 3 RW EUM1 6 Reserved 000 5 4 ECFF 0 3 EUM1 0 2 EWFF1 0 1 EUM0 0 0 EWFF0 0 Description Enable Wakeup Frame Filter 0 (WFF0), which consists of WFBM0, WFCRC0, WFOS0, and WFLB0 registers. Please program WFBM0, WFCRC0, WFOS0, and WFLB0 registers before setting this bit. 1: Enabled wakeup frame detection mode for WFF0. 0: Disabled wakeup frame detection mode for WFF0. Enable Unicast Match mode for Wakeup Frame Filter 0. 1: When receiving frame with DA equal to MACAR and WFF0 is matched, then the packet is considered as valid wakeup frame. 0: When receiving frame with any DA but the WFF0 is matched, then the packet is considered as valid wakeup frame. Enable Wakeup Frame Filter 1 (WFF1), which consists of WFBM1, WFCRC1, WFOS1, and WFLB1 registers. Please program WFBM1, WFCRC1, WFOS1, and WFLB1 registers before setting this bit. 1: Enabled wakeup frame detection mode for WFF1. 0: Disabled wakeup frame detection mode for WFF1. Enable Unicast Match mode for Wakeup Frame Filter 1. 1: When receiving frame with DA equal to MACAR and WFF1 is matched, then the 207 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 4 ECFF RW packet is considered as valid wakeup frame. 0: When receiving frame with any DA but the WFF1 is matched, then the packet is considered as valid wakeup frame. Enable Cascading wakeup Frame Filter 1: Enable cascading the WFF0 and WFF1 into one filter. When enabled, the WFBM0, WFBM1, WFOS0, WFOS1, WFLB1, WFCRC1 will be used, and the WFCRC0 and WFLB0 registers are not used. When enabled, the EWFF0, EWFF1 should both be set to 1 at the same time, and the EUM0, EUM1 should both be set to 1 or 0 at the same time. The value of WFOS1 indicates the offset from the last byte of first filter, WFF0. For example, if WFOS0 = 0x08, and WFOS1 = 0x06, then the first bit of WFBM1 is used as byte mask for the ((8*2) + 32 + (6*2) + 1)th byte in the wakeup frame. In other words, the first bit of WFBM1 is the byte mask of ((WFOS0*2) + 32 + (WFOS1*2) +1)th byte in the wakeup frame. 0: The WFF0 and WFF1 functions as two independent wakeup frame filters. 7: Reserved 5 Wakeup Frame Byte Mask 0 Register (WFBM0, 0x32) 7 Bit 6 5 4 Name Reset Value 3 BM_0_0 BM_0_1 BM_0_2 BM_0_3 0x0000_0000 2 1 0 Bit Name Access Description BM_0_3 ~ 0_0 is the 32 bit for byte mask. The byte mask defines which bytes in the 7:0 BM_0_0 incoming frame will be examined to determine whether or not this is a wake-up frame. ... ... RW The BM_0_0 represents bit 7~0 and BM_0_3 represents bit 31~24. 31:24 BM_0_3 Wakeup Frame CRC 0 Register (WFCRC0, 0x36) 7 Bit 6 5 4 Name Reset Value Bit Name 7:0 CRC_0_0 15:8 CRC_0_1 Access RW 3 CRC_0_0 CRC_0_1 0x0000 2 1 0 Description This register defines the 16-bit CRC value of the valid wakeup frames. Software should calculate this based on the valid wakeup frame patterns, WFOS0 and WFBM0 settings. This value is used to compare with the CRC calculated on the incoming frame, when matched and the WFLB0 is also matched, then the frame is considered as valid wakeup frame. CRC_0_0 represents bit 7~0 and CRC_0_1 represents bit 15~8. CRC-16 Polynomials = X^16 + X^15 + X^2 + 1 208 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Wakeup Frame Offset 0 Register (WFOS0, 0x38) 7 Bit Name Reset Value Bit Name Access 7: OFFSET_ 0 0 RW 6 5 4 3 OFFSET_0 0x00 2 1 0 Description This register defines the offset of the first byte in the incoming frame from which the CRC is calculated for the wakeup frame recognition. Each value represents two bytes in the frame. For example: The offset value of 0 is the first byte of the incoming frame's destination address. The offset value of 1 is the 3rd byte of the incoming frame, etc. Wakeup Frame Last Byte 0 Register (WFLB0, 0x3A) 7 Bit Name Reset Value 5 4 3 2 1 0 LB_0 0x00 Bit Name Access 7: LB_0 0 6 RW Description This 1-byte pattern is used to compare with the last masked byte in the incoming frame. The last masked byte is the byte of the last bit mask being 1 in WFBM0. A valid wakeup frame shall have both WFCRC0 and WFLB0 match conditions. Wakeup Frame Byte Mask 1 Register (WFBM1, 0x40) 7 Bit 6 5 4 Name Reset Value 3 BM_1_0 BM_1_1 BM_1_2 BM_1_3 0x0000_0000 2 1 0 Bit Name Access Description BM_1_3 ~ 1_0 is the 32 bit for byte mask. The byte mask defines which bytes in the 7:0 BM_1_0 ... ... RW incoming frame will be examined to determine whether or not this is a wake-up frame. The BM_1_0 represents bit 7~0 and BM_1_3 represents bit 31~24. 31:24 BM_1_3 Wakeup Frame CRC 1 Register (WFCRC1, 0x44) 7 Bit 6 5 4 Name Reset Value Bit Name 7:0 CRC 1_0 15:8 CRC 1_1 Access RW 3 CRC_1_0 CRC_1_1 0x0000 2 1 0 Description This register defines the 16-bit CRC value of the valid wakeup frames. Software should calculate this based on the valid wakeup frame patterns, WFOS0 and WFBM0 settings. This value is used to compare with the CRC calculated on the incoming frame, when matched and the WFLB0 is also matched, then the frame is considered as valid wakeup frame. CRC_1_0 represents bit 7~0 and CRC_1_1 represents bit 15~8. CRC-16 Polynomials = X^16 + X^15 + X^2 + 1. 209 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Wakeup Frame Offset 1 Register (WFOS1, 0x46) 7 Bit Name Reset Value Bit Name Access 7: OFFSET_ 0 1 RW 6 5 4 3 OFFSET_1 0x00 2 1 0 Description This register defines the offset of the first byte in the incoming frame from which the CRC is calculated for the wakeup frame recognition. Each value represents two bytes in the frame. For example: The offset value of 0 is the first byte of the incoming frame's destination address. The offset value of 1 is the 3rd byte of the incoming frame, etc. Wakeup Frame Last Byte 1 Register (WFLB1, 0x48) Bit Name Reset Value Bit 7 6 5 4 Nam Access e 7: LB_1 0 RW 3 2 1 0 LB_1 0x00 Description This 1-byte pattern is used to compare with the last masked byte in the incoming frame. The last masked byte is the byte of the last bit mask being 1 in WFBM0. A valid wakeup frame shall have both WFCRC1 and WFLB1 match conditions. Wakeup Frame Example If following packet pattern is defined as a Wakeup Frame and the Ethernet MAC will monitor packet with DA = 1234_5678_9abc and L/T=0800. Field Byte Mask Mask Data DA SA L/T Payload 1 1 1 1 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12 34 56 78 9a bc 08 00 Software should set following registers, 1. SPWIE: Enable MWFE bit. 2. WFBM0: Set to 0x0000_303f, where BM_0_0 = 0x3f (indicating byte 0 to 5 are used to compare and byte 6~7 are not used), BM_0_1 = 0x30, BM_0_2 = 0x00, and BM_0_3 = 0x00. 3. WFCRC0: The pattern is "12, 34, 56, 78, 9a, bc, 08, 00", so the CRC-16 result is 0x8fbb. 4. WFOS0: The pattern is compared at the first byte of packet, so offset is 0x00. 5. WFLB0: The last byte of the pattern is 00, so set this register to 0x00. 6. WFCR: Set this register to 0x01 to enable the filter set 0. This register should be set at the end of the procedure. 210 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY PHY Control Register (PCR, 0x22) 7 Bit Name Reset Value Bit Name 0 PSEL 1 Reserved 2 IPRL 6 5 Reserved 0 4 3 2 IPRL 1 1 Reserved 1 0 PSEL 1 Access Description PSEL: PHY Select. R/W 1: Select embedded 10/100 Ethernet PHY (default). 0: Select external PHY, which is attached to the MII interface. IPRL: Internal Ethernet PHY Reset control. This bit controls the reset signal of internal Ethernet PHY. R/W 1: Internal Ethernet PHY is in operating state (default). 0: Internal Ethernet PHY in reset state. 7:3 Reserved 211 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 4.16 10/100M Ethernet PHY The 10/100 Ethernet PHY of AX11015 is compliant with IEEE 802.3 and IEEE 802.3u standards. It contains an on-chip crystal oscillator, PLL-based clock multiplier, and digital phase-locked loop for data/timing recovery. It provides over-sampling mixed-signal transmit drivers complying with 10/100BASE-TX transmit wave-shaping / slew rate control requirements. It has robust mixed-signal loop adaptive equalizer for receiving signal recovery. z Support full-duplex mode, half-duplex mode, and auto-negotiation z Support twisted pair crossover detection and auto-correction (Auto-MDIX) z DSP-based adaptive line equalizer, providing superior immunity to near end crosstalk and inter-symbol interference z Fully compliant with 100BASE-TX, and 10BASE-T PMD level standards (IEEE 802.3u and IEEE 802.3) z DSP-controlled symbol timing recovery circuit z Baseline wander corrective circuits to compensate data dependent offset due to AC coupling transformers z Over-sampling mixed-signal transmit driver complies with 10/100BASE-TX transmit wave-shaping/slew-control requirements PMA (Physical medium attachment sublayer) PCS (Physical coding sublayer) 4B/5B coding/decoding carrier detect PMD (Physical medium dependent sublayer) 100 TX RXIP/N Slicer MII RX MII TX (Ethernet MAC) Decision feedback equalizer Interface Timing recovery and baseline compensation AGC BLC A/D Feedforward equalizer 100RX MUX Adaptive equalizer TXOP/N MII Station Management Interface Link monitor / signal detect 10BASE - receiver 10BASE - transmitter MII serial management interface and registers PLL clock generator Test / LED control Auto negotiation PHY_ID = 1_0000 Figure 124: 10/100M Ethernet PHY Block Diagram 212 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 4.16.1 MII Station Management Function The primary function of station management is to transfer control and status information of the Ethernet PHY to a management entity. This function is accomplished by the MDC clock input from Ethernet MAC (frequency is about 1.5 MHz) along with the MDIO signal to/from the Ethernet PHY. The embedded Ethernet PHY's ID address is fixed to "1_0000". Frames transmitted on the MII management interface will have the frame structure shown in Figure 125. The order of bit transmission is from left to right. Note that reading and writing the management register must be completed without interruption. Read/Write Read Write Field Preamble ST OP PHY ID REGAD TA DATA IDLE Preamble 1. . .1 1. . .1 ST 01 01 OP 10 01 PHY ID AAAAA AAAAA REGAD RRRRR RRRRR TA Z0 10 DATA DDDDDDDDDDDDDDDD DDDDDDDDDDDDDDDD Description Preamble of MII station management frame, which consists of 32 bits of 1. Start of Frame. The start of frame is indicated by a 01 pattern. Operation Code. The operation code for a read transaction is 10. The operation code for a write transaction is a 01. PHY Address. The PHY address is 5 bits, allowing for 32 unique addresses. The first PHY address bit transmitted and received is the MSB of the address. A station management entity that is attached to multiple PHY entities must have prior knowledge of the appropriate PHY address for each entity. The embedded Ethernet PHY's address is fixed to "1_0000". Register Address. The register address is 5 bits, allowing for 32 unique registers within each PHY. The first register address bit transmitted and received is the MSB of the address. Turnaround. The turnaround time is a two-bits time spacing between the register address field, and the data field of a frame, to avoid drive contention on MDIO during a read transaction. During a write to the PHY, these bits are driven to 10 by the station. During a read, the MDIO is not driven during the first bit time and is driven to a 0 by the PHY during the second bit time. Data. The data field is 16 bits. The first bit transmitted and received will be bit 15 of the register being addressed. Idle Condition. The IDLE condition on MDIO is a high-impedance state. All three state drivers will be disabled and the PHY's pull-up resistor will pull the MDIO line to logic 1. Figure 125: MII Station Management Frame Format 4.16.2 10/100M Ethernet PHY SFR Register Map Address 0xBE 0xBF IDLE Z Z Name EPCR EPDR Description Ethernet PHY Command Register Ethernet PHY Data Register Table 43: 10/100 Ethernet PHY SFR Register Map 213 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Ethernet PHY Command Register (EPCR, 0xBE) 7 Bit Name READ 6 Reserved GO 5 4 3 Reserved 2 REG_ADDR PHYID 1 0 0x0000 Reset Value Bit Name Access 4:0 REG_ADDR R/W 7:5 Reserved 12:8 PHYID R/W 13 Reserved 14 GO 15 READ Description The PHY register address to be accessed as listed in Table 44. These bits must be 0, except for "command abort" command. The PHY ID value. When accessing the embedded Ethernet PHY, write "1_0000". This bit must be 0, except for "command abort" command. Setting GO bit to "1" to initiate read or write access request to the Ethernet PHY registers. This bit will remain "1" while the access request is still in progress and be R/W1 cleared to 0 automatically after current access request is completed. Note: software can only write"1" to this bit and can't write"0". Setting READ bit to "1" indicates to read data from Ethernet PHY through EPDR. R/W Setting READ bit to "0" indicates to write data to Ethernet PHY through EPDR. Note: Command Abort operation: While software is reading/writing EPCR, the command can be aborted by writing EPCR register with data = 0xFF. After generating the "Command Abort operation", the following EPCR read/write command will start with accessing bit 7~0 of EPCR. Ethernet PHY Data Register (EPDR, 0xBF) Bit 7 6 5 4 3 PHY_DATA 0 PHY_DATA 1 0x0000 NAME Reset Value 2 1 0 Bit Name Access Description 7:0 PHY_DATA 0 R/W The PHY_DATA 1~0 is the register data being written to or read back from the 15:8 PHY_DATA 1 Ethernet PHY. When writing to Ethernet PHY, software needs to first write desired data into this register before issuing EPCR register. When reading from the Ethernet PHY, software first issues EPCR register and then retrieves the read data from this register. Note: Command Abort operation: While software is reading/writing EPDR, the command can be aborted by writing EPCR register with data = 0xFF. After generating the "Command Abort operation", the following EPDR read/write command will start with accessing bit 7~0 of EPDR. 10/100M Ethernet PHY Register Indirect Access Method Software shall use indirect access method through EPCR and EPDR registers to do read and write access to the Ethernet PHY registers as listed in Table 44. Read a register from 10/100M Ethernet PHY: Step 1. Write EPCR two times: Software indicates REG_ADDR in first write and indicates PHYID and sets READ=1 and GO=1 in second write to SFR register EPCR. Step 2. Read EPCR: Software should keep reading EPCR until GO bit become 0. When GO bit is clear, the Ethernet PHY register data is presented on SFR register EPDR. Note that each EPCR read cycle consists of two SFR bus read accesses to retrieve the 16 bits wide data in EPCR. Step 3. Read EPDR two times: Software then read SFR register EPDR which now stores the read data of Ethernet PHY register provided in step 1. Note that the first read returns the 7:0 bits of Ethernet PHY register data. 214 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Write a register to 10/100M Ethernet PHY: Step 1. Write EPDR two times: Software writes the data you want to write into Ethernet PHY register to SFR register EPDR. The first write is the LSB byte that maps to Ethernet PHY register's 7:0 bits. Step 2: Write EPCR two times: Software indicates REG_ADDR in first write and indicates PHYID and sets READ=0 and GO=1 in second write to SFR register EPCR. Step 3: Read EPCR: Software should keep reading EPCR until GO bit become 0. When GO bit is clear, the requested write to Ethernet PHY register is completed. Note that each EPCR read cycle consists of two SFR bus read accesses to retrieve the 16 bits wide data in EPCR. Embedded 10/100M Ethernet PHY Register Map Address 0h 1h 2h 3h 4h 5h 6h 7h 8h-Fh Register Name BMCR BMSR PHYIDR1 PHYIDR2 ANAR ANLPAR ANER Reserved IEEE reserved Description Basic mode control register, basic register. Basic mode status register, basic register. PHY identifier register 1, extended register. PHY identifier register 2, extended register. Auto negotiation advertisement register, extended register. Auto negotiation link partner ability register, extended register. Auto negotiation expansion register, extended register. Reserved and currently not supported. IEEE 802.3u reserved. Table 44: Embedded 10/100M Ethernet PHY Register Map Basic Mode Control Register (BMCR, 0x00) Bit Bit Name 15 Reset 14 Loopback 13 Speed selection 12 Auto-negotia tion enable 11 Power down 10 Isolate 9 Restart auto-negotiat ion 8 Duplex mode 7 Collision test 6:0 Reserved Reset Value Access Description 0 Reset. R/W/SC 1: Software reset. 0: Normal operation. 0 Loopback. R/W 1: Loopback enabled. 0: Normal operation. 1 Speed selection. R/W 1: 100 Mb/s. 0: 10 Mb/s. 1 Auto-negotiation enable. 1: Auto-negotiation enabled. Bits 8 and 13 of this register are R/W ignored when this bit is set. 0: Auto-negotiation disabled. Bits 8 and 13 of this register determine the link speed and mode. 0 Power down. R/W 1: Power down. 0: Normal operation. , Isolate. (PHYAD = 00000) R/W 1: Isolate. 0: Normal operation. 0 Restart auto-negotiation. R/W/SC 1: Restart auto-negotiation. 0: Normal operation. 1 Duplex mode. R/W 1: Full duplex operation. 0: Normal operation. 0 Collision test. R/W 1: Collision test enabled. 0: Normal operation. RO 215 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Basic Mode Status Register (BMSR, 0x01) Bit Bit Name Reset Value Access 15 100BASE-T4 14 13 12 11 10:7 100BASE-TX full duplex 100BASE-TX half duplex 10BASE-T full duplex 10BASE-T half duplex Reserved 0 RO/PS 1 RO/PS 1 RO/PS 1 RO/PS 1 RO/PS 0 RO 6 MF preamble suppression 0 RO/PS 5 Auto-negotiati on complete 0 RO 4 Remote fault 0 RO/LH 3 Auto-negotiati on ability 1 RO/PS 2 Link status 0 RO/LL 1 Jabber detect 0 RO/LH 0 Extended capability 1 RO/PS Description 100BASE-T4 capable. 0: This PHY is not able to perform in 100BASE-T4 mode. 100BASE-TX full-duplex capable. 1: This PHY is able to perform in 100BASE-TX full-duplex mode. 100BASE-TX half-duplex capable. 1: This PHY is able to perform in 100BASE-TX half-duplex mode. 10BASE-T full-duplex capable. 1: This PHY is able to perform in 10BASE-T full-duplex mode. 10BASE-T half-duplex capable. 1: This PHY is able to perform in 10BASE-T half-duplex mode. Reserved. Write as 0, read as "don't care". Management frame preamble suppression. 0: This PHY will not accept management frames with preamble suppressed. Auto-negotiation completion. 1: Auto-negotiation process completed. 0: Auto-negotiation process not completed. Remote fault. 1: Remote fault condition detected (cleared on read or by a chip reset). 0: No remote fault condition detected. Auto configuration ability. 1: This PHY is able to perform auto-negotiation. Link status. 1: Valid link established (100Mb/s or 10Mb/s operation) 0: Link not established. Jabber detection. 1: Jabber condition detected. 0: No Jabber condition detected. Extended capability. 1: Extended register capable. 0: Basic register capable only. PHY Identifier Register 1 (PHYIDR1, 0x02) Bit Bit Name Reset Value Access 15:0 OUI_MSB 0x003B Description OUI most significant bits. RO/PS Bits 3 to 18 of the OUI are mapped to bits 15 to 0 of this register respectively. The most significant two bits of the OUI are ignored. PHY Identifier Register 2 (PHYIDR2, 0x03) Bit Bit Name 15:10 OUI_LSB Reset Value Access 00_0110 9:4 3:0 VNDR_MDL MDL_REV 00_0101 0001 Description OUI least significant bits: RO/PS Bits 19 to 24 of the OUI are mapped to bits 15 to 10 of this register respectively. RO/PS Vendor model number. RO/PS Model revision number. 216 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Auto Negotiation Advertisement Register (ANAR, 0x04) Bit 15 Bit Name Reset Value Access Description NP 0 Next page indication. RO/PS 0: No next page available. The PHY does not support the next page function. 14 ACK 0 Acknowledgement. RO 1: Link partner ability data reception acknowledged 0: Not acknowledged 13 RF 0 Remote fault. R/W 1: Fault condition detected and advertised 0: No fault detected 12:11 Reserved X R/W Reserved. Write as 0, read as "don't care". 10 Pause 0 Pause. R/W 1: Pause operation enabled for full-duplex links 0: Pause operation not enabled 9 T4 0 100BASE-T4 support. RO/PS 0: 100BASE-T4 not supported 8 TX_FD 1 100BASE-TX full-duplex support. R/W 1: 100BASE-TX full-duplex supported by this PHY. 0: 100BASE-TX full-duplex not supported by this PHY. 7 TX_HD 1 100BASE-TX half-duplex support: R/W 1: 100BASE-TX half-duplex supported by this PHY. 0: 100BASE-TX half-duplex not supported by this PHY. 6 10_FD 1 10BASE-T full-duplex support. R/W 1: 10BASE-T full-duplex supported by this PHY. 0: 10BASE-T full-duplex not supported by this PHY. 5 10_HD 1 10BASE-T half-duplex support. R/W 1: 10BASE-T half-duplex supported by this PHY. 0: 10BASE-T half-duplex not supported by this PHY. 4:0 Selector 0_0001 Protocol selection bits. These bits contain the binary encoded protocol selector supported by R/W this PHY. "0 0001" indicates that this PHY supports IEEE 802.3u CSMA/CD. Auto Negotiation Link Partner Ability Register (ANLPAR, 0x05) Bit Bit Name Reset Value Access 15 NP 0 RO 14 ACK 0 RO 13 RF 0 RO 12:11 Reserved X RO 10 Pause 0 RO 9 T4 0 RO 8 TX_FD 0 RO Description Next page indication. 1: Link partner next page enabled 0: Link partner not next page enabled Acknowledgement. 1: Link partner ability for reception of data word acknowledged 0: Not acknowledged Remote fault. 1: Remote fault indicated by link partner 0: No remote fault indicated by link partner Reserved. Write as 0, read as "don't care". Pause. 1: Pause operation supported by link partner 0: Pause operation not supported by link partner 100BASE-T4 support. 1: 100BASE-T4 supported by link partner 0: 100BASE-T4 not supported by link partner 100BASE-TX full-duplex support. 1: 100BASE-TX full-duplex supported by link partner 0: 100BASE-TX full-duplex not supported by link partner 217 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 7 TX_HD 0 RO 6 10_FD 0 RO 5 10_HD 0 RO 4:0 Selector 0_0000 RO 100BASE-TX half-duplex support. 1: 100BASE-TX half-duplex supported by link partner 0: 100BASE-TX half-duplex not supported by link partner 10BASE-T full-duplex support. 1: 10BASE-T full-duplex supported by link partner 0: 10BASE-T full-duplex not supported by link partner 10BASE-T half-duplex support. 1: 10BASE-T half-duplex supported by link partner 0: 10BASE-T half-duplex not supported by link partner Protocol selection bits. Link partner's binary encoded protocol selector. Auto Negotiation Expansion Register (ANER, 0x06) Bit 15:5 4 Bit Name Reserved PDF Reset Value 0 0 Access 0, RO 0, RO / LH 3 LP_NP_AB 0 0, RO 2 NP_AB 0 0, RO / PS 1 Page_RX 0 0, RO / LH 0 LP_AN_AB 0 0, RO Description Reserved. Write as 0, read as "don't care". Parallel detection fault. 1: Fault detected via the parallel detection function 0: No fault detected Link partner next page enable. 1: Link partner next page enabled 0: Link partner not next page enabled PHY next page enable. 0: PHY is not next page able. New page reception. 1: New page received 0: New page not received Link partner auto-negotiation enable. 1: Link partner auto-negotiation supported. 218 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 4.17 Programmable Counter Array The Programming Counter Array (PCA) provides more timing capabilities with less CPU intervention than the standard timer/counter. Its advantages include reduced software overhead and improved accuracy. As shown in Figure 126, the PCA consists of a dedicated timer/counter, which serves as the time base for an array of 5 compare/capture modules. The PCA uses 6 I/O pins, one external clock input pin, ECI, and five bi-directional capture/compare signal pins, CEX [4:0]. Each of the five modules can be programmed in any of the following modes: z Rising and/or falling edge capture z Software timer z High speed output z Pulse Width Modulator (PWM) PCA related SFR registers SFR Bus Operating system clock PCA Timer/Counter Timer 0 overflow PCA Capture/Compare module ECI Figure 126: Programmable Counter Array Block Diagram 4.17.1 Programmable Counter Array SFR Register Map Address 0xC2 0xC3 0xC4 0xC5 0xD1 0xB1 0xB9 0xD2 0xB2 0xBA 0xD3 0xB3 0xBB 0xD4 0xB4 0xBC 0xD5 0xB5 0xBD Register Name CMOD CCON CL CH CCAPM0 CCAP0L CCAP0H CCAPM1 CCAP1L CCAP1H CCAPM2 CCAP2L CCAP2H CCAPM3 CCAP3L CCAP3H CCAPM4 CCAP4L CCAP4H Description PCA Timer/Counter Mode Register. PCA Timer/Counter Control Register. PCA Timer/Counter. PCA Compare/Capture Module Mode Register 0. PCA Module 0 Compare/Capture Registers. PCA Compare/Capture Module Mode Register 1. PCA Module 1 Compare/Capture Registers. PCA Compare/Capture Module Mode Register 2. PCA Module 2 Compare/Capture Registers. PCA Compare/Capture Module Mode Register 3. PCA Module 3 Compare/Capture Registers. PCA Compare/Capture Module Mode Register 4. PCA Module 4 Compare/Capture Registers. Table 45: Programmable Counter Array SFR Register Map 219 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights CEX4 CEX3 CEX2 CEX1 CEX0 AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 4.17.2 PCA Timer/Counter The PCA timer is a free-running 16-bit timer consisting of registers CH and CL (the high and low bytes of the count values). As shown in Figure 127 and Table 46, the PCA timer/counter's reference timing tick can be selected from operating system clock with 4 different divider ratios, Timer 0 overflow, and the ECI pin input. The PCA timer is the common time base for all five modules. The timer/counter source is determined from the CPS[2:0] bits in the CMOD register. Figure 127: PCA Timer/Counter CPS[2:0] PCA Timer/Counter Mode 000 001 010 011 100 Mode 0: (Fclk / 25) Mode 1: (Fclk / 19) Mode 2: (Fclk / 8) Mode 3: (Fclk / 6) Mode 4: Timer 0 8-bit mode Overflows. Timer 0 16-bit mode programmed to: 8-bit auto-reload Mode 5: External input pin ECI (The max input frequency should be less than Fclk / 2) 111 PCA Timer/Counter Reference Timing Tick Operating System Clock Frequency (Fclk) 25MHz 50MHz 100MHz 1sec 0.76sec 0.32sec 0.24sec 0.5sec 0.38sec 0.16sec 0.12sec 0.25sec 0.19sec 0.08sec 0.06sec Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 > 80ns > 40ns > 20ns Note: 1. The reference timing tick is determined by the Timer 0 overflow rate programmed by software. In Mode 4, the overflow interrupt for Timer 0 does not need to be enabled. Table 46:PCA Timer/Counter Input Sources and Reference Timing Tick 220 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 4.17.3 Compare/Capture Modules Each PCA module has a mode register with it. These registers are: CCAPM0 for module 0, CCAPM1 for module 1, etc. Each register contains 7 bits that are used to control the mode in which each module will operate. Capture Mode Capture mode is used to capture the PCA timer/counter value into a module's capture registers (CCAPnH and CCAPnL). As shown in Figure 128 below, the capture will occur on a positive edge, negative edge, or both on the corresponding module's CEX[n] pin. To use one of the PCA modules in the capture mode, either one or both the CCAPM register bits CAPN and CAPP for that module must be set. When a valid transition occurs on the CEX[n] pin corresponding to the module used, the PCA hardware loads the 16-bit value of the PCA counter register (CH and CL) into the module's capture registers (CCAPnL and CCAPnH). The CCFn bit for the module in the CCON register is set by hardware. The value of trigger event CEXn after last trigger is reflected is CEXn bit of CCAPMn register. If the ECCFn bit in the CCAPMn register is set, then an interrupt on INT3 will be generated. In the interrupt service routine, the 16-bit capture value must be saved in memory before the next event capture occurs. If a subsequent capture occurred, the original capture values would be lost. After the event flag (CCFn) has been set by hardware, the user must clear the flag in software. A common use for the PCA capture mode is to measure the properties of a waveform. Properties such as the period, pulse width or the phase difference of two waveforms are measured by determining the difference in capture values between two edges of the waveform. The hardware support of the PCA capture mode allows accurate measurement of these properties with low software overhead. Figure 128: PCA Capture Mode 221 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 16-bit Software Timer Mode The 16-bit software timer mode is used to trigger interrupt routines, which must occur at periodic intervals. As shown in Figure 129, it is setup by setting both the ECOM and MAT bits in the module's CCAPMn register. The PCA timer will be compared to the module's capture registers (CCAPnL and CCAPnH) and when a match occurs, an interrupt on INT3 will occur, if the ECCFn bit in CCAPMn register for the module is set. If necessary, a new 16-bit compare value can be loaded into CCAPnH and CCAPnL during the interrupt routine. The user should be aware that the hardware temporarily disables the comparator function while these registers are being updated so that an invalid match will not occur. Thus, it is recommended that the user write to the low byte first (CCAPnL) to disable the comparator, then write to the high byte (CCAPnH) to re-enable it. If any updates to the registers are done, the user may want to hold off any interrupts from occurring by clearing the ECCFn bit or the EA bit. Figure 129: PCA Software Timer Mode (Compare Mode) 222 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY High Speed Output Mode In this mode, the CEX[n] output pin associated with the PCA module will toggle every time there is a match between the PCA counter (CH and CL) and the capture registers (CCAPnH and CCAPnL). As shown in Figure 130 below, to activate this mode, the user must set TOG, MAT, and ECOM bits in the module's CCAPMn register. High Speed Output mode is much more accurate than software pin toggling since the toggle occurs before branching to an interrupt. In this case, interrupt latency will not affect the accuracy of the output. When using High Speed Output mode, using an interrupt is optional. Only if the user wishes to change the time for the next toggle is it necessary to update the compare registers. Otherwise, the next toggle will occur when the PCA timer rolls over and matches the last compare value. Figure 130: PCA High-Speed Output Mode 223 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Pulse Width Modulator The Pulse Width Modulator (PWM) mode is used to generate a continuous square-wave with an arbitrary duty cycle. As shown in Figure 131 below, it generates 8-bit PWM by comparing the low byte of the PCA timer (CL) with the low byte of the compare register (CCAPnL). When CL < CCAPnL the output of CEX[n] is low. When CL >= CCAPnL the output CEX[n] is high. To activate this mode, the user must set the PWM and ECOM bits in the module's CCAPMn register. In PWM mode, the frequency of the output depends on the source for the PCA timer. See Table 47 below. Since there is only one set of CH and CL registers, all modules share the PCA timer and frequency. The frequency is fixed to 256 counts of the PCA timer. Duty cycle of the output is controlled by the value loaded into the high byte (CCAPnH). Since writes to the CCAPnH register are asynchronous, a new value written to the high byte will not be shifted into CCAPnL for comparison until the next period of the output (when CL rolls over from 255 to 00). To calculate values for CCAPnH for any duty cycle, use the following equation: CCAPnH = 256 * (1 - Duty Cycle) Where CCAPnH is an 8-bit integer and duty cycle is a fraction. Figure 131: PCA Pulse Width Modulator Mode PCA Timer Mode Max. PWM Frequency Operating System Clock (Fclk) 25MHz 50MHz 100MHz 3.91 KHz 7.81 KHz 15.63 KHz 5.14 KHz 10.28 KHz 20.56 KHz 12.22 KHz 24.41 KHz 48.83 KHz 16.28 KHz 32.55 KHz 65.1 KHz Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 < 48.8 KHz, < 97.7 KHz, < 195.3 KHz, Note 3 Note 3 Note 3 Mode 0: (Fclk / 25), Note 1 Mode 1: (Fclk / 19), Note 1 Mode 2: (Fclk / 8), Note 1 Mode 3: (Fclk / 6), Note 1 Mode 4: Timer 0 8-bit Overflow, 16-bit 8-bit Auto-Reload Mode 5: External input pin ECI (The max input frequency should be less than Fclk / 2) Note: 1. Max. PWM frequency = (Fclk / Divider) / 256, where Divider is 25, 19, 8, 6 for Mode 0, 1, 2, 3, respectively. 2. Max. PWM frequency = Timer 0 overflow rate / 256. 3. Max. PWM frequency = ECI frequency / 256. Table 47: Pulse Width Modulator Frequency 224 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY PCA Timer/Counter Mode Register (CMOD, 0xC2) Bit Name Reset Value Bit Name 0 ECF 3:1 CPS 6:4 Reserved 7 CIDL 7 CIDL 0 6 5 Reserved 00 4 3 2 CPS 00 1 0 ECF 0 Access Description PCA Enable Counter Overflow interrupt. R/W 1: Enables CF bit in CCON to generate an interrupt. 0: Disables the CF bit in CCON. PCA Count Pulse Select. CPS 000 001 010 011 100 111 Description Reference timing tick = operating system clock divided by 25. Reference timing tick = operating system clock divided by 19. Reference timing tick = operating system clock divided by 8. R/W Reference timing tick = operating system clock divided by 6. Reference timing tick = Timer 0 overflow rate. Reference timing tick = external clock at ECI pin (the max input frequency should be less than operating system clock divided by 2) For more details, please refer to Table 46. RO Counter Idle Control. R/W 1: Program the PCA Counter to be gated off during idle. 0: Program the PCA Counter to continue functioning during idle mode. PCA Timer/Counter Control Register (CCON, 0xC3) Bit Name Reset Value 7 CF 0 6 CR 0 5 Res. 0 4 CCF4 0 3 CCF3 0 2 CCF2 0 1 CCF1 0 0 CCF0 0 Bit Name Access Description 0 CCF0 CR PCA Module 0 interrupt flag. Set by hardware when a match or capture occurs. 1 CCF1 CR PCA Module 1 interrupt flag. Set by hardware when a match or capture occurs. 2 CCF2 CR PCA Module 2 interrupt flag. Set by hardware when a match or capture occurs. 3 CCF3 CR PCA Module 3 interrupt flag. Set by hardware when a match or capture occurs. 4 CCF4 CR PCA Module 4 interrupt flag. Set by hardware when a match or capture occurs. 5 Reserved RO 6 CR R/W PCA Counter Run control bit. Set by software to turn the PCA counter on. Must be cleared by software to turn the PCA counter off. 7 CF CR PCA Counter Overflow Flag. Set by hardware when the counter rolls over. CF flags an interrupt to INT3 if bit ECF in CMOD is set. The CCON register shown above is associated with all PCA timer functions. It contains the run control bit (CR) and overflow flags for the PCA timer (CF) and all modules (CCFx). To run the PCA the CR bit (CCON.6) must be set by software. Clearing the bit will turn off PCA. When the PCA counter overflows, the CF (CCON.7) will be set, and an interrupt will be generated if the ECF bit (CMOD.0) is set. The CF bit can only be cleared by software. Each module has its own timer overflow flag or capture flag (CCF0 for module 0, CCF4 for module 4, etc.). They are set when either a match or capture occurs. These flags can be cleared by software read. 225 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY PCA Timer/Counter (CL/CH) CL, 0xC4 Bit Name Reset Value 7 6 5 4 3 2 1 0 3 PTC[15:8] 00 2 1 0 PTC[7:0] 00 CH, 0xC5 Bit Name Reset Value Bit 15:0 7 6 5 4 Name Access PTC RO PCA Timer/Counter. Description PCA Compare/Capture Module Mode Register (CCAPMn) CCAPM0, 0xD1 Bit Name Reset Value 7 CEX0 0 6 ECOM0 0 5 CAPP0 0 4 CAPN0 0 3 MAT0 0 2 TOG0 0 1 PWM0 0 0 ECCF0 0 7 CEX1 0 6 ECOM1 0 5 CAPP1 0 4 CAPN1 0 3 MAT1 0 2 TOG1 0 1 PWM1 0 0 ECCF1 0 7 CEX2 0 6 ECOM2 0 5 CAPP2 0 4 CAPN2 0 3 MAT2 0 2 TOG2 0 1 PWM2 0 0 ECCF2 0 7 CEX3 0 6 ECOM3 0 5 CAPP3 0 4 CAPN3 0 3 MAT3 0 2 TOG3 0 1 PWM3 0 0 ECCF3 0 7 CEX4 0 6 ECOM4 0 5 CAPP4 0 4 CAPN4 0 3 MAT4 0 2 TOG4 0 1 PWM4 0 0 ECCF4 0 CCAPM1, 0xD2 Bit Name Reset Value CCAPM2, 0xD3 Bit Name Reset Value CCAPM3, 0xD4 Bit Name Reset Value CCAPM4, 0xD5 Bit Name Reset Value Bit Name Access Description 0 ECCFn R/W Enable CCF Interrupt. 1: Enable compare/capture flag CCF[4:0] in the CCON register to generate an interrupt. 0: Disable compare/capture flag CCF[4:0] in the CCON register to generate an interrupt. 1 PWMn R/W Pulse Width Modulation mode. 1: Enable CEX[n] pin to be used as a pulse width modulated output. 226 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 2 TOGn R/W 3 MATn R/W 4 CAPNn R/W 5 CAPPn R/W 6 ECOM n R/W 7 CEXn RO 0: Disable PWM mode. Toggle. 1: A match of the PCA counter with this module's compare/capture register causes the CEX[n] pin to toggle. 0: Disable toggle function. Match: Set ECOM[4:0] and MAT[4:0] to implement the software timer mode. 1: A match of the PCA counter with this module's compare/capture register causes the CCFn bit in CCON to be set, flagging an interrupt. 0: Disable software timer mode. Capture Negative. 1: Enable negative edge capture on CEX[4:0]. 0: Disable negative edge capture on CEX[4:0]. Capture Positive. 1: Enable positive edge capture on CEX[4:0]. 0: Disable positive edge capture on CEX[4:0]. Enable Comparator. 1: Enable the comparator function. 0: Disable the comparator function. Capture/Compare External In for PCA Module n. 1: After last trigger event the CEX[n] is 1. 0: After last trigger event the CEX[n] is 0. The ECCFn bit (CCAPMn bit 0 where n = 0, 1, 2, 3, or 4 depending on module) will enable the CCFn flag in the CCON register to generate an interrupt when a match or compare occurs. PWM bit (CCAPMn.1) enables the pulse width modulation mode. The MATn bit (CCAPMn.3) when set will cause the CCFn bit in the CCON register to be set when there is a match between the PCA counter and the module's capture/compare registers. Additionally, the TOG bit (CCAPMn.2) when set, causes the CEX[n] output pin associated with that module to toggle when there is a match between the PCA counter and the module's capture/compare registers. The CAPNn bit (CCAPMn.4) and CAPPn (CCAPMn.5) determine whether the capture input will be active on a positive edge or negative edge. The CAPNn bit enables a capture at the negative edge, and the CAPPn bit enables a capture at the positive edge. When both bits are set, both edges will be enabled and a capture will occur for either transition to measure pulse width. The ECOMn bit (CCAPMn.6) when set enables the comparator function. CEXn bit (CCAPMn.7) shows after last trigger event the CEX[n] value in capture mode to determine whether it's positive or negative edge. Table 48 and Table 49 show the CCAPMn settings for the various PCA functions. Module Mode ECOMn CAPP CAPN MATn TOGn PWMn ECCF n n n 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 No Operation 16-bit capture on positive-edge trigger at CEX[4:0] 16-bit capture on negative-edge trigger at CEX[4:0] 16-bit capture on positive/negative-edge trigger at CEX[4:0] Compare: software timer 1 0 0 1 Compare: high-speed output 1 0 0 1 Compare: 8-bit PWM 1 0 0 0 Note: n = 0, 1, 2, 3, 4 Table 48: PCA Module Modes Without Interrupt Enabled 0 1 0 227 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights 0 0 1 0 0 0 AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Module Mode ECOMn CAPP CAPN MATn TOGn PWMn ECCF n n n 0 1 0 0 0 0 1 0 0 1 0 0 0 1 0 1 1 0 0 0 1 16-bit capture on positive-edge trigger at CEX[4:0] 16-bit capture on negative-edge trigger at CEX[4:0] 16-bit capture on positive/negative-edge trigger at CEX[4:0] Compare: software timer 1 0 0 1 Compare: high-speed output 1 0 0 1 Compare: 8-bit PWM 1 0 0 0 Note: 1. n = 0, 1, 2, 3, 4 2. No PCA interrupt is needed to generate the PWM. Table 49: PCA Module Modes With Interrupt Enabled 0 1 0 0 0 1 1 1 X PCA Module n Compare/Capture Registers (CCAPnL/CCAPnH) There are two additional registers associated with each of the PCA modules: CCAPnH and CCAPnL. They are registers that hold the 16-bit count value when a capture occurs or a comparison occurs. When a module is used in PWM mode, these registers are used to control the duty cycle of the output. CCAP0L, 0xB1 Bit Name Reset Value 7 6 5 4 3 CCAP0[7:0] 00 2 1 0 7 6 5 4 3 CCAP0[15:8] 00 2 1 0 7 6 5 4 3 CCAP1[7:0] 00 2 1 0 7 6 5 4 3 CCAP1[15:8] 00 2 1 0 CCAP0H, 0xB9 Bit Name Reset Value CCAP1L, 0xB2 Bit Name Reset Value CCAP1H, 0xBA Bit Name Reset Value 228 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY CCAP2L, 0xB3 Bit Name Reset Value 7 6 5 4 3 CCAP2[7:0] 00 2 1 0 7 6 5 4 3 CCAP2[15:8] 00 2 1 0 7 6 5 4 3 CCAP3[7:0] 00 2 1 0 7 6 5 4 3 CCAP3[15:8] 00 2 1 0 7 6 5 4 3 CCAP4[7:0] 00 2 1 0 7 6 5 4 3 CCAP4[15:8] 00 2 1 0 CCAP2H, 0xBB Bit Name Reset Value CCAP3L, 0xB4 Bit Name Reset Value CCAP3H, 0xBC Bit Name Reset Value CCAP4L, 0xB5 Bit Name Reset Value CCAP4H, 0xBD Bit Name Reset Value Bit 15:0 Name CCAPn Access Description RO PCA Module n Compare/Capture Registers 229 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 4.18 I2C Controller The I2C controller of AX11015 supports Standard-mode (100K bps) and Fast-mode (400K bps), but not High-speed mode (3.4M bps) of the standard I2C bus spec. As shown in Figure 132, the I2C controller consists of an I2C master controller to support communication to external I2C devices, an I2C slave controller to support communication to external micro-controller with I2C master, and an I2C boot loader to support communication to external I2C EEPROM being used for storing chip configuration data. The I2C master controller is compatible with I2C bus protocol. It provides eight registers to fully control and monitor I2C bus transaction, and it has separate receive and transmit registers to hold data for transactions between AX11015 and the external I2C devices. The I2C master controller also provides arbitration for multi-master operation scenario and reports the arbitration status. Also, the I2C master controller accepts the SCL being extended low by the slow I2C slave devices as additional wait state indication during data or acknowledge cycles. The I2C clock frequency is software programmable. The I2C slave controller allows an external micro-controller with I2C master to communicate with AX11015. It provides an I2C device ID register to allow flexible assignment of AX11015 with any I2C device address for either 7-bit or 10-bit address mode, and can automatically filter I2C bus transactions not belonging to AX11015 in hardware. The I2C slave controller can extend the SCL line low when it needs additional wait state to respond to the external I2C master's bus transaction. The I2C slave controller supports 6 flexible command instructions for the external micro-controller to access the internal registers and memory resources of AX11015. The I2C boot loader is used to load chip configuration data from external I2C EEPROM. It is activated after hardware reset (either power-on-reset or RST_N input) or via the software reload command (via I2CCTR register). The detailed memory map of I2C EEPROM is described in section 3.1. The use of external I2C EEPROM is optional, when not used, the I2C_BOOT_DIS pin should be pulled up during chip hardware reset, in that case, the reset value listed in I2C EEPROM memory map shall be used by this chip by default. I2C Boot Loader Weak internal pull-up SCL SFR Bus SFR registers I2C Master Controller Weak internal pull-up SDA I2C Slave Controller Figure 132: I2C Controller Block Diagram 230 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 4.18.1 I2C Controller SFR Register Map Address Name Description 0x96 I2CCIR I2C Command Index Register is used to indicate the address of I2C controller register. 0x97 I2CDR I2C Data Register is used to read data from or write data to the specified I2C controller register. Table 50: I2C Controller SFR Register Map I2C Command Index Register (I2CCIR, 0x96) Bit Name Reset Value 7 6 5 4 3 2 1 0 I2CCIR 0x00 Bit Name Access Description 7:0 I2CCIR WO Indicate which of the I2C controller register as listed in Table 51 is to be accessed. I2C Data Register (I2CDR, 0x97) Bit Name Reset Value Bit Name 7:0 I2CDR 7 6 5 4 3 2 1 0 I2CDR 0x00 Access Description R/W Data Register is used to write data to or read data from the I2C controller registers. I2C Controller Register Indirect Access Method Software shall use indirect access method through I2CCIR and I2CDR registers to do read and write access to the I2C controller registers as listed in Table 51 below. Read a register from I2C controller: Step 1. Write I2CCIR: Software indicates the I2C controller register address to be accessed as the data and write it to the SFR register I2CCIR. Step 2. Read I2CDR: Software then read SFR register I2CDR. The data read from I2CDR is the I2C controller register data indicated in step 1. Keep reading from I2CDR if the I2C controller registers have more than one byte, in that case, the first byte being read back is LSB byte. Write a register to I2C controller: Step 1. Write I2CDR: Software writes the data you want to write into I2C controller registers to the SFR register I2CDR. Keep writing to I2CDR if the I2C controller registers have more than one byte, in that case, the first byte being written should be LSB byte. Step 2. Write I2CCIR: After writing I2C controller register data to I2CDR, software then indicates the target I2C controller register address as data and write it to I2CCIR. Note: While software is reading or writing I2C controller registers during a sequence of SFR accesses, software can abort that process by writing I2CCIR with 0xFF. 231 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY I2C Controller Register Map Address 0x00 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x0A Name I2CCPR I2CTR I2CRR I2CCTR I2CCR I2CMSR Reserved I2CSDA I2CSSR Description I2C Clock Pre-scale Register. I2C Transmit Register is used to transmit data to device. I2C Receive Register is used to hold data that receive from device. I2C Control Register is used to configure operation mode. I2C Command Register is used to configure operation mode. I2C Master Status Register is used to report status of the I2C master mode. I2C Slave Device Address Register I2C Slave Status Register is used to report status of the I2C slave mode. Table 51: I2C Controller Register Map I2C Clock Pre-scale Register (I2CCPR, 0x00) 7 Bit 6 5 4 Name Reset Value Bit Name 3 2 1 0 PRER0 PRER1 0xFFFF Access Description This register is used to pre-scale the SCL clock line. I2C SCL clock frequency = Operating system clock frequency / (5* (PRER + 1)) 7:0 PRER0 15:8 PRER1 Operating System Clock 25 Mhz 50 Mhz 75 Mhz 100 Mhz 25 Mhz 50 Mhz 75 Mhz 100 Mhz R/W PRER 0x00_0c 0x00_18 0x00_25 0x00_31 0x00_3a 0x00_76 0x00_B1 0x00_C7 Fast mode Standard mode I2C Transmit Register (I2CTR, 0x02) Bit Name Reset Value Bit Name 0 RW_TXD 7:1 TXD 7 6 5 4 TXD 000_0000 3 2 1 Access Description In case of a slave address transfer this bit represents the RW bit, where 1: Reading from slave. R/W 0: Writing to slave. In case of a data transfer this bit represents the data's LSB bit. R/W Next byte to transmit on I2C bus in either master or slave mode. 232 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights 0 RW_TXD 0 AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY I2C Receive Register (I2CRR, 0x03) 7 Bit Name Reset Value Bit 7:0 Name RXD 6 5 4 3 2 1 0 1 EN 0 0 MIE 0 RXD 0x00 Access Description RO Last byte received from I2C bus in either master or slave mode. I2C Control Register (I2CCTR, 0x04) Bit Name Reset Value Bit 0 1 2 3 4 5 6 7 Name 7 MSS 0 6 SIE 0 5 Reserved 0 4 RLE 0 3 TE 0 2 SD 0 Access Description I2C Master mode Interrupt Enable. This bit is only valid when operating in I2C master mode. MIE R/W 1: Interrupt enable. 0: Interrupt disable. I2C controller Enable. EN R/W 1: Enable I2C controller. 0: Disable I2C controller. I2C Speed in slave mode. This bit is only valid when operating in I2C slave mode. SD R/W 1: I2C slave mode operating in STANDARD mode. 0: I2C slave mode operating in FAST mode. Ten address Enable. This bit is only valid when operating in I2C slave mode. TE R/W 1: 10-bit address enable. 0: 7-bit address enable. Re-load I2C Configuration EEPROM. 1: To reload the external I2C EEPROM's content. The I2C Boot Loader will RLE R/W1 automatically re-load the content of I2C EEPROM into the chip. This bit is cleared by hardware. The status of reload progress is reported in I2CMSR. 0: Normal operation mode. Reserved I2C Slave mode Interrupt Enable. This bit is only valid when operating in I2C slave mode. SIE R/W 1: Interrupt enable. 0: Interrupt disable. I2C Master/Slave mode Select. MSS R/W 1: Set I2C controller to operate as I2C master. 0: Set I2C controller to operate as I2C slave. 233 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY I2C Command Register (I2CCR, 0x05) Bit Name Reset Value Bit 0 1 2 3 4 5 6 7 Name 7 STA 0 6 STO 0 5 RD 0 4 WR 0 3 MG 0 2 Reserved 0 1 SG 0 0 RLS 0 Access Description Release the SCL pin. This bit is only valid when operating in I2C slave mode. When the external I2C master controller is reading data from this chip, after each byte being transferred, normally the SCL line will be held low by the I2C slave controller of this chip so that the software can prepare for the next 8-bit data byte in I2CTR. This forces RLS R/W1 the external I2C master controller to wait for this chip. However, in the case of finishing the transfer of the last bit of the last byte during the external I2C master read command, software shall write 1 to this bit to release SCL pin of this chip to allow the STOP condition on I2C bus. Slave Go. This bit is only valid when operating in I2C slave mode. SG R/W1 Writing 1 to this bit starts the transfer in I2C slave mode. This bit remains set during the transfer and is automatically cleared after the transfer finished. Reserved Master Go. This bit is only valid when operating in I2C master mode. MG R/W1 Writing 1 to this bit starts the transfer in I2C master mode. This bit remains set during the transfer and is automatically cleared after the transfer finished. When operating in I2C master mode, setting `1' to request to send the 8-bit data in I2CTR WR R/W1 to the slave. This bit is only valid when operating in I2C master mode. When operating in I2C master mode, setting `1' to request to receive data from slave. The received data is stored in I2CRR. Setting RD bit and STO bit at the same time will cause RD R/W1 the transfer to end with a NACK condition to the addressed slave. Setting RD bit without setting STO bit will cause the transfer to end with an ACK condition to the addressed slave. This bit is only valid when operating in I2C master mode. When operating in I2C master mode, setting `1' to request to generate the STOP condition STO R/W1 on I2C bus. This bit is only valid when operating in I2C master mode. When operating in I2C master mode, setting `1' to request to generate the START or STA R/W1 ReSTART condition on I2C bus. This bit is only valid when operating in I2C master mode. I2C Master Status Register (I2CMSR, 0x06) Bit Name Reset Value 7 ACK 0 Bit Name Access 0 IF CR 1 TIP RO 2 Reserved - 3 RLES RO 4 BLD RO 6 BUSY 0 5 AL 0 4 BLD 1 3 RLES 0 2 Reserved 0 1 TIP 0 0 IF 0 Description Interrupt Flag. This bit is set when following events occur, z One byte transfer has been completed z Arbitration is lost This will cause an interrupt request on INT4 if the MIE bit (I2CCTR.0) is set. Transfer in progress. 1: When transferring data is in progress. 0: When transfer is completed. Reload EEPROM Status. 1: After software sets the RLE bit (I2CCTR.4) to `1', the I2C Boot Loader will reload the I2C EEPROM content and keeps this bit to `1' until the reload is completed. 0: The chip hardware will clear this bit after it completes the reload process. Boot Loader Done. 1: I2C Boot Loader has done with loading. 234 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 5 AL CR 6 BUSY RO 7 ACK CR 0: I2C Boot Loader is still loading configuration data from I2C Configuration EEPROM. Arbitration Lost. This bit is set when the I2C master lose arbitration during multi-master scenario. Arbitration is lost when: z A STOP signal is detected, but non requested z The master drives SDA high, but SDA is low. I2C bus Busy. 1: After the START signal is detected on I2C bus, the I2C bus is busy. 0: After the STOP signal is detected on the I2C bus, the I2C bus is not busy. This flag represents the Acknowledgement received from I2C slave after a transmit transfer (8-bit data being sent to the external I2C device). This bit is only meaningful after the TIP bit changes from `1' to `0' for a transfer. 1: NACK is received from the slave. 0: ACK is received from the slave. I2C Slave Device Address (I2CSDA, 0x08) 7 Bit Name 6 5 4 Reset Value Bit Name 7:0 9:8 DA0 DA1 15:10 Reserved 3 2 1 0 DA0 DA1 0x00 Access Description Device Address of this chip operating in I2C slave mode. The {DA1, DA0} is the I2C device address of this chip operating in I2C slave mode. If R/W the device is configured as 7-bits address mode then only bit [6:0] are valid. The 6th bit is MSB. If the device is configured as 10-bits address mode then bit [9:0] are valid. The 9th bit is MSB. - I2C Slave Status Register (I2CSSR, 0x0a) Bit Name Reset Value 7 ERR 0 Bit Name Access 0 STC CR 1 NACK CR 2 WR RO 3 RD RO 4 RE-STAR T CR 5 START CR 6 STOP CR 7 ERR CR 6 STOP 0 5 START 0 4 RE-START 0 3 RD 0 2 WR 0 1 NACK 0 0 STC 0 Description Slave Transfer Complete. Reading `1' indicates that the external I2C master has just completed one transfer on I2C bus. NACK condition. Reading `1' indicates that the external I2C master returns a NACK condition during current transfer. Write command. Reading `1' indicates that the external I2C master needs to transmit data to this chip. The data is held in I2CRR register. Read command. Reading `1' indicates that the external I2C master needs to receive data from this chip. After knowing this, the software shall put the requested data in I2CTR register. ReSTART condition detected. Reading `1' indicates that the ReSTART condition is detected on the I2C bus. START condition detected. Reading `1' indicates that the SART condition is detected on the I2C bus. STOP condition detected. Reading `1' indicates that the STOP condition is detected on the I2C bus. Error. Reading `1' indicates that the I2C slave controller of this chip has detected an error on SCL and aborted the current transfer. 235 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Example Programming Procedure in I2C Master Mode Example 1: Write 1 byte of data = 0xAC to an external slave device with slave address = 0x51 (101_0001). 1. 2. 3. 4. Write 0xA2 (slave address) to I2CTR. Set STA, WR, and MG bits to I2CCR. Read TIP and ACK bits from I2CMSR until both read as `0' (polling mode or wait for interrupt in interrupt mode). Write 0xAC to I2CTR. Set STO, WR, and MG bits to I2CCR. Read TIP and ACK bits from I2CMSR until both read as `0'. Firs t com m and s equence Second com m and s equence SCL SDA S Wr ack ack P I2CCR STA = 0 STO = 1 WR = 1 RD = 0 MG = 1 I2CCR STA = 1 STO = 0 WR = 1 RD = 0 MG = 1 Figure 133: Transmitting Data to an I2C Slave Device Example 2: Read a byte of data from location 0x20 of an I2C memory device with slave address = 0x4E (100_1110) 1. 2. 3. 4. Write 0x9C (slave address) to I2CTR. Set STA, WR, and MG bits to I2CCR. Read TIP and ACK bits from I2CMSR until both read as `0'. Write 0x20 to I2CTR. Set WR and MG bits to I2CCR. Read TIP and ACK bits from I2CMSR until both read as `0'. Write 0x9D (slave address) to I2CTR. Set STA, WR, and MG bits to I2CCR. Read TIP and ACK bits from I2CMSR until both read as `0'. Set RD, STO and MG bits to I2CCR. Read TIP and IF bits from I2CMSR until both read as `0'. Firs t comm and s equence Second com mand s equence SCL SDA S Wr ack ack I2CCR STA = 0 STO = 0 WR = 1 RD = 0 MG = 1 I2CCR STA = 1 STO = 0 WR = 1 RD = 0 MG = 1 Third com mand s equence Fourthcomm ands equence SCL SDA R I2CCR STA = 1 STO = 0 WR = 1 RD = 0 MG = 1 R ack D7 D6 D5 D4 D3 D2 D1 D0 I2CCR STA = 0 STO = 1 WR = 0 RD = 1 MG = 1 Figure 134: I2C Read Data 236 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights N P AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 4.18.2 I2C Slave Mode Function Description The I2C slave controller of this chip provides 6 reference command instructions, namely, SW_SFR, SR_SFR, IW_SFR, IR_SFR, BWDM, and BRDM commands, for the external I2C master to communicate with this chip. The external I2C master may use these commands to read or write the SFR registers or xDATA memory of this chip. Except for the I2C device address transfer that the I2C slave controller of this chip will be parsing, the remaining byte transfers are pretty much parsing by the software of AX11015, therefore, these commands are allowed to make changes to meet user's applications. The SW_SFR, SR_SFR, IW_SFR, and IR_SFR are single read or write commands, while BWDM and BRDM are burst read or write commands in one transfer with address automatically incremented. Comman d Name Op-code Operation Description Single Write SFR register. 1010 0xxx This command requests to write various bytes of data to the specified SFR register in (0xA0~0xA7) this chip. The xxx indicates the number of bytes to be written to target register. For example, xxx = 000 for 1 byte, and xxx = 111 for 8 bytes. Single Read SFR register. 0010 0xxx This command requests to read various bytes of data from the specified SFR register SR_SFR (0x20~0x27) from this chip. The xxx indicates the number of bytes to be read from the target register. For example xxx = 000 for 1 byte, and xxx = 111 for 8 bytes. Indirect Write SFR register. SW_SFR This command requests to indirectly write various bytes of data through the specified command index register in SFR to the given indirect register in this chip. The xxxx 1011 xxxx indicates the number of bytes to be written to target indirect register. For example, IW_SFR (0xB0~0xBF) xxxx = 0000 for 1 byte, and xxxx = 1111 for 16 bytes. Typical indirect access registers uses following SFR register-pair to access through: DCIR/DDR, MCIR/MDR, EPCR/EPDR, TCIR/TDR, SPICIR/SPIDR, OWCIR/OWDR, etc. Indirect Read SFR register. IR_SFR This command requests to indirectly read various bytes of data through the specified command index register in SFR from the given indirect register in this chip. The xxxx 0011 xxxx indicates the number of bytes to be read from the target indirect register. For example, (0x30~0x3F) xxxx = 0000 for 1 byte, and xxxx = 1111 for 16 bytes. BWDM 1100 0000 BRDM 0100 0000 Typical indirect access registers uses following SFR register-pair to access through: DCIR/DDR, MCIR/MDR, EPCR/EPDR, TCIR/TDR, SPICIR/SPIDR, OWCIR/OWDR, etc. Burst write data to xDATA memory of this chip. The command requests to do burst or single write to xDATA memory. See Note 1. Burst read data from xDATA memory of this chip. This command requests to do burst or single read from the xDATA memory. See Note 1. Note: 1. The memory burst write and memory burst read commands have no pre-defined limit on the number of burst bytes, user can define your own burst command in the lower nibble of the Op-Code like in first 4 commands to assist software decoding and handshaking between the external I2C master controller and internal software of AX11015. Table 52: Reference Command Instructions in I2C Slave Mode 237 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Reference Transfer Format in I2C Slave Mode SW_SFR S Device Addr W A 1010 0000 Instruction S Device Addr W A 1010 0001 Instruction A SFR Addr A Data A P A SFR Addr A Data0 A Data1 A P SR_SFR S Device Addr S Device Addr W A 0010 0000 Instruction A SFR Addr A RS Device Addr R A Data W A 0010 0001 Instruction A SFR Addr A RS Device Addr R A Data0 NA P A Data1 NA P IW_SFR S Device Addr S Device Addr W A 1011 0000 Instruction A Cmd Idx Reg. A Ind Reg. A W A 1011 0001 Instruction A Cmd Idx Reg. A Ind Reg. A A P Data0 Data0 A Data1 A P IR_SFR S Device Addr W A 0011 xxxx Instruction (cont) A Data0 A Cmd Idx Reg. A DataN NA Ind Reg. A RSDevice Addr R A (next) P Where DataN = the (xxxx+1)th byte. BWDM 1100 0000 Instruction S Device Addr W A (cont) DataN A P S Device Addr W A 0100 0000 Instruction A Mem Addr B0 A Mem Addr B2 A Data0 A (next) A RSDevice Addr R A (next) BRDM (cont) Data0 A A Mem Addr B0 DataN A Mem Addr B2 NA P 238 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 4.19 1-Wire Controller The 1-Wire controller of AX11015 is a master-mode controller that controls the communication with multiple external 1-Wire devices. The data transmissions on 1-Wire bus are bit-asynchronous and half-duplex mode only. The 1-Wire controller provides some registers for software to easily perform reading/writing data from/to the 1-Wire devices without having to deal with time-consuming bus timing and control sequences on 1-Wire bus. It supports Standard mode, Standard - Long line mode, and Overdrive mode to work with various 1-Wire devices. For detailed 1-Wire interface timing, please refer to section 5.4.5. The 1-Wire controller also supports Search ROM Accelerator, which relieves CPU from any single bit operations on the 1-Wire Bus. As shown in figure below, it also provides a strong pull-up control pin, STPZ, for the case of large loading or long line conditions. The DQ is an open-drain pin, which needs an external pulled-up resistor or a strong pull-up through a PMOS transistor. SFR registers SFR Bus STPZ 1-Wire Master Controller DQ Figure 135: 1-Wire Controller Block Diagram 4.19.1 1-Wire Controller SFR Register Map Address Name Description 0xD6 OWCIR 1-Wire Command Index Register is used to indicate the address of 1-Wire controller register. 0xD7 OWDR 1-Wire Data Register is used to read data from or write data to the specified 1-Wire controller register. Table 53: 1-Wire Controller SFR Register Map 1-Wire Command Index Register (OWCIR, 0xD6) Bit Name Reset Value Bit 7:0 7 6 5 4 3 2 1 0 OWCIR 0x00 Name Access Description OWCIR WO Indicate which of the 1-Wire controller register as listed in Table 54 is to be accessed. 1-Wire Data Register (OWDR, 0xD7) Bit Name Reset Value 7 6 5 4 3 2 1 0 OWDR 0x00 Bit Name Access Description 7:0 OWDR R/W Data Register is used to write data to or read data from the 1-Wire controller registers. 239 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 1-Wire Controller Register Indirect Access Method Software shall use indirect access method through OWCIR and OWDR registers to do read and write access to the 1-Wire controller registers as listed in Table 54 below. Read a register from 1-Wire controller: Step 1. Write OWCIR: Software indicates the 1-Wire controller register address to be accessed as the data and write it to the SFR register OWCIR. Step 2. Read OWDR: Software then read SFR register OWDR. The data read from OWDR is the 1-Wire controller register data indicated in step 1. Write a register to 1-Wire controller: Step 1. Write OWDR: Software writes the data you want to write into 1-Wire controller registers to the SFR register OWDR. Step 2. Write OWCIR: After writing 1-Wire controller register data to OWDR, software then indicates the target 1-Wire controller register address as data and write it to OWCIR. Note: While software is reading or writing 1-Wire controller registers during a sequence of SFR accesses, software can abort that process by writing OWCIR with 0xFF. 1-Wire Controller Register Map Address 0x00 0x01 Name OWCR OWTRR 0x02 0x03 0x04 0x05 OWISR OWIER OWCTR OWCD Description 1-Wire Command Register is used to configure 1-Wire operation mode. 1-Wire Transmit/Receive buffer Register is used to hold data to be transmitted or data being received from 1-Wire devices. 1-Wire Interrupt Status Register. 1-Wire Interrupt Enable Register. 1-Wire Control Register. 1-Wire Clock Divider Register. Table 54: 1-Wire Controller Register Map 1-Wire Command Register (OWCR, 0x00) Bit Name Reset Value Bit Name 0 1WR 1 SRA 2 FOW 7 6 5 Reserved 0_0000 4 3 2 FOW 0 1 SRA 0 Access 0 1WR 0 Description 1-Wire Reset. 1: If this bit is set a reset will be generated on the 1-Wire bus. Setting this bit automatically clears the SRA bit. 0: This bit will be automatically cleared as soon as the 1-Wire reset completes. The W1 1-Wire Master will set the Presence Detect interrupt flag (PD) when the reset is complete and sufficient time for a presence detect to occur has passed. The result of the presence detect will be reported in the PDR bit (OWISR.1). If a presence detect pulse was received PDR bit will be cleared, otherwise it will be set. Search ROM Accelerator. 1: When this bit is set, the 1-Wire Master will switch to Search ROM Accelerator mode R/W 0: When this bit is set to 0, the master will function in its normal mode. This bit is cleared to 0 on a power-up or master reset. Force One Wire. 1: This bit can be used to bypass 1-Wire Master operations and drive the bus directly if R/W needed. Setting this bit high will drive the bus low until it is cleared or the 1-Wire Master reset. While the 1-Wire bus is held low no other 1-Wire Master operations will function. By controlling the length of time this bit is set and the point when the 240 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY line is sampled, any 1-Wire communication can be generated by the software. To prevent accidental writes to the bus, the EN_FOW bit (OWCTR.2) must be set to a 1 before this bit will function. 0: software is not forcing the 1-Wire bus. This bit is cleared to a 0 on power-up or master reset. 7:3 Reserved - 1-Wire Transmit/Receive buffer Register (OWTRR, 0x01) 7 Bit Name Reset Value 6 5 4 3 2 1 0 DATA 0x00 Bit Name Access Description 7:0 DATA R/W When the BIT_CTL bit (OWCTR.5) is 0, this holds the 8-bit data to be sent to or being received from the 1-Wire device. The LSB bit (bit 0) is serially shifted out or received in first. When the BIT_CTL bit is 1 (in "Bit Banging" mode), the LSB bit holds the 1-bit data to be sent to or being received from the 1-Wire device. 1-Wire Interrupt Status Register (OWISR, 0x02) 7 Bit OW_LOW Name 0 Reset Value Bit Name Access 0 PD CR 1 PDR RO 2 TBE RO 3 TSRE RO 4 RBF RO 6 OW_SHORT 0 5 RSRF 0 4 RBF 0 3 TSRE 0 2 TBE 0 1 PDR 0 0 PD 0 Description Presence Detect. 1: After a 1-Wire Reset has been issued, this flag will be set to 1 after the appropriate amount of time for a presence detect pulse to have occurred. 0: This flag will be 0 when the master has not issued a 1-Wire Reset since the previous read of the OWISR. Presence Detect Result. When a presence detect interrupt occurs, this bit will reflect the result of the presence detect read 1: if no part was found. 0: if a slave was found. Transmit Buffer Empty. 1: This flag will be set to 1 when there is nothing in the Transmit Buffer and it is ready to receive the next byte of data. 0: When it is 0, it indicates that the Transmit Buffer is waiting for the Transmit Shift Register to finish sending its current data before updating it. This bit is cleared when data is written to the Transmit Buffer. Transmit Shift Register Empty. 1: This flag will be set to 1 when there is nothing in the Transmit Shift Register and it is ready to receive the next byte of data to be transmitted from the Transmit Buffer. 0: When this bit is 0, it indicates that the Transmit Shift Register is busy sending out data. This bit is cleared when data is transferred from the Transmit Buffer to the Transmit Shift Register. Receive Buffer Full. 1: This flag will be set to 1 when there is a byte of data waiting to be read in the Receive Buffer. 0: When this bit is 0, it indicates that the Receive Buffer has no new data to be read. This bit will be cleared when the byte is read from the Receive Buffer. Following a read of the OWISR, while Enable Receive Buffer Full Interrupt (ERBF) is set to 1, if the ERBF is not cleared and the value is not read from the Receive Buffer, the 241 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 5 RSRF RO 6 OW_SH ORT CR 7 OW_LO W CR interrupt will fire again. Receive Shift Register Full. 1: This flag will be set to 1 when there is a byte of data waiting in the Receive Shift Register. 0: When this bit is 0, it indicates that the Receive Shift Register is either empty or currently receiving data. This bit will be cleared by the hardware when data in the Receive Shift Register is transferred to the Receive Buffer. One Wire Short. 1: This flag will be set to a 1 when the 1-Wire line was low before the master was able to send out the beginning of a reset or a time slot. 0: When this flag is 0, it indicates that the 1-Wire line was high as expected prior to all resets and time slots. One Wire Low. 1: This flag will be set to 1 when the 1-Wire line is low while the master is in idle signaling that a slave device has issued a presence pulse on the 1-Wire (DQ) line. 1-Wire Interrupt Enable Register (OWIER, 0x03) Bit Name Reset Value Bit Name 0 EPD 1 Reserved 2 ETBE 3 ETSRE 4 ERBF 5 ERSRF 6 EOWSH 7 EOWL 7 EOWL 0 6 EOWSH 0 5 ERSRF 0 4 ERBF 0 3 ETSRE 0 2 ETBE 0 1 Reserved 0 Access 0 EPD 0 Description Enable Presence Detect Interrupt. 1: Setting this bit to a 1 enables the Presence Detect Interrupt. If set, interrupt will be R/W asserted on INT4 when the PD flag is set. 0: Clearing this bit disables PD as an active interrupt source. Enable Transmit Buffer Empty Interrupt. 1: Setting this bit to a 1 enables the Transmit Buffer Empty Interrupt. If set, interrupt will R/W be asserted on INT4 when the TBE flag is set. 0: Clearing this bit disables TBE as an active interrupt source. Enable Transmit Shift Register Empty Interrupt. 1: Setting this bit to a 1 enables the Transmit Shift Register Empty Interrupt. If set, R/W interrupt will be asserted on INT4 when the TSRE flag is set. 0: Clearing this bit disables TSRE as an active interrupt source. Enable Receive Buffer Full Interrupt. 1: Setting this bit to a 1 enables the Receive Buffer Full Interrupt. If set, interrupt will be R/W asserted on INT4 when the RBF flag is set. 0: Clearing this bit disables RBF as an active interrupt source. Enable Receive Shift Register Full Interrupt. 1: Setting this bit to a 1 enables the Receive Shift Register Full Interrupt. If set, interrupt R/W will be asserted on INT4 when the RSRF flag is set. 0: Clearing this bit disables RSRF as an active interrupt source. Enable One Wire Short Interrupt. 1: Setting this bit to a 1 enables the One Wire Short Interrupt. If set, interrupt will be R/W asserted on INT4 when the OW_SHORT flag is set. 0: Clearing this bit disables OW_SHORT as an active interrupt source. Enable One Wire Low Interrupt. 1: Setting this bit to a 1 enables the One Wire Low Interrupt. If set, interrupt will be R/W asserted on INT4 when the OW_LOW flag is set. 0: Clearing this bit disables OW_LOW as an active interrupt source. 242 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 1-Wire Control Register (OWCTR, 0x04) Bit Name Reset Value 7 Reserved 0 Bit Name Access 0 LLM R/W 1 PPM R/W 2 EN_FOW R/W 3 STPEN R/W 4 STP_SPL Y R/W 5 BIT_CTL R/W 6 OD R/W 7 Reserved - 6 OD 0 5 4 BIT_CTL STP_SPLY 0 0 3 STPEN 0 2 EN_FOW 0 1 PPM 0 0 LLM 0 Description Long Line Mode. 1: Setting this bit to a 1 will enable Long Line Mode timings on the 1-Wire line during standard mode communications. This mode effectively moves the write one release, the data sampling, and the time slot recovery times out to roughly 8us, 22us, and 14us respectively. This provides a less strict environment for long line transmissions. 0: Clearing this bit to 0 leaves the write one release, the data sampling, and the time slot recovery times at roughly 5us, 15us, and 7us respectively. Presence Pulse Masking Mode. 1: Setting this bit to a 1 will enable Presence Pulse Masking Mode. This mode causes the master to initiate the falling edge of a presence pulse during a 1-Wire Reset before the fastest slave would initiate one. This enables the master to prevent the larger amount of ringing caused by the slave devices when initiating a low on the DQ line. If the PPM bit is set, the PDR result bit in the Interrupt Register will always be set to a 0 showing that a slave device was on the line even if there were none. 0: Clearing this bit to a 0 disables the Presence Pulse Masking Mode. This mode only support standard mode. Enable Force One Wire. 1: Setting this bit to a 1 will enable the functionality of the Force One Wire (FOW) bit (OWCR .2). 0: Clearing this bit will disable the functionality of the FOW bit. Strong Pull-up Enable. 1: Setting this bit to a 1 enables the strong pull-up output enable (STPZ) pin's functionality which allows this output pin to enable an external strong pull-up any time the master is not pulling the line low or waiting to read a value from a slave device. This functionality is used for meeting the recovery time requirement in Overdrive mode and long-line standard communications. 0: Clearing this bit to a 0 will disable the STPZ output pin. Strong Pull-up Supply. 1: Setting this bit to a 1 while STPEN is also set to a 1 will enable the STPZ output while the master is in an IDLE state. This will provide a stiff supply to devices requiring high current during operations. 0: Clearing this bit to a 0 disables the STPZ output while the master is in an IDLE state. The STP_SPLY bit is a don't-care if STPEN is set to a 0. Bit Control. 1: Setting this bit to a 1 will place the master into its "Bit Banging" mode of operation. In this mode, only the least significant bit of the Transmit/Receive register would be sent/received before enabling the interrupt flags that signal the end of the transmission. 0: Clearing this bit to 0 leaves the master operating in full byte boundaries. Overdrive. 1: Setting this bit to a 1 will place the master into Overdrive mode that effectively changes the master's 1-Wire timings to match those outlined for Overdrive in the Book of iButton Standards. 0: Clearing this bit to a 0 leaves the master operating in Standard mode speed. 243 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 1-Wire Clock Divider Register (OWCD, 0x05) Bit Name Reset Value 7 CLK_EN 0 Bit 1:0 Name PRE Access R/W 4:2 DIV R/W 6:5 Reserved 7 6 5 Reserved 00 4 Operating System Clock Frequency (MHz) 25 50 100 3 DIV 000 2 1 PRE 00 Description Divider Ratio DIV[2:0] PRE[1:0] 24 48 96 011 100 101 01 01 01 - CLK_EN R/W 0 Clock Enable for 1-Wire controller and its bus timing control logic. 1: Enable 1-Wire controller and its bus timing control logic. 0: Disable 1-Wire controller and its bus timing control logic. 244 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 4.20 SPI Controller The serial peripheral interface (SPI) controller of AX11015 provides a full-duplex, synchronous serial communication interface (4 wires) to flexibly work with numerous peripheral devices or micro-controller with SPI. As shown in Figure 136 below, the SPI controller consists of a SPI master controller with 3 slave select pins, SS0, SS1, SS2, to connect up to 3 SPI devices, and a SPI slave controller to support communication with external micro-controller with SPI master. The SPI master controller supports 4 types of interface timing mode, namely, Mode 0, Mode 1, Mode 2, and Mode 3 to allow working with most SPI devices available. Please see Figure 137 for the timing diagram of these timing modes. It supports variable length of transfer word up to 32 bits per software command or even extended length of transfer word for a long burst transfer by keeping slave select pins active. It supports either MSB or LSB first data transfer, and the operating SPI clock, SCLK, is programmable by software and can be run up to 25 Mhz when operating system clock is at 100MHz. The SPI slave controller allows an external micro-controller with SPI master to communicate with AX11015. It supports 2 types of interface timing mode, namely, Mode 0 and Mode 3. In slave mode, only MSB first data transfer is supported and only the slave select pin, SS0, is used. The SPI slave controller supports 8 flexible command instructions for the external micro-controller to access the internal registers and memory resources of AX11015. It contains a 16-bytes FIFO to hold receive/transmit data on SPI interface and the SPI clock can be run up to 6 Mhz when operating system clock is at 100MHz. SS2 SS1 SS0 SPI Master Controller (4-bytes RX FIFO 4-bytes TX FIFO) SCLK MOSI SFR Bus SFR registers MISO SPI Slave Controller (16-bytes FIFO) Figure 136: SPI Controller Block Diagram 245 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Mode 0: CPHA (SPICR.1) = 0, CPOL (SPICR.2) = 0, LSB (SPICR.3) = 0, SPIMCR[CHAR_LEN] = 00111. SCLK MOSI MSB D6 D5 D4 D3 D2 D1 LSB MISO MSB D6 D5 D4 D3 D2 D1 LSB SS Bit sample time Note: SCLK pin needs external pull-down resistor and SSx pins need external pull-up resistor in Mode 0, SPI master mode. Mode 1: CPHA (SPICR.1) = 0, CPOL (SPICR.2) = 1, LSB (SPICR.3) = 0, SPIMCR [CHAR_LEN] = 00111. SCLK MOSI MSB D6 D5 D4 D3 D2 D1 LSB MISO MSB D6 D5 D4 D3 D2 D1 LSB SS Bit sample time Note: SCLK pin needs external pull-up resistor and SSx pins need external pull-up resistor in Mode 1, SPI master mode. Mode 2: CPHA (SPICR.1) = 1, CPOL (SPICR.2) = 0, LSB (SPICR.3) = 0, SPIMCR[CHAR_LEN] = 00111. SCLK MOSI MSB D6 D5 D4 D3 D2 D1 LSB MISO MSB D6 D5 D4 D3 D2 D1 LSB SS Bit sample time Note: SCLK pin needs external pull-down resistor and SSx pins need external pull-up resistor in Mode 2, SPI master mode. Mode 3: CPHA (SPICR.1) = 1, CPOL (SPICR.2) = 1, LSB (SPICR.3) = 0, SPIMCR[CHAR_LEN] = 00111. SCLK MOSI MSB D6 D5 D4 D3 D2 D1 LSB MISO MSB D6 D5 D4 D3 D2 D1 LSB SS Bit sample time Note: SCLK pin needs external pull-up resistor and SSx pins need external pull-up resistor in Mode 3, SPI master mode. Figure 137: SPI Timing Diagram 246 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 4.20.1 SPI SFR Register Map Address Name Description 0xCE SPICIR SPI Command Index Register is used to indicate the address of SPI controller register. 0xCF SPIDR SPI Data Register is used to read data from or write data to the specified SPI controller register. Table 55: SPI Controller SFR Register Map SPI Command Index Register (SPICIR, 0xCE) Bit Name Reset Value 7 6 5 4 3 2 1 0 SPICIR 0x00 Bit Name Access Description 7:0 SPICIR WO Indicate which of the SPI controller register as listed in Table 56 is to be accessed. SPI Data Register (SPIDR, 0xCF) Bit Name Reset Value 7 6 5 4 3 2 1 0 SPIDR 0x00 Bit Name Access Description 7:0 SPIDR R/W Data Register is used to write data to or read data from the SPI controller registers. SPI Controller Register Indirect Access Method Software shall use indirect access method through SPICIR and SPIDR registers to do read and write access to the SPI controller registers as listed in Table 56 below. Read a register from SPI controller: Step 1. Write SPICIR: Software indicates the SPI controller register address to be accessed as the data and write it to the SFR register SPICIR. Step 2. Read SPIDR: Software then read SFR register SPIDR. The data read from SPIDR is the SPI controller register data indicated in step 1. Keep reading from SPIDR if the SPI controller registers have more than one byte, in that case, the first byte being read back is LSB byte. Write a register to SPI controller: Step 1. Write SPIDR: Software writes the data you want to write into SPI controller registers to the SFR register SPIDR. Keep writing to SPIDR if the SPI controller registers have more than one byte, in that case, the first byte being written should be LSB byte. Step 2. Write SPICIR: After writing SPI controller register data to SPIDR, software then indicates the target SPI controller register address as data and write it to SPICIR. Note: While software is reading or writing SPI controller registers during a sequence of SFR accesses, software can abort that process by writing SPICIR with 0xFF. 247 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY SPI Controller Register Map Address 0x00 0x04 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 Name SPIRBR SPITBR SPICR SPIMCR SPIBRR SPISSR SPIISR SPIIER SPISCR Reserved SPISB Description SPI RX Buffer Register SPI TX Buffer Register SPI Control Register SPI Master Command Register SPI Baud Rate Register SPI Slave Select Register SPI Interrupt Status Register SPI Interrupt Enable Register SPI Slave Command Register SPI Slave Buffer Table 56: SPI Controller Register Map SPI RX Buffer Register (SPIRBR, 0x00) 7 Bit 6 5 4 Name Reset Value 3 SPIRBR0 SPIRBR1 SPIRBR2 SPIRBR3 0x0000_0000 2 1 0 Bit Name Access Description 7:0 SPIRBR0 When in SPI master mode, the SPIRBR registers hold the value of received data of the ... ... last executed transfer. Valid bits depend on the CHAR_LEN bits of SPIMCR register. 31:24 SPIRBR3 RO For example, if CHAR_LEN is less or equal to 0_0111, the value of SPIRBR1, SPIRBR2 and SPIRBR3 are undefined; if CHAR_LEN is less than 0_1111, the value of SPITBR2 and SPITBR3 are undefined, and so on. SPI TX Buffer Register (SPITBR, 0x04) Bit 7 6 5 4 Name Reset Value 3 SPITBR0 SPITBR1 SPITBR2 SPITBR3 0x0000_0000 2 1 0 Bit Name Access Description 7:0 SPITBR0 When in SPI master mode, the SPITBR registers hold the data to be transmitted in the ... ... next transfer. Valid bits depend on the CHAR_LEN bits of SPIMCR. For example, if 31:24 SPITBR3 R/W CHAR_LEN is less or equal to 0_0111, the value of SPITBR1, SPITBR2 and SPITBR3 are undefined, if CHAR_LEN is less than 0_1111, the value of SPITBR2 and SPITBR3 are undefined, and so on. 248 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY SPI Control Register (SPICR, 0x08) Bit Name Reset Value Bit Name 7 SSOE 0 Access 0 SSP R/W 1 CPHA R/W 2 CPOL R/W 3 LSB R/W 4 SPIEN R/W 5 ASS R/W 6 MSS R/W 7 SSOE R/W 6 MSS 0 5 ASS 0 4 SPIEN 0 3 LSB 0 2 CPOL 0 1 CPHA 0 0 SSP 0 Description Slave Select pins (SS0, SS1, SS2) active Polarity. This bit is only valid in SPI master mode. 1: The slave select signals are active-high. 0: The slave select signals are active-low. When in SPI slave mode, this chip always uses SS0 for the SPI slave controller and it is always active-low. SPI Clock Phase Bit. This bit is used to control the SCLK pin, serial clock phase vs. serial data. This bit applies to both SPI master and SPI slave mode. 1: The first SCLK edge is issued at the beginning of the 8-cycle transfer operation. 0: The first SCLK edge is issued one-half cycle into the 8-cycle transfer operation. SPI Clock Polarity Bit. 1: Active-low clock selected. 0: Active-high clock selected. When in SPI master mode, this bit indicates that the LSB bit is transmitted/received first. 1: The LSB of SPITBR is sent first on the line, and the first bit received from the line will be put in the LSB position in the SPIRBR register. 0: The MSB of SPITBR is transmitted first and the first bit received is put in MSB position of SPIRBR. Note that in SPI slave mode, it is always the MSB bit of each 8-bit data being transmitted or received first. SPI Enable. 1: SPI controller is enabled. 0: SPI controller is disabled. When in SPI master mode, Automatically generate Slave Select signals (SS0, SS1, SS2). 1: The slave select signal is generated automatically. This means that when setting GO_BSY bit of SPIMCR to start the transfer, the slave select signal that is indicated in SPISSR is asserted by the SPI controller automatically and is de-asserted after the transfer is finished. 0: SS0/1/2 signals are asserted and de-asserted by writing and clearing bits in SPISSR register. When this bit is setting to 0, the SSP of SPICR will not effect, and the SS0/1/2 signals is controlled directly by SPISSR register. This bit is only available in SPI master mode. Master/Slave mode Select. 1: The SPI controller is set to operate in SPI mater mode. 0: The SPI controller is set to operate in SPI slave mode. Slave Select pins (SS0, SS1, SS2) Output Enable. 1: Enable driving slave select signals. 0: Put slave select signals to tri-state. 249 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY SPI Master Command Register (SPIMCR, 0x09) Bit Name Reset Value Bit Name 7 GO_BSY 0 6 LL 0 5 LCSR 0 4 3 2 CHAR_LEN 0_0111 1 0 Access Description When in SPI master mode, this field specifies how many bits in SPIRBR and SPITBR 4:0 CHAR_LEN R/W are transmitted on each transfer. Up to 32 bits can be transmitted. For example, the value of "0_0111" indicates 8 bits to be transferred. When in SPI master mode, setting `1' to suppress the last SCLK in the current transfer 5 LCSR R/W (used in some SPI EEPROM case). Long Length. 1: The desired transfer data length in one transfer is more than the value of CHAR_LEN. Setting `1' to keep the SS0/1/2 pins asserted after the transfer. This 6 LL R/W can be used in the case where more than 32 bits of data need to be transferred in one transfer. 0: The desired transfer data length is equal to CHAR_LEN. Setting `0' makes SS0/1/2 pins de-asserted automatically after the transfer. Writing 1 to this bit starts the transfer. This bit remains set during the transfer and is 7 GO_BSY W1/R automatically cleared after the transfer finished. Writing 0 to this bit has no effect. This bit is only valid in SPI master mode. SPI Baud Rate Register (SPIBRR, 0x0A) 7 Bit Name Reset Value 5 4 3 2 1 0 Divider 0xFF Bit Name Access 7:0 Divider 6 Description The value in this field determines the frequency divider of the operating system clock to generate the serial clock SCLK output. The desired frequency is obtained according to the following equation: R/W SCLK Frequency = Operating System Clock Frequency (Divider+1)*2 SPI Slave Select Register (SPISSR, 0x0B) 7 Bit Name Reset Value Bit Name 2:0 SS 7:3 Reserved 6 5 Reserved 11111 4 3 2 1 SS 111 Access 0 Description When in SPI master mode, this is used to select the desired slave device to communicate to. For example, set SS = 110 to activate the SS0 pin. R/W When in SPI slave mode, this chip always uses SS0 for the SPI slave controller and it is always active-low. - 250 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY SPI Interrupt Status Register (SPIISR, 0x0C) 7 Bit Name Reset Value Bit Name Access 0 STCF CR 3:1 Reserved 4 SRCF 7:5 Reserved 6 Reserved 000 5 4 SRCF 0 3 2 Reserved 000 1 0 STCF 0 Description SPI Transceiver Complete Flag in SPI master mode. 1: This flag is asserted after the requested transfer (via setting GO_BUSY bit in SPIMCR) is completed. 0: The SPI bus is idle or the transfer is in progress. - CR SPI Receive Complete Flag in SPI slave mode. 1: This flag is asserted every time when the SPISB contain valid data received from the external SPI master after one transfer. Note that in Table 57, all the received instructions, except for the RSR and RDR, will cause this bit to be set after transfer completed. 0: The SPI bus is idle or the transfer is in progress. - SPI Interrupt Enable Register (SPIIER, 0x0D) 7 Bit Name Reset Value Bit Name 0 STCFIE 3:1 Reserved 4 SRCFIE 7:5 Reserved 6 Reserved 000 5 4 SRCFIE 0 3 2 Reserved 000 1 0 STCFIE 0 Access Description SPI Transmit Complete Flag Interrupt Enable. R/W 1: Enable interrupt on INT4 whenever STCF flag (SPIISR.0) is asserted. 0: Disable interrupt. SPI Receive Complete Flag Interrupt Enable. R/W 1: Enable interrupt on INT4 whenever SRCF flag (SPIISR.4) is asserted. 0: Disable interrupt. - SPI Slave Command Register (SPISCR, 0x0E) Bit Name Reset Value Bit Name 7 6 5 4 Reserved 000_0000 3 2 1 Access 0 RDY 1 Description During initialization, software shall set this bit to `1' to indicate to the external SPI master that this chip is ready to receive any commands. This bit will be reflected in the RSR instruction as listed in Table 57. This is only valid in SPI slave mode. When external SPI master needs to read data from this chip, software first prepares the data in SPISB register and then set this bit `1' to indicate to the external SPI master that the 0 RDY W1/R data is ready to be retrieved by the external SPI master. When external SPI master needs to write data to this chip, it initiates the SPI bus access and then checks for completion indication from this chip. Software of AX11015 shall retrieve the data from SPISB register and then sets this bit `1' to indicate that the requested write operation has been completed by this chip. 7:1 Reserved - 251 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY SPI Slave Buffer (SPISB, 0x10) 7 Bit Name Reset Value Bit 6 5 4 3 2 1 SB0 SB1 SB2 SB3 SB4 SB5 SB6 SB7 SB8 SB9 SB10 SB11 SB12 SB13 SB14 SB15 0x0000_0000_0000_0000_0000_0000_0000_0000 0 Name Access 7:0 SB0 ... ... 127:120 SB15 Description Slave Buffer. This is only valid in SPI slave mode. When in SPI slave mode, this holds the data received from the external SPI master. The SB0 holds the first 8-bits received, and SB1 holds the second 8-bits received, and so on. R/W Note that the transfer of each 8-bit serial data is always MSB first. When external SPI master issues the read command, software can put requested read data in SPISB here. Again SB0 holds the first 8-bits transmitted data, and SB1 holds the second 8-bits transmitted data, and so on. Example Programming Procedure in SPI Master Mode Example 1: Configure to SPI Mode 0, SPI frequency is 1.6MHz, and enable interrupt mode. Write 2 bytes of data = 0x0500 to slave device. 1. Write 0xFE to SPISSR register. 2. Write 0x1D to SPIBRR register. 3. Write 0x01 to SPIIER register. 4. Write 0xF0 to SPICR register. 5. Write 0x00, 0x05, 0x00, and 0x00 to SPITBR. 6. Write 0x8F to SPICMR register. 7. Wait interrupt. 8. Read SPIISR register to clear STCF. 9. Read SPIRBR register if needed. Example 2: Read 1 byte of data from slave device. 1. Write 0xFE to SPISSR register. 2. Write 0x1D to SPIBRR register. 3. Write 0x01 to SPIIER register. 4. Write 0xF0 to SPICR register. 5. Write 0x87 to SPICMR register. 6. Wait interrupt. 7. Read SPIISR register to clear STCF. 8. Read SPIRBR register. 252 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 4.20.2 SPI Slave Mode Function Description The SPI slave controller of this chip provides 8 different commands for the external SPI master controller to access it. These commands are shown in Table 57 and the command frame format is shown in Figure 138. Note that the serial data is always the MSB bit of each 8-bit data being transmitted or received first. The external SPI master may use these commands to read or write the SFR registers or xDATA memory of this chip. The SPI slave controller hardware shall parse the Op-Code byte and user should follow the definition here, all other bytes in the transfer are parsed by AX11015 software. Therefore, these commands are allowed to make certain changes to meet user's applications. Command Name Op-Code Operation Description Read Status Register. RSR 0000_0000 (0x00) When external SPI master needs to send some data to this chip, the returned status of 0x01 indicates that this chip is ready to receive new data. To avoid the internal 16-bytes FIFO overflow, the external SPI master shall check this status before sending next data to this chip. Returning 0x00 indicates the internal FIFO is still being used and this chip is not ready. When external SPI master needs to receive some data from this chip, returning 0x01 indicates that the requested data is ready in SPISB and the external SPI master can issue RDR command to receive the requested data. Returning 0x00 indicates the data is not ready. RDR 0001_0000 (0x10) Read Data Register. This is the data port for the external SPI master to receive the requested read data after it has issued SR_SFR, IR_SFR, and BR_MEM commands. Single Write SFR register. This command requests to write various bytes of data to the specified SFR register in this 1010_0xxx chip with the given data. The xxx indicates the number of bytes to be written to the target SW_SFR (0xA0~0xA7) registers. For example, xxx = 000 for 1 byte, and xxx = 111 for 8 bytes. After sending this command, to avoid internal 16-byte FIFO being overflowed, the external SPI master should use RSR command to learn that this chip has finished processing the command before it can send next command. Single Read SFR register. SR_SFR This command requests to read various bytes of data from the specified SFR register in 0010_0xxx this chip. The xxx indicates the number of bytes to be read from the target registers. For (0x20~0x27) example, xxx = 000 for 1 byte, and xxx = 111 for 8 bytes. After sending this command, the external SPI master should use RSR command to learn that the requested data is available and then use RDR command to receive the data. Indirect Write SFR register. This command requests to indirectly write various bytes of data through the specified command index register in SFR to the given indirect register in this chip. The xxxx indicates the number of bytes to be written to target indirect register. For example, xxxx = 0000 for 1 byte, and xxxx = 1111 for 16 bytes. IW_SFR 1011_xxxx (0xB0~0xBF) After sending this command, to avoid internal 16-byte FIFO being overflowed, the external SPI master should use RSR command to learn that this chip has finished processing the command before it can send next command. Typical indirect access registers uses following SFR register-pair to access through: DCIR/DDR, MCIR/MDR, EPCR/EPDR, TCIR/TDR, I2CCIR/I2CDR, OWCIR/OWDR, etc. IR_SFR 0011_xxxx Indirect Read SFR register. 253 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY (0x30~0x3F) This command requests to indirectly read various bytes of data through the specified command index register in SFR from the given indirect register in this chip. The xxxx indicates the number of bytes to be read from the target indirect register. For example, xxxx = 0000 for 1 byte, and xxxx = 1111 for 16 bytes. After sending this command, the external SPI master should use RSR command to learn that the requested data is available and then use RDR command to receive the data. Typical indirect access registers uses following SFR register-pair to access through: DCIR/DDR, MCIR/MDR, EPCR/EPDR, TCIR/TDR, I2CCIR/I2CDR, OWCIR/OWDR, etc. Burst Write data to xDATA memory of this chip. BW_MEM This command requests to write the specified address of xDATA memory in this chip with the specified number of bytes and the given data. The {ADDR2, ADDR1, ADDR0} represents the real address of xDATA memory. The xxxx indicates the number of bytes to be written, starting with the specified address. For example, xxxx = 0000 for 1 byte, and xxxx = 1011 for 12 bytes. The Data0 is written to the {ADDR2, ADDR1, ADDR0}, and the Data1 is written to the {ADDR2, ADDR1, ADDR0}+1, and so on. 1100_xxxx (0xC0~0xCB) Note that the fields of ADDR0, ADDR1, ADDR2, Data0, DataN, etc. in BW_MEM command are reference format and can allow making changes as long as the AX11015 software and external SPI master both agree on the format definition. Only that the xxxx in the Op-Code field should match the actual number of bytes being transferred. After sending this command, to avoid internal 16-byte FIFO being overflowed, the external SPI master should use RSR command to learn that this chip has finished processing the command before it can send next command. Burst Read Memory. BR_MEM This command requests to read the specified address of xDATA memory in this chip with the specified number of bytes. The {ADDR2, ADDR1, ADDR0} represents the real address of xDATA memory. The xxxx indicates the number of bytes to be read, starting with the specified address. For example, xxxx = 0000 for 1 byte, and xxxx = 1011 for 12 bytes. 0100_xxxx (0x40~0x4F) Note that the fields of ADDR0, ADDR1, ADDR2, etc. in BR_MEM command are reference format and can allow making changes as long as the AX11015 software and external SPI master both agree on the format definition. Only that the xxxx in the Op-Code field should match the actual number of bytes being transferred. After sending this command, the external SPI master should use RSR command to learn that the requested data is available and then use RDR command to receive the data. Table 57: Command Instruction in SPI Slave Mode 254 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY SS RSR OP (0x00) Status RDR OP (0x10) DR0 DR15 SR_SFR OP SFR Addr (0x20) SW_SFR OP SFR Addr (0xA0) Data0 OP SFR Addr (0xA1) Data0 Data1 IR_SFR OP (0x30) CIR Ind Reg. IW_SFR OP (0xBD) CIR Ind Reg. Data0 BR_MEM OP (0x40 ~ 0x4F) ADDR0 ADDR1 ADDR2 BW_MEM OP (0xC0 ~ 0xCB) ADDR0 ADDR1 ADDR2 Data12 Data0 Data11 Note: DRN : Data Register CIR : Command Index Register Ind Reg. : Indirect Register Master Slave Figure 138: Command Frame Format in SPI Slave Mode 255 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Example Command Frames in SPI Slave Mode 1) Write 0x00 to OWIER register ss OP=B0 CR=D6 Reg.=03 D=00 2) Read Data from I2CCPR register ss OP=30 CR=96 Reg.=00 OP=00 D=00 OP=00 OP=10 D=XX D=XX D=01 3) Write two bytes data (00,01) starting at memory address = 0x012345 and write one byte data(aa) to the other address = 0xccddee ss OP=C1 A0=45 A1=23 A2=01 D=00 OP=C0 A0=ee D=aa D=01 OP=00 D=00 OP=00 D=01 ss A1=dd A2=cc 4) Read three bytes data starting from memory address = 0x445566 and read one byte from the other address = 0x112233 ss OP=42 A0=66 A1=55 A2=44 OP=00 D=00 OP=10 D=XX D=XX D=XX OP=40 A0=33 A1=22 A2=11 OP=00 D=01 ss ss OP=00 D=00 OP=00 D=01 OP=10 D=XX 256 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 4.21 Local Bus Interface and Digiport The Local Bus Interface (LBI) is AX11015 high-speed parallel interface used to communicate with external devices or CPU. It supports three modes of operation, namely, Local Bus master mode, Local Bus slave mode, and Digiport mode. Because they share some pins so only one mode can be activated at a time. When operating in Local Bus master mode, the internal 1T 80390 CPU can accesses through the LBI to control or communicate with the external local bus devices up to 2 chip selects. When operating in Local Bus slave mode, the external system CPU can control the LBI to communicate with internal 1T 80390 CPU to access the internal registers and memory resources. When operating in Digiport mode (receive only) through LBI, the internal 1T 80390 CPU can receive Motion-JPEG streaming data from external STMicroelectronics STv0676 M-JPEG encoder chip or STv0684 M-JPEG encoder chip. For the list of features for the 3 modes of operation, please refer to section 2.21. In all three operation modes, the Local Bus contains a memory bridge with 32-bytes FIFO to allow performing burst read/write access through DMA mode to speed up bulk data transfer time. The single read/write access is handled directly by the 1T 80390 CPU in Local Bus master mode or by the external system CPU in the Local Bus slave mode. SFR Bus SFR registers LBI Master Controller LBI Slave Controller LCS0_N LALE LWR_N LRD_N LINT LUDS_N LLDS_N LRDY LA [3:0] LDA [15:0] Digiport Controller LCS0_N LALE LRDY LDA [7:0] Memory Bridge DMA Engine (with 32-bytes FIFO) LCS0_N LCS1_N LALE LWR_N LRD_N LINT LUDS_N LLDS_N LRDY LA [15:0] LDA [15:0] RD_DRQ RD_DAK WR_DRQ WR_DAK Figure 139: Local Bus Interface and Digiport Block Diagram 257 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Memory Bridge The external bus access cycles of LBI and Digiport is normally slower than the internal xDATA memory bus. The Memory Bridge with 32-bytes FIFO provides transfer rate adaptation function and allows burst data transfer capability from/to xDATA memory through LBI or Digiport interface to/from external devices (or CPU) without compromising the xDATA memory bus utilization. Internally, the Memory Bridge uses burst transfer mode (DMA mode) to move data between the xDATA memory and the 32-bytes FIFO, and the LBI or Digiport interface will move data between the 32-bytes FIFO and the external devices (or CPU). Effectively, when the xDATA memory is not used by Memory Bridge, it allows the 1T 80390 CPU to continue processing, while the LBI or Digiport interface continues processing the data transfer between the 32-bytes FIFO and the external devices (or CPU). In Local Bus master mode or Digiport mode, when initiating a burst transfer through DMA mode within the Memory Bridge, the software on this chip shall configure the DMA Start Address in SFR register DMALR, DMAMR, and DMAHR, and also provide the number of burst transfer bytes in SFR register LCR. Please refer to Table 58. Once burst transfer is initiated, the Memory Bridge will send DMA request to DMA engine for moving data between the xDATA memory and 32-bytes FIFO. If the burst transfer bytes given are over 32 bytes, then the memory bridge will send several DMA requests until done with requested bytes. In Local Bus slave mode, when initiating a burst transfer through DMA mode within the Memory Bridge, the software on external CPU shall configure the DMA Start Address in BALWR and BAHWR register (16-bit bus mode) or BALR, BAMR, BAHR registers (8-bit bus mode), and also provide the number of burst transfer bytes in CR register. Please refer to Table 59. Again, once burst transfer is initiated, the Memory Bridge will send DMA request to DMA engine for moving data between the xDATA memory and 32-bytes FIFO. Bus Endian Type Internal to AX11015, it's operating in 8-bit bus width. When communicating with external local bus devices (or CPU) in 16-bit bus width in Local Bus master or Local Bus slave mode, the Endian type of external LBI data bus can be programmed by I2C EEPROM offset 0x12 to match the Endian type of the external local bus devices (or CPU). Note that when LBI is operating in 8-bit mode, the Endian type setting shall have no effect. Example 1: Following is the example when LBI is in 16-bit bus width and Local Bus master mode. The internal 1T80390 CPU writes data to external devices using SFR register LDLR (0xA9) and LDHR (0xAA). 7 0 7 LDHR 0 LDLR ENDIAN bit = 1 (Little Endian): The LDLR and LDHR will be byte-swapped by LBI before presenting on to LDA [15:0] pins. While reading back, the LDA[15:8] being read shall be stored in LDLR and LDA[7:0] in LDHR. 15 Local bus data bus: LDA [15:0] 8 7 LDLR 0 LDHR 258 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 7 0 7 LDHR ENDIAN bit = 0 (Big Endian): The LDHR and LDLR will be mapped directly on to LDA[15:0] by LBI. While reading back, the LDA[15:8] being read shall be stored in LDHR and LDA[7:0] in LDLR. 15 LDLR 8 7 LDHR Local bus data bus: LDA[15:0] 0 0 LDLR Example 2: Following is the example when LBI is in 16-bit bus width and Local Bus slave mode. The external CPU writes data to AX11015 using XMWR register (0x02). This data can be read by internal 1T80390 CPU via SFR registers XMWHR (0xA5) and XMWLR (0xA4). 15 Local bus data bus: LDA [15:0] ENDIAN bit = 1 (Little Endian): The LDA[15:0] data shall be byte-swapped by LBI before storing it into SFR register XMWLR and XMWHR. Note when external CPU reads XMWR from LDA[15:0], it shall read back the same value as it wrote. 8 XMWR[15:8] 7 7 XMWR[7:0] 0 7 XMWHR 15 Local bus data bus: LDA [15:0] ENDIAN bit = 0 (Big Endian): The LDA[15:0] shall be mapped directly to SFR register XMWHR and XMWLR by LBI. Again, when external CPU reads XMWR from LDA[15:0], it shall read back the same value as it wrote. 0 XMWLR 8 XMWR[15:8] 7 0 7 0 XMWR[7:0] 0 7 XMWHR 0 XMWLR 259 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 4.21.1 Local Bus Interface and Digiport SFR Register Map Table 58 below shows the Local Bus and Digiport SFR register map. These registers are shared by the 3 operation modes, therefore, the register definition may be different in different mode. Address 0xA1 Local Bus Master Mode Name Description Local Bus Mode Setup LMSR Register 0xA2 LCR 0xA3 LSR 0xA4 LDALR 0xA5 LDAHR 0xA6 LDCSR 0xA7 0xA9 LDLR 0xAA LDHR 0xAB DMALR 0xAC DMAMR 0xAD DMAHR Local Bus Slave Mode Digiport Mode Name Description Name Description Local Bus Slave mode Local Bus Mode Setup LSAIER Action and Interrupt LMSR Register Enable Register Local Bus Command Local Bus Slave mode Local Bus Command LSCR LCR Register Command Register Register Local Bus Status Register Local Bus Slave mode Local Bus Status Register LSSR LSR Status Register Local Bus Device External Master Address Low Register XMWLR Write-read Low Reserved Register Local Bus Device External Master Address High Register XMWHR Write-read High Reserved Register Local Bus Device Chip External Master Select Register XMRLR Read-only Low Reserved Register External Master Reserved XMRHR Read-only High Reserved Register Local Bus Data Low Local Bus Data Low Reserved LDLR Register Register Local Bus Data High Local Bus Data High Reserved LDHR Register Register Local Bus DMA Address Local Bus DMA Address Reserved DMALR Low Register Low Register Local Bus DMA Address Local Bus DMA Address Reserved DMAMR Medium Register Medium Register Local Bus DMA Address Local Bus DMA Address Reserved DMAHR High Register High Register Table 58: Local Bus Interface and Digiport SFR Register Map 260 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 4.21.2 Local Bus Master Mode The main features of Local Bus master mode are listed below, z Support 8-bit or 16-bit data bus width, and support little and big Endian bus swap z Support up to 64K bytes address space and 2 chip select outputs z Support asynchronous or synchronous Local Bus interface with required Local Bus clock output, LB_CLK z Allow internal 1T 80390 CPU to control off-chip low speed local bus devices which are Intel 80186/80386, ISA, Motorola 68000, and TI DSP's HPI (16 bits only) compatible bus style z Support single access as well as programmable burst read or write access up to 256 bytes in one software command. Under the control of internal 1T 80390 CPU, it can support burst read/write access for moving data in to/out of internal CPU's xDATA memory via DMA transfer z Support slave request based DMA access (LCS0_N only) for interfacing with external A/V Codec chip with burst data transfer z Support byte-access for single read/write access command in 16-bit bus width (not supported in burst access command) z Flexible bus style configuration loaded from I2C Configuration EEPROM in offset 0x12 and 0x13 For the reference pin connection, please refer to section 2.21.1. 4.21.3 Local Bus Master Mode SFR Register Detailed Description Local Bus Mode Setup Register (LMSR, 0xA1) 7 Bit LB_EN Name 0 Reset Value Bit Name 6 SDMA_EN 0 Access 0 AC_INT_EN R/W 1 EXT_INT_EN R/W 4:2 BUS_ACC R/W 5 DGP_EN R/W 6 SDMA_EN R/W 7 LB_EN R/W 5 DGP_EN 0 4 3 BUS_ACC 00 2 1 0 EXT_INT_EN AC_INT_EN 0 0 Description Access Complete Interrupt Enable. 1: Enable generating interrupt on INT4 and being reflected in LB_INT bit (PISS1R.0) when the AC flag (LSR.0) is set. 0: Disable interrupt. Local Bus External Interrupt Enable. 1: Enable generating interrupt on INT4 and being reflected in LB_EINT bit (PISS1R.1) when the local bus interrupt pin, LINT, is asserted. 0: Disable local bus external interrupts from LINT pin. Bus Cycle. This controls the number of system clock cycles on local bus I/O signal timing. Please refer to local bus AC timing in section 5.4.8 for more details. Digiport Mode Enable. 1: Enable Digiport mode. 0: Disable Digiport mode. Set to "0" in Local Bus master mode. Slave-DMA mode Enable (for LCS0_N only). 1: Enable slave request based DMA mode. When enabled, if SDWR_REQ or SDRD_REQ flag (in LSR) is set, it will trigger an interrupt on INT4. 0: Disable slave request based DMA mode. When disabled, if SDWR_REQ or SDRD_REQ flag is set, it will not trigger interrupt. Local Bus mode Enable. 1: Enable local bus mode. 0: Disable local bus mode. Note: between LB_EN and DGP_EN bits, user should only enable either one to `1' at a time. 261 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Local Bus Command Register (LCR, 0xA2) Bit Name Reset value Bit Name 2:0 BUR_NO 3 BUR_TYP 4 WR 6:5 RDY_CY 7 GO 7 GO 0 Access 6 5 RDY_CY 00 4 WR 0 3 BUR_TYP 0 2 1 BUR_NO 00 0 Description Number of Burst bytes. Software sets this field to notify the LBI the number of bytes to be transferred. Setting to "0" disables burst mode, and the LBI works in single access and uses LDLR & LDHR for single data transfer. Setting to non -zero enables burst mode, and the LBI activates the DMA mode for burst data transfer, and the BURST_NO here is total number of bytes to be transferred in burst on external Local Bus Interface. In that case, the DMA source or target address of xDATA memory is provided in DMALR, DMAMR and DMAHR. R/W BUR_NO Burst Bytes 000 Single access. 001 16 bytes of burst access. 010 32 bytes of burst access. 011 64 bytes of burst access. 100 128 bytes of burst access. 101 256 bytes of burst access. 110 188 bytes of burst access. 111 Reserved. Burst type. If BUR_NO is non-zero when burst mode is enabled, the address bus on Local Bus Interface, LA[15:0] or LDA[15:0] in multiplexed address data bus style, can be: 1: Auto- increment address. The address value of first access is provided in LDALR R/W and LDAHR, the next access will be increased by 1 (8-bit mode) or 2 (16-bit mode) automatically. 0: Fixed address. The address value of each access during the burst mode is always fixed to the value provided in LDALR and LDAHR. Read or write to the external local bus devices. R/W 1: Indicate to write to external local bus devices. 0: Indicate to read from external local bus devices. Terminating the local bus access cycles based on either bus ready pin LRDY or Ready Cycle settings here. If RDY_CY is "00", the bus ready pin LRDY is used to terminate the local bus access cycles. Otherwise, the LBI generates the internal "ready" signal based on RDY_CY setting here to terminate the local bus access cycle automatically (with self-terminated timer). In that case, the internal ready counter starts to count when the bus address and control signal are being generated. Please also refer to local bus AC R/W timing in section 5.4.8 for more details. Bus Access Termination Cycle RDY_CY 00 Use bus ready pin LRDY to terminate access cycle. 01 2*(BUS_ACC+1) 10 3*(BUS_ACC+1) 11 4*(BUS_ACC+1) Local bus access Go. W1/R 1: Setting this bit to "1" to start the single or burst access on local bus. 0: This bit is automatically cleared by LBI once the requested access is finished. 262 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Local Bus Status Register (LSR, 0xA3) Bit Name Reset value 7 LB_MOD 0 Bit Name 0 AC 1 SYNC_BUS 2 SDWR_REQ 3 SDRD_REQ 6 LB_W 0 5 4 3 SDRD_REQ 0 Reserved 00 2 1 SDWR_REQ SYNC_BUS 0 0 0 AC 0 Access Description CR Access Complete. Normally after software issues a LBI single or burst access, software can check this bit to know that the requested access has been completed or not. 1: Reading "1" indicates that the LBI has finished the requested command. 0: The requested access is in progress or LBI is in idle mode. RO Synchronous local bus style. This bit reflects the SYNC_BUS pin setting. 1: Synchronous local bus. 0: Asynchronous local bus. CR Slave DMA Write Request. 1: When SDMA_EN bit (LMSR.6) is enabled, reading "1" indicates that the external local bus device on LCS0_N is ready to receive burst data by asserting the WR_DRQ pin. Note that the write acknowledge to the requested device is automatically generated on WR_DAK pin by LBI once the burst write command is initiated by software in LCR. 0: WR_DRQ pin is not asserted. CR Slave DMA Read Request. 1: When SDMA_EN bit (LMSR.6) is enabled, reading "1" indicates that the external local bus device on LCS0_N is ready to send burst data by asserting the RD_DRQ pin. Note that the read acknowledge to the requested device is automatically generated on RD_DAK pin by LBI once the burst read command is initiated by software in LCR. 5:4 Reserved 6 LB_W RO 7 LB_MOD RO Local bus width indication. This bit reflects the bus width setting in I2C EEPROM. 1: 16 bits bus width. 0: 8 bits bus width. Local bus mode indication. This bit reflects the LB_MOD pin setting. 1: Local bus is operating in slave mode. 0: Local bus is operating in master mode. Local Bus Device Address Low Register (LDALR, 0xA4) Bit Name Reset Value 7 6 5 4 3 LADDR [7:0] 00 2 1 0 Bit Name 7:0 LADDR[7:0] Access Description R/W This configures the value of local bus address pins, LA[7:0] or LDA[7:0] in multiplexed address data bus style. Local Bus Device Address High Register (LDAHR, 0xA5) Bit Name Reset Value 7 6 5 4 3 LADDR [15:8] 00 2 1 0 Bit Name Access Description 7:0 LADDR[15:8] R/W This configures the value of local bus address pins, LA[15:8] or LDA[15:8] in multiplexed address data bus style. 263 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Local Bus Device Chip Select Register (LDCSR, 0xA6) Bit Name Reset Value Bit Name 0 CS0 1 CS1 6: Reserved 2 7 BYTE 7 BYTE 0 6 5 4 Reserved 00 3 2 1 CS1 0 0 CS0 0 Access Description R/W Chip Select 0. 1: Assert LCS0_N pin during local bus access cycles. 0: Do not assert LCS0_N pin during local bus access cycles. R/W Chip Select 1. 1: Assert LCS1_N pin during local bus access cycles. 0: Do not assert LCS1_N pin during local bus access cycles. User should avoid setting both CS0 and CS1 bit to 1 at the same time. R/W Byte-access enable. This feature is only valid in single access and 16-bits bus width. That is, byte-access is not supported in burst access. 1: When set, the LBI will present LDLR on both high and low bytes of LDA[15:0] bus during write access. During read access, it will move either high or low byte of LDA[15:0] to LDLR depending on LDALR value whether is odd or even. In both cases, asserting either LLDS_N or LUDS_N pin is also depending on LDALR value. The byte-access timing diagram is shown in Figure 140. Endian bit 0 (Big Endian) 0 (Big Endian) 1 (Little Endian) 1 (Little Endian) LDALR value Odd Even Odd Even LDA[15:8] value LDLR LDLR LDLR LDLR LDA[7:0] value LDLR LDLR LDLR LDLR Data Strobe Asserted LLDS_N LUDS_N LUDS_N LLDS_N 0: Disable byte access in 16-bit bus width, and every single access is word-access. Local Bus Data Low Register (LDLR, 0xA9) Bit Name Reset value 7 6 5 4 3 DATA[7:0] 00 2 1 0 Bit Name Access Description 7: DATA[7:0] R/W This is the lower byte of local bus data for single access. Following table shows the 0 LDLR mapping to LDA[15:0] bus. If byte access is enabled in single access, this is used to hold the data. Endian bit LDLR 0 LDA[7:0] 1 LDA[15:8] 264 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Local Bus Data High Register (LDHR, 0xAA) Bit Name Reset value 7 6 5 4 3 DATA[15:8] 00 2 1 0 Bit Name Access Description 7:0 DATA[15:8] R/W This is the higher byte of local bus data for single access. Valid only in 16-bit bus width. Following table shows the LDHR mapping to LDA[15:0] bus. Endian bit LDHR 0 LDA[15:8] 1 LDA[7:0] Local Bus DMA Address Low Register (DMALR, 0xAB) Bit Name Reset Value 7 6 5 4 3 2 LB_DMA_ADDR[7:0] 00 1 0 Bit Name Access Description 7:0 LB_DMA_ADDR[7:0] R/W Local Bus DMA Address [7:0] for burst read/write access. Local Bus DMA Address Medium Register (DMAMR, 0xAC) Bit Name Reset Value 7 6 5 4 3 2 LB_DMA_ADDR[15:8] 00 1 0 Bit Name Access Description 7: LB_DMA_ADDR[15:8] R/W Local Bus DMA Address [15:8] for burst read/write access. 0 Local Bus DMA Address High Register (DMAHR, 0xAD) Bit Name Reset Value Bit 7 6 Reserved 5 4 3 2 1 LB_DMA_ADDR[20:16] 0 00 Name Access 4: LB_DMA_ADDR 0 [20:16] Description LB DMA Address [20:16] for burst read/write access. In Local Bus master mode, when doing burst write access to external local bus R/W device, the LB_DMA_ADDR [20:0] is used to indicate the source start address of xDATA memory. When doing burst read access, it indicates the target start address. The number of burst bytes is provided in BUR_NO bits in LCR register. 7: Reserved 5 265 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Byte-Access in 16-bit Bus Width Mode Local Bus master mode supports byte-access when software issues single access command in 16-bit bus width mode. This allows some local bus devices with fewer address lines and using even and odd address space for different register definitions to work with this chip. The LLDS_N and LUDS_N pins are the data strobe signals for indicating low byte data valid and high byte data valid, respectively, on LDA[15:0] data bus. The value of LDALR and ENDIAN bit in I2C EEPROM shall affect the assertion of these two data strobes. Please refer to below timing diagram. Note: In byte-access mode, software always reads and writes data through LDLR. LCSx_N LA [15:0] even odd LWR_N/LRD_N LUDS_N (Big Endian) LLDS_N (Big Endian) LUDS_N (Little Endian) LLDS_N (Little Endian) Figure 140: Byte-Access Timing Diagram in Local Bus Master Mode Example Programming Procedure in Local Bus Master Mode In Local Bus master mode, there are 4 types of bus access supported by LBI, namely, single write, single read, burst write, and burst read accesses. The programming examples of these 4 types are provided below for user reference. Example 1: Single Write Access 1. Software writes local bus device address in LDALR, LDAHR and LDCSR and writes desired data in LDLR, LDHR, and then issues a single write command to LCR. If byte-write access is needed in 16 bits bus width, software can also set the BYTE bit in LDCSR before issuing LCR. 2. The LBI generates external local bus signals and handles transfer until it finishes. 3. Software can wait for the interrupt by enabling AC_INT_EN bit (LMSR.0) or poll the LSR register to know if the requested single write access has been completed. Below shows example SFR programming sequence for this single write access. 266 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Example 2: Single Read Access 1. Software writes local bus device address in LDALR, LDAHR and LDCSR and then issues a single read command to LCR. If byte-read access is needed in 16 bits bus width, software can also set the BYTE bit in LDCSR before issuing LCR. 2. The LBI generates external local bus signals and receives data into LDLR (and LDHR). 3. Software can wait for the interrupt by enabling AC_INT_EN bit (LMSR.0) or poll the LSR register to know if the requested single read access has been completed. 4. Software can read data from LDLR (and LDHR). Below shows example SFR programming sequence for this single read access. Example 3: Burst Write Access 1. Software writes local bus device address in LDALR, LDAHR, and LDCSR, and writes the DMA source start address of internal xDATA memory in DMALR, DMAMR and DMAHR, and then issues a burst write command to LCR. 2. Internally, the LBI sends DMA request to move data from internal xDATA memory to the 32-byte FIFO. When the FIFO becomes non-empty, the LBI starts presenting the data onto external local bus. If requested burst bytes are more than 32, the FIFO can be filled up quickly. The Memory Bridge monitors the FIFO level, it will stop DMA request when full, and it will resume DMA request when almost empty. This way the write data can be appeared on the external local bus continuously without gap in between. Therefore, the burst write access is achieved. 3. After requested burst bytes have been moved from xDATA memory to FIFO, the LBI will stop the DMA request. However, the LBI will continue outputting the write data on to local bus from FIFO until the FIFO is empty. 4. Software can wait for the interrupt by enabling AC_INT_EN bit (LMSR.0) or poll the LSR register to know if the requested burst write access has been completed. Below shows example SFR programming sequence for this burst write access. Note: If the local bus device supports slave-request based DMA write transfer, user can use "LCS0_N" pin for that. When enabled this feature by setting SDMA_EN bit (LMSR.6), the local bus device may assert WR_DRQ pin to indicate it's ready to receive burst write data. This will be reported in SDWR_REQ bit (LSR.2) and also causes an interrupt on INT4. After receiving interrupt (or polling), software can follow step 1 described above to initiate the burst write access. To shorten WR_DRQ assertion to WR_DAK assertion time, software can configure LDALR, LDAHR, LDCSR, DMALR, DMAMR, and DMAHR first and wait for the interrupt triggered by WR_DRQ assertion. When interrupt is triggered, software only sets LCR to initiate the burst write immediately. 267 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Example 4: Burst Read Access 1. Software writes local bus device address in LDALR, LDAHR, and LDCSR, and writes the DMA target start address of internal xDATA memory in DMALR, DMAMR, and DMAHR, and then issues a burst read command to LCR. 2. 2. Internally, the LBI starts generating external local bus signals to read data from local bus devices to the 32-byte FIFO. When the FIFO becomes almost full, the LBI sends DMA request to move data from FIFO to xDATA memory. The data transfer rate of LBI moving into FIFO is slower than DMA moving data out of FIFO. When the FIFO becomes empty, the DMA request will be stopped temporarily. On the other hand, the LBI can continue reading data from external local bus device and putting it in FIFO until done reading requested burst bytes. In that case, the LBI will issue one more DMA request to move the remaining data in FIFO to xDATA memory. 3. Software can wait for the interrupt by enabling AC_INT_EN bit (LMSR.0) or poll the LSR register to know if the requested burst read access has been completed. Below shows example SFR programming sequence for this burst read access. Note: If the local bus device supports slave-request based DMA read transfer, user can use "LCS0_N" pin for that. When enabled this feature by setting SDMA_EN bit (LMSR.6), the local bus device may assert RD_DRQ pin to indicate it's ready to send burst read data. This will be reported in SDRD_REQ bit (LSR.3) and also causes an interrupt on INT4. After receiving interrupt (or polling), software can follow step 1 described above to initiate the burst read access. To shorten RD_DRQ assertion to RD_DAK assertion time, software can configure LDALR, LDAHR, LDCSR, DMALR, DMAMR, and DMAHR first and wait for the interrupt triggered by RD_DRQ assertion. When interrupt is triggered, software only sets LCR to initiate the burst read immediately. 268 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 4.21.4 Local Bus Slave Mode In Local Bus slave mode, AX11015's role is changed to a local bus device and the access of this interface is controlled by the external CPU. The external CPU controls AX11015 through accessing External CPU Registers as defined in Table 59. The main features of Local Bus slave mode are listed below, z Support 8-bit or 16-bit data bus width (in 16-bit data bus width the AX11015 only supports word access and doesn't support byte access), and support little and big Endian bus swap z Require 4-bit address lines and 1 chip select z Support asynchronous or synchronous Local Bus interface with required Local Bus clock input, LB_CLK z Allow external system CPU with Intel 80186/80386, ISA, Motorola 68000/68030, and Renesas SuperH3/4 compatible bus style to communicate with internal 1T 80390 CPU, internal registers, and memory resources z Support single access as well as programmable burst read or write access up to 32 bytes in one software command. Under the control of external system CPU, it can support burst read/write access for moving data out of/in to internal CPU's xDATA memory via DMA transfer z Allow the external system CPU and internal 1T 80390 CPU to exchange data via two unidirectional data ports which allows them to exchange information concurrently z Flexible bus style configuration loaded from I2C Configuration EEPROM in offset 0x12 and 0x13 For the reference pin connection with various CPUs, please refer to section 2.21.2. 4.21.5 External CPU Register in Local Bus Slave Mode Table 59 below shows the External CPU Register Map which the external system CPU can access to this chip in Local Bus slave mode for both 8 and 16-bit bus width. When operating in 8-bit bus width, each register is byte-access. When operating in 16-bit bus width, each register is word-access and no byte-access is allowed. 16-bit Bus Width Mode 8-bit Bus Width Mode Address Name Description Name Description 0x00 BDR Burst Data Register BDR Burst Data Register 0x01 Reserved 0x02 XMWR External Master Write-read Register XMWR External Master Write-read Register 0x03 Reserved 0x04 XMRR External Master Read-only Register XMRR External Master Read-only Register 0x05 Reserved 0x06 Burst Access Start Address Low Word Burst Access Start Address Low Register BALWR BALR Register 0x07 BAMR Burst Access Start Address Medium Register 0x08 Burst Access Start Address High Word Burst Access Start Address High Register BAHWR BAHR Register 0x09 Reserved 0x0A CR Command Register CR Command Register 0x0B Reserved 0x0C SR Status Register SR Status Register 0x0D Reserved 0x0E IER Interrupt Enable Register IER Interrupt Enable Register 0x0F Reserved Table 59: External CPU Register Map 269 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Burst Data Register (BDR, 0x00) 7 15 Bit 6 14 5 13 Name Reset Value 4 3 2 12 11 10 BUR_DATA [7:0] BUR_DATA [15:8] 0x0000 1 9 0 8 Bit Name Access Description BUR_DATA Burst Data register. This register is used to hold data for burst read or burst write access 15:0 R/W [15:0] in local bus slave mode. Note: [15:8] bits are only valid in 16-bit bus width mode. External Master Write-read Register (XMWR, 0x02) 7 15 Bit 6 14 5 13 Name Reset Value Bit Name 15:0 XMW_DATA [15:0] 4 3 12 11 XMW_DATA [7:0] XMW_DATA [15:8] 0x0000 2 10 1 9 0 8 Access Description External Master Write-readable Data register. This register is used for external CPU to send data to the software on internal CPU in single access. The external CPU R/W writing to XMWR register will cause the XW_FUL flag (LSSR.0 on SFR) to be set to "1". Note: [15:8] bits are only valid in 16-bit bus width mode. External Master Read-only Register (XMRR, 0x04) 7 15 Bit 6 14 5 13 Name Reset Value Bit 15:0 Name Access XMR_DAT A [15:0] RO 4 3 2 12 11 10 XMR_DATA [7:0] XMR_DATA [15:8] 0x0000 1 9 0 8 Description External Master Read-only Data register. This register is used for the software on internal CPU to send data to external CPU in single access. The external CPU reading from XMRR register will cause the XR_EMP flag (LSSR.2 on SFR) to be set to "1". Note: [15:8] bits are only valid in 16-bit bus width mode. Burst Access Start Address Low Register (BALR, 0x06) I used in 8-bit bus width Bit Name Reset Value Bit Name 7: BADDR[7:0] 0 7 6 5 4 3 BADDR [7:0] 0x00 2 1 Access Description R/W Burst Access Start Address [7:0]. 270 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights 0 AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Burst Access Start Address Medium Register (BAMR, 0x07) I used in 8-bit bus width 7 Bit Name Reset Value Bit Name 7: BADDR[15:8] 0 6 5 4 3 BADDR [15:8] 0x00 2 1 0 Access Description R/W Burst Access Start Address [15:8]. Burst Access Start Address High Register (BAHR, 0x08) I used in 8-bit bus width Bit Name Reset Value Bit Name 7 6 Reserved 5 4 3 2 1 BADDR [20:16] 0 0x00 Access Description Burst Access Start Address [20:16]. 4: BADDR 0 [20:16] In 8-bit bus width mode, the BAHR, BAMR and BALR are used for indicating the target start address of internal xDATA memory during burst write access (data is moving from R/W external CPU to internal xDATA memory) or for indicating the source start address of internal xDATA memory during burst read access (data is moving from internal xDATA memory to external CPU). During burst access, the address of internal xDATA memory is incremented automatically by LBI. 7: Reserved 5 Burst Access Start Address Low Word Register (BALWR, 0x06) I used in 16-bit bus width Bit 7 15 6 14 5 13 4 12 Name Reset Value 3 11 BADDR [15:0] 0x0000 2 10 1 9 0 8 Bit Name Access Description 15:0 BADDR[15:0] R/W Burst Access Start Address [15:0]. Burst Access Start Address High Word Register (BAHWR, 0x08) I used in 16-bit bus width Bit Name 7 15 6 14 Reserved 5 13 4 12 3 11 2 1 10 9 BADDR [20:16] 0 8 Reserved 0x0000 Reset Value Bit Name Access Description 4:0 BADDR R/W Burst Access Start Address [20:16]. [20:16] In 16-bit bus width mode, the BAHWR and BALWR are used for indicating the target start address of internal xDATA memory during burst write access (data is moving from external CPU to internal xDATA memory) or for indicating the source start address of internal xDATA memory during burst read access (data is moving from internal xDATA memory to external CPU). During burst access, the address of internal xDATA memory is incremented automatically by LBI. 271 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 15:5 Reserved RO Command Register (CR, 0x0A) Bit Name Reset Value 7 BGO 0 Bit Access Name 6 BT 0 5 BRR 0 4 XW_IC 0 3 BRD 0 2 1 BACC_NO 00 0 Description Burst Access Number. When external CPU initiates a burst read or write access, this burst access number indicates the number of bytes to be transferred in burst access. BACC_NO Burst Bytes 000 Reserved. 2:0 BACC_NO R/W 001 16 bytes of burst access. 010 32 bytes of burst access. Others Reserved Burst Read indication: 3 BRD R/W 1: Indicate to do burst read from this chip. 0: Indicate to do burst write to this chip. XMWR data Is Command flag. 1: The external CPU sets this flag to "1" before writing to XMWR register to notify the software on internal CPU that the content of XMWR to be transferred is served as command cycle. This will cause internal XW_IC flag (LSSR.1 on SFR) to be set. 0: The content of XMWR to be transferred is not a command cycle. This will cause 4 XW_IC W1 internal XW_IC flag (LSSR.1 on SFR) to be cleared. Note: The data exchange between the software on external CPU and the software on internal CPU can be in frame format which both agree on. For example, it can consist of Command phase and Data phase, and software can use this bit to indicate the data as being Command phase. Burst Read data Ready. 1: When external CPU initiates a burst read cycle (moving data from internal xDATA memory to external CPU), the external CPU needs to wait for this flag to be set to 5 BRR RO "1", indicating that the LBI has moved data from xDATA memory to the 32-bytes FIFO in LBI, then it can start reading the data from BDR register. This flag will be 1 whenever the FIFO has at least 1 byte of data available to be read. 0: The burst read data is not yet available in FIFO. Burst access Terminate. 1: Set "1" to terminate the burst access in progress. During burst access in progress when the external CPU is writing/reading burst data to/from BDR register, software can set this bit to "1"to terminate the requested burst access. When doing burst write access, upon setting this BT bit, the LBI will still move the already received data in FIFO to internal xDATA memory via DMA transfer. When 6 BT W1 doing burst read access, upon setting this BT bit, the LBI will stop the internal DMA transfer immediately and flush out the data in FIFO. So sometimes, the software on external CPU may decide to stop the burst access based on the number of bytes already been transferred so far. 0: This bit is cleared automatically after the LBI completely stops the burst access cycle and return to normal state. Burst access Go. 1: Set "1" to start a burst read or write access. 0: After the burst bytes being transferred matches the BACC_NO, the LBI will clear 7 BGO W1 this bit automatically, meaning the specified burst access has been completed. Also, after receiving "1" on BT bit, the LBI will also clear this bit during a burst access in progress. 272 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Status Register (SR, 0x0C) Bit Name Reset Value 7 SRDY 0 6 SRDY_COS 0 Bit Name Access 0 XR_FUL RO 1 XR_IC RO 2 XW_EMP RO 4:3 Reserved RO 5 BAC CR 6 SRDY_COS CR 7 SRDY RO 5 BAC 0 4 3 Reserved 00 2 XW_EMP 0 1 XR_IC 0 0 XR_FUL 0 Description XMRR registers Full flag. The external CPU read this bit to know whether XMRR register contain valid data written by the software on internal CPU. 1: Reading "1" indicates that the software on internal CPU has written data into internal SFR register XMRLR and XMRHR. Therefore, the XMRR has valid data from internal software. 0: This flag is cleared automatically after the external CPU reads XMRR register to retrieve data in it. XMRR Is Command flag. 1: Reading "1" indicates to external CPU that the data in XMRR is a command cycle. This bit is set when the software on internal CPU sets XR_IC bit (LSCR.0 in SFR). 0: This flag is cleared automatically after the external CPU reads XMRR register to retrieve data in it. XMWR registers Empty flag. The external CPU reads this bit to know whether the content of XMWR register has been retrieved by software on internal CPU. 1: Reading "1" indicates that the software on internal CPU has retrieved the data in SFR register XMWLR and XMWHR. Therefore, the external CPU can write new data to XMWR. 0: Indicates that the software on internal CPU has not retrieved the data in SFR register XMWLR and XMWHR. Burst data Access Complete flag. 1: When external CPU initiates a burst read or write cycle, after all the requested bytes have been transferred through LBI, this flag will report as "1" to indicate that the requested burst access is completed. 0: The requested burst access is in progress or the no burst access. System Ready has change of state. 1: Reading "1" indicates that the SRDY flag has change of state occurred (either from "0 to 1" or "1 to 0"). Reading "1" on this bit along with reading "1" on SRDY bit indicates that the software on internal CPU is transitioning from non-ready to ready state. Reading "1" on this bit along with reading "0" on SRDY bit indicates that the software on internal CPU is transitioning from ready to non-ready state. 0: No change of state occurred in SRDY flag. System Ready flag. This flag is controlled by software on internal CPU by setting LSA bit (LSAIER.7). 1: The software on internal CPU sets LSA bit to "1" to notify external CPU that this chip has completed initialization and is ready to communicate with the external CPU. The external CPU can now access this chip anytime. 0: Reading back "0" means that the software on internal CPU is still undergoing initialization steps. 273 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Interrupt Enable Register (IER, 0x0E) 7 6 5 Bit Reserved SRDY_COS_EN BAC_EN Name 0 0 0 Reset Value Bit Name 0 XRF_EN 4:1 Reserved 5 BAC_EN 6 SRDY_COS_E N 7 Reserved 4 3 2 Reserved 00 1 0 XRF_EN 0 Access Description R/W XMRR Full interrupt Enable. 1: Enable generating interrupt to external CPU by asserting LINT pin when the XR_FUL flag is set. 0: Disable interrupt. RO R/W Burst data Access Complete interrupt Enable. 1: Enable generating interrupt to external CPU by asserting LINT pin when the BAC flag is set. 0: Disable interrupt. R/W System Ready Change of State interrupt Enable. 1: Enable generating interrupt to external CPU by asserting LINT pin when the SRDY_COS flag is set. 0: Disable interrupt. RO 4.21.6 Local Bus Slave Mode SFR Register Detailed Description Following describes the SFR registers which are used by the software on internal 1T80390 CPU to support the access of Local Bus slave mode. Local Bus Slave mode Action and Interrupt Enable Register (LSAIER, 0xA1) Bit Name Reset Value 7 LSA 0 6 Reserved 0 5 BWC_EN 0 4 BRC_EN 0 3 2 Reserved 0 1 0 XWF_EN 0 Bit Name Access Description 0 XWF_EN R/W XMWLR & XMWHR register full interrupt Enable. 1: Enable generating interrupt on INT4 and being reflected in LB_INT bit (PISS1R.0) when the XW_FUL flag (LSSR.0) is set. 0: Disable interrupt. 3: Reserved RO 1 4 BRC_EN R/W Burst Read Complete interrupt Enable. 1: Enable generating interrupt on INT4 and being reflected in LB_INT bit (PISS1R.0) when the BRC flag (LSSR.4) is set. 0: Disable interrupt. 5 BWC_EN R/W Burst Write Complete interrupt Enable. 1: Enable generating interrupt on INT4 and being reflected in LB_INT bit (PISS1R.0) when the BWC flag (LSSR.5) is set. 0: Disable interrupt. 6 Reserved RO 7 LSA R/W Local Bus Start Action. 1: Indicate to external CPU that the software on internal CPU has finished initialization and is ready. 0: Indicate to external CPU that the software on internal CPU is not ready. 274 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Local Bus Slave mode Command Register (LSCR, 0xA2) Bit Name Reset Value 7 6 5 4 Reserved 000_0000 3 2 1 0 XR_IC 0 Bit Name 0 XR_IC Access Description W1 The content of XMRLR/XMRHR Is Command. 1: Software sets this bit prior to writing to XMRLR/XMRHR to notify the external CPU that the content in XMRR (or SFR register XMRLR/XMRHR) is served as the Command message. 0: This bit is cleared automatically after the external CPU reads the XMRR register to receive data from internal CPU. Note: The data exchange between the software on external CPU and the software on internal CPU can be in frame format which both agree on. For example, it can consist of Command phase and Data phase, and software can use this bit to indicate the data as being Command phase. 7:1 Reserved RO Local Bus Slave mode Status Register (LSSR, 0xA3) 7 6 Bit LB_MOD LB_W Name 0 0 Reset Value 5 BWC 0 4 BRC 0 3 2 1 Reserved XR_EMP XW_IC 0 0 0 0 XW_FUL 0 Bit Name Access Description 0 XW_FUL RO XMWLR and XMWHR register Full flag. The software on internal CPU reads this bit to know whether XMWLR and XMWHR registers contain valid data written by the external CPU. 1: In 8-bit bus width mode, reading "1" indicates that the external CPU has written data into XMWLR register. Therefore, the XMWLR has valid data from external CPU. This flag is cleared automatically after the software on internal CPU reads XMWLR register to retrieve the 8-bit data in it. In 16-bit bus width mode, reading "1" indicates that the external CPU has written data into both XMWLR and XMWHR registers. Therefore, both XMWLR and XMWHR registers have valid data from external CPU. This flag is cleared automatically only after the software on internal CPU reads both XMWLR and XMWHR registers to retrieve the 16-bit data in it. 0: The XMWLR and XMWHR registers are empty. 1 XW_IC RO XMWLR and XMWHR Is Command flag. 1: This flag notify the software on internal CPU the received data from XMWLR and XMWHR is command field. 0: In 8-bit bus width mode This flag is cleared automatically after the software on internal CPU reads XMWLR register to retrieve the 8-bit data in it. In 16-bit mode, this flag is cleared after the software on internal CPU reads both XMWLR and XMWHR registers to retrieve the 16-bit data in it. 2 XR_EMP RO XMRLR and XMRHR register Empty flag. The software on internal CPU reads this bit to know whether the content of XMRLR and XMRHR registers have been retrieved by the external CPU. 1: In 8-bit bus width mode, reading "1" indicates that the external CPU has retrieved the data in XMRLR register. Therefore, the XMRLR now can be written with new data. In 16-bit bus width mode, reading "1" indicates that the external CPU has retrieved that data in both XMRLR and XMRHR registers. Therefore, both XMRLR and XMRHR registers now can be written with new data. 0: The XMRLR and XMRHR registers are still full. 275 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 3 Reserved 4 BRC RO CR 5 BWC CR 6 LB_W RO 7 LB_MO D RO Burst Read Complete. 1: The local bus interface has completed an external CPU's burst read access, the previous occupied xDATA memory space may now be released. 0: The burst read access is still in progress or no burst read access. Burst Write Complete. 1: The local bus interface has completed an external CPU's burst write access, the data is ready in xDATA memory. 0: The burst write access is still in progress or no burst write access. Local bus width indication. This bit reflects the bus width setting in I2C EEPROM. 1: 16 bits bus width. 0: 8 bits bus width. Local bus mode indication. This bit reflects the LB_MOD pin setting. 1: Local bus is operating in slave mode. 0: Local bus is operating in master mode. External Master Write-read Low Register (XMWLR, 0xA4) Bit Name Reset Value 7 6 5 4 3 XMW_DATA [7:0] 00 2 1 0 Bit Name Access Description 7:0 XMW_DATA RO External Master Write-readable Data Register [7:0]. This register is used for the [7:0] external CPU to send data to the software on internal CPU in single access. In 8-bit bus width mode, the external CPU writing XMWR register will cause the XW_FUL flag (LSSR.0) to be set to "1". External Master Write-read High Register (XMWHR, 0xA5) Bit Name Reset Value 7 6 5 4 3 XMW_DATA [15:8] 00 2 1 0 Bit Name Access Description 7:0 XMW_DATA RO External Master Write-readable Data Register [15:8]. This register is used for [15:8] external CPU to send data to the software on internal CPU in single access. Only valid in 16-bit bus width mode. In 16-bit bus width mode, the external CPU writing XMWR register will cause the XW_FUL flag (LSSR.0) to be set to "1". External Master Read-only Low Register (XMRLR, 0xA6) Bit Name Reset Value Bit Name 7:0 XMR_DAT A [7:0] 7 6 5 4 3 XMR_DATA [7:0] 00 2 1 0 Access Description R/W External Master Read-only Data Register [7:0]. This is used for the software on internal CPU to send data to external CPU in single access. In 8-bit bus width mode, the external CPU reading XMRR register will cause the XR_EMP flag (LSSR.2) to be set to "1". 276 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY External Master Read-only High Register (XMRHR, 0xA7) 7 Bit Name Reset Value Bit Name 7:0 XMR_DATA [15:8] 6 5 4 3 XMR_DATA [15:8] 00 2 1 0 Access Description R/W External Master Read-only Data Register [15:8]. This is used for internal CPU to send data to external CPU in single access. Only valid in 16-bit bus width mode. In 16-bit bus width mode, the external CPU reading XMRR register will cause the XR_EMP flag (LSSR.2) to be set to "1". Figure 141 below shows the register mapping relationship between the External CPU Registers and AX11015 SFR Registers in Local Bus slave mode. The software driver of Local Bus slave mode is required to coordinate with the single access, which normally can be used to pass high-level messages between the external system CPU and the application software on internal CPU. Figure 141: Register Mapping Between External CPU Register and Internal SFR Register in Local Bus Slave Mode 277 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Internal CPU's Operation in Local Bus Slave Mode In Local Bus slave mode, after the software on internal CPU finishes the needed initialization steps, it needs to set the LSA flag (LSAIER.7) to notify the external CPU that it's online and ready. This flag will be reflected in SRDY bit (SR.7) of External CPU Register. In Local Bus slave mode, the software on internal CPU and the software on external CPU can use two unidirectional data ports (16 bits each) to exchange control messages with each other. The first data port, XMWLR, XMWHR register is used for the software on internal CPU to receive data sent by external CPU. The LSSR register provides the status of this data port. The second data port, XMRLR, XMRHR register is used for the software on internal CPU to send data to the external CPU. The LSCR register provides the command for this data port. Followings are two example SFR programming sequences for receiving data in XMWLR, XMWHR register from external CPU. The example 1 shows that the XW_FUL and XW_IC bits in LSSR being read as "1" which means the received data in XMWLR and XWMHR (local bus is 16-bits mode) as a command cycle. The example 2 shows that only XW_FUL bit being read as "1" in LSSR which means the received data in XMWLR and XWMHR as data cycle. Example 1: Example 2: PISS1R --- PISS1R LSSR XMWLR (XMWHR) XW_FUL Followings are two example SFR programming sequences for sending data in XMRLR, XMRHR register to external CPU. The software on internal CPU first has to check whether the data port is empty or not, making sure that the previous data has been retrieved by the external CPU. The example 3 shows that the software on internal CPU is sending out a command cycle to the external CPU by setting XR_IC bit in LSCR, while the example 4 shows that the software on internal CPU is sending out a data cycle to the external CPU. Example 3: Example 4: In Local Bus slave mode, external CPU itself controls its access to the internal xDATA memory, and the LBI will not intervene this process. The external CPU can perform burst read or burst write access from or to internal xDATA memory, and the LBI will simply help generate the DMA request to DMA engine. It's the software driver on internal CPU to maintain a predefined data buffer structure in xDATA memory that allows the external system CPU to move data in or out of xDATA memory without corrupting other application data buffer. 278 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY External CPU's Operation Procedure in LBI Slave Mode In Local Bus slave mode, the software on internal CPU is still operating as standalone mode. Whenever needed, the software on external CPU can exchange control messages with the software on internal CPU, based on some predefined high-level messages between the two. There are two unidirectional data ports (16-bit each), namely, XMWR and XMRR, for serving this purpose. The access provided by XMWR and XMRR is always single access at a time. For the purpose of following description, we refer it as "Control Pipe" access. Note that the format of the high-level messages are opened and reserved to software. Also, whenever the software on external CPU needs to write/read bulk data to/from the internal xDATA memory region, it can do so by initiating a burst write or read transfer to LBI, which then activates the DMA request for this. Note that, in Local Bus slave mode, this type of burst transfer is always initiated by the external CPU only and the burst data is always accessed through the BDR register. The software on the two CPU should predefine some data structure that both sides agree on inside xDATA memory for doing such bulk data transaction. For the purpose of following description, we refer it as "Data Pipe" access. During initialization, the external CPU should read the SRDY flag (SR.7) to learn that the software on internal CPU is done with initialization and ready before it can send any Control Pipe access or Data Pipe access commands. Following are two examples of write access sequence for "Control Pipe": Example 1: Software on external CPU sends out a command message to the software on internal CPU 1. Software on external CPU first checks XW_EMP bit in SR register to confirm that XMWR register is empty and can be written. It then sets XW_IC bit (CR.4) and writes desired command bytes to XMWR register. The LBI will automatically set XW_IC and XW_FUL bits (SFR register LSSR.1 and LSSR.0). 2. Software on internal CPU may receive interrupt or poll LSSR register to learn that XMWLR and XMWHR registers have valid data in it. It then can read XMWLR and XMWHR to retrieve the data. After it reads XMWLR and XMWHR registers, the LBI will automatically clear the XW_IC and XW_FUL bits (SFR register LSSR.1 and LSSR.0) and set the XW_EMP bit (SR.2 on External CPU Register). Example 2: Software on external CPU sends out a data message to the software on internal CPU 1. Software on external CPU first checks XW_EMP bit in SR register to confirm that XMWR register is empty and can be written. It then writes desired data bytes to XMWR register. The LBI will automatically set XW_FUL bit (SFR register LSSR.0). 2. Software on internal CPU may receive interrupt or poll LSSR register to learn that XMWLR and XMWHR registers have valid data in it. It then can read XMWLR and XMWHR to retrieve the data. After it reads XMWLR and XMWHR registers, the LBI will automatically clear the XW_FUL bit (SFR register LSSR.0) and set the XW_EMP bit (SR.2 on External CPU Register). 279 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Following are two examples of read access sequence for "Control Pipe": Example 1: Software on external CPU receives a command message from the software on internal CPU 1. Software on internal CPU first checks XR_EMP bit (SFR register LSSR.2) to confirm that XMRLR and XMRHR registers are empty and can be written. Then it sets XR_IC bit (LSCR.0) and puts desired command bytes in XMRLR and XMRHR registers. After that, the LBI will automatically sets XR_FUL and XR_IC flag (SR.0 and SR.1 on External CPU Register) to notify the external CPU. 2. Software on external CPU may receive interrupt or poll SR register to learn that XMRR has valid data. It then reads XMRR to retrieve data in it. After that, the LBI will automatically clear XR_FUL and XR_IC flag (SR.0 and SR.1 on External CPU Register) and set XR_EMP bit (SFR register LSSR.2). Example 2: Software on external CPU receives a data message from the software on internal CPU 1. Software on internal CPU first checks XR_EMP bit (SFR register LSSR.2) to confirm that XMRLR and XMRHR registers are empty and can be written. Then it puts desired data bytes in XMRLR and XMRHR registers. After that, the LBI will automatically sets XR_FUL flag (SR.0 on External CPU Register) to notify the external CPU. 2. Software on external CPU may receive interrupt or poll SR register to learn that XMRR has valid data. It then reads XMRR to retrieve data in it. After that, the LBI will automatically clear XR_FUL flag (SR.0 and SR.1 on External CPU Register) and set XR_EMP flag (SFR register LSSR.2). Following is an example of write access sequence for "Data Pipe": 1. First the software on external CPU sets target start address of internal xDATA memory to BALR, BAMR, and BAHR (or BALWR and BAHWR in 16-bit bus width mode), and then issues a burst write command indicating number of burst bytes to CR register. 2. Now software on external CPU can write desired data into BDR continuously until done writing specified burst data bytes. While doing this, the LBI starts moving the data in BDR to the 32-bytes FIFO, and when the FIFO is almost full, it will send DMA request to move data from FIFO to the internal xDATA memory. If the FIFO experiences full condition some time after the external CPU is writing to BDR, the LBI may hold the ready signal, LRDY, to the external CPU to non-ready state. Note that this situation should be very unlikely, given that the FIFO to xDATA memory transfer is via DMA mode. After all burst write data have been written to BDR by the external CPU, the LBI will send one last DMA request internally to move the remaining data in FIFO to internal xDATA memory. 3. After the last DMA transfer is finished, the LBI can generate an interrupt to notify the software on external CPU and report in SR register. Or the external CPU can poll SR register to learn that the requested burst write access has been completed 280 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Following is an example of read access sequence for "Data Pipe": 1. First the software on external CPU sets source start address of internal xDATA memory to BALR, BAMR, and BAHR (or BALWR and BAHWR in 16-bit bus width mode), and then issues a burst read command indicating number of burst bytes to CR register. 2. Internally, the LBI will issue DMA request to move data from internal xDATA memory to the 32-byte FIFO. After the first byte is filled into the FIFO, the LBI will set BRR flag (CR.5). Software on external CPU can poll this bit to know that the burst read data is ready in BDR register and starts to read data from BDR continuously. After all burst read data have been moved from xDATA memory to FIFO, the LBI will stop the DMA request. However, the software on external CPU can continue reading data in FIFO from BDR until the FIFO is completely empty. 3. After CPU reads the last byte of burst data from BDR, the LBI can generate an interrupt to notify the software on external CPU and report in SR register. Or the external CPU can poll SR register to learn that the requested burst read access has been completed. 281 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 4.21.7 Digiport The Digiport mode of LBI is specially designed to be able to receive compressed streaming video data from STMicroelectronics STv0676 (in Digiport parallel mode) or STv0684 (in Digiport SPI mode) chips directly into internal xDATA memory of 1T 80390 CPU via DMA transfer. When used, the LBI is basically acting as master mode. The main features of Digiport mode are listed below, z When working with STM STv0676 in Digiport parallel mode, after software initiates the DMA command, it can output clock on LALE pin and receive 8-bit streaming data via LDA [7:0] pins and the ready indication from LRDY pin. z When working with STM STv0684 in Digiport SPI mode, after software initiates the DMA command, it can output ready indication on LRDY pin and then start receiving 1-bit streaming data via LDA0. The clock is fed to LALE pin at 24Mhz. The format of Digiport SPI is similar to the SPI Mode 3 (CPHA=1, CPOL=1) z Support automatic SOI (Start of Image, 0xFFD8) and EOI (End of Image, 0xFFD9) bytes detection in receive Motion-JPEG streaming data for both Digiport parallel mode and Digiport SPI mode z Support transparent mode for receiving audio and video mixed streaming in Digiport SPI mode z Support programmable packet size for packetizing the receive Motion JPEG streaming data z Support up to 256-bytes burst read access in each DMA command 4.21.8 Digiport Mode SFR Register Detailed Description Local Bus Mode Setup Register (LMSR, 0xA1) 7 Bit LB_EN Name 0 Reset Value Bit Name 0 AC_INT_EN 4:1 Reserved 5 DGP_EN 6 SDMA_EN 7 LB_EN 6 5 SDMA_EN DGP_EN 0 0 4 3 2 Reserved 0000 1 Access 0 AC_INT_EN 0 Description Access Complete Interrupt Enable. 1: Enable generating interrupt on INT4 and being reflected in LB_INT bit R/W (PISS1R.0) when the AC flag (LSR.0) is set. 0: Disable interrupt. R/W Write 0000 to this bit. Digiport mode Enable. R/W 1: Enable Digiport mode. 0: Disable Digiport mode. Slave-DMA mode Enable (for LCS0_N only). R/W 1: Enable slave request based DMA mode. 0: Disable slave request based DMA mode. Set to "0" in Digiport mode. Local Bus mode Enable. R/W 1: Enable local bus mode. 0: Disable local bus mode. Set to "0" in Digiport mode. 282 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Local Bus Command Register (LCR, 0xA2) 7 GO 0 Bit Name Reset value Bit Name Access 2:0 BUR_NO R/W 3 SOI R/W 4 SOP R/W 6:5 RDY_CY 7 R/W GO R/W1 6 5 RDY_CY 00 4 SOP 0 3 SOI 0 2 1 BUR_NO 00 0 Description Number of Burst bytes. Set to "111" when enabling Digiport mode in DGP_EN bit (LMSR.5). The burst read data through DMA transfer is fixed to 256 bytes unless the EOP or EOI condition is reached prior to 256 bytes. When Digiport mode is enabled in DGP_EN bit, this bit is redefined as "fetch Start of Image (SOI)" to request LBI hardware to retrieve a brand new Motion JPEG image data starting with SOI marker, 0xFFD8, from the external Motion JPEG chip. 1: To fetch a new image data starting with SOI marker, 0xFFD8. 0: To continue fetching what's available in the streaming data. When Digiport mode is enabled in DGP_EN bit, this bit is redefined as "fetch for Start of Packet (SOP). 1: Setting this bit to "1" indicates to LBI hardware to retrieve Motion JPEG image data for a new packet with the number of bytes being specified in LDHR and LDLR registers. 0: Setting this bit to "0" indicates to LBI hardware to continue retrieving Motion JPEG image data for current packet. Write 000 to these bits. When Digiport mode is enabled in DGP_EN bit, this bit is redefined as "DMA Go". 1: Setting this bit to "1" to indicate to the LBI hardware to start receiving streaming data from external Motion JPEG chip via DMA transfer. 0: This bit is automatically cleared by LBI once the requested access is finished. Local Bus Status Register (LSR, 0xA3) Bit Name Reset value 7 LB_MOD 0 Bit Name Access 0 AC CR 1 SYNC_BU S RO 2 Reserved 3 SOI CR 4 EOI CR 5 EOP CR 6 LB_W RO 6 LB_W 0 5 EOP 0 4 EOI 0 3 SOI 0 2 Reserved 1 SYNC_BUS 00 0 AC 0 Description Access Complete. Normally after software issues the GO bit (LCR.7) for receiving streaming data through DMA transfer, software can check this bit to know that the requested access has been completed or not. 1: Reading "1" indicates that the LBI has finished the requested command. 0: The requested access is in progress or LBI is in idle mode. Synchronous local bus style. This bit reflects the SYNC_BUS pin setting. 1: Synchronous local bus. 0: Asynchronous local bus. Start of Image masker, 0xFFD8, this flag only use by SPI mode. 1: Reading "1" indicates that the SOI marker has been received in the streaming data. In Digiport SPI mode, LBI hardware will negate the LRDY pin when the SOI masker is found in this burst access (32 bytes). This allows LBI and external STv0684 chip to synchronize the 32-bytes burst access. After that, software should re-initiate a new burst access command. End of Image marker, 0xFFD9, is detected. 1: Reading "1" indicates that the EOI marker has been received in the streaming data. End of Packet is detected. 1: Reading "1"indicates that the specified number of bytes per packet has been reached during packetizing the Motion JPEG streaming data. Local bus width indication. This bit reflects the bus width setting in I2C EEPROM. 1: 16 bits bus width. 0: 8 bits bus width. 283 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 7 LB_MOD RO Local bus mode indication. This bit reflects the LB_MOD pin setting. 1: Local bus is operating in slave mode. 0: Local bus is operating in master mode. Local Bus Data Low Register (LDLR, 0xA9) Bit Name Reset value 7 6 5 4 3 DATA[7:0] 00 2 1 0 Bit Name Access Description 7: DATA R/W When Digiport mode is enabled in DGP_EN bit, software reads the LDLR to report the actual 0 [7:0] byte count of the last DMA transfer. This is useful to indicate to software the actual byte count of the last DMA transfer when the EOP or EOI bytes are encountered in the received steaming data with EOP flag or EOI flag (LSR.5 or LSR.4) being set to `1". Local Bus Data High Register (LDHR, 0xAA) Bit Name Reset value 7 6 5 4 3 DATA[15:8] 00 2 1 0 Bit Name Access Description 7:0 DATA R/W When Digiport mode is enabled in DGP_EN bit, software writes to LDHR and LDLR [15:8] registers to specify the number of bytes for each packet for packetizing the Motion JPEG streaming data. For example, if each packet size is 1400 bytes, then software writes LDHR = 0x05, LDLR = 0x78. Note: When software reads LDLR, it shall report the actual byte count of the last DMA transfer, not the value being written to LDLR. Local Bus DMA Address Low Register (DMALR, 0xAB) Bit Name Reset Value 7 Bit Name 7: LB_DMA_ADDR[7:0] 0 6 Access R/W 5 4 3 2 LB_DMA_ADDR[7:0] 00 1 0 Description Local Bus DMA Address [7:0] for burst write to xDATA memory. Local Bus DMA Address Medium Register (DMAMR, 0xAC) Bit Name Reset Value 7 Bit Name 7: LB_DMA_ADDR[15:8] 0 6 Access R/W 5 4 3 2 LB_DMA_ADDR[15:8] 00 1 0 Description Local Bus DMA Address [15:8] for burst write to xDATA memory. 284 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Local Bus DMA Address High Register (DMAHR, 0xAD) Bit Name Reset Value Bit 7 6 Reserved 5 4 3 2 1 LB_DMA_ADDR[20:16] 0 00 Name Access 4: LB_DMA_ADD 0 R [20:16] Description LB DMA Address [20:16] for burst write to xDATA memory. In Digiport mode, LB_DMA_ADDR [20:0] is used to indicate the target start R/W address of xDATA memory for writing received streaming data. The DMA byte count is determined by the BUR_NO in LCR register. 7: 5 Example Programming Procedure in Digiport Mode An example Motion JPEG image data is as shown in Figure 142, this shows that the image data is being packetized into (N-1) packets of 1400 bytes each and the last packet with 200 bytes. SOP SOI FFD8 EOP Packet #1 = 1400 bytes SOP Packet #2 = 1400 bytes EOP SOP EOP SOP Packet #N = 200 bytes FFD9 Note: SOI: Start of Image = 0xFFD8 EOI: End of Image = 0xFFD9 SOP: Start of Packet EOP: End of Packet EOI EOP Figure 142: Example Motion JPEG Image Data 285 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Example 1: Digiport Parallel Mode (with STv0676) To receive above image data from the external Motion JPEG chip STv0676 via DMA transfer, software should configure LBI to Digiport mode in DGP_EN bit (LMSR.5) first and clear DG_SPI bit (in I2C EEPROM offset 0x13) to 0. 1. Software writes the required number of bytes for each packet in LDHR, LDLR, writes the target start address of internal xDATA memory in DMALR, DMAMR, DMAHR, and then sets SOI and/or SOP bit to LCR along with GO bit. 2. The LBI generates the Digiport clock and receive Digiport streaming data from the external Motion JPEG chip. The LBI starts filling the 32-bytes FIFO with streaming data. When the FIFO is almost full, the LBI sends DMA request internally to move data from FIFO to xDATA memory. This process continues to receive up to 256 bytes of streaming data for each software command. 3. After 256 bytes of streaming data have been received into FIFO or the EOP or EOI bytes have been detected in the received streaming data, the LBI will stop generating Digiport clock. However, internally the LBI will send one more DMA request to move the remaining data in FIFO to xDATA memory. 4. Software can wait for interrupt by enabling AC_INT_EN bit (LMSR.0) or poll LSR register to know if the requested access has been completed. Below shows example SFR programming sequence for this Digiport receive mode. LDHR LDLR DMALR DMAMR DMAHR LSR PISS1R LCR Note that every software initiated burst read command can allow receiving up to 256 bytes of data from the external Motion JPEG chip, so for a packet size of 1400 bytes, it may take several software burst read commands to complete. Below shows example programming sequence for receiving the 1400 bytes of streaming data in the packet #1 in Figure 142. DMALR DMAMR DMAHR LDHR = 0x05 LDLR = 0x78 LCR[SOI] = 1 LCR[SOP] = 1 LCR[GO] = 1 Write LSR[AC] = 1 LSR[EOI] = 0 LSR[EOP] = 0 DMALR DMAMR DMAHR LCR[SOI] = 0 LCR[SOP] = 0 LCR[GO] = 1 Write Read 256 bytes LSR[AC] = 1 LSR[EOI] = 0 LSR[EOP] = 0 Read 256 bytes DMALR DMAMR DMAHR LCR[SOI] = 0 LCR[SOP] = 0 LCR[GO] = 1 Write LSR[AC] = 1 LSR[EOI] = 0 LSR[EOP] = 1 LDLR = 0x78 Read 120 bytes 286 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Example 2: Digiport SPI Mode (with STv0684) To receive above image data from the external Motion JPEG chip STv0684 via DMA transfer, software should configure LBI to Digiport mode in DGP_EN bit (LMSR.5) first and set DG_SPI bit (in I2C EEPROM offset 0x13) to 1. 1. Software writes the required number of bytes for each packet in LDHR, LDLR, writes the target start address of internal xDATA memory in DMALR, DMAMR, DMAHR, and then sets SOI bit to LCR along with GO bit. 2. Normally upon enabling DGP_EN bit in Digiport SPI mode, the LBI will enable LRDY pin to allow external STv0684 chip to send out streaming data continuously. Whenever software issues fetch-SOI command, the LBI hardware will start detecting the SOI marker in the received streaming data. Once SOI marker is found, the burst read access is terminated automatically by negating the LRDY pin. This will temporarily halt the streaming data from STv0684. 3. Software then reads the LDLR to identify the number of bytes being received since SOI and adjusts the offset in target start address of xDATA in DMALR to accommodate those odd bytes received since SOI. The LBI will wait for the software to re-initiate a new burst read access with 256 bytes. 4. The LBI starts filling the 32-bytes FIFO with streaming data. When the FIFO is almost full, the LBI sends DMA request internally to move data from FIFO to xDATA memory. This process continues to receive up to 256 bytes of streaming data for each software command. 5. After 256 bytes of streaming data have been received into FIFO or the EOI bytes have been detected in the received streaming data, the LBI will enable LRDY pin to allow streaming data to come out continuously again. However, internally the LBI will send one more DMA request to move the remaining data in FIFO to xDATA memory. 6. Software can wait for interrupt by enabling AC_INT_EN bit (LMSR.0) or poll LSR register to know if the requested access has been completed. DMALR DMAMR DMAHR LDHR = 0x05 LDLR = 0x78 LCR[SOI] = 1 LCR[SOP] = 1 LCR[GO] = 1 Write LSR[AC] = 1 LSR[EOI] = 0 LSR[EOP] = 0 DMALR DMAMR DMAHR LCR[SOI] = 0 LCR[SOP] = 0 LCR[GO] = 1 Write Read 256 bytes LSR[AC] = 1 LSR[EOI] = 0 LSR[EOP] = 0 Read 256 bytes DMALR DMAMR DMAHR LCR[SOI] = 0 LCR[SOP] = 0 LCR[GO] = 1 Write LSR[AC] = 1 LSR[EOI] = 0 LSR[EOP] = 1 LDLR = 0x78 Read 120 bytes 287 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 5.0 Electrical Specifications 5.1 DC Characteristics 5.1.1 Absolute Maximum Ratings Symbol VCC18, VCCK VCC3R, VCCIO VCC18A VCC3A VIN18 VIN3 TSTG I IN I OUT Parameter Output voltage of on-chip voltage regulator or digital core power supply. Rating - 0.3 to 2.16 Unit V Power supply of on-chip voltage regulator or 3.3V I/O. - 0.3 to 4.0 V Analog power supply for oscillator, PLL, etc. Analog power supply for bandgap. Input voltage of 1.8V I/O. Input voltage of 3.3V I/O. - 0.3 to 2.16 - 0.3 to 3.8 - 0.3 to 2.16 - 0.3 to 4.0 V V V V Input voltage of 3.3V I/O with 5V tolerant. - 0.3 to 5.8 V Storage temperature. DC input current. Output short circuit current. - 40 to 150 20 20 mA mA Note: Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation should be restricted in the recommended operating condition section of this datasheet. Exposure to absolute maximum rating condition for extended periods may affect device reliability. 5.1.2 Recommended Operating Condition Symbol VCC3R VCCIO VCC3A VCC18 VCCK VCC18A VIN18 VIN3 Tj Ta Parameter Power supply of on-chip voltage regulator. Power supply of 3.3V I/O. Analog power supply for bandgap. Output voltage of on-chip voltage regulator. Digital core power supply. Analog power supply for oscillator, PLL, etc. Input voltage of 1.8 V I/O. Input voltage of 3.3 V I/O. Input voltage of 3.3 V I/O with 5 V tolerance. AX11015 LF operating junction temperature. AX11015 LI operating junction temperature. AX11015 LF operating ambient temperature. AX11015 LI operating ambient temperature. Min 3.0 3.0 3.0 1.62 1.62 1.62 0 0 0 0 -40 0 -40 Typ 3.3 3.3 3.3 1.8 1.8 1.8 1.8 3.3 3.3 25 25 - Max 3.6 3.6 3.6 1.98 1.98 1.98 1.98 3.6 5.25 125 125 70 85 288 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights Unit V V V V V V V V V AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 5.1.3 Leakage Current and Capacitance Symbol IIN IOZ CIN Parameter Input current . Tri-state leakage current . Input capacitance. Condition No pull-up or pull-down Min -10 -10 - Typ 1 1 2.2 Max 10 10 - Unit A A pF COUT Output capacitance. - 2.2 - pF CBID Bi-directional buffer capacitance. - 2.2 - pF Note: The capacitance listed above does not include pad capacitance and package capacitance. One can estimate pin capacitance by adding a pad capacitance of about 0.5pF and the package capacitance. 5.1.4 DC Characteristics of 3.3V I/O Pins Symbol VCCIO Tj Vil Vih Vt VtVt+ Vol Voh Rpu Rpd Iin Ioz Parameter Power supply of 3.3V I/O. Junction temperature. Input low voltage. Input high voltage. Switching threshold. Schmitt trigger negative going threshold voltage. Schmitt trigger positive going threshold voltage Output low voltage. Output high voltage. Input pull-up resistance. Input pull-down resistance. Input leakage current. Input leakage current with pull-up resistance. Input leakage current with pull-down resistance. Tri-state output leakage current. Condition 3.3V I/O LVTTL Min 3.0 -40 2.0 Max 3.6 125 0.8 - 0.8 Typ 3.3 25 1.5 1.1 - Unit V V V V V - 1.6 2.0 V 2.4 40 40 -10 -15 15 75 75 1 45 45 0.4 190 190 10 -85 85 V V K K A A A -10 1 10 A Min 3.0 -40 2.0 Max 3.6 125 0.8 - 0.8 Typ 3.3 25 1.5 1.1 - Unit V V V V V - 1.6 2.0 V 2.4 40 40 -15 75 75 5 -45 0.4 190 190 -85 V V K K A A LVTTL Iol = 4~8mA Ioh = -4~-8mA Vin = 0 Vin = VCCIO Vin = VCCIO or 0 Vin = 0 Vin = VCCIO 5.1.5 DC Characteristics of 3.3V with 5V Tolerant I/O Pins Symbol VCCIO Tj Vil Vih Vt VtVt+ Vol Voh Rpu Rpd Iin Parameter Condition Power supply of 3.3V I/O. 3.3V I/O Junction temperature. Input low voltage. LVTTL Input high voltage. Switching threshold. Schmitt trigger negative going threshold LVTTL voltage. Schmitt trigger positive going threshold voltage Output low voltage. Iol = 4~8mA Output high voltage. Ioh = -4~-8mA Input pull-up resistance. Vin = 0 Input pull-down resistance. Vin = VCCIO Input leakage current. Vin = 5.5V or 0 Input leakage current with pull-up resistance. Vin = 0 289 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Ioz Input leakage current with resistance Tri-state output leakage current. pull-down Vin = VCCIO Vin = 5.5V or 0 15 45 85 A - 10 - A 5.1.6 DC Characteristics of Voltage Regulator Symbol VCC3R Tj Iload VCC18 Description Condition Power supply of on-chip voltage regulator. Operating junction temperature. Driving current. Normal operation, RSM bit = 0 (SFR register PCON.3) Driving current. Standby mode enabled, RSM bit = 1 (PCON.3) Output voltage of on-chip VCC3R = 3.3V voltage regulator. Dropout voltage. VCC18 = -1%, Iload = 10mA Line regulation. VCC3R = 3.3V, Iload = 50mA Min 3.0 VCC3R = 3.3V, 1mA Iload 240mA VCC3R = 3.3V,-40 Tj 125 VCC3R = 3.3V, RSM bit = 1 (PCON.3) VCC3R = 3.3V, RSM bit = 0 (SFR register PCON.3) Quiescent current at 125 VCC3R = 3.3V, RSM bit = 1 (PCON.3) . VCC3R = 3.3V, RSM bit = 0 (SFR register PCON.3) Output external capacitor. Allowable effective series resistance of external capacitor. Vdrop VCC18 (VCC3R x VCC18) Load regulation. VCC18 (Iload x VCC18) Temperature coefficient. VCC18 Tj Iq_25 Quiescent current at 25 . Iq_125 Cout ESR Typ Max Unit 3.3 3.6 V -40 25 125 - - 240 mA - - 30 mA 1.71 1.8 1.89 V - 0.1 0.2 0.2 0.4 V %/V - 0.02 0.05 %/mA - +/-0.2 +/-0.5 mV/ 70 100 A - 100 125 A - 85 115 A - 125 170 A 0.1 - 1 0.5 1 F 290 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 5.2 Power Consumption Symbol I3.3V JC JA Description System Clock Condition Min Typ Max Unit CPU full speed, Ethernet 10Mbps full duplex CPU full speed, Ethernet 100Mbps full duplex CPU in PMM, Ethernet 10Mbps full duplex (Ethernet PHY not powered down) CPU in PMM, Ethernet 100Mbps full duplex (Ethernet PHY not powered down) CPU in PMM, Ethernet PHY powered down 25 Mhz CPU in STOP, Ethernet 10M full duplex mode (Ethernet PHY not powered down and OSC/PLL still running) CPU in STOP, Ethernet 100M full duplex mode (Ethernet PHY not powered down and OSC/PLL still running) CPU in STOP, Ethernet PHY powered down (OSC/PLL still running) CPU in STOP, OSC/PLL stopped (TOFFOP of I2C EEPROM offset 0x01 = 1) CPU full speed, Ethernet 10Mbps full duplex CPU full speed, Ethernet 100Mbps full duplex CPU in PMM, Ethernet 10Mbps full duplex (Ethernet PHY not powered down) Total current of 3.3V CPU in PMM, Ethernet 100Mbps full duplex (Ethernet PHY power supply including not powered down) VCCIO, VCC3A, and CPU in PMM, Ethernet PHY powered down VCC3R. 50 Mhz CPU in STOP, Ethernet 10M full duplex mode (Ethernet PHY not powered down and OSC/PLL still running) Note VCC3R includes CPU in STOP, Ethernet 100M full duplex mode (Ethernet VCC18, VCCK, and PHY not powered down and OSC/PLL still running) VCC18A CPU in STOP, Ethernet PHY powered down (OSC/PLL still running) CPU in STOP, OSC/PLL stopped (TOFFOP of I2C EEPROM offset 0x01 = 1) CPU full speed, Ethernet 10Mbps full duplex CPU full speed, Ethernet 100Mbps full duplex CPU in PMM, Ethernet 10Mbps full duplex (Ethernet PHY not powered down) CPU in PMM, Ethernet 100Mbps full duplex (Ethernet PHY not powered down) 100 CPU in PMM, Ethernet PHY powered down Mhz CPU in STOP, Ethernet 10M full duplex mode (Ethernet PHY not powered down and OSC/PLL still running) CPU in STOP, Ethernet 100M full duplex mode (Ethernet PHY not powered down and OSC/PLL still running) CPU in STOP, Ethernet PHY powered down (OSC/PLL still running) CPU in STOP, OSC/PLL stopped (TOFFOP of I2C EEPROM offset 0x01 = 1) - 166 177 139.3 - mA - 147.7 - mA - 21.6 138.8 - mA - 146.8 - mA - 21.3 - mA - 0.46 - mA - 188 197 139.7 - mA - 148.8 - mA - 22.1 139 - mA - 147.3 - mA - 21.5 - mA - 0.52 - mA - 227 235 140.3 - mA mA - 149.1 - mA - 22.7 139.2 - mA - 147.3 - mA - 21.7 - mA - 0.59 - mA Thermal resistance of junction to case Thermal resistance of junction to ambient - 9.7 - - 45.0 - C/ W C/ W Still air 291 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights mA mA mA mA mA mA mA mA AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 5.3 Power-up Sequence At power-up, AX11015 requires the VCC3R/VCCIO/VCC3A power supply to rise to nominal operating voltage within Trise3 and the VCCK/VCC18A power supply to rise to nominal operating voltage within Trise2. Trise3 3.3V VCC3R/VCCIO/VCC3A 0V Tdelay32 Trise2 1.8V VCCK/VCC18A 0V Trst See Note below RST_N Tclk XTL25P/XTL25N Symbol Trise3 Trise2 Tdelay32 Tclk Trst Parameter 3.3V power supply rise time 1.8V power supply rise time 3.3V rise to 1.8V rise time delay 25Mhz crystal oscillator start-up time RST_N low level interval Condition From 0V to 3.3V From 0V to 1.8V From VCC18A = 1.8V to first clock transition of XTL25P or XTL25N From VCCK = 1.8V to RST_N going high Min 1 -5 - Typ 1 Max 10 10 5 - Unit ms ms ms ms 4 - - ms Note: After RST_N input pin is negated during power-on, the internal I2C boot loader may start loading I2C EEPROM automatically, upon enabled. User should avoid generating 2nd reset pulse to RST_N pin of AX11015 because it will cause the I2C boot loader to be reset again during the process of loading I2C EEPROM configuration parameter. This may cause the I2C EEPROM itself to remain in the "read state", which it may not respond to AX11015's later I2C commands properly, because the I2C EEPROM normally does not have reset pin to reset it while the AX11015 is being reset again and restarting a new I2C command. Figure 143: Power-up Sequence Timing Diagram and Table 292 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 5.4 AC Timing Characteristics 5.4.1 Clock Timing XTL25P TP_XTL25P TL_XTL25P TH_XTL25P VIH VIL TR_XTL25P Symbol TP XTL25P TH XTL25P TL XTL25P TR XTL25P TF XTL25P TF_XTL25P Parameter Condition XTL25P reference frequency XTL25P clock duty cycle XTL25P clock cycle time XTL25P clock high time XTL25P clock low time XTL25P rise time VIL (max) to VIH (min) XTL25P fall time VIH (min) to VIL (max) Min 25-0.005% 40 - Typ 25 50 40 20 20 - Max Unit 25+0.005% Mhz 60 % ns ns ns 1.0 ns 1.0 ns Figure 144: XTL25P Clock Timing Diagram and Table LB_CLK TP_LB_CLK TL_LB_CLK TH_LB_CLK VIH VIL TR_LB_CLK Symbol TP LB CLK TH LB CLK TL LB CLK TR LB CLK TF LB CLK TF_LB_CLK Parameter LB_CLK clock cycle time LB_CLK clock high time LB_CLK clock low time LB_CLK rise time LB_CLK fall time Condition VIL (max) to VIH (min) VIH (min) to VIL (max) Min 20 10 10 - Typ - Figure 145: LB_CLK Clock Timing Diagram and Table 293 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights Max 40 20 20 1.0 1.0 Unit ns ns ns ns ns AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 5.4.2 External Memory Interface Timing XADDR[20:0] Taddr_su Taddr_hd Taddr_su Ta dd r_h d XROMCE1_N Tp rgwr Taddr_su Tprgwr_hd XPRGWR_N Tprgrd Taddr_su XPRGRD_N Twrdata_su Trddata_hd Twrdata_hd XDATA[7:0] Symbol Taddr_su Taddr_hd Tprgrd Trddata_hd Tprgwr Tprgwr_hd Twrdata_su Twrdata_hd Description Address setup time before XROMCE1_N, XPRGRD_N, or XPRGWR_N activation. Address hold time after XROMCE1_N negation. XPRGRD_N activation width. Read data hold time after XROMCE1_N or XPRGRD_N negation. XPRGWR_N activation width. XPRGWR_N negation to XROMCE1_N negation time. Write data setup time before XPRGWR_N activation. Write data hold time after XPRGWR_N negation. Min 0.5 Typ - Max Unit Tsys_clk 1 0 0 WTST[2:0]+1 - - ns Tsys_clk ns 0.5 0.5 0.5 WTST[2:0]+1 - - Tsys_clk Tsys_clk Tsys_clk Tsys_clk Figure 146: CPU Program Read and Program Write Timing Diagram and Table 1 Tsys_clk = 10/20/40ns for 100/50/25Mhz operating system clock. 294 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY XAD D R [20:0] Ta dd r_s u Taddr_hd Taddr_su Taddr_hd XR AMC E[1:0]_N Tdatwr Tdatwr_su Tdatwr_hd XD ATW R _N Tdatrd Ta dd r_s u XD ATR D _N Twrdata_su Trddata_hd Twrdata_hd XD ATA[7:0] Symbol Taddr_su Description Address setup time before XRAMCE[1:0]_N or XDATRD_N activation. Taddr_hd Address hold time after XRAMCE[1:0]_N or XDATRD_N negation . Tdatrd XDATRD_N activation width. Trddata_hd Read data hold time after XRAMCE[1:0]_N or XDATRD_N negation. Tdatwr_su XRAMCE[1:0] activation to XDATWR_N activation. Tdatwr XDATWR_N activation width. Tdatwr_hd XDATWR_N negation to XRAMCE[1:0]_N negation time. Twrdata_su Write data setup time before XDATWR_N activation. Twrdata_hd Write data hold time after XDATWR_N negation. Min 0 Typ - Max - Unit ns 0 - - ns 0 CKCON[2:0]+1 - - Tsys_clk ns 1 0.5 0.5 0.5 CKCON[2:0]+1 - - ns Tsys_clk Tsys_clk Tsys_clk Tsys_clk Figure 147: CPU Data Read and Data Write Timing Diagram and Table 295 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY X A D DR [2 0 :0 ] T a d d r_ su T a d d r_ h d T a d d r_ su T a d d r_ h d X R A M C E [1 :0 ]_ N T d a tw r T da tw r_ su T da tw r_ h d X DA T WR_ N T d a trd T a d d r_ su X DA T RD_ N T rd d a ta _ h d T w rd ata _ su T w rd a ta _ h d X D A T A [7 :0 ] Symbol Taddr_su Description Address setup time before XRAMCE[1:0]_N or XDATRD_N activation. Taddr_hd Address hold time after XRAMCE[1:0]_N or XDATRD_N negation . Tdatrd XDATRD_N activation width. Trddata_hd Read data hold time after XRAMCE[1:0]_N or XDATRD_N negation. Tdatwr_su XRAMCE[1:0] activation to XDATWR_N activation. Tdatwr XDATWR_N activation width. Tdatwr_hd XDATWR_N negation to XRAMCE[1:0]_N negation time. Twrdata_su Write data setup time before XDATWR_N activation. Twrdata_hd Write data hold time after XDATWR_N negation. Min 0.5 Typ - 0 - - ns 0 CKCON[2:0]+1 - - Tsys_clk ns 1 0.5 0 0.5 CKCON[2:0] - - ns Tsys_clk Tsys_clk ns Tsys_clk Figure 148: DMA Data Read and Data Write Timing Diagram and Table 296 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights Max Unit Tsys_clk AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY R eading R eading int ernal F las h and I nt ernal F las h writ ing t o int ernal SR AM X A DDR[2 0 :0 ] 0 x3 FFF R eading ex t ernal F las h and writ ing t o ex t ernal SR AM 0 x0 0 0 0 0 0 0 x0 8 0 0 0 0 X RO M CE 1 _ N T b l k_ rd T p rg _ rd T p rg _ rd X P RG RD_ N T add_hold T ra m ce T add_hold T ra m ce X RA M CE [1 :0 ]_ N T d a twr_ su T d a twr_su T d a twr_ h d T d a twr T d a twr_ h d T d a twr X DA T WR_ N Bloc k N um ber X DA T A [7 :0 ] program c ode T wrd a ta _ h d program c ode T wrd a ta _ h d n Symbol Tblk_rd Description Min XPRGRD_N activation width to read the "block number" located in program address 0x003FFF. Tprg_rd XPRGRD_N activation width to read 1 byte program code from Flash 120 memory. Tadd_hold Address hold time after XRAMCE[1:0]_N negation. 0 Tramce XRAMCE[1:0] activation width to write 1 byte program code to SRAM. 120 Tdatwr_su XRAMCE[1:0] activation to XDATWR_N activation. 1 Tdatwr XDATWR_N activation width to write 1 byte program code to SRAM. 80 Tdatwr_hd XDATWR_N negation to XRAMCE[1:0]_N negation time. 0.5 Twrdata_hd Write data hold time after XDATWR_N negation. 0.5 Typ Max 120 - Unit ns - - ns - - - - - - ns ns ns ns Tsys_clk Tsys_clk Figure 149: Boot Loader Reading Flash and Writing SRAM Timing Diagram and Table 297 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 5.4.3 I2C Interface Timing Tbuf SDA Thd_sta Tlow Tsu_dat Thigh Thd_dat Thd_sta Tsu_sta Tsu_sto SCL Symbol Fclk Parameter SCL clock frequency. Hold time of (repeated) START condition. After this period, Thd_sta the first clock pulse is generated. Thigh High period of the SCL clock. Tlow Low period of the SCL clock. Tsu_sta Setup time for a repeated START condition. Tsu_dat Data Setup time. Thd_dat Data hold time. Tsu_sto Setup time for STOP condition Tbuf Bus free time between a STOP and START condition. Min - Typ 100, 400 2 Max - Unit KHz Tprsc 2 - 2 3 2 1 2 2 4 - Tprsc Tprsc Tprsc Tprsc Tprsc Tprsc Tprsc Min 3 Typ - Max 380 - Unit KHz Tsys_clk 4 0.6 0.4 1 3 0.4 3 1.3 - - s s s Tsys_clk Tsys_clk s Tsys_clk s Table 60: I2C Master Controller Timing Table Symbol Parameter Fclk SCL clock frequency Hold time of (repeated) START condition. After this period, Thd_sta the first clock pulse is generated. High period of the SCL clock in Standard mode. Thigh High period of the SCL clock in Fast mode . Tlow Low period of the SCL clock. Tsu_sta Setup time for a repeated START condition. Tsu_dat Data Setup time. Thd_dat Data hold time. Tsu_sto Setup time for STOP condition Tbuf Bus free time between a STOP and START condition. 3 Table 61: I2C Slave Controller Timing Table 2 Tprsc = 1/Fprsc, where Fprsc = Operating system clock frequency / (PRER + 1) and the PRER is I2C Clock Prescale Register. 3 Tsys_clk = 10/20/40ns for 100/50/25Mhz operating system clock. 298 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 5.4.4 SPI Interface Timing Fclk SCLK Tdly MOSI Ds u Dhd MISO tl Tl Th Tl SS0 Note: Above diagram only shows setup and hold time relationship of SPI pins in Mode 0. For other 3 modes, they are quite similar except that the clock polarity is reversed. Symbol Fclk Tl Th tl Tdly Dsu Dhd Description SCLK clock frequency. Min - Setup time of SS[2:0] to the first SCLK edge. Hold time of SS[2:0], after the last SCLK edge. Minimum idle time between transfers (minimum SS[2:0] high time). MOSI data valid time, after SCLK edge. MISO data setup time before SCLK edge. MISO data hold time after SCLK edge. Internal time base period. Max - Unit MHz 4 - Typ Fsys_clk (SPIBRR+1)*2 0.5 0.5 0.5 - Tclk 5 Tclk Tclk 5.5 6 - 0.5 1 - Tsys_clk 6 ns ns Tclk Figure 150: SPI Master Controller Timing Diagram and Table 4 Fsys_clk is the operating system clock frequency, 25Mhz, 50Mhz, or 100Mhz. The SPIBRR is SPI Baud Rate Register and its minimum setting value is 0x01 and setting to 0x00 is invalid.. 5 Tclk = 1/Fclk. 6 Tsys_clk = 10/20/40ns for 100/50/25Mhz operating system clock. 299 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Fclk SCLK (I) Dsu MOSI (I) MSB MISO (O) MSB Dhd Dsu Dhd Tdly Tdly SSidle SSsu SShd SS0 (I) SPI Slave Mode Timing Diagram in Mode 0 Fclk SCLK (I) Dhd Dsu Dhd MOSI (I) MSB MISO (O) MSB Dsu Tdly Tdly SSidle SSsu SShd SS0 (I) SPI Slave Mode Timing Diagram in Mode 3 Symbol Fclk Tdly Dsu Dhd SSsu SShd SSidle Description SCLK clock frequency at 100Mhz system clock. SCLK clock frequency at 50Mhz system clock. SCLK clock frequency at 25Mhz system clock. MISO data valid time after SCLK edge. MOSI data setup time before SCLK edge. MOSI data hold time after SCLK edge. SS0 setup time before SCLK edge. SS0 hold time after SCLK edge. SS0 negation to next SS0 active time Min 3 2 + (2ns) 8 2 + (2ns) 2 Typ - Max 6 3 1.5 2 + (12ns) - Figure 151: SPI Slave Controller Timing Diagram and Table 300 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights Unit MHz MHz MHz Tsys_clk ns Tsys_clk ns Tsys_clk Tsys_clk AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 5.4.5 1-Wire Interface Timing tRSTL VCC tRSTH tPDH tPDHCNT tPDL DQ GND tPDS LINE TYPE LEGEND: Symbol tRSTL tRSTH tPDH tPDL 1-Wire Master active low Slave device active low Both Master and Slave device active low Resistor pull-up Parameter Reset Time Low Reset Time High Presence Detect High Presence Detect Low Presence Detect Sample tPDS Conditions Standard Overdrive Standard Overdrive Standard Overdrive Standard Overdrive Standard Standard - Long Line Mode Overdrive Min 500.8 50.4 508.8 59.2 15 2 60 6 24 30.4 2.4 Max 626 63 636 74 60 6 240 24 31 38 4 Figure 152: 1-Wire Reset Pulse and Presence Pulse Timing Diagram and Table 301 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights Units s s s s s s s s s s s AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY WRITE 0 SLOT WRITE 1 SLOT tSLOT tLOW0 tLOW1 tREC VCC DQ tSLOT GND Slave Device Sample Window MIN TYP MAX 15s 15s 30s Slave Device Sample Window MIN TYP MAX 15s 15s READ 1 SLOT READ 0 SLOT tLOW1 30s tSLOT tSLOT tREC tLOW1 VCC DQ GND tRDV tRDV Symbol tSLOT tLOW0 Parameter Time Slot Write 0 Low Time Write 1 Low Time tLOW1 Read Data Value tRDV Recovery Time tREC Conditions Standard Overdrive Standard Overdrive Standard Standard - Long Line Mode Overdrive Standard Standard - Long Line Mode Overdrive Standard Standard - Long Line Mode Overdrive Time base Period Min 68.8 12 62.4 8 4.8 7.2 0.8 12 20 1.6 5.5 11.2 4 0.96 Max 86 15 78 12 6 9 1 15 25 2 8 14 5 1 Figure 153: 1-Wire Write and Read Time Slot Timing Diagram and Table 302 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights Units s s s s s s s s s s s s s s AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Reset Timing Read/Write Timing tDLY2 STPEN=1 tDLY3 tDLY3 tOFF2 tDLY1 DQ STPZ tON1 tON2 tON3 tON4 tSLOT tSLOT STPEN=STP_SPLY=1 tOFF1 tDLY2 tDLY3 tOFF2 tDLY1 tDLY3 tOFF2 DQ STPZ tON1 Symbol tOFF1 Description Turn Off Time for 1-Wire Reset tDLY1 Delay Time for Presence Detect tON1 Active Time for Presence Detect tDLY2 Delay Time for Presence Detect Recovery tON2 Active Time for Presence Detect Recovery tDLY3 Delay Time for Write1/Write0 Recovery tON3 Active Time for Write 1 Recovery tOFF2 Turn Off Time for Write1/Write0 tON4 Active Time for Write 0 Recovery tON3 Conditions Standard Overdrive Standard Overdrive Standard Overdrive Standard Overdrive Standard Overdrive Standard Overdrive Standard Overdrive Standard Overdrive Standard Overdrive Min 1.6 1.6 0.8 0.8 6.4 0.8 399.2 31.2 8 8 0.8 0.8 51.2 7.2 0.8 0.8 4 0.8 Max 2 2 1 1 8 1 499 39 10 10 1 1 78 9 1 4.8 12 1 Figure 154: 1-Wire STPZ Reset and Read Write Timing Diagram and Table 303 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights Units s s s s s s s s s s s s s s s s s s AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 5.4.6 Programmable Counter Array Interface Timing T e ci _ p u l se T e ci _ cycl e E CI i n te rn a l sys_ cl k T e ci _ d l y i n te rn a l l y re ti m e d E CI Symbol Description Teci_cycle ECI cycle time Teci_pulse ECI pulse width Teci_dly ECI internally retimed delay Min >2 >1 2 Typ - Max 3 Units Tsys_clk 7 Tsys_clk Tsys_clk Max 2~3 2~3 3 Units Tsys_clk Tsys_clk Tsys_clk Tsys_clk Tsys_clk Figure 155: ECI Timing Diagram and Table T ce x_ h i T ce x_ l o w CE X [4 :0 ] i n te rn a l sys_ cl k T ce x_ ri s CE X [4 :0 ] ri si n g -e d g e d e te cte d i n te rn a l l y T ce x_ fa l CE X [4 :0 ] fa l l i n g -e d g e d e te cte d i n te rn a l l y T ce x_ d l y i n te rn a l l y re ti m e d CE X [4 :0 ] Symbol Tcex_hi Tcex_low Tcex_ris Tcex_fal Tcex_dly Description CEX[4:0] (as input ) high pulse width CEX[4:0] (as input ) low pulse width CEX[4:0] (as input ) rising-edge internal detection time CEX[4:0] (as input ) falling-edge internal detection time CEX[4:0] (as input ) internally retimed delay Min 1.5 1.5 1~2 1~2 2 Typ - Figure 156: CEX[4:0] Timing Diagram and Table 7 Tsys_clk = 10/20/40ns for 100/50/25Mhz operating system clock. 304 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 5.4.7 Timer 0/1/2 Interface Timing Tck_hi Tck_low TM_CK[2:0] internal sys_clk Tck_fal TM_CK[2:0] falling-edge detected internally Symbol Description Tck_hi TM_CK[2:0] high pulse width Tck_low TM_CK[2:0] low pulse width Tck_fal TM_CK[2:0] falling-edge internal detection time Min 2 2 1~2 Typ - Max 2 Units Tsys_clk Tsys_clk Tsys_clk Typ - Max 2 1 Units Tsys_clk Tsys_clk Tsys_clk Tsys_clk Figure 157: TM_CK[2:0] Timing Diagram and Table T gt_hi T gt_low T M_GT [2:0] internal sys_clk T gt_fal T M_GT [2:0] falling-edge detected internally T gt_dl y internally retimed T M_GT [2:0] Symbol Tgt_hi Tgt_low Tgt_fal Tgt_dly Description TM_GT[2:0] high pulse width TM_GT[2:0] low pulse width TM_GT[2:0] falling-edge internal detection time TM_GT[2:0] internally retimed delay Min 2 2 1~2 0.5 Figure 158: TM_GT[2:0] Timing Diagram and Table 305 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 5.4.8 Local Bus Interface Timing LA[15:0] Read Addr Write Addr 6 LCS[1:0]_N slave address sampled 1 1 LALE 5 2 4 LRD_N 7 9 8 LWR_N 14 10 LDA[15:0] Read D at a Write Data 16 13 17 11 LRDY 3 master data s ampled master read data internal LDA[15:0] sampled 12 slave data s ampled slave write data Figure 159: ISA Bus Access Timing Diagram Item 1 2 4 16 5 3 6 7 8 17 9 Min Typ Max Unit Address setup time before LALE activation Description 1 + (1 ns) - 1 + (2 ns) Address valid to LRD_N activation Read access time with self-terminated timer 1 - (0.9 ns) - 1 - (0.4 ns) - Read access time terminated by LRDY Read Address hold time LRDY activation to read data being sampled internally Access to Access 2-3 1- (1 ns) 2-3 LMSR[BUS_ACC+1] x LCR[RDY_CY+1] - Tsys_clk 8 Tsys_clk Tsys_clk 2+LMSR[BUS_ACC] 1 - (0.5 ns) 2+LMSR[BUS_ACC] Tsys_clk Tsys_clk Tsys_clk - - Tsys_clk LMSR[BUS_ACC+1] x LCR[RDY_CY+1] - 1 - (0.3 ns) - Tsys_clk Tsys_clk 2+LMSR[BUS_ACC] 1 - (0.4 ns) Tsys_clk Tsys_clk Address valid to LWR_N activation Write access time with self-terminated timer Write access time terminated by LRDY Write Address hold time 1 + (3 x LMSR[BUS_ACC+1]) 1 - (0.8 ns) 2-3 1 - (0.8 ns) Table 62: ISA Bus Access Timing Table (Master Mode) Item 1 2 4 5 Description 13 10 6 7 8 9 12 Address setup time before LALE activation Address valid to LRD_N activation Read access time with wait state or terminated by LRDY Read Address hold time LRD_N activation to read data valid (async bus mode) LRD_N activation to read data valid (sync bus mode) Read data valid to LRDY valid LCS0_N negation to LDA[15:0] bus tri-state Access to Access Address valid to LWR_N activation Write access time with wait state or terminated by LRDY Write Address hold time LWR_N activation to write data being sampled internally 11 LCS0_N negation to LRDY tri-state 14 Min Typ Max Unit 10 10 4 0 3~4 3 1 - (2.5 ns) 3 6 10 4 0 2 - 1 - (0.8 ns) 8 3 ns ns Tsys_clk ns Tsys_clk Tsys_clk Tsys_clk ns Tsys_clk ns Tsys_clk ns Tsys_clk 3.2 - 8 ns Table 63: ISA Bus Access Timing Table (Slave Mode) 8 Tsys_clk = 10/20/40ns for 100/50/25Mhz operating system clock. 306 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 6 LCS[1:0]_N 10 LDA[15:0] Addr Read Data Addr Write Data slave address sampled 1 1 LALE 4 14 2 5 LRD_N 7 9 8 LWR_N 16 13 17 11 LRDY 3 master data sampled maste r read data internal LDA[15:0] sampled 12 slave data sampled slave write data Figure 160: Intel 80186 Bus Access Timing Diagram Item 1 2 4 16 5 3 6 7 8 17 9 Description Address setup time before LALE activation Address valid to LRD_N activation Read access time with self-terminated timer Read access time terminated by LRDY Read Address hold time LRDY activation to read data being sampled internally Access to Access Address valid to LWR_N activation Write access time with self-terminated timer Write access time terminated by LRDY Write Address hold time Min Typ LMSR[BUS_ACC+1] + (0.8ns) 1 - (0.9ns) - - 2-3 1 - (1 ns) 2-3 1 + (3 x LMSR[BUS_ACC+1]) 1 - (0.75 ns) 2-3 1 - (0.8 ns) Max Unit LMSR[BUS_ACC+1] + (2 Tsys_clk 9 ns) 1 - (0.3 ns) Tsys_clk Tsys_clk LMSR[BUS_ACC+1] x LCR[RDY_CY+1] - 2+LMSR[BUS_ACC] 1 - (0.4 ns) 2+LMSR[BUS_ACC] Tsys_clk Tsys_clk Tsys_clk - - Tsys_clk LMSR[BUS_ACC+1] x LCR[RDY_CY+1] - 1 - (0.25 ns) - Tsys_clk Tsys_clk 2+LMSR[BUS_ACC] 1 - (0.3 ns) Tsys_clk Tsys_clk Table 64: Intel 80186 Bus Access Timing Table (Master Mode) Item 1 2 4 5 14 13 10 6 7 8 9 12 11 Description Address setup time before LALE activation Address valid to LRD_N activation Read access time with wait state or terminated by LRDY LRD_N negation to LCS0_N negation LRD_N activation to read data valid (async bus mode) LRD_N activation to read data valid (sync bus mode) Read data valid to LRDY valid LCS0_N negation to LDA[15:0] bus tri-state LRD_N negation to LDA[15:0] bus tri-state Access to Access Address valid to LWR_N activation Write access time with wait state or terminated by LRDY LWR_N negation to LCS0_N negation LWR_N activation to write data being sampled internally LCS0_N negation to LRDY tri-state LRD_N negation to LRDY tri-state Min Typ Max Unit 10 10 4 0 3~4 3 1 - (1 ns) 1 + (2 ns) 6 10 4 0 2 3.2 1 + (3.5 ns) - 1 - (0.4ns) 4 3 7.6 - ns ns Tsys_clk ns Tsys_clk Tsys_clk Tsys_clk ns Tsys_clk Tsys_clk ns Tsys_clk ns Tsys_clk ns Tsys_clk Table 65: Intel 80186 Bus Access Timing Table (Slave Mode) 9 Tsys_clk = 10/20/40ns for 100/50/25Mhz operating system clock. 307 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY LA[15:0] Read Addr W ri te A ddr 6 LCS[1:0]_N s lave addres s sampled LALE 2 5 1 4 LRD_N 9 1 7 8 LW R_N 14 10 LDA[15:0] Re ad Dat a W ri te D at a 13 16 17 11 LRDY mas ter data s ampled s lave data s ampled 3 12 internal LDA[15:0] s ampled master read data slave write data Figure 161: Intel 80386 Bus Access Timing Diagram Item 1 2 4 16 5 3 6 7 8 17 9 Description Min LCS[1:0]_N falling-edge to LRD_N or LWR_N activation LRD_N activation to LALE rising-edge Read access time with self-terminated timer Read access time terminated by LRDY Read Address hold time LRDY activation to read data being sampled internally Access to Access LWR_N activation to LALE rising-edge 1 + (3 x LMSR[BUS_ACC+1]) LMSR[BUS_ACC+1] Write access time with self-terminated timer Write access time terminated by LRDY Write Address hold time Typ Max Unit LMSR[BUS_ACC+1] + LMSR[BUS_ACC+1] + Tsys_clk 10 (0.5 ns) (1.8 ns) LMSR[BUS_ACC+1] - LMSR[BUS_ACC+1] + Tsys_clk (0.1 ns) (0.6 ns) 1+(LMSR[BUS_ACC+1] x Tsys_clk LCR[RDY_CY+1]) 2-3 2+LMSR[BUS_ACC] Tsys_clk 1 - (0.1ns) 1 + (0.6 ns) Tsys_clk 2-3 2+LMSR[BUS_ACC] Tsys_clk 2-3 1 - (0.8 ns) - - - LMSR[BUS_ACC+1] + (0.6 ns) 1+(LMSR[BUS_ACC+1] x LCR[RDY_CY+1]) 2+LMSR[BUS_ACC] 1 - (0.3 ns) Tsys_clk Tsys_clk Tsys_clk Tsys_clk Tsys_clk Table 66: Intel 80386 Bus Access Timing Table (Master Mode) Item 1 2 4 5 14 13 10 6 7 8 9 12 11 Description LCS0_N falling-edge to LRD_N or LWR_N activation LRD_N activation to LALE rising-edge Read access time with wait state or terminated by LRDY Read Address hold time LALE activation to read data valid (async bus mode) LALE activation to read data valid (sync bus mode) Read data valid to LRDY active LCS0_N negation to LDA[15:0] bus tri-state Access to Access LWR_N activation to LALE rising-edge Write access time with wait state or terminated by LRDY Write Address hold time LALE activation to write data being sampled internally LCS0_N negation to LRDY tri-state Min Typ Max Unit 10 10 4 0 3~4 3 1 - (2.3 ns) 1.8 6 10 4 0 2 3.3 - 1 - (0.5 ns) 4.6 3 8.2 ns ns Tsys_clk ns Tsys_clk Tsys_clk Tsys_clk ns Tsys_clk ns Tsys_clk ns Tsys_clk ns Table 67: Intel 80386 Bus Access Timing Table (Slave Mode) 10 Tsys_clk = 10/20/40ns for 100/50/25Mhz operating system clock. 308 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY LA[15:0] Read Addr Write Addr 12 LCS[1:0]_N 1 slave address sampled 10 1 LALE 4 7 LWR_N 2 5 6 LUDS_N/LLDS_N 14 8 LDA[15:0] Read Data Write Data 15 11 16 13 LRDY 3 internal LDA[15:0] sampled master data sampled master read data 9 slave data sampled slave write data Figure 162: Motorola 68000/010 Bus Access Timing Diagram Item 1 2 15 3 10 12 4 5 6 16 7 Min Typ Max Unit Address setup time before LALE activation Description 1 + (0.85 ns) - 1 + (2 ns) Read access time with self-terminated timer - - Read access time terminated by LRDY LRDY activation to read data being sampled internally Read address hold time Access to access 2-3 2-3 LMSR[BUS_ACC+1] x LCR[RDY_CY+1] - Tsys_clk 11 Tsys_clk 2+LMSR[BUS_ACC] 2+LMSR[BUS_ACC] Tsys_clk Tsys_clk - 1 - (0.7 ns) - Tsys_clk Tsys_clk - 1 + (1.2 ns) 1 + (0.1 ns) Tsys_clk Tsys_clk (LMSR[BUS_ACC+1] x LCR[RDY_CY+1]) - 1 - - Tsys_clk 2+LMSR[BUS_ACC] 1 - (0.3 ns) Tsys_clk Tsys_clk Address setup time before LWR_N activation LWR_N activation to LUDS_N/LLDS_N activation Write access time with self-terminated timer Write access time terminated by LRDY Write address hold time 1 - (0.3 ns) 1 + (3 x LMSR[BUS_ACC+1]) 1 + (0.5 ns) 1 - (0.2 ns) 2-3 1 - (0.8 ns) Table 68: Motorola 68000/010 Bus Access Timing Table (Master Mode) Item 1 2 14 11 8 12 5 6 9 13 Description Address setup time before LALE activation Read access time with wait state or terminated by LRDY LUDS_N/LLDS_N activation to read data valid (async bus mode) LUDS_N/LLDS_N activation to read data valid (sync bus mode) Read data valid to LRDY valid LUDS_N/LLDS_N negation to LDA[15:0] tri-state Access to access LWR_N activation to LUDS_N/LLDS_N activation Write access time with wait state or terminated by LRDY LUDS_N/LLDS_N activation to write data being sampled internally LUDS_N/LLDS_N negation to LRDY tri-state Min Typ Max Unit 10 4 3~4 3 1 - (1.9 ns) 1 + (1.3ns) 6 10 4 2 1 + (2.6 ns) - 1 - (0.6 ns) 1 + (3 ns) 3 1+ (6.6 ns) ns Tsys_clk Tsys_clk Tsys_clk Tsys_clk Tsys_clk Tsys_clk ns Tsys_clk Tsys_clk Tsys_clk Table 69: Motorola 68000/010 Bus Access Timing Table (Slave Mode) 11 Tsys_clk = 10/20/40ns for 100/50/25Mhz operating system clock. 309 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY L A [3 :0 ] R e a d A d dr W ri t e A d d r LCS0_N 1 LALE 5 LWR_N L U D S _ N /L L D S _ N 2 4 L D A [1 5 :0 ] R e a d D a ta W ri t e D a t a 3 7 8 LRDY 6 i n t e rn a l L D A [ 1 5 : 0 ] sa m p l e d sl a v e w ri t e d a t a Figure 163: Motorola 68030/040 Bus Access Timing Diagram (Slave mode) Item Description Min. Typ Max Unit 1 Address setup time before LALE activation LUDS_N/LLDS_N activation to read data valid (async bus mode) LUDS_N/LLDS_N activation to read data valid (sync bus mode) Read data valid to LRDY valid LUDS_N/LLDS_N negation to LDA[15:0] tri-state LWR_N activation before LALE/LUDS_N/LLDS_N LUDS_N/LLDS_N activation to write data being sampled internally LUDS_N/LLDS_N activation to LRDY valid LUDS_N/LLDS_N negation to LRDY tri-state 10 3~4 - - ns Tsys_clk 12 3 - - Tsys_clk 1 - (2.3 ns) 2.5 10 2 - 1 - (0.6 ns) 6.1 3 Tsys_clk ns ns Tsys_clk 2 3.9 - 3 9.7 Tsys_clk ns 2 3 4 5 6 7 8 Table 70: Motorola 68030/040 Bus Access Timing Table (Slave Mode) 12 Tsys_clk = 10/20/40ns for 100/50/25Mhz operating system clock. 310 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY L A [3 :0 ] R ea d A d d r W ri t e A d d r 8 LCS 0_N 1 LRD_N 5 LWR_N 2 L D A [1 5 :0 ] 4 R e a d D a ta W ri t e D a t a 3 6 9 L R D Y (S H 3 ) L R D Y (S H 4 ) 7 i n t e rn a l L D A [ 1 5 : 0 ] sa m p l e d sl a v e w ri t e d a t a Figure 164: Renesas SH3/SH4 Bus Access Timing Diagram (Slave mode) Item Description 1 Address setup time before LRD_N falling-edge 2 3 4 8 5 7 6 9 LRD_N falling-edge to read data valid (async bus mode) LRD_N falling-edge to read data valid (sync bus mode) Read data valid to LRDY valid LCS0_N negation to LDA[15:0] tri-state Access to Access Address setup time before LWR_N falling-edge LWR_N falling-edge to write data being sampled internally LWR_N falling edge to LRDY valid LCS0_N negation to LRDY tri-state Min. Typ. Max 10 - - 3~4 - - 3 - - 1 - (2.5 ns) - 1 - (0.85 ns) 1.8 - 4.6 6 - - 10 - - 2 - 3 2 - 3 1 + (2.6 ns) - 1 + (6.6 ns) Table 71: Renesas SH3/SH4 Bus Access Timing Table (Slave Mode) 13 Tsys_clk = 10/20/40ns for 100/50/25Mhz operating system clock. 311 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights Unit ns Tsys_clk 13 Tsys_clk Tsys_clk ns Tsys_clk ns Tsys_clk Tsys_clk ns AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY LA[3:2] (H C N TL[1:0]) R ead Addr R ead Addr Write Addr Write Addr LA[1] (H H WIL) 6 LC S[1:0]_N (H C S#) 2 2 1 2 1 2 1 1 LALE (H AS#) 4 4 7 5 5 1st h alf wo rd 2nd half 7 8 8 LLD S_N (H D S1#) LWR _N (H R /W#) 10 LD A[15:0] (H D [15:0]) 10 1st halfword 13 2nd halfw 14 LR D Y (H R D Y#) 3 9 internal LD A[15:0] sampled Figure 165: TI HPI Bus Access Timing Diagram (Master mode) Item 1 2 5 13 4 3 9 6 8 14 10 7 Description Min Typ Max Unit Address setup time before LALE falling-edge LALE pulse width Read access time with self-terminated timer Read access time terminated by LRDY LLDS_N negation to LCS[1:0]_N negation LRDY activation to read data being sampled internally LALE negation to read data being sampled internally when LRDY is already active Access to access 1 + (0.9 ns) - 1 + (2 ns) Tsys_clk 14 - LMSR[BUS_ACC] LMSR[BUS_ACC+1] x LCR[RDY_CY+1] - Tsys_clk Tsys_clk Write access time with self-terminated timer Write access time terminated by LRDY LALE negation to write data valid LLDS_N negation to LCS[1:0]_N negation 2-3 1 - (0.75 ns) - 2+LMSR[BUS_ACC] Tsys_clk 1 - (0.35 ns) Tsys_clk 2-3 - 2+LMSR[BUS_ACC] Tsys_clk - 1+LMSR[BUS_ACC] - - 1 + (3 x Tsys_clk LMSR[BUS_ACC+1] LMSR[BUS_ACC+1] Tsys_clk x LCR[RDY_CY+1] 2-3 2+LMSR[BUS_ACC] Tsys_clk 0.4 1.5 ns 1 - (0.3 ns) 1 + (0.75 ns) Tsys_clk Table 72: TI HPI Bus Access Timing Table (Master Mode) 14 Tsys_clk Tsys_clk = 10/20/40ns for 100/50/25Mhz operating system clock. 312 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY LCSx_N LALE LA[15:0]**** 7 WR_DRQ * 1 2 6 WR_DAK ** 3 LWR_N 4 LDA[15:0] Write Data Write Dat Read Dat Read Data 5 LRDY *** 13 RD_DRQ * 11 8 10 12 RD_DAK ** 9 LRD_N *: WR_DRQ and RD_DRQ signal polarity is programmable, by I2C Configuration EEPROM in offset 0x13. **: WR_DAK and RD_DAK signal polarity is programmable, by I2C Configuration EEPROM in offset 0x13. ***: LRDY signal polarity is programmable, by I2C Configuration EEPROM in offset 0x12. Figure 166: Slave-Request DMA Access Timing Diagram (Local Bus Master Mode only) Note: 1. During slave-request DMA read access mode, the LCS0_N and LALE will be held inactive. That means either the external local bus device should support some register based interface for the AX11015's LBI to pre-configure the DMA "source starting address" of external local bus device prior to the DMA access, or the external local bus device should support a FIFO-like interface that simply decodes the assertion of RD_DRQ, RD_DAK and LRD_N signal combination as DMA read access. 2. During slave-request DMA write access mode, the LCS0_N and LALE will be held inactive. That means either the external local bus device should support some register based interface for the AX11015's LBI to pre-configure the DMA "target starting address" of external local bus device prior to the DMA access, or the external local bus device should support a FIFO-like interface that simply decodes the assertion of WR_DRQ, WR_DAK and LWR_N signal combination as DMA write access. 313 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Item 1 2 5 3 4 6 7 8 9 10 11 12 13 Min Typ Max WR_DRQ asserted by external local bus device to WR_DAK granted by LBI Description - - Write access time with self-terminated timer - Depending on software receiving interrupt from LBI in SDWR_REQ bit (LSR.2) and then initiating burst write command in LBI master LMSR[BUS_ACC+1] x LCR[RDY_CY+1] - Write access time terminated by LRDY 2-3 WR_DAK assertion to LWR_N assertion WR_DAK assertion to LDA[15:0] data valid Back to back write access in a burst write command Burst write access duration per one burst write command initiated by software RD_DRQ asserted by external local bus device to RD_DAK granted by LBI 1.2 1.6 1 + (3* LMSR[BUS_ACC]) 16 RD_DAK assertion to LRD_N assertion Read access time with self-terminated timer 0.8 - Read access time terminated by LRDY 2-3 Back to back read access in a burst read command Burst read access duration per one burst read command initiated by software - Depending on software receiving interrupt from LBI in SDRD_REQ bit (LSR.3) and then initiating burst read command in LBI master LMSR[BUS_ACC+1] x LCR[RDY_CY+1] - 1 + (3* LMSR[BUS_ACC]) 16 - 2+ LMSR[BUS_ACC] 2.3 4.1 - Tsys_clk 15 Tsys_clk ns ns Tsys_clk 256 Bytes 1.5 - ns Tsys_clk 2+ LMSR[BUS_ACC] - Tsys_clk 256 Bytes Table 73: Slave-Request DMA Access Timing Table (Local Bus Master Mode only) 15 Unit Tsys_clk = 10/20/40ns for 100/50/25Mhz operating system clock. 314 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights Tsys_clk AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Tlbc Tlbc_h Tlbc_l lb_clk Tctrl_od Tctrl_od LCS[1:0]_N Tctrl_od Tctrl_od LALE Taddr_od Taddr_od LA[15:0] Tctrl_od Tctrl_od Tctrl_od Tctrl_od LWR_N LRD_N Tdata_od Tdata_od LDA[15:0](O) Tdata_set Tdata_hold LDA[15:0](I) Tctrl_od Tctrl_od Tctrl_od Tctrl_od LUDS_N LLDS_N Tctrl_set Tctrl_hold Tctrl_set Tctrl_set LRDY LINT Figure 167: Local Bus Master Synchronous Mode Timing Diagram Symbol Tlbc Tlbc_h Tlbc_l Tctrl_od Taddr_od Tdata_od Tctrl_set Tctrl_hold Tdata_set Tdata_hold Description Local bus clock output cycle time Local bus clock output high time (50%) Local bus clock output low time (50%) Local bus control bus output delay time Local bus address bus output delay time Local bus data bus output delay time Local bus control bus input setup time Local bus control bus input hold time Local bus data bus input setup time Local bus data bus input hold time Min 1.1 1.6 2.3 2 4.5 2 4.5 Typ 10/20/40 5/10/20 5/10/20 - Max 4.5 4.6 5.6 - Table 74: Local Bus Master Synchronous Mode Timing Table 315 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights Units ns ns ns ns ns ns ns ns ns ns AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Tlbc Tlbc_h Tlbc_l lb_clk Tctrl_set Tctrl_hold LCS[1:0]_N Tctrl_set Tctrl_hold LALE Taddr_set Taddr_hold LA[15:0] Tctrl_set Tctrl_hold Tctrl_set Tctrl_hold Tdata_set Tdata_hold LWR_N LRD_N LDA[15:0](I) Tdata_od Tdata_od LDA[15:0](O) Tctrl_set Tctrl_hold Tctrl_set Tctrl_hold LUDS_N LLDS_N Tctrl_od Tctrl_od LRDY Tctrl_od Tctrl_od LINT Figure 168: Local Bus Slave Synchronous Mode Timing Diagram Symbol Tlbc Tlbc_h Tlbc_l Tctrl_set Tctrl_hold Taddr_set Taddr_hold Tdata_set Tdata_hold Tctrl_od Tdata_od Description Local bus clock input cycle time Local bus clock input high time (50%) Local bus clock input low time (50%) Local bus control bus input setup time Local bus control bus input hold time Local bus address bus input setup time Local bus address bus input hold time Local bus data bus input setup time Local bus data bus input hold time Local bus control bus output delay time Local bus data bus output delay time Min 20 10 10 2 4.5 2 4.5 2 4.5 4 2.5 Typ - Max 14 15 Table 75: Local Bus Slave Synchronous Mode Timing Table 316 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights Units ns ns ns ns ns ns ns ns ns ns ns AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 5.4.9 Digiport Interface Timing LRDY (DP[9]) LDA[7:0] (DP[7:0]) FIFO Data 1 FIFO Data 2 FIFO Data 3 2 1 3 4 1 LALE (DP[8]) Figure 169: Digiport Parallel Mode Timing Diagram Item Description Min Typ Max Unit 2 - - 1 340 340 - - Tsys_clk 16 Tsys_clk ns ns LRDY and LDA[7:0] setup time before LALE rising edge 1 2 3 4 LRDY and LDA[7:0] hold time after LALE rising edge LALE (FIFO Clk) clock high time LALE (FIFO Clk) clock low time Table 76: Digiport Parallel Mode Timing Table L C S 0 _ N (S F P 1 3 0 ) 9 1 L R D Y (S F P 5 0 ) 3 2 4 7 8 L A L E (S F P 3 ) L D A [ 0 ] (S F P 2 ) 6 5 b i t7 b i t6 b i t1 b i t0 i n t e rn a l p a ra l l e l d a t a b i t7 b y te 1 b i t0 b y te b y te 3 2 Figure 170: Digiport SPI Mode Timing Diagram Item Description LCS0_N assertion to LRDY assertion Min Typ Max - Depending on software initiating burst read command 20.833 20.833 41.66 - - 1 2 3 4 5 6 7 8 9 LRDY assertion to LALE falling-edge and LDA[0] valid LALE (as SCLK) clock low time LALE (as SCLK) clock high time (typical frequency = 24Mhz) LDA[0] setup time before LALE rising edge LDA[0] hold time after LALE rising edge LALE high time between each 8-bits transfer LALE high to next LRDY assertion, after 32 times of 8-bits transfer. LRDY high time 1 10 10 9 460 Table 77: Digiport SPI Mode Timing Table 16 Tsys_clk = 10/20/40ns for 100/50/25Mhz operating system clock. 317 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights - Unit Tsys_clk ns ns ns ns ns Tsys_clk ns AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 5.4.10 10/100M Ethernet PHY Interface Timing +Vtxov +Vtxa Tr: from 10% to 90% 0V Symbol Description Condition Peak-to-peak differential output voltage 10BASE-T mode Vtxa *2 Peak-to-peak differential output voltage 100BASE-TX mode Tr / Tf Signal rise / fall time 100BASE-TX mode Output jitter 100BASE-TX mode, scrambled idle signal Vtxov Overshoot 100BASE-TX mode Min 4.4 1.9 3 - Typ Max Units 5 5.6 V 2 2.1 V 4 5 ns 1.4 ns - - 5 % Figure 171: 10/100M Ethernet PHY Transmitter Waveform and Spec Symbol Description Receiver input impedance Differential squelch voltage Common mode input voltage Maximum error-free cable length Condition 10BASE-T mode Min Typ Max Units 10 300 2.97 100 400 3.3 - K mV V meter Table 78: 10/100M Ethernet PHY Receiver Spec 318 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights 500 3.63 - AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 5.4.11 MII Timing Ttclk Ttch Ttcl TX_CLK Tts Tth MTXD [3:0] TX_EN, TX_ER Symbol Ttclk Ttch Ttcl Tts Tth Description Min 28.0 4.5 TX_CLK clock cycle time *1 TX_CLK clock high time *2 TX_CLK clock low time *2 TXD [3:0], TX_EN, TX_ER setup time TXD [3:0], TX_EN, TX_ER hold time Trclk Trch Typ 40.0 20.0 20.0 - Max 11.5 Units ns ns ns ns ns Trcl RX_CLK Trs Trh MRXD [3:0] RX_DV, RX_ER Symbol Trclk Trch Trcl Trs Trh Description Min 3.0 0.5 RX_CLK clock cycle time *1 RX_CLK clock high time *2 RX_CLK clock low time *2 RXD [3:0], RX_DV, and RX_ER setup time RXD [3:0], RX_DV, and RX_ER hold time Typ 40.0 20.0 20.0 - Max - *1: For 10Mbps, the typical value of Ttclk and Trclk shall scale to 400ns. *2: For 10Mbps, the typical value of Ttch, Ttcl, Trch, and Trcl shall scale to 200ns. 319 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights Units ns ns ns ns ns AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 5.4.12 Station Management Timing Tclk Tch MDC Tcl Tod MDIO (as output) Ts Th MDIO (as input) Symbol Tclk Tch Tcl Tod Ts Th Description Min 0 10 0 MDC clock cycle time MDC clock high time MDC clock low time MDC clock falling edge to MDIO output delay MDIO data input setup time MDIO data input hold time Typ 640 320 320 - Max 2 - 320 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights Units ns ns ns ns ns ns AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 6.0 Package Information A A2 A1 L L1 D Hd He E pin 1 e b Symbol Millimeter Typ Min A1 A2 A b D E e Hd He L L1 17 0.05 1.35 0.13 13.90 13.90 15.85 15.85 0.45 0 1.40 0.18 14.00 14.00 0.4 BSC 17 16.00 16.00 0.60 1.00 REF 3.5 Max 1.45 1.60 0.23 14.10 14.10 16.15 16.15 0.75 7 BSC stands for Basic Spacing between Centers. Please refer to JEDEC Standard 95, page 4.17 for details. 321 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 7.0 Ordering Information Part Number AX11015 LF AX11015 LI Description Lead Free package, commercial temperature range, 0 to 70C . Lead free package, Industrial temperature range, -40 to 85C. 8.0 Revision History Revision V1.0 V1.1 V1.2 V1.3 V1.04 V1.05 V1.06 V1.07 V1.08 V1.09 Date Comments 2006/08/15 First release. 2007/03/26 Corrected Figure 15 connection diagram and Figure 45 description. Corrected Table 7 and Table 8 setting values in section 3.1.9. Updated section 5.2 power consumption for CPU in STOP, OSC/PLL stopped. Added Tbuf and Tsu_sto value in section 5.4.3 I2C interface timing. Corrected Iol and Ioh value in section 5.1.4 and 5.1.5. Added min value for Trise3 in section 5.3. 2007/05/04 1. Corrected XTL25P pin type to O18 in section 1.4 Signal Description. 2. Removed T2IF in Table 9 SFR Register Map. 2007/12/20 1. Added JC and JA data in section 5.2. 2. Added the device address (1010000b) information of the I2C Configuration EEPROM in section 3.1. 2008/06/06 1. Add the "US Patent Pending" string in the Features page. 2008/07/30 1. Update the protocol support information in the Features page. 2. Update Figure 164 "Slave-Request DMA Access Timing Diagram (Local Bus Master Mode only)" and add some notes. 2008/09/15 1. Added more information into Section 4.6.5. 2. Adjusted the Local Bus Master Synchronous Mode Timing Diagram and Table into the same page in Section 5.4.8. 2008/10/30 1. Updated the Trise3 timing information in Section 5.3. 2. Added Figure 6 Low Speed PLC (Power Line Communication) to Ethernet Converter and Figure 7 Serial to HomePlug (Power Line Communication) Converter. 2009/11/26 1. Updated the SPI related timing decription. 2. Updated Table 14: On-chip Flash Memory Read Protection descption. 2011/06/14 1. Added legal disclaimer description. 322 Copyright (c) 2006-2011 ASIX Electronics Corporation. All rights AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY 4F, No. 8, Hsin Ann Rd., HsinChu Science Park, HsinChu, Taiwan, R.O.C. TEL: 886-3-5799500 FAX: 886-3-5799558 Email: support@asix.com.tw Web: http://www.asix.com.tw 323