SLUS168D – APRIL 1999 – REVISED AUGUST 2002
1
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DDual Output Drive Stages in Push-Pull
Configuration
D130-µA Typical Starting Current
D1-mA Typical Run Current
DOperation to 1-MHz
DInternal Soft Start
DOn Chip Error Amplifier With 2-MHz Gain
Bandwidth Product
DOn Chip VDD Clamping
DOutput Drive Stages Capable Of 500-mA
Peak Source Current, 1-A Peak Sink Current
description
The UCC3808 is a family of BiCMOS push-pull, high-speed, low-power, pulse-width modulators. The UCC3808
contains all of the control and drive circuitry required for off-line or dc-to-dc fixed frequency current-mode switching
power supplies with minimal external parts count.
The UCC3808 dual output drive stages are arranged in a push-pull configuration. Both outputs switch at half the
oscillator frequency using a toggle flip-flop. The dead time between the two outputs is typically 60 ns to 200 ns
depending on the values of the timing capacitor and resistors, thus limiting each output stage duty cycle to less than
50%. (continued)
block diagram
UDG-02116
312
8
7
6
5
4
OSCILLATOR
SQ
R
RC
1.2R
R
0.5 V
PEAK CURRENT
COMPARATOR
Q
Q
T
SQ
R
SQ
R
VDD
VOLTAGE
REFERENCE
14 V
PWM
COMPARATOR
PWM
LATCH
SOFT START
0.5 V
VDD–1 V
0.75 V
2.2 V 2.0 V
FB COMP CS
VDD
OUTA
OUTB
GND
SLOPE = 1 V/ms
VDD OK
OVERCURRENT
COMPARATOR 22 k
Note: Pinout shown is for SOIC and PDIP packages. TSSOP pinout is different.
Ω
Copyright 2002, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
8
7
6
5
COMP
FB
CS
RC
VDD
OUTA
OUTB
GND
D OR N PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
PW PACKAGE
(TOP VIEW)
OUTB
GND
RC
CS
OUTA
VDD
COMP
FB
SLUS168D – APRIL 1999 – REVISED AUGUST 2002
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description (continued)
The UCC3808 family offers a variety of package temperature range options, and choice of undervoltage lockout
levels. The family has UVLO thresholds and hysteresis options for of f-line and battery powered systems. Thresholds
are shown in the table below.
Table 1.
Part Number Turn on Threshold Turn off Threshold
UCCx808–112.5 V 8.3 V
UCCx808–24.3 V 4.1 V
ORDERING INFORMATION
TT
Packaged Devices
TA = TJUVLO Option SOIC (D) PDIP (N) TSSOP (PW)
40°Cto85°C
12.5 V/8.3 V UCC2808D–1 UCC2808N–1 UCC2808PW–1
–40°C to 85°C4.3 V/4.1 V UCC2808D–2 UCC2808N–2 UCC2808PW–2
0°Cto70°C
12.5 V/8.3 V UCC3808D–1 UCC3808N–1 UCC3808PW–1
0°C to 70°C4.3 V/4.1 V UCC3808D–2 UCC3808N–2 UCC3808PW–2
†D (SOIC–8) and PW (TSSOP–8) packages are available taped and reeled. Add TR suffix to device type (e.g.
UCC3808DTR–1) to order quantities of 2500 devices per reel for SOIC-8 and 2000 devices per reel for TSSOP-8.
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage (IDD ≤ 10 mA) 15 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply current 20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OUTA/OUTB source current (peak) –0.5 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OUTA/OUTB sink current (peak) 1.0 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog inputs (FB, CS) –0.3 V to VDD+0.3 V, not to exceed 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power dissipation at TA = 25°C (N Package) 1 W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power dissipation at TA = 25°C (D Package) 650 mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power dissipation at TA = 25°C (PW Package) 400 mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Junction temperature, TJ–55°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature (soldering, 10 sec.) 300°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, an d
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
‡Currents are positive into, negative out of the specified terminal. Consult Packaging Section of the Power Supply Control Data Book (TI Literature
Number SLUD003) for thermal limitations and considerations of packages.
SLUS168D – APRIL 1999 – REVISED AUGUST 2002
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electrical characteristics, TA = 0°C to 70°C for the UCC3808–x, –40°C to 85°C for the UCC2808–x and –55°C
to 125°C for the UCC1808–x, VDD = 10 V (See Note 6), 1 µF capacitor from VDD to GND, R = 22 kΩ, C = 330 pF,
TA = TJ, (unless otherwise specified)
oscillator section
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Oscillator frequency 175 194 213 kHz
Oscillator amplitude/VDD See Note 1 0.44 0.5 0.56 V/V
error amplifier section
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Input voltage COMP = 2 V 1.95 2 2.05 V
Input bias current –1 1 µA
Open loop voltage gain 60 80 dB
COMP sink current FB = 2.2 V, COMP = 1 V 0.3 2.5 mA
COMP source current FB = 1.3 V, COMP = 3.5 V –0.2 –0.5 mA
PWM section
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Maximum duty cycle Measured at OUTA or OUTB 48% 49% 50%
Minimum duty cycle COMP = 0 V 0%
current sense section
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Gain See Note 2 1.9 2.2 2.5 V/V
Maximum input signal COMP = 5 V, See Note 3 0.45 0.5 0.55 V
CS to output delay COMP = 3.5 V, CS from 0 to 600 mV 100 200 ns
CS source current –200 nA
Over current threshold 0.7 0.75 0.8 V
COMP to CS offset CS = 0 V 0.35 0.8 1.2 V
NOTES: 1. Measured at RC. Signal amplitude tracks VDD.
2. Gain is defined by: A +
DVCOMP
DVCS ,0vVCS v0.4 V,
3. Parameter measured at trip point of latch with FB at 0V.
4. Start threshold and zener shunt threshold track one another.
5. For UCCx808–1, set VDD above the start threshold before setting at 10 V.
6. Does not include current in the external oscillator network.
SLUS168D – APRIL 1999 – REVISED AUGUST 2002
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electrical characteristics, TA = 0°C to 70°C for the UCC3808–x, –40°C to 85°C for the UCC2808–x and –55°C
to 125°C for the UCC1808–x, VDD = 10 V (See Note 6), 1 µF capacitor from VDD to GND, R = 22 kΩ, C = 330 pF,
TA = TJ, (unless otherwise specified)
output section
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
OUT low level I = 100 mA 0.5 1 V
OUT high level I = –50 mA, VDD – OUT 0.5 1 V
Rise time CL = 1 nF 25 60 ns
Fall time CL = 1 nF 25 60 ns
undervoltage lockout section
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Start threshold
UCCx808–1, See Note 6 11.5 12.5 13.5 V
Start threshold UCCx808–2 4.1 4.3 4.5 V
Minim m operating oltage after start
UCCx808–1 7.6 8.3 9 V
Minimum operating voltage after start UCCx808–2 3.9 4.1 4.3 V
H steresis
UCCx808–1 3.5 4.2 5.1 V
Hysteresis UCCx808–2 0.1 0.2 0.3 V
soft start section
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
COMP rise time FB = 1.8 V, rise from 0.5 V to 4 V 3.5 20 ms
overall section
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Startup current VDD < start threshold 130 260 µA
Operating supply current FB = 0 V, CS = 0 V, See Note 5 and 6 1 2 mA
VDD zener shunt voltage IDD = 10 mA, See Note 4 13 14 15 V
NOTES: 1. Measured at RC. Signal amplitude tracks VDD.
2. Gain is defined by: A +
DVCOMP
DVCS ,0vVCS v0.4 V,
3. Parameter measured at trip point of latch with FB at 0V.
4. Start threshold and zener shunt threshold track one another.
5. For UCCx808–1, set VDD above the start threshold before setting at 10 V.
6. Does not include current in the external oscillator network.
SLUS168D – APRIL 1999 – REVISED AUGUST 2002
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pin descriptions
COMP: COMP is the output of the error amplifier and the input of the PWM comparator. The error amplifier in the
UCC3808 is a true low-output impedance, 2-MHz operational amplifier. As such, the COMP pin can both source and
sink current. However, the error amplifier is internally current limited, so that zero duty cycle can be externally forced
by pulling COMP to GND.
The UCC3808 family features built-in full cycle soft start. Soft start is implemented as a clamp on the maximum COMP
voltage.
CS: The input to the PWM, peak current, and overcurrent comparators. The overcurrent comparator is only intended
for fault sensing. Exceeding the overcurrent threshold will cause a soft start cycle.
FB: The inverting input to the error amplifier. For best stability, keep FB lead length as short as possible and FB stray
capacitance as small as possible.
GND: Reference ground and power ground for all functions. Due to high currents, and high frequency operation of
the UCC3808, a low impedance circuit board ground plane is highly recommended.
OUTA and OUTB: Alternating high current output stages. Both stages are capable of driving the gate of a power
MOSFET. Each stage is capable of 500-mA peak source current, and 1-A peak sink current.
The output stages switch at half the oscillator frequency, in a push/pull configuration. When the voltage on the RC
pin is rising, one of the two outputs is high, but during fall time, both outputs are off. This dead time between the two
outputs, along with a slower output rise time than fall time, insures that the two outputs can not be on at the same
time. This dead time is typically 60 ns to 200 ns and depends upon the values of the timing capacitor and resistor.
The high-current output drivers consist of MOSFET output devices, which switch from VDD to GND. Each output
stage also provides a very low impedance to overshoot and undershoot. This means that in many cases, external
schottky clamp diodes are not required.
RC: The oscillator programming pin. The UCC3808’s oscillator tracks VDD and GND internally, so that variations in
power supply rails minimally affect frequency stability. Figure 1 shows the oscillator block diagram.
Only tw o c o m ponents are required to program the oscillator: a resistor (tied to the VDD and RC), and a capacitor (tied
to the RC and GND). The approximate oscillator frequency is determined by the simple formula:
fOSCILLATOR +1.41
RC
where frequency is in hertz, resistance in ohms, and capacitance in farads. The recommended range of timing
resistors i s between 10 kΩ and 200 kΩ and range of timing capacitors is between 100 pF and 1000 pF. Timing resistors
less than 10 kΩ should be avoided.
For best performance, keep the timing capacitor lead to GND as short as possible, the timing resistor lead from VDD
as short as possible, and the leads between timing components and RC as short as possible. Separate ground and
VDD traces to the external timing network are encouraged.
VDD: The power input connection for this device. Although quiescent VDD current is very low, total supply current
will be higher, depending on OUTA and OUTB current, and the programmed oscillator frequency. Total VDD current
is the sum of quiescent VDD current and the average OUT current. Knowing the operating frequency and the
MOSFET gate charge (Qg), average OUT current can be calculated from:
IOUT +Qg F, where F is frequency
To prevent noise problems, bypass VDD to GND with a ceramic capacitor as close to the chip as possible along with
an electrolytic capacitor. A 1-µF decoupling capacitor is recommended.
SLUS168D – APRIL 1999 – REVISED AUGUST 2002
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pin descriptions (continued)
NOTE: The oscillator generates a sawtooth waveform on RC. During the RC rise time, the output stages alternate on time, but
both stages are of f during the RC fall time. The output stages switch a ½ the oscillator frequency, with guaranteed duty
cycle of < 50% for both outputs.
UDG–97009
Figure 1. Block Diagram for Oscillator
APPLICATION INFORMATION
A 200-kHz push-pull application circuit with a full wave rectifier is shown in Figure 2. The output, VO, provides 5 V
at 75 W maximum and is electrically isolated from the input. Since the UCC3808 is a peak current mode controller
the 2N2222A emitter following amplifier (buffers the CT waveform) provides slope compensation which is necessary
for duty ratios greater than 50%. Capacitor decoupling is very important with a single ground IC controller, and a 1
µF is suggested as close to the IC as possible. The controller supply is a series RC for start-up, paralleled with a bias
winding on the output inductor used in steady state operation.
Isolation is provided by an optocoupler with regulation done on the secondary side using the UC3965 Precision
Reference with Low Offset Error Amplifier. Small signal compensation with tight voltage regulation is achieved using
this part on the secondary side. Many choices exist for the output inductor depending on cost, volume, and
mechanicall strength. Several design options are iron powder, molypermalloy (MPP), or a ferrite core with an air gap
as shown here. The main power transformer is a low profile design, EFD size 25, using Magnetics Inc. P material
which is a good choice at this frequency and temperature. The input voltage may range from 36 V dc to 72 V dc.
SLUS168D – APRIL 1999 – REVISED AUGUST 2002
7
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APPLICATION INFORMATION
UDG-00142
UCC3808D-1
RC
4.99 kΩ
4.99 kΩ
432 Ω
0.1 µF10 µF
20 kΩ
330 pF
86.6 kΩ
0.01µF
1 kV
NS1
NS2
NP1
NP2 680µF 0.01µF
470 pF
4700 pF 20 kΩ
19.1 kΩ
COMP
19.1 kΩ
200 Ω
LOOP B
LOOP A
2.2 Ω
0.2 Ω
2 kΩ
330 pF
1000 pF
62 Ω
62 Ω
1000 pF
2.2 Ω
51 kΩ
1/4 W
0.47µF4700µF
VIN
36 V TO 72 V
+
–
BYV
28–200 BYV
28–200
32CTQ030ER28
8:2 +
VO
5 V 50 W
5678
4321
H11A1
4
5
6
3
2
1
U3
CURRENT
SENSE
PRIMARY
GROUND
–
IRF640 IRF640
20 kΩ
2N2907
0.1 µF
240Ω
0.1 µF
31TL431
2
10 Ω
12
EF25 7µH
1mH DF02SGICT
2.80 kΩ
VDD OUTA OUTB GND
RCCSFBCOMP
Figure 2. Typical Application Diagram: 48-V In, 5-V, 50-W Output
SLUS168D – APRIL 1999 – REVISED AUGUST 2002
8www.ti.com
APPLICATION INFORMATION
Figure 3
0 50 100 150 200 250
0
10
100
1000
CT=1000pF
CT=820pF CT=560pF
CT=330pF
CT=220pF
CT=100pF
Frequency – kHz
FREQUENCY
vs
TIMING RESISTOR
RT – Timing Resistor – kΩ
Figure 4
0 200 400 800 1000 1200
0
4
8
14
IDD With 1 nF
Load
IDD Without
Load
600
2
6
10
12
VDD = 10 V, T = 25 C
IDD – mA
IDD
vs
OSCILLATOR FREQUENCY
Oscillator Frequency – kHz
Figure 5
–55 –35 –15 5 25 45 65 85 105 125
0
0.2
0.4
0.6
0.8
1.0
1.2
COMP – CS Offset – V
CS OFFSET
vs
TEMPERATURE
Temperature – °C
Figure 6
Frequency – Hz
Phase Margin - Degrees
Gain dB
ERROR AMPLIFIER GAIN AND PHASE
RESPONSE
vs
FREQUENCY
1100 10000 1000000
0
10
20
30
40
50
60
70
80
90
0
20
40
60
80
100
120
140
160
180
Phase
Gain
Figure 7
020 40 60 80 100
0
20
40
60
80
100
120
CT=1000pF
CT=820pF
CT=560pF
CT=330pF
CT=220pF
CT=100pF
Dead Time – ns
DEAD TIME
vs
TIMING RESISTOR
RT – Timing Resistor – kΩ
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
UCC2808D-1 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCC2808D-2 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC2808D-2G4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC2808DTR-1 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCC2808DTR-1G4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCC2808DTR-2 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC2808DTR-2/1G4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCC2808DTR-2G4 PREVIEW SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCC2808N-1 ACTIVE PDIP P 8 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-NC-NC-NC
UCC2808N-2 ACTIVE PDIP P 8 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-NC-NC-NC
UCC2808N-2G4 ACTIVE PDIP P 8 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-NC-NC-NC
UCC3808D-1 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCC3808D-2 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC3808D-2G4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC3808DTR-1 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCC3808DTR-1G4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCC3808DTR-2 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC3808DTR-2G4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC3808N-1 ACTIVE PDIP P 8 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-NC-NC-NC
UCC3808N-1G4 ACTIVE PDIP P 8 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-NC-NC-NC
UCC3808N-2 ACTIVE PDIP P 8 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-NC-NC-NC
UCC3808N-2G4 ACTIVE PDIP P 8 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-NC-NC-NC
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
PACKAGE OPTION ADDENDUM
www.ti.com 13-Sep-2005
Addendum-Page 1
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 13-Sep-2005
Addendum-Page 2
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