LP339
LP339 Ultra-Low Power Quad Comparator
Literature Number: SNOSBE0A
LP339
Ultra-Low Power Quad Comparator
General Description
The LP339 consists of four independent voltage compara-
tors designed specifically to operate from a single power
supply and draw typically 60 µA of power supply drain cur-
rent over a wide range of power supply voltages. Operation
from split supplies is also possible and the ultra-low power
supply drain current is independent of the power supply volt-
age. These comparators also feature a common-mode
range which includes ground, even when operated from a
single supply.
Applications include limit comparators, simple
analog-to-digital converters, pulse, square and time delay
generators; VCO’s; multivibrators; high voltage logic gates.
The LP339 was specifically designed to interface with the
CMOS logic family. The ultra-low supply current makes the
LP339 valuable in battery powered applications.
Advantages
nUltra-low power supply drain suitable for battery
applications
nSingle supply operation
nSensing at ground
nCompatible with CMOS logic family
nPin-out identical to LM339
Features
nUltra-low power supply current drain
(60 µA)—independent of the supply voltage
(75 µW/comparator at +5 V
DC
)
nLow input biasing current: 3 nA
nLow input offset current: ±0.5 nA
nLow input offset voltage: ±2mV
nInput common-mode voltage includes ground
nOutput voltage compatible with MOS and CMOS logic
nHigh output sink current capability (30 mA at V
O
=2 V
DC
)
nSupply Input protected against reverse voltages
Schematic and Connection Diagrams
Typical Applications (V
+
= 5.0 V
DC
)
DS005226-1
DS005226-2
Order Number LP339M for S.O. Package
See NS Package Number M14A
Order Number LP339N for Dual-In-Line Package
See NS Package Number N14A
Basic Comparator
DS005226-3
Driving CMOS
DS005226-4
August 2000
LP339 Ultra-Low Power Quad Comparator
© 2000 National Semiconductor Corporation DS005226 www.national.com
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage 36 V
DC
or ±18 V
DC
Differential Input Voltage ±36 V
DC
Input Voltage −0.3 V
DC
to 36 V
DC
Power Dissipation (Note 2)
Molded DIP 570 mW
Output Short Circuit to GND (Note 3) Continuous
Input Current V
IN
<−0.3 V
DC
(Note 4) 50 mA
Operating Temperature Range 0˚C to +70˚C
Storage Temperature Range −65˚ to +150˚C
Soldering Information:
Dual-In-Line Package (10 sec.) +260˚C
S.O. Package:
Vapor Phase (60 sec.) +215˚C
Infrared (15 sec.) +220˚C
See AN-450 “Surface Mounting Methods and Their Effect on
Product Reliability” for other methods of soldering surface
mount devices.
Electrical Characteristics
(V+=5 V
DC
) (Note 5)
Parameter Conditions Min Typ Max Units
Input Offset Voltage T
A
=25˚C (Note 10) ±2±5mV
DC
Input Bias Current I
IN
(+) or I
IN
(−) with the 2.5 25 nA
DC
Output in the Linear Range, T
A
=25˚C (Note 6)
Input Offset Current I
IN
(+)−I
IN
(−), T
A
=25˚C ±0.5 ±5nA
DC
Input Common T
A
=25˚C (Note 7) 0 V+−1.5 V
DC
Mode Voltage Range
Supply Current R
L
=Infinite on all Comparators, T
A
=25˚C 60 100 µA
DC
Voltage Gain V
O
=1V
DC
to 11 V
DC
, 500 V/mV
R
L
=15 kΩ,V
+
=15 V
DC
,T
A
=25˚C
Large Signal V
IN
=TTL Logic Swing, V
REF
=1.4 V
DC
, 1.3 µSec
Response Time V
RL
=5 V
DC
,R
L
=5.1 kΩ,T
A
=25˚C
Response Time V
RL
=5 V
DC
,R
L
=5.1 kΩ,T
A
=25˚C (Note 8) 8 µSec
Output Sink Current V
IN
(−)=1 V
DC
,V
IN
(+)=0, V
O
=2 V
DC
,1530mA
DC
T
A
=25˚C (Note 12)
V
O
=0.4 V
DC
0.20 0.70 mA
DC
Output Leakage Current V
IN
(+)=1 V
DC
,V
IN
(−)=0, V
O
=5 V
DC
,T
A
=25˚C 0.1 nA
DC
Input Offset Voltage (Note 10) ±9mV
DC
Input Offset Current I
IN
(+)−I
IN
(−) ±1±15 nA
DC
Input Bias Current I
IN
(+) or I
IN
(−) with Output in Linear Range 4 40 nA
DC
Input Common Single Supply 0 V+−2.0 V
DC
Mode Voltage Range
Output Sink Current V
IN
(−)=1 V
DC
,V
IN
(+)=0, V
O
=2 V
DC
10 mA
DC
Output Leakage Current V
IN
(+)=1 V
DC
,V
IN
(−)=0, V
O
=30 V
DC
1.0 µA
DC
Differential Input Voltage All V
IN’s
≥0V
DC
(or V
−
on split supplies) (Note 9) 36 V
DC
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is func-
tional, but do not guarantee specific performance limits.
Note 2: For elevated temperature operation, Tjmax is 125˚C for the LP339. θja (junction to ambient) is 175˚C/W for the LP339N and 120˚C/W for the LP339M when
either device is soldered in a printed circuit board in a still air environment. The low bias dissipation and the “ON-OFF” characteristic of the outputs keeps the chip
dissipation very small (PD≤100 mW), provided the output transistors are allowed to saturate.
Note 3: Short circuits from the output to V+can cause excessive heating and eventual destruction. The maximum output current is approximately 50 mA.
Note 4: This input current will only exist when the voltage at any of the input leads is driven negative. It is due to the collector-base junction of the input PNP tran-
sistors becoming forward biased and thereby acting as input clamp diodes. In addition to this diode action, there is also lateral NPN parasitic transistor action on the
IC chip. This transistor action can cause the output voltage of the comparators to go to the V+ voltage level (or to ground for a large input overdrive) for the time du-
ration that an input is driven negative. This is not destructive and normal output states will re-establish when the input voltage, which is negative, again returns to a
value greater than −0.3 VDC (TA=25˚C).
Note 5: These specifications apply for V+=5VDC and 0˚C≤TA≤70˚ C, unless otherwise stated. The temperature extremes are guaranteed but not 100% production
tested. These parameters are not used to calculate outgoing AQL.
Note 6: The direction of the input current is out of the IC due to the PNP input stage. This current is essentially constant, independent of the state of the output, so
no loading change exists on the reference or the input lines as long as the common-mode range is not exceeded.
Note 7: The input common-mode voltage or either input voltage should not be allowed to go negative by more than 0.3V. The upper end of the common-mode volt-
age range is V+−1.5V (TA=25˚C), but either or both inputs can go to 30 VDC without damage.
Note 8: The response time specified is for a 100 mV input step with 5 mV overdrive. For larger overdrive signals 1.3 µs can be obtained. See Typical Performance
Characteristics section.
LP339
www.national.com 2
Electrical Characteristics (Continued)
Note 9: Positive excursions of input voltage may exceed the power supply level.As long as the other voltage remains within the common-mode range, the compara-
tor will provide a proper output state. The low input voltage state must not be less than −0.3 VDC (or 0.3 VDC below the magnitude of the negative power supply, if
used) at TA=25˚C.
Note 10: At output switch point, VO=1.4V, RS=0Ωwith V+from 5 VDC; and over the full input common-mode range (0 VDC to V+−1.5 VDC).
Note 11: For input signals that exceed V+, only the overdriven comparator is affected. With a 5V supply, VIN should be limited to 25V maximum, and a limiting resistor
should be used on all inputs that might exceed the positive supply.
Note 12: The output sink current is a function of the output voltage. The LP339 has a bi-modal output section which allows it to sink large currents via a Darlington
connection at output voltages greater than approximately 1.5 VDC and sink lower currents below this point. (See typical characteristics section and applications sec-
tion).
Typical Performance Characteristics
Supply Current
DS005226-35
Input Current
DS005226-36
Output Sink Current
DS005226-37
Output Sink Current
DS005226-38
Response Times for
Various Input
Overdrives —
Negative Transition
DS005226-39
Response Times for
Various Input
Overdrives —
Positive Transition
DS005226-40
LP339
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Application Hints
All pins of any unused comparators should be tied to the
negative supply.
The bias network of the LP339 establishes a drain current
which is independent of the magnitude of the power supply
voltage over the range of from 2 V
DC
to 30 V
DC
.
It is usually unnecessary to use a bypass capacitor across
the power supply line.
The differential input voltage may be larger than V+ without
damaging the device. Protection should be provided to pre-
vent the input voltages from going negative more than −0.3
V
DC
(at 25˚C). An input clamp diode can be used as shown
in the application section.
The output section of the LP339 has two distinct modes of
operation-a Darlington mode and a grounded emitter mode.
This unique drive circuit permits the LP339 to sink 30 mA at
V
O
=2 V
DC
(Darlington mode) and 700 µA at V
O
=0.4 V
DC
(grounded emitter mode).
Figure 1
is a simplified schematic
diagram of the LP339 output section.
Notice that the output section is configured in a Darlington
connection (ignoring Q3). Therefore, if the output voltage is
held high enough (V
O
≥1V
DC
), Q1 is not saturated and the
output current is limited only by the product of the betas of
Q1, Q2 and I1 (and the 60ΩR
SAT
of Q2). The LP339 is thus
capable of driving LED’s, relays, etc. in this mode while
maintaining an ultra-low power supply current of typically
60 µA.
If transistor Q3 were omitted, and the output voltage allowed
to drop below about 0.8 V
DC
, transistor Q1 would saturate
and the output current would drop to zero. The circuit would,
therefore, be unable to “pull” low current loads down to
ground (or the negative supply, if used). Transistor Q3 has
been included to bypass transistor Q1 under these condi-
tions and apply the current I1 directly to the base of Q2. The
output sink current is now approximately I1 times the beta of
Q2 (700 µA at V
O
=0.4 V
DC
). The output of the LP339 exhib-
its a bi-modal characteristic with a smooth transition be-
tween modes. (See Output Sink Current graphs in Typical
Performance Characteristics section.)
It is also important to note that in both cases the output is an
uncommitted collector. Therefore, many collectors can be
tied together to provide an output OR’ing function. An output
pull-up resistor can be connected to any available power
supply voltage within the permitted power supply voltage
range and there is no restriction on this voltage due to the
magnitude of the voltage which is applied to the V+ terminal
of the LP339 package.
DS005226-11
FIGURE 1.
LP339
www.national.com 4
Typical Applications (V
+
=15 V
DC
)
One-Shot Multivibrator
DS005226-13
Time-Delay Generator
DS005226-15
LP339
www.national.com5
Typical Applications (V
+
=15 V
DC
) (Continued)
ORing the Outputs
DS005226-16
Squarewave Oscillator
DS005226-17
LP339
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Typical Applications (V
+
=15 V
DC
) (Continued)
Three Level Audio Peak Indicator
DS005226-19
LED Driver
DS005226-22
Pulse Generator
DS005226-18
LP339
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Typical Applications (V
+
=15 V
DC
) (Continued)
Bi-Stable Multivibrator
DS005226-21
Relay Driver
DS005226-23
Buzzer Driver
DS005226-24
Comparator With 60 mA Sink Capability
DS005226-25
LP339
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Typical Applications (V
+
=15 V
DC
) (Continued)
Non-Inverting Comparator with Hysteresis
DS005226-26
Inverting Comparator with Hysteresis
DS005226-27
Comparing Input Voltages
of Opposite Polarity
DS005226-28
Basic Comparator
DS005226-29
Output Strobing
DS005226-30
Transducer Amplifier
DS005226-31
Zero Crossing Detector (Single Power Supply)
DS005226-32
LP339
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Typical Applications (V
+
=15 V
DC
) (Continued)
Split-Supply Applications
Zero Crossing Detector
DS005226-33
Comparator With a Negative Reference
DS005226-34
LP339
www.national.com 10
Physical Dimensions inches (millimeters) unless otherwise noted
S.O. Package (M)
Order Number LP339M or LP339MX
NS Package M14A
Molded Dual-In-Line Package (N)
Order Number LP339N
NS Package Number N14A
LP339
www.national.com11
Notes
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www.national.com
LP339 Ultra-Low Power Quad Comparator
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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