DATA SHEET
ICS831752AGI REVISION A JUNE 28, 2012
1 ©2012 Integrated Device Technology, Inc.
Clock Switch for ATCA/AMC and
PCIe Applications
ICS831752I
General Description
The ICS831752I is a high-performance, differential HCSL clock
switch. The device is designed for the routing of PCIe clock signals in
ATCA/AMC system and is optimized for PCIe Gen 1, Gen 2 and Gen
3. The device has one differential, bi-directional I/O (FCLK) for
connection to ATCA clock sources and to clock receivers through a
connector. The differential clock input CLK is the local clock input and
the HCSL output Q is the local clock output. In the common clock
mode, FCLK serves as an input and is routed to the differential HCSL
output Q. There are two local clock modes. In the local clock mode 0,
CLK is the input, Q is the clock output and FCLK is in high-impedance
state. In the local clock mode 1, CLK is the input and both Q and
FCLK are the outputs of the locally generated PCIe clock signal. The
ICS831752I is characterized to operate from a 3.3V power or 2.5V
power supply. The ICS831752I supports the switching of PCI Express
(2.5 Gb/s), Gen 2 (5 Gb/s) and Gen 3 (8 Gb/s) clock signals.
Features
•Clock switch for PCIe and ATCA/AMC applications
•Supports local and common ATCA/AMC clock modes
•Bi-directional clock I/O FCLK:
- When operating as an output, FCLK is a source-terminated
HCSL signal.
- When operating as an input, FCLK accepts HCSL, LVDS and
LVPECL levels.
•Local clock input (CLK) accepts HCSL, LVDS and LVPECL
differential signals
•Local HCSL clock output (Q)
•Maximum input/output clock frequency: 500MHz
•Maximum input/output data rate: 1000Mb/s (NRZ)
•LVCMOS interface levels for the control inputs
•PCI Express (2.5 Gb/S), Gen 2 (5 Gb/s) and Gen 3 (8 Gb/s) jitter
compliant
•Full 3.3V or 2.5V supply voltage
•Lead-free (RoHS 6) 16-lead TSSOP package
•-40°C to 85°C ambient operating temperature
ICS831752I
16-lead TSSOP
4.4mm x 5.0mm x 0.925mmpackage body
G Package, Top View
Pin Assignment
16 IREF
15 GND
14 VDD
13 Q
12 nQ
11 GND
10 VDD
9 nc
DIR_SEL 1
nOEFCLK 2
VDD 3
FCLK 4
nFCLK 5
GND 6
CLK 7
nCLK 8
Block Diagram
Pulldown
Pullup/Pulldown
Pullup
Pulldown
FCLK
nFCLK
CLK
nCLK
nOEFCLK
DIR_SEL
IREF
1
0
Q
nQ
1=disable
50 50 50 50
22.33
22..33
ICS831752I Data Sheet CLOCK SWITCH FOR ATCA/AMC AND PCIe APPLICATIONS
ICS831752AGI REVISION A JUNE 28, 2012
2 ©2012 Integrated Device Technology, Inc.
Table 1. Pin Descriptions
NOTE: Pullup and pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Function Table
Table 3. Direction Control Function Table
NOTE: X = 0 or 1
Number Name Type Description
1 DIR_SEL Input Pulldown Direction control for the FCLK I/O. Works in conjunction with nOEFCLK.
See Table 3 for function. LVCMOS/LVTTL interface levels.
2 nOEFCLK Input Pullup Output enable for the FCLK I/O output. Works in conjunction with
DIR_SEL. See Table 3 for function. LVCMOS/LVTTL interface levels.
3, 10, 14 VDD Power Core and output power supply pin.
4, 5 FCLK, nFCLK I/O
Differential I/O. Signal direction is controlled by DIR_SEL. Accepts
differential signals when operating as an input. Differential HCSL
signals when operating as an output. Internal source termination can be
disabled. See Table 3 for function.
6, 11, 15 GND Power Power supply ground.
7 CLK Input Pulldown Non-inverting input.
8 nCLK Input Pulldown/Pullup Inverting differential clock input.
9ncUnused No connect.
12, 13 nQ, Q Output Differential output pair. HCSL interface levels.
16 IREF Input
An external fixed precision resistor (475Ω) from this pin to ground
provides a reference current used for the differential current-mode Q
and FCLK outputs.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
CIN Input Capacitance 4pF
RPULLDOWN Input Pulldown Resistor 51 kΩ
RPULLUP Input Pullup Resistor 51 kΩ
Input Input
Operation FCLK FunctionDIR_SEL nOEFCLK
00Local clock mode 0. The input signal at CLK is routed to
both outputs Q and FCLK.
Differential HCSL output with internal 50Ω source
termination
0 (default) 1 (default) Local clock mode 1. The input signal at CLK is routed to
the output Q.
Output is disabled (high impedance). Internal 50Ω
termination is disabled.
1X
Common reference clock mode. FCLK is the clock input.
Q is the clock output.
Differential clock input. Internal 50Ω source
termination is disabled as well as output driver and
22.33Ω resistors.
ICS831752I Data Sheet CLOCK SWITCH FOR ATCA/AMC AND PCIe APPLICATIONS
ICS831752AGI REVISION A JUNE 28, 2012
3 ©2012 Integrated Device Technology, Inc.
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Supply Voltage, VDD 4.6V
Inputs, VI-0.5V to VDD + 0.5V
Outputs, VO-0.5V to VDD + 0.5V
Package Thermal Impedance, θJA 81.2°C/W (0 mps)
Storage Temperature, TSTG -65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = 3.3V±5% or 2.5V±5%, TA = -40°C to 85°C
Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V±5% or 2.5V±5%, TA = -40°C to 85°C
Item Rating
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD Core Supply Voltage 3.135 3.3 3.465 V
2.375 2.5 2.625 V
IDD Power Supply Current 64 mA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VIH Input High Voltage VDD = 3.3V 2 VDD + 0.3 V
VDD = 2.5V 1.7 VDD + 0.3 V
VIL Input Low Voltage VDD = 3.3V -0.3 0.8 V
VDD = 2.5V -0.3 0.7 V
IIH Input High Current DIR_SEL VDD = VIN = 2.625V or 3.465V 150 µA
nOEFLCK 5µA
IIL Input Low Current DIR_SEL VDD = 2.625V or 3.465V, VIN = 0V -5 µA
nOEFLCK -150 µA
ICS831752I Data Sheet CLOCK SWITCH FOR ATCA/AMC AND PCIe APPLICATIONS
ICS831752AGI REVISION A JUNE 28, 2012
4 ©2012 Integrated Device Technology, Inc.
Table 4C. Differential DC Characteristics, VDD = 3.3V±5% or 2.5V±5%, TA = -40°C to 85°C
NOTE 1: VIL should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as VIH.
AC Electrical Characteristics
Table 5A. PCI Express Jitter Specifications, VDD = 3.3V±5% or 2.5V±5%, TA = -40°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions. For additional information, refer to the PCI Express Application Note section in the datasheet.
NOTE: PCI Express JItter Specifications apply to FCLK and nFCLK and Q,nQ operating as outputs. The source generator used in the PCI
Express Jitter measurements is the Stanford Research Systems CG635 2.0GHz Synthezized Clock Generator.
NOTE 1: Peak-to-Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express
Gen 1 is 86ps peak-to-peak for a sample size of 106 clock periods.
NOTE 2: RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and
reporting the worst case results for each evaluation band. Maximum limit for PCI Express Gen 2 is 3.1ps RMS for tREFCLK_HF_RMS (High
Band) and 3.0ps RMS for tREFCLK_LF_RMS (Low Band).
NOTE 3: RMS jitter after applying system transfer function for the common clock architecture. This specification is based on the PCI Express
Base Specification Revision 0.7, October 2009 and is subject to change pending the final release version of the specification.
NOTE 4: This parameter is guaranteed by characterization. Not tested in production.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
IIH
Input
High Current CLK, nCLK VDD = VIN = 3.3V 150 µA
IIL
Input
Low Current
CLK VDD = 3.3V, VIN = 0V -5 µA
nCLK VDD = 3.3V, VIN = 0V -150 µA
VPP Peak-to-Peak Voltage; NOTE 1 0.15 1.3 V
VCMR
Common Mode Input Voltage;
NOTE 1, 2 0.5 VDD – 0.85 V
Symbol Parameter Test Conditions Minimum Typical Maximum
PCIe Industry
Specification Units
tj
(PCIe Gen 1)
Phase Jitter
Peak-to-Peak;
NOTE 1, 4
ƒ = 100MHz
Evaluation Band: 0Hz - Nyquist
(clock frequency/2)
9.95 15.5 86 ps
tREFCLK_HF_RMS
(PCIe Gen 2)
Phase Jitter RMS;
NOTE 2, 4
ƒ = 100MHz
High Band: 1.5MHz - Nyquist
(clock frequency/2)
0.82 1.12 3.1 ps
tREFCLK_LF_RMS
(PCIe Gen 2)
Phase Jitter RMS;
NOTE 2, 4
ƒ = 100MHz
Low Band: 10kHz - 1.5MHz 0.04 0.08 3.0 ps
tREFCLK_RMS
(PCIe Gen 3)
Phase Jitter RMS;
NOTE 3, 4
ƒ = 100MHz
Evaluation Band: 0Hz - Nyquist
(clock frequency/2)
0.153 0.203 0.8 ps
ICS831752I Data Sheet CLOCK SWITCH FOR ATCA/AMC AND PCIe APPLICATIONS
ICS831752AGI REVISION A JUNE 28, 2012
5 ©2012 Integrated Device Technology, Inc.
Table 5B. HCSL AC Characteristics, VDD = 3.3V±5% or 2.5V±5%, TA = -40°C to 85°C
NOTE: Measurements taken with Q output and FCLK output.
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: All measurements were taken with FCLK, nFCLK and Q, nQ operating as outputs unless otherwise noted.
NOTE 1: Measured from the differential input cross point to the differential output crossing point.
NOTE 2: Measurement taken from differential waveform.
NOTE 3: Measurement from -150mV to +150mV on the differential waveform (derived from Q minus nQ). The signal must be monotonic
through the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing.
NOTE 4: TSTABLE is the time the differential clock must maintain a minimum ±150mV differential voltage after rising/falling edges before it is
allowed to drop back into the VRB ±100 differential range. See Parameter Measurement Information Section.
NOTE 5: Measurement taken from single-ended waveform.
NOTE 6: Defined as the maximum instantaneous voltage including overshoot. See Parameter Measurement Information Section.
NOTE 7: Defined as the minimum instantaneous voltage including undershoot. See Parameter Measurement Information Section.
NOTE 8: Measured at crossing point where the instantaneous voltage value of the rising edge of Q equals the falling edge of nQ.
See Parameter Measurement Information Section.
NOTE 9: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing
points for this measurement. See Parameter Measurement Information Section.
NOTE 10: Defined as the total variation of all crossing voltage of rising Q and falling nQ. This is the maximum allowed variance in the VCROSS
for any particular system. See Parameter Measurement Information Section.
NOTE 11: Input duty cycle must be 50%.
NOTE 12: Matching applies to rising edge rate for Q and falling edge rate for nQ. It is measured using a ±75mV window centered on the
median crosspoint where Q meets nQ falling. The median crosspoint is used to calculate the voltage thresholds the oscilloscope is to use for
the edge rate calculations. The rise edge rate of Q should be compared to the fall edge rate of nQ, the maximum allowed difference should not
exceed 20% of the slowest edge rate.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
fOUT Output Frequency 100 500 MHz
tjit Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Plot
100MHz, Integration Range:
12kHz – 20MHz 0.3 0.505 ps
tPD Propagation Delay, NOTE 1
FCLK to Q 1.75 3.65 ns
CLK to Q 1.95 3.90 ns
CLK to FCLK 1.50 3.70 ns
MUXISOL Mux Isolation f = 100MHz -70 dB
Edge Rate Rise/Fall Edge Rate; NOTE 2, 3 0.6 4 V/ns
VRB Ringback Voltage; NOTE 2, 4 -100 100 mV
tSTABLE
Time before VRB is allowed;
NOTE 2, 4 500 ps
VMAX
Absolute Max Output Voltage;
NOTE 5, 6 800 1350 mV
VMIN
Absolute Min Output Voltage;
NOTE 5, 7 -300 -35 mV
VCROSS
Absolute Crossing Voltage;
NOTE 5, 8, 9 250 385 650 mV
∆VCROSS
Total Variation of VCROSS over all
edges; NOTE 5, 8, 10 40 140 mV
odc Output Duty Cycle; NOTE 11 f ≤ 312.5MHz 44 50 56 %
f > 312.5MHz 40 50 60
ICS831752I Data Sheet CLOCK SWITCH FOR ATCA/AMC AND PCIe APPLICATIONS
ICS831752AGI REVISION A JUNE 28, 2012
6 ©2012 Integrated Device Technology, Inc.
Parameter Measurement Information
HCSL Output Load AC Test Circuit
Differential Measurement Points for Rise/Fall Edge Rate
Single-ended Measurement Points for Absolute Cross
Point/Swing
Differential Input Levels
MUX_ISOLATION
Single-ended Measurement Points for Delta Cross Point
475Ω
50Ω
50Ω
HCSL
GND
0V
SCOPE
IREF
1MΩ
1MΩ
VDD
Q - nQ
-150mV
+150mV
0.0V
Fall Edge RateRise Edge Rate
V
CROSS_MAX
V
CROSS_MIN
V
MAX
V
MIN
nQ
Q
V
CMR
Cross Points
V
PP
nCLK,
nFCLK
CLK,
FCLK
VDD
GND
Amplitude (dB)
A0
Spectrum of Output Signal Q
MUX_ISOL = A0 – A1
(fundamental) Frequency
ƒ
MUX selects static input
MUX selects active
input clock signal
A1
∆
V
CROSS
nQ
Q
ICS831752I Data Sheet CLOCK SWITCH FOR ATCA/AMC AND PCIe APPLICATIONS
ICS831752AGI REVISION A JUNE 28, 2012
7 ©2012 Integrated Device Technology, Inc.
Parameter Measurement Information, continued
Propagation Delay
Differential Measurement Points for Ringback
Propagation Delay
tPD
nCLK,
nFCLK
CLK,
FCLK
nQ
Q
TSTABLE
V
RB
Q - nQ
-150mV
V
RB
= -100mV
V
RB
= +100mV
+150mV
0.0V
V
RB
TSTABLE
tPD
nCLK
CLK
nFCLK
FCLK
ICS831752I Data Sheet CLOCK SWITCH FOR ATCA/AMC AND PCIe APPLICATIONS
ICS831752AGI REVISION A JUNE 28, 2012
8 ©2012 Integrated Device Technology, Inc.
Applications Information
Recommended Termination
HC SL
R1
50
R4
47 5
R2
50
V DD =3. 3V or 2. 5V
IREF nQ
Q
HCSL Driv er
ICS831752iVDD
Receiver
+
-
High Impedance Input
GND
Trac e Length < 0.5"
Figure 1. Interface for ICS831752I HCSL driver with built-in 50 ohm Termination to Receiver
with High Input Impedance
ICS831752I Data Sheet CLOCK SWITCH FOR ATCA/AMC AND PCIe APPLICATIONS
ICS831752AGI REVISION A JUNE 28, 2012
9 ©2012 Integrated Device Technology, Inc.
Recommendations for Unused Input Pins
Inputs:
LVCMOS Control Pins
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional protection.
A 1kΩ resistor can be used.
CLK/nCLK Inputs
For applications not requiring the use of the differential input, both
CLK and nCLK can be left floating. Though not required, but for
additional protection, a 1kΩ resistor can be tied from CLK to ground.
FCLK/nFCLK Pins
In case FCLK/nFCLK are unused, one of the following two
configurations can be used: either FCLK/nFCLK are configured as an
output (DIR_SEL = 1) and left floating, or FCLK/nFCLK are
configured as an input (DIR_SEL = 0). In this case 1kΩ pulldown is
required on FCLK and 1kΩ Pullup is required on nFCLK.
Wiring the Differential Input to Accept Single-Ended Levels
Figure 2 shows how a differential input can be wired to accept single
ended levels. The reference voltage V1= VDD/2 is generated by the
bias resistors R1 and R2. The bypass capacitor (C1) is used to help
filter noise on the DC bias. This bias circuit should be located as close
to the input pin as possible. The ratio of R1 and R2 might need to be
adjusted to position the V1in the center of the input voltage swing. For
example, if the input clock swing is 2.5V and VDD = 3.3V, R1 and R2
value should be adjusted to set V1 at 1.25V. The values below are for
when both the single ended swing and VDD are at the same voltage.
This configuration requires that the sum of the output impedance of
the driver (Ro) and the series resistance (Rs) equals the transmission
line impedance. In addition, matched termination at the input will
attenuate the signal in half. This can be done in one of two ways.
First, R3 and R4 in parallel should equal the transmission line
impedance. For most 50Ω applications, R3 and R4 can be 100Ω. The
values of the resistors can be increased to reduce the loading for
slower and weaker LVCMOS driver. When using single-ended
signaling, the noise rejection benefits of differential signaling are
reduced. Even though the differential input can handle full rail
LVCMOS signaling, it is recommended that the amplitude be
reduced. The datasheet specifies a lower differential amplitude,
however this only applies to differential signals. For single-ended
applications, the swing can be larger, however VIL cannot be less
than -0.3V and VIH cannot be more than VDD + 0.3V. Though some
of the recommended components might not be used, the pads
should be placed in the layout. They can be utilized for debugging
purposes. The datasheet specifications are characterized and
guaranteed by using a differential signal.
Figure 2. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels
ICS831752I Data Sheet CLOCK SWITCH FOR ATCA/AMC AND PCIe APPLICATIONS
ICS831752AGI REVISION A JUNE 28, 2012
10 ©2012 Integrated Device Technology, Inc.
3.3V Differential Clock Input Interface
The CLK/nCLK accepts HCSL, LVDS and LVPECL and other
differential signals. Both differential signals must meet the VPP and
VCMR input requirements. Figures 2A to 2E show interface examples
for the CLK/nCLK input driven by the most common driver types. The
input interfaces suggested here are examples only. If the driver is
from another vendor, use their termination recommendation. Please
consult with the vendor of the driver component to confirm the driver
termination requirements. The figures below also apply to FCLK/
nFCLK operating as an input.
Figure 3A. CLK/nCLK Input Driven by a 3.3V LVPECL
Driver
Figure 3C. CLK/nCLK Input Driven by a 3.3V LVPECL
Driver
Figure 3E. CLK/nCLK Input Driven by a 3.3V LVDS Driver
Figure 3B. CLK/nCLK Input Driven by a 3.3V HCSL Driver
Figure 3D. CLK/nCLK Input Driven by a 3.3V LVPECL
Driver with AC Couple
CLK
nCLK
Differential
Input
LVPECL
3.3V
Zo = 50Ω
Zo = 50Ω
3.3V
R1
50Ω
R2
50Ω
R2
50Ω
R3
125
R4
125
R1
84
R2
84
3.3V
Zo = 50Ω
Zo = 50Ω
CLK
nCLK
3.3V
3.3V
LVPECL Differential
Input
3.3V
R1
100
LVDS
CLK
nCLK
3.3V
Differential
Input
Zo = 50Ω
Zo = 50Ω
HCSL
*R3 33Ω
*R4 33Ω
CLK
nCLK
3.3V 3.3V
Zo = 50Ω
Zo = 50Ω
Differential
Input
R1
50Ω
R2
50Ω
*Optional – R3 and R4 can be 0Ω
ICS831752I Data Sheet CLOCK SWITCH FOR ATCA/AMC AND PCIe APPLICATIONS
ICS831752AGI REVISION A JUNE 28, 2012
11 ©2012 Integrated Device Technology, Inc.
2.5V Differential Clock Input Interface
The CLK/nCLK accepts HCSL, LVDS and LVPECL and other
differential signals. Both differential signals must meet the VPP and
VCMR input requirements. Figures 4A to 4 E show interface examples
for the CLK/nCLK input driven by the most common driver types. The
input interfaces suggested here are examples only. If the driver is
from another vendor, use their termination recommendation. Please
consult with the vendor of the driver component to confirm the driver
termination requirements. The figures below also apply to FCLK/
nFCLK operating as an input.
Figure 4A. CLK/nCLK Input Driven by a 2.5V LVPECL
Driver
Figure 4C. CLK/nCLK Input Driven by a 2.5V LVPECL
Driver
Figure 4E. CLK/nCLK Input Driven by a 2.5V LVDS Driver
Figure 4B. CLK/nCLK Input Driven by a 2.5V HCSL Driver
Figure 4D. CLK/nCLK Input Driven by a 2.5V LVPECL
Driver with AC Couple
C
L
K
nC
L
K
D
i
ffe
r
e
nti
a
l
I
nput
L
VPE
CL
2
.
5V
Zo
=
50
Zo
=
50
2
.
5V
R1
50
R2
50
R3
1
8
Ω
R3
250
R4
250
R1
6
2.
5
Ω
R2
6
2.
5
2
.
5V
Zo
=
50
Ω
Zo
=
50
Ω
C
L
K
nC
L
K
2
.
5V
2
.
5V
L
VPE
CL
D
i
ffe
r
e
nti
a
l
I
nput
2
.
5V
R1
1
00
L
VD
S
C
L
K
nC
L
K
2
.
5V
D
i
ffe
r
e
nti
a
l
I
nput
Zo
=
50
Ω
Zo
=
50
Ω
HCSL
*
R
3
33
*R4
33
C
L
K
nC
L
K
2
.
5V
2
.
5V
Zo
=
50
Ω
Zo
=
50
Ω
D
i
ffe
r
e
nti
a
l
I
nput
R1
50
Ω
R2
50
*O
ptional
–
R
3
a
n
d
R4
ca
n
be
0
Ω
R1
125
R2
125
R5
100 - 200
R6
100 - 200
CLK
nCLK
2.5V LVPECL
2.5V
Zo = 50Ω
Zo = 50Ω
2.5V
Differential
Input
C1
C2
R3
84
R4
84
2.5V
ICS831752I Data Sheet CLOCK SWITCH FOR ATCA/AMC AND PCIe APPLICATIONS
ICS831752AGI REVISION A JUNE 28, 2012
12 ©2012 Integrated Device Technology, Inc.
PCI Express Application Note
PCI Express jitter analysis methodology models the system
response to reference clock jitter. The block diagram below shows the
most frequently used Common Clock Architecture in which a copy of
the reference clock is provided to both ends of the PCI Express Link.
In the jitter analysis, the transmit (Tx) and receive (Rx) serdes PLLs
are modeled as well as the phase interpolator in the receiver. These
transfer functions are called H1, H2, and H3 respectively. The overall
system transfer function at the receiver is:
Ht s() H3s() H1s() H2s()–[]×=
The jitter spectrum seen by the receiver is the result of applying this
system transfer function to the clock spectrum X(s) and is:
Ys() Xs() H3s()×H1s() H2s()–[]×=
In order to generate time domain jitter numbers, an inverse Fourier
T
ransform is performed on X(s)*H3(s) * [H1(s) - H2(s)].
PCI Express Common Clock Architecture
For PCI Express Gen 1, one transfer function is defined and the
evaluation is performed over the entire spectrum: DC to Nyquist (e.g
for a 100MHz reference clock: 0Hz – 50MHz) and the jitter result is
reported in peak-peak.
PCIe Gen 1 Magnitude of Transfer Function
For PCI Express Gen 2, two transfer functions are defined with 2
evaluation ranges and the final jitter number is reported in rms. The
two evaluation ranges for PCI Express Gen 2 are 10kHz – 1.5MHz
(Low Band) and 1.5MHz – Nyquist (High Band). The plots show the
individual transfer functions as well as the overall transfer function Ht.
PCIe Gen 2A Magnitude of Transfer Function
PCIe Gen 2B Magnitude of Transfer Function
For PCI Express Gen 3, one transfer function is defined and the
evaluation is performed over the entire spectrum. The transfer
function parameters are different from Gen 1 and the jitter result is
reported in RMS.
PCIe Gen 3 Magnitude of Transfer Function
For a more thorough overview of PCI Express jitter analysis
methodology, please refer to IDT Application Note PCI Express
Reference Clock Requirements.
ICS831752I Data Sheet CLOCK SWITCH FOR ATCA/AMC AND PCIe APPLICATIONS
ICS831752AGI REVISION A JUNE 28, 2012
13 ©2012 Integrated Device Technology, Inc.
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS831752I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS831752I is the sum of the core power plus the analog power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
• Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 64mA = 221.76mW
Power dissipation for the FCLK, nFCLK input internal 50ohm termination. Assume the FCLK, nFCLK input is driven by a HCSL driver. Logic
High input current ~ 17mA. Logic low current ~ 0mA.
• Power (input) = 50ohm * (17mA)2 = 14.45mW
Total Power_MAX (3.465V, with all outputs switching) = 221.76mW + 14.45mW = 236.21mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 81.2°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.236W * 81.2°C/W = 104.2°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 6. Thermal Resistance θJA for 16 Lead TSSOP, Forced Convection
θJA vs. Air Flow
Meters per Second 012.5
Multi-Layer PCB, JEDEC Standard Test Boards 81.2°C/W 73.9°C/W 70.2°C/W
ICS831752I Data Sheet CLOCK SWITCH FOR ATCA/AMC AND PCIe APPLICATIONS
ICS831752AGI REVISION A JUNE 28, 2012
14 ©2012 Integrated Device Technology, Inc.
Package Outline and Package Dimensions
Table 7. θJA vs. Air Flow Table for a 16 Lead TSSOP
Transistor Count
The transistor count for ICS831752I is: 446
Package Outline and Package Dimensions
Package Outline - G Suffix for 16 Lead TSSOP Table 8. Package Dimensions for 16 Lead TSSOP
Reference Document: JEDEC Publication 95, MO-153
θJA vs. Air Flow
Meters per Second 012.5
Multi-Layer PCB, JEDEC Standard Test Boards 81.2°C/W 73.9°C/W 70.2°C/W
All Dimensions in Millimeters
Symbol Minimum Maximum
N16
A1.20
A1 0.05 0.15
A2 0.80 1.05
b0.19 0.30
c0.09 0.20
D4.90 5.10
E6.40 Basic
E1 4.30 4.50
e0.65 Basic
L0.45 0.75
α0° 8°
aaa 0.10
ICS831752I Data Sheet CLOCK SWITCH FOR ATCA/AMC AND PCIe APPLICATIONS
ICS831752AGI REVISION A JUNE 28, 2012
15 ©2012 Integrated Device Technology, Inc.
Ordering Information
Table 9. Ordering Information
NOTE: Parts that are ordered with an “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant
Part/Order Number Marking Package Shipping Packaging Temperature
831752AGILF 831752AL Lead-Free, 16-lead TSSOP Tube -40°C to 85°C
831752AGILFT 831752AL Lead-Free, 16-lead TSSOP Tape & Reel -40°C to 85°C
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
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ICS831752I Data Sheet CLOCK SWITCH FOR ATCA/AMC AND PCIe APPLICATIONS
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