Clock Switch for ATCA/AMC and PCIe Applications ICS831752I DATA SHEET General Description Features The ICS831752I is a high-performance, differential HCSL clock switch. The device is designed for the routing of PCIe clock signals in ATCA/AMC system and is optimized for PCIe Gen 1, Gen 2 and Gen 3. The device has one differential, bi-directional I/O (FCLK) for connection to ATCA clock sources and to clock receivers through a connector. The differential clock input CLK is the local clock input and the HCSL output Q is the local clock output. In the common clock mode, FCLK serves as an input and is routed to the differential HCSL output Q. There are two local clock modes. In the local clock mode 0, CLK is the input, Q is the clock output and FCLK is in high-impedance state. In the local clock mode 1, CLK is the input and both Q and FCLK are the outputs of the locally generated PCIe clock signal. The ICS831752I is characterized to operate from a 3.3V power or 2.5V power supply. The ICS831752I supports the switching of PCI Express (2.5 Gb/s), Gen 2 (5 Gb/s) and Gen 3 (8 Gb/s) clock signals. * * * Clock switch for PCIe and ATCA/AMC applications * Local clock input (CLK) accepts HCSL, LVDS and LVPECL differential signals * * * * * Local HCSL clock output (Q) * * * Full 3.3V or 2.5V supply voltage Pin Assignment DIR_SEL nOEFCLK VDD FCLK nFCLK GND CLK nCLK 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 Supports local and common ATCA/AMC clock modes Bi-directional clock I/O FCLK: - When operating as an output, FCLK is a source-terminated HCSL signal. - When operating as an input, FCLK accepts HCSL, LVDS and LVPECL levels. Maximum input/output clock frequency: 500MHz Maximum input/output data rate: 1000Mb/s (NRZ) LVCMOS interface levels for the control inputs PCI Express (2.5 Gb/S), Gen 2 (5 Gb/s) and Gen 3 (8 Gb/s) jitter compliant Lead-free (RoHS 6) 16-lead TSSOP package -40C to 85C ambient operating temperature IREF GND VDD Q nQ GND VDD nc ICS831752I 16-lead TSSOP 4.4mm x 5.0mm x 0.925mmpackage body G Package, Top View Block Diagram 1 FCLK nFCLK Q nQ 22.33 50 50 0 22..33 50 50 1=disable CLK nCLK nOEFCLK DIR_SEL IREF ICS831752AGI REVISION A JUNE 28, 2012 Pulldown Pullup/Pulldown Pullup Pulldown 1 (c)2012 Integrated Device Technology, Inc. ICS831752I Data Sheet CLOCK SWITCH FOR ATCA/AMC AND PCIe APPLICATIONS Table 1. Pin Descriptions Number Name Type Description 1 DIR_SEL Input Pulldown 2 nOEFCLK Input Pullup 3, 10, 14 VDD Power Direction control for the FCLK I/O. Works in conjunction with nOEFCLK. See Table 3 for function. LVCMOS/LVTTL interface levels. Output enable for the FCLK I/O output. Works in conjunction with DIR_SEL. See Table 3 for function. LVCMOS/LVTTL interface levels. Core and output power supply pin. Differential I/O. Signal direction is controlled by DIR_SEL. Accepts differential signals when operating as an input. Differential HCSL signals when operating as an output. Internal source termination can be disabled. See Table 3 for function. 4, 5 FCLK, nFCLK I/O 6, 11, 15 GND Power 7 CLK Input Pulldown 8 nCLK Input Pulldown/Pullup 9 nc Unused No connect. 12, 13 nQ, Q Output Differential output pair. HCSL interface levels. 16 IREF Input Power supply ground. Non-inverting input. Inverting differential clock input. An external fixed precision resistor (475) from this pin to ground provides a reference current used for the differential current-mode Q and FCLK outputs. NOTE: Pullup and pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance 4 pF RPULLDOWN Input Pulldown Resistor 51 k RPULLUP Input Pullup Resistor 51 k Function Table Table 3. Direction Control Function Table Input Input DIR_SEL nOEFCLK Operation FCLK Function 0 0 Local clock mode 0. The input signal at CLK is routed to both outputs Q and FCLK. Differential HCSL output with internal 50 source termination 0 (default) 1 (default) Local clock mode 1. The input signal at CLK is routed to the output Q. Output is disabled (high impedance). Internal 50 termination is disabled. 1 X Common reference clock mode. FCLK is the clock input. Q is the clock output. Differential clock input. Internal 50 source termination is disabled as well as output driver and 22.33 resistors. NOTE: X = 0 or 1 ICS831752AGI REVISION A JUNE 28, 2012 2 (c)2012 Integrated Device Technology, Inc. ICS831752I Data Sheet CLOCK SWITCH FOR ATCA/AMC AND PCIe APPLICATIONS Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDD + 0.5V Package Thermal Impedance, JA 81.2C/W (0 mps) Storage Temperature, TSTG -65C to 150C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VDD = 3.3V5% or 2.5V5%, TA = -40C to 85C Symbol Parameter VDD Core Supply Voltage IDD Power Supply Current Test Conditions Minimum Typical Maximum Units 3.135 3.3 3.465 V 2.375 2.5 2.625 V 64 mA Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V5% or 2.5V5%, TA = -40C to 85C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH Input High Current IIL Input Low Current Test Conditions Minimum VDD = 3.3V Maximum Units 2 VDD + 0.3 V VDD = 2.5V 1.7 VDD + 0.3 V VDD = 3.3V -0.3 0.8 V VDD = 2.5V -0.3 0.7 V 150 A 5 A DIR_SEL nOEFLCK VDD = VIN = 2.625V or 3.465V DIR_SEL nOEFLCK ICS831752AGI REVISION A JUNE 28, 2012 VDD = 2.625V or 3.465V, VIN = 0V 3 Typical -5 A -150 A (c)2012 Integrated Device Technology, Inc. ICS831752I Data Sheet CLOCK SWITCH FOR ATCA/AMC AND PCIe APPLICATIONS Table 4C. Differential DC Characteristics, VDD = 3.3V5% or 2.5V5%, TA = -40C to 85C Symbol Parameter Test Conditions IIH Input High Current IIL Input Low Current VPP Peak-to-Peak Voltage; NOTE 1 0.15 1.3 V VCMR Common Mode Input Voltage; NOTE 1, 2 0.5 VDD - 0.85 V CLK, nCLK Minimum Typical VDD = VIN = 3.3V Maximum Units 150 A CLK VDD = 3.3V, VIN = 0V -5 A nCLK VDD = 3.3V, VIN = 0V -150 A NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode input voltage is defined as VIH. AC Electrical Characteristics Table 5A. PCI Express Jitter Specifications, VDD = 3.3V5% or 2.5V5%, TA = -40C to 85C Symbol Parameter tj (PCIe Gen 1) Phase Jitter Peak-to-Peak; NOTE 1, 4 tREFCLK_HF_RMS Phase Jitter RMS; NOTE 2, 4 (PCIe Gen 2) Typical Maximum PCIe Industry Specification Units = 100MHz Evaluation Band: 0Hz - Nyquist (clock frequency/2) 9.95 15.5 86 ps = 100MHz High Band: 1.5MHz - Nyquist (clock frequency/2) 0.82 1.12 3.1 ps Test Conditions Minimum tREFCLK_LF_RMS (PCIe Gen 2) Phase Jitter RMS; NOTE 2, 4 = 100MHz Low Band: 10kHz - 1.5MHz 0.04 0.08 3.0 ps tREFCLK_RMS (PCIe Gen 3) Phase Jitter RMS; NOTE 3, 4 = 100MHz Evaluation Band: 0Hz - Nyquist (clock frequency/2) 0.153 0.203 0.8 ps NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. For additional information, refer to the PCI Express Application Note section in the datasheet. NOTE: PCI Express JItter Specifications apply to FCLK and nFCLK and Q,nQ operating as outputs. The source generator used in the PCI Express Jitter measurements is the Stanford Research Systems CG635 2.0GHz Synthezized Clock Generator. NOTE 1: Peak-to-Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1 is 86ps peak-to-peak for a sample size of 106 clock periods. NOTE 2: RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and reporting the worst case results for each evaluation band. Maximum limit for PCI Express Gen 2 is 3.1ps RMS for tREFCLK_HF_RMS (High Band) and 3.0ps RMS for tREFCLK_LF_RMS (Low Band). NOTE 3: RMS jitter after applying system transfer function for the common clock architecture. This specification is based on the PCI Express Base Specification Revision 0.7, October 2009 and is subject to change pending the final release version of the specification. NOTE 4: This parameter is guaranteed by characterization. Not tested in production. ICS831752AGI REVISION A JUNE 28, 2012 4 (c)2012 Integrated Device Technology, Inc. ICS831752I Data Sheet CLOCK SWITCH FOR ATCA/AMC AND PCIe APPLICATIONS Table 5B. HCSL AC Characteristics, VDD = 3.3V5% or 2.5V5%, TA = -40C to 85C Symbol Parameter fOUT Output Frequency tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Plot tPD Propagation Delay, NOTE 1 Test Conditions Minimum 100MHz, Integration Range: 12kHz - 20MHz Typical Maximum Units 100 500 MHz 0.3 0.505 ps FCLK to Q 1.75 3.65 ns CLK to Q 1.95 3.90 ns CLK to FCLK 1.50 3.70 ns MUXISOL Mux Isolation f = 100MHz -70 dB Edge Rate Rise/Fall Edge Rate; NOTE 2, 3 0.6 4 V/ns VRB Ringback Voltage; NOTE 2, 4 -100 100 mV tSTABLE Time before VRB is allowed; NOTE 2, 4 500 VMAX Absolute Max Output Voltage; NOTE 5, 6 VMIN Absolute Min Output Voltage; NOTE 5, 7 -300 -35 VCROSS Absolute Crossing Voltage; NOTE 5, 8, 9 250 385 650 mV VCROSS Total Variation of VCROSS over all edges; NOTE 5, 8, 10 40 140 mV odc Output Duty Cycle; NOTE 11 % ps 800 1350 mV mV f 312.5MHz 44 50 56 f > 312.5MHz 40 50 60 NOTE: Measurements taken with Q output and FCLK output. NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: All measurements were taken with FCLK, nFCLK and Q, nQ operating as outputs unless otherwise noted. NOTE 1: Measured from the differential input cross point to the differential output crossing point. NOTE 2: Measurement taken from differential waveform. NOTE 3: Measurement from -150mV to +150mV on the differential waveform (derived from Q minus nQ). The signal must be monotonic through the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing. NOTE 4: TSTABLE is the time the differential clock must maintain a minimum 150mV differential voltage after rising/falling edges before it is allowed to drop back into the VRB 100 differential range. See Parameter Measurement Information Section. NOTE 5: Measurement taken from single-ended waveform. NOTE 6: Defined as the maximum instantaneous voltage including overshoot. See Parameter Measurement Information Section. NOTE 7: Defined as the minimum instantaneous voltage including undershoot. See Parameter Measurement Information Section. NOTE 8: Measured at crossing point where the instantaneous voltage value of the rising edge of Q equals the falling edge of nQ. See Parameter Measurement Information Section. NOTE 9: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for this measurement. See Parameter Measurement Information Section. NOTE 10: Defined as the total variation of all crossing voltage of rising Q and falling nQ. This is the maximum allowed variance in the VCROSS for any particular system. See Parameter Measurement Information Section. NOTE 11: Input duty cycle must be 50%. NOTE 12: Matching applies to rising edge rate for Q and falling edge rate for nQ. It is measured using a 75mV window centered on the median crosspoint where Q meets nQ falling. The median crosspoint is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. The rise edge rate of Q should be compared to the fall edge rate of nQ, the maximum allowed difference should not exceed 20% of the slowest edge rate. ICS831752AGI REVISION A JUNE 28, 2012 5 (c)2012 Integrated Device Technology, Inc. ICS831752I Data Sheet CLOCK SWITCH FOR ATCA/AMC AND PCIe APPLICATIONS Parameter Measurement Information VDD SCOPE 50 VDD nCLK, nFCLK 1M V HCSL Cross Points PP V CMR CLK, FCLK 50 IREF GND 1M GND 475 0V Differential Input Levels HCSL Output Load AC Test Circuit Spectrum of Output Signal Q MUX selects active input clock signal Rise Edge Rate Amplitude (dB) A0 Fall Edge Rate +150mV 0.0V -150mV MUX_ISOL = A0 - A1 MUX selects static input A1 Q - nQ (fundamental) Frequency MUX_ISOLATION Differential Measurement Points for Rise/Fall Edge Rate VMAX nQ nQ VCROSS_MAX VCROSS VCROSS_MIN Q Q VMIN Single-ended Measurement Points for Delta Cross Point Single-ended Measurement Points for Absolute Cross Point/Swing ICS831752AGI REVISION A JUNE 28, 2012 6 (c)2012 Integrated Device Technology, Inc. ICS831752I Data Sheet CLOCK SWITCH FOR ATCA/AMC AND PCIe APPLICATIONS Parameter Measurement Information, continued nCLK, nFCLK nCLK CLK, FCLK CLK nQ nFCLK FCLK Q tPD tPD Propagation Delay Propagation Delay TSTABLE VRB +150mV VRB = +100mV 0.0V VRB = -100mV -150mV Q - nQ VRB TSTABLE Differential Measurement Points for Ringback ICS831752AGI REVISION A JUNE 28, 2012 7 (c)2012 Integrated Device Technology, Inc. ICS831752I Data Sheet CLOCK SWITCH FOR ATCA/AMC AND PCIe APPLICATIONS Applications Information Recommended Termination VDD=3.3V or 2.5V VDD ICS831752i HCSL Driver Trace Length < 0.5" Q + IREF nQ HCSL R4 475 R1 50 Receiver High Impedance Input R2 50 GND Figure 1. Interface for ICS831752I HCSL driver with built-in 50 ohm Termination to Receiver with High Input Impedance ICS831752AGI REVISION A JUNE 28, 2012 8 (c)2012 Integrated Device Technology, Inc. ICS831752I Data Sheet CLOCK SWITCH FOR ATCA/AMC AND PCIe APPLICATIONS Recommendations for Unused Input Pins Inputs: LVCMOS Control Pins FCLK/nFCLK Pins All control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. In case FCLK/nFCLK are unused, one of the following two configurations can be used: either FCLK/nFCLK are configured as an output (DIR_SEL = 1) and left floating, or FCLK/nFCLK are configured as an input (DIR_SEL = 0). In this case 1k pulldown is required on FCLK and 1k Pullup is required on nFCLK. CLK/nCLK Inputs For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from CLK to ground. Wiring the Differential Input to Accept Single-Ended Levels Figure 2 shows how a differential input can be wired to accept single ended levels. The reference voltage V1= VDD/2 is generated by the bias resistors R1 and R2. The bypass capacitor (C1) is used to help filter noise on the DC bias. This bias circuit should be located as close to the input pin as possible. The ratio of R1 and R2 might need to be adjusted to position the V1in the center of the input voltage swing. For example, if the input clock swing is 2.5V and VDD = 3.3V, R1 and R2 value should be adjusted to set V1 at 1.25V. The values below are for when both the single ended swing and VDD are at the same voltage. This configuration requires that the sum of the output impedance of the driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the input will attenuate the signal in half. This can be done in one of two ways. First, R3 and R4 in parallel should equal the transmission line impedance. For most 50 applications, R3 and R4 can be 100. The values of the resistors can be increased to reduce the loading for slower and weaker LVCMOS driver. When using single-ended signaling, the noise rejection benefits of differential signaling are reduced. Even though the differential input can handle full rail LVCMOS signaling, it is recommended that the amplitude be reduced. The datasheet specifies a lower differential amplitude, however this only applies to differential signals. For single-ended applications, the swing can be larger, however VIL cannot be less than -0.3V and VIH cannot be more than VDD + 0.3V. Though some of the recommended components might not be used, the pads should be placed in the layout. They can be utilized for debugging purposes. The datasheet specifications are characterized and guaranteed by using a differential signal. Figure 2. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels ICS831752AGI REVISION A JUNE 28, 2012 9 (c)2012 Integrated Device Technology, Inc. ICS831752I Data Sheet CLOCK SWITCH FOR ATCA/AMC AND PCIe APPLICATIONS 3.3V Differential Clock Input Interface from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. The figures below also apply to FCLK/ nFCLK operating as an input. The CLK/nCLK accepts HCSL, LVDS and LVPECL and other differential signals. Both differential signals must meet the VPP and VCMR input requirements. Figures 2A to 2E show interface examples for the CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. If the driver is 3.3V 3.3V 3.3V 3.3V Zo = 50 CLK *R3 33 Zo = 50 CLK Zo = 50 nCLK R1 50 Zo = 50 Differential Input LVPECL R2 50 nCLK HCSL *R4 33 R1 50 R2 50 Differential Input *Optional - R3 and R4 can be 0 R2 50 Figure 3B. CLK/nCLK Input Driven by a 3.3V HCSL Driver Figure 3A. CLK/nCLK Input Driven by a 3.3V LVPECL Driver 3.3V 3.3V 3.3V R3 125 R4 125 Zo = 50 CLK Zo = 50 nCLK Differential Input LVPECL R1 84 R2 84 Figure 3C. CLK/nCLK Input Driven by a 3.3V LVPECL Driver Figure 3D. CLK/nCLK Input Driven by a 3.3V LVPECL Driver with AC Couple 3.3V 3.3V Zo = 50 CLK R1 100 Zo = 50 LVDS nCLK Differential Input Figure 3E. CLK/nCLK Input Driven by a 3.3V LVDS Driver ICS831752AGI REVISION A JUNE 28, 2012 10 (c)2012 Integrated Device Technology, Inc. ICS831752I Data Sheet CLOCK SWITCH FOR ATCA/AMC AND PCIe APPLICATIONS 2.5V Differential Clock Input Interface from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. The figures below also apply to FCLK/ nFCLK operating as an input. The CLK/nCLK accepts HCSL, LVDS and LVPECL and other differential signals. Both differential signals must meet the VPP and VCMR input requirements. Figures 4A to 4 E show interface examples for the CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. If the driver is 2.5V 2.5V 2.5V 2.5V Zo = 50 CLK *R3 Zo = 50 33 CLK Zo = 50 nCLK R1 50 Zo = 50 Differential Input LVPECL R2 50 nCLK *R4 HCSL Differential Input 33 R1 50 R2 50 *Optional - R3 and R4 can be 0 R3 18 Figure 4B. CLK/nCLK Input Driven by a 2.5V HCSL Driver Figure 4A. CLK/nCLK Input Driven by a 2.5V LVPECL Driver 2.5V 2.5V 2.5V R3 250 2.5V R4 250 2.5V Zo = 50 R3 84 2.5V CLK 2.5V LVPECL Zo = 50 C1 Zo = 50 C2 R4 84 Zo = 50 CLK nCLK LVPECL R1 62.5 R2 62.5 Differential Input nCLK R5 100 - 200 Figure 4C. CLK/nCLK Input Driven by a 2.5V LVPECL Driver R6 100 - 200 R1 125 R2 125 Differential Input Figure 4D. CLK/nCLK Input Driven by a 2.5V LVPECL Driver with AC Couple 2.5V 2.5V Zo = 50 CLK R1 100 Zo = 50 LVDS nCLK Differential Input Figure 4E. CLK/nCLK Input Driven by a 2.5V LVDS Driver ICS831752AGI REVISION A JUNE 28, 2012 11 (c)2012 Integrated Device Technology, Inc. ICS831752I Data Sheet CLOCK SWITCH FOR ATCA/AMC AND PCIe APPLICATIONS PCI Express Application Note PCI Express jitter analysis methodology models the system response to reference clock jitter. The block diagram below shows the most frequently used Common Clock Architecture in which a copy of the reference clock is provided to both ends of the PCI Express Link. In the jitter analysis, the transmit (Tx) and receive (Rx) serdes PLLs are modeled as well as the phase interpolator in the receiver. These transfer functions are called H1, H2, and H3 respectively. The overall system transfer function at the receiver is: Ht ( s ) = H3 ( s ) x [ H1 ( s ) - H2 ( s ) ] The jitter spectrum seen by the receiver is the result of applying this system transfer function to the clock spectrum X(s) and is: Y ( s ) = X ( s ) x H3 ( s ) x [ H1 ( s ) - H2 ( s ) ] In order to generate time domain jitter numbers, an inverse Fourier Transform is performed on X(s)*H3(s) * [H1(s) - H2(s)]. PCIe Gen 2A Magnitude of Transfer Function PCI Express Common Clock Architecture For PCI Express Gen 1, one transfer function is defined and the evaluation is performed over the entire spectrum: DC to Nyquist (e.g for a 100MHz reference clock: 0Hz - 50MHz) and the jitter result is reported in peak-peak. PCIe Gen 2B Magnitude of Transfer Function For PCI Express Gen 3, one transfer function is defined and the evaluation is performed over the entire spectrum. The transfer function parameters are different from Gen 1 and the jitter result is reported in RMS. PCIe Gen 1 Magnitude of Transfer Function For PCI Express Gen 2, two transfer functions are defined with 2 evaluation ranges and the final jitter number is reported in rms. The two evaluation ranges for PCI Express Gen 2 are 10kHz - 1.5MHz (Low Band) and 1.5MHz - Nyquist (High Band). The plots show the individual transfer functions as well as the overall transfer function Ht. ICS831752AGI REVISION A JUNE 28, 2012 PCIe Gen 3 Magnitude of Transfer Function For a more thorough overview of PCI Express jitter analysis methodology, please refer to IDT Application Note PCI Express Reference Clock Requirements. 12 (c)2012 Integrated Device Technology, Inc. ICS831752I Data Sheet CLOCK SWITCH FOR ATCA/AMC AND PCIe APPLICATIONS Power Considerations This section provides information on power dissipation and junction temperature for the ICS831752I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS831752I is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. * Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 64mA = 221.76mW Power dissipation for the FCLK, nFCLK input internal 50ohm termination. Assume the FCLK, nFCLK input is driven by a HCSL driver. Logic High input current ~ 17mA. Logic low current ~ 0mA. * Power (input) = 50ohm * (17mA)2 = 14.45mW Total Power_MAX (3.465V, with all outputs switching) = 221.76mW + 14.45mW = 236.21mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125C. Limiting the internal transistor junction temperature, Tj, to 125C ensures that the bond wire and bond pad temperature remains below 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 81.2C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.236W * 81.2C/W = 104.2C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 6. Thermal Resistance JA for 16 Lead TSSOP, Forced Convection JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards ICS831752AGI REVISION A JUNE 28, 2012 0 1 2.5 81.2C/W 73.9C/W 70.2C/W 13 (c)2012 Integrated Device Technology, Inc. ICS831752I Data Sheet CLOCK SWITCH FOR ATCA/AMC AND PCIe APPLICATIONS Package Outline and Package Dimensions Table 7. JA vs. Air Flow Table for a 16 Lead TSSOP JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 81.2C/W 73.9C/W 70.2C/W Transistor Count The transistor count for ICS831752I is: 446 Package Outline and Package Dimensions Package Outline - G Suffix for 16 Lead TSSOP Table 8. Package Dimensions for 16 Lead TSSOP All Dimensions in Millimeters Symbol Minimum Maximum N 16 A 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 4.90 5.10 E 6.40 Basic E1 4.30 4.50 e 0.65 Basic L 0.45 0.75 0 8 aaa 0.10 Reference Document: JEDEC Publication 95, MO-153 ICS831752AGI REVISION A JUNE 28, 2012 14 (c)2012 Integrated Device Technology, Inc. ICS831752I Data Sheet CLOCK SWITCH FOR ATCA/AMC AND PCIe APPLICATIONS Ordering Information Table 9. Ordering Information Part/Order Number 831752AGILF 831752AGILFT Marking 831752AL 831752AL Package Lead-Free, 16-lead TSSOP Lead-Free, 16-lead TSSOP Shipping Packaging Tube Tape & Reel Temperature -40C to 85C -40C to 85C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. ICS831752AGI REVISION A JUNE 28, 2012 15 (c)2012 Integrated Device Technology, Inc. ICS831752I Data Sheet CLOCK SWITCH FOR ATCA/AMC AND PCIe APPLICATIONS We've Got Your Timing Solution 6024 Silver Creek Valley Road San Jose, California 95138 Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support netcom@idt.com +480-763-2056 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT's sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. 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