NJU26102FR1 - New Japan Radio Co., Ltd.

NJU26102

Ver.2004-08-26

Digit al Signal Processor for TV

■ General Description

The NJU26102 is a digital signal processor that provides Delay, eala, ViVA2+,

PEQ, and AGC.

The NJU26102 is suitable for audio products such as TV, CD radio- cassette,

speakers system, and others.

■ Feature

• 3D Sound: eala, BBE V iVA, BBE ViVA+, BBE ViVA2+.

• Sound enhancement: B BE, Mach3Bass.

• 5band - PEQ, Tone Control.

• AGC to control sou nd-volume differe nce between channels or pro grams.

■ Digit al Signal Processor S pecification

• 24bit Fixed- point Digital Sign al Processing

• Maximum System Clock Frequency : 38MHz

• Digit al Audio Inter face : 3 Input port s / 3 Output po rts

• Master / Slave Mode

• Master Mode MCK :1/2 fclk, 1/3 fclk

ex. MCK = 384Fs(1/2) or MCK = 256Fs(1/3) at fclk=768Fs

• Two kinds of micro computer inter face

・ I2C bus (standard-mode/ 100kbps)

・ Serial interface (4 lines: clock, enable, input dat a, output dat a)

• Power Supply : 2.5V ( 3.3V Input tolerant )

• Package : QFP32-R1

The deta il hardware specification of t he NJU26102 is described in the “ NJU26100 Series Ha rdware Data

Sheet”.

■Package

NJU26102FR1

NJU26102

-Ver.2004-08-26

■ DSP Block Diagram

Fig.1 NJU26102 DSP Block Diagram

TIMING

GENERATOR

PROGRAM

CONTROL

ALU

24-BIT x 24-BIT

MULTIPLIER

ADDRESS GENERATION UNIT

FIRMWARE

ROM

DELAY

RAM DATA

RAM

SERIAL

HOST

INTERFACE

GPIO AND

CONFIGURATION

INTERFACE

SDO0~

SDI2

SEL1

SCL/SCK

SDA/SDOUT

AD1/SDIN AD2/SSb

DSP ARITHMETIC UNIT

SDI0~

SDO2

LRI

BCKI

MCK

BCKO

LRO

L/R

SERIAL AUDIO

INTERFACE

NJU26102

RESETb

■ Function Block Diagram

Fig.2 NJU26102 Function Blo ck Diagram

SDI0

SDO2

SDI1

Trim

Delay

Simulated Stereo

eala(stereo) BBE

Continuous

Siginal Det.

5Band

PEQ

AGC

SDI2 AGC HPF +

4PEQ

T.C. +

3PEQ

HPF+T.C.

+2PEQ

AGC

Master Vol.

SDO1

SDO0

Note 1. only one AGCs(*1, *2, *3) should be used.

SW1

SW4

SW10

SW8SW7SW5 SW6

SW3

SW2

BBE ViVA+ (3D, BBE, Ma ch3Bass)

BBE ViVA2+ (3D, BBE, Mach3Ba ss, AGC)

CLOCK GENERATOR

Note 2. Do not use *1AGC and *3AGC during BBE ViVA2 being in use .

WDC

SW9

BBE ViVA (3D, BBE)

BBE Mach3 Bass

3D Enhancement EQ

NJU26102

Ver.2004-08-26

■ Pin Configuration

SDO2

SDO1

SDO0

SEL1

SCL/SCK

SDA/SDOUT

AD1/SDIN

AD2/SSb

910111213141516

3231302928272625

NJU26102

VDDC

VSSC

VDDR

VSSR

VDDO

VSSO

RESETb

VDDC

VSSC

WDC

SDI0

VSSC

SDI1

SDI2

LRI

BCKI

MCK

BCKO

LRO

Fig.3 NJU26102 Pin Co nfiguration

■ Pin Description

Table 1 Pin Description

No. Symbol I/O Description No. Symbol I/O Description

1 SDO2 O Audio Dat a Output 2 L/R 17 VDDC -- Core Power Supply +2.5V

2 SDO1 O Audio Dat a Output 1 L/R 18 VDDC -- Core Power Supply +2.5V

3 SDO0 O Audio Dat a Output 0 L/R 19 VSSC -- Core GND

4 SEL1 I *2 Select I2C or Serial bus 20 VSSC -- Cor e GND

5 SCL/SCK I I2C Cloc k / Serial Clock 21 VDDR -- I/O Power Supply +2.5V

6 SDA/SDOUT

I/O I2C I/O / Serial Out put 22 VDDR -- I/O Power Supply +2.5V

7 AD1/SDIN I I2C Address / Serial Input 23 VSSR -- I/O GND

8 AD2/SSb I I2C Address / Serial Enable 24 VSSR -- I/O GND

9 VDDO -- OSC Power Sup ply +2.5V 25 SDI0 I Audio Data In put 0 L/R

10 XI I X’tal Clo ck Input 26 SDI1 I Audio Dat a Input 1 L/R

11 XO O OSC O utput 27 SDI2 I Audio Dat a Input 2 L/R

12 VSSO -- OSC GND 28 LRI I LR Clock Input

13 RESETb I RESET (active Low) 29 BCKI I Bit Clock Input

14 VDDC -- Core Power Supply +2.5V 30 MCK O Master Clock Out put

15 VSSC -- Core GND 31 BCKO O Bit Clock Output

16 WDC O *2 Clock for W atch Dog T imer 32 LRO O LR Clock Output

*1 I : Input, O : Outp ut, I/O : Bi-directional

*2 SEL1 : Input, WDC : Ou tput

NJU26102

-Ver.2004-08-26

■ Audio Interface

The NJU26102 audio interface provides industry serial data formats of I2S, MSB-first left-justified or MSB-first

Right-justified. The NJU26102 audio interface provides three data inputs, SDI0, SDI1, and SDI2, and three data

outputs, SDO0, SDO1, and SDO3, as shown in table 2 and 3. The input serial data is selected by the firmware

command.

Table 2 Serial Audio Input Pin

Pin No. Symbol Description

25 SDI0 Audio Dat a Input 0 L / R

26 SDI1 Audio Dat a Input 1 L / R

27 SDI2 Audio Dat a Input 2 L / R

Table 3 Serial Audio Output Pin

Pin No. Symbol Description

3 SDO0 Audio Dat a Output 0 L / R

2 SDO1 Audio Dat a Output 1 L / R

1 SDO2 Audio Dat a Output 2 L / R

■ Host Interface

The NJU26102 can be controlled via Serial Host Interface (SHI) using either of two serial bus formats : 4-Wire

serial bus or I2C bus. Data tran sf ers are in 8 bits packets (1 byte) w hen using either format. The SHI operates only

in a SLAVE fashion. A host controller connected to the interface always drives the clock (SCL / SCK) line and

initiates dat a transfers, regardle ss of the chosen communication protocol.

The detail 4-Wire Serial bus and I2C bus information are described in the “ NJU26100 Series Hardware Data

Sheet”.

■ I

2C address

AD1 and AD2 pin s are used to configure t he seven-bit SLAVE address of the seria l host interf ace. These p ins of fer

additional flexibility to SLAVE address. 4 addresses could be chosen by AD1 and AD2-pin. The AD1 and AD2-pin

addresses are decided by the co nnections of AD1 and AD2-pin. The AD1 and AD2 addresses sh ould be the same

level as AD1 and AD2-pin connections.

Table 4 I

2C Bus SLAVE Address

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

0 0 1 1 1 AD2* AD1* R/W

* AD1 or A D2 address is 0 when AD 1 or AD2-pin is “ L”. AD1 or AD2 address is 1 when AD1 or AD2-pin is “H” .

The detail I2C bus timing of the NJU26102 is described in the “ NJU26100 Series Hardware Data Sheet”.

NJU26102

Ver.2004-08-26

■ Watchdog Clock

NJU26102 output s clock pulse through WDC (Pin No. 16) during normal operation.

WDC Clock Cycle (L / H) T ime 184msec(fs=48kHz)

200msec(fs=44.1kHz)

276msec(fs=32kHz)

The NJU26102 gene rates a clock pulse through the WDC terminal after re setting the NJU26102. The WDC clock

is useful to ch eck the statu s of the NJU26102 opera tion. For example, a microcompute r monitors the WDC clock

and checks the st atus of the N JU26102. When the WDC clock pulse is lost or not normal clock cycle, the

NJU26102 does not o perate correctly. Then reset the NJU2 6102 and set up th e NJU26102 again.

NJU26102

-Ver.2004-08-26

■ Firmware Command Table

Host processor can contr ol the NJU26102 via 4-Wire seria l bus or I2C bus interface. The following table

summarizes the available use r commands.

Table 5 NJU26102 Command

No. Command Command Description

1 System S tat e DSP Mo de, Data Width, Seri al Audio Mode, Audio Clock, MCK cl ock

2 Firmware Version No.

Request Firmware V ersion No. Request

3 Firmware

Mode Sele ct eala, BBE, Mach3Bass, V iV A, V iV A +, ViVA2, PEQ, AGC, Signal Detect, Byp ass

4 Input Select /

Fs Select Input Select: SDI0, SDI1, SDI2, Delay Input Select

Sample Rate: 48, 44. 1, 32kHz

5 Input Trim 0 to -31dB

6 Master V olu me 0 to -96dB, -Inf (with Smooth Cont rol)

7 Channel Bal ance 0 to -30dB, -Inf, L/R Select

8 AGC Threshold Level Threshold Level: -6 t o -40dBFS

Noise Compre ssor Threshol d Level: -50 to -96dBFS, -I nf

Attack T ime: 0.1, 0.2, 0.5, 1, 2 , 5sec

Release T ime: 1, 2, 5msec

Ratio: 1.5:1, 2: 1, 4:1, 8:1, 20:1, -Inf:1

Boost: 0 to +24dB

Output T rim: 0 to -31dB

Position: forwa rd the 3D, EQ, backward the Master V olume

9 eala Gain 0 to +12dB

10 BBE ViVA / V iV A+

Surround Gain 0 to +6dB

11 BBE Level: 0 to -15dB

HF Adjust: 0 to 15

12 BBE ViVA2+ AGC Threshold Level: -6 to -26dBFS

Attack T ime: 0.1, 0.2, 0.5, 1, 2 , 5sec

Release T ime: 1, 2, 5msec

Ratio: 2:1, 4:1, 8:1, -Inf:1

Boost: 0 to +24dB

Output T rim: 0 to -31dB

13 BBE Mach3Bass f0: 40 to 150Hz

Q: 1.8 to 8.2

Gain: 0 to +12dB

14 EQ Mode 5band PEQ, HPF, Tone Control

15 PEQ f0 /HPF fc f0: 20 to 20kHz(1/6 oct ave, 20 point s/decade)

Q: 0.33 to 8.2

Gain: -12 to +12dB

16 Delay T ime Delay: 0 to 37.5msec (at Fs = 32kHz)

17 Continuous Signal

Detect Continuous Sign al Detect

18 NOP No Operation

In respect to det ail command inf ormation, request NJR.

NJU26102

Ver.2004-08-26

■ License Information

1. The NJU26102 is manufactured by New Japan Radio Co.,Ltd. under license from BBE Sound Inc. BBE is a

registered trademark of BBE Sound Inc. A license from BBE Sound Inc. must be required before the NJU26102

can be purchase d from New Japan Radio Co. ,Ltd.

BBE Sound, Inc.

5831 Production Drive

Huntington Beach, CA 92649 USA

Tel: 714-897-6766 Fax: 714-896-0736 http://www.bbesound.com

2. Purchase of I2C components of New Japan Radio Co. ,Ltd or one of sublicensed Associated Companies

conveys a license under the Philips I2C Patent Right s t o use the se components in an I 2C system, provided that the

system conforms to th e I2C S t andard specification as defined by Philips.

Version V1.1

[CAUTION]

The specifications on this databook are only

given for information , without any guarantee

as regards either mistak es or omissions. The

applic ation circuits in th is databook ar e

described only to show representative usages

of the product and n ot intended for the

guarantee or permission of any right including

the industrial ri

hts.