LT8672
1
Rev. D
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TYPICAL APPLICATION
FEATURES DESCRIPTION
Active Rectifier Controller
with Reverse Protection
The LT
®
8672 is an active rectifier controller for reverse
input protection. It drives an external N-channel MOSFET
to replace a power Schottky diode. Its very low quiescent
current and fast transient response meet the tough require-
ments in automotive applications where AC input signals
of up to 100kHz are present. These signals are rectified
with minimum power dissipation on the external FET,
simplifying thermal management on the PCB.
With a drop of only 20mV, the LT8672 solution eases the
minimum input voltage requirement during cold crank
and start-stop, allowing simpler and more efficient cir-
cuits. If the input power source fails or is shorted, a fast
turn-off minimizes reverse current transients. An available
shutdown mode reduces the quiescent current to 3.5μA.
An integrated auxiliary boost regulator provides the re-
quired boost voltage to turn the external FET fully on. A
power good pin signals when the external FET is ready to
take load current.
12V, 5A Automotive Reverse Battery Protection Rectification of Input Ripple
n AEC-Q100 Qualified for Automotive Applications
n Reverse Input Protection to –40V
n Improved Performance Compared to a
Schottky Diode
n Reduce Power Dissipation by >90%
n Reduce Drop to 20mV
n Ultrafast Transient Response
n Rectifies 6VP-P Up to 50kHz
n Rectifies 2VP-P Up to 100kHz
n Wide Operating Voltage Range: 3V to 42V
n Low 20µA Quiescent Current in Operation
n Low 3.5µA Shutdown Current
n Accurate 1.21V Enable Pin Threshold
n Small 10-Lead MSOP Package, 10-Lead 3mm ×
2mm DFN Package and 3mm × 2mm Side-Wettable
DFN Package
APPLICATIONS
n Automotive Battery Protection
n Industrial Supplies
n Portable Instrumentation
IPD100N06S4-03
1μF
100μH
TPSMB33A
33V
TPSMB18A
18V
8672 TA01a
VOU
T
5A
V
BATT
12V
4.7µF
+
470µF
TO SYSTEM LOADS
OFF
ON
SOURCE
DRAIN
AUXSW
AUX
PG
GND
EN/UVLO
LT8672
VOUT
2V/DIV
500µs/DIV
VBATT
2V/DIV
8672 TA01b
All registered trademarks and trademarks are the property of their respective owners.
LT8672
2
Rev. D
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PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
DRAIN ...................................................... –0.3V to 42V
SOURCE, EN/UVLO ................................... –40V to 42V
DRAIN–SOURCE ......................................... –5V to 54V
AUX .......................................................... VDRAIN + 13V
GATE ......................... VSOURCE – 0.3V to VSOURCE + 17V
GATE ................................... VAUX – 67V to VAUX + 0.3V
PG .............................................................. –0.3V to 5V
(Notes 1 and 2)
1
2
3
4
5
EN/UVLO
GND
PG
GND
NC
10
9
8
7
6
GATE
SOURCE
DRAIN
AUX
AUXSW
TOP VIEW
MS PACKAGE
10-LEAD PLASTIC MSOP
θJA = 160°C/W
TOP VIEW
11
DDB/DDBM PACKAGE
10-LEAD (3mm × 2mm) PLASTIC DFN
θJA = 76°C/W, θJC = 13.5°C/W
EXPOSED PAD (PIN 11) MUST BE SHORTED TO GND OR LEFT FLOATING
EN/UVLO
GND
PG
GND
NC
GATE
SOURCE
DRAIN
AUX
AUXSW
6
8
7
9
10
5
4
2
3
1
Operating Junction Temperature Range (Notes 3, 4)
E-, I-Grades ..................................... −40°C to 125°C
J-, H-Grades .................................... −40°C to 150°C
Storage Temperature Range ................ −65°C to 150°C
Lead Temperature (Soldering, 10 sec)
MS Package .................................................... 300°C
LT8672
3
Rev. D
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ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LT8672EMS#PBF LT8672EMS#TRPBF LTGYT 10-Lead Plastic MSOP –40°C to 125°C
LT8672IMS#PBF LT8672IMS#TRPBF LTGYT 10-Lead Plastic MSOP –40°C to 125°C
LT8672JMS#PBF LT8672JMS#TRPBF LTGYT 10-Lead Plastic MSOP –40°C to 150°C
LT8672HMS#PBF LT8672HMS#TRPBF LTGYT 10-Lead Plastic MSOP –40°C to 150°C
MINI REEL
LT8672EDDB#TRMPBF LT8672EDDB#TRPBF LGYS 10-Lead (3mm × 2mm) Plastic DFN –40°C to 125°C
LT8672IDDB#TRMPBF LT8672IDDB#TRPBF LGYS 10-Lead (3mm × 2mm) Plastic DFN –40°C to 125°C
LT8672JDDB#TRMPBF LT8672JDDB#TRPBF LGYS 10-Lead (3mm × 2mm) Plastic DFN –40°C to 150°C
LT8672HDDB#TRMPBF LT8672HDDB#TRPBF LGYS 10-Lead (3mm × 2mm) Plastic DFN –40°C to 150°C
AUTOMOTIVE PRODUCTS**
LT8672EMS#WPBF LT8672EMS#WTRPBF LTGYT 10-Lead Plastic MSOP –40°C to 125°C
LT8672IMS#WPBF LT8672IMS#WTRPBF LTGYT 10-Lead Plastic MSOP –40°C to 125°C
LT8672JMS#WPBF LT8672JMS#WTRPBF LTGYT 10-Lead Plastic MSOP –40°C to 150°C
LT8672HMS#WPBF LT8672HMS#WTRPBF LTGYT 10-Lead Plastic MSOP –40°C to 150°C
LT8672EDDBM#WTRMPBF LT8672EDDBM#WTRPBF LHJR 10-Lead (3mm × 2mm) Plastic Side-
Wettable DFN Package
–40°C to 125°C
LT8672IDDBM#WTRMPBF LT8672IDDBM#WTRPBF LHJR 10-Lead (3mm × 2mm) Plastic Side-
Wettable DFN Package
–40°C to 125°C
LT8672JDDBM#WTRMPBF LT8672JDDBM#WTRPBF LHJR 10-Lead (3mm × 2mm) Plastic Side-
Wettable DFN Package
–40°C to 150°C
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
**Versions of this part are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. These
models are designated with a #W suffix. Only the automotive grade products shown are available for use in automotive applications. Contact your local
Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models.
LT8672
4
Rev. D
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ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect the device
reliability and lifetime.
Note 2: Positive currents flow into pins, negative currents flow out of pins.
Minimum and Maximum values refer to absolute values.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Minimum Drain Voltage l2.85 3 V
Total System Quiescent Current VEN/UVLO = 0V
l
3.5 5
15
µA
µA
VEN/UVLO = 2V, Active Rectifier Controller
In Regulation (Note 4)
l
20
20
26
39
µA
µA
EN/UVLO Pin Threshold High Pin Voltage Rising l1.22 1.28 1.34 V
EN/UVLO Pin Threshold Low Pin Voltage Falling l1.16 1.21 1.26 V
EN/UVLO Pin Hysteresis 70 mV
EN/UVLO Pin Current VEN/UVLO = 2V –0.1 0.1 µA
PG Pin Leakage VPG = 3.3V –0.1 0.1 µA
PG Pull-Down Resistance VPG = 0.1V l650 2000 Ω
Auxiliary Boost Regulator
Regulation Voltage VAUX – VDRAIN l10.2 11 11.8 V
Power NMOS Current Limit l75 100 120 mA
Power NMOS On-Resistance 2 Ω
Catch Diode Forward Voltage IDIODE = 100mA 0.8 V
AUXSW Pin Leakage VAUXSW = 12V –0.2 0.2 µA
Active Rectifier Controller
SOURCE–DRAIN Regulation Voltage l10 20 25 mV
SOURCE–DRAIN Fast Pull-Up Threshold l60 75 90 mV
DRAIN Current With Gate Driver in Regulation 12 µA
SOURCE Current With Gate Driver in Regulation
Fault Condition, VSOURCE = –40V
5
–1
µA
mA
Maximum Gate Drive (GATE–SOURCE) l10.2 11 11.8 V
Gate Pull-Up Current –26 –50 mA
Gate Pull-Down Current 170 300 mA
Gate-Source Off Voltage for Reverse SOURCE Fault Condition, VSOURCE = –5V, IGATE = 1mA
Fault Condition, VSOURCE = –40V, IGATE = 1mA
l
l
0.01
0.01
0.3
0.3
V
V
Gate Turn-Off Delay Time Step (VSOURCE–VDRAIN) from 130mV to −70mV
VGATE–VSOURCE < 1V, CGATE–SOURCE = 10nF
l0.6 1.1 µs
Gate Turn-On Delay Time Step (VSOURCE–VDRAIN) from −70mV to 130mV
VGATE–VSOURCE > 5V , CGATE–SOURCE = 10nF
l1.7 3.1 µs
Maximum Frequency of AC Input Signal to Be
Rectified
AC Input Ripple < 6VP-P, CGATE–SOURCE = 10nF
AC Input Ripple < 2VP-P, CGATE–SOURCE = 10nF
l
l
50
100
kHz
kHz
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VSOURCE = VDRAIN = 12V, unless otherwise noted. (Note 3)
Note 3: The LT8672E is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the −40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LT8672I is guaranteed over the full −40°C to 125°C operating junction
temperature range. The LT8672J and the LT8672H are guaranteed over
the full −40°C to 150°C operating junction temperature range. Operating
lifetime is derated at junction temperatures greater than 125°C.
Note 4: Total system current with active rectifier controller in regulation.
LT8672
5
Rev. D
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TYPICAL PERFORMANCE CHARACTERISTICS
Total Input Current in Regulation Total Input Current in Shutdown
GATE Current vs
Forward Voltage Drop
Fast Pull-Down Current Fast Pull-Up Current Forward Regulation Voltage
GATE Turn-Off Time vs
GATE Capacitance
GATE Turn-On Time vs
GATE Capacitance Fast Pull-Down Threshold
0
5
10
15
20
25
30
35
40
V
(
V
)
B
A
T
T
100n
1μ
10μ
100μ
I
(
µ
A
)
B
A
T
T
VBATT RISING
VBATT FALLING
8672 G01
0
5
10
15
20
25
30
35
40
V
(
V
)
B
A
T
T
0
1
2
3
4
5
I
(
µ
A
)
B
A
T
T
Total Input Current In Shutdown
8672 G02
−10
0
10
20
30
40
50
60
70
80
−30
−25
−20
−15
−10
−5
0
5
10
15
20
I
(
µ
A
)
G
A
T
E
Forward Voltage Drop
VSOURCE-DRAIN (mV)
8672 G03
−50
−25
0
25
50
75
100
125
150
TEMPERATURE (°C)
180
190
200
210
220
230
240
250
260
270
280
290
300
310
320
I
(
m
A
)
G
A
T
E
Fast Pull-Down Current
VGATE-SOURCE = 5V
8672 G04
−50
−25
0
25
50
75
100
125
150
−70
−60
−50
−40
−30
I
(
m
A
)
G
A
T
E
Fast Pull-Up Current
VGATE-SOURCE = 5V
TEMPERATURE (°C)
8672 G05
0
1
2
3
4
5
6
7
8
9
10
C
(
n
F
)
G
A
T
E
-
S
O
U
R
C
E
0
100
200
300
400
500
600
TIME (ns)
GATE Capacitance
8672 G07
0
1
2
3
4
5
6
7
8
9
10
C
(
n
F
)
G
A
T
E
-
S
O
U
R
C
E
0
0.5
1.0
1.5
2.0
2.5
3.0
TIME (µs)
GATE Capacitance
@VGATE-SOURCE = 10V
@VGATE-SOURCE = 5V
8672 G08
−50
−25
0
25
50
75
100
125
150
15
16
17
18
19
20
21
22
23
24
25
V
SOURCE-DRAIN
(mV)
TEMPERATURE (°C)
8672 G06
−50
−25
0
25
50
75
100
125
150
−12
−11
−10
−9
−8
−7
−6
−5
−4
Fast Pull-Down Threshold
TEMPERATURE (°C)
V
SOURCE-DRAIN
(mV)
8672 G09
LT8672
6
Rev. D
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
Fast Pull-Up Threshold AUX–DRAIN Regulation Voltage
Auxiliary Boost Regulator
Current Limit
EN/UVLO Pin Thresholds Fast Pull-Up to PG Low Delay Dropout Performance
0
5
10
15
20
25
30
35
40
V
(
V
)
D
R
A
I
N
10.90
10.95
11.00
11.05
11.10
V
(
V
)
A
U
X
-
D
R
A
I
N
Regulation Voltage
T
=
1
5
0
°
C
T
=
2
5
°
C
T
=
–
5
0
°
C
8672 G11
−50
−25
0
25
50
75
100
125
150
80
85
90
95
100
105
110
115
120
CURRENT LIMIT (mA)
Current Limit
TEMPERATURE (°C)
8672 G12
0
1
2
3
4
5
V
(
V
)
B
A
T
T
Start-Up Dropout Performance
5ms/DIV
V
B
A
T
T
V
O
U
T
R
=
1
Ω
L
O
A
D
8672 G15
Auxiliary Boost Regulator
Switching Waveforms
Auxiliary Boost Regulator
Response to Fast Pull-Up
Switching Waveforms
V
A
U
X
S
W
10V/DIV
I
L
100mA/DIV
V
A
U
X
-
D
R
A
I
N
100mV/DIV
500ns/DIV
8672 G16
−50
−25
0
25
50
75
100
125
150
70
71
72
73
74
75
76
77
78
79
80
TEMPERATURE (°C)
V
SOURCE-DRAIN
(mV)
8672 G10
−50
−25
0
25
50
75
100
125
150
1.20
1.21
1.22
1.23
1.24
1.25
1.26
1.27
1.28
1.29
1.30
V
(
V
)
E
N
/
U
V
L
O
EN/UVLO Pin Thresholds
RISING
FALLING
TEMPERATURE (°C)
8672 G13
−50
−25
0
25
50
75
100
125
150
12
13
14
15
16
17
18
19
20
21
22
DELAY (µs)
Fast Pull-Up Timer
TEMPERATURE (°C)
8672 G14
I
L
O
A
D
5A/DIV
V
S
OURCE-DRAIN
300mV/DIV
V
G
A
T
E
5V/DIV
V
A
U
X
S
W
10V/DIV
2µs/DIV
FET: BUK7Y3R5-40E
8672 G17
LT8672
7
Rev. D
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PIN FUNCTIONS
EN/UVLO (Pin 1): The LT8672’s active rectifier controller
and the auxiliary boost regulator are shut down when this
pin is below 1.21V. Tie to DRAIN if this shutdown feature
is not used.
GND (Pin 2): This pin has no function in the application
and should be connected to ground.
PG (Pin 3): The PG pin is the open drain output of an in-
ternal monitor circuitry. PG pulls low if any of the following
criteria is met: the part is in shutdown, the AUX voltage
has not reached its regulation value during start-up or
the gate driver’s fast pull-up path is active for more than
17µs. If the PG pin is used to control the output load, it can
protect the MOSFET from being overloaded under these
conditions. PG output is valid when DRAIN is above the
minimum input voltage.
GND (Pin 4): This is the ground of all the internal circuitry.
Tie directly to the local GND plane.
NC (Pin 5): This pin is not connected internally. Connect
it to ground or leave it floating.
AUXSW (Pin 6): Output of the Internal Power Switch of the
Auxiliary Boost Regulator. This node should be kept small
on the PCB for good performance and low EMI. Connect
the boost inductor between this pin and the DRAIN pin.
AUX (Pin 7): Auxiliary Boost Regulator Output. This pin
is used to provide a drive voltage, higher than the input
voltage, to the gate driver of the active rectifier controller.
Connect a 1µF capacitor between this pin and the DRAIN
pin as close as possible to the IC. Do not place a capacitor
to any other node than DRAIN on this pin.
DRAIN (Pin 8): Drain Voltage Sense and Supply Voltage.
The voltage sensed at this pin is used to control the external
MOSFET gate. It also provides current to the LT8672’s
internal circuitry. Connect this pin as close as possible
to the drain of the external N-channel MOSFET. This pin
must be locally bypassed with at least 4.7µF.
SOURCE (Pin 9): Source Connection. SOURCE is the return
path of the gate fast pull-down. The voltage sensed at this
pin is also used to control the MOSFET gate. Connect
this pin as close as possible to the source of the external
N-channel MOSFET.
GATE (Pin 10): Gate Drive Output. This pin drives the gate
of the external N-channel MOSFET. Connect this pin to the
gate of the MOSFET.
Exposed Pad (Pin 11, DFN Only): The exposed pad must
either be left floating or be connected to the GND pin.
LT8672
8
Rev. D
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BLOCK DIAGRAM
+
–
GATE
DRIVER
–
+
NC
GND
GND
PG
MONITOR
LOGIC
BOOST
CONTROL
1.21V VREF
GENERATION
SOURCE
GATE
DRAIN
AUXSW
AUX
9
10
8
6
7
AUX
EN/UVLO
EN/UVLO
AUXOK
ENABLE
1.21V
5
4
2
3
CAUX
COUT
V
OUT
VBATT
LAUX
CBYP
M1
8672 BD
1
FPU
LT8672
9
Rev. D
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OPERATION
The LT8672 is an active rectifier controller including an
integrated auxiliary boost regulator for fast turn on of the
external N-channel MOSFET. Operation is best understood
by referring to the Block Diagram.
Active Rectifier Controller
The active rectifier controller controls an external N-channel
MOSFET (M1) to form an ideal diode. The GATE amplifier
senses across DRAIN and SOURCE and drives the gate of
the MOSFET to regulate the forward voltage to 20mV. As
the load current increases, GATE is driven higher until a
point is reached where the MOSFET is fully on. If the load
current is reduced, the GATE amplifier drives the MOSFET
gate lower to maintain a 20mV drop. If the voltage VDRAIN
is reduced to a point where a forward drop of 20mV cannot
be supported, the GATE amplifier drives the MOSFET off.
During fast SOURCE–DRAIN transients such as fast varying
input (SOURCE) signals where the regulating 20mV loop
is too slow, fast pull-up (FPU) and fast pull-down (FPD)
current paths turn on and off the external MOSFET quickly.
This rectifies the input signal the same way a diode would
do but with much less power dissipation.
The SOURCE and GATE pins are protected against reverse
input voltages of up to –40V. GATE is pulled to SOURCE
when SOURCE goes negative, turning off the MOSFET and
isolating DRAIN from the negative input.
The gate voltage for the external MOSFET is provided by
the auxiliary boost regulator, which regulates its output
AUX to 11V above DRAIN.
The EN/UVLO pin can be used to shut down the active
rectifier controller and auxiliary boost regulator. By setting
EN/UVLO low, total system input current is reduced to less
than 3.5µA. The conduction path on the external MOSFET
would only be through its body diode.
Note that it typically takes 7ms for the internal supply
voltages to stabilize once the DRAIN voltage exceeds the
minimum voltage of 2.85V.
Auxiliary Boost Regulator
The auxiliary boost regulator uses a hysteretic control
scheme in conjunction with a constant low side current
limit of 100mA. When the AUX–DRAIN voltage is below
its nominal value of typically 11V, the low side power
switch is turned on. The LAUX inductor current rises, until
it reaches the low side current limit of 100mA, at which
point the low side switch is turned off and the inductor
discharges into CAUX until its current falls to zero. Then,
the low side switch turns on again, unless the AUX–DRAIN
voltage has risen above its nominal value. In this case,
all high power circuitry is shut off in order to reduce the
quiescent current.
This control scheme results in a switching frequency which
depends on inductor value and DRAIN voltage.
Power Good Pin (PG)
The open drain power good pin PG goes high impedance
when no fault is present. This indicates the external MOSFET
is operating properly.
LT8672
10
Rev. D
For more information www.analog.com
Active Rectifier Controller
Blocking diodes are commonly placed in series with sup-
ply inputs to protect against supply reversal. The LT8672
replaces diodes in these applications with a MOSFET to
reduce both the voltage drop and power loss associated
with a passive solution. The curve shown in Figure1 illus-
trates the dramatic improvement in power loss achieved in
a practical application. This represents significant savings
in board area by greatly reducing power dissipation in the
pass device. At low input voltages, the improvement in
forward voltage loss is readily appreciated where headroom
is tight, as shown in Figure2.
APPLICATIONS INFORMATION
The LT8672 operates from 3V to 42V and withstands an
absolute maximum range of –40V to 42V without damage.
In automotive applications the LT8672 operates through
load dump, cold crank and two-battery jumps, and it
survives reverse battery connections while also protecting
the load. Furthermore, due to its fast response to changes
in the external MOSFET’s forward voltage, it can rectify
input ripple with amplitudes as high as 6VP-P up to 50kHz.
Rectification up to 100kHz is possible with amplitudes as
high as 2VP-P. The fast gate drive capability of the LT8672
prevents the external MOSFET from overheating during
these demanding conditions since its body diode conducts
current only for a very small portion of the ripple period.
The LT8672 does not require any bypass capacitor at the
SOURCE pin (CBYP in the Block Diagram). Should such
a capacitor be needed for other reasons, for example as
part of an up-front EMI filter, its capacitance must not
exceed 60nF; otherwise, the gate driver’s stability may be
impaired. This applies to the total capacitance connected
to SOURCE on the PCB.
It is important to note that the EN/UVLO pin, while dis-
abling the LT8672 and reducing its current consumption to
3.5μA, does not disconnect the load from the input since
the MOSFET’s body diode is ever-present.
Shutdown Mode/Undervoltage Lockout
In shutdown, the LT8672 pulls GATE low to SOURCE,
turning off the MOSFET and reducing current consump-
tion to 3.5μA. Shutdown does not interrupt forward
current flow; a path is still present through M1’s body
diode. When enabled, the LT8672 operates as an active
rectifier. If shutdown is not needed, connect EN/UVLO to
DRAIN. EN/UVLO may be driven with a 3.3V or 5V logic
signal. To disable the part, EN/UVLO must be pulled down
below1.21V.
Figure1. Power Dissipation Comparison Between
MOSFET and Schottky Diode
Figure2. Forward Voltage Drop Comparison
Between MOSFET and Schottky Diode
0
5
10
15
20
CURRENT (A)
0
2
4
6
8
10
POWER DISSIPATION (W)
SCHOTTKY DIODE (SBG2040CT)
POWER
SAVED
MOSFET (BSC028N06NS)
8672 F01
0
5
10
15
20
CURRENT (A)
0
0.1
0.2
0.3
0.4
0.5
VOLTAGE
SCHOTTKY DIODE
(SBG2040CT)
MOSFET
(BSC028N06NS)
8672 F02
LT8672
11
Rev. D
For more information www.analog.com
Adding a resistive divider from SOURCE to EN/UVLO, as
shown in Figure3, programs the LT8672 to disable itself
when VBATT is below a threshold voltage VBATT(EN/UVLO),
given by:
R1=R2
V
BATT EN/UVLO
( )
1.21V – 1
⎛
⎝
⎜
⎜
⎞
⎠
⎟
⎟
Input Short-Circuit Faults and Negative Transients
For fast negative input transients, the LT8672 relies on
its fast pull-down (FPD) comparator. But since the FPD
threshold is negative, reverse current is built up in the
external MOSFET prior to an FPD turn-off. This process
resembles the reverse recovery of a diode, although
cause and timing differ. Since there is always a parasitic
or, in case of an up front EMI filter, intended inductance
in front of SOURCE, the reverse current stores energy
in this inductance. This energy pulls the SOURCE node
negative, once the external MOSFET is finally turned off.
A zero impedance short-circuit directly across the input
and ground is especially troublesome because it permits
the highest possible reverse current to build up.
This negative transient on SOURCE may potentially
be destructive to the LT8672, since the voltage on the
SOURCE pin is limited to –40V. To prevent damage to the
LT8672, protect the SOURCE pin as shown in Figure4
by clamping to the ground node with two TVS diodes.
Negative spikes, seen after the MOSFET turns off during
an FPD event, are clamped by D2. The example, an 18V
TVS, is a good choice for automotive applications, where
a reversed battery could produce a reverse voltage of up
to 14.4V, at which D2 should not conduct any current. D2
is not required if reverse-input protection is not needed.
APPLICATIONS INFORMATION
Figure3. EN/UVLO Pin Allows Programmable
Undervoltage Lockout
1nFR2
R1
V
BATT
SOURCE
EN/UVLO
LT8672
8672 F03
ENABLE
+
–
1.21V
Note that due to the comparator’s hysteresis, the LT8672
will not be enabled until VBATT rises slightly above
VBATT(EN/UVLO). If EN/UVLO is connected using a high
ohmic resistor, it is subject to capacitive coupling from
nearby clock lines or traces exhibiting high dV/dt. Bypass
EN/UVLO to GND with 1nF to eliminate injection.
This capacitor, if sized accordingly, will also prevent
negative voltage transients on VBATT from inadvertently
disabling the LT8672.
Figure4. Reverse Recovery Produces an Inductive Spike at the SOURCE Pin. The Polarity of Step Recovery
Is Shown Across the Parasitic Inductance (See Text for D3)
SOURCE
GATE
DRAIN
AUXSW
AUX
PG
GND
EN/UVLO
LT8672
1μF
100μH
D1
TPSMB33A
33V
D3
DDZ9700T
13V
D2
TPSMB18A
18V
8672 F04
VOU
T
V
BATT
4.7µF
+
CLOAD
INPUT
SHORT
INPUT PARASITIC
INDUCTANCE OR
EMI FILTER REVERSE RECOVERY CURRENT
+ –
LT8672
12
Rev. D
For more information www.analog.com
D1 protects SOURCE in the positive direction during load
steps and overvoltage conditions. The example, a 33V
TVS, is a good choice for automotive applications, where
a load dump could produce an overvoltage at which D1
should not conduct any current.
If neither D1 nor any reverse current protection (D2) is
needed, a diode is still required at SOURCE to protect the
LT8672 from negative inductive spikes caused by any
parasitic input inductance.
For input voltages 4V greater than VGS(MAX) of the external
MOSFET, a direct short (minimal inductance of less than
a fewnH) at the SOURCE node on the PCB could tempo-
rarily increase the VGS of the external MOSFET above its
VGS(MAX). If such a short is to be expected, D3 is needed
to protect the external MOSFET.
Any leakage current in D3 will increase the total quiescent
current accordingly. In addition, D3’s leakage current
should not exceed 5µA, as it would otherwise create an
offset at the gate driver’s input, increasing the SOURCE–
DRAIN regulation voltage.
Rectification of Fast Input Ripple
The LT8672 is specifically designed to address the chal-
lenging specifications for battery connected automotive
electronic control units (ECUs). For example, according
to automotive norms ISO16750 or LV124 an ECU may be
subjected to an AC ripple superimposed on its supply, with
frequencies of up to 30kHz and amplitudes of up to 6VP-P.
Due to its gate driver’s high output current and short delay
times, the LT8672 is able to control the external MOSFET
rapidly enough even at these frequencies to keep power
dissipation and reverse current conduction to a minimum.
In addition, this significantly reduces the ripple current in
the output capacitor.
Figure5, Figure6 and Figure7 show input and output
waveforms for various input ripple frequencies.
APPLICATIONS INFORMATION
Figure5. Rectification of Input Ripple Waveform
(f = 1kHz, 5A Load Current)
Figure6. Rectification of Input Ripple Waveform
(f = 30kHz, 5A Load Current)
Figure7. Rectification of Input Ripple Waveform
(f = 100kHz, 5A Load Current)
200µs/DIV
V
B
A
T
T
V
O
U
T
1V/DIV
1V/DIV
8672 F05
V
B
A
T
T
V
O
U
T
1V/DIV
1V/DIV
10µs/DIV
8672 F06
2µs/DIV
V
B
A
T
T
V
O
U
T
1V/DIV
1V/DIV
8672 F07
LT8672
13
Rev. D
For more information www.analog.com
MOSFET Selection
All load current passes through an external MOSFET, M1.
The important characteristics of the MOSFET are on-
resistance, RDS(ON), the maximum drain-source voltage,
BVDSS, the gate threshold voltage VGS(TH) and the total
gate charge QGTOT.
Gate drive is compatible with standard threshold and
logic-level MOSFETs over the entire operating range of
3V to 42V. For logic-level MOSFETs, VGS(MAX) should be
±15V or higher.
The maximum allowable drain-source voltage, BVDSS, must
be higher than the power supply voltage. If the input is
grounded, the full supply voltage will appear across the
MOSFET. If the input is reversed and the output is held up
by a charged capacitor, battery or power supply, the sum
of the input and output voltages will appear across the
MOSFET and require a BVDSS > VOUT + |VBATT|.
The MOSFET’s on-resistance, RDS(ON), directly affects
the forward voltage drop and power dissipation. Desired
forward voltage drop should be less than that of a diode
for reduced power dissipation; 60mV is a good starting
point. Choose a MOSFET which has:
RDS(ON) <
Forward Voltage Drop
ILOAD
The resulting power dissipation is
Pd=ILOAD2•RDS ON
( )
APPLICATIONS INFORMATION
For fast gate drive operation choose a MOSFET with the
smallest total gate charge QGTOT that also satisfies the
BVDSS and RDS(ON) requirements. A MOSFET with smaller
QGTOT not only reduces reverse current during the turn-off
phase but also stays cooler during rectification of high
amplitude ripple on the input.
If the MOSFET has an integrated gate protection, its
leakage should not exceed 5µA, as this would otherwise
create an offset at the gate driver’s input, increasing the
SOURCE–DRAIN regulation voltage.
When the LT8672 rectifies an AC ripple voltage, the aver-
age current through the external MOSFET still equals the
load current, but the peak current is much higher. Since
the MOSFET’s power dissipation is proportional to the
square of this current as described above, the average
power dissipation during rectification exceeds the power
dissipation in steady state. The actual peak current depends
on the external components and their parasitics. Figure8
shows a simple model which can be used to estimate the
peak current by computer simulation. RBATT represents
the impedance of the voltage source VBATT, the inductor
models the combined inductance of the cable and, if
present, the EMI filter inductor. The ideal diode has no
resistance and a forward voltage of 0V. RDS(ON) represents
the on-resistance of the external MOSFET, while CLOAD and
RESR represent the electrolytic capacitor and its equivalent
series resistance.
Figure8. Simplified Application Model Including All Relevant Parasitics
+
VOUT
RESR
CLOAD
RDS(ON)
IDEAL
DIODE
LCABLE + LEMI
RBATT
V
BATT
8672 F08
LT8672
14
Rev. D
For more information www.analog.com
For example, an application with CLOAD = 470µF,
RESR=16mΩ, RDS(ON) = 5mΩ, LCABLE + LEMI = 1µH, and
RBATT = 50mΩ dissipates 0.5W of power in steady state
with a load current of 10A. But this power increases to
1.13W when a 6VP-P AC-ripple with a frequency of 10kHz is
superimposed on VBATT. Removing any inductance raises
this power even further to 1.3W, while the RMS current
in CLOAD reaches 12.6A.
This model can also be used to select an electrolytic ca-
pacitor which can handle the corresponding RMS current
for the duration of the AC-ripple.
Electrolytic Capacitor and Ripple Voltage
During rectification, the electrolytic capacitor CLOAD re-
duces the ripple voltage seen by the load. Figure9 shows
the corresponding waveforms for the rectification of a
sinusoidal SOURCE ripple voltage.
where VAC is the ripple amplitude in V, f the ripple frequency
in Hz, CLOAD the capacitance of the electrolytic capacitor
in F, and ILOAD the load current in A. Note that any ripple
caused by the equivalent series resistance of CLOAD will
increase VR accordingly, in particular at high frequencies.
Since the power supply rejection of the load usually de-
grades with frequency, it is often desirable to limit VR at
a given frequencyf. Using the above equation, the neces-
sary minimum capacitance CLOAD can be calculated from:
CLOAD = 4VAC – VR
4V
AC
• V
R
• f • ILOAD
For example, if the ripple voltage VR is to be kept below
2V at f = 5kHz, VAC = 3V (6VP-P), and a load current of
ILOAD = 5A, then CLOAD = 417µF.
When selecting an electrolytic capacitor also keep in mind
the high peak currents at high frequencies as discussed
in the previous section.
Automotive Cold Crank
During the so-called “cold crank” (e.g. LV124 E-11) a car’s
battery voltage may drop to 3.2V. As a result, the high
voltage drop of traditional reverse protection schemes
using passive rectifiers like Schottky diodes require the
supplied circuitry to work at minimum input voltages as
low as 2.5V. Buck-boost regulators may then be needed
instead of simpler and more efficient buck regulators in
order to provide a stable 3V supply often required by many
microcontrollers.
The LT8672’s minimum input operating voltage of 3V al-
lows the active rectifier to operate through the cold crank
pulse with minimum drop between input and output. This
allows use of a buck regulator with a minimum operating
voltage of 3V and low dropout characteristics like the
LT8650S to generate a 3V supply.
Figure10 shows input and output waveforms during a
cold crank pulse, comparing the LT8672 active rectifier
controller to a Schottky diode.
APPLICATIONS INFORMATION
Figure9. Waveforms For Rectification Of a
Sinusoidal SOURCE Ripple Voltage
TIME
VOLTAGE
V
R
V
A
C
V
D
R
A
I
N
V
S
O
U
R
C
E
8672 G09
The load is exposed to the remaining ripple voltage VR,
which depends on CLOAD, ripple frequency, ripple ampli-
tude, and load current. This ripple voltage decreases with
frequency and is approximately:
VR = 4VAC • ILOAD
4V
AC
• f • C
LOAD
+ I
LOAD
LT8672
15
Rev. D
For more information www.analog.com
This maximum available AUX current is achieved at the
boost regulator’s maximum switching frequency which
can be approximated by following equation:
fAUXSW(MAX) =
1180 •(V
DRAIN
– 0.2)
(V
DRAIN
+11.6) •(10L
AUX
+3V
DRAIN
– 0.6)
where fAUXSW(MAX) is the maximum switching frequency
in MHz, VDRAIN is the DRAIN pin voltage in volts and LAUX
is the boost regulator inductor in μH.
However, depending on the total average current required
by the gate driver on the AUX pin to switch the external
MOSFET on and off periodically, the boost regulator might
enter discontinuous mode and switch at a lower frequency
given by the following equation:
fAUXSW =2.9 •IAUX
LAUX
where fAUXSW is the switching frequency in MHz, IAUX is
the average current required by the gate driver in mA and
LAUX is the boost regulator inductor in μH.
During rectification of input ripple, fully charging and
discharging the gate capacitance of the external MOSFET
requires an average AUX current
IAUX =f • QG
1000
where f is the ripple frequency in kHz, QG is the total gate
charge of the external MOSFET in nC, and IAUX is the AUX
current in mA drawn by the gate driver. For example, recti-
fication of a 6VP-P–50kHz input ripple superimposed on the
12V battery voltage, using an external MOSFET with 100nC
of total gate charge under full load conditions, requires an
average turn on gate current of 5mA which the gate driver
takes from the AUX pin. Under these conditions, the boost
regulator runs with a switching frequency of 145kHz using
a 100μH inductor. The maximum available AUX current is
approximately 23mA with the boost regulator switching
at about 595kHz.
When the active rectifier is in steady state conditions, the
AUX pin current required by the gate driver is approximately
1μA and the boost regulator is most of the time in sleep
APPLICATIONS INFORMATION
Figure10. Automotive Cold Crank Waveforms
0
2
4
6
8
10
12
14
16
VOLTAGE
V
(
L
T
8
6
7
2
+
F
E
T
)
O
U
T
V
B
A
T
T
V
(
SCHOTTKY)
O
U
T
100ms/DIV
I
=
5
A
L
O
A
D
SCHOTTKY DIODE BYT60P-400
8672 F10
Auxiliary Boost Regulator
The auxiliary boost regulator provides a boosted voltage
to the gate driver to enhance the external MOSFET fully
with at least 10V of gate drive.
It uses a hysteretic control scheme in conjunction with
a constant low side current limit of 100mA. This control
scheme results in a switching frequency with a maximum
value which depends on inductor value and DRAIN voltage.
Recommended boost regulator external passive compo-
nents are a 1μF/16V ceramic capacitor and a 47μH to 100μH
inductor. The inductor’s saturation current should be at
least 120mA and its ESR should not exceed 10Ω, therefore
small chip inductors like CBC2518T470K or CBC2518T101K
from Taiyo Yuden or those from the XPL2010 series from
Coilcraft are good options.
The boost regulator maximum output current available to
the gate driver on the AUX pin can be approximated by
the following equation:
IAUX MAX
( )
=50 • VDRAIN – 1
V
DRAIN
+11.8
where IAUX(MAX) is the maximum boost regulator output
current in mA and VDRAIN is the DRAIN pin voltage in volts.
LT8672
16
Rev. D
For more information www.analog.com
mode waking up only from time to time to maintain the
AUX pin voltage 11V above DRAIN.
Figure11, Figure12 and Figure13 show typical waveforms
with 1µA, 5mA, and 10mA of AUX load current.
APPLICATIONS INFORMATION
Figure11. Auxiliary Boost Regulator Waveforms for
1µA Load on AUX (Steady State in Regulation)
V
A
U
X
S
W
10V/DIV
I
L
100mA/DIV
V
A
U
X
100mV/DIV
10ms/DIV
8672 F11
Figure12. Auxiliary Boost Regulator Waveforms for
5mA Load on AUX
Figure13. Auxiliary Boost Regulator Waveforms for
10mA Load on AUX
Power Good Pin
The power good pin is the output of internal monitoring
circuitry, which signals when the external MOSFET is able
to pass the full load current with a voltage of less than
75mV between its source and drain. PG only goes high if
the LT8672 is enabled, and the AUX voltage has reached
its regulation value during start-up, and if the gate driver’s
fast pull-up path is not engaged for more than 17µs. This
allows detection of a number of system faults.
For example, the gate of the external MOSFET may be
shorted to ground or source. It would then be impossible
to turn it on, which would keep the gate driver’s fast pull-
up path active indefinitely, thereby pulling PG low. The
fast pull-up path would never be active for so long in a
correctly working system, because charging the external
MOSFET’s gate requires much less time.
An insufficient AUX voltage (for example during start-up
or due to a system fault) may be able to deliver sufficient
gate-source voltage to the external MOSFET for small load
currents, but not for high load currents. Therefore PG is
pulled low if AUX remains too low during start-up.
PG is valid (and pulls low) even in shutdown. Although
this may increase the overall shutdown current through
the external pull-up resistor on PG, it keeps the system
correctly informed about the shutdown status of the
LT8672 and that it cannot enhance the external MOSFET.
Thus, if PG is used to control the load current in the
external MOSFET, its body diode can be prevented from
conducting large currents for a prolonged period of time.
This significantly reduces the amount of heat generated
by the external MOSFET even in fault conditions.
The fast pull-up path is active when the external MOSFET’s
forward voltage exceeds 75mV, therefore it is recom-
mended to choose a MOSFET large enough not to exceed
this threshold with maximum load current. If the PG flag
is ignored in the application, the MOSFET can be pushed
to higher forward voltages provided that its power dis-
sipation is kept within safe levels.
V
A
U
X
S
W
10V/DIV
I
L
100mA/DIV
V
A
U
X
100mV/DIV
5µs/DIV
8672 F12
V
A
U
X
S
W
10V/DIV
I
L
100mA/DIV
V
A
U
X
100mV/DIV
2µs/DIV
8672 F13
LT8672
17
Rev. D
For more information www.analog.com
The PG output is valid when DRAIN is above the minimum
input voltage. Figure14 and Figure15 show power good pin
waveforms under several “MOSFET Not Ready” conditions.
APPLICATIONS INFORMATION
Figure14. PG Waveform Showing How PG Responds
to a Very Long Fast Pull-Up Condition
Figure16. Recommended PCB Layout for the LT8672 (MSOP)
Layout Considerations
Connect the SOURCE and DRAIN pins as close as possible
to the MOSFET source and drain pins. Keep the traces to
the MOSFET wide and short to minimize resistive losses
as shown in Figure16 and Figure17. Place surge sup-
pressors and necessary transient protection components
close to the LT8672 using short lead lengths. Keep more
than minimum distance from GATE traces to other nodes
to prevent leakage that could turn the MOSFET on. Only
SOURCE and DRAIN traces are allowed to run beside GATE
traces. Use no-clean flux to minimize PCB contamination.
Note that the integrated boost regulator causes switched
currents to flow in CAUX and COUT and in the pins AUX,
AUXSW, and GND. The loops formed by CAUX and COUT
should be minimized by placing these capacitors as close
as possible to the LT8672 as shown in Figure16 and Fig-
ure17. COUT can be split into two capacitors COUT1 (close
to the LT8672) and COUT2 (further away), provided that
COUT1 has a capacitance of at least 1µF.
V
E
N
/
U
V
L
O
2V/DIV
V
A
U
X
-
D
R
A
I
N
5V/DIV
V
P
G
2V/DIV
500µs/DIV
FRONT PAGE APPLICATION
8672 F15
Figure15. PG Waveform Showing How PG Behaves
During Start-Up and How It Depends on EN/UVLO
10
9
1
2
3
4
5
6
7
8
VBATT
VOUT
GND
AUXSW
VIAS
AUX
FET
LAUX
CAUX
COUT1
COUT2
LT8672
8672 F16
I
L
O
A
D
20A/DIV
FAST PULL-UP
17µs
V
P
G
2V/DIV
10µs/DIV
FRONT PAGE APPLICATION
V
S
OURCE-DRAIN
60mV/DIV
8672 F14
LT8672
18
Rev. D
For more information www.analog.com
APPLICATIONS INFORMATION
Figure17. Recommended PCB Layout for the LT8672 (DFN)
VBATT
VOUT
GND
AUXSW
VIAS
AUX
FET
LAUX
CAUX
COUT1
COUT2
LT8672
8672 F17
11
6
8
7
9
10
5
4
2
3
1
LT8672
19
Rev. D
For more information www.analog.com
TYPICAL APPLICATIONS
Active Rectifier for 12V Automotive Applications
Active Rectifier for 12V Automotive Applications with EMI Filter at DRAIN
Active Rectifier for 12V Automotive Applications with High Load
IPD100N06S4-03
CAUX
1μF
LAUX
100μH
D1
TPSMB33A
33V
D2
TPSMB18A
18V
VOU
T
5A
V
BATT
12V
COUT
4.7µF CLOAD
470µF
OFF
ON CAUX: X7R, 50V, 0805
COUT: X7R, 50V, 1210
LAUX: XPL2010-104ML
CLOAD: EEEFK1V471AQ
8672 TA03
+
SOURCE
GATE
DRAIN
AUXSW
AUX
PG
GND
EN/UVLO
LT8672
TO SYSTEM LOADS
BUK7Y4R8-60E
CAUX
1μF
LAUX
100μH
D1
TPSMB33A
33V
D2
TPSMB18A
18V
8672 TA04
VOUT
10A
V
BATT
12V COUT
1µF CLOAD
3000µF
CAUX, COUT: X7R, 50V, 0805
CEMI: X7R, 50V, 1210
LAUX: XPL2010-104ML
LEMI: IHLP6767GZER1R0M51
CLOAD: 2× EEEFK1V152AM
+
SOURCE
GATE
DRAIN
AUXSW
AUX
PG
GND
EN/UVLO
LT8672
OFF
ON
CEMI
4.7µF
TO SYSTEM
LOADS
EMI FILTER
LEMI
1µH
SQM50020EL
CAUX
1μF
LAUX
100μH
VOUT
20A
V
IN
12V
COUT
4.7µF CLOADS
10000µF
CAUX: X7R, 50V, 0805
COUT: X7R, 50V, 1210
LAUX: XPL2010-104ML
CLOAD: 5×
MAL225099017E3
8672 TA05
+
OFF
ON
SOURCE
GATE
DRAIN
AUXSW
AUX
PG
GND
EN/UVLO
D1
TPSMB33A
33V
D2
TPSMB18A
18V
LT8672
TO SYSTEM LOADS
LT8672
20
Rev. D
For more information www.analog.com
PACKAGE DESCRIPTION
MSOP (MS) 0213 REV F
0.53 ±0.152
(.021 ±.006)
SEATING
PLANE
0.18
(.007)
1.10
(.043)
MAX
0.17 –0.27
(.007 – .011)
TYP
0.86
(.034)
REF
0.50
(.0197)
BSC
1234 5
4.90 ±0.152
(.193 ±.006)
0.497 ±0.076
(.0196 ±.003)
REF
8910 76
3.00 ±0.102
(.118 ±.004)
(NOTE 3)
3.00 ±0.102
(.118 ±.004)
(NOTE 4)
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.254
(.010) 0° – 6° TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
5.10
(.201)
MIN
3.20 – 3.45
(.126 – .136)
0.889 ±0.127
(.035 ±.005)
RECOMMENDED SOLDER PAD LAYOUT
0.305 ±0.038
(.0120 ±.0015)
TYP
0.50
(.0197)
BSC
0.1016 ±0.0508
(.004 ±.002)
MS Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661 Rev F)
LT8672
21
Rev. D
For more information www.analog.com
PACKAGE DESCRIPTION
2.00 ±0.10
(2 SIDES)
NOTE:
1. DRAWING CONFORMS TO VERSION (WECD-1) IN JEDEC PACKAGE OUTLINE M0-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
0.50 ±0.05
BOTTOM VIEW—EXPOSED PAD
0.25 ±0.05
(2 SIDES)
0.75 ±0.05
R = 0.115
TYP
R = 0.05
TYP
2.5 ±0.05
(2 SIDES)
3.00 ±0.10
(2 SIDES)
15
106
PIN 1 BAR
TOP MARK
(SEE NOTE 6)
0.200 REF
0 – 0.05
(DDB10) DFN 0216 REV Ø
0.25 ±0.05
0.50 BSC
PIN 1
R = 0.20 OR
0.125 × 45°
CHAMFER
0.25 ±0.05
2.5 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
0.25 ±0.05
(2 SIDES)
0.95 ±0.05
0.80 ±0.05
2.55
±0.05
PACKAGE
OUTLINE
0.50 BSC
DDB Package
10-Lead Plastic DFN (3mm × 2mm) COL
(Reference LTC DWG # 05-08-1531 Rev Ø)
LT8672
22
Rev. D
For more information www.analog.com
PACKAGE DESCRIPTION
2.00 ±0.10
(2 SIDES)
NOTE:
1. DRAWING CONFORMS TO VERSION (WECD-1) IN JEDEC PACKAGE OUTLINE M0-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
0.50 ±0.10
BOTTOM VIEW—EXPOSED PAD
0.25 ±0.10
(2 SIDES)
0.75 ±0.05
R = 0.115
TYP
2.50 ±0.10
(2 SIDES)
3.00 ±0.10
(2 SIDES)
15
106
PIN 1 BAR
TOP MARK
(SEE NOTE 6)
0.200 REF
0 – 0.05
(DDBM10) DFN 1218 REV A
0.25 ±0.05
0.50 BSC
PIN 1
R = 0.20 OR
0.25 × 45°
CHAMFER
0.25 ±0.05
2.50 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
0.25 ±0.05
(2 SIDES)
1.15 ±0.05
0.70 ±0.05
2.55 ±0.05
PACKAGE
OUTLINE
0.50 BSC
DDBM Package
10-Lead Plastic SIDE WETTABLE DFN (3mm × 2mm)
(Reference LTC DWG # 05-08-1655 Rev A)
0.203 REF
TERMINAL THICKNESS
TERMINAL LENGTH
0.50 ± 0.10
0.05 REF
PLATED AREA
DETAIL A
0.10 REF
DETAIL A
LT8672
23
Rev. D
For more information www.analog.com
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 04/18 Added DFN package option
Clarified Figure16 and Figure17
Added Figure17
Added DFN package drawing
1, 2, 6
16
17
20
B 09/18 Clarified Gate Turn-On and Turn-Off Delay Time 3
C 10/18 Added J-Grade temperature option
Clarified θJC
2, 3
2
D 04/19 Added J-Grade side-wettable plank option DFN package with W Flow (LT8672JDDBM#WTRPBF)
Added side-wettable flank DFN package drawing
2
20
LT8672
24
Rev. D
For more information www.analog.com
www.analog.com
ANALOG DEVICES, INC. 2017-2019
D16853-0-04/19
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CAUX
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LAUX
100μH
VOUT
5A
V
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12V COUT
4.7µF CLOAD
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CAUX, CEMI1, CEMI2
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LAUX: XPL2010-104ML
LEMI: IHLP2525BDER3R3MA1
C
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8672 TA02
+
OFF
ON
SOURCE
GATE
DRAIN
AUXSW
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PG
GND
EN/UVLO
D1
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33V
D2
TPSMB18A
18V
LT8672
TO SYSTEM LOADS
EMI FILTER
PART NUMBER DESCRIPTION COMMENTS
LT3667/LT3668 40V (60VMAX), 400mA Step-Down Switching Regulator with
Dual Fault Protected LDOs
4.3VIN(MIN), 40VIN(MAX) (60V MAX), 0.8VOUT(MIN), IQ = 50µA, ISD
= <1µA, MSOP-16E and 3mm × 5mm QFN-24 Packages
LTC
®
4359 Ideal Diode Controller with Reverse Input Protection 4VIN(MIN), 80VIN(MAX), –40VOUT(MIN) Reverse Protection, IQ =
150µA, ISD = <9µA, MSOP-8 and 2mm × 3mm DFN-6 Packages
LT8609S 42V, 2A, 94% Efficiency, 2.2MHz Synchronous Micropower
Step-Down DC/DC Converter with IQ = 2.5μA
3VIN(MIN), 42VIN(MAX), 0.8VOUT(MIN), IQ = 2.5µA, ISD = <1µA,
3mm × 3mm LQFN-16 Package
LT8650S 42V, Dual 4A, 95% Efficiency, 2.2MHz Synchronous Silent
Switcher 2 Step-Down DC/DC Converter with IQ = 6.2μA
3VIN(MIN), 42VIN(MAX), 0.8VOUT(MIN), IQ = 6.2µA, ISD = <1µA,
4mm × 6mm LQFN-32 Package
LT8640S 42V, 6A, 95% Efficiency, 2.2MHz Synchronous Silent
Switcher
®
2 Step-Down DC/DC Converter with IQ = 2.5μA
3.4VIN(MIN), 42VIN(MAX), 0.97VOUT(MIN), IQ = 2.5µA, ISD = <1µA,
4mm × 4mm LQFN-24 Package
LT8645S 65V, 8A, 95% Efficiency, 2.2MHz Synchronous Silent Switcher2
Step-Down DC/DC Converter with IQ = 2.5μA
3.4VIN(MIN), 65VIN(MAX), 0.8VOUT(MIN), IQ = 2.5µA, ISD = <1µA,
4mm × 6mm LQFN-32 Package
LT8609/LT8609A/
LT8609B
42V, 2A, 94% Efficiency, 2.2MHz Synchronous Micropower
Step-Down DC/DC Converter with IQ = 2.5μA
3VIN(MIN), 42VIN(MAX), 0.8VOUT(MIN), IQ = 2.5µA, ISD = <1µA,
MSOP-10E Package
LT8640 42V, 5A, 95% Efficiency, 2.2MHz Synchronous Silent Switcher2
Step-Down DC/DC Converter with IQ = 2.5μA
3.4VIN(MIN),42VIN(MAX), 0.97VOUT(MIN), IQ = 2.5µA, ISD = <1µA,
3mm × 4mm QFN-16 Package
LT8612 42V, 6A, 96% Efficiency, 2.2MHz Synchronous Micropower
Step-Down DC/DC Converter with IQ = 2.5μA
3.4VIN(MIN), 42VIN(MAX), 0.97VOUT(MIN), IQ = 3.0µA, ISD = <1µA,
3mm × 6mm QFN-28 Package
LT8602 42V, Quad Output (2.5A + 1.5A + 1.5A + 1.5A) 95% Efficiency,
2.2MHz Synchronous Micropower Step-Down DC/DC Converter
with IQ = 25μA
3VIN(MIN), 42VIN(MAX), 0.8VOUT(MIN), IQ = 25µA, ISD = <1µA,
6mm × 6mm QFN-40 Package