ue 199% a Am27HB010 1 Megabit (131,072 x 8-Bit) Burst Mode CMOS EPROM cl Advanced Micro Devices DISTINCTIVE CHARACTERISTICS w High speed - 50ns random access 15 ns burst access mw No burst boundary @ No burst limit gu Pin compatible with Am27C010 = Supports all Burst microprocessors ~ Amz29000 compatibie m Single + 5 V power supply + 10% power supply tolerance available @ High speed Flashrite programming - Typically less than 30 seconds GENERAL DESCRIPTION The Am27HB010 is a 1 megabit ultraviolet erasable pro- grammable read-only memory. It is organized as 128K words by 8 bits per word. Two modes are available to ac- cess the data. Random access mode is selected by placing Vin on the Vpp/BURST pin and this allows full random access to the data. Burst access is selected by placing Vi_on the Vep/BURST pin which allows high speed access to sequential data. Burst mode may be entered without regard to page or word boundaries and may be sustained all the way up to the physical device boundary (128K bytes) if required. The Am27HB010 is ideal for use with the fastest proces- sors due to the high speed random access time. This de- vice also achieves maximum performance with all of todays burstable processors due to the extremely fast burst mode access time. Designers may take full advan- tage of high speed digital signal processors and micro- processors by allowing code to be executed at full speed directly out of EPROM. The Am27HB010 is programmed using AMD's Flashrite programming algorithm which allows the en- tire chip to be programmed typically in less than 30 seconds. This device is available in 32-pin windowed DIP as well as surface mount packages and is offered in commer- cial, industrial and extended temperature ranges. BLOCK DIAGRAM n _ Py ma Ai ~ Ais : 1,048 576-Bit re | DQo - DQ? Address \) e| A00reSS| 4} EPROM Cell Output [> > Data inputs | > 9 Matrix Buffers t- Outputs = ~ P P oT CE___+ Control oe Logic Vpep/BURST. PGM 14970-001B PRODUCT SELECTOR GUIDE Family Part No. Am27HB010 Vcc +10% -50 -55 -70 90 Max Access Time (ns) 50 55 70 90 Burst Access (ns) 15 15 20 30 CE (B) Access (ns) 50 55 70 90 OE (G) Access (ns) 15 15 20 30 Publication # 14970 Rev. C Amendment /O issue Date: January 1992al AMD CONNECTION DIAGRAMS Top View DIP LCC* vee/BuURST I 1 Vee Aw G2 1] BGM (P) Ais G3 NC Ai2 4 N Ais Ata A7 U5 N Ai3 Aig As [6 1 As A As U7 1 As As 8 An Ag As 9 0 OE (G) Ann Ao {10 Ato SE (G) AY 1 1) CE(E) Ato Ao/CLK pa, TEE) DQo 1] DOs oar DQ; 1} DOs DQ2 fl] DOs GND 1} DQs 14970-002B 14970-003B Note: JEDEC nomenclature is in parenthesis Also available in a 32-pin PLCC. PIN DESCRIPTION Ao-Ar6 Address Inputs PGM (P) Program Enable Input CE (B Chip Enable Input Vec Vcc Supply Voltage DQo-DQ7 _ Data Input/Outputs Vee/BURST Program Supply Voltage OE G) Output Enable Input & Burst Enable CLK Clock GND Ground NC No Internal Connection LOGIC SYMBOL Ee 200 - park > 7124, E(B) *| PGM (P) SE (G) ea! Vee/BURST 14970-0048 2 Am27HB010ORDERING INFORMA Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: AM27HB010 -50 TION AMD al B L_ OPTIONAL PROCESSING Blank = Standard processing B = Burn-in TEMPERATURE RANGE C = Commercial (0 to +70C) | = Industrial (-40 to +85C) E = Extended Commercial (-55 to +125C) PACKAGE TYPE D = 32-Pin Ceramic DIP (CDV032) DEVICE NUMBER/DESCRIPTION Am27HB010 1 Megabit (128K x 8) High Speed Burst Mode CMOS UV EPROM Valid Combinations AM27HB010-50 AM27HB010-55 DC, DCB, LC, LCB AM27HB010-70 AM27HB010-90 DC, DCB, DE, DEB, Di, Di, LC, LCB, LI, LIB, LE, LEB L = 32-Pin Rectangular Ceramic Leadless Chip Carrier (CLV032) SPEED OPTION See Product Selector Guide and Valid Combinations Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations or to check on newly released combinations. Am27HB010cl AMD ORDERING INFORMATION OTP Products (Preliminary) AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: AM27HB010 -55 = P & r tL OPTIONAL PROCESSING Blank = Standard processing TEMPERATURE RANGE CG = Commercial (0 to +70C) PACKAGE TYPE P = 32-Pin Plastic DIP (PD 032) J = 32-Pin Rectangular Plastic Leaded Chip Carrier (PL 032) SPEED OPTION See Product Selector Guide and Valid Combinations DEVICE NUMBER/DESCRIPTION Am27HB010 1 Megabit (128K x 8) High Speed Burst Mode CMOS OTP EPROM Vaild Combinations Valid Combinations AM27HB010-55 AM27HB010-70 PC, JC AM27HB010-90 Valid Combinations list configurations pianned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations or to check on newly released combinations. Am27HBO010AMD al ORDERING INFORMATION APL Products AMD products for Aerospace and Defense applications are available in several packages and operating ranges. APL (Ap- proved Products List) products are fully compliant with MIL-STD-883C requirements. The order number ( is formed by a combination of: AM27HBO10 alid Combination) A tL LEAD FINISH A = Hot Solder Dip PACKAGE TYPE X = 32-Pin Ceramic DiP (CDV032) U = 32-Pin Rectangular Ceramic Leadless Chip Carrier (CLV032) DEVICE CLASS /B = Class B SPEED OPTION See Product Selector Guide and Valid Combinations DEVICE NUMBER/DESCRIPTION Am27HB010 1 Megabit (128K x 8) High Speed Burst Mode CMOS UV EPROM Valid Combinations Valid Combinations AM27HBO010-70 Valid Combinations list configurations planned to AM27HB010-90 be supported in volume for this device. Consult the IBXA, /BUA local AMD sales office to confirm availability of specific valid combinations, or to check on newly released combinations. Group A Tests Group A tests consist of Subgroups 1, 2, 3, 7, 8, 9, 10, 11. Am27HB010 5cl AMD FUNCTIONAL DESCRIPTION Erasing the Am27HB010 In order to clear all locations of their programmed con- tents, it is necessary to expose the AM27HB010 to an ultraviolet light source. A dosage of 15 W seconds/cm? is required to completely erase an AmM27HBO010. This dosage can be obtained by exposure to an ultraviolet lampwavelength of 2537 Angstroms (A) with inten- sity of 12,000 W/cm? for 15 to 20 minutes. The Am27HB010 should be directly under and about one inch from the source and all filters should be removed from the UV light source prior to erasure. It is important to note that the Am27HB010, and similar devices, will erase with light sources having wave- lengths shorter than 4000 A. Although erasure timeswill be much longer than with UV sources at 25374, never- theless the exposure to fluorescent light and sunlight will eventually erase the Am27HB010 and exposure to them should be prevented to realize maximum system reli- ability. If used in such an environment, the package window should be covered by an opaque label or substance. Programming the Am27HB010 Upon delivery, or after each erasure, the Am27HB010 has all 1,048,576 bits in the ONE, or HIGH state. ZE- ROs are loaded into the Am27HBO010 through the pro- cedure of programming. The programming mode is entered when 12.75+0.25V is applied to the Ver pin, and CE and PGM are at Vit, and OE is at Vin. For programming, the data to be pro- grammed is applied 8 bits in parallel to the data output pins. The Flashrite programming algorithm reduces program- ming time by using initial 100 us pulses followed by a byte verification to determine whether the byte has been successfully programmed. If the data does not verify, an additional pulse is applied for a maximum of 25 pulses. This process is repeated while sequencing through each address of the EPROM. The Flashrite programming algorithm programs and verifies at Vcc = 6.25 V and Vep = 12.75 V. After the final address is completed, all bytes are compared to the original data with Vcc = Vpp = 5.25 V. Program Inhibit Programming of multiple Am27HB010s in paralle! with different data is also easily accomplished. Except for CE, all like inputs of the parallel Am27HB010 may be common. A TTL low-level program pulse applied to an Am27HB010 CE input with Vee = 12.75 + 0.25 V, PGM is LOW, and_OE HIGH will program that Am27HB010. A high-level CE input inhibits the other Am27HB010 from being programmed. Program Verify Averify should be performed on the programmed bits to determine that they were correctly programmed. The verify should be performed with OE and CE at Vi, PGM at Vin, and Vpp between 12.5 V to 13.0 V. Auto Select Mode The auto select mode allows the reading out of a binary code from an EPROM that will identify its manufacturer and type. This mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional in the 25C + 5C ambient temperature range that is required when programming the Am27HB010. To activate this mode, the programming equipment must force 12.0 + 0.5 V on address line As of the Am27HB010. Two identifier bytes may then be se- quenced from the device outputs by toggling address line Ao from Vit to Vin. All other address lines must be held at Vi. during auto select mode. Byte 0 (Ao = Vi.) represents the manufacturer code, and byte 1 (Ao = Vin), the device identifier code. For the Am27HB010, these two identifier bytes are given in the Mode Select table. All identifiers for manufacturer and device codes will possess odd parity, with the MSB (DQ7) defined as the parity bit. Random Read Mode The Am27HB010 has three control functions that must be logically satisfied in order to obtain random access data at the outputs. Chip Enable (CE) is the power con- trol and should be used for device selection. Output En- able (OE) is the output control and should be used to gate data to the output pins, independent of device se- lection. Ver/BURST must be at Vin. Assuming that ad- dresses are stable, address access time (tacc) is equal to the delay from CE to output (tce). Data is available at the outputs toe after the falling edge of OE, assuming that CEhas been LOW and addresses have been stable for at least tacc toe. Initial Burst Access The Am27HB010 will enter the burst-mode when both Vep/BURST and CE are at logic 0. The last pinto switch from Vi to Vi (either Vep/BURST or CB), will determine the exact entry into the burst-mode. At this time the ad- dresses (AoAte) are latched internally to the device for the remainder of the burst access. There are no bound- ary address conditions for entering the burst-mode. The access time for the initial access is measured from when the addresses (A1 A1e) are stable. The delay in Aowill have no effect on access speed as long as the condi- tions listed in Switching Characteristics are met. Burst Read Mode After the initial access, sequential bytes of data may be accessed by toggling the Ao/CLK signal. Data will be available in the specified burst access time. There are no minimum or maximum amounts of data required fora burst. The device will perform a one byte burst or con- tinue to the physical end of the device, 128K if required. 6 Am27HB010AMD al The device will also wrap around and go to the very beginning of the memory once the physical boundary of the device is reached. To exit burst mode, Vep/BURST is toggled from Vit to Vin. Burst Suspend Mode Burst mode may be suspended by removing CE while Vpp/BURST is still at Vi. To resume burst mode, Vpp/ BURST remains at Vit while CE is re-asserted. Data will then be available within the burst access time. It should be noted that Ao has to be low while going into Burst Suspend Mode. Standby Mode The Am27HB010 has a TTL standby mode which reduces the maximum Vcc current to 20% of the active current. It is placed in standby mode when CE and Vpp/ BURST is at Vin. The amount of current drawn in standby mode depends on the frequency and the num- ber of address pins switching. The Am27HB010 is specified with 50% of the address fines toggling at 10 MHz. A reduction of the frequency or quantity of address lines toggling will significantly reduce the actual standby current. The Vcc DC current can further be de- creased to 1 mA by placing all inputs at steady CMOS logic levels. Output OR-Tieing To accommodate multiple memory connections, a two- line control function is provided to allow for: 1. Low memory power dissipation, and 2. Assurance that output bus contention will not occur. Itis recommended that CE be decoded and used as the primary device-selecting function, while OE be made a common connection to all devices in the array and con- nected to the READ line from the system control bus. This assures that all deselected memory devices are in their low-power standby mode and that the output pins are only active when data is desired from a particular memory device. System Applications During the switch between active and standby condi- tions, transient current peaks are produced on the rising and failing edges of Chip Enable. The magnitude of these transient current peaks is dependent on the out- put capacitance loading of the device. At a minimum, a 0.1 yF ceramic capacitor (high frequency, low inherent inductance) should be used on each device between Vcc and GND to minimize transient effects. In addition, to overcome the voltage drop caused by the inductive effects of the printed circuit board traces on EPROM ar- rays, a 4.7 pF bulk electrolytic capacitor should be used between Vcc and GND for each eight devices. The loca- tion of the capacitor should be close to where the power supply is connected to the array. Mode Select Table Mode Pins) GE | OE | PGM |AoCLK| As | Ver BURST | Outputs Read Vir VIL x x xX Vin Dout Output Disable Vit Vin x xX x x Hi-Z Standby Vin Xx Xx x x Vie Hi-Z BURST Enable Vit Vir x xX x Vit Dout BURST Suspend (Note 7) Vin Vin X X x Vit Hi-Z BURST Suspend (Note 7) VIH Vit xX x x Vit DouT BURST Read Vit Vit xX L-H xX Vir Dout Program Vit Vin Vit X X Vpp Din Program Verify Vit Vit VIH x X Vpp DouT Program Inhibit VIH x x xX X Vpp Hi-Z Auto Select |Manufacturer Code| Vit Vit xX Vit Vx Vin 01H (Notes 3 & 5)/Device Code Vi | Vin x Vin | Va Via OEH Notes: 1. VH=12.0V+t05V 2. X= Either Vi or Vin (cannot exceed Vcc + 0.5 V) 3. A1 As = A1o- Ate = VIL 4. See DC Programming Characteristics for Vpp voltage during programming. 5. The Am27HBO010 uses the same Flashrite algorithm during program as the Am27C010. 6. Vi < 0.8 V; ViH > 2.0 V 7. BURST suspend is entered only when CE toggles from Vit to ViH during Burst Mode operation. Am27HB010 7al AMD ABSOLUTE MAXIMUM RATINGS Storage Temperature: OTP product 65 to +125C All other products ~65 to +150C Ambient Temperature with Power Applied ~55 to +125C Voltage with Respect to Ground: All pins except Ag, Vep, and Vcc (Note 1) -0.6 to Vcc +0.6 V Ag and Vpp (Note 2) -0.6 to 13.5V Vcc -0.6 to 7.0 V Stresses above those listed under Absolute Maximum Rat- ings may cause permanent device failure. This is a stress rat- ing only; functional operation of the device at these limits or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure of the device to absolute maximum ratings for extended periods may affect device reliability. Notes: 1. During transitions, the input may overshoot GND to -2.0 V for periods of up to 10 ns. Maximum DC voltage on in- put and VO may overshoot to Vcc + 2.0 V for periods of up to 10 ns. 2. During transitions, Ag and Vpp may overshoot GND to -2.0 V for periods of up to 10 ns. Ag and Vep must not exceed 13.5 V for any period of time. OPERATING RANGES Commercial (C) Devices Case Temperature (Tc) 0 to +70C Industrial (I) Devices Case Temperature (Tc) 40 to +85C Extended Commercial (E) Devices Case Temperature (Tc) 55 to +125C Military (M) Devices Case Temperature (Tc) 55 to +125C Supply Read Voltages: Vcc for AmM27HB010-XX +4.50 to +5.50 V Operating ranges define those limits between which the func- tionality of the device is guaranteed. 8 Am27HB010AMD ct DC CHARACTERISTICS over operating ranges unless otherwise specified (Notes 1, 4, 5 & 8) (for APL Products, Group A, Subgroups 1, 2, 3, 7, and 8 are tested unless otherwise noted) Parameter Symbol | Parameter Description Test Conditions Min. Max. | Unit VoH Output HIGH Voltage lon = 4 mA 2.4 Vv Vou Output LOW Voltage lo. = 12 mA (C Devices) lo. = 10 mA (I Devices) 0.45 Vv lo. = 8 mA (E/M Devices) Vin Input HIGH Voltage (Note 9) 2.0 Vec +0.5) V Vit Input LOW Voltage (Note 9) -0.5 +0.8 Vv Iu input Load Current Vin = 0 Vto Vec + 0.5 V 1.6 pA ILo Output Leakage Current Vout = 0 V to + Vcc 10 pA lect Vcc Active Current (Note 5) CE=Vu, C/l Devices 400 f = 10 MHz mA lour =O mA . (Open Outputs) E/M Devices 120 Icce Vcc Standby Current (TTL) CE = Vin C/l Devices 25 Vee/BURST = Vin mA E/M Devices 35 ever) Vcc Standby Current (CMOS) CE = Vec - 0.3 V to Veo + 0.5 V 1.0 mA Vep/BURST = Vcc - 0.3 V to Voc + 0.5 V IPPs Vpp Current During Read (Note 6)| CE = OE = Vir, Vpp = Voc 100 pA CAPACITANCE (Notes 2, 3, & 7) Parameter Test PL 032 CDV032 CLV032 Symbol | Parameter Description Conditions Typ. | Max. | Typ.| Max. | Typ.| Max.| Unit Cint Address Input Capacitance Vin=O0V 6 12 6 12 6 12 pF Cina Vee Input Capacitance Vin=0V 12 20 12 20 12 20 pF Cout Output Capacitance Vout = 0 V 8 15 10 15 8 15 pF Notes: 1. Vcc must be applied simultaneously or before Vep, and removed simultaneously or after Vpp. 2. Typical values are for nominal supply voltages. 3. This parameter is only sampled, not 100% tested. 4. Caution: The Am27HB010 must not be removed from (or inserted into) a socket when Vpp or Vcc is applied. 5. Icc1 is tested with OE = ViH to simulate open outputs. 6. Maximum active power usage is the sum of Icc and IpP1, 7. Ta = 25C, f = 1 MHz. 8. During transitions, the inputs may overshoot to -2.0 V for periods less than 10 ns. Maximum DC voltage on output pins may overshoot to Vcc + 2.0 V for periods less than 10 ns. 9. Tested under static DC conditions. Am27HB010 9ra AMD SWITCHING CHARACTERISTICS over operating ranges unless otherwise specified (Notes 1, 3, & 4) Parameter Symbols Am27HB010 Parameter JEDEC | Standard |Description Test Conditions -50 55 -70 |-90] Unit tavav_ | tacc Address Access Time |CE=OE =Vu,CLr=Ciit 50 55 70 | 90] ns teacc Burst Access Time CE = OE = Vpp/BURST-} 15 15 20 | 30] ns Vii, Ci = Cus tecav | tce Chip Enable to OE = Vn, CL = Cur 50 55 70 190] ns Output Delay tetav | toe Output Enable to CE = Vu, CL =Cu 15 15 20 |30] ns Output Delay teHaz | tor Output Enable to CE = Vu, Ci = Cre 10 10 15 1251] ns (Note 2) Output Float taxax | tox Output Hold from Min. 0 0 0 0 Addresses, CE or OE, ns whichever occurs first Max. - ~ - - tseT Address Setup to CE = Vi, Ci = Cur 10 10 | 15 [25] ns BURST or CE Enable tHoLD1 Address Ao Hold to CE = Vi, CL = Cu 0 0 0 | 0] ns BURST or CE Enable tHoLpe Addresses Ai-AisHold | CE = OE = Ver/BURST-| 7 7 7 7 | ns to BURST or CE Enable | Vu, CL = Cu tecLkLow {Minimum Low Time for | CE = OE =Vpe/BURSI-| 10 10 15 | 25] ns for Ao to Start BURST Vi, Cr = Cu tasusps BURST Suspend Setup | Vpp/BURST = Vi, 10 10 15 | 251 ns Time Ci =Cu tBsuUSPH BURST Suspend Hold | Ver/BURST = Vit 10 10 15 | 25] ns Time Ci =Cu tBRES BURST Resume Setup | Vpe/BURST = Vit, 10 10 15 |25] ns Time Ct = Cu tetenMcLK |BURST Terminate Setup] Vee/BURST = Vin, 10 10 15 | 25] ns to Ao/CLOCK Time Ci = Cu tacik Minimum CLOCK HIGH | CE = OE = Vep/BURST.| 6 6 8 113] ns Time (Note 7) Vir, CL = Cus tecLks Minimum CLOCK LOW | CE = OE =Vpp/BURST-| 6 6 8 113] ns Time (Note 7) Vir, CL = Cus Notes: 1. 2 3. 4 Vcc must be applied simultaneously or before Vpp, and removed simultaneously or after Vp. . This parameter is only sampled, not 100% tested. Caution: The Am27HB010 must not be removed from (or inserted into) a socket or board when Vpp or Vcc is applied. . Output Load: 1 TTL gate and C = C, Input Rise and Fall Times: 3 ns for -50; 5 ns for -60; 7 ns for -90 Input Pulse Levels: 0 to 3 V Timing Measurement Reference Level: 1.5 V for inputs and outputs Transient Input Low Voltages to ~2.0 V with 10 ns duration at the 50% amplitude point are permitted. To guarantee Initial Burst Access, tsET + t8CLKLOW + tHOLD > tacc. Burst clocks should have 50% duty cycle. Clock skews are allowed as long as minimum tectk and tacLkB specitications are met and tBAcc = tBCLK + tBCLKB. 10 Am27HB010AMD al KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS OUTPUTS Must Be Will Be Steady Steady May Will Be Change Changing from H to L from H to L "May Will Be Change Changing from L toH from L to H Don't Care Changing Any Change State Permitted Unknown Does Not Center Apply Line is High Impedance Off State KS000010 SWITCHING TEST CIRCUIT Device Ri Under 4 WA OV. Test Re = 121 C VL = 1.9V t Ci: = 30pF Cl2 = 5SpF 14970-0058 SWITCHING TEST WAVEFORM 3V se Test Points 31.5 OV Input Output AC Testing: Inputs are driven at 3.0 V for a logic "1" and O fora logic O. Input pulse rise and fall times are < 3 ns for -50; < 5 ns for -60; and <7 for -90. 14970-006B Am27HB010 11ot AMD SWITCHING WAVEFORMS (Read TimingsRandom Access Mode) 3V Addresses 1.5V OV CE tacc (Note 1) Output Notes: 1. OE may be delayed up to tacc-toe after the falling edge of CE without impact on tacc. Addresses 2. tor is specified from OE or CE, whichever occurs first. SWITCHING WAVEFORMS (Burst Mode) _ KN f (Note 2) AVY High-Z 14970-007B VAVAVAVAVAVAVAVAVAVAVAVAVAVAVAVAVAVAVAVAVAVAVAVaVAVAVAVAVAVAVAVAVAVAVAVAVAVAVAVAVAVAVAVAVAVAVAV) Ai Ais x KYA Kh aw \__ANYX Ao/CLK \ A \\K I\J / tBCLK CE \ {BCLKLOW _*f'BCLKB J | tBSUSPH 'BRES \ tBACC IBSUSPS = 7 / OE \ Py tHOLD \ J Vep/BURST } tsET toe Outputs { Do x D1 xX D2 xX x tacc {CE tBTERMCLK Initial Burst Burst Burst Burst Burst Access (3 Bytes) Suspend Resume Terminate 14970-008C 12 Am27HB010AMD cl PROGRAMMING FLOW CHART Interactive Section Verity Section Start Address = First Location Vcc = 6.25 V Vep = 12.75 V Increment Address Program One 100 ps Pulse Verify Byte ? Pass Last Address? Vcc = Vpp = 5.25 V Device Failed Device Passed 14970-009B Am27HB010 13Pa AMD DC PROGRAMMING CHARACTERISTICS (Ta = +25C +5C) (Notes 1, 2, & 3) Parameter Symbol | Parameter Description Test Conditions Min. Max. { Unit Iu Input Current (All Inputs) Vin = Vitor Vin 10.0 pA Vit Input LOW Level (All Inputs) 0.3 0.8 Vv Vin Input HIGH Level 2.0 Vec +05] V Vor Output LOW Voltage During Verify lo. = 12 mA 0.45 Vv Vou Output HIGH Voltage During Verity lon = 4 mA 2.4 Vv Vu Ag Auto Select Voltage 11.5 12.5 Vv Icc3 Vec Supply Current (Program & Verify) 50 mA Ipp2 Vere Supply Current (Program) CE = Vu, OF = Vin 50 mA Vec1 Supply Voltage 6.00 6.50 Vv Vep Programming Voltage 12.5 13.0 Vv SWITCHING PROGRAMMING CHARACTERISTICS (Ta = +25C +5C) (Notes 1, 2, & 3) Parameter Symbols JEDEC Standard Parameter Description Min. Max. Unit {AVEL tas Address Setup Time 2 HS tozet toes OE Setup Time 2 bs tove tos Data Setup Time 2 ps IGHAX taH Address Hoid Time 0 ps tEHDX tox Data Hold Time 2 ys taHaz torp Output Enable to Output Float Delay 0 130 ns tves tves Vee Setup Time 2 HS teLeHt tw PGM Program Pulse Width 95 105 us tvcs tvcs Vcc Setup Time 2 ys tELPL {ces CE Setup Time 2 ps tctav toe Data Valid from OE 75 ns Notes: 1. Voc must be applied simultaneously or before Vep, and removed simultaneously or after Vpp. 2. When programming the Am27HBO010, a 0.1 uF capacitor is required across Vpp and ground to suppress spurious voltage transients which may damage the device. 3. Programming characteristics are sampled but not 100% tested at worst-case conditions. 14 Am27HB010AMD cl PROGRAMMING ALGORITHM WAVEFORM (Notes 1 & 2) Program Program Verify Addresses tas Data Data In Stable Data Out Valid 1Ds VPP Vcc Notes: 14970-0108 1. The input timing reference level is 0.8 for a Vit and 2 V for a Vin. 2. toe and toFp are characteristics of the device but must be accommodated by the programmer. Am27HB010 15ol AMD PHYSICAL DIMENSIONS CDV 032 Ceramic Dip with View iat 1,635 ~ 1.680 098 | "MAX I) oo) od ed eo eo) es a oo) od en sd co L 365 605 1 2 in _- = 100 _| a eee BSC 008 MIN 0185 060 4 +|. 2s 125 022 .160 4 FT 580 615 008 0 012 45 ae .150 MIN .700 { MAX 11092A 16 Am27HB010CLV 032 Ceramic Leadiess Chip Carrier with View .300 BSC .150 AMD cl .050 - BSC .045 055 -400 BSC 006 022 080 = .140 003 ||. 054 O15 BOTTOM VIEW INDEX CORNER dea .020 X 45 REF. OPTIONAL _ .040 X 45 REF. (3X) A } (OPTIONAL) aN j | 340 560 .530 MAX PLANE 2 # PLANE 1 - ig + 42 .458 TOP VIEW SIDE VIEW 08242F Am27HB010 17zl AMD PD 032 Plastic Dip (* 1.640 1.680 oO oo oo en oi oo en oe sn ) 1 oo mcs |b +e @ .110 005 , MIN 600 .015 625 .060 .140 e 225 t .008 AY rif . i 630 j | o 700 |. oe! la 125 014 - 7 12416B .022 BCS 160 7/12/91 cde PL 032 Plastic Leaded Chip Carrier .020 042 .050 MIN .048 REF 042 + "086 LS . Ds .032 q cf 585 547 4 : .400 .490 595 .553 REF .530 q ql q N [ il q ql jag ___447_ 015] .080 453 ~~ 1.095 oea71C 485 125 AW 9 PL 032 495 140" | 1/2/92 cde TOP VIEW SIDE VIEW 18 Am27HB010Sales Offices North American ALABANA.... (205) 882-9122 ARIZONA (602) 242-4400 CALIFORNIA, Culver City ...(213) 645-1524 Newport Beach . Sacramento(Roseville) .. ...(714) 752-6262 (916) 786-6700 San Diego... (619) 560-7030 San Jose..... (408) 452-0500 Woodland Hills .. CANADA, Ontario, ... (613) 592-0060 Willowdale .. .. (416) 224-5193 COLORADO .... ... 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(0483) 756196 North American Representatives____ CANADA Burnaby, B.C. - DAVETEK MARKETING (604) 430-3680 Kanata, Ontario VITEL ELECTRONICS ..........(613) 592-0060 Mississauga, Ontario - VITEL ELECTRONICS .(416) 676-9720 Lachine, Quebec VITEL ELECTRONICS ........ (514) 636-5951 ILLINOIS Skokie - INDUSTRIAL REPRESENTATIVES,ING occ (708) 967-8430 INDIANA Huntington - ELECTRONIC MARKETING CONSULTANTS, INC 0. ccc er teeetenes (317) 921-3450 Indianapolis - ELECTRONIC MARKETING CONSULTANTS, ING oe eeeeneeeeeneteeee (317) 921-3450 IOWA LORENZ SALES. ... (319) 377-4666 KANSAS - Merriam LORENZ SALES Wichita - LORENZ SALES KENTUCKY ELECTRONIC MARKETING CONSULTANTS, INC oo. cececeecserteneenteees (317) 921-3452 MICHIGAN Birmingham MIKE RAICK ASSOCIATES ........ (313) 644-5040 Holland - COM-TEK SALES, INC ... ..(616) 392-7100 Novi - COM-TEK SALES, INC (313) 227-0007 MINNESOTA Mel Foster Tech. Sales, Inc. .... (612) 941-9790 MISSOURI (913) 469-1312 (316) 721-0500 LORENZ SALES 0. eeeeeteteneteteeeee (314) 997-4558 NEBRASKA LORENZ SALES 0c ceeceeeeeteeetenee (402) 475-4660 NEW MEXICO THORSON DESERT STATES oe (505) 883-4343 NEW YORK East Syracuse ~ NYCOM, INC oo (315) 437-8343 Hauppauge ~ COMPONENT OHO NSULTANTS, ING oe eeeseeeeeeteneeeee (516) 273-5050 | Centerville ~ DOLFUSS ROOT & CO... Columbus - DOLFUSS ROOT & CO. (513) 433-6776 (614) 885-4844 Westlake - DOLFUSS ROOT & CO... (216) 899-9370 OREGON ELECTRA TECHNICAL SALES, INC... (503) 643-5074 PENNSYLVANIA RUSSELL F. CLARK CO.,ING. eee (412) 242-9500 PUERTO RICO COMP REP ASSOC, INC oor (809) 746-6550 WASHINGTON ELECTRA TECHNICAL SALES ... (206) 821-7442 WISCONSIN Brookfield INDUSTRIAL REPRESENTATIVES,ING ooo... cececceeceeaees (414) 789-9393 Advanced Micro Devices reserves the right to make changes in its product without notice in order to improve design or performance characteristics. The performance characteristics listed in this document are guaranteed by specific tests, guard banding, esign and other practices common to the industry. For specific testing details, contact your local AMD sales representative. The company assumes no responsibility for the use of any circuits described herein. Advanced Micro Devices, inc. 901 Thompson Place, P.O. Box? ~~ ~ =F AA Nang LICA 32649 J _ 8 | Tal: (408) 732-2400 TWX: 910-339-9280 + TELEX: 34-6306 APPLICATIONS HOTLINE & LITERATURE ORDERING - TO RECYCLED & i RECYCLABLE 1991 Advanced Micro Devices, Inc. 1/3/92 WCP-13.5M-1/92-0 Printed in USA