High Performance 512Kx8/256Kx16 5V CMOS Flash EEPROM AS29F400 (R) 512Kx8/256Kx16 CMOS Flash EEPROM Preliminary information Features * Organization: 512Kx8 or 256Kx16 * Sector architecture * Low power consumption - 35 mA maximum read current - 60 mA maximum program current - 1 A typical standby current (RESET = 0) - One 16K; two 8K; one 32K; and seven 64K byte sectors - Boot code sector architecture--T (top) or B (bottom) - Erase any combination of sectors or full chip * JEDEC standard software, packages and pinouts * Single 5.00.5V power supply for read/write operations * Sector protection * High speed 55/70/90/120/150 ns address access time * Automated on-chip programming algorithm - 48-pin TSOP - 44-pin SO * Detection of program/erase cycle completion - DQ7 DATA polling - DQ6 toggle bit - RY/BY output - Automatically programs/verifies data at specified address * Automated on-chip erase algorithm * Erase suspend/resume - Automatically preprograms/erases chip or specified sectors - Supports reading data from or programming data to a sector not being erased * 10,000 write/erase cycle endurance * Hardware RESET pin * Low VCC write lock-out below 3.2V - Resets internal state machine to read mode Logic block diagram Pin arrangement 48-pin TSOP VSS Input/output buffers Program/erase control Command register Program voltage generator AS29F400 STB Chip enable Output enable Logic CE OE A-1 STB Timer Data latch Y gating 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VCC detector Y decoder Address latch WE BYTE Erase voltage generator 44-pin SO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 RESET DQ0-DQ15 X decoder Cell matrix 1 2 44 43 WE A17 A7 3 4 42 41 RESET A8 A9 A6 A5 5 6 40 39 A10 A11 A4 A3 7 8 38 37 A12 A13 A2 9 36 A14 A1 A0 10 11 35 34 A15 A16 CE VSS 12 13 33 32 BYTE VSS OE DQ0 14 15 31 30 DQ15/A-1 DQ7 DQ8 DQ1 16 17 29 28 DQ14 DQ6 DQ9 DQ2 18 19 27 26 DQ13 DQ5 DQ10 DQ3 20 21 25 24 DQ12 DQ4 DQ11 22 23 VCC A16 BYTE V SS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 V CC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE V SS CE A0 A0-A17 NC RY/BY AS29F400 VCC Sector protect switches A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE RESET NC NC RY/BY NC A17 A7 A6 A5 A4 A3 A2 A1 RY/BY Selection guide 29F400-55 29F400-70 29F400-90 29F400-120 29F400-150 Unit Maximum access time tAA 55 70 90 120 150 ns Maximum chip enable access time tCE 55 70 90 120 150 ns Maximum output enable access time tOE 25 30 35 50 55 ns ALLIANCE SEMICONDUCTOR 1 AS29F400 Preliminary information (R) Functional description The AS29F400 is a 4 megabit, 5 volt only Flash memory organized as 512K bytes of 8 bits each or 256K words of 16 bits each. For flexible erase and program capability, the 4 megabits of data is divided into 11 sectors: one 16K byte, two 8K byte, one 32K byte, and seven 64K byte. The x8 data appears on DQ0-DQ7; the x16 data appears on DQ0-DQ15. The AS29F400 is offered in JEDEC standard 44-pin SO and 48-pin TSOP packages. This device is designed to be programmed and erased in-system with a single 5.0V VCC supply. The device can also be reprogrammed in standard EPROM programmers. The AS29F400 offers access times of 55/70/90/120/150 ns, allowing 0-wait state operation of high speed microprocessors. To eliminate bus contention the device has separate chip enable (CE), write enable (WE), and output enable (OE) controls. Word mode (x16 output) is selected by BYTE = High and Byte mode (x8 output) is selected by BYTE = Low. The AS29F400 is fully compatible with the JEDEC single power supply Flash standard. Write commands to the command register using standard microprocessor write timings. An internal state-machine uses register contents to control the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Read data from the device in the same manner as other Flash or EPROM devices. Use the program command sequence to invoke the automated on-chip programming algorithm that automatically times the program pulse widths and verifies proper cell margin. Use the erase command sequence to invoke the automated on-chip erase algorithm that preprograms the sector if it is not already programmed before executing the erase operation, times the erase pulse widths, and verifies proper cell margin. Boot sector architecture enables the device to boot from either the top (AS29F400T) or bottom (AS29F400B) sector. Sector erase architecture allows specified sectors of memory to be erased and reprogrammed without altering data in other sectors. A sector typically erases and verifies within 1.0 seconds. Hardware sector protection disables both program and erase operations in all or any combination of the eleven sectors. The device provides true background erase with Erase Suspend, which puts erase operations on hold to either read data from or program data to a sector that is not being erased. The chip erase command will automatically erase all unprotected sectors. A factory shipped AS29F400 is fully erased (all bits = 1). The programming operation sets bits to 0. Data is programmed into the array one byte/word at a time in any sequence and across sector boundaries. A sector must be erased to change bits from 0 to 1. Erase returns all bytes/words in a sector to the erased state (all bits = 1). Each sector is erased individually with no effect on other sectors. The device features single 5.0V power supply operation for read, write, and erase functions. Internally generated and regulated voltages are provided for the program and erase operations. A low VCC detector automatically inhibits write operations during power transtitions. The RY/BY pin, DATA polling of DQ7, or toggle bit (DQ6) may be used to detect end of program or erase operations. The device automatically resets to the read mode after program/erase operations are completed. DQ2 indicates which sectors are being erased. The AS29F400 resists accidental erasure or spurious programming signals resulting from power transitions. Control register architecture permits alteration of memory contents only after successful completion of specific command sequences. During power up, the device is set to read mode with all program/erase commands disabled when VCC is less than VLKO (lockout voltage). The command registers are not affected by noise pulses of less than 5 ns on OE, CE, or WE. CE and WE must be logical zero and OE a logical one to initiate write commands. When the device's hardware RESET pin is driven low, any program/erase operation in progress will be terminated and the internal state machine will be reset to read mode. If the RESET pin is tied to the system reset circuitry and a system reset occurs during an automated onchip program/erase algorithm, data in address locations being operated on will become corrupted and require rewriting. Resetting the device enables the system's microprocessor to read boot-up firmware from the Flash memory. The AS29F400 uses Fowler-Nordheim tunnelling to electrically erase all bits within a sector simultaneously. Bytes/words are programmed one at a time using EPROM programming mechanism of hot electron injection. 2 AS29F400 Preliminary information (R) Operating modes Mode CE OE WE A0 A1 A6 A9 RESET DQ ID read MFR code L L H L L L VID H Code ID read device code L L H H L L VID H Code Read L L H A0 A1 A6 A9 H DOUT Standby H X X X X X X H High Z Output disable L H H X X X X H High Z Write L H L A0 A1 A6 A9 H DIN Enable sector protect L VID Pulse/L L H L VID H X Sector unprotect L VID Pulse/L L H H VID H X Verify sector protect L L H L H L VID H Code Temporary sector unprotect X X X X X X X VID X Hardware Reset X X X X X X X L High Z L = Low (<VIL); H = High (>V IH); VID = 12.0 0.5V; X = don't care; In x16 mode, BYTE = VIH . In x8 mode, BYTE = VIL and DQ8-14 is High Z with DQ15 = A-1(X). Mode definitions Item Description ID MFR code, device code Selected by A9 = VID(11.5-12.5V), CE = OE = A1 = A6 = L, enabling outputs. When A0 is low (VIL) the output data = 52h, a unique Mfr. code for Alliance Semiconductor Flash products. When A0 is high (VIH), DOUT represents the device code for the 29F400. Read mode Selected with CE = OE = L, WE = H. Data is valid in tACC time after addresses are stable, tCE after CE is low and tOE after OE is low. Standby Selected with CE = H. Part is powered down, and ICC reduced to <1.0 mA for TTL input levels and <100 A for CMOS levels. If activated during an automated on-chip algorithm, the device completes the operation before entering standby. Output disable Part remains powered up; but outputs disabled with OE pulled high. Write Selected with CE = WE = L, OE = H. Accomplish all Flash erasure and programming through the command register. Contents of command register serve as inputs to the internal state machine. Address latching occurs on the falling edge of WE or CE, whichever occurs later. Data latching occurs on the rising edge WE or CE, whichever occurs first. Filters on WE prevent spurious noise events from appearing as write commands. Enable sector protect Hardware protection circuitry implemented with external programming equipment causes the device to disable program and erase operations for specified sectors. Sector unprotect Disables sector protection using external programming equipment. Verify sector protect Verifies write protection for sector. Sectors are protected from program/erase operations on commercial programming equipment. Determine if sector protection exists in a system by writing the ID read command sequence and reading location XXX02h, where address bits A12-17 select the defined sector addresses. A logical 1 on DQ0 indicates a protected sector; a logical 0 indicates an unprotected sector. Temporary sector unprotect Temporarily disables sector protection for in-system data changes to protected sectors. Apply +12V to RESET to activate temporary sector unprotect mode. During temporary sector unprotect mode, program protected sectors by selecting the appropriate sector address. All protected sectors revert to protected state on removal of +12V from RESET. 3 AS29F400 Preliminary information (R) Item Description RESET Resets the interal state machine to read mode. If device is programming or erasing when RESET = L, data may be corrupted. Deep power down Hold RESET low to enter deep power down mode (<1 A CMOS). Recovery time to active mode is 1.5 s. Flexible sector architecture Bottom boot sector architecture (AS29F400B) Top boot sector architecture (AS29F400T) Sector x8 x16 Size (Kbytes) x8 x16 Size (Kbytes) 0 00000h-03FFFh 00000h-01FFFh 16 00000h-0FFFFh 00000h-07FFFh 64 1 04000h-05FFFh 02000h-02FFFh 8 10000h-1FFFFh 08000h-0FFFFh 64 2 06000h-07FFFh 03000h-03FFFh 8 20000h-2FFFFh 10000h-17FFFh 64 3 08000h-0FFFFh 04000h-07FFFh 32 30000h-3FFFFh 18000h-1FFFFh 64 4 10000h-1FFFFh 08000h-0FFFFh 64 40000h-4FFFFh 20000h-27FFFh 64 5 20000h-2FFFFh 10000h-17FFFh 64 50000h-5FFFFh 28000h-2FFFFh 64 6 30000h-3FFFFh 18000h-1FFFFh 64 60000h-6FFFFh 30000h-37FFFh 64 7 40000h-4FFFFh 20000h-27FFFh 64 70000h-77FFFh 38000h-3BFFFh 32 8 50000h-5FFFFh 28000h-2FFFFh 64 78000h-79FFFh 3C000h-3CFFFh 8 9 60000h-6FFFFh 30000h-37FFFh 64 7A000h-7BFFFh 3D000h-3DFFFh 8 10 70000h-7FFFFh 38000h-3FFFFh 64 7C000h-7FFFFh 3E000h-3FFFFh 16 In word mode, there are one 8K word, two 4K word, one 16K word, and seven 32K word sectors. Address range is A17-A-1 if BYTE = VIL; address range is A17-A0 if BYTE = VIH. ID Sector address table Bottom boot sector address (AS29F400B) Top boot sector address (AS29F400T) Sector A17 A16 A15 A14 A13 A12 A17 A16 A15 A14 A13 A12 0 0 0 0 0 0 X 0 0 0 X X X 1 0 0 0 0 1 0 0 0 1 X X X 2 0 0 0 0 1 1 0 1 0 X X X 3 0 0 0 1 X X 0 1 1 X X X 4 0 0 1 X X X 1 0 0 X X X 5 0 1 0 X X X 1 0 1 X X X 6 0 1 1 X X X 1 1 0 X X X 7 1 0 0 X X X 1 1 1 0 X X 8 1 0 1 X X X 1 1 1 1 0 0 9 1 1 0 X X X 1 1 1 1 0 1 10 1 1 1 X X X 1 1 1 1 1 X 4 AS29F400 Preliminary information (R) READ codes Mode A17-A12 A6 A1 A0 Code MFR code (Alliance Semiconductor) X L L L 52h x8 T boot X L L H 23h x8 B boot X L L H ABh x16 T boot X L L H 2223h x16 B boot X L L H 22ABh Sector address L H L 01h protected 00h unprotected Device code Sector protection Key: L =Low (<V IL ); H = High (>VIH); X =Don't care; T = top; B = bottom Command format Command sequence Reset/Read Required bus cycles 1 x16 Reset/Read 1st bus write cycle 2nd bus write cycle 3rd bus write cycle 4th bus write cycle 5th bus write cycle 6th bus write cycle Address Data Address Data Address Data Address Data Address F0h Read Address Read Data F0h Read Address Read Data XXXXh 5555h 4 2AAAh AAh 5555h 55h x8 AAAAh 5555h AAAAh x16 5555h 2AAAh 5555h 01h Device code AutoselectI D Read x8 AAAAh 4 5555h AAh Address Data 2223h (T) 22ABh (B) 23h (T) ABh (B) AAAAh 55h Data 90h 00h MFR code 52h x16/x8 XXX02h Sector protection x16 Program 5555h 4 x8 x16 Chip Erase x8 x8 AAAAh 1 XXXXh B0h Sector Erase Resume 1 XXXXh 30h 2AAAh AAh AAAAh 55h 5555h 10h AAAAh 2AAAh AAh AAAAh 5555h 55h 5555h 5555h 80h AAAAh Program Data 5555h 5555h 55h 5555h Program Address 80h AAAAh 2AAAh AAh Sector Erase Suspend 1 2 3 4 5 6 5555h 55h 5555h 5555h 6 A0h AAAAh 2AAAh AAh AAAAh x16 5555h 55h 5555h 5555h 6 Sector Erase 2AAAh AAh AAAAh 01 = protected 00 = unprotected Sector Address 30h Bus operations defined in "Mode definitions," on page 3. Reading from and programming to non-erasing sectors allowed in Erase Suspend mode. Address bit A15 = X = Don't care for all address commands except Program Address and Sector Address. Address bit A16 = X = Don't care for all address commands except Program Address and Sector Address. Address bit A17 = X = Don't care for all address commands except Program Address and Sector Address. System should generate address patterns: x16 mode - 5555h or 2AAAh to addresses A0-A14; x8 mode - AAAAh or 5555h to addresses A-1-A14. 5 AS29F400 Preliminary information (R) Command definitions Item Description Reset/Read Initiate read or reset operations by writing the Read/Reset command sequence into the command register. This allows the microprocessor to retrieve data from the memory. Device remains in read mode until command register contents are altered. Device automatically powers up in read/reset state. This feature allows only reads, therefore ensuring no spurious memory content alterations during power up. AS29F400 provides manufacturer and device codes in two ways. External PROM programmers typically access the device codes by driving +12V on A9. AS29F400 also contains an ID Read command to read the device code with only +5V, since multiplexing +12V on address lines is generally undesirable. ID Read Initiate device ID read by writing the ID Read command sequence into the command register. Follow with a read sequence from address XXX00h to return MFR code. Follow ID Read command sequence with a read sequence from address XXX01h to return device code. To verify write protect status on sectors, read address XXX02h. Sector addresses A17-A12 produce a 1 on DQ0 for protected sector and a 0 for unprotected sector. Exit from ID read mode with Read/Reset command sequence. Hardware Reset Holding RESET low for 500 ns resets the device, terminating any operation in progress; data handled in the operation is corrupted. The internal state machine resets 20 s after RESET is driven low. RY/BY remains low until the RESET operation is completed. After RESET is set high, there is a delay of 1.5 s for the device to permit read operations. Programming the AS29F400 is a four bus cycle operation performed on a byte-by-byte or wordby-word basis. Two unlock write cycles precede the Program Setup command and program data write cycle. Upon execution of the program command, no additional CPU controls or timings are necessary. Addresses are latched on the falling edge of CE or WE, whichever is last; data is latched on the rising edge of CE or WE, whichever is first. The AS29F400's automated on-chip program algorithm provides adequate internally-generated programming pulses and verifies the programmed cell margin. Byte/word Programming Check programming status by sampling data on the DATA polling (DQ7), toggle bit (DQ6), or RY/BY pin. The AS29F400 returns the equivalent data that was written to it (as opposed to complemented data), to complete the programming operation. The AS29F400 ignores commands written during programming. A hardware reset occurring during programming may corrupt the data at the programmed location. AS29F400 allows programming in any sequence, across any sector boundary. Changing data from 0 to 1 requires an erase operation. Attempting to program data 0 to 1 results in either DQ5 = 1 (exceeded programming time limits) or success according to DATA polling; reading this data after a read/reset operation returns a 0. When programming time limit is exceeded, DQ5 reads high, and DQ6 continues to toggle. In this state, a Reset command returns the device to read mode. Chip erase requires six bus cycles: two unlock write cycles; a setup command, two additional unlock write cycles; and finally the Chip Erase command. Chip Erase 6 Chip erase does not require logical 0s to be written prior to erasure. When the automated on-chip erase algorithm is invoked with the Chip Erase command sequence, AS29F400 automatically programs and verifies the entire memory array for an all-zero pattern prior to erase. The AS29F200 returns to read mode upon completion of chip erase unless DQ5 is set high as a result of exceeding time limit. AS29F400 Preliminary information (R) Item Description Sector erase requires six bus cycles: two unlock write cycles, a setup command, two additional unlock write cycles, and finally the Sector Erase command. Identify the sector to be erased by addressing any location in the sector. The address is latched on the falling edge of WE; the command, 30h is latched on the rising edge of WE. The sector erase operation begins after a 80 s time-out. Sector Erase To erase multiple sectors, write the Sector Erase command to each of the addresses of sectors to erase after following the six bus cycle operation above. Timing between writes of additional sectors must be <80 s, or the AS29F400 ignores the command and erasure begins. During the 80 s time-out period any falling edge of WE resets the time-out. Any command (other than Sector Erase or Erase Suspend) during time-out period resets the AS29F400 to read mode, and the device ignores the sector erase command string. Erase such ignored sectors by restarting the Sector Erase command on the ignored sectors. The entire array need not be written with 0s prior to erasure. AS29F400 writes 0s to the entire sector prior to electrical erase; writing of 0s affects only selected sectors, leaving non-selected sectors unaffected. AS29F400 requires no CPU control or timing signals during sector erase operations. Automatic sector erase begins after 80 s time-out from the last rising edge of WE from the sector erase command stream and ends when the DATA polling (DQ7) is logical 1. DATA polling address must be performed on addresses that fall within the sectors being erased. AS29F400 returns to read mode after sector erase unless DQ5 is set high by exceeding the time limit. Erase Suspend allows interruption of sector erase operations to read data from or program data to a sector not being erased. Erase suspend applies only during sector erase operations, including the time-out period. Writing an Erase Suspend command during sector erase time-out results in immediate termination of the time-out period and suspension of erase operation. AS29F400 ignores any commands during erase suspend other than Read/Reset, Program or Erase Resume commands. Writing the Erase Resume Command continues erase operations. Addresses are DON'T CARE when writing Erase Suspend or Erase Resume commands. Erase Suspend AS29F400 takes 0.1-15 s to suspend erase operations after receiving Erase Suspend command. To determine completion of erase suspend, either check DQ6 after selecting an address of a sector not being erased, or poll RY/BY. Check DQ2 in conjunction with DQ6 to determine if a sector is being erased. AS29F400 ignores redundant writes of Erase Suspend. While in erase-suspend mode, AS29F400 allows reading data (erase-suspend-read mode) from or programming data (erase-suspend-program mode) to any sector not undergoing sector erase, treated as standard read or standard programming mode. AS29F400 defaults to erase-suspend-read mode while an erase operation has been suspended. Write the Resume command 30h to continue operation of sector erase. AS29F400 ignores redundant writes of the Resume command. AS29F400 permits multiple suspend/resume operations during sector erase. Sector Protect When attempting to write to a protected sector, DATA polling and Toggle Bit 1 (DQ6) are activated for about <1 s. When attempting to erase a protected sector, DATA polling and Toggle Bit 1 (DQ6) are activated for about <5 s. In both cases, the device returns to read mode without altering the specified sectors. Ready/Busy RY/BY indicates whether an automated on-chip algorithm is in progress (RY/BY = low) or completed (RY/BY = high). The device does not accept Program/Erase commands when RY/BY = low. RY/BY= high when device is in erase suspend mode. RY/BY is an open drain output, enabling multiple RY/BY pins to be tied in parallel with a pull up resistor to VCC. 7 AS29F400 Preliminary information (R) Status operations DATA polling (DQ7) Only active during automated on-chip algorithms or sector erase time outs. DQ7 reflects complement of data last written when read during the automated on-chip algorithm (0 during erase algorithm); reflects true data when read after completion of an automated on-chip algorithm (1 after completion of erase agorithm). Toggle bit 1 (DQ6) Active during automated on-chip algorithms or sector time outs. DQ6 toggles when CE or OE toggles, or an Erase Resume command is invoked. DQ6 is valid after the rising edge of the fourth pulse of WE during programming; after the rising edge of the sixth WE pulse during chip erase; after the last rising edge of the sector erase WE pulse for sector erase. For protected sectors, DQ6 toggles for <1 s during writes, and <5 s during erase (if all selected sectors are protected); in both cases, data is unaffected. Exceeding time limit (DQ5) Indicates unsuccessful completion of program/erase operation (DQ5 = 1). DATA polling remains active; CE powers the device down to 2 mA. If DQ5 = 1 during chip erase, all or some sectors are defective; during sector erase, the sector is defective (in this case, reset the device and execute a program or erase command sequence to continue working with functional sectors); during byte programming, that particular byte is defective. Attempting to program 0 to 1 will set DQ5 = 1. Sector erase timer (DQ3) Checks whether sector erase timer window is open. If DQ3 = 1, erase is in progress; no commands will be accepted. If DQ3 = 0, the device will accept sector erase commands. Check DQ3 before and after each Sector Erase command to verify that the command was accepted. Toggle bit 2 (DQ2) During sector erase, DQ2 toggles with OE or CE only during an attempt to read a sector being erased. During chip erase, DQ2 toggles with OE or CE for all addresses. If DQ5 = 1, DQ2 toggles only at sector addresses where failure occurred, and will not toggle at other sector addresses. Use DQ2 in conjunction with DQ6 to determine whether device is in auto erase or erase suspend mode. Write operation status Status DQ7 DQ6 DQ5 DQ3 DQ2 Auto programming (byte/word) DQ7 Toggle 0 0 No toggle Erase suspend mode 0 1 Toggle 0 Read erasing sector 1 No toggle 0 0 Toggle 1 Read non-erasing sector Data Data Data Data Data 1 Program in erase suspend DQ7 Toggle 0 0 Toggle 0 DQ7 Toggle 1 0 No toggle 0 Program/erase in auto erase Program in erase suspend 0 DQ7 Toggle Toggle Toggles with OE or CE only for erasing or erase suspended sector addresses. Toggles only if DQ5 = 1 and address applied is within sector that exceeded timing limits. DQ8-DQ15 = Don't care in x16 mode. 8 0 Toggle Auto programming (byte/word) Exceeded time limits 0 Program/erase in auto erase In progress RY/BY 1 1 1 0 0 0 Toggle Toggle AS29F400 Preliminary information (R) Automated on-chip programming algorithm Automated on-chip erase algorithm Write erase command sequence (see below) Write program command sequence (see below) DATA polling or toggle bit successfully completed DATA poll device Erase complete Chip erase command sequence x16 mode (address/command): Sector erase command sequence x16 mode (address/command): 5555h/AAh 5555h/AAh Programming completed 2AAAh/55h 2AAAh/55h Program command sequence x16 mode (address/command): 5555h/80h 5555h/80h 5555h/AAh 5555h/AAh 2AAAh/55h 2AAAh/55h 5555h/10h Sector address/30h Verify byte? NO YES 5555h/AAh 2AAAh/55h 5555h/A0h Program address/program data Sector address/30h Optional multiple sector erase commands Sector address/30h The system software should check the status of DQ3 prior to and following each subsequent sector erase command to ensure command completion. The device may not have accepted the command if DQ3 is high on second status check. 9 AS29F400 Preliminary information (R) DATA polling algorithm Toggle bit algorithm Read byte (DQ0-DQ7) Address = VA Read byte (DQ0-DQ7) Address = don't care DQ7 = data ? DQ6 = toggle ? YES DONE NO NO DQ5 = 1 ? NO DQ5 = 1 ? YES Read byte (DQ0-DQ7) Address = VA Read byte (DQ0-DQ7) Address = don't care DQ7 = data ? DQ6 = toggle ? YES DONE NO VA = Byte address for programming. VA = any of the sector addresses within the sector being erased during Sector Erase. VA = valid address equals any non-protected sector group address during Chip Erase. DQ7 rechecked even if DQ5 = 1 because DQ5 and DQ7 may not change simultaneously. NO DONE YES FAIL 10 DONE YES YES NO FAIL DQ6 rechecked even if DQ5 = 1 because DQ6 may stop toggling when DQ5 changes to 1. AS29F400 Preliminary information (R) DC electrical characteristics VCC = 5.00.5V Parameter Symbol Test conditions Min Max Unit Input load current ILI VIN = VSS to VCC, VCC = VCC MAX - 1 A A9 Input load current ILIT VCC = VCC MAX, A9 = 12.5V 90 A ILO - 1 A IOS VOUT = VSS to VCC, VCC = VCC MAX VOUT = 0.5V - 200 mA ICC CE = VIL, OE = VIH - 35 mA ICC2 CE = VIL, OE = VIH - 60 mA Standby current (TTL) ISB1 CE = OE = VIH, VCC = VCCMAX, RESET = VIH - 1.0 mA Standby current (CMOS) ISB2 CE = VCC + 0.5V, OE = VIH, VCC = VCC MAX, RESET = VCC 0.5V - 100 A Deep power down current ISB3 RESET = VSS 0.3V - 5.0 A Input low voltage VIL -0.5 0.8 V Input high voltage VIH 2.0 VCC + 0.5 V Output low voltage VOL IOL = 5.8mA, VCC = VCC MIN - 0.45 V VOH1 IOH = -2.5 mA, VCC = VCC MIN 2.4 - V VOH2 IOH = -100 A, VCC = VCC MIN VCC - 0.4 - V Output leakage current Output short circuit current 1 Active current, read @ 6MHz 2 Active current, program/erase Output high voltage 3 Low VCC lock out voltage VLKO 3.2 4.2 V Input HV select voltage VID 11.5 12.5 V 1 2 3 Not more than one output tested simultaneously. Duration of the short circuit must not be >1 second. VOUT = 0.5V was selected to avoid test problems caused by tester ground degradation. (This parameter is sampled and not 100% tested, but guaranteed by characterization.) The ICC current listed includes both the DC operating current and the frequency dependent component (@ 6 MHz). The frequency component typically is less than 2 mA/MHz with OE at VIH . ICC active while program or erase operations are in progress. Maximum negative overshoot waveform 20 ns +0.8V -0.5V 20 ns AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AAA 20 ns AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AAA -2.0V Maximum positive overshoot waveform VCC+2.0V AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AA VCC+0.5V AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AA +2.0V 20 ns AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAA A AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAA A 20 ns 20 ns 11 AS29F400 Preliminary information (R) AC parameters: read cycle -55 -70 -90 -120 -150 JEDEC Symbol Std Symbol Parameter Min Max Min Max Min Max Min Max Min Max Unit tAVAV tRC Read cycle time 55 - 70 - 90 - 120 - 150 - ns tAVQV tACC Address to output delay - 55 - 70 - 90 - 120 - 150 ns tELQV tCE Chip enable to output - 55 - 70 - 90 - 120 - 150 ns tGLQV tOE Output enable to output - 25 - 30 - 35 - 50 - 55 ns tEHQZ tDF Chip enable to output High Z - 15 - 20 - 20 - 30 - 35 ns tGHQZ tDF Output enable to output High Z - 15 - 20 - 20 - 30 - 35 ns tAXQX tOH Output hold time from addresses, first occurrence of CE or OE 0 - 0 - 0 - 0 - 0 - ns tELFL/ELFH CE to BYTE transition low/high - 5 - 5 - 5 - 5 - 5 ns tPWH RESET high to output delay - 1.5 - 1.5 - 1.5 - 1.5 - 1.5 s tBDEL BYTE switching to valid data - 55 - 70 - 90 - 120 - 150 ns tFLQZ BYTE low to DQ8-DQ15 tri-state 25 - 30 - 35 - 50 - 55 - ns tPHQV Key to switching waveforms AAAAAAA AAAAAAA AAAA AAA Rising input AAAAAAA AAAAAAA AAA AAAA AAAAAAA AAAAAAA AAAA AAA Falling input Undefined output/don't care Read waveform tRC Addresses AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAA A AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAA A AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A Addresses stable tACC CE tDF tOE OE tOEH WE tOH tCE Outputs AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA Output validAAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA High Z tELFL/ELFH BYTE tBDEL tPWH RESET 12 High Z AS29F400 Preliminary information (R) AC parameters -- write cycle WE controlled -55 -70 -90 -120 -150 JEDEC Symbol Std Symbol Parameter Min Max Min Max Min Max Min Max Min Max Unit tAVAV tWC Write cycle time 55 - 70 - 90 - 120 - 150 - ns tAVWL tAS Address setup time 0 - 0 - 0 - 0 - 0 - ns tWLAX tAH Address hold time 40 - 45 - 45 - 50 - 50 - ns tDVWH tDS Data setup time 25 - 30 - 45 - 50 - 50 - ns tWHDX tDH Data hold time 0 - 0 - 0 - 0 - 0 - ns tOES Output enable setup time 0 - 0 - 0 - 0 - 0 - ns tOEH Output enable hold time: Toggle and data polling 10 - 10 - 10 - 10 - 10 - ns tREADY RESET pin low to read mode 20 - 20 - 20 - 20 - 20 - s tRP RESET pulse 500 - 500 - 500 - 500 - 500 - ns tGHWL tGHWL Read recover time before write 0 - 0 - 0 - 0 - 0 - ns tELWL tCS CE setup time 0 - 0 - 0 - 0 - 0 - ns tWHEH tCH CE hold time 0 - 0 - 0 - 0 - 0 - ns tWLWH tWP Write pulse width 35 - 35 - 45 - 50 - 55 - ns tWHWL tWPH Write pulse width high 20 - 20 - 20 - 20 - 20 - ns tWHWH1 tWHWH1 Programming time 15 - 15 - 15 - 15 - 15 - s tWHWH2 tWHWH2 Erase time 0.3 - 0.3 - 0.3 - 0.3 - 0.3 - sec Write waveform WE controlled tWC Addresses 3rd bus cycle tAS 5555h Program address tAH tCH DATA polling AAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA Program address CE tGHWL; tOES OE tWP WE DATA tCS tWHWH1 or 2 tWPH tDH A0h tDS Program data DQ7 DOUT VSS 13 AS29F400 Preliminary information (R) AC parameters--write cycle 2 CE controlled -55 -70 -90 -120 -120 JEDEC Symbol Std Symbol Parameter Min Max Min Max Min Max Min Max Min Max Unit tAVAV tWC Write cycle time 55 - 70 - 90 - 120 - 150 - ns tAVEL tAS Address setup time 0 - 0 - 0 - 0 - 0 - ns tELAX tAH Address hold time 40 - 45 - 45 - 50 - 50 - ns tDVEH tDS Data setup time 25 - 30 - 45 - 50 - 50 - ns tEHDX tDH Data hold time 0 - 0 - 0 - 0 - 0 - ns tOES Output enable setup time 0 - 0 - 0 - 0 - 0 - ns Output enable hold time: Read 0 - 0 - 0 - 0 - 0 - ns tOEH Output enable hold time: Toggle and data polling 10 - 10 - 10 - 10 - 10 - ns tGHEL tGHEL Read recover time before write 0 - 0 - 0 - 0 - 0 - ns tWLEL tWS WE setup time 0 - 0 - 0 - 0 - 0 - ns tEHWH tWH WE hold time 0 - 0 - 0 - 0 - 0 - ns tELEH tCP CE pulse width 35 - 35 - 45 - 50 - 55 - ns tEHEL tCPH CE pulse width high 20 - 20 - 20 - 20 - 20 - ns Programming time 15 - 15 - 15 - 15 - 15 - s - sec tWHWH1 tWHWH1 tWHWH2 tWHWH2 Erase time 0.3 - 0.3 - 0.3 - 0.3 - Write waveform 2 Addresses CE controlled AAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AAA Program address AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AAA 5555h tWC tAS DATA polling Program address AAAAAAAAAAAAAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AAA DQ7 DOUT tAH WE tGHEL, tOES OE tCP tWHWH1 or 2 CE tCPH tDH Data A0h tDS 14 0.3 Program data AS29F400 Preliminary information (R) Erase waveform x16 mode only tWC Addresses tAS 5555h 2AAAh 5555h 5555h 2AAAh Sector address tAH CE tGHWL OE tWP tWC WE tWPH tCS Data 10h for Chip Erase tDH AAh 55h 80h AAh 55h 30h tDS RESET waveform CE AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AAA RY/BY tRP RESET tREADY RY/BY waveform CE Rising edge of last WE signal WE RY/BY Program/erase operation tri-stated open-drain DATA polling waveform CE tCH tDF tOE OE tOEH WE DQ7 tCE Input DQ7 AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA tOH Output DQ7 Output AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA High Z tWHWH1 or 2 15 AS29F400 Preliminary information (R) Toggle bit waveform CE tOEH WE OE DQ6 AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA tDH tOE Erase and programming performance Limits Parameter Min Typical Max Unit Sector erase and verify-1 time (excludes 00h programming prior to erase) - 1.0 - sec Word programming time - 15 - s Byte program time - 15 - s Chip programming time - 2.5 - sec Erase program cycles - - 10,000 cycles Latchup tolerance Parameter Min Max Unit Input voltage with respect to VSS on A9, OE, and RESET pin -1.0 +13.0 V Input voltage with respect to VSS on all DQ, address and control pins -1.0 VCC+1.0 V Current -100 +100 mA Includes all pins except VCC. Test conditions: VCC = 5.0V, one pin at a time. AC test conditions +5.0V 1N3064 or equivalent 2.7K Device under test 6.2K 100 pF* VSS *including scope and jig capacitance 16 1N3064 or equivalent VSS VSS AS29F400 Preliminary information (R) Recommended operating conditions Parameter Supply voltage Input voltage Symbol Min Typ Max Unit VCC +4.5 5.0 +5.5 V VSS 0 0 0 V VIH 2.0 - VCC + 0.5 V VIL -0.5 - 0.8 V Absolute maximum ratings Parameter Symbol Min Max Unit Input voltage (Input or DQ pin) VIN -2.0 +7.0 V Input voltage (A9 pin, OE, RESET) VIN -2.0 +13.0 V Power supply voltage VCC -0.5 +5.5 V Operating temperature TOPR -55 +125 C Storage temperature (plastic) TSTG -65 +125 C Short circuit output current IOUT - 200 mA Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. TSOP pin capacitance Symbol Parameter Test setup Typ Max Unit CIN Input capacitance VIN = 0 6 7.5 pF COUT Output capacitance VOUT = 0 8.5 12 pF CIN2 Control pin capacitance VIN = 0 8 10 pF Symbol Parameter Test setup Typ Max Unit CIN Input capacitance VIN = 0 6 7.5 pF COUT Output capacitance VOUT = 0 8.5 12 pF CIN2 Control pin capacitance VIN = 0 8 10 pF Temp.(C) Min Unit 150 10 years 125 20 years SO pin capacitance Data retention Parameter Minimum pattern data retention time 17 AS29F400 Preliminary information (R) Package dimensions h 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 48-pin TSOP j g e i f d a b c d e f g h i j 48-pin TSOP min (mm) max (mm) - 1.20 - 0.25 0.5 0.7 0.1 0.21 18.30 18.50 19.80 20.20 11.90 12.10 0.95 1.05 0.05 0.15 - 0.50 m n o p q r s t u w 44-pin SO min (mm) max (mm) 28.00 28.40 0.35 0.50 0.10 0.35 2.17 2.45 - 2.80 1.27 - 13.10 13.50 15.70 16.30 0.06 1.00 0.10 0.21 a 0-5 c b w 0-8 u 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 44-pin SO s t 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 r q p n m 18 o AS29F400 Preliminary information (R) AS29F400 ordering codes Package \ Access Time 55ns (commercial only) 70 ns (commercial/industrial) 90 ns (commercial/industrial) 120 ns (commercial/industrial) 150 ns (commercial/industrial) AS29F400B-55TC AS29F400B-70TC AS29F400B-70TI AS29F400B-90TC AS29F400B-90TI AS29F400B-120TC AS29F400B-120TI AS29F400B-150TC AS29F400B-150TI AS29F400T-55TC AS29F400T-70TC AS29F400T-70TI AS29F400T-90TC AS29F400T-90TI AS29F400T-120TC AS29F400T-120TI AS29F400T-150TC AS29F400T-150TI AS29F400B-55SC AS29F400B-70SC AS29F400B-70SI AS29F400B-90SC AS29F400B-90SI AS29F400B-120SC AS29F400B-120SI AS29F400B-150SC AS29F400B-150SI AS29F400T-55SC AS29F400T-70SC AS29F400T-70SI AS29F400T-90SC AS29F400T-90SI AS29F400T-120SC AS29F400T-120SI AS29F400T-150SC AS29F400T-150SI TSOP, 12x20 mm, 48-pin SO, 600 mil wide, 44-pin AS29F400 part numbering system AS29F 400 X -XXX Flash EEPROM prefix Device number B (bottom) or T (top) boot block Address access time X Package: X S= SO T= TSOP Temperature range: C = Commercial: 0C to 70C I = Industrial: -40C to 85C 19 AS29F400 (R) Representatives and sales offices DOMESTIC REPS ILLINOIS NEBRASKA RHODE ISLAND ALABAMA El-Mech 3511 N. Cicero Avenue Chicago, IL 60641 (312) 794-9100 CenTech 3751 Pennridge Dr., Suite #107 Bridgeton, MO 63044 (314) 291-4230 CenTech 10312 East 63rd Terrace Raytown, MO 64133 (816) 358-8100 Kitchen & Kutchin Associates 87 Cambridge Street Burlington, MA 01803 (617) 229-2660 NEVADA SOUTH CAROLINA Brooks Technical Group 883 N. Shoreline Blvd. Mountain View, CA 94043 (415) 960-3880 Concord Component Reps 10608 Dunhill Terrace Raleigh, NC 27615 (919) 846-3441 NEW HAMPSHIRE SOUTH DAKOTA Kitchen & Kutchin Associates 87 Cambridge Street Burlington, MA 01803 (617) 229-2660 D.A. Case Associates 4620 W. 77th Street Suite #250 Minneapolis, MN 55435 (612) 831-6777 Concord Component Reps 190 Lime Quarry, Suite #102 Madison, AL 35758 (205) 772-8883 ARKANSAS Southern States Marketing 1702 N. Collins Blvd., Suite #250 Richardson, TX 75080 (214) 238-7500 CALIFORNIA North: Brooks Technical Group 883 N. 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Case Associates 4620 W. 77th Street Suite #250 Minneapolis, MN 55435 (612) 831-6777 MISSOURI Concord Component Reps 6825 Jimmy Carter Blvd. 1303 Norcross, GA 30071 (770) 416-9597 CenTech 3751 Pennridge Dr., Suite #107 Bridgeton, MO 63044 (314) 291-4230 CenTech 10312 East 63rd Terrace Raytown, MO 64133 (816) 358-8100 HAWAII MISSISSIPPI Brooks Technical Group 883 N. Shoreline Blvd. Mountain View, CA 94043 (415) 960-3880 Concord Component Reps 190 Lime Quarry, Suite #102 Madison, AL 35758 (205) 772-8883 IDAHO MONTANA ES/Chase 6655 SW Hampton, Suite #120 Tigard, OR 97223 (503) 684-8500 ES/Chase 6655 SW Hampton, Suite #120 Tigard, OR 97223 (503) 684-8500 GEORGIA NEW YORK OKLAHOMA Southern States Marketing 1702 N. Collins Blvd., Suite #250 Richardson, TX 75080 (214) 238-7500 OREGON ES/Chase 6655 SW Hampton, Suite #120 Tigard, OR 97223 (503) 684-8500 PENNSYLVANIA Electro Tech 621 E. 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Tel:+886-2-516-7995 Fax:+886-2-517-4928 alliance@netra.wow.net.tw Alliance Semiconductor reserves the right to make changes in this data sheet at any time to improve design and supply the best product possible. Publication of advance information does not constitute a committment to produce or supply the product described. The company cannot assume responsibility for circuits shown or represent that they are free from patent infringement. Alliance products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of Alliance. ProMotion(R) and the Alliance logo are registered trademarks of Alliance Semiconductor Corporation. All other trademarks are property of their respective holders. 3099 North First Street Printed in U.S.A. ALLIANCE SEMICONDUCTOR San Jose, CA 95134 Tel (408) 383-4900 Fax (408) 383-4999 Copyright (c) 1996 All rights reserved. BBS: (408) 383-4994 www.alsc.com September 1996