ANALOG DEVICES +15 V Qperation Digital Potentiometer AD7376* FEATURES 128 Position Potentiometer Replacement 10 kO, 50k, 100 ko, 1M Power Shutdown: Less than 71 pA 3-Wire SPI Compatible Serial Data Input +5 V to +30 V Single Supply Operation +5 V to +15 V Dual Supply Operation Midscale Preset APPLICATIONS Mechanical Potentiometer Replacement Instrumentation: Gain, Offset Adjustment Programmable Voltage-to-Current Conversion Programmable Filters, Delays, Time Constants Line Impedance Matching Power Supply Adjustment GENERAL DESCRIPTION The AD7376 provides a single channel, 128-position digitally- controlled variable resistor (VR) device. This device performs the same electronic adjustment function as a potentiometer or vari- able resistor. These products were optimized for instrument and test equipment applications where a combination of high voltage with a choice between bandwidth or power dissipation are avail- able as a result of the wide selection of end-to-end terminal resis- tance values. The AD7376 contains a fixed resistor with a wiper contact that taps the fixed resistor value at a point determined by a digital code loaded into the SPI-compatible serial-input regis- ter. The resistance between the wiper and either endpoint of the fixed resistor varies linearly with respect to the digital code trans- ferred into the VR latch. The variable resistor offers a completely programmable value of resistance between the A terminal and the wiper or the B terminal and the wiper. The fixed A to B terminal resistance of 10 kQ, 50 kQ, 100 kQ or 1 MQ has a nominal tem- perature coefficient of -300 ppmfC. The VR has its own VR latch which holds its programmed resis- tance value. The VR latch is updated from an internal serial-to- parallel shift register which is loaded from a standard 3-wire serial-input digital interface. Seven data bits make up the data word clocked into the serial data input register (SDI). Only the last seven bits of the data word loaded are transferred into the 7-bit VR latch when the CS strobe is returned to logic high. A serial data output pin (SDQ) at the opposite end of the serial register allows simple daisy-chaining in multiple VR applications without additional external decoding logic. The reset (RS) pin forces the wiper to the midscale position by loading 40, into the VR latch. The SHDN pin forces the resistor *Patent Number: 5495245 REV. 0 Information furnished by Analog Devices is believed to be accurate and teliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. FUNCTIONAL BLOCK DIAGRAM AD7376 Yop q A 7-BIT TF 7-BIT | 7 SERIAL LATCH w REGISTER B SDI BD cK a Vas cLK cS GND fs SHDN to an end-to-end open circuit condition on the A terminal and shorts the wiper to the B terminal, achieving a microwatt power shutdown state. When shutdown is returned to logic high, the previous latch settings put the wiper in the same resistance setting prior to shutdown as long as power to Vpp is not re- moved. The digital interface is still active in shutdown so that code changes can be made that will produce a new wiper posi- tion when the device is taken out of shutdown. The AD 7376 is available in both surface mount (SOL-16) and the 14-lead plastic DIP package. For ultracompact solutions selected models are available in the thin TSSOP package. All parts are guaranteed to operate over the extended industrial temperature range of -40C to +85C. For operation at lower supply voltages (+3 V to +5 V), see the AD8400/AD8402/ AD 8403 products. spi 13 5 (DATAIN) | 9 x tos > | 1 0 1 Ov +1 LSB ERROR BAND +1 LSB Figure 1. Detail Timing Diagram The last seven data bits clocked into the serial input register will be transferred to the VR 7-bit latch when CS returns to logic high. Extra data bits are ignored. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http: /www.analog.com Fax: 781/326-8703 Analog Devices, Inc., 1997AD7376SPECIAICATIONS ELECTRICAL CHARACTERISTICS (VoolVeg = 15 V+ 10% or + 5V + 10%, Vy= +Vip, Va= Vogl V, 40C < Tye 485C unless otherwise noted.) Parameter | Symbol | Conditions Min Typ Max | Units DC CHARACTERISTICS RHEOSTAT MODE (Specifications Apply to All VRs) Resistor Differential NL? R-DNL Rwe, a=NC 1 +0.25 +1 LSB Resistor N onlinearity* R-INL Rwe. a = NC -l1 40.5 +1 LSB Nominal Resistor Tolerance AR Ta=4+25C -30 30 % Resistance Temperature Coefficient RapiAT Vap= Yoo, Wiper = No Connect -300 ppm/fc Wiper Resistance Ry Tw = +15 VW/Ryomiwac 120 200 Q Wiper Resistance Rw ly = +5 V/Rweomiwac 200 QO DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE (Specifications Apply to All VRs) Resolution N 7 Bits Integral N onlinearity INL -1 +0.5 41 LSB Differential Nonlinearity? DNL -1 +0.1 +1 LSB Voltage Divider Temperatute Coefficient | AWVy/AT Code = 404 5 ppm/fc Full-Scale Error Vwese Code = 7Fy -2 -0.5 +0 LSB Zero-Scale Error Vwzse Code = 004 0 40.5 +1 LSB RESISTOR TERMINALS Voltage Range* VaB.w Vss Von | Capacitance? A, B Cas f= 1 MHz, Measured to GND, Code = 404 45 pF Capacitance? W Cw f= 1MHz, Measured to GND, Code = 404 60 pF Shutdown Supply Current Ta sp V,= Von, Va= 0 V, SHDN = 0 0.01 1 pA Shutdown Wiper Resistance Rw sp Va= Yoo. Vp= 0, SHDN = 0, Vpp = 415 V 170 6.400 || 8 Comimon-M ode Leakage Tem V,= Ve= Vw 1 nA DIGITAL INPUTS AND OUTPUTS Input Logic High Vin Von = +5 Vor+15V 2.4 Vv Input Logic Low Vit Von = +5 Vor+15V 0.8 Vv Output Logic High Vou Rp = 2.2 k2to+5 V 4.9 Vv Output Logic Low Voi Toy = 1.6 mA, Viogic = +35 , Vpp = +15 V 0.4 Vv Input Current In Vin = 0 Vor+15 +1 pA Input Capacitance? Cw 5 pF POWER SUPPLIES Power Supply Range VopVss Dual Supply Range +4.5 +16.5| V Power Supply Range Vop Single Supply Range, Vss = 0 4.5 28 Vv Supply Current Ipp Vin = +5 V ot Vip = OV, Vpp = +5 V 0.0001 0.01 mA Supply Current Too Vin =4+5 VorVy = OV, Voo =4+15V 0.75 2 mA Supply Current Iss Vin = +5 Vor Vip = OV, Vss = -5 Vor-15 0.02 0.1 mA Power Dissipation* Poss Vin = +5 V or Vy = OV, Vpp = +15 V, Vsg =-15 V 11 30 mW Power Supply Sensitivity PSS AVpp = +5 V+ 10%, or AVss = -5 V4 10% 0.05 O15 | %/% PSS AVpp = +15 VE 10% or AVs5 = -15 V+ 10% 0.01 0.02 | %/% DYNAMIC CHARACTERISTICS? * & Bandwidth 3 dB BW_10K | Rag = 10 kQ, Code = 40, 520 kHz Bandwidth 3 dB BW_S50K Rap = 50 k2, Code = 404 125 kHz Bandwidth 3 dB BW_100K | Rag = 100k, Code = 404 60 kHz T otal Harmonic Distortion THDy V,= 1 Vis, Vg=0V,f = 1kHz 0.005 Go Vy Settling Time ts V, = 10 V, Vg = 0 V, +1 LSB Error Band 4 ps Resistor Noise Voltage en _we Rwe = 25 kQ, f= 1 kHz, RS=0 14 nVVHz INTERFACE TIMING CHARACTERISTICS (Applies to All Parts [N otes 5, 11]) Input Clock Pulsewidth ton, ter Clock Level High or Low 120 ns Data Setup Time tos 30 ns Data Hold Time tou 20 ns CLK to SDO Propagation Delay" tep R, = 2.2 kQ, C. < 20 pF 10 100 | ns cs Setup Time tess 120 ns CS High Pulsewidth tesw 150 ns Reset Pulsewidth tes 120 ns CLK Rise to CS Rise Hold Time tesu 120 ns CS Rise to Clock Rise Setup tes 120 ns 2 REY. 0AD7376 NOTES 'Typicals represent average readings at +25C, Vpp = +15 V, and Vg, = -L5 V. Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper posi- tions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 27. Test Circuit. 3INL and DNL are measured at Vy with the RD AC configured as a potentiometer divider similar to a voltage output D/A converter. V4 = Vpp and Vz = 0 V. DNL specification limits of +1 LSB maximum are Guaranteed Monotonic operating conditions. See Figure 26. Test Circuit. *Resistor terminals A, B, W have no limitations on polarity with respect to each other. >Guaranteed by design and not subject to production test. Measured at the A terminal. A terminal is open circuit in shutdown mode. "To = 200 LA for the 50 kQ version operating at Vypp = +5 V. Poiss is calculated from (Ipp s pp). CMOS logic level inputs result in minimum power dissipation. *Bandwidth, noise and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest band- width. The highest R value results in the minimum overall power consumption. MO All dynamic characteristics use Vypp = +15 V and Ves = -L5 V. USee timing diagram for location of measured values. All input control voltages are specified with ty = te = 1 ns (10% to 90% of V,,) and timed from a voltage level of 1.6 . Switching characteristics are measured using both Vpp = +5 Vor4+15 V. Propagation delay depends on value of Vpp, R,, and C,, see Applications section. Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS (Ta = 425C, unless otherwise noted) Vop to GND V3 toGND Vop to Vas Va, Ve, Vw to GND Ax _ By, Ax Wx, Bx -Wyx Digital Input Voltages to GND Digital Output Voltage to GND Operating Temperature Range Maximum Junction Temperature (T} MAX) Storage Temperature Lead Temperature (Soldering, 10 sec) Package Power Dissipation PIN CONFIGURATIONS P & TSSOP-14 e 4] w fa] NC rz] Ypp ii] spa AD7376 TOP VIEW (Not to Scala) [a] 801 Bit PDI bocce ees eeeteceeveeees -0.3 V, +30V Cv b cee eeeseseeeeereees 40.3 V, -16.5V alt bcc cee eesseeteeeveeees -0.3-V,+44V ale be ee ee Vss, Vop v, By Levee een e eee eeeeees +20 mA 8s eee 0 V, Vpp + 0.3 V eno [A Lov c ee veeneees OV, +30V cs] Liebe sees -40C to +85C Asp] Leena +150C cLk[7 | Love bub eve seneens -65C to +150C Ll eeeeeeenee +300C Thermal Resistance Oj, P-DIP (N-14) SOIC (SOL-16) TSSOP-14 CAUTION 92C /W 120C -W 240C (W NC = NO CONNECT ORDERING GUIDE ho] SHON SOL-16 a[ile of Ves [3] enp [4] oJ El rs [5] clk 7] ne [3] AD7376 TOP VIEW (Not to Scala) lie] w 15] Nc 14] Yop iia] D0 2] SHON ri] $01 [io] Ne [a] Nc NC = NO CONNECT Temperature Package Package M adel ko Range Description Options AD7376AN 10 LO -40C to +85C PDIP-14 N-14 AD7376AR10 LO -40C to +85C SOL-16 R-16 AD7376ARU 10 LO 40C to +85C TSSOP-14 RU-14 AD7376AN50 50 40C to +85C PDIP-14 N-14 AD7376AR50 50 -40C to +85C SOL-16 R-16 AD7376ARU 50 50 40C to +85C TSSOP-14 RU-14 AD7376AN 100 100 40C to +85C PDIP-14 N-14 AD7376AR100 100 40C to +85C SOL-16 R-16 AD7376ARU100 | 100 40C to +85C TSSOP-14 RU-14 AD7376AN 1M 1,000 40C to +85C PDIP-14 N-14 AD7376ARIM 1,060 40C to +85C SOL-16 R-16 AD7376ARU 1M 1,060 40C to +85C TSSOP-14 RU-14 Die Size: 101.6 mil x 127.6 mil, 2.58 mm x 3.24 mm Number Transistors: 840 ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7376 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. 0 _3_ WARNING! ee ed ESD SENSITIVE DEVICEAD7376-Typical Performance Characteristics 100 oe) 0.25 2 0.4 0.20 e # 0.3 0.15 1 75 Zu 0.2 @ 0.10 =9 4 4 3 ! 1 oa bo. a 0.05 wa o o Om 50 ce oO ra id ce oc o be ui Wi lig a4 =! 0.05 G2 = a Ty = 485C be oc 0.2 oe 0.10 ao 25 - C 3 15 Woo = +15" 2 ss = " Awe Fwy 4 0.20 ag = SOKSL D 05 0.25 D 32 64 96 128 0 16 32 48 64 8D 96 112 128 0 16 32 48 64 80 96 112 128 CODE Dacimal CODE Decimal CODE - Dacimal Figure 2. Wiper To End Terminal Figure 3. Resistance Step Position Figure +. Relative Resistance Step Percent Resistance vs. Code Nonlinearity Error vs. Code Change from ideal vs. Code ~ 90 15 T T T 2 lw = 1D0pA, Ty = +25C i Vasey f DATA = 40, Dag pp=+ 1.2 2 Veg =-15 fe = 50k2. NOMINAL qi y @ {NX iB 4a % og r 1 Q 2 |UN e' 16 N 5 , i a Pa Ww | z 46 03 z 7Fy 3 = 45 o a5 a5 415.5 25 45 65 85 105 125 D O25 OS O75 1 1.25 15 1.75 2 5 10 1s 20 25 30 TEMPERATURE C lwa- mA SUPPLY VOLTAGE (Vpp - Vgg) Volts Figure 5. Nominal Resistance vs Figure 6. Resistance Linearity vs. Figure 7. Resistance Nonlinearity Temperature Conduction Current Error vs. Supply Voltage 10 20 1000 Va = 25V 15 3 900 | Rag = SURLY Vp = OV 10 ano 8 CODE = 40,, | wg g - we 5 = 700 Rag = 50kn = & E Vop = i oft oo 2 600 pp. m 0.6 J a a gg = OV zo Q NL wl o 5 fc 500 a IW fa pp =* b 400 Z o4 Pee RE 18 gg =-15V 5 B Q -15 Vaz +25 S$ 300 Vp = OV 4 = -20 850 <T c i 200 0.2 <Ty<t8> o 25 = 50k2. = 100 pp=+15V Veg =15V o 30 o 5 10 15 2D 2 30 D 16 32 48 64 80 96 112 128 55-35 -15 5 25 45 65 85 105 125 SUPPLY VOLTAGE (Vpp - Vag) Volts CODE = Dacimal TEMPERATURE C Figure 8. Potentiometer Divider Figure 9. AVy,/AT Potentiometer Figure 10. Wiper Contact Nonlinearity Error vs. Supply Mode Tempco Resistance vs. Temperature Voltage 4 REV. 0AD/7376 0.25 0.20 O15 6.10 0.05 0.05 pp =+15V -o.10 | Yss = -15V Va =+2.5 0.15 p= OV 0.20 | Rag = 50k Ty =+85C INL NONLINEARITY ERROR - LSB 0.25 0 616 632 48 64 80 96 112 128 CODE Dacimal Figure 11. Potentiometer Divider Nonlinearity Error vs. Code -6 -12 GAIN -dB & 4 = 415V 48 Vou =-15 Vamp = 50mrms 1k 10k 100k 1M FREQUENCY Hz Figure 14. 10 kQ Gain vs. Frequency vs. Code E=7Fy | Rag = S0kD oO E=40 4 -6 H 12 1D, o 1B | z 24)AMP = a Vpp = +15 O44 O30 "yo. =-15V g5= 02, 36/7 R_ = 1MO Oty 42 A 48 B GP275 54 1k 10k 100k 1M FREQUENCY Hz Figure 17. 50 kQ Gain vs. Frequency vs. Code REV. 0 6.25 6.20 6.15 Go.10 0.05 DNL - LSB a 0.05 Vop=+ 6.10 gg = 15 Va=4+2.5V Vp =0V 0.20 ag = 5Ok2. 0.15 0.25 G6 16 32 48 64 #80 96 112 128 CODE Dacimal Figure 12. Potentiom eter Divider Differential Nonlinearity Error vs. Code GAIN- dB CODE=01, Vpp =+15 Vgg =-15 VampL = 50mrms Ran =1M0 100 1k 10k ol 100k FREQUENCY Hz Figure 15. 1 MQ Gain vs. Frequency vs. Code 2pS/DI Figure 18. Large Signal Settling Time Vop=+ Veg = -15V Rap = 50k. RHEOSTAT MGDE TEMPCO - ppm o 16 32 48 64 80 96 112 128 CODE Decimal Figure 13. ARwz/AT Rheostat Mode Tempco oO) PRE ec iis atl ol Peeks SS/DIV Figure 16. Midscale Transition Ghitch 1.0 pp =+ Vgg =-15 V,=+10Vpp oA = 40, # NON-INVERTINGR,, = SOkKfL 1 MODE TEST Q CKT FIG 36 = FE 0.010 ON-INVERTI MODE TEST 0.001 FIG 35 0.0005 1o 100 1k 10k 200k FREQUENCY Hz Figure 19. Total Harmonic Distortion Plus Noise vs. FrequencyAD7376 -12 mo -18 a | 2 -24 3 30 36 42 Vpp = +15 Vg =-15 48 VeupL= 50mrms = 100k 1k 10k 100k 1M FREQUENCY Hz Figure 20. 100 kQ Gain vs. Frequency vs. Code 0.1 1 O.2 0.3 | z 04 | pp = +15 < Veo =15V Go5+,55 Vamp_ = 5Somrms 0.5 | CODE = 40, 0.7 Al w 0.8 B OPR275 0.9 10 100 1k 10k FREQUENCY Hz 100k 1M Figure 23. Gain Flatness vs Fre- quency vs. Nominal Resistance Rap 10 Ipp@ pp = +15. Viogic = +5 Ipp@Vpp = +15, Vlogic = OF = o gs = -15V, Viogic = +15V Ipp@Vpp = +5, VLogic = +0.8 SUPPLY CURRENT - mA 9 0.010 = gic = Rap = 50k2 0.001 55-35 15 5 25 45 65 85 105 125 TEMPERATURE C Figure 26. Supply Current (pp. Iss} vs. Temperature 18 Vpp = +15 Vag =-15V Vamec = SOomrms 36 E=40, GAIN dB & 1k 10k 100k 1M FREQUENCY Hz Figure 21. 3 dB Bandwidth vs. Nominal Resistance 90 z 80 Vpp = +15V+10% Vgg =-15V 70 Vpp = +15 mo 50 Veg =15V410% | m 50 oc a 40 30 20 Vpp = +5+ 10% Vg =-5V 19 10 100 1k 10k 100k FREQUENCY Hz Figure 24. Power Supply Rejection vs. Frequency 1.6 0.1 6.010 SHUTDOWN CURRENT pA 0.001 55-35 -15 5 25 45 65 85 105 125 TEMPERATURE C Figure 27. ly sp Shutdown Current vs. Tem perature SUPPLY CURRENT mA Figure 22. Clock Feedthrough 400 K Ta= fare 4 Vop = +8V 30 PNA \ ves =-5v 300 Von = +15 \ DD 250 Veg =-15V Y 200 nd 150 P| 100 50 P SEE FIGURE 38 TEST CIRCUIT D | | | | -15 -10 5 6 5 16 15 Vp Volts Figure 25. Incremental Wiper Contact Resistance vs. Com mon-Mode Voltage 1k 10k CLOCK FREQUENCY - Hz 100k 1M 10M Figure 28. Ipp Supply Current vs. input Clock Frequency REV. 0AD/7376 3.5 3.0 | 2 25 | az . Lr oo c 20 Fu _ Va=t5 ee isl Ve =0 8 FB ral g= Sa Vag = OV E 51.0 a Zz 0.5 oD 5 10 15 20 25 30 Figure 29. Input Logic Threshold Voltage vs. SUPPLY VOLTAGE (Vpp) Volts Vop Supply Voltage 1600 1200 4 B00 | NX 2 Von =+15 - Vag =15 400 NI Vop = +5 } Vag = OV OR SY NN o an 1 oO 5 10 15 Figure 30. Supply Current (pp) vs. Logic Voltage Vioaic PARAMETRIC TEST CIRCUITS V+ = Vpp DUT 1LSB = V+128 Sa wi 4 B Vas Vv Figure 31. Potentiometer Divider Nonlinearity Error Test Circuit INL. DNL) NO CONNECT lw A DUT fw 4. =< B Vis Vv Figure 32. Resistor Position Nonlinearity Error (Rheostat Operation; R-INL, R-DNL) REV. 0 Ins put [4 w z<4 B Vv Vw lw = 1/RNoMINAL = Vus V+ Vop Ry =_Ywe- (ws + Iw [Rawll Rew) lw WHERE Vyyq = Vag WHEN hy = 0 AND Vwe = Vas WHEN lw= 1/R Figure 33. Wiper Resistance Test Circuit V+ = Vpp +10% OR Veg +10% - AVMs PSRR (dB) = 20L0G (44 ) AVMS% v Ms AVe% PSS (96/%) = Figure 34. Power Supply Sensitivity Test Circuit (PSS. PSRR) Figure 35. Inverting Programmable Gain Test Circuit oO Vout Figure 36. Noninverting Programmable Gain Test Circuit +18V OP275 MO VouT -18V Figure 37. Gain vs. Frequency Test CircuitAD7376 _ ov low CODE = 00, os O-},. = O1V Rew BUT V5 TO Vpp Figure 38. Incremental ON Resistance Test Circuit Figure 39. Common-Mode Leakage Current Test Circuit OPERATION The AD7376 provides a 128-position digitally-controlled vari- able resistor (VR) device. Changing the programmed VR set- tings is accomplished by clocking in a 7-bit serial data word into the SDI (Serial Data Input) pin, while CS is active low. When CS returns high the last seven bits are transferred into the RD AC latch setting the new wiper position. The exact timing require- ments are shown in Figure L. The AD 7376 resets to a midscale by asserting the RS pin, sim- plifying initial conditions at power-up. Both parts have a power shutdown SHDN pin which places the RD AC in a zero power consumption state where terminal A is open circuited and the wiper W is connected to B, resulting in only leakage currents being consumed in the VR structure. In shutdown mode the YR latch settings are maintained so that, returning to opera- tional mode from power shutdown, the VR settings return to their previous resistance values. B- I SHDN O------------ ---+--[ 0-9 Ast D6 Bs Ast D4 7 fos} D2 ow D1 Ast Do 1 Joel J z RDAC 1 bd 1 LATCH i & DECODER r 7 is# B Rg = Byominar128 Figure 40. AD7376 Equivalent RDAC Circuit PROGRAMMING THE VARIABLE RESISTOR Rheostat O peration The nominal resistance of the RDAC between terminals A and B are available with values of 10 kQ, 50 kQ, 100 kQ and 1 MQ. The final three characters of the part number determine the nominal resistance value, e.g., 10 kQ = 10; 50 kG = 50; 100 kQ = 100; 1 MQ = 1M. The nominal resistance (Rag) of the VR has 128 contact points accessed by the wiper terminal, plus the B terminal contact. The 7-bit data word in the RDAC latch is decoded to select one of the 128 possible settings. The wipers first connection starts at the B terminal for data 004. This B-termi- nal connection has a wiper contact resistance of 120 Q. The second connection (10 kQ part) is the first tap point located at 198 2 (= Rga [nominal resistance]/128 + Rw = 78 @ + 120 Q) for data Oly. The third connection is the next tap point repre- senting 156 + 120 = 276 for data 024. Each LSB data value increase moves the wiper up the resistor ladder until the last tap point is reached at 10041 . The wiper does not directly con- nect to the B terminal. See Figure 40 for a simplified diagram of the equivalent RD AC circuit. The general transfer equation that determines the digitally pro- grammed output resistance between W and B is: Awe{D) = (D)/128 x Rea + Aw (1) where D is the data contained in the 7-bit VR latch, and Apa is the nominal end-to-end resistance. For example, when Vg = 0 V and A+erminal is open circuit, the following output resistance values will be set for the following YR latch codes (applies to the 10 kQ potentiometer). Table I. D Rwe (DEC); (9) Output State 127 10041 Full-Scale 64 5120 Midscale (RS = 0 Condition) 1 276 | LSB 0 198 Zero-Scale (Wiper Contact Resistance) Note that in the zero-scale condition a finite wiper resistance of 120 Qis present. Care should be taken to limit the current flow between W and B in this state to a maximum value of 5 mA to avoid degradation or possible destruction of the internal switch contact. Like the mechanical potentiometer the RDAC replaces, it is totally symmetrical. The resistance between the wiper W and terminal A also produces a digitally controlled resistance Rwa. When these terminals are used the B+erminal should be tied to the wiper. Setting the resistance value for Rw, starts at a maxi- mum value of resistance and decreases as the data loaded in the latch is increased in value. The general transfer equation for this operation is: Rwa(D) = (128-D)/128 x Apa + Aw (2) where D is the data contained in the 7-bit RDAC latch, and Apa is the nominal end-to-end resistance. For example, when Va= 0 V and B-terminal is tied to the wiper W the following output resistance values will be set for the following RD AC latch codes. REV. 0AD/7376 Table ll. D Rwa (DEC) (Q) Output State 127 74 Full-Scale 64 5035 Midscale (RS = 0 Condition) 1 9996 1 LSB 0 10035 Zero-Scale The typical distribution of Rg, from device to device matching is process lot dependent having a +30% variation. The change in RBA with temperature has a -300 ppm/C temperature coefficient. PROGRAMMING THE POTENTIOMETER DIVIDER Voltage Output Operation The digital potentiometer easily generates an output voltage proportional to the input voltage applied to a given terminal. For example connecting A-terminal to +5 V and B-terminal to ground produces an output voltage at the wiper which can be any value starting at zero volts up to 1 LSB less than +5 V. Each LSB of voltage is equal to the voltage applied across terminal AB divided by the 128-position resolution of the potentiometer divider. The general equation defining the output voltage with respect to ground for any given input voltage applied to termi- nals AB is: Vw(D) = DiL28 x Vag + Ve Operation of the digital potentiometer in the divider mode results in more accurate operation over temperature. Here the output voltage is dependent on the ratio of the internal resis- tors, not the absolute value; therefore, the drift improves to 5 ppm/c, AD7376 sbo Q 7-BIT 7 SERIAL REGISTER SDI DB cK cLk cs GND RS Figure 41. Block Diagram DIGITAL INTERFACING The AD7376 contains a standard three-wire serial input control interface. The three inputs are clock (CLK), CS and serial data input (SDI). The positive-edge sensitive CLK input requires REV. 0 clean transitions to avoid clocking incorrect data into the serial input register. Standard logic families work well. If mechanical switches are used for product evaluation they should be de- bounced by a flip-flop or other suitable means. When CS is taken active low the clock loads data into the serial register on each positive clock edge, see Table ITI. The last seven bits clocked into the serial register will be transferred to the 7-bit RDAC latch, see Figure 41. Extra data bits are ignored. The serial-data-output (SDO) pin contains an open drain n-channel FET. This output requires a pull-up resistor in order to transfer data to the next packages SDI pin. This allows for daisy chain- ing several RDACs from a single processor serial data line. Clock period needs to be increased when using a pull-up resistor to the SDI pin of the following device in the series. Capacitive loading at the daisy chain node SDO-SDI between devices must be accounted for to successfully transfer data. When daisy chaining is used, the CS should be kept low until all the bits of every package are clocked into their respective serial registers insuring that the data bits are in the proper decoding location. This would require 14 bits of data when two AD7376 RDACs are daisy chained. During shutdown (SHDN) the SDO output pin is forced to the off (logic high state) to disable power dissi- pation in the pull up resistor. See Figure 42 for equivalent SDO output circuit schematic. Table Ill. Input Logic Control Truth Table CLK | CS | RS | SHDN| Register Activity L L H /8 Enables SR, enables SDO pin. P L H |H Shifts one bit in from the SDI pin. The seventh previously entered bit is shifted out of the SDO pin. xX P H |H Loads SR data into 7-bit RDAC latch. H No Operation. c Sets 7-bit RDAC latch to mid- scale, wiper centered, and SDO latch cleared. x H P H Latches 7-bit RDAC latch to 40y. xX H H |L Opens circuits resistor A-terminal, connects W to B, turns off SDO output transistor. NOTE P = positive edge, X = dont care, SR = shift register.AD7376 The data setup and data hold times in the specification table determine the data valid time requirements. The last seven bits of the data word entered into the serial register are held when CS returns high. At the same time CS goes high it transfers the 7-bit data to the VR latch. SHON cs spo soI pecisten {Da cK AS ck [> AS Figure 42. Detail SDO Output Schematic of the AD7376 All digital inputs are protected with a series input resistor and parallel Zener ESD structure shown in Figure 43. Applies to digital input pins CS, SDI, SDO, RS, SHDN, CLK 1Q Locic Figure 43. Equivalent ESD Protection Circuit Yop A,B,W Ves Figure 44. Equivalent ESD Protection Analog Pins REV. 0AD/7376 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 0.015 (0.38) 14-Lead Plastic DIP 14-Lead TSSOP (N-14) (RU-14) 0.795 (20.19) 0.201 (5.10) 0-725 (18.42) " 0.193 (4.90) Pa 14 | [| 0.280 (7.11} * ; es (6.10} 0.325 (8.25) J 8 a avd so 0.300 (7.62) 0.195 (4.95) B & 8 PIN 1 0.060 (1.52) /= ee 5|5 aA F (2.93) 0.210 (5.33) max 4 Lf Lf} LIL LL 1 0.130 D.160 (4.06) JIN (3.30) 7 7 D115 (293) pig he: MIN 0.015 (0.381) ny 0.022 (0.558) 0.100 0.070(1.77) seaine 0.008 (0.204) PIN 4 0.014 (0.356) es 0.045 (1.15) 0.006 (0.15) 0.002 (0.05) 0.0433 (1.10) fee aie MAX + 9.028 (0.70) Ti SEATING 7-5255 2 0.0118 (0.30) 0.020 (0.50} PLANE (2:55) 0.0075 (0.19) acer (020) BSC 0.0035 (0.090} 16-Lead Wide Body SOIC 0.4133 (10.50) 0.3977 (10.00) (R-16) PRAAR AEE f 16 a] * a|a 8)e wo) -| L Ble ele L nN = g\R 2/8 1 sl|FS cla 2 ma ue EU gg rot PIN 1 0.1043 (2.65) 0.0291 (0. 74) 0.0118 (0.30) 0.0926 (2.35) *| [* c.0098 (0.25 (0. 25) * 0.0040 (0.10) a + ee oot ba 2 ge 0.0500 (1.27) reo 0.0192 (0.49) o- aTiNG 0.0125 (0.32) o 0.0157 (0.40) BSC 0.0138 (0.35) PLANE 0.0091 (0.23) REV. 0 l1J-L6/01-8-9T 5 WSN NI GA.LNIad 1?