EV-ADF4355SD1Z - Analog Devices

Microwave Wideband Synthesizer

with Integrated VCO

Data Sheet

ADF4355

FEATURES

RF output frequency range: 54 MHz to 6800 MHz

Fractional-N synthesizer and integer-N synthesizer

High resolution 38-bit modulus

Low phase noise, voltage controlled oscillator (VCO)

Programmable divide by 1, 2, 4, 8, 16, 32, or 64 output

Analog and digital power supplies: 3.3 V

Charge pump and VCO power supplies: 5.0 V typical

Logic compatibility: 1.8 V

Programmable dual modulus prescaler of 4/5 or 8/9

Programmable output power level

RF output mute function

3-wire serial interface

Analog and digital lock detect

APPLICATIONS

Wireless infrastructure (W-CDMA, TD-SCDMA, WiMAX, GSM,

PCS, DCS, DECT)

Point to point/point to multipoint microwave links

Satellites/VSATs

Test equipment/instrumentation

Clock generation

GENERAL DESCRIPTION

The ADF4355 allows implementation of fractional-N or

integer-N phase-locked loop (PLL) frequency synthesizers

when used with an external loop filter and an external reference

frequency. A series of frequency dividers permits operation

from 54 MHz to 6800 MHz.

The ADF4355 has an integrated VCO with a fundamental

output frequency ranging from 3400 MHz to 6800 MHz. In

addition, the VCO frequency is connected to divide by 1, 2, 4, 8,

16, 32, or 64 circuits that allow the user to generate RF output

frequencies as low as 54 MHz. For applications that require

isolation, the RF output stage can be muted. The mute function

is both pin and software controllable.

Control of all on-chip registers is through a simple 3-wire interface.

The ADF4355 operates with analog and digital power supplies

ranging from 3.15 V to 3.45 V, with charge pump and VCO

supplies from 4.75 V to 5.25 V. T h e ADF4355 also contains

hardware and software power-down modes.

FUNCTIONAL BLOCK DIAGRAM

12910-001

MUXOUT

OUT

REG

BIAS

REF

CLK

DATA

REG

DDDD

GND

GNDVCO

SET

VCO

TUNE

REF

OUT

A+

OUT

A–

OUT

B+

OUT

B–

VCO

CORE

PHASE

COMPARATOR

CHARGE

PUMP

OUTPUT

STAGE

OUTPUT

STAGE

PDB

MULTIPLEXER

10-BIT R

COUNTER

÷2

DIVIDER

×2

DOUBLER

FUNCTION

LATCH

DATA REGISTER

INTEGER

N COUNTER

FRACTION

THIRD-ORDER

FRACTIONAL

INTERPOLATOR

MODULUS

MULTIPLEXER

LOCK

DETECT

÷1/2/4/8

16/32/64

ADF4355

REF

GNDRF

REGVCO

Figure 1.

Rev. 0 Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support www.analog.com

ADF4355 Data Sheet

Rev. 0 | Page 2 of 35

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Timing Characteristics ................................................................ 5

Absolute Maximum Ratings ............................................................ 6

Transistor Count ........................................................................... 6

ESD Caution .................................................................................. 6

Pin Configuration and Function Descriptions ............................. 7

Typical Performance Characteristics ............................................. 9

Circuit Description ......................................................................... 12

Reference Input Section ............................................................. 12

RF N Divider ............................................................................... 12

Phase Frequency Detector (PFD) and Charge Pump ............ 13

MUXOUT and Lock Detect ...................................................... 13

Input Shift Registers ................................................................... 13

Program Modes .......................................................................... 13

VCO.............................................................................................. 14

Output Stage ................................................................................ 14

Frequency Update Sequence ..................................................... 29

RF Synthesizer—A Worked Example ...................................... 30

Reference Doubler and Reference Divider ............................. 30

Spurious Optimization and Fast Lock ..................................... 30

Optimizing Jitter ......................................................................... 30

Spur Mechanisms ....................................................................... 31

Lock Time .................................................................................... 31

Applications Information .............................................................. 32

Direct Conversion Modulator .................................................. 32

Power Supplies ............................................................................ 33

Printed Circuit Board (PCB) Design Guidelines for a Chip-

Scale Package .............................................................................. 33

Output Matching ........................................................................ 34

Outline Dimensions ....................................................................... 35

Ordering Guide .......................................................................... 35

REVISION HISTORY

4/15—Revision 0: Initial Version

Data Sheet ADF4355

SPECIFICATIONS

AVDD = DVDD = VRF = 3.3 V ± 5%, 4.75 V ≤ VP = VVCO ≤ 5.25 V, A GND = CPGND = AGNDVCO = SDGND = AGNDRF = 0 V, R SET = 5.1 kΩ,

dBm referred to 50 Ω, TA = TMIN to TMAX, unless otherwise noted.

Table 1.

Parameter Symbol Min Typ Max Unit Test Conditions/Comments

REF

A/REF

B CHARACTERISTICS

Input Frequency For f < 10 MHz, ensure slew rate > 21 V/µs

Single-Ended Mode 10 250 MHz

Differential Mode 10 600 MHz

Input Sensitivity

Single-Ended Mode

0.4

V p-p

REF

A biased at AV

/2; ac coupling

ensures AVDD/2 bias

Differential Mode 0.4 1.8 V p-p LVDS and LVPECL compatible,

REFINA/REFINB biased at 2.1 V;

ac coupling ensures 2.1 V bias

Input Capacitance

Single-Ended Mode 6.9 pF

Differential Mode 1.4 pF

Input Current ±60 µA Single-ended reference programmed

±250 µA Differential reference programmed

Phase Detector Frequency 125 MHz

CHARGE PUMP (CP)

Charge Pump Current, Sink/Source ICP RSET = 5.1 kΩ

High Value 4.8 mA

Low Value

0.3

RSET Range 5.1 kΩ Fixed

Current Matching 3 % 0.5 V ≤ VCP1 ≤ VP − 0.5 V

ICP vs. VCP1 3 % 0.5 V ≤ VCP1 ≤ VP − 0.5 V

ICP vs. Temperature 1.5 % VCP1 = 2.5 V

LOGIC INPUTS

Input High Voltage VINH 1.5 V

Input Low Voltage VINL 0.6 V

Input Current IINH/IINL ±1 µA

Input Capacitance

3.0

LOGIC OUTPUTS

Output High Voltage VOH DVDD − 0.4 V

1.5 1.8 V 1.8 V output selected

Output High Current IOH 500 µA

Output Low Voltage VOL 0.4 V IOL2 = 500 µA

POWER SUPPLIES

Analog Power AVDD 3.15 3.45 V

Digital Power and RF Supply Voltage DVDD, VRF AVDD Voltages must equal AVDD

Charge Pump and VCO Voltage VP, VVCO 4.75 5.0 5.25 V VP must equal VVCO

Charge Pump Supply Power Current IP 8 9

Digital Power Supply Current +

Analog Power Supply Curent3

, AI

Output Dividers 6 to 36 mA Each output divide by 2 consumes 6 mA

Supply Current IVCO 70 85 mA

RFOUTA±/RFOUTB± Supply Current

±xRFOUT

16/20/

42/55

20/35/

50/70

mA RF output stage is programmable;

RFOUTB+/RFOUTB− powered off

Low Power Sleep Mode 500 µA Hardware power-down

1000 µA Software power-down

Rev. 0 | Page 3 of 35

ADF4355 Data Sheet

Parameter Symbol Min Typ Max Unit Test Conditions/Comments

RF OUTPUT CHARACTERISTICS

VCO Frequency Range 3400 6800 MHz Fundamental VCO range

RF Output Frequency 53.125 6800 MHz

VCO Sensitivity KV 15 MHz/V

Frequency Pushing (Open-Loop)

MHz/V

Frequency Pulling (Open-Loop) 0.5 MHz Voltage standing wave ratio (VSWR) = 2:1

Harmonic Content

Second −27 dBc Fundamental VCO output (RFOUTA+)

−22 dBc Divided VCO output (RFOUTA+)

Third −20 dBc Fundamental VCO output (RFOUTA+)

−12 dBc Divided VCO output (RFOUTA+)

RF Output Power4 +8 dBm RFOUTA+ = 1 GHz

+3 dBm RFOUTA+/RFOUTA− = 4.4 GHz

RF Output Power Variation ±1 dB RFOUTA+/RFOUTA− = 4.4 GHz

RF Output Power Variation (over

Frequency)

±3 dB RFOUTA+/RFOUTA− = 1 GHz to 4.4 GHz

Level of Signal with RF Output

Disabled

−60 dBm RFOUTA+/RFOUTA− = 1 GHz, VCO = 4 GHz

−30 dBm RFOUTA+/RFOUTA− = 4.4 GHz, VCO = 4.4 GHz

NOISE CHARACTERISTICS

Fundamental VCO Phase Noise

Performance

VCO noise in open-loop conditions

−116 dBc/Hz 100 kHz offset from 3.4 GHz carrier

−136 dBc/Hz 800 kHz offset from 3.4 GHz carrier

−138 dBc/Hz 1 MHz offset from 3.4 GHz carrier

−155 dBc/Hz 10 MHz offset from 3.4 GHz carrier

−113 dBc/Hz 100 kHz offset from 5.0 GHz carrier

−133 dBc/Hz 800 kHz offset from 5.0 GHz carrier

−135 dBc/Hz 1 MHz offset from 5.0 GHz carrier

−153 dBc/Hz 10 MHz offset from 5.0 GHz carrier

−110 dBc/Hz 100 kHz offset from 6.8 GHz carrier

−130 dBc/Hz 800 kHz offset from 6.8 GHz carrier

−132 dBc/Hz 1 MHz offset from 6.8 GHz carrier

−150 dBc/Hz 10 MHz offset from 6.8 GHz carrier

Normalized In-Band Phase Noise Floor

Fractional Channel

−221

dBc/Hz

Integer Channel6 −223 dBc/Hz

Normalized 1/f Noise, PN1_f7 −116 dBc/Hz 10 kHz offset; normalized to 1 GHz

Integrated RMS Jitter 150 fs

Spurious Signals due to Phase

Frequency Detector (PFD) Frequency

−80 dBc

1 VCP is the voltage at the CPOUT pin.

2 IOL is the output low current.

3 TA = 25°C; AVDD = DVDD = VRF = 3.3 V; VVCO = VP = 5.0 V; prescaler = 4/5; fREFIN = 122.88 MHz; fPFD = 61.44 MHz; and fRF = 1650 MHz.

4 RF output power using the EV-ADF4355SD1Z evaluation board measured into a spectrum analyzer, with board and cable losses de-embedded. The EV-ADF4355SD1Z

RF outputs are pulled up externally using a 4.7 nH inductor. Unused RF output pins are terminated in 50 Ω.

5 Use this figure to calculate the phase noise for any application. To calculate in-band phase noise performance as seen at the VCO output, use the following formula:

−221 + 10log(fPFD) + 20logN. The value given is the lowest noise mode for the fractional channel.

6 Use this figure to calculate the phase noise for any application. To calculate in-band phase noise performance as seen at the VCO output, use the following formula:

−223 + 10log(fPFD) + 20logN. The value given is the lowest noise mode for the integer channel.

7 The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency (fRF)

and at a frequency offset (f) is given by PN = P1_f + 10log(10 kHz/f) + 20log(fRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in the

ADIsimPLL design tool.

Rev. 0 | Page 4 of 35

Data Sheet ADF4355

TIMING CHARACTERISTICS

AVDD = DVDD =VRF = 3.3 V ± 5%, 4.75 V ≤ VP = VVCO ≤ 5.25 V, AGND = CPGND = AGNDVCO = SDGND = AGNDRF = 0 V, R SET = 5.1 kΩ,

dBm referred to 50 Ω, TA = TMIN to TMAX, unless otherwise noted.

Table 2. Write Timing

Parameter Limit Unit Description

t1 20 ns min LE setup time

t2 10 ns min DATA to CLK setup time

t3 10 ns min DATA to CLK hold time

t4 25 ns min CLK high duration

t5 25 ns min CLK low duration

t6 10 ns min CLK to LE setup time

t7 20 ns min LE pulse width

Write Timing Diagram

CLK

DATA

DB31 (MSB) DB30 DB1

(CONTROL BIT C2)

DB0 (LSB)

(CONTROL BIT C1)

t2t3

t4t5

DB2

(CONTROL BIT C3)

DB3

(CONTROL BIT C4)

12910-002

Figure 2. Write Timing Diagram

Rev. 0 | Page 5 of 35

ADF4355 Data Sheet

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

VRF, DVDD, AVDD to GND1 −0.3 V to +3.6 V

AVDD to DVDD −0.3 V to +0.3 V

VP, VVCO to GND1 −0.3 V to +5.8 V

VP, VVCO to AVDD −0.3 V to AVDD + 2.5 V

CPOUT to GND1 −0.3 V to VP + 0.3 V

Digital Input/Output Voltage to GND1 −0.3 V to DVDD + 0.3 V

Analog Input/Output Voltage to GND

−0.3 V to AV

+ 0.3 V

REFINA, REFINB to GND1 −0.3 V to AVDD + 0.3 V

REFINA to REFINB ±2.1 V

Operating Temperature Range −40°C to +85°C

Storage Temperature Range −65°C to +125°C

Maximum Junction Temperature 150°C

θJA, Thermal Impedance Pad Soldered

to GND1

27.3°C/W

Reflow Soldering

Peak Temperature 260°C

Time at Peak Temperature 40 sec

Electrostatic Discharge (ESD)

Charged Device Model 1000 V

Human Body Model 2500 V

1 GND = AGND = SDGND = AGNDRF = AGNDVCO = CPGND = 0 V.

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

The ADF4355 is a high performance RF integrated circuit with

an ESD rating of 2500 V and is ESD sensitive. Take proper

precautions for handling and assembly.

TRANSISTOR COUNT

The transistor count for the ADF4355 is 103,665 (CMOS) and

3214 (bipolar).

ESD CAUTION

Rev. 0 | Page 6 of 35

Data Sheet ADF4355

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

12910-003

CLK

DATA

BIAS

REF

REG

REF

GND

OUT

GND

MUXOUT

SET

OUT

A+

OUT

A−

OUT

B+

OUT

B−

TUNE

GNDVCO

PDB

REG

GNDRF

VCO

NOTES

1. THE EXPOSED PAD MUST BE CONNECTED TO A

GND

REGVCO

GND

ADF4355

TOP VIEW

(Not to Scale)

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 CLK Serial Clock Input. Data is clocked into the 32-bit shift register on the CLK rising edge. This input is a high

impedance CMOS input.

2 DATA Serial Data Input. The serial data is loaded most significant bit (MSB) first with the four least significant bits (LSBs)

as the control bits. This input is a high impedance CMOS input.

3 LE Load Enable, CMOS Input. When LE goes high, the data stored in the shift register is loaded into the register that

is selected by the four LSBs.

4 CE Chip Enable. A logic low on this pin powers down the device and puts the charge pump into three-state mode. A

logic high (at levels equal to DVDD) on this pin powers up the device, depending on the status of the power-down bits.

5, 16 AVDD Analog Power Supply. This pin ranges from 3.15 V to 3.45 V. Connect decoupling capacitors to the analog ground

plane as close to this pin as possible. AVDD must have the same value as DVDD.

6 VP Charge Pump Power Supply. VP must have the same value as VVCO. Connect decoupling capacitors to the ground

plane as close to this pin as possible.

7 CPOUT Charge Pump Output. When enabled, this output provides ±ICP to the external loop filter. The output of the loop

filter is connected to VTUNE to drive the internal VCO.

GND

Charge Pump Ground. This output is the ground return pin for CP

OUT

9 AGND Analog Ground. Ground return pin for AVDD.

10 VRF Power Supply for the RF Output. Connect decoupling capacitors to the analog ground plane as close to this pin

as possible. VRF must have the same value as AVDD.

11 RFOUTA+ VCO Output. The output level is programmable. The VCO fundamental output or a divided down version is

available.

12 RFOUTA− Complementary VCO Output. The output level is programmable. The VCO fundamental output or a divided down

version is available.

13 AGNDRF RF Output Stage Ground. Ground return pins for the RF output stage.

14 RFOUTB+ Auxiliary VCO Output. The output level is programmable. The VCO fundamental output or a divided down version

is available.

OUT

B−

Complementary Auxiliary VCO Output. The output level is programmable. The VCO fundamental output or a

divided down version is available.

17 VVCO Power Supply for the VCO. The voltage on this pin ranges from 4.75 V to 5.25 V. Connect decoupling capacitors to

the analog ground plane as close to this pin as possible.

18, 21 AGNDVCO VCO Ground. Ground return path for the VCO.

19 VREGVCO VCO Compensation Node. Connect decoupling capacitors to the ground plane as close to this pin as possible.

Connect this pin directly to VVCO.

20 VTUNE Control Input to the VCO. This voltage determines the output frequency and is derived from filtering the CPOUT

output voltage.

Rev. 0 | Page 7 of 35

ADF4355 Data Sheet

Pin No. Mnemonic Description

22 RSET Bias Current Resistor. Connecting a resistor between this pin and ground sets the charge pump output current.

23 VREF Internal Compensation Node. DC biased at half the tuning range. Connect decoupling capacitors to the ground

plane as close to this pin as possible.

24 VBIAS Reference Voltage. Connect a 100 nF decoupling capacitor to the ground plane as close to this pin as possible.

25, 32 CREG1, CREG2 Outputs from the LDO Regulator. Pin 25 and Pin 32 are the supply voltages to the digital circuits and have a

nominal voltage of 1.8 V. Decoupling capacitors of 100 nF connected to AGND are required for these pins.

26 PDBRF RF Power-Down. A logic low on this pin mutes the RF outputs. This mute function is also software controllable.

27 DVDD Digital Power Supply. This pin must be at the same voltage as AVDD. Place decoupling capacitors to the ground

plane as close to this pin as possible.

28 REFINB Complementary Reference Input. If unused, ac-couple this pin to AGND.

29 REFINA Reference Input.

30 MUXOUT

Multiplexer Output. The multiplexer output allows the digital lock detect, the analog lock detect, scaled RF, or the

scaled reference frequency to be externally accessible.

31 SDGND Digital Σ-Δ Modulator Ground. Pin 31 is the ground return path for the Σ-Δ modulator.

EP Exposed Pad. The exposed pad must be connected to AGND.

Rev. 0 | Page 8 of 35

Data Sheet ADF4355

TYPICAL PERFORMANCE CHARACTERISTICS

–170

–150

–130

–110

–90

–70

–50

1k 10k 100k 1M 10M 100M

FREQUENCY (Hz)

PHASE NOISE (dBc/Hz)

12910-004

Figure 4. Open-Loop VCO Phase Noise, 3.4 GHz

1k 10k 100k 1M 10M 100M

FREQUENCY (Hz)

PHASE NOISE (dBc/Hz)

–170

–150

–130

–110

–90

–70

–50

12910-005

Figure 5. Open-Loop VCO Phase Noise, 5.0 GHz

1k 10k 100k 1M 10M 100M

FREQUENCY (Hz)

PHASE NOISE (dBc/Hz)

–170

–150

–130

–110

–90

–70

–50

12910-006

Figure 6. Open-Loop VCO Phase Noise, 6.8 GHz

1k 10k 100k 1M 10M 100M

FREQUENCY (Hz)

PHASE NOISE (dBc/Hz)

–170

–150

–130

–110

–90

–70

–50

÷1

÷2

÷4

÷8

÷16

÷32

÷64

12910-007

Figure 7. Closed-Loop Phase Noise, RFOUTA+, Fundamental VCO and Dividers,

VCO = 3.4 GHz, PFD = 61.44 MHz, Loop Bandwidth = 20 kHz

1k 10k 100k 1M 10M 100M

FREQUENCY (Hz)

PHASE NOISE (dBc/Hz)

–170

–150

–130

–110

–90

–70

–50

÷1

÷2

÷4

÷8

÷16

÷32

÷64

12910-008

Figure 8. Closed-Loop Phase Noise, RFOUTA+, Fundamental VCO and Dividers,

VCO = 5.0 GHz, PFD = 61.44 MHz, Loop Bandwidth = 20 kHz

1k 10k 100k 1M 10M 100M

FREQUENCY (Hz)

PHASE NOISE (dBc/Hz)

–170

–150

–130

–110

–90

–70

–50

÷1

÷2

÷4

÷8

÷16

÷32

÷64

12910-009

Figure 9. Closed-Loop Phase Noise, RFOUTA+, Fundamental VCO and Dividers,

VCO = 6.8 GHz, PFD = 61.44 MHz, Loop Bandwidth = 20 kHz

Rev. 0 | Page 9 of 35

ADF4355 Data Sheet

1k 10k 100k 1M 10M 100M

FREQUENCY (Hz)

PHASE NOISE (dBc/Hz)

–170

–150

–130

–110

–90

–70

–50

÷1

÷2

12910-010

Figure 10. Closed-Loop Phase Noise, RFOUTA+, Fundamental VCO and

Divide by 2, VCO = 3.4 GHz, PFD = 61.44 MHz, Loop Bandwidth = 2 kHz

1k 10k 100k 1M 10M 100M

FREQUENCY (Hz)

PHASE NOISE (dBc/Hz)

–170

–150

–130

–110

–90

–70

–50

÷1

÷2

12910-011

Figure 11. Closed-Loop Phase Noise, RFOUTA+, Fundamental VCO and

Divide by 2, VCO = 5.0 GHz, PFD = 61.44 MHz, Loop Bandwidth = 2 kHz

1k 10k 100k 1M 10M 100M

FREQUENCY (Hz)

PHASE NOISE (dBc/Hz)

–170

–150

–130

–110

–90

–70

–50

÷1

÷2

12910-012

Figure 12. Closed-Loop Phase Noise, RFOUTA+, Fundamental VCO and

Divide by 2, VCO = 6.8 GHz, PFD = 61.44 MHz, Loop Bandwidth = 2 kHz

–10

–9

–8

–7

–6

–5

–4

–3

–2

–1

1 2 3 4 5 6 7

OUTPUT POWER (dBm)

FREQUENCY (GHz)

12910-016

–40°C

+25°C

+85°C

Figure 13. Output Power vs. Frequency, RFOUTA+/RFOUTA− (7.5 nH Inductors,

10 pF Bypass Capacitors, Board Losses De-Embedded)

–50

–45

–40

–35

–30

–25

–20

–15

–10

–5

1 2 3 4 5 6 7

POWER (dBc)

FREQUENCY (GHz)

12910-017

SECOND HARMONIC

THIRD HARMONIC

Figure 14. RFOUTA+/RFOUTA− Harmonics vs. Frequency (7.5 nH Inductors,

10 pF Bypass Capacitors, Board Losses De-Embedded)

FREQUENCY (GHz)

POWER (dBm)

–10

–8

–6

–4

–2

01 2 3 4 5 6 7

12910-018

Figure 15. RFOUTA+/RFOUTA− Power vs. Frequency (100 nH Inductors, 100 pF

Bypass Capacitors, Board Measurement)

Rev. 0 | Page 10 of 35

Data Sheet ADF4355

0.8 1.8 2.8 3.8 4.8 5.8 6.8

0.05

0.10

0.15

0.20

0.25

0.30

0.35

0.40

0.45

0.50

RMS JITTER (ps)

OUTPUT FREQUENCY (GHz)

RMS JITTER (ps) 1kHz TO 20MHz

RMS JITTER (ps) 12kHz TO 20MHz

12910-021

Figure 16. RMS Jitter vs. Output Frequency, PFD Frequency = 61.44 MHz,

Loop Filter = 20 kHz

–110

–100

–90

–80

–70

–60

–50

PFD SPUR AMPLITUDE (dBc)

OUT

A+/RF

OUT

A– OUTPUT FREQUENCY (GHz)

12910-022

0 1 2 3 4 5 6 7

PFD = 15.36MHz

PFD = 30.72MHz

PFD = 61.44MHz

Figure 17. PFD Spur Amplitude vs. RFOUTA+/RFOUTA− Output Frequency,

PFD = 15.36 MHz, PFD = 30.72 MHz, PFD = 61.44 MHz, Loop Filter = 20 kHz

1k 10k 100k 1M 10M 100M

FREQUENCY (Hz)

NOISE AND SPUR POWER (dBc/Hz)

–160

–150

–140

–130

–120

–110

–100

–90

–80

12910-024

Figure 18. Fractional-N Spur Performance, GSM1800 Band, RFOUTA+ =

1550.2 MHz, REFIN = 122.88 MHz, PFD = 61.44 MHz, Output Divide by 4

Selected, Loop Filter Bandwidth = 20 kHz, Channel Spacing = 20 kHz

1k 10k 100k 1M 10M 100M

FREQUENCY (Hz)

NOISE AND SPUR POWER (dBc/Hz)

–160

–150

–140

–130

–120

–110

–100

–90

–80

12910-025

Figure 19. Fractional-N Spur Performance, W-CDMA Band, RFOUTA+ =

2113.5 MHz, REFIN = 122.88 MHz, PFD = 61.44 MHz, Output Divide by 2

Selected, Loop Filter Bandwidth = 20 kHz, Channel Spacing = 20 kHz

1k 10k 100k 1M 10M 100M

FREQUENCY (Hz)

NOISE AND SPUR POWER (dBc/Hz)

–160

–150

–140

–130

–120

–110

–100

–90

–80

12910-026

Figure 20. Fractional-N Spur Performance, RFOUTA+ = 2.591 GHz,

REFIN = 122.88 MHz, PFD = 61.44 MHz, Output Divide-by-2 Selected,

Loop Filter Bandwidth = 20 kHz, Channel Spacing = 20 kHz

4.65

4.15

–1 01234

4.20

4.25

4.30

4.35

4.40

4.45

4.50

4.55

FREQUENCY (GHz)

TIME (ms)

4.60

12910-128

Figure 21. Lock Time for 250 MHz Jump from 4150 MHz to 4400 MHz,

Loop Bandwidth = 20 kHz

Rev. 0 | Page 11 of 35

ADF4355 Data Sheet

Rev. 0 | Page 12 of 35

CIRCUIT DESCRIPTION

REFERENCE INPUT SECTION

Figure 22 shows the reference input stage. The reference input

can accept both single-ended and differential signals. Use the

reference mode bit (Register 4, DB9) to select the signal. To use a

differential signal on the reference input, program this bit high.

In this case, SW1 and SW2 are open, SW3 and SW4 are closed,

and the current source that drives the differential pair of

transistors switches on. The differential signal buffers and

provides an emitter-coupled logic (ECL) to CMOS converter.

When a single-ended signal is used as the reference, program

Bit DB9 in Register 4 to 0. Connect the single-ended reference

signal to REFINA. In this case, SW1 and SW2 are closed, SW3

and SW4 are open, and the current source that drives the

differential pair of transistors switches off.

When the input reference frequency is below 250 MHz, it is

recommended to operate in single-ended mode for best spur

performance.

2.5k2.5k

REF

BIAS

GENERATOR

BUFFER

85k

SW2

SW3

SW1

REFERENCE

INPUT MODE

SW4

ECL TO CMOS

CONVERTER

R COUNTER

MULTIPLEXER

12910-226

Figure 22. Reference Input Stage

RF N DIVIDER

The RF N divider allows a division ratio in the PLL feedback

path. Determine the division ratio by the INT, FRAC1, FRAC2,

and MOD2 values that this divider comprises.

THIRD-ORDER

FRACTIONAL

INTERPOLATOR

FRAC1INT

RF N COUNTER

FROM

VCO OUTPUT/

OUTPUT DIVIDERS

TO PFD

N COUNTER

FRAC2

VALUE

MOD2

VALUE

N = INT +

FRAC1 +

MOD1

FRAC2

MOD2

12910-027

Figure 23. RF N Divider

INT, FRACx, MODx, and R Counter Relationship

The INT, FRAC1, FRAC2, MOD1, and MOD2 values, in

conjunction with the R counter, make it possible to generate

output frequencies that are spaced by fractions of the PFD

frequency (fPFD). For more information, see the RF Synthesizer—

A Worked Example section.

Calculate the RF VCO frequency (VCOOUT) by

VCOOUT = fPFD × N (1)

where:

VCOOUT is the output frequency of the VCO (without using the

output divider).

fPFD is the frequency of the phase frequency detector.

N is the desired value of the feedback counter, N.

Calculate fPFD by

fPFD = REFIN × [(1 + D)/(R × (1 + T))] (2)

where:

REFIN is the reference input frequency.

D is the REFIN doubler bit.

R is the preset divide ratio of the binary 10-bit programmable

reference counter (1 to 1023).

T is the REFIN divide by 2 bit (0 or 1).

N comprises

MOD1

MOD2

FRAC2

FRAC1

INTN



 (3)

where:

INT is the 16-bit integer value (23 to 32,767 for the 4/5

prescaler, 75 to 65,535 for the 8/9 prescaler).

FRAC1 is the numerator of the primary modulus (0 to 16,777,215).

FRAC2 is the numerator of the 14-bit auxiliary modulus

(0 to 16,383).

MOD2 is the programmable, 14-bit auxiliary fractional

modulus (2 to 16,383).

MOD1 is a 24-bit primary modulus with a fixed value of 224 =

16,777,216.

Equation 3 results in a very fine frequency resolution with no

residual frequency error. To apply this formula, take the

following steps:

1. Calculate N by dividing VCOOUT/fPFD.

2. The integer value of this number forms INT.

3. Subtract the INT value from the full N value.

4. Multiply the remainder by 224.

5. The integer value of this number forms FRAC1.

6. Calculate MOD2 based on the channel spacing (fCHSP) by

MOD2 = fPFD/GCD(fPFD, fCHSP) (4)

where:

GCD(fPFD, fCHSP) is the greatest common divider of the PFD

frequency and the channel spacing frequency.

fCHSP is the desired channel spacing frequency.

7. Calculate FRAC2 by the following equation:

FRAC2 = [(N − INT) × 224 − FRAC1)] × MOD2 (5)

Data Sheet ADF4355

The FRAC2 and MOD2 fraction results in outputs with zero

frequency error for channel spacings when

fPFD/GCD(fPFD/fCHSP) < 16,383 (6)

where:

fPFD is the frequency of the phase frequency detector.

GCD is a greatest common denominator function.

fCHSP is the desired channel spacing frequency.

If zero frequency error is not required, the MOD1 and MOD2

denominators operate together to create a 38-bit resolution

modulus.

INT N Mode

When FRAC1 and FRAC2 = 0, the synthesizer operates in

integer-N mode.

R Counter

The 10-bit R counter allows the input reference frequency

(REFIN) to be divided down to produce the reference clock to

the PFD. Division ratios from 1 to 1023 are allowed.

PHASE FREQUENCY DETECTOR (PFD) AND

CHARGE PUMP

The PFD takes inputs from the R counter and N counter and

produces an output proportional to the phase and frequency

difference between them. Figure 24 is a simplified schematic

of the PFD. The PFD includes a fixed delay element that sets the

width of the antibacklash pulse. This pulse ensures that there is

no dead zone in the PFD transfer function and provides a

consistent reference spur level. Set the phase detector polarity to

positive on this device because of the positive tuning of the VCO.

CLR2

Q2D2

DOWN

HIGH

–IN

+IN

CHARGE

PUMP

DELAY

CLR1

Q1D1

12910-028

Figure 24. PFD Simplified Schematic

MUXOUT AND LOCK DETECT

The output multiplexer on the ADF4355 allows the user to access

various internal points on the chip. The M3, M2, and M1 bits in

MUXOUT section in block diagram form.

GND

CONTROLMUX MUXOUT

ANALOG LOCK DETECT

DIGITAL LOCK DETECT

R DIVIDER OUTPUT

N DIVIDER OUTPUT

GND

RESERVED

THREE-STATE OUTPUT

12910-029

Figure 25. MUXOUT Block Diagram

INPUT SHIFT REGISTERS

The ADF4355 digital section includes a 10-bit R counter, a

16-bit RF integer-N counter, a 24-bit FRAC1 counter, a 14-bit

auxiliary fractional counter, and a 14-bit auxiliary modulus

counter. Data clocks into the 32-bit shift register on each rising

edge of CLK. The data clocks in MSB first. Data transfers from

the shift register to one of 12 latches on the rising edge of LE.

The state of the four control bits (C4, C3, C2, and C1) in the

shift register determines the destination latch. As shown in

Figure 2, the four least significant bits (LSBs) are DB3, DB2,

DB1, and DB0. The truth table for these bits is shown in Table 5.

Figure 28 and Figure 29 summarize the programing of the latches.

Table 5. Truth Table for the C4, C3, C2, and C1 Control Bits

Control Bits

C4 C3 C2 C1

0 0 0 0 Register 0

0 0 0 1 Register 1

0 0 1 1 Register 3

0 1 0 0 Register 4

0 1 0 1 Register 5

0 1 1 0 Register 6

0 1 1 1 Register 7

1 0 0 0 Register 8

1 0 0 1 Register 9

1 0 1 0 Register 10

1 0 1 1 Register 11

1 1 0 0 Register 12

PROGRAM MODES

Table 5 and Figure 28 through Figure 42 show the program

modes that must be set up in the ADF4355.

The following settings in the ADF4355 are double buffered: main

fractional value (FRAC1), auxiliary modulus value (MOD2),

auxiliary fractional value (FRAC2), reference doubler, reference

divide by 2 (RDIV2), R counter value, and charge pump current

setting. Two events must occur before the ADF4355 uses a new

value for any of the double buffered settings. First, the new value

must latch into the device by writing to the appropriate register,

and second, a new write to Register 0 must be performed.

Rev. 0 | Page 13 of 35

ADF4355 Data Sheet

For example, to ensure that the modulus value loads correctly,

every time the modulus value updates, Register 0 must be

written to. The RF divider select in Register 6 is also double

buffered, but only when DB14 of Register 4 is high.

VCO

The VCO core in the ADF4355 consists of four separate VCOs,

each of which uses 256 overlapping bands, which allows covering

a wide frequency range without a large VCO sensitivity (KV) and

without resultant poor phase noise and spurious performance.

The correct VCO and band are chosen automatically by the

VCO and band select logic when Register 0 is updated and auto-

calibration is enabled. The VCO VTUNE is disconnected from

the output of the loop filter and is connected to an internal

reference voltage.

The R counter output is used as the clock for the band select

logic. After band selection, normal PLL action resumes. The

nominal value of KV is 15 MHz/V when the N divider is driven

from the VCO output, or the KV value is divided by D. D is the

output divider value if the N divider is driven from the RF

output divider (chosen by programming Bits[D23:D21] in

The VCO shows variation of KV as the tuning voltage, VTUNE,

varies within the band and from band to band. For wideband

applications covering a wide frequency range (and changing

output dividers), a value of 15 MHz/V provides the most accurate

KV, because this value is closest to the average value. Figure 26

shows how KV varies with fundamental VCO frequency along with

an average value for the frequency band. Users may prefer this

figure when using narrow-band designs.

FREQUENCY (GHz)

3.3 3.8 4.3 4.8 5.3 5.8 6.3 6.8

VCO SENSITIVITY, KV (MHz/V)

AVERAGE

VCO SENSITIVITY

LINEAR

TREND LINE

12910-133

Figure 26. KV vs. Frequency

OUTPUT STAGE

The RFOUTA+ and RFOUTA− pins of the ADF4355 connect to

the collectors of an NPN differential pair driven by buffered

outputs of the VCO, as shown in Figure 27. In this scheme, the

ADF4355 contains internal 50 Ω resistors connected to the VRF pin.

To optimize the power dissipation vs. the output power requirements,

the tail current of the differential pair is programmable using

Bits[D2:D1] in Register 6. Four current levels can be set. These

levels give approximate output power levels of −4 dBm, −1 dBm,

+2 dBm, and +5 dBm, respectively, using a 50 Ω resistor to VRF

and ac coupling into a 50 Ω load. For accurate power levels,

refer to the Typical Performance Characteristics section. With

an output power of 5 dBm, an external shunt inductor is necessary

to provide higher power levels; however, this addition results in

less wideband than the internal bias only. Terminate the unused

complementary output with a similar circuit to the used output.

VCO

RFOUTA+ RFOUTA–

VRF

50Ω 50Ω

BUFFER/

DIVIDE BY

1/2/4/8/

16/32/64

12910-032

Figure 27. Output Stage

Another feature of the ADF4355 is that the supply current to the

output stages can shut down until the ADF4355 achieves lock as

measured by the digital lock detect circuitry. The mute till lock

detect (MTLD) bit (DB11) in Register 6 enables this.

The RFOUTB+/RFOUTB− pins are duplicate outputs that can be

used independently or in addition to the RFOUTA+/RFOUTA− pins.

Rev. 0 | Page 14 of 35

Data Sheet ADF4355

Table 6. Total IDD (RFOUTA± Refers to RFOUTA+/RFOUTA−)

Divide By RFOUTA± Off RFOUTA± = −4 dBm RFOUTA± = −1 dBm RFOUTA± = +2 dBm RFOUTA± = +5 dBm

5 V Supply (IVCO and IP) 78 mA 78 mA 78 mA 78 mA 78 mA

3.3 V Supply (AIDD, DIDD, IRF)

1 79.8 mA 101.3 mA 111.9 mA 122.7 mA 132.8 mA

2 87.8 mA 110.1 mA 120.6 mA 131.9 mA 141.9 mA

4 97.1 mA 119.3 mA 130.1 mA 141.6 mA 152.1 mA

8 104.9 mA 127.1 mA 137.8 mA 149.2 mA 159.7 mA

16 109.8 mA 131.8 mA 142.7 mA 154.1 mA 164.6 mA

32 113.6 mA 135.5 mA 146.5 mA 157.8 mA 168.4 mA

64 115.9 mA 137.8 mA 148.9 mA 160.1 mA 170.8 mA

Rev. 0 | Page 15 of 35

ADF4355 Data Sheet

DBR = DOUBLE BUFFERED REGISTER—BUFFERED BY THE WRITE TO REGISTER 0.

DBB = DOUBLE BUFFERED BITS—BUFFERED BY A WRITE TO REGISTER 0 WHEN BIT DB14 OF REGISTER 4 IS HIGH.

DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

N16 N15 N14 N13 N12 N11N10 N9

RESERVED 16-BIT INTEGER VALUE (INT) CONTROL

BITS

N8 N7 N6 N5 N4 N3 N2 N1 C4(0) C3(0) C2(0)

PRESCALER

PR1

AC1

0000

0C1(0)

DB31

AUTOCAL

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0F24 F23 F22 F21

RESERVED 24-BIT MAIN FRACTIONAL VALUE (FRAC1) CONTROL

BITS

F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 C3(0) C2(0) C1(1)

C4(0)

DBR

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

14-BIT AUXILIARY MODULUS VALUE (MOD2) CONTROL

BITS

M14 M13 M12 M11 M10 M9 M8 M7 M6 M5 M4 M3 M2 M1 C3(0) C2(1) C1(0)

C4(0)

DBR

F11F10 F9 F8 F7 F6 F5 F4 F3 F2 F1

F12F13

F14

14-BIT AUXILIARY FRACTIONAL VALUE (FRAC2) DBR

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

PA1 P24 P23 P22 P21

24-BIT PHASE VALUE (PHASE) CONTROL

BITS

P20 P19 P18 P17 P16 P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 C3(0) C2(1) C1(1)

C4(0)PR1SD10

DBR

PHASE

ADJUST

PHASE

RESYNC

SD LOAD

RESET

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

10-BIT R COUNTER

CONTROL

BITS

D1 CP4 CP3 CP2 CP1 U6 U5 U4 U3 U2 U1 C3(1) C2(0) C1(0)

C4(0)

DBR

MUXOUTRESERVED

CURRENT

SETTING

MUX LOGIC

POLARIT Y

POWER-DOWN

CP THREE-

STATE

COUNTER

RESET

REF MODE

DOUBLE BUFF

RDIV2

REFERENCE

DOUBLER

DBR

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1

0000000 0 C4(0) C3(1) C2(0)

CONTROL

BITS

0 0

RESERVED

DB0

C1(1)

000 010000000000001

12910-034

0 0 M3 M2 M1 RD2RD1R10 R9 R8 R7 R6 R5 R4 R3 R2 R1

RF DIVIDER

SELECT

OUTPUT

POWER

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 1 0 1 0 D13 D12 D11 D10 BL1 1 D8 1 D6 D5 D4 D3 D2 D1 C4(0) C3(1) C2(1)

CONTROL

BITS

CHARGE PUMP BLEED CURRENT

RF OUTPUT

ENABLE

AUX RF

OUTPUT

POWER

AUX RF OUTPUT

ENABLE

MTLD

FEEDBACK

SELECT

RESERVED

C1(0)

RESERVED

BL2

BL3

BL4

BL5

BL6

BL7

BL8

NEGATIVE

BLEED

BL9

RESERVED

BL10

GATED

BLEED

RESERVED

Figure 28. Register Summary (Register 0 to Register 6)

Rev. 0 | Page 16 of 35

Data Sheet ADF4355

DB31DB30DB29DB28DB27DB26DB25DB24DB23DB22DB21DB20DB19DB18DB17DB16DB15DB14DB13DB12DB11DB10DB9DB8DB7DB6DB5DB4DB3DB2DB1DB0

0 0 LE 0 0 0 0 0 0 0 0 0 0LD1 C3(1) C2(1) C1(1)

CONTROL

BITS

RESERVED

C4(0)

LD2LD3

FRAC-N LD

PRECISION

LDO MODE

LOL MODE

LOL

LD4

LD5

CYCLE

COUNT

00000010

RESERVED

LE SYNC

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

10 0 0 0

RESERVED

CONTROL

BITS

0 1 0 1 1 0 1 0 0 0 1 0 0 0 1 0 C3(0) C2(0) C1(0)

C4(1)

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

VC5 VC4 VC3 VC2 VC1

TIMEOUT

CONTROL

BITS

TL10 TL9 TL8 TL7 TL6 TL5 TL4 TL3 TL2 TL1 AL5 AL4 AL3 AL2 AL1 SL5 SL4 SL3 SL2 SL1 C3(0) C2(0) C1(1)C4(1)VC6VC7VC8

VCO BAND DIVISION

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0 0

RESERVED

CONTROL

BITS

1 1 0 0 0 0 0 0 0 0 C3(0) C2(1) C1(0)C4(1)000 AE1AE2AD1AD2AD3AD4AD5AD6

ADC ENABLE

ADC

CONVERSION

AD7AD8

ADC

CLOCK DIVIDER

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

000 0 0

RESERVED

CONTROL

BITS

0 1 1 0 0 0 0 1 0 0 11 0 0 0 0 0 0 0 0 C3(0) C2(1) C1(1)

C4(1)

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

P13 P12 P11 P10 P9

RESYNC CLOCK

CONTROL

BITS

P8 P7 P6 P5 P4 P3 P2 P1 0 0 00 0 1 0 0 0 0 0 1 C3(1) C2(0) C1(0)

C4(1)

P14

P15

P16

RESERVED

12910-035

SYNTHESIZER

LOCK TIMEOUTAUTOMATIC LEVEL TIMEOUT

Figure 29. Register Summary (Register 7 to Register 12)

Rev. 0 | Page 17 of 35

ADF4355 Data Sheet

Rev. 0 | Page 18 of 35

N16N15...N5N4N3N2N1 INTEGERVALUE (INT)

00...00000 NOTALLOWED

00...00001 NOTALLOWED

00...00010 NOTALLOWED

.......... ...

00...10110 NOTALLOWED

00...10111 23

00...11000 24

.......... ...

1 1 ... 1 1 1 0 1 65533

1 1 ... 1 1 1 1 0 65534

1 1 ... 1 1 1 1 1 65535

DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

N16 N15 N14 N13 N12 N11 N10 N9

RESERVED 16-BIT INTEGER VALUE (INT) CONTROL

BITS

N8 N7 N6 N5 N4 N3 N2 N1 C4(0) C3(0) C2(0)

INTMIN = 75 WITH PRESCALER = 8/9

PR1 PRESCALER

04/5

18/9

PRESCALER

PR1

AC1

0000000000 C1(0)

DB31

AUTOCAL

AC1 VCO

AUTOCAL

0DISABLED

1ENABLED

12910-036

Figure 30. Register 0

Control Bits

With Bits[C4:C1] set to 0000, Register 0 is programmed. Figure 30

shows the input data format for programming this register.

Reserved

Bits[DB31:DB22] are reserved and must be set to 0.

Automatic Calibration (Autocal)

Write to Register 0 to enact (by default) the VCO automatic

calibration, and to choose the appropriate VCO and VCO

subband. Write 1 to the AC1 bit (Bit DB21) to enable the

automatic calibration, which is the recommended mode of

operation.

Set the AC1 bit to 0 to disable the automatic calibration, which

leaves the ADF4355 in the same band it is already in when

Disable the automatic calibration only for fixed frequency

applications, phase adjust applications, or very small (<10 kHz)

frequency jumps. Toggling automatic calibration (autocal) is

also required when changing frequency (see the Frequency

Update Sequence section for additional details).

Prescaler

The dual modulus prescaler (P/P + 1), along with the INT,

FRACx, and MODx counters, determines the overall division

ratio from the VCO output to the PFD input. The PR1 bit

(Bit DB20) in Register 0 sets the prescaler value.

Operating at CML levels, the prescaler takes the clock from the

VCO output and divides it down for the counters. It is based on

a synchronous 4/5 core. When the prescaler is set to 4/5, the

maximum RF frequency allowed is 7 GHz. The prescaler limits

the INT value; therefore, if P is 4/5, NMIN is 23, and if P is 8/9,

NMIN is 75.

16-Bit Integer Value

The 16 INT bits (Bits[DB19:DB4]) set the INT value, which

determines the integer part of the feedback division factor. The

INT value is used in Equation 3 (see the INT, FRACx, MODx,

and R Counter Relationship section). All integer values from 23

to 32,767 are allowed for the 4/5 prescaler. For the 8/9 prescaler,

the minimum integer value is 75, and the maximum value is

65,535.

Data Sheet ADF4355

Rev. 0 | Page 19 of 35

F24 F23 .......... F2 F1 MAIN FRACTIONA L VALUE (FRAC1)

0 0 .......... 0 0 0

0 0 .......... 0 1 1

0 0 .......... 1 0 2

0 0 .......... 1 1 3

. . .......... . . .

1 1 .......... 0 0 16777212

1 1 .......... 0 1 16777213

1 1 .......... 1 0 16777214

1 1 ......... 1 1 16777215

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0F24 F23 F22 F21

RESERVED 24-BIT MAIN FRACTIONAL VALUE (FRAC1) CONTROL

BITS

F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 C3(0) C2(0) C1(1)

C4(0)

DBR

12910-037

DBR = DOUBLE BUFFERED REGISTER—BUFFERED BY THE WRITE TO REGISTER 0.

Figure 31. Register 1

Control Bits

With Bits[C4:C1] set to 0001, Register 1 is programmed. Figure 31

shows the input data format for programming this register.

Reserved

Bits[DB31:DB28] are reserved and must be set to 0.

24-Bit Main Fractional Value

The 24 FRAC1 bits (Bits[DB27:DB4]) set the numerator of the

fraction that is input to the Σ-Δ modulator. This fraction, along

with the INT value, specifies the new frequency channel that

the synthesizer locks to, as shown in the RF Synthesizer—A

Worked Example section. FRAC1 values from 0 to (MOD1 − 1)

cover channels over a frequency range equal to the PFD

reference frequency.

ADF4355 Data Sheet

Rev. 0 | Page 20 of 35

M14 M13 .......... M2 M1 MODULUS VALUE (MOD2)

0 0 .......... 0 0 NOT ALLOWED

0 0 .......... 0 1 NOT ALLOWED

0 0 .......... 1 0 2

0 0 .......... 1 1 3

. . .......... . . .

1 1 .......... 0 0 16380

1 1 .......... 0 1 16381

1 1 .......... 1 0 16382

1 1 ......... 1 1 16383

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

14-BIT AUXILIARY MODULUS VALUE (MOD2) CONTROL

BITS

M14M13M12M11M10M9M8M7M6M5M4M3M2M1 C3(0) C2(1) C1(0)

C4(0)

DBR

F14 F13 .......... F2 F1 FRAC2 WORD

0 0 .......... 0 0 0

0 0 .......... 0 1 1

0 0 .......... 1 0 2

0 0 .......... 1 1 3

. . .......... . . .

1 1 .......... 0 0 16381

1 1 .......... 0 1 16382

1 1 .......... 1 0 16382

1 1 ......... 1 1 16383

F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1F12F13F14

14-BIT AUXILIARY FRACTIONAL VALUE (FRAC2)

12910-038

DBR = DOUBLE BUFFERED REGISTER—BUFFERED BY THE WRITE TO REGISTER 0.

Figure 32. Register 2

Control Bits

With Bits[C4:C1] set to 0010, Register 2 is programmed. Figure 32

shows the input data format for programming this register.

14-Bit Auxiliary Fractional Value (FRAC2)

The 14-bit auxiliary fractional value (Bits[DB31:DB18]) controls

the auxiliary fractional word. FRAC2 must be less than the

MOD2 value programmed in Register 2.

14-Bit Auxiliary Modulus Value (MOD2)

The 14-bit auxiliary modulus value (Bits[DB17:DB4]) sets the

auxiliary fractional modulus. Use MOD2 to correct any residual

error due to the main fractional modulus.

Data Sheet ADF4355

Rev. 0 | Page 21 of 35

P24 P23 .......... P2 P1 PHASE VALUE (PHASE)

0 0 .......... 0 0 0

0 0 .......... 0 1 1

0 0 .......... 1 0 2

0 0 .......... 1 1 3

. . .......... . . .

1 1 .......... 0 0 16777212

1 1 .......... 0 1 16777213

1 1 .......... 1 0 16777214

1 1 ......... 1 1 16777215

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

PA1 P24 P23 P22 P21

24-BIT PHASE VALUE (PHASE) CONTROL

BITS

P20 P19 P18 P17 P16 P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 C3(0) C2(1) C1(1)

C4(0)PR1SD10

DBR

PHASE

ADJUST

PHASE

RESYNC

SD LOAD

RESET

RESERVED

PA1 PHASE

ADJUST

0DISABLED

1 ENABLED

PR1 PHASE

RESYNC

0DISABLED

1 ENABLED

SD1 SD LOAD

RESET

0 ON REGISTER0 UPDATE

1DISABLED

12910-039

1DBR = DOUBLE BUFFERED REGISTER—BUFFERED BY THE WRITE TO REGISTER 0.

Figure 33. Register 3

Control Bits

With Bits[C4:C1] set to 0011, Register 3 is programmed. Figure 33

shows the input data format for programming this register.

Reserved

Bit DB31 is reserved and must be set to 0.

SD Load Reset

When writing to Register 0, the Σ-Δ modulator resets. For

applications in which the phase is continually adjusted, this may

not be desirable; therefore, in these cases, the Σ-Δ reset can be

disabled by writing a 1 to the SD1 bit (Bit DB30).

Phase Resync

To use the phase resynchronization feature, the PR1 bit (Bit DB29)

must be set to 1. If unused, the bit can be programmed to 0. The

phase resync timer must also be used in Register 12 to ensure that

the resynchronization feature is applied after the PLL has settled

to the final frequency. If the PLL has not settled to the final frequency,

phase resync may not function correctly. Resynchronization is

useful in phased array and beam forming applications. It ensures

repeatability of output phase when programming the same

frequency. In phase critical applications that use frequencies

requiring the output divider (<3400 MHz), it is necessary to

feed the N divider with the divided VCO frequency as distinct

from the fundamental VCO frequency. This is achieved by

programming the D13 bit (Bit DB24) in Register 6 to 0, which

ensures divided feedback to the N divider.

For resync applications, enable the SD load reset in Register 3

by setting DB30 to 0.

Phase Adjust

To adjust the relative output phase of the ADF4355 on each

differs from the resynchronization feature in that it is useful

when adjustments to phase are made continually in an

application. For this function, disable the VCO automatic

calibration by setting the AC1 bit (Bit DB21) in Register 0 to 1,

and disable the SD load reset by setting the SD1 bit (Bit DB30)

in Register 3 to 1. Note that phase resync and phase adjust

cannot be used simultaneously.

24-Bit Phase Value

The phase of the RF output frequency can adjust in 24-bit steps;

from 0° (0) to 360° (224 − 1). For phase adjust applications, the

phase is set by

(Phase Value/16,777,216) × 360°

When the phase value is programmed to Register 3, each

subsequent adjustment of Register 0 increments the phase by

the value in this equation.

ADF4355 Data Sheet

Rev. 0 | Page 22 of 35

RD2 REFERENCE

DOUBLER

0DISABLED

1ENABLED

RD1 REFERENCE DIVIDE BY 2

0DISABLED

1ENABLED

CP4CP3CP2CP1

ICP (mA)

5.1kΩ

00000.31

00010.63

00100.94

00111.25

01001.56

01011.88

01102.19

01112.50

10002.81

10013.13

10103.44

10113.75

11004.06

11014.38

11104.69

11115.00

R10 R9 ..........

..........

R2 R1 R DIVIDER (R)

00 011

00 102

.. ...

1 1 0 0 1020

1 1 0 1 1021

1 1 1 0 1022

1 1 1 1 1023

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1

00 M3 M2 M1 RD2 RD1 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 D1 CP4 CP3 CP2 CP1 U6 U5 U4 U3 U2 U1 C3(1) C2(0) C1(0)

RDIV2

REFERENCE

DOUBLER

CURRENT

SETTING

10-BIT R COUNTER

CONTROL

BITS

MUX LOGIC

POLARITY

POWER-DOWN

CP THREE-

STATE

COUNTER

RESET

REF MODE

MUXOUT

DOUBLE BUFF

U5 LDP

01.8V

13.3V

U4 PD POLARITY

0NEGATIVE

1POSITIVE

U3 POWER DOWN

0DISABLED

1ENABLED

U2 CP

THREE-STATE

0DISABLED

1ENABLED

U1 COUNTER

RESET

0DISABLED

1ENABLED

D1 DOUBLE BUFFERED

0DISABLED

1ENABLED

U6 REFIN

0SINGLE

1DIFF

M3 M2 M1 OUTPUT

0 0 0 THREE-STATE OUTPUT

00 1DV

01 0SD

GND

0 1 1 R DIVIDER OUTPUT

1 0 0 N DIVIDER OUTPUT

1 0 1 ANALOG LOCK DETECT

1 1 0 DIGITAL LOCK DETECT

11 1RESERVED

DB0

C4(0)

RESERVED

DBR

12910-040

1DBR = DOUBLE BUFFERED REGISTER—BUFFERED BY THE WRITE TO REGISTER 0.

Figure 34. Register 4

Control Bits

With Bits[C4:C1] set to 0100, Register 4 is programmed. Figure 34

shows the input data format for programming this register.

Reserved

Bits[DB31:DB30] are reserved and must be set to 0.

MUXOUT

The on-chip multiplexer (MUXOUT) is controlled by

Bits[DB29:DB27]. For additional details, see Figure 34.

Reference Doubler

Setting the RD2 bit (Bit DB26) to 0 feeds the REFIN signal directly

to the 10-bit R counter, disabling the doubler. Setting this bit to

1 multiplies the reference frequency by a factor of 2 before

feeding it into the 10-bit R counter. When the doubler is

disabled, the REFIN falling edge is the active edge at the PFD

input to the fractional synthesizer. When the doubler is enabled,

both the rising and falling edges of the reference frequency

become active edges at the PFD input.

The maximum allowable reference frequency when the doubler

is enabled is 60 MHz.

RDIV2

Setting the RD1 bit (Bit DB25) to 1 inserts a divide by 2 toggle

flip-flop between the R counter and PFD, which extends the

maximum reference frequency input rate. This function

provides a 50% duty cycle signal at the PFD input.

10-Bit R Counter

The 10-bit R counter divides the input reference frequency

(REFIN) to produce the reference clock to the PFD. Division

ratios range from 1 to 1023.

Double Buffer

The D1 bit (Bit DB14) enables or disables double buffering of

the RF divider select bits (Bits[DB23:DB21]) in Register 6. The

Program Modes section explains how double buffering works.

Charge Pump Current Setting

The CP4 to CP1 bits (Bits[DB13:DB10]) set the charge pump

current. Set this value to the charge pump current that the loop

filter is designed with (see Figure 34). For the lowest spurs, the

0.9 mA setting is recommended.

Data Sheet ADF4355

Reference Mode

The ADF4355 permits use of either differential or single-ended

reference sources.

For optimum integer boundary spur performance, use the

single-ended setting for all references up to 250 MHz (even if

using a differential reference signal). Use the differential setting for

reference frequencies above 250 MHz.

Level Select

To assist with logic compatibility, MUXOUT is programmable to

two logic levels. Set theU5 bit (Bit DB8) to 0 to select 1.8 V

logic, and set it to 1 to select 3.3 V logic.

Phase Detector (PD) Polarity

The U4 bit (Bit DB7) sets the phase detector polarity. When a

passive loop filter or a noninverting active loop filter is used,

set DB7 to 1 (positive). If an active filter with an inverting

characteristic is used, set this bit to 0 (negative).

Power-Down

The U3 bit (Bit DB6) sets the programmable power-down mode.

Setting DB6 to 1 performs a power-down. Setting DB6 to 0

returns the synthesizer to normal operation. In software power-

down mode, the ADF4355 retains all information in its registers.

The register contents are only lost if the supply voltages are

removed.

When power-down activates, the following events occur:

• The synthesizer counters are forced to their load state

conditions.

• The VCO powers down.

• The charge pump is forced into three-state mode.

• The digital lock detect circuitry resets.

• The RFOUTA+/RFOUTA− and RFOUTB+/RFOUTB− output

stages are disabled.

• The input registers remain active and capable of loading

and latching data.

Charge Pump Three-State

Setting the U2 bit (Bit DB5) to 1 puts the charge pump into

three-state mode. Set DB5 to 0 for normal operation.

Counter Reset

The U1 bit (Bit DB4) resets the R counter, N counter, and VCO

band select of the ADF4355. When DB4 is set to 1, the RF

synthesizer N counter and R counter, and the VCO band select,

are reset. For normal operation, set DB4 to 0. Toggling counter

reset (Bit DB4) is also required when changing frequency (see

the Frequency Update Sequence section for additional details).

The bits in Register 5 are reserved and must be programmed as

described in Figure 35, using a hexadecimal word of 0x00800025.

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1

00000 0 0 0 C4(0) C3(1) C2(0)

CONTROL

BITS

0 0

RESERVED

DB0

C1(1)

0010

000

12910-041

Figure 35. Register 5 (0x00800025)

Rev. 0 | Page 23 of 35

ADF4355 Data Sheet

Rev. 0 | Page 24 of 35

12910-042

BITS[DB23:DB21] ARE BUFFERED BY A WRITE TO REGISTER 0 WHEN THE DOUBLE BUFFER BIT IS ENABLED, BIT DB14 OF REGISTER 4.

D3 RF OUT

0DISABLED

1 ENABLED

D2 D1 OUTPUT POWER

0 0 –4dBm

0 1 –1dBm

10+2dBm

11+5dBm

D5 D4 AUXILIARY OUTPUT POWER

0 0 –4dBm

0 1 –1dBm

10+2dBm

11+5dBm

D6 AUXILIARY OUT

0DISABLED

1 ENABLED

D8 MUTE TILL

LOCK DETECT

0 MUTE DISABLED

1 MUTE ENABLED

D13 FEEDBACK

SELECT

FUNDAMEN TAL

DIVIDED

D12 D11 RF DIVIDER SELECT

00 ÷1

00 ÷2

01 ÷4

01 ÷8

D10

÷16

÷32

÷64

BL8 BL7 ..........

..........

BL2 BL1 BLEED CURRENT

0 0 0 1 1 (3.75µA)

0 0 1 0 2 (7.5µA)

.. ...

1 1 0 0 252 (945µA)

1 1 0 1 253 (948.75µA)

1 1 1 0 254 (952.5µA)

1 1 1 1 255 (956.25µA)

BL9 BLEED CURRENT

ENABLED

DISABLED

BL10 GATED BLEED

ENABLED

DISABLED

RF DIVIDER

SELECT

OUTPUT

POWER

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 1 0 1 0 D13 D12 D11 D10 BL1 1 D8 0 D6 D5 D4 D3 D2 D1 C4(0) C3(1) C2(1)

CONTROL

BITS

CHARGE PUMP BLEED CURRENT

RF OUTPUT

ENABLE

AUX RF

OUTPUT

POWER

AUX RF OUTPUT

ENABLE

MTLD

FEEDBACK

SELECT

RESERVED

C1(0)

RESERVED

BL2

BL3

BL4

BL5

BL6

BL7

BL8

NEGATIVE

BLEED

BL9

RESERVED

BL10

GATED

BLEED

RESERVED

Figure 36. Register 6

Control Bits

With Bits[C4:C1] set to 0110, Register 6 is programmed. Figure 36

shows the input data format for programming this register.

Reserved

Bit DB31 is reserved and must be set to 0.

Gated Bleed

Bleed currents can be used for improving phase noise and

spurs; however, due to a potential impact on lock time, the

gated bleed bit, BL10 (Bit DB30), if set to 1, ensures bleed

currents are not switched on until the digital lock detect asserts

logic high. Note that this function requires digital lock detect to

be enabled.

Negative Bleed

Use of constant negative bleed is recommended for most

applications because it improves the linearity of the charge

pump leading to lower noise and spurs than leaving negative

bleed off. To enable negative bleed, write 1 to BL9 (Bit DB29),

and to disable negative bleed, write 0 to BL9 (Bit DB29).

Reserved

Bits[DB28:DB25] are reserved and must be set to 1010.

Feedback Select

D13 (Bit DB24) selects the feedback from the output of the

VCO to the N counter. When D13 is set to 1, the signal is taken

directly from the VCO. When this bit is set to 0, the signal is

taken from the output of the output dividers. The dividers

enable coverage of the wide frequency band (54 MHz to

6800 MHz). When the divider is enabled and the feedback

signal is taken from the output, the RF output signals of two

separately configured PLLs are in phase. Divided feedback is

useful in some applications where the positive interference of

signals is required to increase the power.

RF Divider Select

D12 to D10 (Bits[DB23:DB21]) select the value of the RF output

divider (see Figure 36).

Data Sheet ADF4355

Charge Pump Bleed Current

BL8 to BL1 (Bits[DB20:DB13]) control the level of the bleed

current added to the charge pump output. This current

optimizes the phase noise and spurious levels from the device.

Tests have shown that the optimal bleed set is the following:

4/N < IBLEED/ICP < 10/N

where:

IBLEED is the value of constant negative bleed applied to the

charge pump, which is set by the contents of Bits[BL8:BL1].

ICP is the value of charge pump current setting, Bits[DB13:DB10] of

N is the value of the feedback counter from the VCO to the PFD.

Reserved

Bit DB12 is reserved and must be set to 0.

Mute Till Lock Detect

When D8 (Bit DB11) is set to 1, the supply current to the RF

output stage is shut down until the device achieves lock, as

determined by the digital lock detect circuitry.

Reserved

Bit DB10 is reserved and must be set to 1.

Auxiliary RF Output Enable

Bit DB9 enables or disables the auxiliary frequency RF output

(RFOUTB+/RFOUTB−). When DB9 is set to 1, the auxiliary

frequency RF output is enabled. When DB9 is set to 0, the

auxiliary RF output is disabled.

Auxiliary RF Output Power

Bits[DB8:DB7] set the value of the auxiliary RF output power

level (see Figure 36).

RF Output Enable

Bit DB6 enables or disables the primary RF output (RFOUTA+/

RFOUTA−). When DB6 is set to 0, the primary RF output is

disabled. When DB6 is set to 1, the primary RF output is

enabled.

Output Power

Bits[DB5:DB4] set the value of the primary RF output power

level (see Figure 36).

Rev. 0 | Page 25 of 35

ADF4355 Data Sheet

Rev. 0 | Page 26 of 35

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0LE0 0 0000000 0 LD1 C3(1) C2(1) C1(1)

CONTROL

BITS

RESERVED

LD3 LD2 FRACTIONAL-N LD PRECISION

005.0ns

016.0ns

108.0ns

1112.0ns

LD1

0FRACTIONAL-N

1INTEGER-N (2.9ns)

C4(0)

LOCK DETECT MODE

LD2LD3

FRAC-N LD

PRECISION

LD MODE

LOL

0DISABLED

1 ENABLED

LOSS OF LOCK MODE

LOL MODE

LOL

LD5 LD4 LOCK DETECT CYCLE COUNT

0 0 1024

0 1 2048

1 0 4096

1 1 8192

LD4

LD5

CYCLE

COUNT

000000100

0DISABLED

1 LE SYNCED TO REFIN

LE SYNCHRONIZ ATION

RESERVED

LE SYNC

12910-043

Figure 37. Register 7

Control Bits

With Bits[C4:C1] set to 0111, Register 7 is programmed. Figure 37

shows the input data format for programming this register.

Reserved

Bits[DB31:DB29] are reserved and must be set to 0. Bit DB28 is

reserved and must be set to 1. Bits[DB27:DB26] are reserved

and must be set to 0.

LE Sync

When set to 1, Bit DB25 ensures that the load enable (LE) edge

is synchronized internally with the rising edge of reference

input frequency. This synchronization prevents the rare event of

reference and RF dividers loading at the same time as a falling

edge of reference frequency, which can lead to longer lock times.

Reserved

Bits[DB24:DB10] are reserved and must be set to 0.

Fractional-N Lock Detect Count (LDC)

LD5 and LD4 (Bits[DB9:DB8]) set the number of consecutive

cycles counted by the lock detect circuitry before asserting lock

detect high. See Figure 37 for details.

Loss of Lock Mode

Set LOL (Bit DB7) to 1 when the application is a fixed frequency

application in which the reference (REFIN) is likely to be removed,

such as a clocking application. The standard lock detect circuit

assumes that REFIN is always present; however, this may not be

the case with clocking applications. To enable this functionality,

set DB7 to 1.

Fractional-N Lock Detect Precision (LDP)

LD3 and LD2 (Bits[DB6:DB5]) set the precision of the lock detect

circuitry in fractional-N mode. LDP is available at 5.0 ns, 6.0 ns,

8.0 ns, or 12.0 ns. If bleed currents are used, use 12 ns.

Lock Detect Mode (LDM)

If LD1 (Bit DB4) is set to 0, each reference cycle is set by

fractional-N lock detect precision as described in the

Fractional-N Lock Detect Count (LDC) section. If DB4 is

set to 1, each reference cycle is 2.9 ns long, which is more

appropriate for integer-N applications.

Data Sheet ADF4355

Rev. 0 | Page 27 of 35

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

10 0 00

RESERVED

CONTROL

BITS

01 011010 00 1000 10 C3(0) C2(0) C1(0)

C4(1)

12910-044

Figure 38. Register 8 (0x102D0428)

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

VC5 VC4 VC3 VC2 VC1

TIMEOUT

CONTROL

BITS

TL10 TL9 TL8 TL7 TL6 TL5 TL4 TL3 TL2 TL1 AL5 AL4 AL3 AL2 AL1 SL5 SL4 SL3 SL2 SL1 C3(0) C2(0) C1(1)

C4(1)VC6VC7VC8

TL10 TL9 ..........

..........

TL2 TL1 TIMEOUT

00 011

00 102

.. ...

1 1 0 0 1020

1 1 0 1 1021

1 1 1 0 1022

1 1 1 1 1023

AL5 AL4 ..........

..........

AL2 AL1 ALC WAIT

00 011

00 102

.. ...

11 0028

11 0129

11 1030

11 1131

VC8 VC7 ..........

..........

VC2 VC1 VCO BAND DIV

00 011

00 102

.. ...

11 00252

11 01253

11 10254

11 11255

VCO BAND DIVISION

SL5 SL4 ..........

..........

SL2 SL1 SLC WAIT

00 011

00 102

.. ...

11 0028

11 0129

11 1030

11 1131

12910-045

SYNTHESIZER

LOCK TIMEOUTAUTOMATIC LEVEL TIMEOUT

Figure 39. Register 9

The bits in this register are reserved and must be programmed

as described in Figure 38, using a hexadecimal word of

0x102D0428.

Control Bits

With Bits[C4:C1] set to 1001, Register 9 is programmed. Figure 39

shows the input data format for programming this register.

VCO Band Division

VC8 to VC1 (Bits[DB31:DB24]) set the value of the VCO band

division clock. Determine the value of this clock by PFD/(band

division × 16) such that the result is <150 kHz.

Timeout

TL10 to TL1 (Bits[DB23:DB14]) set the timeout value for the

VCO band select. Use this value as a variable in the other VCO

calibration settings.

Automatic Level Calibration Timeout

AL5 to AL1 (Bits[DB13:DB9]) set the timer value used for the

automatic level calibration of the VCO. This function combines

the PFD frequency, the timeout variable, and ALC wait variable.

Choose ALC such that the following equation is always greater

than 50 μs.

(Timeout × ALC Wait/PFD Frequency) > 50 μs

Synthesizer Lock Timeout

SL5 to SL1 (Bits[DB8:DB4]) set the synthesizer lock timeout

value. Use this value to allow the VTUNE force to settle on the

VTUNE pin. The value must be 20 μs. Calculate the value using

the following equation:

(Timeout × Synthesizer Lock Timeout/PFD Frequency) > 20 μs

ADF4355 Data Sheet

Rev. 0 | Page 28 of 35

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

00 0 00

RESERVED

CONTROL

BITS

110 0000000 C3(0) C2(1) C1(0)

C4(1)000 AE1AE2AD1AD2AD3AD4AD5AD6

ADC ENABLE

ADC

CONVERSION

AD7AD8

ADC

CLOCK DIVIDER

AD8 AD7 ..........

..........

AD2 AD1 ADC CLK DIV

00 011

00 102

.. ...

11 00252

11 01253

11 10254

11 11255

AE1 ADC

0DISABLED

1 ENABLED

AE2 ADC CONVERSION

0 DISABLED

1 ENABLED

12910-047

Figure 40. Register 10

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

00000

RESERVED

CONTROL

BITS

011 0000100110 0000000 C3(0) C2(1) C1(1)

C4(1)

12910-048

Figure 41. Register 11 (0x0061300B)

Control Bits

With Bits[C4:C1] set to 1010, Register 10 is programmed.

Figure 40 shows the input data format for programming this

Reserved

Bits[DB31:DB14] are reserved. Bits[DB23:DB22] must be set to

11, but all other bits in this range must be set to 0.

ADC Clock Divider (ADC_CLK_DIV)

An on-board analog-to-digital converter (ADC) determines the

VTUNE setpoint relative to the ambient temperature of the

ADF4355 environment. The ADC ensures that the initial tuning

voltage in any application is chosen correctly to avoid any

temperature drift issues.

The ADC uses a clock that is equal to the output of the R

counter (or the PFD frequency) divided by ADC_CLK_DIV.

AD8 to AD1 (Bits[DB13:DB6]) set the value of this divider. On

power-up, the R counter is not programmed; however, in these

power-up cases, it defaults to R = 1.

Choose ADC_CLK_DIV such that

PFD/((ADC_CLK_DIV × 4) + 2) < 100 kHz

ADC Conversion Enable

AE2 (Bit DB5) ensures that the ADC performs a conversion

when a write to Register 10 is performed. It is recommended to

enable this mode.

ADC Enable

AE1 (Bit DB4), when set to 1, powers up the ADC for the

temperature dependent VTUNE calibration. It is recommended to

always use this function.

The bits in this register are reserved and must be programmed

as described in Figure 41, using a hexadecimal word of

0x0061300B.

Data Sheet ADF4355

Rev. 0 | Page 29 of 35

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

P13 P12 P11 P10 P9

RESYNC CLOCK

CONTROL

BITS

P8 P7 P6 P5 P4 P3 P2 P1 0 0 0001000001 C3(1) C2(0) C1(0)

C4(1)

P14

P15

P16

P16P15...P5P4P3P2P1 RESYNC CLOCK

00...00000 NOTALLOWED

00...00001 1

00...00010 2

.......... ...

00...10110 22

00...10111 23

00...11000 24

.......... ...

11...11101 65533

11...11110 65534

11...11111 65535

RESERVED

12910-049

Figure 42. Register 12

Control Bits

With Bits[C4:C1] set to 1100, Register 12 is programmed.

Figure 42 shows the input data format for programming this

Phase Resync Clock Divider Value

P16 to P1 (Bits[DB31:DB16]) set the timeout counter for

activation of phase resync. This value must be set such that a

resync happens immediately after (and not before) the PLL has

achieved lock after reprogramming.

Calculate the timeout value using the following equation:

Time Out Value = Phase Resync Clock/PFD Frequency

Reserved

Bits[DB15:DB4] are reserved. Bit DB10 and Bit DB4 must be set

to 1, but all other bits in this range must be set to 0.

At initial power-up, after the correct application of voltages to

the supply pins, program the ADF4355 registers in the

following sequence:

1. Register 12

2. Register 11

3. Register 10

4. Register 9

5. Register 8

6. Register 7

7. Register 6

8. Register 5

9. Register 4

10. Register 3

11. Register 2

12. Register 1

13. Register 0

FREQUENCY UPDATE SEQUENCE

Frequency updates require updating the auxiliary modulator

(MOD2) in Register 2, the fractional value (FRAC1) in Register 1,

and the integer value (INT) in Register 0. A counter reset

(Bit DB4) is also required in the frequency update sequence.

Therefore, the sequence must be as follows:

1. Register 4 (counter reset enabled [DB4 = 1])

2. Register 2

3. Register 1

4. Register 0 (autocal disabled [DB21 = 0])

5. Register 4 (counter reset disabled [DB4 = 0])

6. Wait > 16 ADC_CLK cycles. For example, if ADC_CLK =

99.417 kHz, wait 16/99417 sec = 161 μs. See Register 10.

7. Register 0 (autocal enabled [DB21 = 1])

The frequency change occurs on the second write to Register 0.

ADF4355 Data Sheet

RF SYNTHESIZER—A WORKED EXAMPLE

Use the following equations to program the ADF4355 synthesizer:

RFOUT =

MOD1

MOD2

FRAC2

FRAC1

INT

× (fPFD)/RF Divider (7)

where:

RFOUT is the RF frequency output.

INT is the integer division factor.

FRAC1 is the fractionality.

FRAC2 is the auxiliary fractionality.

MOD2 is the auxiliary modulus.

MOD1 is the fixed 24-bit modulus.

RF Divider is the output divider that divides down the VCO

frequency.

fPFD = REFIN × ((1 + D)/(R × (1 + T))) (8)

where:

REFIN is the reference frequency input.

D is the RF REFIN doubler bit.

R is the RF reference division factor.

T is the reference divide by 2 bit (0 or 1).

For example, in a universal mobile telecommunication system

(UMTS) where 2112.8 MHz RF frequency output (RFOUT) is

required, a 122.88 MHz reference frequency input (REFIN) is

available. Note that the ADF4355 VCO operates in the frequency

range of 3.4 GHz to 6.8 GHz. Therefore, an RF divider of 2 must

be used (VCO frequency = 4225.6 MHz, RFOUT = VCO frequency/

RF divider = 4225.6 MHz/2 = 2112.8 MHz).

The feedback path is also important. In this example, the VCO

output is fed back before the output divider (see Figure 43).

In this example, divide the 122.88 MHz reference signal by 2 to

generate a fPFD of 61.44 MHz. The desired channel spacing is

200 kHz.

12910-148

PFD

PFD VCO

DIVIDER

÷2

OUT

Figure 43. Loop Closed Before Output Divider

The worked example is as follows:

• N = VCOOUT/fPFD = 4225.6 MHz/61.44 MHz =

68.7760416666666667

• INT = int(VCO frequency/fPFD) = 68

• FRAC = 0.7760416666666667

• MOD1 = 16,777,216

• FRAC1 = int(MOD1 × FRAC) = 13019817

• Remainder = 0.6666666667 or 2/3

• MOD2 = fPFD/GCD(fPFD/fCHSP) = 61.44 MHz /

GCD(61.44 MHz/200 kHz) = 1536

• FRAC2 = remainder × 1536 = 1024

From Equation 8,

fPFD = (122.88 MHz × (1 + 0)/2) = 61.44 MHz (9)

2112.8 MHz = 61.44 MHz × ((INT + (FRAC1 +

FRAC2/MOD2)/224))/2 (10)

where:

INT = 68

FRAC1 = 13,019,817

MOD2 = 1536

FRAC2 = 1024

RF Divider = 2

REFERENCE DOUBLER AND REFERENCE DIVIDER

The on-chip reference doubler allows the input reference signal

to be doubled. The doubler is useful for increasing the PFD

comparison frequency. To improve the noise performance of

the system, increase the PFD frequency. Doubling the PFD

frequency usually improves noise performance by 3 dB.

The reference divide by 2 divides the reference signal by 2,

resulting in a 50% duty cycle PFD frequency.

SPURIOUS OPTIMIZATION AND FAST LOCK

Narrow loop bandwidths can filter unwanted spurious signals,

but these bandwidths usually have a long lock time. A wider

loop bandwidth achieves faster lock times but may lead to

increased spurious signals inside the loop bandwidth.

OPTIMIZING JITTER

For lowest jitter applications, use the highest possible PFD

frequency to minimize the contribution of in-band noise from

the PLL. Set the PLL filter bandwidth such that the in-band noise

of the PLL intersects with the open-loop noise of the VCO,

minimizing the contribution of both to the overall noise.

Use the ADIsimPLL design tool for this task.

Rev. 0 | Page 30 of 35

Data Sheet ADF4355

SPUR MECHANISMS

This section describes the two different spur mechanisms that

arise with a fractional-N synthesizer and how to minimize them

in the ADF4355.

Integer Boundary Spurs

One mechanism for fractional spur creation is the interactions

between the RF VCO frequency and the reference frequency.

When these frequencies are not integer related (the purpose of a

fractional-N synthesizer), spur sidebands appear on the VCO

output spectrum at an offset frequency that corresponds to the

beat note or the difference in frequency between an integer

multiple of the reference and the VCO frequency. These spurs

are attenuated by the loop filter and are more noticeable on

channels close to integer multiples of the reference where the

difference frequency can be inside the loop bandwidth (thus

the name, integer boundary spurs).

Reference Spurs

Reference spurs are generally not a problem in fractional-N

synthesizers because the reference offset is far outside the loop

bandwidth. However, any reference feedthrough mechanism

that bypasses the loop may cause a problem. Feedthrough of

low levels of on-chip reference switching noise, through the

prescaler back to the VCO, can result in reference spur levels

as high as −80 dBc.

LOCK TIME

The PLL lock time divides into a number of settings. All of

these are modeled in the ADIsimPLL design tool. Faster lock

times than those detailed in this data sheet are possible; contact

your local Analog Devices, Inc., sales representative for more

information.

Lock Time—A Worked Example

Assuming fPFD = 61.44 MHz,

VCO Band Div = Ceiling(fPFD/2,400,000) = 26

where Ceiling() rounds up to the nearest integer.

By combining the following two equations:

ALC Wait > (50 µs × fPFD)/Timeout

Synthesizer Lock Timeout > (20 µs × fPFD)/Timeout

The following is found:

ALC Wait = 2.5 × Synthesizer Lock Timeout

Maximize ALC Wait (to reduce Timeout to minimize time) so

that ALC Wait = 30 and Synthesizer Lock Timeout = 12.

Finally, ALC Wait > (50 µs × fPFD)/Timeout, is rearranged as

Timeout = Ceiling((fPFD × 50 µs)/ALC Wait)

Timeout = Ceiling((61.44 MHz × 50 µs)/30) = 103

Synthesizer Lock Timeout

The synthesizer lock timeout ensures that the VCO calibration

DAC, which forces VTUNE, has settled to a steady value for the

band select circuitry.

The timeout and synthesizer lock timeout variables programmed

in Register 9 select the length of time the DAC is allowed to

settle to the final voltage before the VCO calibration process

continues to the next phase, which is VCO band selection. The

PFD frequency is used as the clock for this logic, and the

duration is set by

Frequency

PFD

Timeout

Lockr

Synthesize

Timeout ×

The calculated time must be equal to or greater than 20 µs.

VCO Band Selection

Use the PFD frequency again as the clock for the band selection

process. Calculate this value by

PFD/(VCO Band Selection × 16) < 150 kHz

The band selection takes 11 cycles of the previously calculated

value. Calculate the duration by

11 × (VCO Band Selection × 16)/PFD Frequency

Automatic Level Calibration Timeout

Use the automatic level calibration (ALC) function to choose

the correct bias current in the ADF4355 VCO core. Calculate

the time taken by

5 × 11 × ALC Wait × Timeout/PFD Frequency

PLL Low-Pass Filter Settling Time

The time taken for the loop to settle is inversely proportional to

the low-pass filter bandwidth. The settling time is also modeled

in the ADIsimPLL design tool.

The total lock time for changing frequencies is the sum of the

four separate times (synthesizer lock, VCO band selection, ALC

timeout, and PLL settling time) and is all modeled in the

ADIsimPLL design tool.

Rev. 0 | Page 31 of 35

ADF4355 Data Sheet

APPLICATIONS INFORMATION

DIRECT CONVERSION MODULATOR

Direct conversion architectures are increasingly being used to

implement base station transmitters. Figure 44 shows how to

use Analog Devices devices to implement such a system.

The circuit block diagram shows the AD9761 TxDAC+® being

used with the ADL5375. The use of a dual integrated DAC, such

as the AD9761, ensures minimum error contribution (over

temperature) from this portion of the signal chain.

The local oscillator (LO) is implemented using the ADF4355.

The low-pass filter was designed using the ADIsimPLL design

tool for a PFD of 61.44 MHz and a closed-loop bandwidth of

20 kHz.

The LO ports of the ADL5375 can be driven differentially from

the complementary RFOUTA+/RFOUTA− outputs of the ADF4355.

Differential drive gives better second-order distortion performance

than a single-ended LO driver and eliminates the use of a balun

to convert from a single-ended LO input to the more desirable

differential LO input for the ADL5375.

The ADL5375 accepts LO drive levels from −6 dBm to +6 dBm.

The optimum LO power can be software programmed on the

ADF4355, which allows levels from −4 dBm to +5 dBm from

each output.

The RF output is designed to drive a 50 Ω load; however, it

must be ac-coupled, as shown in Figure 44. If the I and Q inputs

are driven in quadrature by 2 V p-p signals, the resulting output

power from the ADL5375 modulator is approximately 2 dBm.

AD9761

TxDAC

REFIO

FSADJ

MODULATED

DIGITAL

DATA

QOUTB

IOUTA

IOUTB

QOUTA

2kΩ

LOW-PASS

FILTER

LOW-PASS

FILTER

IBBP

IBBN

QBBP

QBBN

LOIP

LOIN

51Ω 51Ω

51Ω51Ω

ADL5375

RFOUT

QUADRATURE

PHASE

SPLITTER

DSOP

1500pF 390pF

33nF

3.3kΩ

1kΩ

SPI-COMPATIBLE SERIAL BUS

ADF4355

VCO

OUT

B–

OUT

B+

OUT

1nF1nF

4.7kΩ

SET

DATA

CLK

REF

FREF

TUNE

VCO

PDB

OUT

A–

OUT

A+

7.5nH 7.5nH

1nF

OUT

1nF1nF

FREF

MUXOUT

LOCK

DETECT

25 30

REG

100nF

REG

100nF

12910-138

LPF

GND

831 913 18 21

GNDRF

GNDVCO

19 23 24

GND

10pF 0.1µF 10pF 0.1µF 10pF 0.1µF

REGVCO

BIAS

REF

Figure 44. Direct Conversion Modulator

Rev. 0 | Page 32 of 35

Data Sheet ADF4355

POWER SUPPLIES

The ADF4355 contains four multiband VCOs that together cover

an octave range of frequencies. To ensure best performance, it is

vital to connect a low noise regulator, such as the ADM7150, to

the VVCO pin. Connect the same regulator to VREGVCO and VP.

For the 3.3 V supply pins, use one or two ADM7150 regulators.

Figure 45 shows the recommended connections.

PRINTED CIRCUIT BOARD (PCB) DESIGN

GUIDELINES FOR A CHIP-SCALE PACKAGE

The lands on the 32-lead lead frame chip-scale package are

rectangular. The PCB pad for these lands must be 0.1 mm

longer than the package land length and 0.05 mm wider than

the package land width. Center each land on the pad to

maximize the solder joint size.

The bottom of the chip-scale package has a central exposed

thermal pad. The thermal pad on the PCB must be at least as

large as the exposed pad. On the PCB, there must be a minimum

clearance of 0.25 mm between the thermal pad and the inner

edges of the pad pattern. This clearance ensures the avoidance

of shorting.

To improve the thermal performance of the package, use

thermal vias on the PCB thermal pad. If vias are used,

incorporate them into the thermal pad at the 1.2 mm pitch grid.

The via diameter must be between 0.3 mm and 0.33 mm, and

the via barrel must be plated with 1 oz. of copper to plug the via.

For a microwave PLL and VCO synthesizer, such as the

ADF4355, take care with the board stack-up and layout. Do not

consider using FR4 material because it is too lossy above 3 GHz.

Instead, Rogers 4350, Rogers 4003, or Rogers 3003 dielectric

material is suitable.

Take care with the RF output traces to minimize discontinuities

and ensure the best signal integrity. Via placement and

grounding are critical.

1500pF 390pF

33nF

3.3kΩ

1kΩ

SPI-COMPATIBLE SERIAL BUS

ADF4355

VCO

GND

OUT

B–

OUT

B+

OUT

1nF1nF

4.7kΩ

SET

DATA

CLK

FREF

TUNE

CE MUXOUT

831 913 18 21

LOCK

DETECT

GNDRF

GNDVCO

19 23 24

25 30

PDB

GND

632

10pF 0.1µF 10pF 0.1µF 10pF 0.1µF

OUT

A–

OUT

A+

7.5nH 7.5nH

1nF

OUT

1µF

OUT

= 5.0V

= 6.0V

OFF

OUT

BYP

1µF

REG

10µF

100nF 100nF

1nF1nF

FREF

OUT

1µF

OUT

= 3.3V

= 6.0V

VOUT

REF

REF_SENSE

VIN

GND

OFF

ADM7150

BYP

1µF

REG

10µF

BYP

VREG

VOUT

REF

REF_SENSE

VIN

GND

ADM7150

BYP

VREG

REF

REGVCO

BIAS

REG

2 C

REG

REF

12910-050

Figure 45. ADF4355 Power Supplies

Rev. 0 | Page 33 of 35

ADF4355 Data Sheet

OUTPUT MATCHING

The low frequency output can simply be ac-coupled to the next

circuit, if desired; however, if higher output power is required,

use a pull-up inductor to increase the output power level.

7.5nH

100pF

RFOUTA+

VRF

50Ω

12910-051

Figure 46. Optimum Output Stage

When differential outputs are not needed, terminate the unused

output or combine it with both outputs using a balun.

For lower frequencies below 2 GHz, it is recommended to use a

100 nH inductor on the RFOUTA+/RFOUTA− pins.

The RFOUTA+/RFOUTA− pins are a differential circuit. Provide

each output with the same (or similar) components where

possible, such as the same shunt inductor value, bypass

capacitor, and termination.

The auxiliary frequency output, RFOUTB+/RFOUTB−, can be

treated the same as the RFOUTA+/RFOUTA− output. If unused,

leave both RFOUTB+/RFOUTB− pins open.

Rev. 0 | Page 34 of 35

Data Sheet ADF4355

Rev. 0 | Page 35 of 35

OUTLINE DIMENSIONS

08-16-2010-B

0.50

BSC

BOTTOM VIEWTOP VIEW

PIN 1

INDICATOR

916

EXPOSED

PAD

PIN 1

INDICATOR

SEATING

PLANE

0.05 MAX

0.02 NOM

0.20 REF

COPLANARITY

0.08

0.30

0.25

0.18

5.10

5.00 SQ

4.90

0.80

0.75

0.70

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

SECTION OF THIS DATA SHEET.

0.50

0.40

0.30

0.25 MIN

*3.75

3.60 SQ

3.55

*COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-5

WITH THE EXCEPTION OF THE EXPOSED PAD DIMENSION.

Figure 47. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

5 mm × 5 mm Body, Very, Very Thin Quad

(CP-32-12)

Dimensions shown in millimeters

ORDERING GUIDE

Model1 Temperature Range Package Description Package Option

ADF4355BCPZ −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-12

ADF4355BCPZ-RL7 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-12

EV-ADF4355SD1Z Evaluation Board

1 Z = RoHS Compliant Part.

registered trademarks are the property of their respective owners.

D12910-0-4/15(0)

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