Ultralow Noise VGAs with
Preamplifier and Programmable RIN
AD8331/AD8332
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.326.8703 © 2003 Analog Devices, Inc. All rights reserved.
FEATURES
Ultralow noise preamplifier
Voltage noise = 0.74 nV/√Hz
Current noise = 2.5 pA/√Hz
3 dB bandwidth: 120 MHz
Low power: 125 mW/channel
Wide gain range with programmable postamp
–4.5 dB to +43.5 dB
+7.5 dB to +55.5 dB
Low output-referred noise: 48 nV/√Hz typical
Active input impedance matching
Optimized for 10-/12-bit ADCs
Selectable output clamping level
Single 5 V supply operation
Available in space-saving chip scale package
APPLICATIONS
Ultrasound and sonar time-gain control
High performance AGC systems
I/Q signal processing
High speed dual ADC driver
GENERAL DESCRIPTION
The AD8331/AD8332 are single- and dual-channel ultralow
noise, linear-in-dB, variable gain amplifiers. Although optimized
for ultrasound systems, they are usable as low noise variable
gain elements at frequencies up to 120 MHz.
Each channel consists of an ultralow noise preamplifier (LNA),
an X-AMP® VGA with 48 dB of gain range, and a selectable gain
postamplifier with adjustable output limiting. The LNA gain is
19 dB with a single-ended input and differential outputs capable
of accurate, programmable active input impedance matching by
selecting an external feedback resistor. Active impedance
control optimizes noise performance for applications that
benefit from input matching.
The 48 dB gain range of the VGA makes these devices suitable
for a variety of applications. Excellent bandwidth uniformity is
maintained across the entire range. The gain control interface
provides precise linear-in-dB scaling of 50 dB/V for control
voltages between 40 mV and 1 V. Factory trim ensures excellent
part-to-part and channel-to-channel gain matching. Differential
signal paths lead to superb second and third order distortion
performance and low crosstalk.
FUNCTIONAL BLOCK DIAGRAM
BIAS AND
INTERPOLATOR
VOL1
VPSV
VOH1
V
MID
BIAS
(V
MID
)
COM1
LNA 1 VGA 1
–
+
–
+
–
+
[(–48 to 0) + 21] dB
–
+
LNA 2 VGA 2
POST
AMP1
POST
AMP2
ENB
VPS1
26
23
27
28
1
2
3
6
COM2
INH2
LMD2
INH1
LMD1
VPS2
VIN1VIP1LOP1LON1
VIN2VIP2LOP2LON2
GAIN
INT
VOL2
VOH2
GAIN
CLAMP
RCLMP
COMM
HILOVCM2VCM1
3.5dB/15.5dB
+19dB
25 24 22 21 15 20 9 19
4 5 7 8 14 18 11
17
16
10
13
12
03199-B-001
Figure 1. AD8332 Shown 28-Lead TSSOP
GAIN (dB)
FREQUENCY (Hz)
–10
0
10
20
40
30
50
100k
–20 1M 1G100M10M
V
GAIN
= 1V
0.8V
0.6V
0.4V
0.2V
0V
03199-C-002
Figure 2. Frequency Response vs. Gain
The VGA’s low output-referred noise is advantageous in driving
high speed differential ADCs. The gain of the postamplifier may
be pin selected to 3.5 dB or 15.5 dB to optimize gain range and
output noise for 12-bit or 10-bit converter applications. The
output may be limited to a user-selected clamping level,
preventing input overload to a subsequent ADC. An external
resistor adjusts the clamping level.
The operating temperature range is –40°C to +85°. The
AD8331 is available in a 20-lead QSOP package, and the
AD8332 in 28-lead TSSOP and 32-lead LFCSP packages. They
require a single 5 V supply, and the quiescent power
consumption is 125 mW/ch. A power-down (enable) pin is
provided.
AD8331/AD8332
Rev. C | Page 2 of 32
TABLE OF CONTENTS
REVISION HISTORY.................................................................. 2
AD8331, AD8332—Specifications.................................................. 3
Absolute Maximum Ratings............................................................ 6
ESD CAUTION ............................................................................ 6
AD8331, AD8332—Typical Performance Characteristics .......... 7
Test Circuits..................................................................................... 15
Theory of Operation......................................................................17
Overview...................................................................................... 17
Low Noise Amplifier (LNA)...................................................... 17
Variable Gain Amplifier............................................................. 19
Postamplifier ............................................................................... 21
Applications..................................................................................... 22
LNA – External Components................................................... 22
Driving ADCs ............................................................................. 24
Overload...................................................................................... 24
Optional Input Overload Protection. ...................................... 25
Layout, Grounding, And Bypassing......................................... 25
Multiple Input Matching ........................................................... 25
Disabling the LNA...................................................................... 25
Measurement Considerations................................................... 26
Ultrasound TGC Application ................................................... 26
Pin Configuration and Function Descriptions........................... 30
AD8331........................................................................................ 30
AD8332........................................................................................ 31
Outline Dimensions....................................................................... 32
Ordering Guide .......................................................................... 32
REVISION HISTORY
Revision C
11/03—Data Sheet Changed from REV. B to REV. C
Addition of New Part...........................................................Universal
Changes to Figures ...............................................................Universal
Updated Outline Dimensions..........................................................32
5/03—Data Sheet Changed from REV. A to REV. B
Edits to Ordering Guide....................................................................32
Edits to Ultrasound TGC Application section................................25
Added Figure 71, Figure 72, and Figure 73......................................26
Updated Outline Dimensions............................................................31
2/03—Data Sheet Changed from REV. 0 to REV. A
Edits to Ordering Guide.....................................................................32
AD8331/AD8332
Rev. C | Page 3 of 32
AD8331, AD8332—SPECIFICATIONS
Table 1. TA = 25°C, VS = 5 V, RL = 500 Ω, RS = RIN = 50 Ω, RFB = 280 Ω, CSH = 22 pF, f = 10 MHz, RCLMP = ∞, CL = 1 pF,
VCM pin floating, –4.5 dB to +43.5 dB gain (HILO = LO), and differential output voltage, unless otherwise specified.
Parameter Conditions Min Typ Max Unit
LNA CHARACTERISTICS
Single-Ended Input
to Differential Output 19 dB
Gain
Input to Output (Single-Ended) 13 dB
Input Voltage Range AC-Coupled ±275 mV
RFB = 280 Ω 50 Ω
RFB = 412 Ω 75 Ω
RFB = 562 Ω 100 Ω
RFB = 1.13 kΩ 200 Ω
Input Resistance
RFB = ∞ 6 kΩ
Input Capacitance 13 pF
Output Impedance Single-Ended, Either Output 5 Ω
–3 dB Small Signal Bandwidth VOUT = 0.2 V p-p 130 MHz
Slew Rate 650 V/µs
Input Voltage Noise RS = 0 Ω, HI or LO Gain,
RFB = ∞, f = 5 MHz 0.74 nV/√Hz
Input Current Noise RFB = ∞, HI or LO Gain, f = 5 MHz 2.5 pA/√Hz
Noise Figure f = 10 MHz, LOP Output
Active Termination Match RS = RIN = 50 Ω 3.7 dB
Unterminated RS = 50 Ω, RFB = ∞ 2.5 dB
Harmonic Distortion @ LOP1 or LOP2
HD2 –56 dBc
HD3
VOUT = 0.5 V p-p,
Single-Ended, f = 10 MHz –70 dBc
Output Short-Circuit Current Pins LON, LOP 165 mA
LNA + VGA CHARACTERISTICS
–3 dB Small Signal Bandwidth VOUT = 0.2 V p-p 120 MHz
–3 dB Large Signal Bandwidth VOUT = 2 V p-p 110 MHz
LO Gain 300 V/µs Slew Rate
HI Gain 1200 V/µs
Input Voltage Noise RS = 0 Ω, HI or LO Gain,
RFB = ∞, f = 5 MHz 0.82 nV/√Hz
Noise Figure VGAIN = 1.0 V
RS = RIN = 50 Ω,
f = 10 MHz, Measured 4.15 dB
Active Termination Match
RS = RIN = 200 Ω,
f = 5 MHz, Simulated 2.0 dB
RS = 50 Ω, RFB = ∞,
f = 10 MHz, Measured 2.5 dB
Unterminated
RS = 200 Ω, RFB = ∞,
f = 5 MHz, Simulated 1.0 dB
VGAIN = 0.5 V, LO Gain 48 nV/√Hz Output-Referred Noise
VGAIN = 0.5 V, HI Gain 178 nV/√Hz
Output Impedance, Postamplifier DC to 1 MHz 1 Ω
Output Signal Range, Postamplifier RL ≥ 500 Ω,
Unclamped, Either Pin V
CM ± 1.125 V
Differential 4.5 V p-p
Output Offset Voltage
Differential –50 ±5 +50 mV
Common-Mode
VGAIN = 0.5 V
–125 –25 +100 mV
Output Short-Circuit Current 45 mA
AD8331/AD8332
Rev. C | Page 4 of 32
Parameter Conditions Min Typ Max Unit
Harmonic Distortion VGAIN = 0.5 V, VOUT = 1 V p-p
HD2 –88 dBc
HD3 f = 1 MHz –85 dBc
HD2 –68 dBc
HD3 f = 10 MHz –65 dBc
Input 1 dB Compression Point VGAIN = 0.25 V, VOUT = 1 V p-p, f = 1 MHz–10 MHz 7 dBm1
VGAIN = 0.72 V, VOUT = 1 V p-p, f = 1 MHz –80 dBc
Two-Tone Intermodulation
Distortion (IMD3) VGAIN = 0.5 V, VOUT = 1 V p-p, f = 10 MHz –72 dBc
VGAIN = 0.5 V, VOUT = 1 V p-p, f = 1 MHz 38 dBm Output Third Order Intercept
VGAIN = 0.5 V, VOUT = 1 V p-p, f = 10 MHz 33 dBm
Channel-to-Channel Crosstalk
(AD8332) VGAIN = 0.5 V, VOUT = 1 V p-p, f = 1 MHz –84 dB
Overload Recovery VGAIN = 1.0 V,
VIN = 50 mV p-p/1 V p-p,
f = 10 MHz
5 ns
Group Delay Variation 5 MHz < f < 50 MHz, Full Gain Range ±2 ns
ACCURACY
0.05 V < VGAIN < 0.10 V –1 +0.5 +2 dB
0.10 V < VGAIN < 0.95 V –1 ±0.3 +1 dB
Absolute Gain Error2
0.95 V < VGAIN < 1.0 V –2 –1 +1 dB
Gain Law Conformance3 0.1 V < VGAIN < 0.95 V ±0.2 dB
Channel-to-Channel Gain Matching 0.1 V < VGAIN < 0.95 V ±0.1 dB
GAIN CONTROL INTERFACE
(Pin GAIN)
Gain Scaling Factor 0.10 V < VGAIN < 0.95 V 50 dB/V
LO Gain –4.5 to +43.5 dB Gain Range
HI Gain +7.5 to +55.5 dB
Input Voltage (VGAIN) Range 0 to 1.0 V
Input Impedance 10 MΩ
Response Time 48 dB Gain Change to 90% Full Scale 750 ns
COMMON-MODE INTERFACE
(Pin VCMn)
Input Resistance Current Limited to ±1 mA 30 Ω
Output CM Offset Voltage VCM = 2.5 V –125 –25 +100 mV
Voltage Range VOUT = 2.0 V p-p 1.5 to 3.5 V
ENABLE INTERFACE
(Pins ENB, ENBL, ENBV)
Logic Level to Enable Power 2.25 5 V
Logic Level to Disable Power 0 1.0 V
Pin ENB 25 kΩ
Pin ENBL 40 kΩ
Input Resistance
Pin ENBV 70 kΩ
VINH = 30 mV p-p 300 µs Power-Up Response Time
VINH = 150 mV p-p 4 ms
HILO GAIN RANGE INTERFACE
(Pin HILO)
Logic Level to Select HI Gain Range 2.25 5 V
Logic Level to Select LO Gain Range 0 1.0 V
Input Resistance 50 kΩ
1 All dBm values are referred to 50 Ω, unless otherwise noted.
2 Conformance to theoretical gain expression (see Equation 1).
3 Conformance to best fit dB linear curve.
AD8331/AD8332
Rev. C | Page 5 of 32
Parameter Conditions Min Typ Max Unit
OUTPUT CLAMP INTERFACE
(Pin RCLMP; HI or LO Gain)
Accuracy
HILO = LO RCLMP = 2.74 kΩ, VOUT = 1 V p-p (Clamped) ±50 mV
HILO = HI RCLMP = 2.21 kΩ, VOUT = 1 V p-p (Clamped) ±75 mV
MODE INTERFACE
(Pin MODE)
Logic Level for Positive Gain Slope 0 1.0 V
Logic Level for Negative Gain Slope 2.25 5 V
Input Resistance 200 kΩ
POWER SUPPLY
(Pins VPS1, VPS2, VPSV, VPSL, VPOS)
Supply Voltage 4.5 5.0 5.5 V
Quiescent Current per Channel 25 mA
Power Dissipation per channel No Signal 125 mW
Disable Current
AD8332 (VGA and LNA) 300 600 µA
AD8331 (VGA and LNA) 240 400 µA
AD8332 (ENBL) Each Channel 12 mA
AD8332 (ENBV) Each Channel 13 mA
AD8331 (ENBL) 11 mA
AD8331 (ENBV) 14 mA
PSRR VGAIN = 0, f = 100 kHz –68 dB
AD8331/AD8332
Rev. C | Page 6 of 32
ABSOLUTE MAXIMUM RATINGS
Table 2. Absolute Maximum Ratings
Parameter Rating
Voltage
Supply Voltage (VPSn, VPSV, VPSL, VPOS) 5.5 V
Input Voltage (INHn) VS + 200 mV
ENB, ENBL, ENBV, HILO Voltage VS + 200 mV
GAIN Voltage 2.5 V
Power Dissipation
RU-28 Package (AD8332)4 0.96 W
CP-32 Package (AD8332)5 1.97 W
RQ-20 Package (AD8331)4 0.78 W
Temperature
Operating Temperature –40°C to +85°C
Storage Temperature –65°C to +150°C
Lead Temperature (Soldering 60 sec) 300°C
θJA
RU-28 Package (AD8332)4 68°C/W
CP-32 Package (AD8332)5 33°C/W
RQ-20 Package (AD8331)4 83°C/W
θJC
RU-28 Package (AD8332)4 14°C/W
CP-32 Package (AD8332)5 33°C/W
RQ-20 Package (AD8331)4 n/a
4 Four-Layer JEDEC Board (2S2P).
5 Exposed pad soldered to board, nine thermal vias in pad — JEDEC 4-Layer
Board J-STD-51-9.
Stresses above those listed under the Absolute Maximum
Ratings may cause permanent damage to the device. This is a
stress rating only; functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
AD8331/AD8332
Rev. C | Page 7 of 32
AD8331, AD8332—TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VS = 5 V, RL = 500 Ω, RS = RIN = 50 Ω, RFB = 280 Ω, CSH = 22 pF, f = 10 MHz, RCLMP = ∞, CL = 1 pF, VCM = 2.5 V,
–4.5 dB to +43.5 dB gain (HILO = LO), and differential signal voltage, unless otherwise specified.
0 0.2 V
GAIN
(V)
0.60.4 1.00.8 1.1
GAIN (dB)
40
50
30
10
0
20
–10
60
MODE = HI
(AC PACKAGE
ONLY)
MODE = LO
HILO = LO
03199-C-003
HILO = HI
Figure 3. Gain vs. VGAIN and MODE (MODE Available on AC Package)
03199-C-004
GAIN ERROR (dB)
0.5
1.0
2.0
1.5
00.2 VGAIN (V)
0.60.4
0
–1.0
–1.5
–0.5
–2.0 1.00.8 1.1
–40°C
+85°C
+25°C
Figure 4. Absolute Gain Error vs. VGAIN at Three Temperatures
GAIN ERROR (dB)
0.5
1.0
2.0
1.5
0 0.2 V
GAIN
(V)
0.60.4
0
–1.0
–1.5
–0.5
–2.0 1.00.8 1.1
1MHz
30MHz
70MHz
03199-C-005
10MHz
Figure 5. Absolute Gain Error vs. VGAIN at Various Frequencies
0
% OF UNITS
10
20
30
40
50
–0.1
GAIN ERROR (dB) 0.40–0.3 –0.2 0.1–0.4–0.5 0.30.2 0.5
SAMPLE SIZE = 80 UNITS
V
GAIN
= 0.5V
03199-C-006
Figure 6. Gain Error Histogram
% OF UNITS
0.01
CHANNEL-TO-CHANNEL GAIN MATCH(dB)
0
0.15
0.13
0.11
0.09
0.07
0.05
0.03
–0.01
0.21
0.19
0.17
–0.17
–0.15
–0.13
–0.11
–0.09
–0.07
–0.05
–0.03
5
25
20
15
10
0
5
25
20
15
10
V
GAIN
= 0.7V
SAMPLE SIZE = 50 UNITS
V
GAIN
= 0.2V
03199-C-007
Figure 7. Gain Match Histogram for VGAIN = 0.2 V and 0.7 V
GAIN(dB)
–10
0
10
20
40
30
50
100k
–20
FREQUENCY (Hz)
1M 1G100M10M
V
GAIN
= 1V
0.8V
0.6V
0.4V
0.2V
0V
03199-C-008
Figure 8. Frequency Response for Various Values of VGAIN
AD8331/AD8332
Rev. C | Page 8 of 32
FREQUENCY (Hz)
GAIN (dB)
–10
0
10
20
40
30
50
60
0.8V
0.6V
0.4V
0.2V
0V
1M 1G100k 100M10M
03199-C-009
V
GAIN
= 1V
Figure 9. Frequency Response for Various Values of VGAIN, HILO = HI
GAIN (dB)
–10
0
10
20
–40
30
–30
–20
1M 1G
100k 100M10M
VGAIN =0.5V RIN =R
S=50Ω,75Ω,100Ω
RIN =RS=1kΩ
03199-C-010
RIN =R
S= 500Ω
RIN =R
S=200Ω
FREQUENCY (Hz)
Figure 10. Frequency Response for Various Matched Source Impedances
FREQUENCY (Hz)
GAIN (dB)
–10
0
10
20
–40
30
–30
–20
1M 1G100k 100M10M
V
GAIN
= 0.5V
R
FB
= ∞
03199-C-011
Figure 11. Frequency Response, Unterminated, RS = 50 Ω
FREQUENCY (Hz)
CROSSTALK(dB)
–70
0
–60
–50
–30
–40
–20
1M100k 100M10M
–10
–90
–80
0.7V 0.4V
0.9V
V
GAIN
= 1V
0.5V
V
OUT
= 1 V p-p
03199-C-012
Figure 12. Channel-to-Channel Crosstalk vs.
Frequency for Various Values of VGAIN
FREQUENCY (Hz)
1M100k 100M10M
0
50
45
40
35
30
25
20
15
10
5
03199-C-013
0.1µF
COUPLING
1µF
COUPLING
GROUP DELAY (ns)
Figure 13. Group Delay vs. Frequency
1.10.40.20 0.30.1 0.90.70.5 0.80.6 1.0
–20
–10
0
10
20
–20
–10
0
10
20 T=+25°C
LO GAIN
T=+25°C
03199-C-014
VGAIN (V)
OFFSET VOLTAGE (mV)
HI GAIN T=+85°C
T=+85°C
T = –40°C
T = –40°C
T = –40°C
T=+25°C
T=+85°C
T = –40°C
Figure 14. Representative Differential Output Offset Voltage vs. VGAIN at Three
Temperatures
AD8331/AD8332
Rev. C | Page 9 of 32
% TOTAL
50.5
GAIN SCALING FACTOR
050.449.6 49.7 49.8 49.9 50.0 50.1 50.2 50.3
5
25
20
15
10
35 SAMPLE SIZE = 100
0.2V < VGAIN < 0.7V
30
03199-B-015
Figure 15. Gain Scaling Factor Histogram
100
100k 1M
10
1
0.1 10M 100M
FREQUENCY (Hz)
OUTPUT IMPEDANCE(Ω)
SINGLE ENDED, PIN VOH OR VOL
R
L
= ∞
03199-C-016
Figure 16. Output Impedance vs. Frequency
FREQUENCY (Hz)
INPUT IMPEDANCE (Ω)
100
1k
10
10k
1M100k 100M10M
R
FB
= ∞, C
SH
= 0pF
R
FB
= 270Ω, C
SH
= 22pF
R
FB
= 412Ω, C
SH
= 12pF
R
FB
= 549Ω, C
SH
= 8.2pF
R
FB
= 3.01kΩ, C
SH
= 0pF
R
FB
= 6.65kΩ, C
SH
= 0pF
R
FB
= 1.1kΩ, C
SH
= 1.2pF
03199-C-017
Figure 17. LNA Input Impedance vs. Frequency for
Various Values of RFB and CSH
0
Ω
17
Ω
25j
–25j
50j
–50j
100j
–100j
f = 100kHz
R
IN
= 50
Ω
R
FB
= 270
Ω
R
IN
= 75
Ω
,
R
FB
= 412
Ω
R
IN
= 100
Ω
,
R
FB
= 549
Ω
,
R
IN
= 200
Ω
,
R
FB
= 1.1k
Ω
R
IN
= 6k
Ω
,
R
FB
=
∞
03199-B-018
Figure 18. Smith Chart, S11 vs. Frequency, 0.1 MHz to 200 MHz
for Various Values of RFB
1G
FREQUENCY (Hz)
10M
GAIN (dB)
100k
–10
–5
0
5
20
10
15
100M1M
–20
–15
R
IN
= 50
Ω
, 75
Ω
,
AND 100
Ω
R
IN
= 200
Ω
R
IN
= 200
Ω
R
IN
= 500
Ω
R
IN
= 1k
Ω
03199-C-019
Figure 19. LNA Frequency Response,
Single-Ended, for Various Values of RIN
1G
FREQUENCY (Hz)
10M
GAIN (dB)
100k
–10
–5
0
5
20
10
15
100M1M
–20
–15
R
FB
= ∞
03199-C-020
Figure 20. LNA Frequency Response, Unterminated, Single-Ended
AD8331/AD8332
Rev. C | Page 10 of 32
500
0 0.4V
GAIN
(V) 1.00.6
300
0
100
400
200
0.2 0.8
OUTPUT-REFERRED NOISE(nV/ Hz)
HILO = HI
f = 10MHz
HILO = LO
03199-C-021
Figure 21. Output-Referred Noise vs. VGAIN
1M 10M
0100M100k FREQUENCY (Hz)
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
INPUT NOISE(nV/ Hz)
R
S
= 0, R
FB
= ∞, V
GAIN
= 1V
HILO = LO OR HI
03199-C-022
Figure 22. Short-Circuit Input-Referred Noise vs. Frequency
1
0 0.4 V
GAIN
(V) 1.00.6
0.1
100
10
0.2 0.8
INPUT NOISE (nV/ Hz)
R
S
= 0, R
FB
= ∞,
HILO = LO OR HI, f = 10MHz
03199-C-023
Figure 23. Short-Circuit Input-Referred Noise vs. VGAIN
90
TEMPERATURE (°C)
10–30–50 –10 705030
0.50
1.00
0.95
0.90
0.85
0.80
0.75
0.70
0.65
0.60
0.55
INPUT NOISE(nV/ Hz)
RS = 0, RFB = ∞,
VGAIN = 1V, f = 10MHz
03199-C-024
Figure 24. Short-Circuit Input-Referred Noise vs. Temperature
110
1.0
0.1 100 1k
SOURCE RESISTANCE (
Ω
)
10
INPUT NOISE(nV/ Hz)
R
S
= THERMAL NOISE ALONE
f = 5MHz, R
FB
=
∞
, V
GAIN
= 1V
03199-C-025
Figure 25. Input-Referred Noise vs. RS
NOISE FIGURE(dB)
5
6
7
4
2
1
3
010050 1k
75Ω
200Ω
SOURCE RESISTANCE (Ω)
R
IN
= 50Ω
R
FB
= ∞
INCLUDES NOISE OF VGA
SIMULATION
100Ω
03199-C-026
Figure 26. Noise Figure vs. RS for Various Values of RIN
AD8331/AD8332
Rev. C | Page 11 of 32
NOISE FIGURE(dB)
40
50
0 0.2 V
GAIN
(V)
0.60.4
30
10
0
20
5
1.00.8 1.1
35
45
25
15
0.1 0.50.3 0.90.7
HILO = LO, R
IN
= 50Ω
HILO = LO, R
FB
=∞
HILO = HI, R
FB
=∞
HILO = HI, R
IN
= 50Ω
f = 10MHz, R
S
= 50Ω
03199-C-027
Figure 27. Noise Figure vs. VGAIN
NOISE FIGURE(dB)
30
10 20 GAIN (dB)
3525
20
0
5
5545 60
25
15
10
15 30 5040
HILO = HI, RIN = 50Ω
HILO = HI, RFB =∞
HILO = LO, RIN = 50Ω
HILO = LO, RFB =∞
f = 10MHz, RS= 50Ω
03199-C-028
Figure 28. Noise Figure vs. Gain
HARMONIC DISTORTION (dBc)
–70
–60
–50
–40
–100
–90
–80
100M1M 10M
HILO = HI,
HD3
–30
–20
–10
0
G = 30dB
V
OUT
=1V
P-P
FREQUENCY (Hz)
03199-C-029
HILO = LO,
HD3
HILO = HI,
HD2
HILO = LO,
HD2
Figure 29. Harmonic Distortion vs. Frequency
HARMONIC DISTORTION(dBc)
–70
–60
–50
–40
–100
–90
–80
200 8000 600400 1.0k 2.0k1.8k1.6k1.4k1.2k
–30
R
LOAD
(Ω)
HILO = LO,
HD3
HILO = LO,
HD2
f = 10MHz
V
OUT
= 1V p-p
HILO = HI,
HD2 HILO = HI,
HD3
03199-C-030
Figure 30. Harmonic Distortion vs. RLOAD
HARMONIC DISTORTION(dBc)
–70
–60
–50
–40
–100
–90
–80
10 40 5003020C
LOAD
(pF)
HILO = HI,
HD3 HILO = LO,
HD2
HILO = LO,
HD3
f = 10MHz
V
OUT
= 1V p-p
03199-C-031
HILO = HI,
HD2
Figure 31. Harmonic Distortion vs. CLOAD
HARMONIC DISTORTION(dBc)
–70
–60
–50
–40
–100
–90
–80
14032
f = 10MHz
GAIN = 30 dB
V
OUT
(V p-p)
HILO = LO,
HD3
HILO = HI,
HD3
HILO = LO,
HD2
03199-C-032
HILO = HI,
HD2
Figure 32. Harmonic Distortion vs. Differential Output Voltage
AD8331/AD8332
Rev. C | Page 12 of 32
DISTORTION (dBc)
0
–100
–80
–60
–40
–20
0
–120
V
OUT
= 1V p-p
03199-C-033
V
GAIN
(V)
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
HILO = LO,
HD2 HILO = HI,
HD2
HILO = LO,
HD3
HILO = HI,
HD3
INPUT RANGE
LIMITED WHEN
HILO = LO
Figure 33. Harmonic Distortion vs. VGAIN, f = 1 MHz
–100
–80
–60
–40
–20
0
–120
INPUT RANGE
LIMITED WHEN
HILO = LO
HILO = HI,
HD2 HILO = HI,
HD3
HILO = LO,
HD2
HILO = LO,
HD3
0V
GAIN
(V)
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
V
OUT
= 1V p-p
03199-C-034
DISTORTION (dBc)
Figure 34. Harmonic Distortion vs. VGAIN, f = 10 MHz
0.40.2
INPUT POWER(dBm)
0 0.30.1
–30 0.90.70.5 0.80.6 1.0
5
0
–5
–10
–15
–20
–25
10
V
GAIN
(V)
f = 10MHz
HILO = HI HILO = LO
03199-C-035
Figure 35. Input 1 dB Compression vs. VGAIN
100M
FREQUENCY (Hz)
1M
IMD3(dBc)
10M
–10
–90
–80
–70
–60
–30
–50
–40
–20
0V
OUT
= 1V p-p COMPOSITE (f
1
+ f
2
)
G = 30dB
03199-C-036
Figure 36. IMD3 vs. Frequency
OUTPUT IP3(dBm)
VGAIN (V)
15
20
25
30
0
5
10
0.1 0.40 0.30.2 1.00.90.80.70.60.5
40
35
HILO = HI,
1MHz
HILO = HI,
10MHz
HILO = LO,
10MHz
HILO = LO,
1MHz
VOUT = 1V p-p COMPOSITE (f1 + f2)
03199-C-037
Figure 37. Output Third Order Intercept vs. VGAIN
100
90
10
0
2mV
50mV 10ns
03199-C-038
Figure 38. Small Signal Pulse Response, G = 30 dB,
Top: Input, Bottom: Output Voltage, HILO = HI or LO
AD8331/AD8332
Rev. C | Page 13 of 32
100
90
10
0
500mV 10ns
03199-C-039
20mV
Figure 39. Large Signal Pulse Response, G = 30 dB,
HILO = HI or LO, Top: Input, Bottom: Output Voltage
10–10–30 0–20
–2 604020 5030–40
1
0
–1
2
8070
INPUT
03199-C-040
V
OUT
(V)
TIME (ns)
G = 30dB C
L
= 50pF
C
L
= 0pF
INPUT IS NOT TO SCALE
Figure 40. Large Signal Pulse Response for
Various Capacitive Loads, CL = 0 pF, 10 pF, 20 pF, 50 pF
400ns
200mV
500mV
03199-B-041
Figure 41. Pin GAIN Transient Response,
Top: VGAIN, Bottom: Output Voltage
V
OUT
(V p-p)
010 3020 5040
1
4
3
2
0
5
R
CLMP
(k
Ω
)
HILO = LO
HILO = HI
03199-C-042
Figure 42. Clamp Level vs. RCLMP
30
TIME (ns)
10
V
OUT
(V)
–10 200
–4 6040 50
1
0
–1
2
4
3
–2
–3
G = 40dB
R
CLMP
= 48.1kΩR
CLMP
= 16.5kΩ
R
CLMP
= 7.15kΩR
CLMP
= 2.67kΩ
03199-C-043
Figure 43. Clamp Level Pulse Response
100
90
10
0
100ns
200mV
03199-B-044
Figure 44. LNA Overdrive Recovery, VINH 0.05 V p-p to
1 V p-p Burst, VGAIN = 0.27 V, VGA Output Shown
AD8331/AD8332
Rev. C | Page 14 of 32
100
90
10
0
100ns
50mV
03199-B-045
Figure 45. VGA Overdrive Recovery, VINH 4 mV p-p to 70 mV p-p Burst,
VGAIN = 1 V, VGA Output Shown Attenuated 24 dB
100
90
10
0
100ns
50mV
03199-B-046
Figure 46. VGA Overdrive Recovery, VINH 4 mV p-p to 275 mV p-p Burst,
VGAIN = 1 V, VGA Output Shown Attenuated 24 dB
1ms
200mV
2V
03199-B-047
Figure 47. Enable Response, Top: VENB, Bottom: VOUT, VINH = 30 mV p-p
1V
2V
1ms
03199-B-048
Figure 48. Enable Response, Large Signal,
Top: VENB, Bottom: VOUT, VINH = 150 mV p-p
FREQUENCY (Hz)
PSRR(dB)
1M100k 100M10M
–80
0
–10
–20
–30
–40
–50
–60
–70
VPS1, VGAIN = 0.5V
VPS1, VGAIN = 0V
VPSV, VGAIN = 0.5V
03199-C-049
Figure 49. PSRR vs. Frequency (No Bypass Capacitor)
400
–40
40
45
50
55
60
20
–20
30
1008060
20
25
35
03199-C-050
TEMPERATURE (°C)
AD8331
AD8332
V
GAIN
= 0.5V
QUIESCENT SUPPLY CURRENT (mA)
Figure 50. Quiescent Supply Current vs. Temperature
AD8331/AD8332
Rev. C | Page 15 of 32
TEST CIRCUITS
LMD
1.8nF
22pF
FB*
120nH
INOUT
0.1µF
DUT
03199-C-051
*FERRITE BEAD
NETWORK ANALYZER
0.1µF
28Ω
237Ω
28Ω1:1
50Ω50Ω
0.1µF
270Ω
INH
237Ω
0.1µF
Figure 51. Gain and Bandwidth Measurements
1:1
IN
LMD DUT
0.1µF
22pF
FB*
120nH 0.1µF
03199-C-052
*FERRITE BEAD
50Ω
0.1µF
INH
0.1µF28Ω
237Ω
237Ω
28Ω
50Ω
1.8nF270Ω
OSCILLOSCOPE
Figure 52. Transient Measurements
1:1
LMD
INH
DUT
0.1µF
SPECTRUM
ANALYZER
IN
22pF
1Ω
49Ω
50Ω
ABG
*FERRITE BEAD
FB*
120nH
0.1µF
0.1µF
50Ω
03199-C-053
0.1µF
Figure 53. Used for Noise Measurements
AD8331/AD8332
Rev. C | Page 16 of 32
IN
50Ω
0.1µF
28Ω
03199-C-054
28Ω
0.1µF
0.1µF
0.1µF
50Ω
SPECTRUM
ANALYZER
120nH
FB*
22pF LMD
INH
DUT 1:1
1.8nF 270Ω
237Ω
237Ω
*FERRITE BEAD
Figure 54. Distortion
270Ω
1:1
NETWORK ANALYZER
LMD
INH
DUT
1.8nF
0.1µF
22pF
FB*
120nH
50Ω
INOUT
*FERRITE BEAD 28Ω
237Ω
50Ω
50Ω
0.1µF
0.1µF
0.1µF
237Ω
28Ω50Ω
03199-C-055
Figure 55. S11 Measurements
AD8331/AD8332
Rev. C | Page 17 of 32
THEORY OF OPERATION
OVERVIEW
The following discussion applies to all part numbers. Figure 56
and Figure 1 are functional block diagrams of the AD8331 and
AD8332, respectively.
LNA
2
1
6
3
LMD
INH
COML
VPSL
10
GAIN
COMM
LNA
BIAS
(V
MID
)
VGA
∆
G = –48dB to 0dB
+21dB
BIAS AND
INTERPOLATOR
20
4 5 78
17 19 18
V
MID
POST
AMP1
12
CLAMP
GAIN
INT
11 19
15
16
9
3.5dB/
15.5dB
ENBL ENBV RCLMP
VOH
VOL
MODE
LON LOP VIP VIN VPOS VCM
14
HILO
COMM
AD8331
03199-C-056
Figure 56. Functional Block Diagram — AD8331
Each channel contains an LNA that provides user-adjustable
input impedance termination, a differential X-AMP VGA, and a
programmable gain postamplifier with adjustable output
voltage limiting. Figure 57 shows a simplified block diagram.
VOL
VOH
LNA
CLAMP*
–
+INH
LMD
LOP
LON
HILO
VCM
PREAMPLIFIER
19dB
X-AMP VGA POSTAMP
[(–48 to 0) + 21] dB 3.5dB/15.5dB
GAIN
INTERFACE*
GAIN
BIAS AND
INTERPOLATOR*
VIN
VIP
*SHARED BETWEEN CHANNELS
RCLMP
BIAS
(V
MID
)V
MID
03199-B-057
Figure 57. Simplified Block Diagram
The linear-in-dB gain control interface is trimmed for slope and
absolute accuracy. The overall gain range is 48 dB, extending
from –4.5 dB to +43.5 dB or from +7.5 dB to +55.5 dB,
depending on the setting of the HILO pin. The slope of the gain
control interface is 50 dB/V, and the gain control range is 40 mV
to 1 V, leading to the following expressions for gain:
(
)
()
(
)
1,56 50)( LOHILOdB.–VVdBdBGAIN GAIN =×=
or
(
)
()
(
)
2,55 50)( HIHILOdB.VVdBdBGAIN GAIN =+×=
The gain characteristics are shown in Figure 58.
GAIN (dB)
40
50
00.2 V
GAIN
(V)
0.60.4
30
10
0
20
–10 1.00.8 1.1
60
HILO = HI
HILO = LO
MODE = LO
MODE = HI
(WHERE AVAILABLE)
03199-C-058
Figure 58. Gain Control Characteristics
When MODE is set high, (where available):
(
)
()
()
3=,545+×50–=)( LOHILOdB.VVdBdBGAIN GAIN
or
(
)
()
()
4=,557+×50–=)( HIHILOdB.VVdBdBGAIN GAIN
The LNA converts a single-ended input to a differential output
with a voltage gain of 19 dB. When only one output is used, the
gain is 13 dB. The inverting output is used for active input
impedance termination. Each of the LNA outputs is capacitively
coupled to a VGA input. The VGA consists of an attenuator
with a range of 48 dB followed by an amplifier with 21 dB of
gain, for a net gain range of –27 dB to +21 dB. The X-AMP
gain-interpolation technique results in low gain error and
uniform bandwidth, and differential signal paths minimize
distortion.
The final stage is a logic programmable amplifier with gains of
3.5 dB or 15.5 dB. The LO and HI gain modes are optimized
for 12-bit and 10-bit A/D converter applications, in terms of
output-referred noise and absolute gain range. Output voltage
limiting may be programmed by the user.
LOW NOISE AMPLIFIER (LNA)
Good noise performance relies on a proprietary ultralow noise
preamplifier at the beginning of the signal chain, which
minimizes the noise contribution in the following VGA. Active
impedance control optimizes noise performance for
applications that benefit from input matching.
AD8331/AD8332
Rev. C | Page 18 of 32
A simplified schematic of the LNA is shown in Figure 59. INH
is capacitively coupled to the source. An on-chip bias generator
centers the output dc levels at 2.5 V and the input voltages at
3.25 V. A capacitor CLMD of the same value as the input coupling
capacitor CINH is connected from the LMD pin to ground.
VPOS
INH
LOP
LMD
LON
R
S
C
INH
Q1 Q2
I
0
C
LMD
C
SH
R
FB
C
FB
03199-C-059
I
0
I
0
I
0
Figure 59. Simplified LNA Schematic
The LNA supports differential output voltages as high as
5 V p-p with positive and negative excursions of ±1.25 V, about
a common-mode voltage of 2.5 V. Since the differential gain
magnitude is 9, the maximum input signal before saturation is
± 275 mV or 550 mV p-p. Overload protection ensures quick
recovery time from large input voltages. Since the inputs are
capacitively coupled to a bias voltage near midsupply, very large
inputs can be handled without interacting with the ESD
protection.
Low value feedback resistors and the current-driving capability
of the output stage allow the LNA to achieve a low input-
referred voltage noise of 0.74 nV/√Hz. This is achieved with a
modest current consumption of 10 mA per channel (50 mW).
On-chip resistor matching results in precise gains of 4.5 per side
(9 differential), critical for accurate impedance control. The use
of a fully differential topology and negative feedback minimizes
distortion. Low HD2 is particularly important in second
harmonic ultrasound imaging applications. Differential
signaling enables smaller swings at each output, further
reducing third order distortion.
Active Impedance Matching
The LNA supports active impedance matching through an
external shunt feedback resistor from Pin LON to Pin INH. The
input resistance RIN is given by Equation 5, where A is the
single-ended gain of 4.5, and 6 kΩ is the unterminated input
impedance.
()
5
+Ω33
×Ω6
=Ω6
+1
=
FB
FB
FB
IN Rk
Rk
k
A
R
R
CFB is needed in series with RFB, since the dc levels at Pins LON
and INH are unequal. Expressions for choosing RFB in terms of
RIN and for choosing CFB are found in the Applications section.
CSH and the ferrite bead enhance stability at higher frequencies
where the loop gain declines and prevents peaking. Frequency
response plots of the LNA are shown in Figure 19 and Figure 20.
The bandwidth is approximately 130 MHz for matched input
impedances of 50 Ω to 200 Ω and declines at higher source
impedances. The unterminated bandwidth (RFB = ∞) is
approximately 80 MHz.
Each output can drive external loads as low as 100 Ω in addition
to the 100 Ω input impedance of the VGA (200 Ω differential).
Capacitive loading up to 10 pF is permissible. All loads should
be ac-coupled. Typically, Pin LOP output is used as a single-
ended driver for auxiliary circuits, such as those used for
Doppler mode ultrasound imaging, and Pin LON drives RFB.
Alternatively, a differential external circuit can be driven from
the two outputs, in addition to the active feedback termination.
In both cases, important stability considerations discussed in
the Applications section should be carefully observed.
The impedance at each LNA output is 5 Ω. A 0.4 dB reduction
in open-circuit gain results when driving the VGA, and 0.8 dB
with an additional 100 Ω load at the output. The differential
gain of the LNA is 6 dB higher. If the load is less than 200 Ω on
either side, a compensating load is recommended on the
opposite output.
LNA Noise
The input-referred voltage noise sets an important limit on
system performance. The short-circuit input voltage noise of the
LNA is 0.74 nV/√Hz or 0.82 nV/√Hz (at maximum gain),
including the VGA noise. The open-circuit current noise is
2.5 pA/√Hz. These measurements, taken without a feedback
resistor, provide the basis for calculating the input noise and
noise figure performance of the configurations in Figure 60.
Figure 61 and Figure 62 are simulations extracted from these
results, and the 4.1 dB NF measurement with the input actively
matched to a 50 Ω source. Unterminated (RFB = ∞) operation
exhibits the lowest equivalent input noise and noise figure.
Figure 61 shows the noise figure versus source resistance, rising
at low RS, where the LNA voltage noise is large compared to the
source noise, and again at high RS due to current noise. The
VGA’s input-referred voltage noise of 2.7 nV/√Hz is included in
all of the curves.
AD8331/AD8332
Rev. C | Page 19 of 32
V
OUT
UNTERMINATED
+
–
V
IN
R
IN
R
S
V
OUT
RESISTIVE TERMINATION
+
–
V
IN
R
IN
R
S
R
S
V
OUT
ACTIVE IMPEDANCE MATCH –R
S
= R
IN
+
–
V
IN
R
IN
R
FB
R
FB
1 + 4.5
R
S
R
IN
=
03199-C-060
Figure 60. Input Configurations
NOISE FIGURE(dB)
5
6
7
4
2
1
3
010050 1k
RS(Ω)
ACTIVE IMPEDANCE MATCH
RESISTIVE TERMINATION
(RS = RIN)
UNTERMINATED
SIMULATION
INCLUDES NOISE OF VGA
03199-C-061
Figure 61. Noise Figure vs. RS for Resistive,
Active Matched, and Unterminated Inputs
NOISE FIGURE (dB)
5
6
7
4
2
1
3
010050 1k
R
IN
= 50
Ω
70
Ω
R
FB
=
∞
R
S
(
Ω
)
200
Ω
INCLUDES NOISE OF VGA
100
Ω
SIMULATION
03199-C-081
Figure 62. Noise Figure vs. RS for Various Fixed Values of RIN, Actively Matched
The primary purpose of input impedance matching is to
improve the system transient response. With resistive
termination, the input noise increases due to the thermal noise
of the matching resistor and the increased contribution of the
LNA’s input voltage noise generator. With active impedance
matching, however, the contributions of both are smaller than
they would be for resistive termination by a factor of 1/(1 +
LNA Gain). Figure 61 shows their relative noise figure (NF)
performance. In this graph, the input impedance has been swept
with RS to preserve the match at each point. The noise figures
for a source impedance of 50 Ω are 7.1 dB, 4.1 dB, and 2.5 dB,
respectively, for the resistive, active, and unterminated
configurations. The noise figures for 200 Ω are 4.6 dB, 2.0 dB,
and 1.0 dB, respectively.
Figure 62 is a plot of the NF versus RS for various values of RIN,
which is helpful for design purposes. The plateau in the NF for
actively matched inputs mitigates source impedance variations.
For comparison purposes, a preamp with a gain of 19 dB and
noise spectral density of a 1.0 nV/√Hz, combined with a VGA
with 3.75 nV/√Hz, would yield a noise figure degradation of
approximately 1.5 dB (for most input impedances), significantly
worse than the AD8332 performance.
The equivalent input noise of the LNA is the same for single-
ended and differential output applications. The LNA noise
figure improves to 3.5 dB at 50 Ω without VGA noise, but this
is exclusive of noise contributions from other external circuits
connected to LOP. A series output resistor is usually
recommended for stability purposes, when driving external
circuits on a separate board (see the Applications section). In
low noise applications, a ferrite bead is even more desirable.
VARIABLE GAIN AMPLIFIER
The differential X-AMP VGA provides precise input
attenuation and interpolation. It has a low input-referred noise
of 2.7 nV/√Hz and excellent gain linearity. A simplified block
diagram is shown in Figure 63.
GAIN INTERPOLATOR
(BOTH CHANNELS) POST-AMP
VIP
GAIN
R
6dB
2R 48dB
VIN
g
m
03199-C-063
POST-AMP
Figure 63. Simplified VGA Schematic
AD8331/AD8332
Rev. C | Page 20 of 32
X-AMP VGA
The input of the VGA is a differential R-2R ladder attenuator
network, with 6 dB steps per stage and a net input impedance of
200 Ω differential. The ladder is driven by a fully differential
input signal from the LNA and is not intended for single-ended
operation. LNA outputs are ac-coupled to reduce offset and
isolate their common-mode voltage. The VGA inputs are biased
through the ladder’s center tap connection to VCM, which is
typically set to 2.5 V and is bypassed externally to provide a
clean ac ground.
The signal level at successive stages in the input attenuator falls
from 0 dB to –48 dB, in 6 dB steps. The input stages of the
X-AMP are distributed along the ladder, and a biasing interpolator,
controlled by the gain interface, determines the input tap point.
With overlapping bias currents, signals from successive taps merge
to provide a smooth attenuation range from 0 dB to –48 dB. This
circuit technique results in excellent, linear-in-dB gain law
conformance and low distortion levels and deviates ±0.2 dB or less
from ideal. The gain slope is monotonic with respect to the control
voltage and is stable with variations in process, temperature, and
supply.
The X-AMP inputs are part of a gain-of-12 feedback amplifier,
which completes the VGA. Its bandwidth is 150 MHz. The input
stage is designed to reduce feedthrough to the output and
ensure excellent frequency response uniformity across gain
setting (see Figure 8 and Figure 9).
Gain Control
Position along the VGA attenuator is controlled by a single-
ended analog control voltage, VGAIN, with an input range of 40 mV
to 1.0 V. The gain control scaling is trimmed to a slope of 50 dB/V
(20 mV/dB). Values of VGAIN beyond the control range saturate to
minimum or maximum gain values. Both channels of the
AD8332 are controlled from a single gain interface to preserve
matching. Gain can be calculated using Equations 1 and 2.
Gain accuracy is very good since both the scaling factor and
absolute gain are factory trimmed. The overall accuracy relative
to the theoretical gain expression is ±1 dB for variations in
temperature, process, supply voltage, interpolator gain ripple, trim
errors, and tester limits. The gain error relative to a best-fit line for
a given set of conditions is typically ±0.2 dB. Gain matching
between channels is better than 0.1 dB (see Figure 7, which shows
gain errors in the center of the control range). When VGAIN < 0.1
or > 0.95, gain errors are slightly greater.
The gain slope may be inverted, as shown in Figure 58 (avail-
able in most versions). The gain drops with a slope of
–50 dB/V across the gain control range from maximum to
minimum gain. This slope is useful in applications, such as
automatic gain control, where the control voltage is
proportional to the measured output signal amplitude. The
inverse gain mode is selected by setting the MODE pin HI.
Gain control response time is less than 750 ns to settle within
10% of the final value for a change from minimum to max-
imum gain.
VGA Noise
In a typical application, a VGA compresses a wide dynamic
range input signal to within the input span of an ADC. While
the input-referred noise of the LNA limits the minimum
resolvable input signal, the output-referred noise, which
depends primarily on the VGA, limits the maximum
instantaneous dynamic range that can be processed at any one
particular gain control voltage. This limit is set in accordance
with the quantization noise floor of the ADC.
Output and input-referred noise as a function of VGAIN are
plotted in Figure 21 and Figure 23 for the short-circuited input
condition. The input noise voltage is simply equal to the output
noise divided by the measured gain at each point in the control
range.
The output-referred noise is flat over most of the gain range,
since it is dominated by the fixed output-referred noise of the
VGA. Values are 48 nV/√Hz in LO gain mode and 178 nV/√Hz
in HI gain mode. At the high end of the gain control range, the
noise of the LNA and source prevail. The input-referred noise
reaches its minimum value near the maximum gain control
voltage, where the input-referred contribution of the VGA
becomes very small.
At lower gains, the input-referred noise, and thus noise figure,
increases as the gain decreases. The instantaneous dynamic
range of the system is not lost, however, since the input capacity
increases with it. The contribution of the ADC noise floor has
the same dependence as well. The important relationship is
the magnitude of the VGA output noise floor relative to that
of the ADC.
With its low output-referred noise levels, these devices ideally
drive low-voltage ADCs. The converter noise floor drops 12 dB
for every 2 bits of resolution and drops at lower input full-scale
voltages and higher sampling rates. ADC quantization noise is
discussed in the Applications section.
The preceding noise performance discussion applies to a
differential VGA output signal. Although the LNA noise
performance is the same in single-ended and differential
applications, the VGA performance is not. The noise of the
VGA is significantly higher in single-ended usage, since the
contribution of its bias noise is designed to cancel in the
differential signal. A transformer can be used with single-ended
applications when low noise is desired.
AD8331/AD8332
Rev. C | Page 21 of 32
Gain control noise is a concern in very low noise applications.
Thermal noise in the gain control interface can modulate the
channel gain. The resultant noise is proportional to the output
signal level and usually only evident when a large signal is
present. Its effect is observable only in LO gain mode, where the
noise floor is substantially lower. The gain interface includes an
on-chip noise filter, which reduces this effect significantly at
frequencies above 5 MHz. Care should be taken to minimize
noise impinging at the GAIN input. An external RC filter may
be used to remove VGAIN source noise. The filter bandwidth
should be sufficient to accommodate the desired control
bandwidth.
Common-Mode Biasing
An internal bias network connected to a midsupply voltage
establishes common-mode voltages in the VGA and postamp.
An externally bypassed buffer maintains the voltage. The bypass
capacitors form an important ac ground connection, since the
VCM network makes a number of important connections
internally, including the center tap of the VGA’s differential
input attenuator, the feedback network of the VGA’s fixed gain
amplifier, and the feedback network of the postamplifier in both
gain settings. For best results, use a 1 nF and a 0.1 µF capacitor
in parallel, with the 1 nF nearest to Pin VCM. Separate VCM
pins are provided for each channel. For dc-coupling to a 3 V
ADC, the output common-mode voltage is adjusted to 1.5 V by
biasing the VCM pin.
POSTAMPLIFIER
The final stage has a selectable gain of 3.5 dB or 15.5 dB, set by
the logic Pin HILO. These correspond to linear gains of 1.5 or 6.
A simplified block diagram of the postamplifier is shown in
Figure 64.
Separate feedback attenuators implement the two gain settings.
These are selected in conjunction with an appropriately scaled
input stage to maintain a constant 3 dB bandwidth between the
two gain modes (~150 MHz). The slew rate is 1200 V/µs in HI
gain mode and 300 V/µs in LO gain mode. The feedback
networks for HI and LO gain modes are factory trimmed to
adjust the absolute gains of each channel.
Noise
The topology of the postamplifier provides constant input-
referred noise with the two gain settings and variable output-
referred noise. The output-referred noise in HI gain mode
increases (with gain) by four. This setting is recommended
when driving converters with higher noise floors. The extra gain
boosts the output signal levels and noise floor appropriately.
When driving circuits with lower input noise floors, the LO gain
mode optimizes the output dynamic range.
Gm2
+
–Gm1
VOH
VOL
VCM
Gm1
Gm2
F1
F2
03199-B-064
Figure 64. Postamplifier Block Diagram
Although the quantization noise floor of an ADC depends on a
number of factors, the 48 nV/√Hz and 178 nV/√Hz levels are
well suited to the average requirements of most 12-bit and
10-bit converters, respectively. An additional technique,
described in the Applications section, can extend the noise floor
even lower for possible use with 14-bit ADCs.
Output Clamping
Outputs are internally limited to a level of 4.5 V p-p differential
when operating at a 2.5 V common-mode voltage. The postamp
implements an optional output clamp engaged through a
resistor from RCLMP to ground. Table shows a list of
recommended resistor values.
Output clamping can be used for ADC input overload
protection, if needed, or postamp overload protection when
operating from a lower common-mode level, such as 1.5 V. The
user should be aware that distortion products increase as output
levels approach the clamping levels and should adjust the clamp
resistor accordingly. Also, see the Applications section.
The accuracy of the clamping levels is approximately ±5% in LO
or HI mode. Figure 65 illustrates the output characteristics for a
few values of RCLMP.
–3 –2
V
INH
(V)
V
OH
, V
OL
(V)
0–1
0.5
213
1.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
0
5.0
8.8k
Ω
3.5k
Ω
R
CLMP
=
∞
R
CLMP
= 1.86k
Ω
03199-C-065
Figure 65. Output Clamping Characteristics
AD8331/AD8332
Rev. C | Page 22 of 32
APPLICATIONS
LNA – EXTERNAL COMPONENTS
The LMD pin (connected to the bias circuitry) must be
bypassed to ground, and signal source to the INH pin
capacitively coupled using 2.2 nF to 0.1 μF capacitors (see
Figure 66).
The unterminated input impedance of the LNA is 6 kΩ. The
user may synthesize any LNA input resistance between 50 Ω
and 6 kΩ. RFB is calculated according to Equation 6 or selected
from Table .
()
()
()
6
–Ω6
×Ω33
=
IN
IN
FB Rk
Rk
R
Table 3. LNA External Component Values
for Common Source Impedances
RIN (Ω) RFB (Nearest STD 1% Value, Ω) CSH (pF)
50 280 22
75 412 12
100 562 8
200 1.13k 1.2
500 3.01k None
6k ∞ None
When active input termination is used, a 0.1 µF capacitor (CFB) is
required to isolate the input and output bias voltages of the LNA.
The shunt input capacitor, CSH, reduces gain peaking at higher
frequencies where the active termination match is lost due to
the HF gain roll-off of the LNA. Suggested values are shown in
Table ; for unterminated applications, reduce the capacitor value
by half.
When a long trace to Pin INH is unavoidable, or if both LNA
outputs drive external circuits, a small ferrite bead (FB) in series
with Pin INH preserves circuit stability with negligible effect on
noise. The bead shown is 75 Ω at 100 MHz (Murata BLM21 or
equivalent). Other values may prove useful.
Figure 67 shows the interconnection details of the LNA output.
Capacitive coupling between LNA outputs and the VGA inputs
is required because of differences in their dc levels and to
eliminate the offset of the LNA. Capacitor values of 0.1 µF are
recommended. There is 0.4 dB loss in gain between the LNA
output and the VGA input due to the 5 Ω output resistance.
Additional loading at the LOP and LON outputs will affect
LNA gain.
21
22
23
24
28
25
26
27
15
16
20
17
18
19
8
7
6
5
1
4
3
2
14
13
9
12
11
10
VCM2
RCLMP
COMM
VOL2
VOH2
VIP2
GAIN
VIN2
LOP2
COM2
LMD2
LON2
VPS2
INH2
COM1
LOP1
LMD1
LON1
VPS1
INH1
VOH1
ENB
VIP1
VCM1
VIN1
VPSV
VOL1
HILO
0.1 F
C
FB
*
CLMD
0.1µF
1nF
5V
5V
1nF
R
FB
*
5V
+5V
C
SH
*
*
*
LNA
SOURCE
VGA OUT
VGA OUT
5V
1nF
0.1µF
*
SEE TEXT
LNA OUT
1nF
V
GAIN
FB
1nF
0.1µF
0.1µF
0.1µF
0.1µF
1nF
0.1µF
03199-C-066
Figure 66. Basic Connections for a Typical Channel (AD8332 Shown)
50Ω
LNA
VIN
VIP
LOP
VCM 100Ω
5Ω
LON
TO EXT
CIRCUIT
TO EXT
CIRCUIT
C
SH
5Ω
50Ω
100Ω
03199-C-067
Figure 67. Interconnections of the LNA and VGA
Both LNA outputs are available for driving external circuits. Pin
LOP should be used in those instances when a single-ended
LNA output is required. The user should be aware of stray
capacitance loading of the LNA outputs, in particular LON. The
LNA can drive 100 Ω in parallel with 10 pF. If an LNA output is
routed to a remote PC board, it will tolerate a load capacitance
up to 100 pF with the addition of a 49.9 Ω series resistor or
ferrite 75 Ω/100 MHz bead.
AD8331/AD8332
Rev. C | Page 23 of 32
Gain Input
Pin GAIN is common to both channels of the AD8332. The
input impedance is nominally 10 MΩ and a bypass capacitor
from 100 pF to1 nF is recommended.
Parallel connected devices may be driven by a common voltage
source or DAC. Decoupling should take into account any
bandwidth considerations of the drive waveform, using the total
distributed capacitance.
If gain control noise in LO gain mode becomes a factor,
maintaining ≤15 nV/√Hz noise at the GAIN pin will ensure
satisfactory noise performance. Internal noise prevails below
15 nV/√Hz at the GAIN pin. Gain control noise is negligible in
HI gain mode.
VCM Input
The common-mode voltage of Pins VCM, VOL, and VOH
defaults to 2.5 Vdc. With output ac-coupled applications, the
VCM pin will be unterminated; however, it must still be
bypassed in close proximity for ac grounding of internal
circuitry. The VGA outputs may be dc connected to a
differential load, such as an ADC. Common-mode output
voltage levels between 1.5 V and 3.5 V may be realized at Pins
VOH and VOL by applying the desired voltage at Pin VCM.
DC-coupled operation is not recommended when driving loads
on a separate PC board.
The voltage on the VCM pin is sourced by an internal buffer
with an output impedance of 30 Ω and a ±2 mA default output
current (see Figure 68). If the VCM pin is driven from an
external source, its output impedance should be <<30 Ω and its
current drive capability should be >>2 mA. If the VCM pins of
several devices are connected in parallel, the external buffer
should be capable of overcoming their collective output
currents. When a common-mode voltage other than 2.5 V is
used, a voltage-limiting resistor, RCLMP, is needed to protect
against overload.
V
CM
NEW V
CM
R
O
<< 30Ω
100pF
2mA MAX
30Ω
0.1µF
INTERNAL
CIRCUITRY
AC GROUNDING FOR
INTERNAL CIRCUITRY
03199-B-068
Figure 68. VCM Interface
Logic Inputs—ENB, MODE, and HILO
The input impedance of all enable pins is nominally 25 kΩ and
may be pulled up to 5 V (a pull-up resistor is recommended) or
driven by any 3 V or 5 V logic families. The enable pins perform
a power-down function, when disabled, the VGA outputs are
near ground. Multiple devices may be driven from a common
source. Consult the pin-function tables for circuit functions
controlled by the enable pins.
Pin HILO is compatible with 3 V or 5 V CMOS logic families. It
is either connected to ground or pulled up to 5 V, depending on
the desired gain range and output noise.
Optional Output Voltage Limiting
The RCLMP pin provides the user with a means to limit the
output voltage swing when used with loads that have no
provisions for prevention of input overdrive. The peak-to-peak
limited voltage is adjusted by a resistor to ground, and Table
lists several voltage levels and the corresponding resistor value.
Unconnected, the default limiting level is 4.5 V p-p.
Note that third harmonic distortion will increase as waveform
amplitudes approach clipping. For lowest distortion, the clamp
level should be set higher than the converter input span. A
clamp level of 1.5 V p-p is recommended for a 1 V p-p linear
output range, 2.7 V p-p for a 2 V p-p range, or 1 V p-p for a
0.5 V p-p operation. The best solution will be determined
experimentally. Figure 69 shows third harmonic distortion
as a function of the limiting level for a 2 V p-p output signal.
A wider limiting level is desirable in HI gain mode.
HD3(dBc)
5.0
–50
–40
–30
–80
–70
–60
2.0 3.51.5 3.02.5 4.0 4.5
–20
CLAMP LIMIT LEVEL (V p-p)
V
GAIN
= 0.75V
HILO = HI
HILO = LO
03199-C-069
Figure 69. HD3 vs. Clamping Level for 2 V p-p Differential Input
AD8331/AD8332
Rev. C | Page 24 of 32
Table 4. Clamp Resistor Values
Clamp Resistor Value (kΩ) Clamp Level
(V p-p) HILO = LO HILO = HI
0.5 1.21
1.0 2.74 2.21
1.5 4.75 4.02
2.0 7.5 6.49
2.5 11 9.53
3.0 16.9 14.7
3.5 26.7 23.2
4.0 49.9 39.2
4.4 100 73.2
Output Filtering and Series Resistor
Requirements
To ensure stability at the high end of the gain control range,
series resistors or ferrite beads are recommended for the
outputs when driving large capacitive loads, or circuits on other
boards,. These components can be part of the external
noise filter.
Recommended resistor values are 84.5 Ω for LO gain mode and
100 Ω for HI gain mode (see Figure 66) and are placed near
Pins VOH and VOL. Lower value resistors are permissible for
applications with nearby loads or with gains less than 40 dB.
Lower values are best selected empirically.
An antialiasing noise filter is typically used with an ADC. Filter
requirements are application dependent.
When the ADC resides on a separate board, the majority of
filter components should be placed nearby to suppress noise
picked up between boards and mitigates charge kickback from
the ADC inputs. Any series resistance beyond that required for
output stability should be placed on the ADC board. Figure 70
shows a second order low-pass filter with a bandwidth of
20 MHz. The capacitor is chosen in conjunction with the 10 pF
input capacitance of the ADC.
18pF
OPTIONAL
BACKPLANE
84.5Ω
0.1µF
0.1µF
1.5µH
1.5µH
158Ω
158Ω84.5ΩADC
Figure 70. 20 MHz Second-Order Low-Pass Filter
DRIVING ADCS
The output drive will accommodate a wide range of ADCs. The
noise floor requirements of the VGA will depend on a number
of application factors, including bit resolution, sampling rate,
full-scale voltage, and the bandwidth of the noise/antialias filter.
The output noise floor and gain range can be adjusted by
selecting HI or LO gain mode.
The relative noise and distortion performance of the two gain
modes can be compared in Figure 21 and Figure 27 through
Figure 37. The 48 nV/√Hz noise floor of the LO gain mode is
suited to converters with higher sampling rates or resolutions
(such as 12 bits). Both gain modes can accommodate ADC full-
scale voltages as high as 4 V p-p. Since distortion performance
remains favorable for output voltages as high as 4 V p-p (see
Figure 32), it is possible to lower the output-referred noise even
further by using a resistive attenuator (or transformer) at the
output. The circuit in Figure 71 has an output full-scale range of
2 V p-p, a gain range of –10.5 dB to +37.5 dB, and an output
noise floor of 24 nV/√Hz, making it suitable for some 14-bit
ADC applications.
VOH
VOL
LPF
4V p-p DIFF,
48n V/
187Ω
2V p-p DIFF,
24n V/
2:1 374Ω
HZ
187Ω
ADC
AD6644
HZ
03199-C-071
Figure 71. Adjusting the Noise Floor for 14-Bit ADCs
OVERLOAD
These devices respond gracefully to large signals that overload
its input stage and to normal signals that overload the VGA
when the gain is set unexpectedly high. Each stage is designed
for clean-limited overload waveforms and fast recovery when
gain setting or input amplitude is reduced.
Signals larger than ±275 mV at the LNA input are clipped to
5 V p-p differential prior to the input of the VGA. Figure 44
shows the response to a 1 V p-p input burst. The symmetric
overload waveform is important for applications, such as CW
Doppler ultrasound, where the spectrum of the LNA outputs
during overload is critical. The input stage is also designed to
accommodate signals as high as ±2.5 V without triggering the
slow-settling ESD input protection diodes.
Both stages of the VGA are susceptible to overload. Postamp
limiting is more common and results in the clean-limited
output characteristics found in Figure 45. Under more extreme
conditions, the X-AMP will overload, causing the minor glitches
evident in Figure 46. Recovery is fast in all cases. The graph in
Figure 72 summarizes the combinations of input signal and
gain that lead to the different types of overload.
AD8331/AD8332
Rev. C | Page 25 of 32
GAIN (dB)
1m
LO GAIN
MODE
15mV
–4.5
25mV
LNA OVERLOAD
X-AMP
OVERLOAD
POSTAMP
OVERLOAD X-AMP
OVERLOAD
POSTAMP
OVERLOAD
29dB
43.5
INPUT AMPLITUDE (V)
.2750.110m
24.5dB
GAIN (dB)
HI GAIN
MODE
4mV
7.5
25mV
LNA OVERLOAD
41dB
56.5
INPUT AMPLITUDE (V)
24.5dB
11m 0.2750.110m 1
03199-C-072
Figure 72. Overload Gain and Signal Conditions
The previously mentioned clamp interface controls the
maximum output swing of the postamp and its overload
response. When no RCLMP resistor is provided, this level defaults
to near 4.5 V p-p differential to protect outputs centered at a
2.5 V common mode. When other common-mode levels are set
through the VCM pin, the value of RCLMP should be chosen for
graceful overload. A value of 8.3 kΩ or less is recommended for
1.5 V or 3.5 V common-mode levels (7.2 kΩ for HI gain mode).
This limits the output swing to just above 2 V p-p diff.
OPTIONAL INPUT OVERLOAD PROTECTION.
Applications in which high transients are applied to the LNA
input may benefit from the use of clamp diodes. A pair of back-
to-back Schottky diodes can reduce these transients to
manageable levels. Figure 73 illustrates how such a diode-
protection scheme may be connected.
20
19
4
3
2
LON
VPS
INH
COMM
ENBL
0.1µF
C
SH
FB
C
FB
BAS40-04
R
SH
R
FB
2
3
1
OPTIONAL
SCHOTTKY
OVERLOAD
CLAMP
03199-C-072
Figure 73. Input Overload Clamping
When selecting overload protection, the important parameters
are forward and reverse voltages and trr (or τrr.). The Infineon
BAS40 series shown in Figure 73 has a τrr of 100 ps and VF of
310 mV at 1 mA. Many variations of these specifications can be
found in vendor catalogs.
LAYOUT, GROUNDING, AND BYPASSING
Due to their excellent high frequency characteristics, these
devices are sensitive to their PCB environment. Realizing
expected performance requires attention to detail critical to
good high speed board design.
A multilayer board with power and ground plane is
recommended, and unused area in the signal layers should be
filled with ground. The multiple power and ground pins provide
robust power distribution to the device and must all be
connected. The power supply pins should each be with multiple
values of high frequency ceramic chip capacitors to maintain
low impedance paths to ground over a wide frequency range.
These should have capacitance values of 0.01 μF to 0.1 μF in
parallel with 100 pF to 1 nF, and be placed as close as possible to
the pins. The LNA power pins should be decoupled from the
VGA using ferrite beads. Together with the decoupling
capacitors, ferrite beads help eliminate undesired high
frequencies without reducing the headroom, as do small value
resistors.
Several critical LNA areas require special care. The LON and
LOP output traces must be as short as possible before
connecting to the coupling capacitors connected to Pins VIN
and VIP. RFB must be placed nearby the LON pin as well.
Resistors must be placed as close as possible to the VGA output
pins VOL and VOH to mitigate loading effects of connecting
traces. Values are discussed in the section entitled Output
Filtering and Series Resistor
Requirements.
Signal traces must be short and direct to avoid parasitic effects.
Wherever there are complementary signals, symmetrical layout
should be employed to maintain waveform balance. PCB traces
should be kept adjacent when running differential signals over a
long distance.
MULTIPLE INPUT MATCHING
Matching of multiple sources with dissimilar impedances can
be accomplished as shown in the circuit of Figure 75. A relay
and low supply voltage analog switch may be used to select
between multiple sources and their associated feedback
resistors. An ADG736 dual SPDT switch is shown in this
example; however, multiple switches are also available and users
are referred to the Analog Devices Selection Guide for switches
and multiplexers.
DISABLING THE LNA
Where accessible, connection of the LNA enable pin to ground
will power down the LNA, resulting in a current reduction of
about half. In this mode, the LNA input and output pins may be
left unconnected, however the power must be connected to all
the supply pins for the disabling circuit to function. Figure 74
illustrates the connections using an AD8331 as an example.
AD8331/AD8332
Rev. C | Page 26 of 32
15
16
20
17
18
19
8
7
6
5
1
4
3
2
9
13
10
COMM
VIP
LOP
COML
LMD
LON
VPS
INH
COMM
ENBV
ENBL
GAIN
0.1µF
HILO
+5V
+5V
C
FB
0.018µF
NC
VOH
VOL
VOUT
VPOS +5V
14
11
12
VCM
R
CLMP
NC
NC
NC
VIN
0.1µF
AD8331
MODE
03199-C-074
GAIN
MODE
VCM
CLMP
HILO
VIN
Figure 74. Disabling the LNA
INH
LNA
5Ω
LMD LOP
ADG736
LON
200Ω
50Ω0.1µF
18nF
SELECTR
FB
280Ω
1.13kΩ
AD8332
03199-C-075
5Ω
Figure 75. Accommodating Multiple Sources
MEASUREMENT CONSIDERATIONS
Figure 51 through Figure 55 show typical measurement
configurations and proper interface values for measurements
with 50 Ω conditions.
Short-circuit input noise measurements are made using
Figure 53. The input-referred noise level is determined by
dividing the output noise by the numerical gain between Point
A and Point B and accounting for the noise floor of the
spectrum analyzer. The gain should be measured at each
frequency of interest and with low signal levels since a 50 Ω
load is driven directly. The generator is removed when noise
measurements are made.
ULTRASOUND TGC APPLICATION
The AD8332 ideally meets the requirements of medical and
industrial ultrasound applications. The TGC amplifier is a key
subsystem in such applications, since it provides the means for
echolocation of reflected ultrasound energy.
Figure 76 through Figure 78 are schematics of a dual, fully
differential system using the AD8332 and AD9238 12-bit high
speed ADC with conversion speeds as high as 65 MSPS. In this
example, the VGA outputs are dc-coupled, using the reference
output of the ADC and a level shifter to center the common-
mode output voltage to match that of the converter. Consult the
data sheet of the converter to determine whether external CMV
biasing is required. AC coupling is recommended if the CMV
of the VGA and ADC are widely disparate.
Using the circuit shown, and a high speed ADC FIFO
evaluation kit connected to a laptop PC, an FFT can be
performed on the AD8332. With the on-board clock of 20 MHz,
and minimal low-pass filtering, and both channels driven with a
1 MHz filtered sine wave, the THD is –75 dB, noise floor –93 dB
and HD2 –83 dB.
AD8331/AD8332
Rev. C | Page 27 of 32
TB1
+5V
TB2
GND
C46
1µF+5VLNA
+5VGA
L7
120nH FB
L6
120nH FB
TP4
(BLACK)
TP3
(RED)
VOH1
21
25
VIN1
LON1
C78
1nF
C58
0.1µF
17
AD8332ARU
VIN+A
1LMD2
C49
0.1µF
2INH2
C80
22PF
3VPS2
CFB1
18nF
C59
0.1µF
C41
0.1µFC74
1nF
4LON2
7
5
VIP2
LOP2
C53
0.1µF
VPS1 26
COM2
6COM1 23
8VIN2
C51
0.1µF
27
INH1 S1
EIN1
C60
0.1µF
C79
22 PF
L13
120nH FB
TP6
28
LMD1 C70
0.1µF
COM
14
9VCM2
C48
0.1µF
10 GAIN
C83
1nF
11 CLMP
R3
(RCLMP)
C54
0.1µF
VOH2
12
VIN+B
C55
0.1µF
VOL2
13
JP12 VPSV 15
C45
0.1µFC85
1nF
VOL1
C56
0.1µF
16
L8
120nF FB
18
ENB
+5VGA
19
HILO
20
VCM1 C43
0.1µF
C77
1nF
22
24
VIP1
LOP1
+5VLNA
VCM1
0.1µF
AD8541
VCM
R22
1kΩ
R23
2kΩ
7
6
3
2
100Ω
RFB1
274Ω
RFB2
274Ω
VREF
C50
0.1µF
S3
EIN2
L12
120nH FB
TP5
CFB2
18nF
C71 1nF
C68
1nF
C69
0.1µF
R27
100Ω
L11
120nH FB
JP8
DC2H
L10
120nH FB
JP7
DC2L R26
+5VGA
ENABLE
HI GAIN
DISABLE
LO GAIN
L9
120nH FB
R24
100ΩJP9
JP10
JP17
TP2 GAIN
JP5
IN2 JP6
IN1
TP7 GND
L17
SAT
L18
SAT
L19
SAT
L20
SAT
C67
SAT
C66
SAT
L1
SAT
L14
SAT
L15
SAT
L16
SAT
C64
SAT C65
SAT
OPTIONAL 4-POLE LOW-PASS
FILTER
OPTIONAL 4-POLE LOW-PASS
FILTER
JP14
JP13
VCM1
4
+5VGA
JP10
JP16
R25
100Ω
+
+5VLNA
+5V
V
IN–B
C42
0.1µF
VIN–A
03199-C-076
Figure 76. Schematic, TGC, VGA Section
AD8331/AD8332
Rev. C | Page 28 of 32
VREF
VIN+_A
VIN –_A
VIN –_B
VIN+_B
MUX_SELECT
1
2
3
17
AVDD
62
SHARED_REF
6
7
REFT_A
REFB_A
SENSE
11
10
REFT_B
REFB_B
14
15
CLK_A
18
CLK_B
63
DCS
19
DFS
20
PDWN_B
PDWN_A
60
21
OEB_B
22
16
4
13
AGND
AGND
64
12
5
AVDD
AVDD
AVDD
8
9
AGND
AGND
D5_B
D4_B
D3_B
DRGND
D2_B
D1_B
D0_B
DNC
DNC
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
DRVDD
D10_A
D11_A
OTRA_A
D11_A(MSB)
DRGND
D8_A
DRVDD
D7_A
D6_A
D5_A
D4_A
D3_A
D2_A
D1_A
D0_A
DRVDD
D10_A
DRGND
OTRB_B
61
D9_A
59
58
57
56
55
54
53
OTR_A
U1 A/D CONVERTER AD9238
D9_A
D8_A
D6_A
D7_A
D5_A
D4_A
D3_A
D2_A
D1_A
D0_A
DNC
DNC
D4_B
D3_B
D2_B
D1_B
D0_B
DNC
DNC
OTR_B
D11_B
D10_B
D9_B
D8_B
D7_B
D6_B
D5_B
20MHz
ADCLK
+3.3VCLK
ADCLK
+3.3VAVDD
V
IN
–B
V
IN
+B
+
+3.3VADDIG
SG-636PCE
14
3
2
U5
74VHC04
+
+
TP 9
TP 12
4312
1213
10
11
U5
74VHC04
U5
74VHC04
U5
74VHC04
U5
74VHC04
U5
74VHC04
SPARES
8965
TP 13
JP 1
3
2
1
V
DD
OUT
GND
OE
JP 4
S2
EXT CLOCK
+
JP 11JP 3
JP 2
SHARED
REF
+3.3VADDIG
Y
D10_B
D9_B
D8_B
D7_B
D6_B
D11_B(MSB)
DNC
DNC
OEB_A
EXT
INT
V
IN
+_A
V
IN
–_A N
DATA
CLK
VREF
C11
10µF
6.3V
C14
0.1µF
C23
0.1µFC25
1nF
R14
4.7kΩ
R11
100Ω
R10
0Ω
R15
0Ω
C22
0.1µFC21
1nF
C86
0.1µFC47
10µF
6.3V ADCLK
C2
10µF
6.3V
C18
1nF
C17
0.1µF
C52
10nF
C57
10nF
C61
18pF
C40
0.1µF
R5
33Ω
R6
33Ω
R4
1.5kΩ
R12
1.5kΩ
1.5kΩ1.5kΩ
C12
10µF
6.3V
R9
0Ω
R8
33Ω
R7
33Ω
C19
1nF
C20
0.1µF
C63
0.1µF
C26
0.1µFC24
1nF
C33
10µF
6.3V
C38
0.1µF
C16
0.1µF
C62
18pF
C15
1nF
C35
0.1µF
C36
0.1µF
C37
0.1µF
R20
4.7kΩ
R17
49.9Ω
R41
4.7kΩ
+3.3VCLK
R19
499Ω
R16
5kΩ
R18
499Ω
+
+3.3VADDIG
3
2
1
C32
0.1µF
C39
10µF
C34
10µF
6.3V
C44
1µF
C31
0.1µ
F
C30
0.1µ
F
C29
0.1µ
F
C1
0.1
µ
F
OUT
VR1
ADP3339AKC-3.3
L2
120nH FB
L3
120nH FB
L4
120nH FB
L5
120nH FB
IN
OUT
GND
312
TAB
+
+5V
03199-C-077
C13
1nF
+3.3VCLK
+3.3VADDIG
+3.3VAVDD
+3.3VDVDD
U6
Figure 77. Converter Schematic
AD8331/AD8332
Rev. C | Page 29 of 32
19
1
D10_A
D11_A
24
39
VCC
GND
Y1
A1
G1
1
2
3
6
7
10
4
5
8
9
17
11
14
15
18
19
20 +
16
13
12
G2
A8
A7
A6
A5
A4
A3
A2
Y8
Y7
Y6
Y5
Y4
Y3
Y2
VCC
GND
Y1
A1
G1
1
2
3
6
7
10
4
5
8
9
17
11
14
15
18
19
20 +
16
13
12
G2
A8
A7
A6
A5
A4
A3
A2
Y8
Y7
Y6
Y5
Y4
Y3
Y2
VCC
GND
Y1
A1
G1
1
2
3
6
7
10
4
5
8
9
17
11
14
15
18
19
20 ++
16
13
12
G2
A8
A7
A6
A5
A4
A3
A2
Y8
Y7
Y6
Y5
Y4
Y3
Y2
VCC
GND
Y1
A1
G1
1
2
3
6
7
10
4
5
8
9
17
11
14
15
18
19
20 +
16
13
12
G2
A8
A7
A6
A5
A4
A3
A2
Y8
Y7
Y6
Y5
Y4
Y3
Y2
2
3
6
7
10
4
5
8
9
17
11
14
15
18
20
16
13
12
37
21
26 25
30
22
23
28 27
35
29
34 33
38
40
36
3132
R39
22Ω
DATACLKA
OTR_A
D9_A
D8_A
D6_A
D7_A
D5_A
D4_A
D3_A
D2_A
D1_A
D0_A
DNC
DNC
OTR_B
D11_B
D10_B
D9_B
D8_B
D7_B
D6_B
D5_B
D4_B
D3_B
D2_B
D1_B
D0_B
DNC
DNC
+3.3VDVDD
+3.3VDVDD
+3.3VDVDD
DATACLK
U3
74VHC541
U10
74VHC541
U7
74VHC541
U2
74VHC541
SAM080UPM
76
61
79
58
41
80
77
73
72
78
75
74
71
63
69
68
65
64
62
66
67
70
43
59
56 55
52
60
57
54 53
45
51
48 47
44
42
46
4950
SAM080UPM
RP 9
18
7
6
54
3
2
18
7
6
54
3
2
18
7
6
54
3
2
18
7
6
54
3
2
18
7
6
54
3
2
18
7
6
54
3
2
7
6
54
3
2
18
7
6
54
3
2
RP 11
RP 12
RP 13
RP 14
18
RP 15
RP 16
R40
22Ω
18
7
6
54
3
2RP 1
18
7
6
54
3
2RP2
18
7
6
54
3
2RP 3
18
7
6
54
3
2RP 4
18
7
6
54
3
2RP 5
18
7
6
54
3
2RP 6
18
7
6
54
3
2RP 7
18
7
6
54
3
2RP 8
22× 4
22× 4
RP 10
22 ×4
22× 4
22× 4
22× 4
22× 4
22× 4
HEADER UP MALE NO SHROUDHEADER UP MALE NO SHROUD
C3
0.1µFC28
10µF
6.3V
C8
0.1µFC10
0.1µFC76
10µF
6.3V
C7
0.1µFC9
0.1µFC27
10µF
6.3V
C4
0.1µFC5
0.1µFC6
0.1µFC75
10µF
6.3V
+3.3VDVDD
22× 4
22× 4
22× 4
22× 4
22× 4
22× 4
22× 4
22× 4
03199-B-078
Figure 78. Interface Schematic
AD8331/AD8332
Rev. C | Page 30 of 32
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD8331
MODE RCLMP
VIP
GAIN
VIN
LOP
COML
LMD
LON
VPSL
INH
COMM
VOH
ENBV
VCM
VPOS
VOL
HILO
ENBL
COMM
03199-C-079
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
PIN 1
IDENTIFIER
AD8331
TOP VIEW
(Not to Scale)
Figure 79. 20-Lead QSOP
Table 5. 20–Lead QSOP (RQ PACKAGE)
Pin No. Name Description
1 LMD LNA Signal Ground
2 INH LNA Input
3 VPSL LNA 5V Supply
4 LON LNA Inverting Output
5 LOP LNA Noninverting Output
6 COML LNA Ground
7 VIP VGA Noninverting Input
8 VIN VGA Inverting Input
9 MODE Gain Slope Logic Input
10 GAIN Gain Control Voltage
11 VCM Common-Mode Voltage
12 CLMP Output Clamping Level
13 HILO Gain Range Select (HI or LO)
14 VPOS VGA 5 V Supply
15 VOH Noninverting VGA Output
16 VOL Inverting VGA Output
17 COMM VGA Ground
18 ENBV VGA Enable
19 ENBL LNA Enable
20 COMM VGA Ground
AD8331/AD8332
Rev. C | Page 31 of 32
AD8332
COM1
LOP1
LMD1
LON1
VPS1
INH1
VOH1
ENB
VIP1
VCM1
VIN1
VPSV
VOL1
HILO
VCM2
RCLMP
COMM
VOL2
VOH2
VIP2
GAIN
VIN2
LOP2
COM2
LMD2
LON2
VPS2
INH2
03199-B-081
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PIN 1
IDENTIFIER
AD8332
TOP VIEW
(Not to Scale)
Figure 80. 28-Lead TSSOP
Table 6. 28–Lead TSSOP (AR PACKAGE)
Pin No. Name Description
1 LMD2 CH2 LNA Signal Ground
2 INH2 CH2 LNA Input
3 VPS2 CH2 Supply LNA 5 V
4 LON2 CH2 LNA Inverting Output
5 LOP2 CH2 LNA Noninverting Output
6 COM2 CH2 LNA Ground
7 VIP2 CH2 VGA Noninverting Input
8 VIN2 CH2 VGA Inverting Input
9 VCM2 CH2 Common-Mode Voltage
10 GAIN Gain Control Voltage
11 RCLMP Output Clamping Resistor
12 VOH2 CH2 Noninverting VGA Output
13 VOL2 CH2 Inverting VGA Output
14 COMM VGA Ground (Both Channels)
15 VPSV VGA Supply 5 V (Both Channels)
16 VOL1 CH1 Inverting VGA Output
17 VOH1 CH1 Noninverting VGA Output
18 ENB Enable—VGA/LNA
19 HILO VGA Gain Range Select (HI or LO)
20 VCM1 CH1 Common-Mode Voltage
21 VIN1 CH1 VGA Inverting Input
22 VIP1 CH1 VGA Noninverting Input
23 COM1 CH1 LNA Ground
24 LOP1 CH1 LNA Noninverting Output
25 LON1 CH1 LNA Inverting Output
26 VPS1 CH1 LNA Supply 5 V
27 INH1 CH1 LNA Input
28 LMD1 CH1 LNA Signal Ground
AD8332
TOP VIEW
(Not to Scale)
LMD2
LON2
VPS2
INH2
LMD1
LON1
VPS1
INH1
VIP2
VIN2
LOP2
COM2
14139 1211
10
RCLMP
GAIN
15 16
VCM2
MODE
COMM
VOL2
VOH2
20
17
18
19
VOH1
VOL1
21
22
23
24
NC
VPSV
COMM
2930
3132 28 252627
COM1
LOP1
VIP1
VIN1
HILO
ENBL
VCM1
ENBV
03199-C-082
1
2
3
4
5
6
7
8
PIN 1
INDICATOR
Figure 81. 32-Lead LFCSP
Table 7. 32–Lead LFCSP (AC PACKAGE)
Pin No. Name Description
1 LON1 CH1 LNA Inverting Output
2 VPS1 CH1 LNA Supply 5 V
3 INH1 CH1 LNA Input
4 LMD1 CH1 LNA Signal Ground
5 LMD2 CH2 LNA Signal Ground
6 INH2 CH2 LNA Input
7 VPS2 CH2 LNA Supply 5 V
8 LON2 CH2 LNA Inverting Output
9 LOP2 CH2 LNA Noninverting Output
10 COM2 CH2 LNA Ground
11 VIP2 CH2 VGA Noninverting Input
12 VIN2 CH2 VGA Inverting Input
13 VCM2 CH2 Common-Mode Voltage
14 MODE Gain Slope Logic Input
15 GAIN Gain Control Voltage
16 RCLMP Output Clamping Level Input
17 COMM VGA Ground
18 VOH2 CH2 Noninverting VGA Output
19 VOL2 CH2 Inverting VGA Output
20 NC Not Connected
21 VPSV VGA Supply 5 V
22 VOL1 CH1 Inverting VGA Output
23 VOH1 CH1 Noninverting VGA Output
24 COMM VGA Ground
25 ENBV VGA Enable
26 ENBL LNA Enable
27 HILO VGA Gain Range Select (HI or LO)
28 VCM1 CH1 Common-Mode Voltage
29 VIN1 CH1 VGA Inverting Input
30 VIP1 CH1 VGA Noninverting Input
31 COM1 CH1 LNA Ground
32 LOP1 CH1 LNA Noninverting Output
AD8331/AD8332
Rev. C | Page 32 of 32
OUTLINE DIMENSIONS
28 15
141
8°
0°
COMPLIANT TO JEDEC STANDARDS MO-153AE
SEATING
PLANE
COPLANARITY
0.10
1.20 MAX
6.40 BSC
0.65
BSC
PIN 1
0.30
0.19 0.20
0.09
4.50
4.40
4.30
0.75
0.60
0.45
9.80
9.70
9.60
0.15
0.05
Figure 82. 28-Lead Thin Shrink Small Outline Package [TSSOP] (RU-28)
Dimensions shown in millimeters
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
0.30
0.23
0.18 0.20 REF
0.80 MAX
0.65 TYP
0.05 MAX
0.02 NOM
12° MAX
1.00
0.85
0.80 SEATING
PLANE
COPLANARITY
0.08
1
32
8
9
25
24
16
17
BOTTOM
VIEW
0.50
0.40
0.30
3.50 REF
0.50
BSC 3.25
3.10 SQ
2.95
0.60 MAX
0.60 MAX
0.25MIN
TOP
VIEW
PIN 1
INDICATOR
PIN 1
INDICATOR
5.00
BSC SQ
4.75
BSC SQ
Figure 83. 32-Lead Frame Chip Scale Package [LFCSP] (CP-32)
Dimensions shown in millimeters
20 11
10
1
PIN 1
8°
0°
0.236
BSC
0.154
BSC
0.010
0.004 0.012
0.008
0.025
BSC
C
OPLANARIT
Y
0.004
0.065
0.049 0.069
0.053
SEATING
PLANE 0.010
0.006
0.050
0.016
0.341
BSC
COMPLIANT TO JEDEC STANDARDS MO-137AD
Figure 84. 20 Lead Shrink Outline [QSOP] (RQ-20)
Dimensions shown in millimeters
ORDERING GUIDE
AD8331/AD8332
Models
Temperature Range
Package Description
Package Outline
AD8331ARQ –40°C to +85°C Shrink Small Outline Package 150 mil Body, 25 mil pitch RQ-20
AD8331ARQ-REEL –40°C to +85°C Shrink Small Outline Package 150 mil Body, 25 mil pitch RQ-20
AD8331ARQ-REEL7 –40°C to +85°C Shrink Small Outline Package 150 mil Body, 25 mil pitch RQ-20
AD8331-EVAL Evaluation Board with AD8331ARQ
AD8332ARU –40°C to +85°C Thin Shrink Small Outline Package (TSSOP) RU-28
AD8332ARU-REEL –40°C to +85°C Thin Shrink Small Outline Package (TSSOP) RU-28
AD8332ARU-REEL7 –40°C to +85°C Thin Shrink Small Outline Package (TSSOP) RU-28
AD8332ACP-REEL –40°C to +85°C Lead Frame Chip Scale Package (LFCSP) CP-32
AD8332ACP-REEL7 –40°C to +85°C Lead Frame Chip Scale Package (LFCSP) CP-32
AD8332-EVAL Evaluation Board with AD8332ARU
© 2003 Analog Devices, Inc. All rights reserved. Trademarks
and registered trademarks are the property of their respective owners.
C03199-0-11/03(C)
