DATASHEET
VALUE-LINE TWO-CHANNEL AC’97 CODECS STAC9750/9751
IDT™
1 STAC9750/9751 V 5.8 103106
VALUE-LI NE TWO-CHANNEL AC’97 CODECS
OVERVIEW
Value-Line Stereo AC'97 CODECs with headphone drive
and SPDI F outputs.
FEATURES
• Full Duplex Stereo 18-bit ADCs and 20-bit DACs
• AC’97 Rev 2.2 Compliant
• High Performance Σ∆ Technology
• SPDIF Output
• Crystal Elimination Circuit
• Headphone amplifier
• Independent Sample Rates for ADCs & DACs
(hardware SRCs)
• 20dB or 30dB Microphone Boost Capability
• 90dB SNR LINE-LINE
• 5-Wire AC-Link Protocol Compliance
• Digital-Ready Architecture
• General Purpose I/O
• +3.3 V (STAC9751) and +5 V (STAC9750) Analog
Power Supply Options
• Pin Compatible With STAC9700/21/56/66
• IDT Surround (SS3D) Stereo Enhancement
• Energy Saving Dynamic Power Modes
KEY SPECIFICATIONS
• Analog LINE_OUT SNR: 90dB
• Digital DAC SNR: 89dB
• Digital ADC SNR: 85dB
• Full-scale Total Harmonic Distortion: 0.005%
• Crosstalk between Input Channels: -70dB
• Spurious Tone Rejection: 100dB
RELATED MATERIALS
• Data Sheet
• Reference Designs for MB, CNR, ACR and PCI
applications
• Audio Precision Performance Plots
DESCRIPTION
IDT's STAC9750/9751 are general purpose, full duplex,
audio CODECs conforming to the analog component spec-
ification of AC'97 (Audio CODEC 97 Component Specifica-
tion Rev. 2.2). They have 18-bit ADCs and 20-bit DACs.
The STAC9750/9751 incorporate IDT's proprietary Σ∆ tech-
nology to achieve a DAC SNR in excess of 89dB.
The DACs, ADCs and mixer are integrated with analog I/
Os, which include four analog line-level stereo inputs, two
analog line-level mono inputs, two stereo outputs, and one
mono output channel.
The STAC9750/9751 include digital input/output capability
for support of modern PC systems and also an output that
supports the SPDIF format.
The STAC9750/9751 is a standard 2-channel stereo
CODEC. With IDT’s headphone drive capability, head-
phones can be driven with no external amplifier.
The STAC9750/9751 may be used as a secondary
CODEC, with the STAC9700/21/44/56/08/84/66 as the pri-
mar y, in a mult ip l e CO DEC co n fig u rat i o n co n for m i ng t o t h e
AC'97 Rev . 2.2 specification. This configuration can provide
the true six-channel, AC-3 playback required for DVD appli-
cations.
The STAC9750/9751 communicates via the five-wire
AC-Link to any digital component of AC'97, providing flexi-
bility in the audio system design.
The STAC9750/9751 supports General Purpose Input/Out-
put (GPIO), as well as SPDIF output. These digital I/O
options provide for a number of advanced architectural
implementations, with volume controls and digital mixing
capabilities built directly into the CODEC.
Packaged in an AC'97 compliant 48-pin TQFP, the
STAC9750/9751 can be placed on the motherboard,
daughter boards, PCI, AMR, CNR, or ACR cards.
STAC9750/9751
VALUE-LINE TWO-CHANNEL AC’97 CODECS PC AUDIO
IDT™
2 STAC9750/9751 V 5.8 103106
VALUE-LI NE TWO-CHANNEL AC’97 CODECS
TABLE OF CONTENTS
1. PRODUCT BRIEF ......................................................................................................................5
1.1. Features ............................................................................................................................................5
1.2. Description ........................................................................................................................................5
1.3. STAC9750/9751 Block Diagram ........................................................................................................6
1.4. Key Specifications .............................................................................................................................7
1.5. Related Materials ..............................................................................................................................7
1.6. Additional Support .............................................................................................................................7
2. CHARACTERISTICS/SPECIFICATIONS ..................................................................................8
2.1. Electrical Specifications .....................................................................................................................8
2.2. AC Timing Characteristics ...............................................................................................................15
3. TYPICAL CONNECTION DIAGRAM .......................................................................................19
4. AC-LINK ...................................................................................................................................20
4.1. Clocking ...........................................................................................................................................20
4.2. Reset ...............................................................................................................................................20
5. DIGITAL INTERFACE ..............................................................................................................21
5.1. AC-Link Digital Serial Interface Protocol .........................................................................................21
5.2. AC-Link Low Power Mode ...............................................................................................................29
5.3. Waking up the AC-Link ....................................................................................................................30
6. STAC9750/9751 MIXER ..........................................................................................................31
6.1. Analog Mixer Input ..........................................................................................................................33
6.2. Analog Mixer Output ........................................................................................................................33
6.3. SPDIF Digital Mux ...........................................................................................................................33
6.4. PC Beep Implementation ................................................................................................................33
6.5. Programming Registers ...................................................................................................................34
7. LOW POWER MODES ............................................................................................................56
8. MULTIPLE CODEC SUPPORT ...............................................................................................58
8.1. Primary/Secondary CODEC Selection ............................................................................................58
8.2. Secondary CODEC Register Access Definitions .............................................................................59
9. TESTABILITY ..........................................................................................................................60
10. PIN DESCRIPTION ................................................................................................................61
10.1. Digital I/O .......................................................................................................................................62
10.2. Analog I/O .....................................................................................................................................63
10.3. Filter/References/GPIO .................................................................................................................64
10.4. Power and Ground Signals ...........................................................................................................64
11. ORDERING INFORMATION ..................................................................................................65
12. PACKAGE DRAWINGS .........................................................................................................66
12.1. 48-Pin LQFP ..................................................................................................................................66
13. SOLDER REFLOW PROFILE ...............................................................................................67
13.1. Standard Reflow Profile Data ........................................................................................................67
13.2. Pb Free Process - Package Classification Reflow Temperatures .................................................68
14. APPENDIX A: SPLIT INDEPENDENT POWER SUPPLY OPERATION ..............................69
15. APPENDIX B: PROGRAMMING REGISTERS .....................................................................71
16. REVISION HISTORY .............................................................................................................72
STAC9750/9751
VALUE-LINE TWO-CHANNEL AC’97 CODECS PC AUDIO
IDT™
3 STAC9750/9751 V 5.8 103106
VALUE-LI NE TWO-CHANNEL AC’97 CODECS
LIST OF FIGURES
Figure 1. STAC9750/9751 Block Diagram ......................................................................................................6
Figure 2. Cold Reset Timing .........................................................................................................................15
Figure 3. Warm Reset Timing .......................................................................................................................15
Figure 4. Clocks Timing ................................................................................................................................16
Figure 5. Data Setup and Hold Timing .........................................................................................................17
Figure 6. Signal Rise and Fall Times Timing ................................................................................................17
Figure 7. AC-Link Low Power Mode Timing .................................................................................................18
Figure 8. ATE Test Mode Timing ..................................................................................................................18
Figure 9. STAC9751 Typical Connection Diagram .......................................................................................19
Figure 10. AC-Link to its Companion Controller ...........................................................................................20
Figure 11. AC'97 Standard Bi-directional Audio Frame ................................................................................22
Figure 12. AC-Link Audio Output Frame ......................................................................................................22
Figure 13. Start of an Audio Output Frame ...................................................................................................23
Figure 14. STAC9750/9751 Audio Input Frame ...........................................................................................26
Figure 15. Start of an Audio Input Frame .....................................................................................................26
Figure 16. STAC9750/9751 Powerdown Timing .........................................................................................29
Figure 17. STAC9750 2-Channel Mixer Functional Diagram ..................................................................31
Figure 18. STAC9751 2-Channel Mixer Functional Diagram .......................................................................32
Figure 19. Example of STAC9750/9751 Powerdown/Powerup Flow ...........................................................56
Figure 20. STAC9750/9751 Powerdown/Powerup Flow With Analog Still Active ........................................57
Figure 21. STAC9750/9751 Pin Description Drawing ...................................................................................61
Figure 22. Package Drawing - 48-pin LQFP ..................................................................................................66
Figure 23. Reflow Profile ..............................................................................................................................67
Figure 24. STAC9750/9751 Split Independent Power Supply Operation Typical Connection Diagram ....... 70
STAC9750/9751
VALUE-LINE TWO-CHANNEL AC’97 CODECS PC AUDIO
IDT™
4 STAC9750/9751 V 5.8 103106
VALUE-LI NE TWO-CHANNEL AC’97 CODECS
LIST OF TABLES
Table 1. STAC9751 Analog Performance Characteristics .............................................................................13
Table 2. Cold Reset Specifications ................................................................................................................15
Table 3. Warm Reset Specifications ..............................................................................................................15
Table 4. Clocks Specifications .......................................................................................................................16
Table 5. Clock Mode Configuration ...............................................................................................................16
Table 6. Data Setup and Hold Specifications ................................................................................................17
Table 7. Signal Rise and Fall Times Specifications .......................................................................................17
Table 8. AC-Link Low Power Mode Timing Specifications ............................................................................18
Table 9. ATE Test Mode Specifications .........................................................................................................18
Table 10. STAC9750/9751 Available Data Streams ......................................................................................21
Table 11. Command Address Port Bit Assignments ......................................................................................23
Table 12. Command Data Port Bit Assignments ...........................................................................................24
Table 13. Status Address Port Bit Assignments ............................................................................................27
Table 14. Status Data Port Bit Assignments ..................................................................................................27
Table 15. Programming Registers .................................................................................................................34
Table 16. Play Master Volume Register ........................................................................................................35
Table 17. PC_BEEP Register ........................................................................................................................36
Table 18. Analog Mixer Input Gain Register ..................................................................................................37
Table 19. Record Select Control Registers ................................................................................................... 39
Table 20. Record Gain Registers .................................................................................................................39
Table 21. General Purpose Register .............................................................................................................40
Table 22. 3D Control Registers ....................................................................................................................40
Table 23. Powerdown Status Registers .........................................................................................................42
Table 24. Extended Audio ID .........................................................................................................................43
Table 25. Slot assignment relationship between SPSA1 and SPSA0 ...........................................................45
Table 26. STAC9750/9751 AMAP compliant .................................................................................................45
Table 27. Hardware Supported Sample Rates ..............................................................................................45
Table 28. SPDIF Control ...............................................................................................................................46
Table 29. Extended Moden Status and Control .............................................................................................47
Table 31. GPIO Pin Polarity/Type Register ...................................................................................................48
Table 32. GPIO Pin Sticky Register ...............................................................................................................48
Table 30. GPIO Pin Configuration Register ...................................................................................................48
Table 33. GPIO Pin Mask Register ................................................................................................................49
Table 35. Digital Audio Control Register ........................................................................................................50
Table 34. GPIO Pin Status Register ..............................................................................................................50
Table 36. ADC data on AC LINK ...................................................................................................................52
Table 37. Mic Boost Select ............................................................................................................................52
Table 38. Analog Current Adjust ...................................................................................................................53
Table 39. GPIO Access Registers (74h) ........................................................................................................54
Table 40. Low Power Modes .........................................................................................................................56
Table 41. CODEC ID Selection .....................................................................................................................58
Table 42. Secondary CODEC Register Access Slot 0 Bit Definitions ...........................................................59
Table 43. Digital Connection Signals .............................................................................................................62
Table 44. Analog Connection Signals ...........................................................................................................63
Table 45. Filtering and Voltage References ..................................................................................................64
Table 46. Power and Ground Signals ............................................................................................................64
STAC9750/9751
VALUE-LINE TWO-CHANNEL AC’97 CODECS PC AUDIO
IDT™
5 STAC9750/9751 V 5.8 103106
VALUE-LI NE TWO-CHANNEL AC’97 CODECS
1. PRODUCT BRI EF
1.1. Features
• Full duplex stereo 18-bit ADC and 20-bit DAC
• AC’97 Rev 2.2-compliant
• High performanc e Σ∆ technology
• SPDIF output
• Crystal elimination circuit
• Headphone amplifier
• Independent sample rates for ADCs & DACs (hardware SRCs)
• 20dB or 30dB microphone boost capability
• 90dB SNR LINE-LINE
• 5-Wire AC-Link protocol compliance
• Digita l-R ea dy ar ch ite ctu re
• General Purpose I/O
• +3.3 V (STAC9751) and +5 V (STAC9750) analog power supply options
• Pin compatible with the STAC9700/21/44/08/56/66/52
• IDT Surround (SS3D) Stereo Enhancement
• Energy saving dynamic power modes
1.2. Description
IDT's STAC9750/9751 are general purpose 18-bit ADC, 20-bit DAC, full duplex, audio CODECs con-
forming to the analog compone nt specifi cation of AC'9 7 (Audio Codec ‘9 7 Component Spec ification
Rev. 2.2) . The STAC 9750/97 51 incor porate ID T's pr oprietary Σ∆ techno logy to ach ieve a DA C SNR
in exce ss o f 90 dB . T he DAC s, ADCs , a nd mix er a re in teg ra ted with ana lo g I/O s , wh ic h in clu de f our
analog line-level stereo inputs, two analog line-level mono inputs, two stereo outputs, and one mono
output channel. The STAC9750/9751 include digital input/output capability for support of modern PC
system s with an ou tput tha t sup ports the SPDIF format. T he S TAC97 50/9751 is a s tandard 2-chan-
nel stereo CODEC. With IDT’s headphone drive capability, headphones can be driven with no exter-
nal amplifier. The STAC9750/9751 may be used as a secondary CODEC, with the STAC9700/21/44/
56/08/84/66 as the primary, in a multiple CODEC configuration conforming to the AC'97 Rev. 2.2
specification. This configuration can provide the true six-channel, AC-3 playback required for DVD
applica tions. The STAC9750/97 51 c om mun ic ates v ia th e five- wi re AC- Li nk t o any di gital c omp onen t
of AC'97, providing flexibility in the audio system design. Packaged in an AC'97 compliant 48-pin
LQFP, the STAC975 0/9751 c an be placed on a moth erboard, d aughter boards, PCI, AMR, CNR, or
ACR cards.
The STAC9750/9751 block diagram is illustrated in Figure 1. It provides variable sample rate Digi-
tal-to-Analog (DA) and Analog-to-Digital (AD) conversion, mixing, and analog processing. Supported
audio sample rates include 48 KHz, 44.1 KHz, 32 KHz, 22.05 KHz, 16 KHz, 11.025 KHz, and 8 KHz;
additional rates are supported in the STAC9750/9751 soft audio drivers. The digital interface com-
municates with the AC'97 controller via the five-wire AC-Link and contains the 64-word by 16-bit reg-
STAC9750/9751
VALUE-LINE TWO-CHANNEL AC’97 CODECS PC AUDIO
IDT™
6 STAC9750/9751 V 5.8 103106
VALUE-LI NE TWO-CHANNEL AC’97 CODECS
isters. The two DACs convert the digital stereo PCM-out content to audio. The MIXER block
combines the PCM_OUT with any analog sources, to drive the LINE_OUT and HP_OUT outputs.
The MONO_OUT delivers either microphone o nly, or a mono mix of sources from the MIXER. The
stereo v ariable sam ple rate ADC s provide r ecord capability fo r any mix of mono or ste reo sources ,
and deliver a digital stereo PCM_IN signal back to the AC-Link. The microphone input and mono
input can be recorde d simultaneously, thus allowing for an all digital output in support of the digital
ready initiative. All ADCs operate at 18-bit resolution and DACs at 20-bit resolution. For a digital
ready record path, the microphone is connected to the left channel ADC while the mono output of the
stereo mixer is connected to right channel ADC. Make sure the microphone input is not connected to
the stereo mixer when in this mode.
The STAC9750/9751 supports General Purpose Input/Output (GPIO), as well as SPDIF output.
These d igital I/O options pro vide for a numb er of advance d architectur al implementations , with vol-
ume controls and digital mixing capabilities built directly into the CODEC.
The STAC9750/97 51 i s designe d pri mar i ly to support st er eo (2-s pe aker ) aud io. True AC-3 p lay ba ck
can be achieved for 6-speaker applications by taking advantage of the multi-CODEC option avail-
able in th e STA C9750/9751 to s upport multipl e CODECs in an AC'97 architect ure. Additional ly, th e
STAC9750/9751 provides for a stereo enhancement feature, IDT Surround 3D (SS3D). SS3D pro-
vides the listener with several options for improved speaker separation beyond the normal 2/
4-speaker arrangements.
Together with the logic component (controller or advanced core logic chip-set) of AC'97, STAC9750/
9751 can be SoundBlaster® and Windows Sound System® compatible with IDT’s WDM driver for
WIN 98/2K/ME/XP.
SoundBlaster is a registered trademark of Creative Labs.
Windows is a registered trademark of Microsoft Corporation.
1.3. STAC9750/9751 Block Diagram
Figure 1. STAC9750/9751 Block Diagram
HP_OUT
AC-link
Digital
Interface
Registers
64x16 bits
SYNC
BIT_CLK
SDATA_OUT
SDATA_IN
RESET#
Power
Management
DAC
DAC
ADC
ADC
PCM out DACs
PCM in ADCs
4 stereo
sources 2 mono
sources
MONO_OUT
Mic Boost
0,20 or 30 dB MIC1
Stereo
Mono
MIXER
Analog mixing
and Gain Control
M
U
X
MIC2
LINE_OUT
Multi-Codec
CID0
CID1
SPDIF
Variable Sample Rate
20-Bit DACs and
18-Bit ADCs
STAC9750/9751
VALUE-LINE TWO-CHANNEL AC’97 CODECS PC AUDIO
IDT™
7 STAC9750/9751 V 5.8 103106
VALUE-LI NE TWO-CHANNEL AC’97 CODECS
1.4. Key Specifications
• Analog LINE_OUT SNR: 90 dB
• Digital DAC SNR: 89 dB
• Digital ADC SNR: 85 dB
• Full-scale Total Harmonic Distortion: 0.005%
• Crosstalk between Input Channels: -70 dB
• Spurious Tone Rejection: 100 dB
1.5. Related Mat erials
•Product Brief
• Reference Designs for MB, AMR, CNR, and ACR applications
• Audio Precision Performance Plots
1.6. Additional Support
Additional product and company information can be obtained by going to the
IDT website at: ww w.IDT.com
STAC9750/9751
VALUE-LINE TWO-CHANNEL AC’97 CODECS PC AUDIO
IDT™
8 STAC9750/9751 V 5.8 103106
VALUE-LI NE TWO-CHANNEL AC’97 CODECS
2. CHARACTERISTICS/SPECIFICATIONS
2.1. Electrical Specifications
2.1.1. Absolute Maximum Ratings:
Stresses above the ratings listed below can cause permanent damage to the STAC9750/9751. These ratings,
which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the
device at these or any other conditions above those indicated in the operational sections of the specifications is not
implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability.
Electrical parameters are guaranteed only over the recommended operating temperature range.
2.1.2. Recommended Operation Conditions
Item Pin Maximum Rating
Maximum supply voltage Vdd 5.5 Volts
Output current per pin ± 4 mA, except VREF_OUT = ± 5mA
Voltage on any pin relative to ground Vss - 0.3 V to Vdd + 0.3 V
Operating temperature 0oC to +70oC
Storage temperature -55 oC to +125 oC
Soldering temperature 260 oC for 10 seconds *
Soldering temperature information for all available packages
begins on page 67.
Parameter Min. Typ. Max. Units
Power Supply Voltage Digital - 3.3 V 3.135 3.3 3.465 V
Analog - 5 V 4.75 5 5.25 V
Analog - 3.3 V 3.135 3.3 3.465 V
Ambient Operating Temperature 0 +70 °C
Cas e Temperature Tcase (48-LQF P) +90 °C
ESD: The STAC9750/9751 is an ESD (elect rost atic dischar ge) sensiti ve device. The hu man body and
test equipment can accumulat e and dischar ge elect ros ta tic c harges up to 4000 Volts wit hout dete cti on.
Even though the STAC9750/9751 implements internal ESD protection circuitry , proper ESD precautions
should be followed to avoid damaging the functionality or performance.
STAC9750/9751
VALUE-LINE TWO-CHANNEL AC’97 CODECS PC AUDIO
IDT™
9 STAC9750/9751 V 5.8 103106
VALUE-LI NE TWO-CHANNEL AC’97 CODECS
2.1.3. Power Consumption
Parameter Min Typ Max Unit
Digital Supply Current
+ 3.3 V Digital - 30 - mA
Analog Supply Current (at Reset state)
+ 5 V Analog - 35 - mA
+ 3.3 V Analog - 35 - mA
Power Down Status (individually asserted)
All PR measurem en t s taken whil e unmu ted .
All paths unmuted +5 V Analog Supply Current
+3.3 V Analog Supply Current
+3.3 V Digital Supply Current -50
44
33 -mA
PR0 +5 V Analog Supply Current
+3.3 V Analog Supply Current
+3.3 V Digital Supply Current -42
39
22 -mA
PR1 +5 V Analog Supply Current
+3.3 V Analog Supply Current
+3.3 V Digital Supply Current -41
38
28 -mA
PR2 +5 V Analog Supply Current
+3.3 V Analog Supply Current
+3.3 V Digital Supply Current -32
29
12 -mA
PR3 +5 V Analog Supply Current
+3.3 V Analog Supply Current
+3.3 V Digital Supply Current -23
19
12 -mA
PR4 +5 V Analog Supply Current
+3.3 V Analog Supply Current
+3.3 V Digital Supply Current -50
44
0.2 -mA
PR5 +5 V Analog Supply Current
+3.3 V Analog Supply Current
+3.3 V Digital Supply Current -50
44
12 -mA
PR6 +5 V Analog Supply Current
+3.3 V Analog Supply Current
+3.3 V Digital Supply Current -38
36
33 -mA
PR0 & PR1 +5 V Analog Supply Current
+3.3 V Analog Supply Current
+3.3 V Digital Supply Current -35
35
12 -mA
PR0, PR1, PR2, PR6 +5 V Analog Supply Current
+3.3 V Analog Supply Current
+3.3 V Digital Supply Current -5
5
12 -mA
PR0, PR1, PR2, PR3, PR6 +5 V Analog Supply Current
+3.3 V Analog Supply Current
+3.3 V Digital Supply Current -0.6
0.6
12 -mA
STAC9750/9751
VALUE-LINE TWO-CHANNEL AC’97 CODECS PC AUDIO
IDT™
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VALUE-LI NE TWO-CHANNEL AC’97 CODECS
2.1.4. Revision Comparison
2.1.5. AC-Link Static Digita l Specifications
(Tambient = 25 ºC, DVdd = 3.3 V ± 5%, AVss=DVss=0 V; 50 pF external load)
CA3 CC1 % Of Savings
Analog Digital Analog Digital Analog Digital
5 V 3.3 V 3.3 V 5 V 3.3 V 3.3 V 5 V 3.3 V 3.3 V
No P R 78 69 27 50 44 33 36% 36% -22%
PR0 62 56 23 42 39 22 32% 30% 4%
PR1 63 52 24 41 38 28 35% 27% -17%
PR2 48 42 27 32 29 12 33% 31% 56%
PR3 40 35 21 23 19 12 43% 46% 43%
PR4 76 68 1 50 44 0.2 34% 35% 80%
PR5 75 68 7.5 50 44 12 33% 35% -60%
PR6 97 61 27 38 36 33 61% 41% -22%
PR bit individually asserted. All PR measurements taken while unmuted.
Parameter Symbol Min Typ Max Unit
Input Voltage Range Vin -0.30 - DVdd + 0.30 V
Low level input range Vil - - 0.35xDVdd V
High level input voltage Vih 0.65xDVdd - - V
High level output voltage Voh 0.90xDVdd - - V
Low level output voltage Vol - - 0.1xDVdd V
Input Leakage Current (AC-Link inputs) - -10 - 10 µA
Output Leakage Current (AC-Link outputs - Hi-Z) - -10 - 10 µA
Output buffer drive current - - 4 - mA
STAC9750/9751
VALUE-LINE TWO-CHANNEL AC’97 CODECS PC AUDIO
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VALUE-LI NE TWO-CHANNEL AC’97 CODECS
2.1.6. STAC9750 Analog Performance Characteristics
(Tambient = 25 ºC, AVdd = 5.0 V ± 5%, DVdd = 3. 3 V ± 5%, AVss=DVss =0 V; 1 K Hz in put si ne w ave ;
Sample Frequency = 48 KHz; 0dB = 1 Vrms, 10 KΩ/50 pF load, Testbench Characterization BW:
20 Hz – 20 KHz, 0dB settings on all gain stages)
Parameter Min Typ Max Unit
Full Scale Input Voltage:
All Analog Inputs except Microphone - 1.0 - Vrms
Microphone Inputs (Note 1) - 0.03 - Vrms
Full Scale Output:
Line Output - 1.0 - Vrms
PCM (DAC) to LINE_OUT - 1.0 Vrms
MONO_OUT - 1.0 - Vrms
HEADPHONE_OUT (32 Ω load) (peak) -50-mW
Analog S/N: (Note 2)
CD to LINE_OUT - 90 - dB
Other to LINE_OUT - 90 - dB
D/A to LINE_OUT - 89 - dB
LINE_IN to A/D with High pass filter enabled - 85 - dB
Analog Frequency Response (Note 3) 20 - 20,000 Hz
Total Harmon ic Distortion : (Note 4)
CD to LINE_OUT - 89 - dB
Other to LINE_OUT - 89 - dB
D/A to LINE_OUT (full scale) - 89 - dB
LINE_IN to A/D with High pass filter enabled 84 - - dB
HEADPHONE_OUT 74 80 - dB
A/D & D/A Digital Filter Pass Band (Note 5) 20 - 19,200 Hz
A/D & D/A Digital Filter Transition Band 19,200 - 28,800 Hz
A/D & D/A Digital Filter Stop Band 28,800 - - Hz
A/D & D/A Digital Filter Stop Band Rejection (Note 6) 100 - - dB
DAC Out-of-Band Rejection (Note 7) 55 - - dB
Group Delay (48KHz sample rate) - 1 ms
Any Analog Input to LINE_OUT Crosstalk (10 KHz Signal Frequency) - 70 - dB
Any Analog Input to LINE_OUT Crosstalk (1 KHz Signal Frequency) - 100 - dB
Spurious Tone Rejection - 100 - dB
Attenuation, Gain Step Size - 1.5 - dB
Input Impedance (Note 8) - 50 - KΩ
Input Capacitance - 15 - pF
VREF_OUT - 0.5 X AVdd - V
STAC9750/9751
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Note: 1. With +30 dB Boost on, 1.0 Vrms with Boost off.
2. Ratio of Full Scale signal to idle channel noise output is measured “A weighted” over a 20 Hz to a 20 KHz bandwidth.
(AES17-1991 Idle Channel Noise or EIAJ CP-307 Signal-to-noise Ratio).
3. ± 1dB limits for Line Output & 0 dB gain.
4. Ratio of Full Scale signal to THD+N output with -3dB signal, measured “A weighted” over a 20 KHz BW, 48 KHz Sample
Frequency.
5. ± 0.25dB limits
6. Stop Band rejection determines filter requirements. Out-of-Band rejection determines audible noise.
7. The integrated Out-of-Band noise generated by the DAC process, during normal PCM audio playback, over a bandwidth
28.8 to 100 KHz, with respect to a 1 Vrms DAC output.
8. For all inputs except PC BEEP.
Interchannel Gain Mismatch ADC - - 0.5 dB
Interchannel Gain Mismatch DAC - - 0.5 dB
Parameter Min Typ Max Unit
STAC9750/9751
VALUE-LINE TWO-CHANNEL AC’97 CODECS PC AUDIO
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13 STAC97 50/9751 V 5.8 1031 06
VALUE-LI NE TWO-CHANNEL AC’97 CODECS
2.1.7. STAC9751 Analog Performance Characteristics
(Tambient = 25 ºC, AVdd = DVdd = 3.3 V ± 5%, AVss=DVss=0 V ; 1 KHz input sine wave; Sample Fre-
quency = 48 KHz; 0dB = 1 Vrms, 10 KΩ/50 pF load, Testbench Characterization BW: 20 Hz –
20 KHz, 0dB settings on all gain stages)
Parameter Min Typ Max Unit
Full Scale Input Voltage:
All Analog Inputs except Microphone - 1.0 - Vrms
Microp hon e Inpu ts (Note 1) - 0.03 - Vr ms
Full Scale Output:
Line Output - 0.5 - Vrms
PCM (DAC) to LINE_OUT 0.5 Vrms
MONO_OUT - 0.5 - Vrms
HEADPHONE_OUT (32 Ω load) (pea k) - 12.5 - mW
Analog S/N: (Note 2)
CD to LINE_OUT - 90 - dB
Other to LINE_OUT - 90 - dB
D/A to LINE_OUT - 89 - dB
LINE_IN to A/D with High pa ss filter ena ble d - 85 - dB
Analog Fr equ enc y Resp on se (N ote 3) 20 - 20,000 Hz
Total Harmonic Distortion: (Note 4)
CD to LINE_OUT - 89 - dB
Other to LINE_OUT - 89 - dB
D/A to LINE_OUT (full scale) - 89 - dB
LINE_IN to A/D with High pa ss filter ena ble d - 84 - dB
HEADPHONE_OUT 74 80 - dB
A/D & D/A Digital Filter Pass Band (Note 5) 20 - 19,200 Hz
A/D & D/A Digital Filter Transition Band 19,200 - 28,800 Hz
A/D & D/A Digital Filter Stop Band 28,800 - - Hz
A/D & D/A Digital Filter Stop Band Rejection (Note 6) 100 - - dB
DAC Out-of-Ba nd Re je cti on (Not e 7) 55 - - dB
Group Delay (48 KHz sample rate) - - 1 ms
Any Analog Input to LINE_OUT Crosstalk (10 KHz Signal Frequency) - 70 - dB
Any Analog Input to LINE_OUT Crosstalk (1 KHz Signal Frequency) - 100 - dB
Spurious Tone Rejection - 100 - dB
Attenuation, Gain Step Size - 1.5 - dB
Input Impedance (Note 8) - 50 - KΩ
Input Capa citance - 15 - p F
VREF_OUT -0.5 X AVdd- V
Table 1. STAC9751 Analog Performance Characteristics
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Note: 1. With +30 dB Boost on, 1.0 Vrms with Boost off.
2. Ratio of Full Scale signal to idle channel noise output is measured “A weighted” over a 20 Hz to a 20 KHz bandwidth.
(AES17-1991 Idle Channel Noise or EIAJ CP-307 Signal-to-noise Ratio).0 dB gain, 20 KHz BW, 48 KHz Sample
Frequency± 1 dB limits.
3. ± 1dB limits for Line Output & 0 dB gain.
4. Ratio of Full Scale signal to THD+N output with -3dB signal, measured “A weighted” over a 20 KHz BW, 48 KHz Sample
Frequency.
5. ± 0.25dB limits
6. Stop Band rejection determines filter requirements. Out-of-Band rejection determines audible noise.
7. The integrated Out-of-Band noise generated by the DAC process, during normal PCM audio playback, over a bandwidth
28.8 to 100 KHz, with respect to a 1 Vrms DAC output.
8. For all inputs except PC BEEP.
Interchannel Gain Mismatch ADC - - 0.5 dB
Interchannel Gain Mismatch DAC - - 0.5 dB
Gain D rift - 100 - ppm/ºC
Parameter Min Typ Max Unit
Table 1. STAC9751 Analog Performance Characteristics (Continued)
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2.2. AC Timing Characteristics
(Tambient = 25 °C, AVdd = 3.3 V or 5 V ± 5%, DVdd = 3.3 V ± 5%, AVss = DVss = 0 V; 50 pF external
load)
2.2.1. Cold Reset
Figure 2. Cold Reset Timing
Note: BIT_CLK and SDATAIN are in a high impedance state during reset.
2.2.2. Warm Reset
Figure 3. Warm Reset Timing
Table 2. Cold Reset Specifications
Parameter Symbol Min Typ Max Units
RESET# active low pulse width Tres_low 1.0 - - µs
RESET# inactive to BIT_CLK startup delay Trst2clk 162.8 - - ns
Table 3. Warm Reset Specifications
Parameter Symbol Min Typ Max Units
SYNC active high pulse width Tsync_high 1.0 1.3 - µs
SYNC inactive to BIT_CLK startup delay Tsync2clk 162.8 - - ns
Tres_low
Trst2clk
RESET#
BIT_CLK
SDATA_IN
Tsync_high Tsync_2clk
SYNC
BIT_CLK
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2.2.3. Clocks
Figure 4. Clocks T imin g
The STA C9750/9751 supports several clock freque ncy inputs as desc ribed in the following table . In
general , when a 24.576 MHz c lock XTAL is not used, the XTA L_OUT pin sh ould be tied to ground.
This short to ground configures the part into an alternate clock mode and enables an on board PLL.
Table 4. Clocks Specifications
Parameter Symbol Min Typ Max Units
BIT_CLK frequ en cy - 12.288 - MHz
BIT_CLK period Tclk_period - 81.4 - ns
BIT_CLK output jitt er - 750 - p s
BLT_CLK high pulse width (Note 1) Tclk_high 36 40.7 45 ns
BIT_CLK low pulse width (Note 1) Tclk_low 36 40.7 45 ns
SYNC frequency - 48.0 - KHz
SYNC period Tsync_p eriod - 2 0.8 - µs
SYNC high pulse width Tsync_high - 1.3 - µs
SYNC low pulse width Tsync_low - 19.5 - µs
Note: 1. Worst case duty cycle restricted to 45/55.
Table 5. Clock Mode Configuration
XTL_OUT
Pin Config CID1
Pin Config CID0
Pin Config Clock Source Input CODEC
Mode CODEC
ID
XTAL float float 24.576 MHz XTAL P 0
XTAL or open float pulldown 12.288 MHz BIT_CLK S 1
XTAL or open pulldown float 12.288 MHz BIT_CLK S 2
XTAL or open pulldown pulldown 12.288 MHz BIT_CLK S 3
sh ort to ground float float 14.31818 MHz source P 0
short to ground float pulldown 27 MHz source P 0
short to ground pulldown float 48 MHz source P 0
short to ground pulldown pulldown 24.576 MHz source P 0
SYNC
BIT_CLK Tclk_high
Tclk_low
Tclk_period
Tsync_high
Tclk_period
Tsync_low
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2.2.4. Data Setup and Hold
(47.5-75 pF external load)
Figure 5. Data Setup and Hold Timing
2.2.5. Signal Rise and Fall Times
(75pF external load; from 10% to 90% of Vdd)
Figure 6. Signal Rise and Fall Times Timing
Table 6. Data Setup and Hold Specifications
Parameter Symbol Min Typ Max Units
Setup to falling edge of BIT_CLK Tsetup 10 - - ns
Hold from falling edge of BIT_CLK Thold 10 - - ns
Note: Setup and hold time parameters for SDATA_IN are with respect to the AC'97 controller.
Table 7. Signal Rise and Fall Times Specifications
Parameter Symbol Min Typ Max Units
BIT_CLK rise time T r ise clk - - 6 ns
BIT_CLK fall time Tfallclk - - 6 ns
SDATA_IN rise time Trisedin - - 6 ns
SDATA_IN fall time Tfalldin - - 6 ns
BIT_CLK
Thold
Tsetup
SDATA_OUT
SDATA_IN
SYNC
tco
Vih Vil
Voh
Vol
BIT_CLK
SDATA_IN
TfallclkTriseclk
Trisedin Tfalldin
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2.2.6. AC-Link Low Power Mode Timing
Figure 7. AC-Link Low Power Mode Timing
2.2.7. ATE Test Mode
Figure 8. ATE Test Mode Timing
Note: 1. All AC-Link signa ls are no rma lly low thro ugh th e trailing e dge o f RESET# . Bri ngi ng SDATA_OUT high for th e tr ail ing e dge
of RESET# causes the STAC9750/9751 AC-Link outputs to go high-impedance, which is suitable for ATE in-circuit testing.
2. Once the test mode has been entered, the STAC9750/9751 must be issued another RESET# with all AC-Link signals low
to return to the normal operating mode.
3. # denotes active l ow.
Table 8. AC-Link Low Power Mode Timing Specifications
Parameter Symbol Min Typ Max Units
End of Slot 2 to BIT_CLK, SDATA_IN low Ts2_pdown - - 1.0 µs
Table 9. ATE Test Mode Specifications
Parameter Symbol Min Typ Max Units
Setup to trailing edge of RESET# (also applies to SYNC) Tsetup2rst 15.0 - - ns
Rising edge of RESET# to Hi-Z delay Toff - - 25.0 ns
BIT_CLK
SDATA_IN
N o te : B IT _ C L K n o t to s c a le
Ts2_pdown
Don't care
D a ta P R 4
Write to
0x20
Slot 2Slot 1
SDATA_OUT
SYNC
Tsetup2rst
Hi-Z
Toff
RESET#
SDATA_OUT
SDATA_IN, BIT_CLK
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3. TYPICAL CONNECTION DIAGRAM
Figure 9. STAC9751 Typical Connection Diagram
Note: 1. See Appendix A for specific connection requirements prior to operation.
2. See Figure 24 on page 70 for split supply connections.
3. Pin 48: To Enable SPDIF, use an 1 KW-10 KW external pulldown. To Disable SPDIF, use an 1 KW-10 KW external pullup.
Do NOT le ave Pin 48 floating.
4. The CD_GN D si gna l i s an AC sig na l retu rn fo r the tw o CD inp ut c ha nne ls . It is no rma lly bi ase d at about 2.5V. The name of
the pin in the AC97 specification is CD_GND, and this has confused many designers. It should not have any DC path to
GND. Connecting the CD_GND signal directly to ground will change the internal bias of the entire CODEC, and cause
significant distortion. If there is no analog CD input, then this pin can be No-Connect.
0.1 µF 1 µF 0.1 µF 0.1 µF 10 µF 0.1 µF
2 Ω* Ferrite Bead* *Suggested 3.3V ± 5%
AVdd1 AVdd2 DVdd1 DVdd2 XTL_IN
XTL_OUT
9
2
3
27 pF
27 pF
24.576 MHz
13825
PC_BEEP
12
PHONE
13
AUX_L
14
AUX_R
15
VIDEO_L
16
VIDEO_R
17
CD_L
18
CD_GND
19
CD_R
20
MIC1
21
MIC2
22
LINE_IN_L
23
LINE_IN_R
41
CAP2
32
*OPTIONAL
0.1 µF 1 µF*
820 pF 29
30
AFILT1
AFILT2
820 pF
AVss1 AVss2
26 42 4 7
DVss1 DVss2 HP_OUT_R
*Terminate ground
plane as clos e to codec
as possible
Analog
Ground Digital
Ground
HP_OUT_L 39
37
MONO_OUT
36
LINE_OUT_R
35
LINE_OUT_L
43
GPIO0
44
GPIO1
40
HP_COMM
48
SPDIF
34
NC
33
NC
31
NC 0.1 µF 1 µF*
*OPTIONA
L
27
VREF
VREFOUT
EAPD
CID1
CID0
28
47
46
45
11
RESET#
10
SYNC
24
SDATA_IN
BIT_CLK
SDATA_OUT 5
6
827 pF
22 Ω
EMI
Filter
*OPTIONAL
STAC9751
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4. AC-LINK
Figure 10 shows t he AC -Link point to p oint s erial inter connect between the STAC9750/97 51 and its
companion controller. All digital audio streams and command/status information are communicated
over this AC-Link. See “Digital Interface” on page 21 for details.
Figure 10. AC-Link to its Companion Controller
4.1. Clocking
STAC9750/9751 derives its clock internally from an externally connected 24.576 MHz crystal or an
oscillator, through the XTAL_IN pin. Synchronization with the AC'97 controller is achieved through
the BIT_CLK pin at 12.288 MHz.
The begi nning o f all au dio sa mple pack ets, or “Au dio F rames” , transfer red o ver AC- Link is sync hro-
nized to t he rising e dge of th e “SYNC” sign al driven b y the AC'97 controller. Data is transition ed on
AC-Link on ev ery r i si ng e dge of B IT_CLK, and s ub seq uen tly sa mp led by the receivin g side on e a ch
immediately following falling edge of BIT_CLK.
4.2. Reset
There are 3 types of resets:
1. a “cold” reset where all STAC9750/9751 logic and registers are initialized to their default state
2. a “warm” reset where the contents of the STAC9750/9751 register set are left unaltered
3. a “register” reset which only initializes the STAC9750/9751 registers to their default states
After signaling a reset to the STAC9750/9751, the AC'97 controller should not attempt to play or cap-
ture audio data until it has sampled a “CODEC Ready” indication via register 26h from the
STAC9750/9751.
For proper reset operation SDATA_OUT should be 0 during cold reset.
SYNC
Digital DC'97
Controller AC '97 C odec
BIT_CLK
SDATA_OUT
SDATA_IN
RESET#
XTAL_IN
XTAL_OUT
A
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5. DIGITAL INTERFACE
5.1. AC-Link Digital Serial Interface Protocol
The STAC9750/9751 communicates to the AC'97 controller via a 5-wire, digital, serial, AC-Link inter-
face, which is a bi-directional, fixed rate, serial PCM digital stream. All digital audio streams, com-
mands and status information are communicated over this point-to-point serial interconnect. The
AC-Link han dle s m ult ipl e in put and output audi o s treams , as wel l as co ntr ol re gist er ac c esses us in g
a time division multiplexed (TDM) scheme. The AC'97 controller synchronizes all AC-Link data trans-
action. Table 10 shows the data streams available on the STAC9750/9751:
Synchron iz ati on o f all AC- Li nk data trans ac tio ns is hand le d by the A C'97 c on tro ller. The STAC9750/
9751 drives the serial bit clock onto AC-Link. The AC'97 controller then qualifies with a synchroniza-
tion signal to construct audio frames.
SYNC, fixed at 48 KHz, is derived by dividing down the serial bit clock (BIT_CLK). BIT_CLK, fixed at
12.288 MHz, provides the necessary clocking granularity to support twelve 20-bit outgoing and
incoming time slots. AC-Link serial data is transitioned on each rising edge of BIT_CLK. The receiver
of AC-Link data, STAC9750/97 51 for out goi ng da ta and AC '97 cont ro ll er for i ncomi ng da ta, samp les
each serial bit on the falling edges of BIT_CLK.
The AC-Li nk protoc ol prov ides for a spe cial 16-bi t (13-bi ts defined, wi th 3 Res erved trai ling b it posi-
tions) time slot (Slot 0) wherein each bit conveys a “slot-valid” tag for its corresponding time slot
within the current audio frame. A 1 in a given bit position of slot 0 indicates that t he corresponding
time slot within the current audio frame has been assigned to a data stream, and contains valid data.
If a slot is tagged invalid, it is the responsibility of the source of the data, (STAC9750/9751 for the
input stream, AC'97 controller for the output stream), to stuff all bit positions with 0s during that slot’s
active tim e.
SYNC re mains high f or a total dur ation of 1 6 BIT_CLKs a t the beg inning of e ach audio frame. The
portion of the a udio fram e wher e SYNC is high is de fined a s the “Tag Pha se”. The r emai nder of th e
audio frame where SYNC is low is defined as the “Data Phase”.
Additionally, for power savings, all clock, SYNC, and data signals can be halted by the controller.
Table 10. STAC9750/9751 Available Data Streams
PCM Playback 2 output slots 2 Channel composite PCM output stream
PCM Record data 2 input slots 2 Channel composite PCM input stream
Control 2 output slots Control register write port
Status 2 input slots Control register read port
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Figure 11. AC'97 Standard Bi-directional Audio Frame
5.1.1. AC-Link Audio Output Frame (SDATA_OUT)
The audio output frame data streams correspond to the multiplexed bundles of all digital output data
targeting th e STAC975 0/9751 DA C inputs, an d control register s. Each audio ou tput fram e suppo rts
up to twelve 20- bit outgoi ng data time slots. Slot 0 is a speci al Reserved tim e slot co ntaining 16 bits
that are used for AC-Link protocol infrastructure.
Within slot 0, the first bit is a global bit (SDATA_OUT slot 0, bit 15) which flags the validity for the
entire au dio fra me. If the “ Val id Fram e” bit is a 1, this i ndi ca tes t hat th e cu rren t aud io fr am e c ontains
at least one slot time of valid data. The next 12 bit positions sampled by the STAC9750/97 51 indi-
cate wh ich of the co rrespo nding 1 2 tim es slots con tain vali d data. In th is way data st reams o f differ-
ing sample rates can be transmitted across AC-Link at its fixed 48 KHz audio frame rate. The
following diagram illustrates the time slot based AC-Link protocol.
Figure 12. AC-Link Audio Output Frame
A new audio output frame begins with a low to high transition of SYNC. SYNC is synchronous to the
rising edge of BIT_CLK. On the immediately following falling edge of BIT_CLK, the STAC9750/9751
samples the as ser tio n of SY NC. Th is fo ll owi ng ed ge ma rks the tim e whe n both si des of AC- Li nk ar e
aware of the start of a new audio frame. On the next rising edge of BIT_CLK, the AC'97 controller
transit ions SDATA_OUT int o the first bit p osition of slot 0 (Valid Frame bit) . Each new bi t positio n is
presented to AC-Link on a rising edge of BIT_CLK, and subsequently sampled by the STAC9750/
9751 on the following falling edge of BIT_CLK. This sequence ensures that data transitions, and
subsequent sample points for both incoming and outgoing data streams, are time aligned.
OUTGOING STREAMS
INCOMING STREAMS
SYNC
TAG PHASE DATA PHASE
PCM
LEFT
CMD
ADR NA PCM
LSURR PCM
LFE PCM
RALT
TAG CMD
DATA PCM
RT PCM
CTR PCM
RSURR PCM
LALT RSVD
PCM
LEFT
STATUS
ADR NA RSVD RSVD RSVDTAG STATUS
DATA PCM
RT NA RSVD RSVD RSVD
SYNC
BIT_CLK
SDATA_OUT slot1 slot2
End of previous audio frame
slot(12) "0" 19
Data Phase
20.8 u S (48 k HZ )Tag Phase
12.288 M Hz
Time Slot "Valid " Bits S l ot 1 Slot 2 Slot 3 Slot 12
("1" = time s lo t contain s valid PCM da ta)
CID1 CID0
valid "0" 19 19"0"
Frame 19"0" "0"
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Figure 13. Start of an Audio Output Frame
SDATA_OUT’s composite stream is MSB justified (MSB first) with all non-valid slots’ bit positions
stuffed with 0s by the AC'97 controller.
When mono audio sample streams are sent from the AC'97 controller, it is necessary that BOTH left
and right sample stream time slots be filled with the same data.
5.1.1.1. Slot 1: Command Address Port
The command port is used to control features and monitor status (see Audio Input Frame Slots 1
and 2) o f the S TA C97 50/9 751 f unctio ns inclu ding, bu t not limited to, mixe r setting s and powe r man-
agement (refer to the Control Register section of this specification).
The control interface architecture supports up to sixty-four 16-bit read/write registers, addressable
on even byte bounda ries. O nly the even regis ters ( 00h, 0 2h, etc .) are valid. Odd acce sses ar e con-
sidered invalid and return 0000h.
Audio o utpu t frame slot 1 com munic ates control regi ster a ddress and wr ite/rea d com mand infor ma-
tion to the STAC9750/9751.
The first bit (MSB) sampled by ST AC9750/9751 indicates whether the current control transaction is a
read or a write operation. The following 7 bit positions communicate the targeted control register
address . The tr ail ing 12 bit po si tio ns within the sl ot ar e Res erve d and mus t be st uffed with 0s by th e
AC'97 controller.
Table 11. Command Address Port Bit Assignments
Bit Description Comments
19 Read/Write command 1= read, 0=write
18:12 Control Register Index Sixty-four 16-bit locations, addressed on even byte boundaries
11:0 Reserved Stuffed with 0s
SYNC
BIT_CLK
SDATA_OUT slot1 slot2
End of previous audio fram e
valid
Frame
SYNC
asserted
first
SDATA_OUT
bit of frame
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5.1.1.2. Slot 2: Command Data Port
The com mand da ta port is used t o deliver 16- bit co ntrol registe r write d ata in th e event that the cur-
rent command port operation is a write cycle (as indicated by Slot 1, bit 19).
If the cur rent comman d port operat ion is a r ead cycle , then the ent ire slot tim e must be s tuffed with
0s by the AC'97 controller.
5.1.1.3. Slot 3: PCM Playback Left Channel
Audio output frame slot 3 is the composite digital audio left playback stream. In a typical “Games
Compatible” PC this slot is composed of standard PCM (.wav) output samples digitally mixed (on the
AC'97 controller or host processor) with music synthesis output samples. If a sample stream of reso-
lution less than 20-bits is transferred, the AC'97 controller must stuff all trailing non-valid bit positions
within this time slot with 0s.
5.1.1.4. Slot 4: PCM Playback Right Channel
Audio output frame slot 4 is the composite digital audio right playback stream. In a typical “Games
Compatible” PC this slot is composed of standard PCM (.wav) output samples digitally mixed (on the
AC'97 controller or host processor) with music synthesis output samples. If a sample stream of reso-
lution less than 20-bits is transferred, the AC'97 controller must stuff all trailing non-valid bit positions
within this time slot with 0s.
5.1.1.5. Slot 5: Reserved
Audio output frame slot 5 is Reserved for modem operation and is not used by the STAC9750/9751.
5.1.1.6. Slot 6: PCM Center Channel
Audio ou tpu t frame slot 6 is the com pos i te d ig ital au dio c en ter s tream used in a mul ti -cha nnel a ppl i-
catio n where the STAC9750/97 51 is progra mme d to accept the prima ry DAC P CM da ta from s lots 6
and 9. Please refer to the register programming section for details on the multi-channel programming
options.
5.1.1.7. Slot 7: PCM Left Surround Channel
Audio output frame slot 7 is the composite digital audio left surround stream. In the default state, the
STAC9750/9751 accepts PCM data from slots 7 and 8 for the surround DACs, for output to the
DAC_OUT pins. As a programming option, PCM data from slots 7 and 8 may be used to supply data
to the primary DACs when slots 6 and 9 are used to drive the surround DACs. Please refer to the
register programming section for details on the multi-channel programming options.
Table 12. Command Data Port Bit Assignments
Bit Description Comments
19:4 Control Register Write Data Stuffed with 0s if current operation is a read
3:0 Reserved Stuffed with 0s
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5.1.1.8. Slot 8: PCM Right Surround Channel
Audio output frame slot 8 is the composite digital audio right surround stream. As a programming
option , PCM d ata from sl ots 7 and 8 may be us ed to s upply da ta to th e primary DACs. Pleas e refer
to the register programming section for details on the multi-channel programming options.
5.1.1.9. Slot 9: PCM Low Frequency Channel
Audio output frame slot 9 is the composite digital audio low frequency stream used in a multi-channel
application where the STAC9750/9751 is programmed to accept the primary DAC PCM data from
slots 6 and 9. Pleas e refer to th e register programmi ng secti on for details on the mul ti-channel pro-
gramming options.
5.1.1.10. Slot 10: PCM Alternate Left
Audio output frame slot 10 is the composite digital audio alternate left stream used in a multi-channel
applications. Please refer to the register programming section for details on the multi channel pro-
gramming options.
5.1.1.11. Slot 11: PCM Alternate Right
Audio outp ut frame slot 11 is the c om pos it e dig ital au dio alternate right str ea m us ed i n a mu lti -chan-
nel applications. Please refer to the register programming section for details on the multi channel
programmi ng opti ons .
5.1.1.12. Slot 12: Reserved
Audio output frame slot 12 is Reserved for modem operations and is not used by the STAC9750/
9751.
5.1.2. AC-Link Audio Input Frame (SDATA_IN)
The audio input frame data streams correspond to the multiplexed bundles of all digital input data
targeting the AC'97 controller. As is the case for audio output frame, each AC-Link audio input frame
consis ts of twelv e 20- bit time slots. S lot 0 i s a spec ial R eser ved time slot c ontainin g 16 bi ts that ar e
used for AC-Link protocol infrastructure.
Within slot 0, the first bit is a global bit (SDATA_IN slot 0, bit 15) which flags whether the STAC9750/
9751 is in the “CODEC Ready” state or not. If the “CODEC Ready” bit is a 0, this indicates that
STAC9750/9751 is not ready for normal operation. This condition is normal following the d e-asser-
tion of power on reset, for example, while STAC9750/9751’s voltage references settle. When the
AC-Link “CODEC Rea dy” i ndicator bit is a 1, it i ndica tes that the AC-L ink and STAC 9750/97 51 con-
trol/status registers are in a fully operational state. The AC'97 controller must further probe the Pow-
erdown Control Status Register (refer to Mixer Register section) to determine exactly which
subsections, if any, are ready.
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Prior to any attempts at putting STAC9750/9751 into operation the AC'97 controller should poll the
first bit in the audio in put frame ( SDATA_I N slot 0, bit 15) for an indi catio n that STAC9750/9751 has
become “CODEC Ready”. Once the STAC9750/9751 is sampled “CODEC Ready”, the next 12 bit
positions sampled by the AC'97 controller indicate which of the corresponding 12 time slots are
assigned to input data streams, and that they contain valid data. The following diagram illustrates the
time slot based AC-Link protocol.
Figure 14. STAC9750/9751 Audio Inpu t Frame
A new audio input fram e begins w ith a low to hi gh transiti on of SYNC. SYNC is sync hronous to th e
rising edge of BIT_CLK. Immediately following the falling edge of BIT_CLK, the STAC9750/9751
samples the assertion of SYNC. This falling edge marks the time when both sides of AC-Link are
aware of the start of a ne w audio fram e. On the nex t risi ng of BIT_CL K, the S TAC97 50/9751 transi-
tions SDATA_IN into the first bit position of slot 0 (“CODEC Ready” bit). Each new bit position is pre-
sente d to AC-Link on a risi ng edge of BIT_CLK a nd subsequent ly sample d by the AC'97 controll er
on the following falling edge of BIT_CLK. This sequence ensures that data transitions, and subse-
quent sample points for both incoming and outgoing data streams are time aligned.
Figure 15. Start of an Audio Input Frame
SDATA_IN's composite stream is MSB justified (MSB first) with all non-valid bit positions (for
assign ed and/or unassign ed time sl ots) stuffed with 0s by STAC 9750/ 9751. SDATA _IN data is sam-
pled on the falling edges of BIT_CLK.
5.1.2.1. Slot 1: Status Address Port
The status port i s used to mon itor status for STAC975 0/9751 func tions i ncluding, but not limited to,
mixer settings and power management.
SYNC
BIT_CLK
SDATA_IN slot1 slot2
End of previous audio frame
slot(12) "0" 19
Data Phase
20.8 uS (48 kHZ)Tag Phase
12.288 MHz
Time Slot "Valid" Bits Slot 1 Slot 2 Slot 3 Slot 12
("1" = time slot contains va l id PCM data)
valid "0" 19 19"0"
Frame 19"0" "0""0" "0"
SYNC
BIT_CLK
SDATA_IN slot1 slot2
End of previous audio fram e
Codec
Ready
SYNC
asserted
first
SDATA_OUT
bit of fram e
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Audio input frame slot 1’s stream echoes the control register index, for historical reference, for the
data to be returned in slot 2. (Assuming that slots 1 and 2 had been tagged “valid” by STAC9750/
9751 during slot 0.)
The first bit (MSB) generated by STAC9750/9751 is always stuffed with a 0. The following 7 bit posi-
tions communicate the associated control register address, and the trailing 12 bit positions are
stuffed with 0 by the STAC9750/9751.
5.1.2.2. Slot 2: Status Data Port
The status data port delivers 16-bit control register read data.
If Slot 2 is tagged “invalid” by STAC9750/9751, then the entire slot will be stuffed with 0's.
5.1.2.3. Slot 3: PCM Record Left Channel
Audio input frame slot 3 is the left channel output of STAC9750/9751 input MUX, post-ADC.
STAC9750/9751 ADCs are implemented to support 18-bit resolution.
STAC9750/9751 outputs its ADC data (MSB first), and stuffs any trailing non-valid bit positions with 0
to fill out its 20-bit time slot.
5.1.2.4. Slot 4: PCM Record Right Channel
Audio input frame slot 4 is the right channel output of STAC9750/9751 input MUX, post-ADC.
STAC9750/9751 outputs its ADC data (MSB first), and stuffs any trailing non-valid bit positions with 0
to fill out its 20-bit time slot.
5.1.2.5. Slot 5: Reserved
Audio i nput fram e slot 5 i s Reserved f or modem operation and is not used by the STA C9750/9751 .
This slot is always stuffed with 0.
Table 13. Status Address Port Bit Assignments
Bit Description Comments
19 Reserved Stuffed with 0
18:12 Control Register Index Echo of register index for which data is being returned
11:2 Slot Request see sections below
1:0 Reserved Stuffed with 0
Table 14. Status Data Port Bit Assignments
Bit Description Comments
19:4 Control Register Read Data Stuffed with 0 if tagged “invalid”
3:0 Reserved Stuffed with 0
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5.1.2.6. Slot 6: PCM Left Record Channel
Audio input frame slot 6 is the left channel output of STAC9750/9751 input MUX, post-ADC.
STAC9750/9751 ADCs are implemented to support 18-bit resolution.
STAC9750/9751 outputs its ADC data (MSB first), and stuffs any trailing non-valid bit positions with 0
to fill out its 20-bit time slot.
See section 6.5.25; page 51 for slot configurations and register settings.
5.1.2.7. Slot 7: PCM Left Record Channel
Audio input frame slot 7 is the left channel output of STAC9750/9751 input MUX, post-ADC.
STAC9750/9751 ADCs are implemented to support 18-bit resolution.
STAC9750/9751 outputs its ADC data (MSB first), and stuffs any trailing non-valid bit positions with 0
to fill out its 20-bit time slot.
See section 6.5.25; page 51 for slot configurations and register settings.
5.1.2.8. Slot 8: PCM Right Record Channel
Audio input frame slot 8 is the right channel output of STAC9750/9751 input MUX, post-ADC.
STAC9750/9751 ADCs are implemented to support 18-bit resolution.
STAC975 0/9751 o utputs its ADC data (MS B first), and st uffs any trail ing non-val id bit positi ons with
0's to fill out its 20-bit time slot.
See section 6.5.25; page 51 for slot configurations and register settings.
5.1.2.9. Slot 9: PCM Right Record Channel
Audio input frame slot 9 is the right channel output of STAC9750/9751 input MUX, post-ADC.
STAC9750/9751 ADCs are implemented to support 18-bit resolution.
STAC9750/9751 outputs its ADC data (MSB first), and stuffs any trailing non-valid bit positions with 0
to fill out its 20-bit time slot.
See section 6.5.25; page 51 for slot configurations and register settings.
5.1.2.10. Slot 10: PCM Left Record Channel
Audio input frame slot 10 is the left channel output of STAC9750/9751 input MUX, post-ADC.
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STAC9750/9751 ADCs are implemented to support 18-bit resolution.
STAC9750/9751 outputs its ADC data (MSB first), and stuffs any trailing non-valid bit positions with 0
to fill out its 20-bit time slot.
See section 6.5.25; page 51 for slot configurations and register settings.
5.1.2.11. Slot 11: PCM Right Record Channel
Audio input frame slot 11 is the right channel output of STAC9750/9751 input MUX, post-ADC.
STAC9750/9751 ADCs are implemented to support 18-bit resolution.
STAC9750/9751 outputs its ADC data (MSB first), and stuffs any trailing non-valid bit positions with 0
to fill out its 20-bit time slot.
See section 6.5.25; page 51 for slot configurations and register settings.
5.1.2.12. Slot 12: Reserved
Audio input frame slot 12 is Reserved for modem operation and is not used by the STAC9750/9751.
This slot is always stuffed with 0.
5.2. AC-Link Low Power Mode
The STAC9750/9751 AC-Link can be placed in the low power mode by programming register 26h to
the appropriate value. Both BIT_CLK and SDATA_IN will be brought to, and held at a logic low volt-
age le ve l. The AC'97 cont ro ll er ca n wake u p th e S TAC 97 50/9 751 by pr ovidi ng the a ppr op ri ate reset
signals.
Figure 16. STAC9750/9751 Powerdown Timing
BIT_CLK and SDATA_IN are transitioned low im mediately (wit hin the maximum specified time) fol-
lowing the de co de of the write to the Power down Reg ister (2 6h) with PR4 . When the AC'97 control-
ler driver is at the point where it is ready to program the AC-Link into its low power mode, slots (1
and 2) a re as sume d to be th e o nly v al id st ream in the audio ou tpu t fr am e ( al l so urce s of audio i npu t
have been neutr aliz ed).
SYNC
BIT_CLK
SDATA_OUT
Note: B IT_C LK not to scale
SDATA_IN
TAG Write to
0x20
slot 2
per
frame
DATA
PR4
TAG
slot 2
per
frame
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The AC'97 controller should also drive SYNC, and SDATA_OUT low after programming the
STAC9750/9751 to this low power mode.
5.3. Waking up the AC-Link
Once the STAC9750/9751 has halte d BIT_CL K, there are only two wa ys to “wake up” the AC- Link.
Both meth ods mus t be activa ted by th e AC'97 c ontroller. The A C-Link proto col prov ides for a “Cold
AC'97 Reset”, and a “Warm AC'97 Reset”. The current power down state would ultimately dictate
which form of reset is appropriate. Unless a “cold” or “register” reset (a write to the Reset register) is
performed, wherein the AC'97 registers are initialized to their default values, registers are required to
keep state during all power down modes. Once powered down, re-activation of the AC-Link via
re-asserti on of the SYNC si gnal must not occu r for a m inimum o f 4 audio frame t imes fol lowing th e
frame in which the power down was triggered. When AC-Link powers up it indicates readiness via
the CODEC Ready bit (input slot 0, bit 15).
Cold Reset - a cold reset is achieved by asserting RESET# for the minimum specified time, and
then bringing RESET# back HIGH. The reset occurs on the rising edge when RESET# is deas-
serted. By asserting and deasserting RESET#, BIT_CLK and SDATA_IN will be activated, or re-acti-
vated as the cas e may be , and al l S TA C97 50/ 9751 c ontr ol regi st er s wi ll be in iti aliz ed to their defaul t
power-on-reset values.
Note: RESET# is an asynchronous input. (# denotes active low)
Warm Reset - a warm reset will re-activate the AC-Link without altering the current STAC9750/9751
register values. A warm reset is signaled by driving SYNC high for a minimum of 1 µs in the absence
of BIT_CLK.
Note: Within normal audio frames, SYNC is a synchronous input. However, in the absence of BIT_CLK,
SYNC is treated as an asynchronous input used in the generation of a warm reset to the STAC9750/
9751.
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6. STAC9750/9751 MIXER
The STA C9750/9 751 in clud es analo g and digital mixer s for maxim um flexibi lity. The anal og mixe r is
designed to the AC'97 specification to manage the playback and record of all digital and analog
audio sources in the PC environment. The analog mixer also includes several extensions of the
AC’97 sp ecificatio n to support “al l analog record” capability as we ll as “POP BYPASS” mode f or all
digital playback. The analog sources include:
•System Audio: digital PCM input and output for business, games and multimedia
•CD/DVD: analog CD/DVD-ROM audio with internal connections to CODEC mixer
•Mono microphone: choice of desktop microphone, with programmable boost and gain
•Speakerphone: use of system microphone and speakers for telephone, DSVD, and video con-
ferencing
•Video: TV tuner or video capture card with internal connections to CODEC mixer
•AUX/synth: analog FM or wavetable synthesizer, or other internal source
The digital mixer includes inputs for the PCM DAC and the recorded ADC output
Figure 17. STAC9750 2-Channel Mixer Functional Diagram
Σ
0Ah
0Ch
0Eh
10h
12h
16h
14h
PC_BEEP
Phone
CD
AUX
VIDEO
LINEIN
MIC1
MIC2
20h:D8 20 or
30 dB
Σ
AllAnalog
vs
AllRecord
6Eh:D12
-6dB
Σ
MUX
ADC
04h
Mono
Volume
Master
Volume 3D LINE_OUT
3D HP_OUT
02h
06h
MUX
Σ
1Ch
20h:D15
Analog
Audio
Sources
Slot
Select
Slot
Select
MUX
PCM to
SPDIF SPDIF
PCMOut
2Ah:D5-D4
28h: D5-D4
PCMIn
Ganged3DControl
20h:D13
22h:D2-D3
1Ah
-6dB
MonoAnalog
StereoAnalog
Digital
KEY
20h:D9
ADCRecord
6E:D2
MUX
vol mute
vol mute
vol mute
vol mute
vol mute
vol mute
vol mute
vol mute
MUX
DAC
3D Record
Volume
6Ah:D1
18h
Headphone
Volume
MONO_OUT
0Eh:D6
Slot
Select
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Figure 18. STAC9751 2-Channel Mixer Functional Diagram
Source Function Connection
PC_BEEP PC BEEP pass through to LINE_OUT From PC_BEEP output
PHONE MONO input From telephony subsystem
MIC1 Desktop microphone From microphone jack
MIC2 Second microphone From second microphone jack
LINE_IN External audio source From line-in jack
CD Audio from CD-ROM Cable from CD-ROM
VIDEO Audio from TV tuner or video camera Cable from TV or VidCap card
AUX Upgrade synth or other external source Internal connector
PCM o ut Digital aud io out put from AC'97 Contro ller AC-Link
Destination Function Connection
HP_OUT Stereo mix of all sources To headphone out jack
LINE_OUT Stereo mix of all sources To output jack
MONO_OUT Microphone or MONO Analog mixer output To telephony subsystem
PCM in Digital data from the CODEC to the AC'97 Controller AC-Link
SPDIF SPDIF digital audio output To SPDIF output connecto r
Σ
0Ah
0Ch
0Eh
10h
12h
16h
14h
PC_BEEP
Phone
CD
AUX
VIDEO
LINEIN
MIC1
MIC2
20h:D8
Σ
AllAnalog
vs
AllRecord
6Eh:D12
-6dB
Σ
MUX
04h
Mono
Volume
Master
Volume
02h
06h
MUX
Σ
1Ch
20h:D15
Analog
Audio
Sources
1Ah
-6dB
MonoAnalog
StereoAnalog
Digital
KEY
20h:D9
ADCRecord
0Eh:D6
MUX
vol mute
vol mute
vol mute
vol mute
vol mute
vol mute
vol mute
vol mute
MUX
3D Record
Volume +6dB
-6dB
-6dB
-6dB
-6dB
-6dB
-6dB
18h
Headphone
Volume
-6dB
20 or
30 dB
6E:D2
Slot
Select
Slot
Select
MUX
PCMOut
2Ah:D5-D4
DAC
ADC
3D LINE_OUT
3D HP_OUT
PCMIn
Ganged3DControl
20h:D13
22h:D2-D3
MONO_OUT
Slot
Select
28h: D5- D4 PCM to
SPDIF SPDIF
6Ah:D1
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6.1. Analog Mixer Input
The mixer provides recording and playback of any audio sources or ou tput mix of all sources. The
STAC9750/9751 supports the following input sources:
• Any mono or stereo source
• Mono or stereo mix of all sources
• Two-channel input with mono output reference (microphone + stereo mix)
Note: A ll unus ed in puts shou ld be t ied tog ether c onnec ted to g round th rough a ca pacito r (0.1
µ
F sugges ted).
6.2. Analog Mixer Output
The mixer generates three distinct outputs:
• A stereo mix of all sources for output to the LINE_OUT and HP_OUT
• A stereo mix of all analog sources for recording
• Microphone only or mono mix of all sources for MONO_OUT
Note: Mono output of stereo mix is attenuated by -6 dB.
6.3. SPDIF Digital Mux
The STAC9750/97 51 inc orpo ra tes a di gital o utpu t th at supports SPDIF forma ts. A m ul tip lex er d eter -
mines which of two digital input streams are used for the digital output conversion process. These
two streams include the PCM OUT data from the audio controller and the ADC recorded output. The
normal analog LIN E_OUT si gnal can be conv erted to the SPDIF fo rmats by usi ng the in ternal ADC
to record the “MIX” outp ut, which is the combina tio n of all analog and all digital so urce s. In the cas e
of digital controllers with support for 4 or more channels, the SPDIF output mode can be used to sup-
port compressed 6-channel output streams for delivery to home theater systems. These can be
routed on al ternate AC -Link slots to the SPDIF outpu t, while the standa rd 2-channe l output is de liv-
ered as selected by bits D5 and D4 in Register 6E. If the digital controller supports 6 channels, a
SPDIF ou tput with 4 anal og channels ca n also be con figured (in a m ulti-CODEC setup). For more
informat ion for SPDIF please see 6.5.12.2; page 44.
Pin 48: To Enable SPDIF, use an 1 KΩ-10 KΩ external pulldown. To Disable SPDIF, use an
1KΩ-10 KΩ external pullup. Do NOT leave Pin 48 floating.
6.4. PC Beep Implem entation
PC Beep is active on power up and defaults to an un-muted state. The PC_BEEP input is routed
directly to the MONO_OUT, LINE_OUT and HP_OUT pins of the CODEC. Because th e PC_BEEP
input drive is often a full scale digital signal, some resistive attenuation of the PC_BEEP input is rec-
ommend ed to keep t he beep tone within reas onabl e volum e leve ls. Th e user sho uld mute th is inpu t
before using any other mixer input because the PC Beep input can contribute noise to the lineout
during no rmal ope ra tio n. T his s ty le o f PC B eep is re la ted to the A C’97 Specific atio n Rev 2.2 . To us e
the analog PC B eep, a value of 00h to bits F[7 :0](D[12:5]) di sables the Digital PC Beep genera tion.
PV[3:0] (D[4:1]) controls the volume level from 0 to 45dB of attenuation in 3dB steps.
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6.5. Programming Registers
* Register 74h is used for GPIO control in revision CA3.
Table 15. Programming Registers
Address Name Default Location
00h Reset 6990h 6.5.1; page 35
02h Master Volume 8000h 6.5.2.1; page 35
04h HP_OUT Mixer Volume 8000h 6.5.2.2; page 35 and 35
06h Master Volume MONO 8000h 6.5.2.3; page 36
0Ah PC Beep Mixer Vo lume 0000h 6.5.3; page 36
0Ch Phone Mixer Volume 8008h 6.5.4.1; page 37
0Eh Microphone Mixer Volume 8008h 6.5.4.2; page 37
10h Line In M ixer Volume 8808h 6.5.4.3; page 37
12h CD Mixer Volume 8808h 6.5.4.4; page 38
14h Video Mixer Volume 8808h 6.5.4.5; page 38
16h Aux Mixer Volume 8808h 6.5.4.6; page 38
18h PCM Out Mixer V olume 8808h 6.5.4.7; page 38
1Ah Record Select 0000h 6.5.5; page 38
1Ch Record Gain 8000h 6.5.6; page 39
20h General Purpose 0000h 6.5.7; page 39
22h 3D Control 0000h 6.5.8; page 40
24h Audio Interrupt 0000h 6.5.9; page 41
26h Powerdown Control/Status 000Fh 6.5.10; page 41
28h Extended Audio ID 0205h 6.5.11; page 42
2Ah Extended Audio Control/Status 0400h 6.5.12; page 44
2Ch PCM DAC Rate BB80h 6.5.14; page 46
32h PCM LR ADC Rate BB80h 6.5.15 ; p age 46
3Ah SPDIF Control 2A00h 6.5.16; page 46
3Eh Extended Modem Control/Status 0100h 6.5.17; page 47
4Ch GPIO Pin Configuration 0003h 6.5.18; page 47
4Eh GPIO Pin Polarity/Type FFFFh 6.5.19; page 48
50h GPIO Pin Sticky 0000h 6.5.20; page 48
52h GPIO Wake-up 0000h 6.5.21; page 49
54h GPIO Pin Status 0000h 6.5.22; page 49
6Ah Digital Audio Control 0000h 6.5.16; page 46
6Ch Revision Code 00xxh 6.5.24; page 51
6Eh Analog Special 0000h 6.5.25; page 51
70h 72h Enable 0000h 6.5.25.6 ; pa ge 53
72h Analog Current Adjust 0000h 6.5.25.7; page 53
74h* GPIO Current Access 0000h 6.5.26; page 54
76h 78h Enable 0000h 6.5.27.1 ; pa ge 54
78h Clo ck Access 0000h 6.5.27.2; page 55
7Ch Vendor ID1 8384h 6.5.28.1; page 5 5
7Eh Vendor ID2 76x xh 6.5.28.2; page 55
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6.5.1. Reset (00h)
Default: 6990h
Writing any value to this register performs a register reset, which causes all registers to revert to
their default values. Reading this register returns the ID code of the part.
6.5.2. Play Master Volume Registers (Index 02h, 04h, and 06h)
These registers manage the output signal volumes. Register 02h controls the stereo LINE_OUT
master vol ume (both right and left channels), register 04h controls the Headphone Out master vol-
ume, and register 06h controls the MONO volume output. Each step corresponds to 1.5 dB. The
MSB of the r egi s ter is the m ute bi t. W hen this bi t is set to 1 the le vel for that chann el i s set at -∞ dB.
ML5 through ML0 is for left channel level, MR5 through MR0 is for the right channel and MM5
through MM0 is f or the mo no out c hann el . W hen bi ts D5 and D13 are se t i n an y of thes e regis te rs i t
automatically writes all 1 to the next lower 5-bits.
The default value is 8000h for registers 02h, 04h, and 06h , which corresponds to 0 dB attenuation
with mute on.
6.5.2.1. Master Volume (02h)
Default: 8000h
Note: If optional bits D13 & D5 of register 02h are set to 1, then the corresponding attenuation is set to
46.5dB and the register reads will produce 1Fh as a value for this attenuation/gain block.
6.5.2.2. Headphone Out Volume (04h)
Default: 8000h
D15 D14 D13 D12 D11 D10 D9 D8
RSRVD4 SE4 SE3 SE2 SE1 SE0 ID9 ID8
D7 D6 D5 D4 D3 D2 D1 D0
ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
Table 16. Play Master Volume Register
Mute Mx5…Mx0 Function Range
0 00 0000 0dB Attenuation Req.
0 01 1111 46.5 Attenuation Req.
1 xx xxxx ∞ dB Attenuation Req.
D15 D14 D13 D12 D11 D10 D9 D8
Mute RSRVD ML5 ML4 ML3 ML2 ML1 ML0
D7 D6 D5 D4 D3 D2 D1 D0
Reserved MR5 MR4 MR3 MR2 MR1 MR0
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Note: If optional bits D13 & D5 of register 04h are set to 1, then the corresponding attenuation is set to
46.5dB and the register reads will produce 1Fh as a value for this attenuation/gain block.
6.5.2.3. Master Volume MONO (06h)
Default: 8000h
Note: If op tional bit D5 of r egiste r 06h i s se t to 1, then t he cor resp ondin g atten uation is s et to 4 6.5dB a nd the
register reads will produce 1Fh as a value for this attenuation/gain block.
6.5.3. PC Beep Mixer Volume (Index 0Ah)
Default: 0000h
Note: PC_BEEP defaults to 0000h, mute off.
This reg ister c ontrols th e leve l for the PC Beep i nput. Eac h step c orrespond s to appr oximatel y 3dB
of attenuation. The MSB of the register is the mute bit. When this bit is set to 1, the level for that
channel is set at -∞dB. PC_BEEP supports motherboard implementations. The intention of routing
PC_BEEP through the STAC9750/9751 mixer is to eliminate the requirement for an onboard
speaker by guaranteeing a connection to speakers connected via the output jack. In order for this to
be viable , the PC_BEEP si gnal needs to reac h the output jack at al l times. NOTE: the P C_BEEP is
routed to the mono outputs when the STAC9750/9751 is in a RESET state. This is so that Power On
Self Test (POST) codes can be heard by the user in ca se of a hardware problem with the PC. For
further PC_BEEP implementation details please refer to the AC'97 Technical FAQ sheet. The default
value is 0000h, which corresponds to 0 dB attenuation with mute off.
D15 D14 D13 D12 D11 D10 D9 D8
Mute RSRVD HPL5 HPL4 HPL3 HPL2 HPL1 HPL0
D7 D6 D5 D4 D3 D2 D1 D0
Reserved HPR5 HPR4 HPR3 HPR2 HPR1 HPR0
D15 D14 D13 D12 D11 D10 D9 D8
Mute Reserved
D7 D6 D5 D4 D3 D2 D1 D0
Reserved MM5 MM4 MM3 MM2 MM1 MM0
D15 D14 D13 D12 D11 D10 D9 D8
Mute Reserved
D7 D6 D5 D4 D3 D2 D1 D0
Reserved PV3 PV2 PV1 PV0 RSRVD
Table 17. PC_BEEP Register
Mute PV3…PV0 Function
0 0000 0 dB Attenuation
0 1111 45 dB Attenuation
1xxxx ∞ dB Attenuation
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6.5.4. Analog Mixer Input Gain Registers (Index 0Ch - 18h)
These regi st ers c on tro l th e gain/attenuati on fo r eac h of the anal og inp uts. Each s tep corr esponds to
approxima tely 1.5 d B. The MSB of the regi ster is the mu te bit. Wh en this b it is set to 1 the level for
that channel is set at -∞ dB.
The default value for stereo registers is 8808h, corresponding to 0 dB gain with mute on.
6.5.4.1. Phone Mixer Volume (0Ch)
Default: 8008h
6.5.4.2. Mic Mixer Volume (0Eh)
Default: 8008h
Register 0Eh (Mic V olume Register) Bit D6 is the Mic boost enable. To select between 20dB or 30dB
Mic Boost, see register 6Eh, D2 in section 6.5.25; page 51.
6.5.4.3. Line In Mixer Volume (10h)
Default: 8808h
Table 18. Analog Mixer Input Gain Register
Mute Gx4…Gx0 Function
0 0 0000 +12 dB gain
0 0 1000 0 dB gain
0 1 1111 -34.5 dB gain
D15 D14 D13 D12 D11 D10 D9 D8
Mute Reserved
D7 D6 D5 D4 D3 D2 D1 D0
Reserved GN4 GN3 GN2 GN1 GN0
D15 D14 D13 D12 D11 D10 D9 D8
Mute Reserved
D7 D6 D5 D4 D3 D2 D1 D0
RSRVD BOOST_EN RSRVD GN4 GN3 GN2 GN1 GN0
D15 D14 D13 D12 D11 D10 D9 D8
Mute Reserved GL4 GL3 GL2 GL1 GL0
D7 D6 D5 D4 D3 D2 D1 D0
Reserved GR4 GR3 GR2 GR1 GR0
STAC9750/9751
VALUE-LINE TWO-CHANNEL AC’97 CODECS PC AUDIO
IDT™
38 STAC97 50/9751 V 5.8 1031 06
VALUE-LI NE TWO-CHANNEL AC’97 CODECS
6.5.4.4. CD Mixer Volume (12h)
Default: 8808h
6.5.4.5. Video Mixer Volume (14h)
Default: 8808h
6.5.4.6. AUX Mixer Volume (16h)
Default: 8808h
6.5.4.7. PCM Out Mixer Volume (18h)
Default: 8808h
6.5.5. Record Select (1Ah)
Default: 0000h (corresponding to Mic in)
D15 D14 D13 D12 D11 D10 D9 D8
Mute Reserved GL4 GL3 GL2 GL1 GL0
D7 D6 D5 D4 D3 D2 D1 D0
Reserved GR4 GR3 GR2 GR1 GR0
D15 D14 D13 D12 D11 D10 D9 D8
Mute Reserved GL4 GL3 GL2 GL1 GL0
D7 D6 D5 D4 D3 D2 D1 D0
Reserved GR4 GR3 GR2 GR1 GR0
D15 D14 D13 D12 D11 D10 D9 D8
Mute Reserved GL4 GL3 GL2 GL1 GL0
D7 D6 D5 D4 D3 D2 D1 D0
Reserved GR4 GR3 GR2 GR1 GR0
D15 D14 D13 D12 D11 D10 D9 D8
Mute Reserved GL4 GL3 GL2 GL1 GL0
D7 D6 D5 D4 D3 D2 D1 D0
Reserved GR4 GR3 GR2 GR1 GR0
D15 D14 D13 D12 D11 D10 D9 D8
Reserved SL2 SL1 SL0
D7 D6 D5 D4 D3 D2 D1 D0
Reserved SR2 SR1 SR0
STAC9750/9751
VALUE-LINE TWO-CHANNEL AC’97 CODECS PC AUDIO
IDT™
39 STAC97 50/9751 V 5.8 1031 06
VALUE-LI NE TWO-CHANNEL AC’97 CODECS
Used to select the record source independently for right and left.
6.5.6. Record Gain (1Ch)
Default: 8000h (corresponding to 0 dB gain with mute on)
The 1Ch regis ter ad justs the ster eo input record ga in. Each s tep corr espond s to 1.5dB . 22.5dB cor-
responds to 0F0Fh. The MSB of the register is the mute bit. When this bit is set to 1, the level for that
channel(s) is set at -∞dB.
6.5.7. General Purpose (20h)
Default: 0000h
Table 19. Record Select Control Registers
Bit(s) Reset Name Description
15:11 0 Reserved Bits not used, should read back 0
10:8 0 SL2:SL0
Left Channel Input Select
000 = Mic
001 = CD In (left)
010 = Video In (left)
011 = Aux In (left)
100 = Line In (left)
101 = Stereo Mix (left)
110 = Mono Mix
111 = Phone
7:3 0 Reserved Bits not used, should read back 0
2:0 0 SR2:SR0
Right Channel Input Select
000 = Mic
001 = CD In (right)
010 = Video In (right)
011 = Aux In (right)
100 = Line In (right)
101 = Stereo Mix (right)
110 = Mono Mix
111 = Phone
D15 D14 D13 D12 D11 D10 D9 D8
Mute Reserved GL3 GL2 GL1 GL0
D7 D6 D5 D4 D3 D2 D1 D0
Reserved GR3 GR2 GR1 GR0
Table 20. Record Gain Registers
Mute Gx3… Gx0 Function
0 1111 +22.5 dB gain
0 0000 0 dB gain
1xxxx-∞ gain
D15 D14 D13 D12 D11 D10 D9 D8
POP BYP RSRVD 3D Reserved MIX MS
D7 D6 D5 D4 D3 D2 D1 D0
LPBK Reserved
STAC9750/9751
VALUE-LINE TWO-CHANNEL AC’97 CODECS PC AUDIO
IDT™
40 STAC97 50/9751 V 5.8 1031 06
VALUE-LI NE TWO-CHANNEL AC’97 CODECS
This register is used to control some miscellaneous functions. Below is a summary of each bit and its
function. The MS bit controls the MIC selector. The LPBK bit enables loopback of the ADC output to
the DAC input without involving the AC-Link, allowing for full system performance measurements.
6.5.8. 3D Control (22 h)
Default: 0000h
This regi ster is used to c ontrol the 3D ster eo enha nceme nt function , IDT S urround 3D (SS3D), b uilt
into the AC'97 c omp one nt. Note tha t reg is ter b its DP 3-DP 2 a re used to co ntr ol th e separa tio n r at ios
in the 3D control for LINE_OUT. SS3D provides for a wider soundstage extending b eyond the nor-
mal 2-speaker arrangement. Note that the 3D bit in the general purpose register (20h) must be set to
1 to enable SS3D functionality and for the bits in 22h to take effect.
The three separation ratios are implemented as shown in Table 22. The separation ratio defines a
series of equations that determine the amount of depth difference (High, Medium, and Low) per-
ceived during two-channel playback. The ratios provide for options to narrow or widen the sound-
stage.
Table 21. General Purpose Register
Bit Function
3D 3D Stereo Enhancement ON/OFF - 1 = on
MIX Mono output select - 0 = Mix, 1= Mic
MS Mic select - 0 = Mic1, 1 = Mic2
POP BYP DAC bypasses mixer and connects directly to Line Out
LPBK ADC/DAC loopback mode
D15 D14 D13 D12 D11 D10 D9 D8
Reserved
D7 D6 D5 D4 D3 D2 D1 D0
Reserved DP3 DP2 Reserved
Table 22. 3D Control Registers
DP3, DP2 LINE_OUT SEPARATION RATIO
0 0 0 (Off)
0 1 3 (Low)
1 0 4.5 (Med)
1 1 6 (High)
STAC9750/9751
VALUE-LINE TWO-CHANNEL AC’97 CODECS PC AUDIO
IDT™
41 STAC97 50/9751 V 5.8 1031 06
VALUE-LI NE TWO-CHANNEL AC’97 CODECS
6.5.9. Audio Interrupt (24h)
Default: 0000h
6.5.10. Powerdown Ctrl/Stat (26h)
Default: 000Fh
D15 D14 D13 D12 D11 D10 D9 D8
I4 I3 Reserved I0 Reserved
D7 D6 D5 D4 D3 D2 D1 D0
Reserved
Bit(s) Reset
Value R/W Name Description
15 0 RW I4
0 = Interrupt is clear
1 = Interrupt is set
Interrupt event is cleared by writing a 1 to this bit.
The interrupt bit will change regardless of condition of interrupt enable (I0) status.
An interrupt in the GPI in slot 12 in the AC-Link will follow this bit change when
interrupt enable (I0) is unmasked.
14 0 RO I3
Interrupt Cause
0 = No Interrupt Caused
1 = Change in GPIO input status
These bits will reflect the general cause of the first interrupt event generated. It
sh ould be read after interrupt status has b een confirmed as interrupting. The
information should be used to scan possible interrupting events in proper pages.
13-12 0 RW Reserved Bits not used, should read back 0
11 0 RW I0
Interrupt Enable
0 = Interrupt generation is masked.
1 = Interrupt generation is un-masked.
The driver sh ould no t un -mask the i nterrupt unless ensure d by the AC ‘97 cont roller
that no conflict is possible with modem slot 12 - GPI functionality. Some AC’97 2.2
complia nt c ont roll ers do not su ppo rt a udi o C O DEC in terru pt i nfra stru ctu re. In e ithe r
ca se, S/W should poll the interrupt status after init iating a sense cycle and wait for
Sense Cycle Max Delay to determine if an interrupting event has occurred.
10:0 0 RO Reserved Bits not used, should read back 0
D15 D14 D13 D12 D11 D10 D9 D8
EAPD PR6 PR5 PR4 PR3 PR2 PR1 PR0
D7 D6 D5 D4 D3 D2 D1 D0
Reserved REF ANL DAC ADC
STAC9750/9751
VALUE-LINE TWO-CHANNEL AC’97 CODECS PC AUDIO
IDT™
42 STAC97 50/9751 V 5.8 1031 06
VALUE-LI NE TWO-CHANNEL AC’97 CODECS
This read/write register is used to program power down states and monitor subsystem readiness.
The EAPD external control is also supported through this register.
6.5.10.1. Ready Status
The lower half of this register is read only status, a 1 indicating that the subsection is ready. Ready is
defined as the subsection's ability to perform in its nominal state. When this register is written, the bit
values that come in on AC-Link will have no effect on read only bits 0-7.
When the AC-Link “CODEC Ready” indicator bit (SDATA_IN slot 0, bit 15) is a 1, it indicates that the
AC-Link and AC'97 co ntrol and status regist ers are in a ful ly operationa l state. The AC'97 cont roller
must fur the r pr ob e th is P owe rdown Con tr ol/Status Reg is ter to determine exac tl y whi ch s ubs ec tions ,
if any are ready. When this register is written, the bit values that come in on AC-Link will have no
effect on read only bits 0-7.
6.5.10.2. Powerdown Controls
The STAC9750/9751 is capable of operating at reduced power when no activity is required. The
state of power down is controlled by the Powerdown Register (26h). See the section “Low Power
Modes” for more information.
6.5.10.3. External Amplifier Power Down Control
The EA PD bit 1 5 of the Powerdown Control/Status Re gister ( Index 26h ) direct ly cont rols the o utput
of the EAP D ou tput (pin 4 5), and prod uces a lo gi ca l 1 when this bi t is s et t o lo gi c h igh . T hi s func tio n
is used to control an external audio amplifier power down. EAPD = 0 places approximately 0V on the
output pin, enabling an external audio amplifier. EAPD = 1 places approximately DVdd on the output
pin, disabling the external audio amplifier. Audio amplifiers that operate with reverse polarity will
likely require an external inverter to maintain software driver compatibility.
6.5.11. Extended Audio ID (28h)
Default: 0605h
Table 23. Powerdown Status Registers
Bit Function
EAPD External Amplifier Power Down
REF VREF’s up to nominal level
ANL Analog mixers, etc. ready
DAC DAC section ready to playback data
ADC ADC section ready to playback data
D15 D14 D13 D12 D11 D10 D9 D8
ID1 ID0 Reserved REV1 REV0 AMAP LDAC
D7 D6 D5 D4 D3 D2 D1 D0
SDAC CDAC DSA1 DSA0 VRM SPDIF DRA VRA
STAC9750/9751
VALUE-LINE TWO-CHANNEL AC’97 CODECS PC AUDIO
IDT™
43 STAC97 50/9751 V 5.8 1031 06
VALUE-LI NE TWO-CHANNEL AC’97 CODECS
The Ex tended Audi o ID regi ster is a read- only registe r, except fo r bits D 5:D4. ID1 an d ID0 e cho th e
configuration of the CODEC as defined by the programming of pins 45 and 46 externally. A returned
00 defines the CODEC as the primary CODEC, while any other code identifies the CODEC as one of
three secondary CODEC possibilities. SDAC = 0 tells the controller that the STAC9750/9751 is a
two-chan nel CODEC as defined by the Intel specif ication. The AM AP bit, D9, will return a 1 indicat-
ing that the CODEC supports the optional “AC’97 2.2 compliant AC-link slot to audio DAC map-
pings”. The default condition assumes that 00 are loaded in the DSA0 and DSA1 bits of the
Extended Audio ID (Ind ex 28h). With 0 0 in the DSAx bits, t he CODEC slot assi gnments are as per
the AC’97 specification recomme ndations. If the DSAx bits do not contain 00, the slot assignments
are as pe r the table in the sec tion describ ing the Extended Audio ID (Ind ex 28h). The VR A bit, D0,
will return a 1 indicating th at the CODEC supports the optional variable sample rate conversion as
defined by the AC’97 specification.
1. External CID pin status (from analog) these bits are the logical inversion of the pin polarity (pin
45-46). These bits are zero if XTAL_OUT is grounded with an alternate external clock source in
primary mode only. Secondary mode can either be through BIT CLK driven or 24 MHz clock
driver with XTAL_OUT floating/shorted.
2. If pin 48 is held high at powerup, this bit will be held to zero, to indicate the SPDIF is not avail-
able. Pin 48: To Enable SPDIF, use an 1 KΩ-10 KΩ external pulldown. To Disable SPDIF, use an
1KΩ-10 KΩ external pullup. Do NOT leave Pin 48 floating.
Table 24. Extended Audio ID
Bit Name Access Reset Value Function
15:14 ID [1,0] Read only variable 00 = XTAL_OUT grounded (Note 1)
CID1#, CID0# = XTAL_OUT cry stal or floating
13:12 Reserved Read only 00 Reserved
11:10 Rev[1:0] Read only 01 Indicates CODEC is AC’97 Rev 2.2 compliant
9 AMAP Read only 1 Multi-channel slot support (Always = 1)
8 LDAC Read only 0 Low Frequency Effect, not supported (Always=0)
7 SDAC Read only 0 Surround DAC, not supported (Always = 0)
6 CDAC Read only 0 Center channel, not supported (Always = 0)
5:4 DSA [1,0] Read/Write 00
DAC slot ass ign me nt
If CID[1:0] = 00 then DSA[1:0] resets to 00
If CID[1:0] = 01 then DSA[1:0] resets to 01
If CID[1:0] = 10 then DSA[1:0] resets to 01
If CID[1:0] = 11 then DSA[1:0] resets to 10
00 = left slot 3, right slot 4
01 = left slot 7, right slot 8
10 = left slot 6, right slot 9
11 = left slot 10, right slot 11
3 VRM Read only 0 Variable Sample Rate Mic, not supported (Always = 0)
2 SPDIF Read only 1 0 = SPDIF pulled high on reset, SPDIF disabled
1 = default, SPDIF enabled (Note 2)
1 DRA Read only 0 Double Rate Audio, not supported (Always = 0)
0 VRA Read only 1 Variable sample rates supported (Always = 1)
STAC9750/9751
VALUE-LINE TWO-CHANNEL AC’97 CODECS PC AUDIO
IDT™
44 STAC97 50/9751 V 5.8 1031 06
VALUE-LI NE TWO-CHANNEL AC’97 CODECS
6.5.12. Extended Audio Control/ Status (2Ah)
Default: 0400h
6.5.12.1. Variable Rate Sampling Enable
The Extended Audio S tatus Control register also contains one active bit to enable or disable the V ari-
able Sampling Rate capabilities of the DACs and ADCs. If the VRA, bit D0, is 1, the variable sample
rate control registers (2Ch and 32h) are active, and “on-demand” slot data required transfers are
allowed. If the VRA bit is 0, the DACs and ADCs will operate at the default 48 KHz data rate.
The STAC9750/9751 supports “on-demand” slot request flags. These flags are passed from the
CODEC to the AC’97 controller in every audio input frame. Each time a slot request flag is set (active
low) in a give n audi o frame, th e contr oller will pass th e next PCM sample fo r the corres pondi ng slot
in the audio frame that immediately follows. The VRA enable bit must be set to 1 to enable
“on-demand” data transfers. If the VRA enable bit is not set, the CODEC will default to 48 KHz trans-
fers and every audio frame will include an active slot request flag and data is transferred every
frame.
For var ia ble s am pl e r at e o utpu t, the CODEC e xam in es i ts sa mpl e ra te co ntrol r eg ist ers , th e state of
the FIFOs, and the incoming SDATA_OUT tag bits at the beginning of each audio output frame to
determine which SLOTREQ bits to set active (low). SLOTREQ bits are asserted during the current
audio in put frame for active output slots, which will require da ta i n the next audio output frame.
For va riable sam ple rate inpu t, the tag bit for e ach input s lot indica tes whether v alid data is pre sent
or not. Thus, even in variable sample rate mode, the CODEC is always the master: for SDATA_IN
(CODEC to controller), the CODEC sets the TAG bit; for SDATA_OUT (controller to CODEC), the
CODEC sets the SLOTREQ bit and then checks for the TAG bit in the next frame. Whenever VRA is
set to 0, the PCM rate registers (2Ch and 32h) are overwritten with BB80h (48 KHz).
6.5.12.2. SPDIF
The SPDIF bit in the Extended Audio Status Control Register is used to enable and disable the
SPDIF functionality within the STAC9750/9751. If the SPDIF is set to a 1, then the function is
enabled and when set to a 0 it is disabled.
6.5.12.3. SPCV (SPDIF Configuration Valid)
The SPCV bit is rea d only and in dicat es wheth er or not the S PDIF system is se t up cor rectly. When
SPCV is a 0, it indicates the system configuration is invalid and valid if it is a 1.
D15 D14 D13 D12 D11 D10 D9 D8
Reserved SPCV Reserved
D7 D6 D5 D4 D3 D2 D1 D0
Reserved SPSA1 SPSA0 RSRVD SPDIF RSRVD VRA enable
STAC9750/9751
VALUE-LINE TWO-CHANNEL AC’97 CODECS PC AUDIO
IDT™
45 STAC97 50/9751 V 5.8 1031 06
VALUE-LI NE TWO-CHANNEL AC’97 CODECS
6.5.12.4. SPSA1, SPSA0 (SPDIF Slot Assignment)
SPSA1 and SPSA0 combine to provide the slot assignments for the SPDIF data. The following
details the slot assignment relationship between SPSA1 and SPSA0.
The STAC9750/9751 are AMAP compliant with the following table.
6.5.13. PCM DAC Rate Registers (2Ch and 32h)
The internal sample rate for the DACs and ADCs are controlled by the value in these read/write reg-
isters that c on tain a 16- bit uns ig ned val ue b etwe en 0 an d 655 35 r epres en tin g the con ve rsio n rate i n
Hertz (Hz). In VRA mode (register 2Ah bit D0 = 1), if the value written to these registers is supported,
that value wi ll be echoe d back wh en read , otherwise the clos est (hig her in the case of a tie) sampl e
rate is supported and returned. Per PC 99 / PC 2001 specification, independent sample rates are
supported for record and playback. Whenever VRA is set to 0, the PCM rate registers (2Ch and 32h)
will read back with BB80h (48 KHz).
Table 25. Slot assignment relationship between SPSA1 and SPSA0
SPSA[1,0] Slot Assignment Comments
00 3 & 4 SPDIF source data slot assignment
01 7 & 8 2-channel CODEC primary default
10 6 & 9 4-channel CODEC primary default
11 10 & 11 6-channel CODEC primary default
Table 26. STAC9750/9751 AMAP compliant
CODEC
ID Function SPSA = 00 SPSA = 01 SPSA = 10 SPSA = 11
00 2-channel Primary w/SPDIF 3 & 4 7 & 8* 6 & 9 10 & 11
01 2-channel Dock CODEC w/SPDIF 3 & 4 7 & 8 6 & 9* 10 & 11
10 +2-channel Surr w/ SPDIF 3 & 4 7 & 8 6 & 9* 10 & 11
11 +2-channel Cntr/LFE w/ SPDIF 3 & 4 7 & 8 6 & 9 10 & 11*
Note: * is the default slot assignment
Table 27. Hardware Supported Sample Rates
Sample Rate SR15-SR0 Value
8 KHz 1F40h
11.025 KHz 2B11h
16 KHz 3E80h
22.05 KHz 5622h
32 KHz 7D00h
44.1 KHz AC44h
48 KHz BB80h
STAC9750/9751
VALUE-LINE TWO-CHANNEL AC’97 CODECS PC AUDIO
IDT™
46 STAC97 50/9751 V 5.8 1031 06
VALUE-LI NE TWO-CHANNEL AC’97 CODECS
6.5.14. PCM DAC Rate (2Ch)
Default: BB80h
6.5.15. PCM LR ADC Rate (32h)
Default: BB80h
6.5.16. SPDIF Control (3Ah)
Default: 2A00h
Register 3Ah is a r ead/write register that co ntrols S PDIF functional ity an d manag es bit fi elds pro pa-
gated as c hannel status (or sub- frame in the V case ). With excepti on of V, thi s register shoul d only
be written to when the SPDIF transmitter is disabled (SPDIF bit register 2 Ah is 0). This ensures that
control an d s tatus inf or mati on start up co rre ctl y at t he begi nn ing of SP DIF transmis s ion. T he de faul t
is 2A00h which sets the SPDIF output sample rate at 48 KHz and the normal SPDIF expectations.
D15 D14 D13 D12 D11 D10 D9 D8
SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8
D7 D6 D5 D4 D3 D2 D1 D0
SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0
D15 D14 D13 D12 D11 D10 D9 D8
SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8
D7 D6 D5 D4 D3 D2 D1 D0
SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0
D15 D14 D13 D12 D11 D10 D9 D8
#V DRS SPSR1 SPSR2 L CC6 CC5 CC4
D7 D6 D5 D4 D3 D2 D1 D0
CC3 CC2 CC1 CC0 PRE COPY #PCM/AUDIO PRO
Table 28. SPDIF Control
Bit(s) Reset Access Name Description (note 1-2)
15 0 Read & Write #V Validity bit is set indicating each sub-frame’s samples are invalid. If
#V is 0, then it indicates that each sub-frame was transmitted and
received correctly by the interface.
14 0 Read Only DRS 1 = Double Rate SPDIF support (always = 0)
13:12 10 Read & Write SPSR[1,0]
SPDIF Sample Rate.
00 44.1 KHz Rate
01 Reserved
10 48 KHz Rate (default)
11 32 KHz Rate
11 0 Read & Write L Generat ion Le ve l i s def ine d b y the IEC s t an dard, or as appropriate .
(Always = 1)
STAC9750/9751
VALUE-LINE TWO-CHANNEL AC’97 CODECS PC AUDIO
IDT™
47 STAC97 50/9751 V 5.8 1031 06
VALUE-LI NE TWO-CHANNEL AC’97 CODECS
1. If pin 48 is held high at powerup, 28h D2 will be low indicating no SPDIF available and the regis-
ter 3Ah will then read back 0000h. Pin 48: To Enable SPDIF, use an 1 KΩ-10 KΩ external pull-
down. To Disable SPDIF, use an 1 KΩ-10 KΩ external pullup. Do NOT leave Pin 48 floating.
2. Bits D15, D13-D00 of this register cannot be written to without first setting Reg 2Ah bit D2 = 0
(SPDIF disabled) and Register 28h bit D2 = 1 (SPDIF available).
6.5.17. Extended Modem S tatus and Control Register (3Eh)
Default: 0100h
6.5.18. GPIO Pin Configurati on Register (4Ch)
Default: 0003h
10:4 0 Read & Write CC[6, 0] Category Cod e is de fin ed by the IEC st andard or as approp ria te by
media.
3 0 Read & Write PRE 0 = 0 µsec Pre-emphasis
1 = Pre-emphasis is 50/15 µsec
2 0 Read & Write COPY 0 = Copyright not asserted
1 = Copyright is asserted
1 0 Read & Wr ite /AUDIO 0 = PCM data
1 = Non-Audio or non-PCM format
0 0 Read & Write PRO 0 = Consumer use of the channel
1 = Professional use of the channel
D15 D14 D13 D12 D11 D10 D9 D8
Reserved PRA
D7 D6 D5 D4 D3 D2 D1 D0
Reserved GPIO
Table 29. Extended Modem Status and Control
Bit(s) Access Reset Value Name Description
15:9 Read Only 0 Reserved Bit not used, should read back 0
8 Read / Write 1 PRA 0 = GPI O powe red up / enabled
1 = GPIO powered down / disabled
7:1 Read Only 0 Reserved Bit not used, should read back 0
0 Read Only 0 GPIO 0 = GPIO not ready (powered down)
1 = GPIO ready (powered up)
D15 D14 D13 D12 D11 D10 D9 D8
Reserved
D7 D6 D5 D4 D3 D2 D1 D0
Reserved GC1
(GPIO1) GC0
(GPIO0)
Table 28. SPDIF Control (Continued)
Bit(s) Reset Access Name Description (note 1-2)
STAC9750/9751
VALUE-LINE TWO-CHANNEL AC’97 CODECS PC AUDIO
IDT™
48 STAC97 50/9751 V 5.8 1031 06
VALUE-LI NE TWO-CHANNEL AC’97 CODECS
6.5.19. GPIO Pin Polarity/Type Register (4Eh)
Default: FFFFh
6.5.20. GPIO Pin Sticky Register (50h)
Default: 0000h
Table 30. GPIO Pin Configuration Register
Bit(s) Access Reset Value Name Description
15:2 Read Only 0 Reserved Bit not used, should read back 0
1 Read / Write 1 GC1 0 = GPIO1 configured as outp ut
1 = GPIO1 configured as input
0 Read / Write 1 GC0 0 = GPIO0 configured as outp ut
1 = GPIO0 configured as input
D15 D14 D13 D12 D11 D10 D9 D8
Reserved
D7 D6 D5 D4 D3 D2 D1 D0
Reserved GP1
(GPIO1) GP0
(GPIO0)
Table 31. GPIO Pin Polarity/Type Register
Bit(s) Access Reset Value Name De scription
15:2 Read Only 0 Reserved Bit not used, should read back 0
1 Read / Write 1 GP1 0 = GPIO1 Input Polarity Inverted, CMOS output drive.
1 = GPIO1 Input Polarity Non-inverted, Open-Drain output drive.
0 Read / Write 1 GP0 0 = GPIO0 Input Polarity Inverted, CMOS output drive.
1 = GPIO0 Input Polarity Non-inverted, Open-Drain output drive.
D15 D14 D13 D12 D11 D10 D9 D8
Reserved
D7 D6 D5 D4 D3 D2 D1 D0
Reserved GS1
(GPIO1) GS0
(GPIO0)
Table 32. GPIO Pin Sticky Register
Bit(s) Access Reset Value Name Description
15:2 Read Only 0 Reserved Bit not used, should read back 0
1 Read / Write 0 GS1 0 = GPIO1 Non Sticky configuration.
1 = GPIO1 Sticky configuration.
0 Read / Write 0 GS0 0 = GPIO0 Non Sticky configuration.
1 = GPIO0 Sticky configuration.
STAC9750/9751
VALUE-LINE TWO-CHANNEL AC’97 CODECS PC AUDIO
IDT™
49 STAC97 50/9751 V 5.8 1031 06
VALUE-LI NE TWO-CHANNEL AC’97 CODECS
6.5.21. GPIO Pin Mask Register (52h)
Default: 0000h
6.5.22. GPIO Pin Status Register (54h)
Default: 0000h
D15 D14 D13 D12 D11 D10 D9 D8
Reserved
D7 D6 D5 D4 D3 D2 D1 D0
Reserved GW1
(GPIO1) GW0
(GPIO0)
Table 33. GPIO Pin Mask Register
Bit(s) Access Reset Value Name Description
15:2 Read Only 0 Reserved Bit not used, should read back 0
1 Read / Write 0 GW1 0 = GPIO1 interrupt not passed to GPIO_INT slot 12.
1 = GPIO1 interrupt is passed to GPIO_INT slot 12.
0 Read / Write 0 GW0 0 = GPIO0 interrupt not passed to GPIO_INT slot 12.
1 = GPIO0 interrupt is passed to GPIO_INT slot 12.
D15 D14 D13 D12 D11 D10 D9 D8
Reserved
D7 D6 D5 D4 D3 D2 D1 D0
Reserved GI1
(GPIO1) GI0
(GPIO0)
STAC9750/9751
VALUE-LINE TWO-CHANNEL AC’97 CODECS PC AUDIO
IDT™
50 STAC97 50/9751 V 5.8 1031 06
VALUE-LI NE TWO-CHANNEL AC’97 CODECS
6.5.23. Digital Audio Control (6Ah)
Default: 0000h
This read/write register is used to program the digital mixer input status. In the default state, the PCM
DAC path is enabled and the ADC record inputs are disabled.
The DO1 and DO0 bits control the input source for the PCM to digital output converters. The table
describes the available options.
Table 34. GPIO Pin Status Register
Bit(s) Access Reset Value Name Description
15:2 Read Only 0 Reserved Bit not used, should read back 0
1 Read / Write x GI1
When GPIO1 is configured as output and Register 74h bit[0] = 0
(default), the value of this register will be placed on the GPIO1 pad.
When GPIO1 is configured as output and Register 74h bit[0] =1, the
GPIO1 pad will get its value from slot12.
When GPIO 1 is config ured as in put and confi gured as a sti cky wri tin g
a 1 does nothing, writing a 0 clears this bit.
When GPIO1 is configured as input this register reflects the value on
the GPIO1 pad after interpretation of the polarity and sticky
configurations.
0 Read / Write x GI0
When GPIO0 is configured as output and Register 74h bit[0] = 0
(default), the value of this register will be placed on the GPIO0 pad.
When GPIO0 is configured as output and Register 74h bit[0] =1, the
GPIO0 pad will get its value from slot12.
When GPIO 0 is config ured as in put and confi gured as a sti cky wri tin g
a 1 does nothing, writing a 0 clears this bit.
When GPIO0 is configured as input this register reflects the value on
the GPIO0 pad after interpretation of the polarity and sticky
configurations.
D15 D14 D13 D12 D11 D10 D9 D8
Reserved
D7 D6 D5 D4 D3 D2 D1 D0
Reserved DO1 DO0
Table 35. Digital Audio Control Register
Bit(s) Reset Name Description
15:2 0 Reserved Bits not used, should read ba ck 0
10 DO1 SPDIF Digital Output Source Selection:
DO1 = 0; PCM data from the AC-Link to SPDIF
DO1 = 1; ADC record data to SPDIF
0 0 DO0 Always read s zero
STAC9750/9751
VALUE-LINE TWO-CHANNEL AC’97 CODECS PC AUDIO
IDT™
51 STAC97 50/9751 V 5.8 1031 06
VALUE-LI NE TWO-CHANNEL AC’97 CODECS
6.5.24. Revision Code (6Ch)
Default: 00xxh
The devi ce Revision Code re gister (index 6Ch) contains a software readab le revision-s pecific code
used to identify performance, architectural, or software differences between various device revi-
sions. Bits 7:0 of the Revision Code register are user readable; bits 15:8 are not used at this time
and will r etu rn zer os when read . This va lu e ca n be u se d by the a udi o driv er, or m inipo rt driv er in th e
case of WIN98® WDM approaches, to adjust software functionality to match the feature-set of the
STAC9750/9751. This will allow the software driver to identify any required operational differences
between the existing STAC9750/9751 and future versions.
6.5.25. Analog Special (6Eh)
Default: 0000h
The Analog Special register has several bits used to control various functions specific to the
STAC9750/9751.
6.5.25.1. ALL MIX
The AC’97 ALL_MIX, bit D12 of register 6Eh, controls the record source when the Stereo Mix option
is selected for recording. If the AC’97 mode is default logic 1, the “Stereo Mix Record” option will
include the sum of the analog sources with or without 3D enhancement, and the main PCM DAC
output. If the “AL L Analog Record” option is se lected, the Stereo Mi x Record option wi ll include the
sum of the analog sources only, with or without 3D enhancement. The “AC’97 mode” is useful for
recor ding all soun d sources. The “ALL A nalog Record” mode is us eful in co njunction with the POP
BYPASS mode for recording all analog sources, which are often further processed and combined
with other PCM data to be output directly to the DAC outputs which are configured in POP_BYPASS
mode using the General Purpose register (index 20h).
D15 D14 D13 D12 D11 D10 D9 D8
00000000
D7 D6 D5 D4 D3 D2 D1 D0
00000000
D15 D14 D13 D12 D11 D10 D9 D8
Reserved AC97 ALL MIX Reserved
D7 D6 D5 D4 D3 D2 D1 D0
RSVD MUTE FIX
DISABLE ADCSLT1 ADCSLT0 Reserved 20/30 SEL SPLYOVR EN SPLYOVR
VAL
STAC9750/9751
VALUE-LINE TWO-CHANNEL AC’97 CODECS PC AUDIO
IDT™
52 STAC97 50/9751 V 5.8 1031 06
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6.5.25.2. ADC Data on AC LINK
Bits D5-D4 select slots for ADC data on ACLINK.
6.5.25.3. MuteFix Disable
Bit D6 controls the enable and disable of the MuteFix functions.
• 0 = MUTE FIX Enabled
•1 = MUTE FIX Disabled
When this bit is zero, and either channel is set to -46.5dB attenuation (1Fh), then that channel is fully
muted. When this bit is one, then operation is per AC’97 specification.
This bit is reserved in revisions prior to CC1.
6.5.25.4. Mic Boost Select
The Mic boost value can be selected with bit D2, which in enabled by Register 0Eh, bit D6. W riting a
zero to bit D2 will provide 20dB of Mic Boost. Writing a one will provide 30dB of Mic Boost.
6.5.25.5. Supply Override Select
The Supp ly Override b it, D1, allows o verri de of the supply detect. Writing a z ero disables t he over-
ride on su pply detect. Writi ng a one, override s supply detect with bit D0 . Bit D0 provides the supply
override value. A zero forces 3.3 V analog operation and one forces 5 V analog operation.
Table 36. ADC data on AC LINK
Value Function
00 left s lot 3, right sl ot 4
01 left s lot 7, right sl ot 8
10 left s lot 6, right sl ot 9
11 left slot 10, right slot 11
Table 37. Mic Boost Select
Value Function
0 20dB
1 30dB
STAC9750/9751
VALUE-LINE TWO-CHANNEL AC’97 CODECS PC AUDIO
IDT™
53 STAC97 50/9751 V 5.8 1031 06
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6.5.25.6. 72h Enable (70h)
Default: 0000h
6.5.25.7. Analog Current Adjust (72h)
Default: 0000h
The Ana log Curr ent Ad just r egister (in dex 72h) is a lock ed regis ter a nd ca n only be pr operly writte n
and read from when ABBAh has been written into register 70h. The IBIASx bits allow the analog cur-
rent to be adjusted with minimal reduction in performance. A lower analog current setting is NOT
recomm ended wh en a 5V a nalog s upply is used . A lowe r setting for 3.3 V supp lies is reco mmende d
for notebook computers to reduce power consumption to its lowest level.
6.5.25.8. Internal Power-On/Off Anti-Pop Circuit
The STAC9 750/9751 include s an internal power supply anti-pop circuit that prevents audib le clicks
and pops from b eing heard whe n the CODEC i s powered on an d off. This functio n is accompl ished
by delay ing the charge/dis charge of the VREF capacitor (Pin 2 7). CVREF val ue of 1 µF will cause a
turn-on delay of roughly 3 seconds, which will allow the power supplies to stabilize before the
CODEC outputs are enabled. The delay can be extended to 30 seconds if a value of CVREF value of
10 µF is used. The CODEC outputs are also ke pt stable for the same amou nt of time at power-off to
allow the s ystem to b e gracefully tu rned off. The INT_A POP bit D7 of register 72 h allows t his delay
circuit t o be bypassed fo r rapid produc tion testing. Any external component an ti-pop circui t is unaf-
fected by the internal circuit.
D15 D14 D13 D12 D11 D10 D9 D8
EN15 EN14 EN13 EN12 EN11 EN10 EN9 EN8
D7 D6 D5 D4 D3 D2 D1 D0
EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0
D15 D14 D13 D12 D11 D10 D9 D8
Reserved
D7 D6 D5 D4 D3 D2 D1 D0
INT APOP Reserved IBIAS1 IBIAS0 RSVD
Table 38. Analog Current Adjust
IBIAS1 IBIAS0 Analog Current
0 0 Normal Current
0 1 80% of nominal Analog Current
1 0 120% of nominal Analog Current
1 1 140% of nominal Analog Current
STAC9750/9751
VALUE-LINE TWO-CHANNEL AC’97 CODECS PC AUDIO
IDT™
54 STAC97 50/9751 V 5.8 1031 06
VALUE-LI NE TWO-CHANNEL AC’97 CODECS
6.5.26. GPIO Access Register (74h)
Default: 0800h
The GPIO Access Register requires that the output enable bits (D11, D9 and D8) be used in con-
junctio n with the data sou rce select ion (input or o utput) for t he EAPD, GPIO0 a nd GPIO1 (p ins 47,
43 and 44 res pectively). For exampl e, to use GPIO1 as an out put, set D9 = 1 to enable the outpu t,
and use D13 to write the o utput value desired. To use GPIO1 a s an input, set D9 = 0 to disable th e
output, and use D13 to read the input value.
6.5.27. High Pass Filter Bypass (Index 76h and 78h)
The High Pass Filter Bypass register (index 78h) is a locked register and can only be properly written
and read from when ABBAh has been writt en into regi ster 76h. Bit D0 co ntrols the Hi gh Pass Fil ter
Bypass. Default is zero which provides for normal operation where the high pass filter is active. Writ-
ing a one, will disable, or bypass the ADC high pass filter.
6.5.27.1. 78h Enable (76h)
Default: 0000h
D15 D14 D13 D12 D11 D10 D9 D8
EAPD Reserved GPIO1 GPIO0 EAPD_OEN Reserved GPIO1_OEN GPIO0_OEN
D7 D6 D5 D4 D3 D2 D1 D0
Reserved
Table 39. GPIO Access Registers (74h)
Bit(s) Reset Value Name Description
15 0 EAPD EAPD data output on EAPD when bit D11 = 1
EAPD data input from pin when bit D11 = 0
14 0 Reserved Reserved
13 0 GPIO1 GPIO1 data output on GPIO1 when bit D9 = 1
GPIO1 data input from pin when bit D9 = 0
12 0 GPIO0 GPIO0 data output on GPIO0 when bit D8 = 1
GPIO0 data input from pin when bit D8 = 0
11 1 EAPD_OEN 0 = EAPD data out disabled
1 = EAPD data output enabled
10 0 Reserved Reserved
90GPIO1_OEN
0 = GPIO1 data out disabled
1 = GPIO1 data output enabled
80GPIO0_OEN
0 = GPIO0 data out disabled
1 = GPIO0 data output enabled
7:0 0 Reserved Reserved
D15 D14 D13 D12 D11 D10 D9 D8
EN15 EN14 EN13 EN12 EN11 EN10 EN9 EN8
D7 D6 D5 D4 D3 D2 D1 D0
EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0
STAC9750/9751
VALUE-LINE TWO-CHANNEL AC’97 CODECS PC AUDIO
IDT™
55 STAC97 50/9751 V 5.8 1031 06
VALUE-LI NE TWO-CHANNEL AC’97 CODECS
6.5.27.2. ADC High Pass FIlter Byp a ss(78h)
Default: 0000h
6.5.28. Vendor ID1 and ID2 (Index 7Ch and 7Eh)
These two registers contain four 8-bit ID codes. The first three codes have been assigned by
Microsoft using their Plug and Play Vendor ID methodology. The fourth code is an IDT assigned
code iden tifyin g the STAC9750/975 1. The ID1 reg ister (ind ex 7Ch) contains the valu e 8384h, wh ich
is the first (8 3h) and sec ond (84h ) characte rs of the Micr osoft ID code. The ID2 register (index 7E h)
contains the value 7650h, which is the third (76h) of the Microsoft ID code, and 50h which is the
STAC975 0/97 51 ID code .
Note: The lower half of the Vendor ID2 register (index 7Eh) currently contains the value xxh identifying the
STAC9750/9751. This value can be used by the audio driver, or miniport driver in the case of WIN98®,
to adjust software functionality to match the feature-set of the STAC9750/9751. This portion of the
register will likely contain different values if the software profile of the STAC9750/9751 changes, as in
the case of sil icon level device modi fic ati ons . This will al low the so ftware dri ver to ide nti fy an y requ ired
operational differences between the existing STAC9750/9751 and any future versions.
6.5.28.1. Vendor ID1 (7Ch)
Default: 8384h
6.5.28.2. Vendor ID2 76xx (7Eh)
Default: 7650h
D15 D14 D13 D12 D11 D10 D9 D8
Reserved
D7 D6 D5 D4 D3 D2 D1 D0
Reserved ADC HPF BYP
D15 D14 D13 D12 D11 D10 D9 D8
10000011
D7 D6 D5 D4 D3 D2 D1 D0
10000100
D15 D14 D13 D12 D11 D10 D9 D8
01110110
D7 D6 D5 D4 D3 D2 D1 D0
01010000
STAC9750/9751
VALUE-LINE TWO-CHANNEL AC’97 CODECS PC AUDIO
IDT™
56 STAC97 50/9751 V 5.8 1031 06
VALUE-LI NE TWO-CHANNEL AC’97 CODECS
7. LOW POWER MODES
The STAC9750/9751 is capable of operating at reduced power when no activity is required. The
state of po wer-d own is contr ol le d by the Powerd own Registe r (2 6h). T h er e are 7 c omm and s o f s ep-
arate power down. The power down options are listed in Table 40. The first three bits, PR0..PR2, can
be used individually or in combination with each other, and control power distribution to the ADCs,
DACs and Mixer. The last analog power control bit, PR3, affects analog bias and reference voltages,
and can only be used in combination with PR0, PR1, and PR2. PR3 essentially removes power from
all analog sections of the CODEC, and is generally only asserted when the CODEC will not be
needed for long periods. PR0 and PR1 control the PCM ADCs and DACs only. PR2 and PR3 do not
need to be “set” before a PR4, but PR0 and PR1 must be “set” before PR4. PR5 disables the internal
CODEC cl ock and requ ires an exter nal cold reset for recove ry. P R6 disables t he headphone dr iver
amplifier for additional analog power saving.
The Figur e 19 illus trate s one ex ample procedu re to do a complete p ower do wn of STAC 9750/ 9751.
From nor mal operati on, s equenti al wri tes to t he Powerdow n Regi ster are p erfor med t o powe r down
STAC975 0/9751 a pie ce at a time. After eve rything has bee n shut off, a final write (of P R4) can be
executed to shut d own the AC -Link. T he part will remain in sleep mode with all its regi sters ho lding
their static values. To wake up, the AC'97 controller will send an extended pulse on the sync line,
issuing a warm reset. This will restart the AC-Link (resetting PR4 to zero). The STAC9750/9751 can
also be wok en up with a cold reset. A cold r eset will reset all of the reg isters to their defaul t states .
When a section is powered back on, the Powerdown Control/Status register (index 26h) should be
read to verify that the section is ready (stable) before attempting any operation that requires it.
Figure 19. Example of STAC9750/9751 Powerdown/Powerup Flow
Table 40. Low Power Modes
GRP Bits Function
PR0 PCM in ADCs & Input Mux Powerdown
PR1 PCM out DACs Powerdown
PR2 Analog Mixer power down (VREF still on)
PR3 Analog Mixer power down (VREF off)
PR4 Digital Interface (AC-Link) power down (external clock off)
PR5 Internal Clock disable
PR6 Powerdown HEADPHONE_OUT
Warm Reset
Cold ResetReady =1
Normal ADCs off PR0 DACs off PR1 Analog off
PR2 or PR3 Digital I/F off
PR4 Shut off
AC-Link
Default
PR0=0 & ADC=1 PR1=0 & DAC=1 PR2=0 & ANL=1
PR0=1 PR1=1 PR2=1 PR4=1
STAC9750/9751
VALUE-LINE TWO-CHANNEL AC’97 CODECS PC AUDIO
IDT™
57 STAC97 50/9751 V 5.8 1031 06
VALUE-LI NE TWO-CHANNEL AC’97 CODECS
Figure 2 0 ill ustrates a state wh en all the mixer s sho uld wo rk w ith the static v olume setti ngs that are
contained in the ir ass oc iate d reg is ters . T his c on fig ur ation c an be u se d wh en p lay ing a CD ( or exter -
nal LINE_IN source) through STAC9750/9751 to the speakers, while most of the system in low
power mo de. T he proc edur e for thi s follo ws the pre vious e xcept th at the analog mix er is never shut
down.
Figure 20. STAC9750/9751 Powerdown/Powerup Flow With Analog Still Active
Warm Reset
Normal ADCs off PR0 DACs off PR1 Digital I/F off
PR4 Shut off
AC-Link
PR0=0 & ADC=1 PR1=0 & DAC=1
PR0=1 PR1=1 PR4=1
STAC9750/9751
VALUE-LINE TWO-CHANNEL AC’97 CODECS PC AUDIO
IDT™
58 STAC97 50/9751 V 5.8 1031 06
VALUE-LI NE TWO-CHANNEL AC’97 CODECS
8. MULTIPLE CODEC SUPPORT
The STAC9750/9751 pr ov id es s upp or t f or th e m ult i-CO DE C o ption ac co rd ing to th e I ntel A C'97 , r ev
2.2 specification. By definition there can be only one Primary CODEC (CODEC ID 00) and up to
three Second ary CO DECs (CO DEC IDs 01 , 10, and 11). The CODEC ID func tions as a chip select.
Seco ndary devices therefor e have comple tely orth ogonal reg ister sets; eac h is individ ually acces si-
ble and they do not share registers.
8.1. Primary/Secondary CODEC Selection
In a multi- CODEC environ ment the COD EC ID is provide d by externa l programming o f pins 45 an d
46 (CID0 and CID1). The CID pin elec trical function is logi cally inverte d fro m the COD EC ID desig-
nation. The corresponding pin state and its associated CODEC ID are listed in the “CODEC ID
Selecti on” table. Als o see slot a ssig nment discus sion, “ Multi -Channel Pr ogrammi ng Reg ister ( Index
74)”.
8.1.1. Primary CODEC Operation
As a Primary device the STAC9750/9751 is completely compatible with existing AC'97 definitions
and extensions. Primary CODEC registers are accessed exactly as defined in the AC'97 Component
Specification and AC'97 Extensions. The STAC9750/9751 operates as Primary by default, and the
external ID pins (45 and 46), have internal pull-ups so that these pins may be left as no-connects for
primar y operation.
When used as the Primary CODEC, the STAC9750/9751 generates the master AC-Link BIT_CLK
for both the AC'97 Digital Controller and any Secondary CODECs. The STAC9750/9751 can support
up to f our load s of 1 0 KΩ an d 50 p F on the BIT_ CLK li ne. T his is to ens ure tha t im pleme ntations o f
up to four CODECs will not load down the clock output.
8.1.2. Secondary CODEC Operation
When the STAC9750/9751 is configured as a Secondary device the BIT_CLK pin is configured as an
input at po wer up. Using the BIT_CLK provided by the Primary CODEC insures that everything on
the AC-Li nk will be synchron ous. As a Seconda ry device it can be de fined as CODEC ID 01 , 10 or
11 in the two-bit field(s) of the Extended Audio and/or Extended Modem ID Register(s).
Table 41. CODEC ID Selection
CID1 State CID0 St ate CODEC ID CODEC Status
DVdd or floating DVdd or floating 00 Primary
DVdd or floating 0 V 01 Seconda ry
0 V DVdd or floating 10 Secondary
0 V 0 V 11 Secondary
STAC9750/9751
VALUE-LINE TWO-CHANNEL AC’97 CODECS PC AUDIO
IDT™
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8.2. Secondary CODEC Register Access Definitions
The AC'97 Digital Controller can independently access Primary and Secondary CODEC registers by
using a 2-bit CODEC ID field (chip se lect) which is defined as the LSBs of Output Slot 0. For Sec-
ondary CODEC access, the AC'97 Digital Controller must invalidate the tag bits for Slot 1 and 2
Command A ddr es s and Data (Slot 0, bi ts 14 a nd 1 3) and pla ce a non-zero value ( 01, 10, o r 11) into
the CODEC ID field (Slot 0, bits 1 and 0).
As a S ec ond ary CO DEC, the S TA C97 50/ 9751 wi ll d isre gard the Comma nd Add re ss a nd Com man d
Data (Slot 0, b its 14 a nd 13) tag b its when it se es a 2-bit CO DE C ID va lu e ( Slot 0, bi ts 1 and 0) that
matches its configuration. In a sense the Secondary CODEC ID field functions as an alternative
Valid Command Address (for Secondary reads and writes) and Command Data (for Secondary
writes) tag indi cator.
Secondary CODECs must mon ito r the Frame Val id bit, and ig nor e the frame (regar dl es s of the state
of the Secondary CODEC ID bits) if it is not valid. AC'97 Digital Controllers should set the frame valid
bit for a frame with a secondary register access, even if no other bits in the output tag slot except the
Secondary CODEC ID bits are set.
This method is designed to be backward compatible with existing AC'97 controllers and CODECs.
There is no change to output Slot 1 or 2 definitions.
Table 42. Secondary CODEC Register Access Slot 0 Bit Definitions
Output Tag Slot (16-bits)
Bit Description
15 Frame Valid
14 Slot 1 Valid Command Address bit († Primary CODEC only)
13 Slot 2 Valid Command Data bit († Primary CODEC only)
12-3 Slot 3-12 Valid bits as defined by AC'97
2 Reserved (Set to 0)
†1-0 2-bit CODEC ID field (00 Reserved for Primary; 01, 10, 11 indicate Secondary)
Note: † New definitions for Secondary CODEC Register Access
STAC9750/9751
VALUE-LINE TWO-CHANNEL AC’97 CODECS PC AUDIO
IDT™
60 STAC97 50/9751 V 5.8 1031 06
VALUE-LI NE TWO-CHANNEL AC’97 CODECS
9. TESTABILITY
The STAC9750/9751 has two test modes. One is for ATE in-circuit test and the other is restricted for
IDT’s internal use. STAC9750/9751 enters the ATE in-circuit test mode if SDATA_OUT is sampled
high at the trailing edge of RESET#. Once in the ATE test mode, the digital AC-Link outputs
(BIT_CLK and SDATA_IN) are driven to a high impedance state. This allows ATE in-circuit testing of
the AC'97 controller. Use of the ATE test mode is the recommended means of removing the CODEC
from the AC-Link when another CODEC is to be used as the primary. This case will never occur dur-
ing standard operating conditions. Once either of the two test modes have been entered, the
STAC9750/9751 must be issued another RESET# with all AC-link signals held low to return to the
normal operating mode.
STAC9750/9751
VALUE-LINE TWO-CHANNEL AC’97 CODECS PC AUDIO
IDT™
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VALUE-LI NE TWO-CHANNEL AC’97 CODECS
10. PIN DESCRIPTION
Figure 21. STAC9750/9751 Pin Description Drawing
Pin 48:
To Enable SPDIF, use an 1 KΩ-10 KΩ external pulldown .
To Disable SPDIF, use an 1 KΩ-10 KΩ external pullup.
Do NOT leave Pin 48 floating.
The CD_GND signal is an AC signal return for the two CD input channels. It is normally biased at
about 2.5V. The na me of the pi n i n the AC 97 speci fic at ion is CD_GND, an d thi s has con fus ed m any
designers. It should not have any DC path to GND. Connecting the CD_GND signal directly to
ground wil l chan ge the inte rn al bias of the enti re CODE C, an d ca use si gni fic an t dist orti on. If ther e is
no analog CD input, then this pin can be No-Connect
DVdd1 1
XTL_IN 2
XTL_OUT 3
DVss1 4
SDATA_OUT 5
BIT_CLK 6
DVss2 7
SDATA_IN 8
DVdd2 9
SYNC 10
RESET# 11
PC_BEEP 12
24 LINE_IN
_R
23 LINE_IN
_L
22 MIC2
21 MIC1
20 CD_R
19 CD_GND
18 CD_L
17 VIDEO_R
16 VIDEO_L
15 AUX_R
14 AUX_L
13 PHONE
36 LINE_OUT_R
35 LINE_OUT_L
34 NC
33 NC
32 CAP2
31 NC
30 AFILT2
29 AFILT1
28 VREFout
27 VREF
26 AVss1
25 AVdd1
M
ONO_OUT 37
AVdd2 38
HP_OUT_L 39
HP_COMM 40
HP_OUT_R 41
AVss2 42
GPIO0 43
GPIO1 44
CID0 45
CID1 46
EAPD 47
SPDIF 48
48-Pin LQFP
STAC9750/9751
VALUE-LINE TWO-CHANNEL AC’97 CODECS PC AUDIO
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10.1. Digital I/O
These signals connect the STAC9750/9751 to its AC'97 controller counterpart, an external crystal,
multi-CODEC selection and external audio amplifier.
Table 43. Digital Connection Signals
Pin Name Pin # Type Description
XTL_IN 2 I 24.576 MHz Crystal or External Clock Source
XTL_OUT 3 I/O 24.576 MHz Crystal or ground if external clock source connected to XTAL_IN
SDATA_OUT 5 I Serial, time division multiplexed, AC'97 input stream
BIT_CLK 6 I/O 12.288 MHz serial data clock
SDATA__IN 8 O Serial, time division multiplexed, AC'97 output stream
SYNC 10 I 48 KHz fixed rate sample sync
RESET# 11 I AC'97 Master H/W Reset
NC 31 I/O No Connec t
NC 33 I/O No Connec t
NC 34 I/O No Connec t
GPIO0 43 I/O General Purpose I/O
GPIO1 44 I/O General Purpose I/O
CID0 45 I Multi-CODEC ID select - bit 0
CID1 46 I Multi-CODEC ID select - bit 1
EAPD 47 I/O External Amplifier Power Down
SPDIF 48 O
SPDIF digital output
Pin 48: - To Enable SPDIF, use an 1 KΩ-10 KΩ external pulldown.
To Disable SP DIF, use an 1 KΩ-10 KΩ external pullup.
Do NOT le ave Pin 48 floating.
STAC9750/9751
VALUE-LINE TWO-CHANNEL AC’97 CODECS PC AUDIO
IDT™
63 STAC97 50/9751 V 5.8 1031 06
VALUE-LI NE TWO-CHANNEL AC’97 CODECS
10.2. Analog I/O
These signals connect the STAC9750/9751 to analog sources and sinks, including microphones and
speakers.
* any unused input pins should be tied toget her through a capacitor (0.1 µF suggested ) to ground,
except the MIC inputs which should have their own capacitor to ground if not used.
†The CD_GND s ignal is an AC s ignal return for th e two CD input cha nnels. It is normal ly biased at
about 2.5 V. The name of the pin in the AC’97 specification is CD_GND, and this has confused many
designers. It should not have any DC path to GND. Connecting the CD_GND signal directly to
ground wil l chan ge the inte rn al bias of the enti re CODE C, an d ca use si gni fic an t dist orti on. If ther e is
no analog CD input, then this pin can be No-Connect
Table 44. Analog Connection Signals
Pin Name Pin # Type Description
PC-BEEP 12 I* PC Speaker beep pass-through
PHONE 13 I* From telephony subsystem speakerphone (or DLP - Down Line Phone)
AUX_L 14 I* Aux Left Channel
AUX_R 15 I* Aux Right Channel
VIDEO_L 16 I* Video Audio Left Channel
VIDEO_R 17 I* Video Audio Right Channel
CD_L 18 I* CD Audio Left Channel
CD_GND 19 I* CD Audio analog signal return †
CD_R 20 I* CD Audio Right Channel
MIC1 21 I* Desktop Microphone Input
MIC2 22 I* Second Microphone Input
LINE_IN _ L 23 I* Line In Left Chan nel
LINE_IN _ R 24 I* Line In Right Chan nel
LINE_OUT_L 35 O Line Out Left Channel
LINE_OUT_R 36 O Line Out Right Channel
MONO_OUT 37 O To telephony subsystem speakerphone (or DLP - Down Line Phone)
HP_OUT_L 39 O Headphone Out Left Channel
HP_COMM 40 O Headphone Ground Return
HP_OUT_R 41 O Headphone Out Right Channel
STAC9750/9751
VALUE-LINE TWO-CHANNEL AC’97 CODECS PC AUDIO
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10.3. Filter/References/GPIO
These sign als are co nnected to re sistors, capacitors , specific vo ltages, or pro vide Genera l Purpose
I/O.
10.4. Power and Ground Signals
Table 45. Filtering and Voltage References
Signal Name Pin Number Type D escription
VREF 27 O Analog ground (0.45 * Vdd, at 5 V; 0.41 * Vdd at 3 V)
VREFOUT 28 O Reference Voltage out 5 mA drive (intended for MIC bias) (~Vdd/2)
AFILT1 29 O Anti-Aliasing Filter Cap - ADC left channel
AFILT2 30 O Anti-Aliasing Filter Cap - ADC right channel
CAP2 32 O ADC reference Cap
Table 46. Power and Ground Signals
Pin Name Pin # Type Description
AVdd1 25 I Analog Vdd = 5.0 V or 3.3 V
AVdd2 38 I Analog Vdd = 5.0 V or 3.3 V (headphone power source)
AVss1 26 I Analog Gnd
AVss2 42 I Analog Gnd
DVdd1 1 I Digital Vdd = 3.3 V
DVdd2 9 I Digital Vdd = 3.3 V
DVss1 4 I Digital Gnd
DVss2 7 I Digital Gnd
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11. ORDERING INFORMATION
Ordering Information
NOTE: Whe n orde ring thes e parts the “yy” will be repla ced wi th the CODE C revis ion. Ad d an “R ” to
the end of any of these part numbers for delivery on Tape and Reel. The minimum order quantity for
Tape and Reel is 2,000 units.
Part Number Package Temp Range Supply Range
STAC9750XXTAEyy X 48-pin RoHS LQFP 7mm x 7mm x 1.4mm 0° C to + 70° C DVdd = 3.3V, AVdd = 5.0V
STAC9751XXTAEyy X 48-pin RoHS LQFP 7mm x 7mm x 1.4mm 0° C to + 70° C DVdd = 3.3V, AVdd = 3.3V
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12. PACKAGE DRAWINGS
12.1. 48-Pin LQFP
Figure 22. Package Drawing - 48-pin LQFP
Key LQFP Dimensions in mm
Min. Nom. Max.
A1.401.501.60
A1 0.05 0.10 0.15
A2 1.35 1.40 1.45
D8.809.009.20
D1 6.90 7.00 7.10
E8.809.009.20
E1 6.90 7.00 7.10
L0.450.600.75
e0.50
c0.09 - 0.20
b0.170.220.27
48 pin LQ FP
E
E1
D
D1
Pin 1
b
A
A2
A
1
c
e
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13. SOLDER REFLOW PROFILE
13.1. Standard Reflow Profile Data
Note: These devices can be hand soldered at 360 oC for 3 to 5 seconds.
FROM: IPC / JEDE C J-STD-0 20C “Moistur e/Reflow Sens itivity Classific ation for Nonh ermetic Solid
State Surface Mount Devices” (www.jedec.org/download).
Figure 23. Reflow Profile
Profile Feature Pb Free Assembly
Average Ramp-Up Rate (Tsmax - Tp) 3 oC / seco nd max
Preheat Temperature Min (Tsmin)
Temperature Max (Tsmax)
Ti me (tsmin - tsmax)
150 oC
200 oC
60 - 180 seconds
Time ma intained abo ve Temperature (TL)
Ti me (tL)217 oC
60 - 150 seconds
Peak / Classifi cation Tempe rature (Tp) See “Package Classi ficat ion Reflow Temperatures” on page 68.
Time within 5 oC of actual Peak Temperature (tp) 20 - 40 seconds
Ramp-Down rate 6 oC / second max
Time 25 oC to Peak Temperature 8 m inute s max
Note: All temperatures refer to topside of the package, measured on the package body surface.
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13.2. Pb Free Process - Package Classification Reflow Te mperatures
Package Type MSL Reflow Temperature
LQFP 48-pin 3 260 oC*
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14. APPENDIX A: SPLIT INDEPENDENT POWER SUPPLY OPERATION
In PC applications, one power supply input to the STAC9750/9751 may be derived from a supply
regulator (as shown in Figure 24) and the other directly from the PCI power supply bus. When power
is applied to the PC, the regulated supply input to the IC will be applied some time delay after the
PCI power supply. Without proper on-chip partitioning of the analog and digital circuitry, some manu-
facturer's CODECs would be subject to on-chip SCR type latch-up.
IDT’s STAC9750 /9751 s peci fically allows po wer- up sequenc ing de lays between the anal og (AVdd x)
and digital ( VDddx) supp ly pins. These two power suppli es can power-up independe ntly and at dif-
ferent rates with no adverse effects to the CODEC. The IC is designed with independent analog and
digital circuitry that prevents on-chip SCR type latch-up.
However, the STA C9750/9751 is not designed to operate for exten ded period s with only the an alog
supply active.
Note: Pin 48:
To Enable SPDIF, use a 1 K
Ω
-10 K
Ω
external pulldown.
To Disable SPDIF, use a 1 K
Ω
-10 K
Ω
external pullup.
Do NOT le ave Pin 48 floating.
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Figure 24. STAC9750/9751 Split Independent Power Supply Operation Typical Connection Diagram
0.1 µF 1 µ F 0.1 µ F 0.1 µF 10 µF 0.1 µF
*Suggested
AVdd1 AVdd2 DVdd1 DVdd2 XTL_IN
XTL_OUT
9
2
3
27 pF
27 pF
24.576 MHz
13825
PC_BEEP
12
PHONE
13
AUX_L
14
AUX_R
15
VIDEO_L
16
VIDEO_R
17
CD_L
18
CD_GND
19
CD_R
20
MIC1
21
MIC2
22
LINE_IN_L
23
LINE_IN_R
41
32
*OPTIONAL
0.1 µF 1 µF*
820 pF 29
30
820 pF
AVss1 AVss2
26 42 4 7
DVss1 DVss2 HP_OUT_R
*Terminate ground
plane as close to codec
as possible
Analog
Ground Digital
Ground
HP_OUT_L 39
37
MONO_OUT
36
LINE_OUT_R
35
LINE_OUT_L
43
44
40
48
34
33
31 0.1 µF 1 µ F*
27
VREFOUT
EAPD
CID1
CID0
28
47
46
45
11
RESET#
10
SYNC
24
BIT_CLK
SDATA_OUT 5
6
827 pF
22 Ω
EMI
Filter
3.3V ± 5%3.3V or 5V ± 5%
OPTIONAL
*OPTIONAL
CAP2
AFILT1
AFILT2
GPIO0
GPIO1
HP_COMM
SPDIF
NC
NC
NC
VREF
SDATA_IN
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15. APPENDIX B: PROGRAMMING REGISTERS
Note: All registers not shown, and those labeled “Reserved”, can be written to but are “Don’t Care” on read back.
Note: PC_BEEP defaults to 0000h, mute off.
Reg # Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default
00h Reset RSRVD SE4 SE3 SE2 SE1 SE0 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 6990h
02h Master Volume Mute RSRVD ML5 ML4 ML3 ML2 ML1 ML0 Reserved MR5 MR4 MR3 MR2 MR1 MR0 8000h
04h HP_OUT
Mixer Volume Mute RSRVD HPL5 HPL4 HPL3 HPL2 HPL1 HPL0 Reserved HPR5 HPR4 HPR3 HPR2 HPR1 HPR0 8000h
06h Master Volume
Mono Mute Reserved MM5 MM4 MM3 MM2 MM1 MM0 8000h
0Ah PC_BEEP
Volume Mute Reserved PV3 PV2 PV1 PV0 RSRVD 0000h
0Ch Phone Volume Mute Reserved GN4 GN3 GN2 GN1 GN0 8008h
0Eh Mic Volume Mute Reserved boosted RSRVD GN4 GN3 GN2 GN1 GN0 8008h
10h Line In Volume Mute Reserved GL4 GL3 GL2 GL1 GL0 Reserved GR4 GR3 GR2 GR1 GR0 8808h
12h CD Volume Mute Reserved GL4 GL3 GL2 GL1 GL0 Reserved GR4 GR3 GR2 GR1 GR0 8808h
14h Video Volume Mute Reserved GL4 GL3 GL2 GL1 GL0 Reserved GR4 GR3 GR2 GR1 GR0 8808h
16h AUX Volume Mute Reserved GL4 GL3 GL2 GL1 GL0 Reserved GR4 GR3 GR2 GR1 GR0 8808h
18h PCM Out
Volume Mute Reserved GL4 GL3 GL2 GL1 GL0 Reserved GR4 GR3 GR2 GR1 GR0 8808h
1Ah Record Select Reserved SL2 SL1 SL0 Reserved SR2 SR1 SR0 0000h
1Ch Record Gain Mute Reserved GL3 GL2 GL1 GL0 Reserved GR3 GR2 GR1 GR0 8000h
20h General
Purpose P OP BYP RSRVD 3D Reserved MIX MS LPBK Reserved 0000h
22h 3D Control Reserved DP3 DP2 Reserved 0000h
24h Audio Interrupt I4 I3 Reserved I0 Reserved 0000h
26h Powerdown
Ctrl/Stat EAPD PR6 PR5 PR4 PR3 PR2 PR1 PR0 Reserved REF ANL DAC ADC 000Fh
28h Extended
Audio ID ID1 ID0 Reserved REV1
(0) REV0
(1) AMAP LDAC SDAC CDAC DSA1 DSA0 RSVD SPDIF DRA VRA 0605h
2Ah Extended
Audio Contro l/
Status Reserved SPCV RSRVD SPSA1 SPSA0 RSRVD SPDIF RSRVD VRA
enable 0400h
2Ch PCM DAC
Rate SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 BB80h
32h PCM LR
ADC Rate SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 BB80h
3Ah SPDIF Control #V DRS SPSR1 SPSR2 L CC6 CC5 CC4 CC3 CC2 CC1 CC0 PRE COPY #PCM/
AUDIO PRO 2A00h
3Eh Extended
Modem Status Reserved PRA Reserved GPIO 0100h
4Ch GPIO Pin
Config Reserved GC1
(GPIO1) GC0
(GPIO0) 0300h
4Eh GPIO Pin
Polarity/Type Reserved GP1
(GPIO1) GP0
(GPIO0) FFFFh
50h GPIO Pin
Sticky Reserved GS1
(GPIO1) GS0
(GPIO0) 0000h
52h GPIO Pin
Mask Reserved GW1
(GPIO1) GW0
(GPIO0) 0000h
54h GPIO Pin
Status Reserved GI1
(GPIO1) GI0
(GPIO0) 0000h
60h Z_DATA
Volume Mute Reserved GL4 GL3 GL2 GL1 GL0 Reserved GR4 GR3 GR2 GR1 GR0 8808h
6Ah Digital Audio
Control Reserved DO1 DO0 0000h
6Ch Revision Code 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00xxh
6Eh Analog Special Reserved AC97 ALL MIX Reserved MUTE
FIX
DISBLE ADCslot1 ADCslot0 RSVD MIC
GAIN
VALUE
SPLY
OVR
EN
SPLY
OVR
VAL 1000h
70h 72h Enable EN15 EN14 EN13 EN12 EN11 EN10 EN9 EN8 EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0 0000h
72h Analog Current
Adjust Reserved INT APOP Reserved IBIAS<1:0> RSVD 0000h
74h*GPIO Access EAPD RSVD GPIO1 GPIO0 EAPD_OEN Reserved GPIO1_OEN GPIO0_OEN Reserved 0000h
76h 78h Enable EN15 EN14 EN13 E N12 EN11 EN10 EN9 EN8 EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0 0000h
78h High Pass
Filter Bypass RSESERVED ADC
HPF
BYP 0000h
7Ch Vendor ID1 1 0 0 0 0 0 1 1 1 0 0 0 0 1 0 0 8384h
7Eh Vendor ID2
9750 0 1 1 1 0 1 1 0 0 1 0 1 0 0 0 0 7650h
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16. REVISION HISTORY
Revision Date Description of Change
5.2 October 2003
Corrected error on page 26: Slot 1 Status Address Port, bit D2 is a SLot Request not Reserved as
stated in rev 5.1
Added CD_GND elaboration note on connection diagram, pin list and pin out diagrams:
The CD_GND signal is an AC signal return for the two CD input channels. It is normally biased at
about 2. 5V. The name of the pi n in the AC97 s pecif icatio n is CD_ GND, a nd th is has c onfus ed many
designers. It should not have any DC path to GND. Connecting the CD_GND signal directly to
ground wi ll cha nge the interna l bias of the e ntire COD EC, and ca use si gnific ant dis tortio n. If there is
no analog CD input, then this pin can be No-Connect.
5.3 June 2004
Corrected Note 4 in performance characteristics, was missing the text “Ratio of Full Scale signal to
THD+N outpu t wit h -3dB sig nal, m easured “A weig hted” ov er a”. Co mplet e n ote now reads “R atio of
Full Scale signal to THD+N output with -3dB signal, measured “A weighted” over a 20 Hz to a 20
KHz bandwidth. 48 KHz Sample Frequency”.
5.4 January 2005 Added updated 48-pin package drawing. Added reflow profile information.
5.5 February 2005 Revised reflow profile information
5.6 March 2005 Revised TQFP to say LQFP.
5.7 December 2005
Updated with new logo template
Added Part order information for RoHS package, with EOL information to Pb-bearing
Removed re ferences to older re visions (C A3) and the ir relation ship to CC1 , as CA3 is EOL an d CC1
is the only production revision.
5.8 30 October 2006 Initial release in IDT format.
© 2006 Integrated De vice Technology, Inc. All rights reserved. Product specifications subj ec t to change without not ice. IDT and the IDT logo are tr adem arks of Int egrated Dev ice
Tec hno logy, Inc. Accelerated Thinking is a service mark of Integrated Device Te chnology, Inc. All other brands, product names and marks are or may be trademarks or registered
trademarks used to identify products or services of their respective owners.
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