Features * High Performance, Low Power AVR(R)32 UC 32-Bit Microcontroller * * * * * * * * * * * * - Compact Single-Cycle RISC Instruction Set Including DSP Instruction Set - Read-Modify-Write Instructions and Atomic Bit Manipulation - Performing 1.49DMIPS/MHz * Up to 91DMIPS Running at 66MHz from Flash (1 Wait-State) * Up to 54 DMIPS Running at 36MHz from Flash (0 Wait-State) - Memory Protection Unit Multi-Layer Bus System - High-Performance Data Transfers on Separate Buses for Increased Performance - 8 Peripheral DMA Channels (PDCA) Improves Speed for Peripheral Communication - 4 generic DMA Channels for High Bandwidth Data Paths Internal High-Speed Flash - 256KBytes, 128KBytes, 64KBytes versions - Single-Cycle Flash Access up to 36MHz - Prefetch Buffer Optimizing Instruction Execution at Maximum Speed - 4 ms Page Programming Time and 8ms Full-Chip Erase Time - 100,000 Write Cycles, 15-year Data Retention Capability - Flash Security Locks and User Defined Configuration Area Internal High-Speed SRAM - 64KBytes Single-Cycle Access at Full Speed, Connected to CPU Local Bus - 64KBytes on the Multi-Layer Bus System Interrupt Controller - Autovectored Low Latency Interrupt Service with Programmable Priority System Functions - Power and Clock Manager Including Internal RC Clock and One 32KHz Oscillator - Two Multipurpose Oscillators and Two Phase-Lock-Loop (PLL), - Watchdog Timer, Real-Time Clock Timer External Memories - Support SDRAM, SRAM, NandFlash (1-bit and 4-bit ECC), Compact Flash - Up to 66 MHz External Storage device support - MultiMediaCard (MMC), Secure-Digital (SD), SDIO V1.1 - CE-ATA, FastSD, SmartMedia, Compact Flash - Memory Stick: Standard Format V1.40, PRO Format V1.00, Micro - IDE Interface One Advanced Encryption System (AES) for AT32UC3A3256S, AT32UC3A3128S, AT32UC3A364S, AT32UC3A4256S, AT32UC3A4128S and AT32UC3A364S - 256-, 192-, 128-bit Key Algorithm, Compliant with FIPS PUB 197 Specifications - Buffer Encryption/Decryption Capabilities Universal Serial Bus (USB) - High-Speed USB (480Mbit/s) Device/MiniHost with On-The-Go (OTG) - Flexible End-Point Configuration and Management with Dedicated DMA Channels - On-Chip Transceivers Including Pull-Ups One 8-channel 10-bit Analog-To-Digital Converter, multiplexed with Digital IOs. Two Three-Channel 16-bit Timer/Counter (TC) Four Universal Synchronous/Asynchronous Receiver/Transmitters (USART) - Independent Baudrate Generator, Support for SPI, IrDA and ISO7816 interfaces AVR(R)32 32-Bit Microcontroller AT32UC3A3256S AT32UC3A3256 AT32UC3A3128S AT32UC3A3128 AT32UC3A364S AT32UC3A364 AT32UC3A4256S AT32UC3A4256 AT32UC3A4128S AT32UC3A4128 AT32UC3A464S AT32UC3A464 Preliminary Summary 32072BS-AVR32-09/09 AT32UC3A3/A4 - Support for Hardware Handshaking, RS485 Interfaces and Modem Line * Two Master/Slave Serial Peripheral Interfaces (SPI) with Chip Select Signals * One Synchronous Serial Protocol Controller - Supports I2S and Generic Frame-Based Protocols * Two Master/Slave Two-Wire Interface (TWI), 400kbit/s I2C-compatible * On-Chip Debug System (JTAG interface) - Nexus Class 2+, Runtime Control, Non-Intrusive Data and Program Trace * 110 General Purpose Input/Output (GPIOs) - Standard or High Speed mode - Toggle capability: up to 66MHz * 144-pin TBGA and LQFP * 100-pin VFBGA * Single 3.3V Power Supply 2 32072BS-AVR32-09/09 AT32UC3A3/A4 1. Description The AT32UC3A3/A4 is a complete System-On-Chip microcontroller based on the AVR32 UC RISC processor running at frequencies up to 66MHz. AVR32 UC is a high-performance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications, with particular emphasis on low power consumption, high code density and high performance. The processor implements a Memory Protection Unit (MPU) and a fast and flexible interrupt controller for supporting modern operating systems and real-time operating systems. Higher computation capabilities are achievable using a rich set of DSP instructions. The AT32UC3A3/A4 incorporates on-chip Flash and SRAM memories for secure and fast access. The Peripheral Direct Memory Access Controller (PDCA) enables data transfers between peripherals and memories without processor involvement. The PDCA drastically reduces processing overhead when transferring continuous and large data streams. The Direct Memory Access controller (DMACA) allows high bandwidth data flows between high speed peripherals (USB, External Memories, MMC, SDIO, ...) and through high speed internal features (AES, internal memories). The Power Manager improves design flexibility and security: the on-chip Brown-Out Detector monitors the power supply, the CPU runs from the on-chip RC oscillator or from one of external oscillator sources, a Real-Time Clock and its associated timer keeps track of the time. The Device includes two sets of three identical 16-bit Timer/Counter (TC) channels. Each channel can be independently programmed to perform frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation. 16-bit channels are combined to operate as 32-bit channels. The AT32UC3A3/A4 also features many communication interfaces for communication intensive applications like UART, SPI or TWI. Additionally, a flexible Synchronous Serial Controller (SSC) and an USB are available. The SSC provides easy access to serial communication protocols and audio standards like I2S. The High-Speed (480 MBit/s) USB 2.0 Device interface supports several USB Classes at the same time thanks to the rich Endpoint configuration. The On-The-Go (OTG) Host interface allows device like a USB Flash disk or a USB printer to be directly connected to the processor. AT32UC3A3/A4 integrates a class 2+ Nexus 2.0 On-Chip Debug (OCD) System, with non-intrusive real-time trace, full-speed read/write memory access in addition to basic runtime control. 3 32072BS-AVR32-09/09 AT32UC3A3/A4 2. Blockdiagram Blockdiagram NEXUS CLASS 2+ OCD USB HS INTERFACE ID VBOF INSTR INTERFACE DATA INTERFACE M S M DMA M M S S M DMACA 32KB RAM DMA S S S HRAM S M S S CONFIGURATION PB HS B HSB-PB BRIDGE B REGISTERS BUS HSB PERIPHERAL DMA CONTROLLER HSB-PB BRIDGE A PB NMI_N EXTERNAL INTERRUPT CONTROLLER PDC EXTINT[7..0] KPS[7..0] PDC INTERRUPT CONTROLLER USART1 USART0 USART2 PDC PA PB PC PX MULTIMEDIA CARD & MEMORY STICK INTERFACE USART3 PDC DATA[15..0] DMA CLK CMD[1..0] SERIAL PERIPHERAL INTERFACE 0/1 PDC PBA GENERAL PURPOSE IOs 32KB RAM SYNCHRONOUS SERIAL CONTROLLER WATCHDOG TIMER XOUT1 CLOCK GENERATOR SDA10 SDCK SDCKE SDCS1 SDWE CFCE1 CFCE2 CFRW NANDOE NANDWE RXD TXD CLK RTS, CTS DSR, DTR, DCD, RI RXD TXD CLK RTS, CTS TXD PA PB PC PX SCK MISO, MOSI NPCS0 NPCS[3..1] TX_CLOCK, TX_FRAME_SYNC TX_DATA RX_CLOCK, RX_FRAME_SYNC TWO-WIRE INTERFACE 0/1 ANALOG TO DIGITAL CONVERTER AUDIO BITSTREAM DAC SCL SDA OSC0 OSC1 PLL0 CLOCK CONTROLLER SLEEP CONTROLLER PLL1 RESET_N NCS[5..0] NRD NWAIT NWE0 NWE1 NWE3 RAS CAS RX_DATA PDC XIN1 POWER MANAGER PDC XIN0 XOUT0 32 KHz OSC DATA[15..0] ADDR[23..0] CLK PDC XIN32 XOUT32 512/256/ 128/64 KB FLASH RXD REAL TIME COUNTER 115 kHz RCOSC 64 KB SRAM M HIGH SPEED BUS MATRIX AES FAST GPIO GENERAL PURPOSE IOs VBG VBUS DH+,DL+ DH-,DL- MEMORY PROTECTION UNIT PBB MCKO MDO[5..0] MSEO[1..0] EVTI_N EVTO_N UC CPU LOCAL BUS INTERFACE FLASH CONTROLLER JTAG INTERFACE EXTERNAL BUS INTERFACE (SDRAM, STATIC MEMORY, COMPACT FLASH & NAND FLASH) TCK TDO TDI TMS MEMORY INTERFACE Figure 2-1. GCLK[3..0] A[2..0] B[2..0] CLK[2..0] RESET CONTROLLER AD[7..0] ADVREF DATA[1..0] DATAN[1..0] TIMER/COUNTER 0/1 4 32072BS-AVR32-09/09 AT32UC3A3/A4 2.1 2.1.1 Processor and Architecture AVR32 UC CPU * 32-bit load/store AVR32A RISC architecture - - - - - 15 general-purpose 32-bit registers 32-bit Stack Pointer, Program Counter and Link Register reside in register file Fully orthogonal instruction set Privileged and unprivileged modes enabling efficient and secure Operating Systems Innovative instruction set together with variable instruction length ensuring industry leading code density - DSP extension with saturating arithmetic, and a wide variety of multiply instructions * Three stage pipeline allows one instruction per clock cycle for most instructions - Byte, halfword, word and double word memory access - Multiple interrupt priority levels * MPU allows for operating systems with memory protection 2.1.2 Debug and Test System * IEEE1149.1 compliant JTAG and boundary scan * Direct memory access and programming capabilities through JTAG interface * Extensive On-Chip Debug features in compliance with IEEE-ISTO 5001-2003 (Nexus 2.0) Class 2+ * * * * 2.1.3 - Low-cost NanoTrace supported Auxiliary port for high-speed trace information Hardware support for six Program and two data breakpoints Unlimited number of software breakpoints supported Advanced Program, Data, Ownership and Watchpoint trace supported Peripheral DMA Controller * Transfers from/to peripheral to/from any memory space without intervention of the processor * Next Pointer Support, forbids strong real-time constraints on buffer management * Eight channels and 24 Handshake interfaces - - - - - - 2.1.4 Two for each USART Two for each Serial Synchronous Controller (SSC) Two for each Serial Peripheral Interface (SPI) One for ADC Four for each TWI Interface Two for each Audio Bit Stream DAC Bus System * High Speed Bus (HSB) matrix with 7 Masters and 10 Slaves handled - Handles Requests from * Masters: the CPU (Instruction and Data Fetch), PDCA, CPU SAB, USBB, DMACA * Slaves: the internal Flash, internal SRAM, Peripheral Bus A, Peripheral Bus B, External Bus Interface (EBI), Advanced Encrytion Standard (AES) - Round-Robin Arbitration (three modes supported: no default master, last accessed default master, fixed default master) - Burst breaking with Slot Cycle Limit - One address decoder provided per master * Peripheral Bus A able to run on at divided bus speeds compared to the High Speed Bus 5 32072BS-AVR32-09/09 AT32UC3A3/A4 3. Signals Description The following table gives details on the signal name classified by peripheral Table 3-1. Signal Description List Signal Name Function Type Active Level Comments Power VDDIO I/O Power Supply Power 3.0 to 3.6 V VDDANA Analog Power Supply Power 3.0 to 3.6 V VDDIN Voltage Regulator Input Supply Power 2.7 to 3.6 V ONREG Voltage Regulator ON/OFF Power Control VDDCORE Voltage Regulator Output for Digital Supply Power Output GNDANA Analog Ground Ground GNDIO I/O Ground Ground GNDCORE DIgital Ground Ground GNDPLL PLL Ground Ground 1 2.7 to 3.6 V 1.65 to 1.95V Clocks, Oscillators, and PLL's XIN0, XIN1, XIN32 Crystal 0, 1, 32 Input Analog XOUT0, XOUT1, XOUT32 Crystal 0, 1, 32 Output Analog JTAG TCK Test Clock Input TDI Test Data In Input TDO Test Data Out TMS Test Mode Select Output Input Auxiliary Port - AUX MCKO Trace Data Output Clock Output MDO[5:0] Trace Data Output Output MSEO[1:0] Trace Frame Control Output EVTI_N Event In Output Low EVTO_N Event Out Output Low Power Manager - PM 6 32072BS-AVR32-09/09 AT32UC3A3/A4 Table 3-1. Signal Description List Signal Name Function GCLK[2:0] Generic Clock Pins RESET_N Reset Pin Type Active Level Comments Output Input Low DMA Controller - DMACA (optional) DMAACK[1:0] DMA Acknowledge DMARQ[1:0] DMA Requests Output Input External Interrupt Module - EIM EXTINT[7:0] External Interrupt Pins Input KPS0 - KPS7 Keypad Scan Pins NMI_N Non-Maskable Interrupt Pin Output Input Low General Purpose Input/Output pin - GPIOA, GPIOB, GPIOC, GPIOX PA[31:0] Parallel I/O Controller GPIOA I/O PB[11:0] Parallel I/O Controller GPIOB I/O PC[5:0] Parallel I/O Controller GPIOC I/O PX[59:0] Parallel I/O Controller GPIO X I/O External Bus Interface - EBI ADDR[23:0] Address Bus Output CAS Column Signal Output Low CFCE1 Compact Flash 1 Chip Enable Output Low CFCE2 Compact Flash 2 Chip Enable Output Low CFRNW Compact Flash Read Not Write Output DATA[15:0] Data Bus NANDOE NAND Flash Output Enable Output Low NANDWE NAND Flash Write Enable Output Low NCS[5:0] Chip Select Output Low NRD Read Signal Output Low NWAIT External Wait Signal Input Low NWE0 Write Enable 0 Output Low NWE1 Write Enable 1 Output Low I/O 7 32072BS-AVR32-09/09 AT32UC3A3/A4 Table 3-1. Signal Description List Type Active Level Row Signal Output Low SDA10 SDRAM Address 10 Line Output SDCK SDRAM Clock Output SDCKE SDRAM Clock Enable Output SDCS SDRAM Chip Select Output Low SDWE SDRAM Write Enable Output Low Signal Name Function RAS Comments MultiMedia Card Interface - MCI CLK Multimedia Card Clock Output CMD[1:0] Multimedia Card Command I/O DATA[15:0] Multimedia Card Data I/O Serial Peripheral Interface - SPI0 MISO Master In Slave Out I/O MOSI Master Out Slave In I/O NPCS[3:0] SPI Peripheral Chip Select I/O SCK Clock Low Output Synchronous Serial Controller - SSC RX_CLOCK SSC Receive Clock I/O RX_DATA SSC Receive Data Input RX_FRAME_SYNC SSC Receive Frame Sync I/O TX_CLOCK SSC Transmit Clock I/O TX_DATA SSC Transmit Data Output TX_FRAME_SYNC SSC Transmit Frame Sync I/O Timer/Counter - TC0, TC1 A0 Channel 0 Line A I/O A1 Channel 1 Line A I/O A2 Channel 2 Line A I/O B0 Channel 0 Line B I/O B1 Channel 1 Line B I/O 8 32072BS-AVR32-09/09 AT32UC3A3/A4 Table 3-1. Signal Description List Signal Name Function Type B2 Channel 2 Line B CLK0 Channel 0 External Clock Input Input CLK1 Channel 1 External Clock Input Input CLK2 Channel 2 External Clock Input Input Active Level Comments I/O Two-wire Interface - TWI0, TWI1 SCL Serial Clock I/O SDA Serial Data I/O Universal Synchronous Asynchronous Receiver Transmitter - USART0, USART1, USART2, USART3 CLK Clock I/O CTS Clear To Send DCD Data Carrier Detect Only USART1 DSR Data Set Ready Only USART1 DTR Data Terminal Ready Only USART1 RI Ring Indicator Only USART1 RTS Request To Send RXD Receive Data Input RXDN Inverted Receive Data Input TXD Transmit Data Output TXDN Inverted Transmit Data Output Input Output Low Low Analog to Digital Converter - ADC AD0 - AD7 Analog input pins Analog input Audio Bitstream DAC (ABDAC) DATA0-DATA1 D/A Data out Output DATAN0-DATAN1 D/A Data inverted out Output Universal Serial Bus Device - USB FSDM USB Full Speed Data - Analog FSDP USB Full Speed Data + Analog HSDM USB High Speed Data - Analog 9 32072BS-AVR32-09/09 AT32UC3A3/A4 Table 3-1. Signal Description List Signal Name Function Type HSDP USB High Speed Data + Analog USB_VBIAS USB VBIAS reference Analog USB_VBUS USB VBUS for OTG feature Output Active Level Comments Connect to the ground through a 6810ohms (+/- 0.5%) resistor 10 32072BS-AVR32-09/09 AT32UC3A3/A4 4. Package and Pinout 4.1 Package The device pins are multiplexed with peripheral functions as described in the Peripheral Multiplexing on I/O Line section. Figure 4-1. TBGA144 Pinout (top view) 1 2 3 4 5 6 7 8 9 10 11 12 A B C D E F G H J K L M Table 4-1. BGA144 Package Pinout A1..M8 1 2 3 4 5 6 7 8 9 10 11 12 PX40 PB00 PA28 PA27 PB03 PA29 PC02 PC04 PC05 DPHS DMHS USB_VBUS PX10 PB11 PA31 PB02 VDDIO PB04 PC03 VDDIO DMFS GNDPLL PA09 C PX09 PX35 GNDIO PB01 PX16 PX13 PA30 PB08 DPFS GNDCORE PA08 PA10 D PX08 PX37 PX36 PX47 PX19 PX12 PB10 PA02 PA26 PA11 PB07 PB06 E PX38 VDDIO PX54 PX53 VDDIO PX15 PB09 VDDIN PA25 PA07 VDDCORE PA12 F PX39 PX07 PX06 PX49 PX48 GNDIO GNDIO PA06 PA04 PA05 PA13 PA16 G PX00 PX05 PX59 PX50 PX51 GNDIO GNDIO PA23 PA24 PA03 PA00 PA01 H PX01 VDDIO PX58 PX57 VDDIO PC01 PA17 VDDIO PA21 PA22 VDDANA PB05 J PX04 PX02 PX34 PX56 PX55 PA14 PA15 PA19 PA20 TMS TDO RESET_N K PX03 PX44 GNDIO PX46 PC00 PX17 PX52 PA18 PX27 GNDIO PX29 TCK L PX11 GNDIO PX45 PX20 VDDIO PX18 PX43 ONREG PX26 PX28 GNDANA TDI M PX22 PX41 PX42 PX14 PX21 PX23 PX24 PX25 PX32 PX31 PX30 PX33 A B USB_ VBIAS 11 32072BS-AVR32-09/09 AT32UC3A3/A4 Figure 4-2. LQFP144 Pinout 108 73 109 72 144 37 1 Table 4-2. 36 Package Pinout 1 USB_VBUS 37 PX10 73 PX20 109 PA21 2 VDDIO 38 PX35 74 PX46 110 PA22 3 USB_VBIAS 39 PX47 75 PX50 111 PA23 4 GNDIO 40 PX15 76 PX57 112 PA24 5 DMHS 41 PX48 77 PX51 113 PA20 6 DPHS 42 PX53 78 PX56 114 PA19 7 GNDIO 43 PX49 79 PX55 115 PA18 8 DMFS 44 PX36 80 PX21 116 PA17 9 DPFS 45 PX37 81 VDDIO 117 GNDANA 10 VDDIO 46 PX54 82 GNDIO 118 VDDANA 11 PB08 47 GNDIO 83 PX17 119 PA25 12 PC05 48 VDDIO 84 PX18 120 PA26 13 PC04 49 PX09 85 PX23 121 PB05 14 PA30 50 PX08 86 PX24 122 PA00 15 PA02 51 PX38 87 PX52 123 PA01 16 PB10 52 PX39 88 PX43 124 PA05 17 PB09 53 PX06 89 PX27 125 PA03 18 PC02 54 PX07 90 PX26 126 PA04 19 PC03 55 PX00 91 PX28 127 PA06 20 GNDIO 56 PX59 92 PX25 128 PA16 21 VDDIO 57 PX58 93 PX32 129 PA13 22 PB04 58 PX05 94 PX29 130 VDDIO 23 PA29 59 PX01 95 PX33 131 GNDIO 24 PB03 60 PX04 96 PX30 132 PA12 25 PB02 61 PX34 97 PX31 133 PA07 26 PA27 62 PX02 98 PC00 134 PB06 12 32072BS-AVR32-09/09 AT32UC3A3/A4 Table 4-2. Package Pinout 27 PB01 63 PX03 99 PC01 135 PB07 28 PA28 64 VDDIO 100 PA14 136 PA11 29 PA31 65 GNDIO 101 PA15 137 PA08 30 PB00 66 PX44 102 GNDIO 138 PA10 31 PB11 67 PX11 103 VDDIO 139 PA09 32 PX16 68 PX14 104 TMS 140 GNDCORE 33 PX13 69 PX42 105 TDO 141 VDDCORE 34 PX12 70 PX45 106 RESET_N 142 VDDIN 35 PX19 71 PX41 107 TCK 143 ONREG 36 PX40 72 PX22 108 TDI 144 GNDPLL Figure 4-3. VFBGA100 Pinout (top view) 1 2 3 4 5 6 7 8 9 10 A B C D E F G H J K Table 4-3. VFBGA100 Package Pinout 1 2 3 4 5 6 7 8 9 10 A PA28 PA27 PB04 PA30 PC02 PC03 PC05 HSDP HSDM VBUS B PB00 PB01 PB02 PA29 VDDIO VDDIO PC04 FSDP FSDM GNDUSB C PB11 PA31 GNDIO PB03 PB09 PB08 VBIAS GNDIO PA11 PA10 D PX12 PX10 PX13 PX53/PX16 PB10 PB07 PB06 PA09 ONREG VDDIN E PX47/PA02 GNDIO PX08 PX09 VDDIO GNDIO PA16 PA06/PA13 PA04 VDDCORE F PX59/PX19 VDDIO PX06 PX07 GNDIO VDDIO PA26/PB05 PA08 PA03 GNDCORE G PX05 PX01 PX02 PX00 PX30 PA23/PX46 PA25/PA12 PA18/PA00 PA05 PA17/PA01 H PX04 PX21 GNDIO PX25 PX31 PA22/PX20 TMS GNDANA PA20/PX18 PA19/PA07 J PX03 PX24 PX26 PX29 VDDIO VDDANA PA15/PX45 TDO RESET_N PA24/PX17 K PX23 PX27 PX28 PX32/PX15 PC00/PX14 PC01 PA14/PX11 TDI TCK PA21/PX22 13 32072BS-AVR32-09/09 AT32UC3A3/A4 4.2 Peripheral Multiplexing on I/O lines Each GPIO line can be assigned to one of 4 peripheral functions; A, B, C, or D. The following table define how the I/O lines on the peripherals A, B, C, or D are multiplexed by the GPIO. Table 4-4. TBGA144 G11 G12 GPIO Controller Function Multiplexing QFP144 122 123 VFBGA100 (1) G8 G10 (1) GPIO Pin Function A Function B Function C PA00 GPIO 0 USART0 - RTS TC0 - CLK1 SPI1 - NPCS[3] PA01 GPIO 1 USART0 - CTS TC0 - A1 USART2 - RTS PA02 GPIO 2 USART0 - CLK TC0 - B1 SPI0 - NPCS[0] D8 15 G10 125 F9 PA03 GPIO 3 USART0 - RXD EIC - EXTINT[4] DAC - DATA[0] F9 126 E9 PA04 GPIO 4 USART0 - TXD EIC - EXTINT[5] DAC - DATAN[0] F10 124 G9 PA05 GPIO 5 USART1 - RXD TC1 - CLK0 USB - USB_ID PA06 GPIO 6 USART1 - TXD TC1 - CLK1 USB - USB_VBOF PA07 GPIO 7 SPI0 - NPCS[3] DAC - DATAN[0] USART1 - CLK F8 127 E1 (1) PIN E8 (1) (1) E10 133 H10 C11 137 F8 PA08 GPIO 8 SPI0 - SCK DAC - DATA[0] TC1 - B1 B12 139 D8 PA09 GPIO 9 SPI0 - NPCS[0] EIC - EXTINT[6] TC1 - A1 C12 138 C10 PA10 GPIO 10 SPI0 - MOSI USB USB_VBOF TC1 - B0 D10 136 C9 PA11 GPIO 11 SPI0 - MISO USB - USB_ID TC1 - A2 E12 132 G7(1) PA12 GPIO 12 USART1 - CTS SPI0 - NPCS[2] TC1 - A0 F11 129 E8(1) PA13 GPIO 13 USART1 - RTS SPI0 - NPCS[1] EIC - EXTINT[7] J6 100 K7(1) PA14 GPIO 14 SPI0 - NPCS[1] TWIMS0 TWALM TWIMS1 - TWCK J7 101 (1) PA15 GPIO 15 MCI - CMD[1] SPI1 - SCK TWIMS1 - TWD F12 128 PA16 GPIO 16 MCI - DATA[11] SPI1 - MOSI TC1 - CLK2 PA17 GPIO 17 MCI - DATA[10] SPI1 - NPCS[1] ADC - AD[7] PA18 GPIO 18 MCI - DATA[9] SPI1 - NPCS[2] ADC - AD[6] PA19 GPIO 19 MCI - DATA[8] SPI1 - MISO ADC - AD[5] ADC - AD[4] H7 K8 J8 J9 H9 H10 G8 116 115 114 113 109 110 111 J7 E7 G10 (1) (1) G8 H10 (1) H9(1) K10 H6 (1) PA20 GPIO 20 EIC - EXTINT[8] SSC RX_FRAME_SYN C PA21 GPIO 21 ADC - AD[0] EIC - EXTINT[0] USB - USB_ID (1) PA22 GPIO 22 ADC - AD[1] EIC - EXTINT[1] USB - USB_VBOF (1) PA23 GPIO 23 ADC - AD[2] EIC - EXTINT[2] DAC - DATA[1] (1) PA24 GPIO 24 ADC - AD[3] EIC - EXTINT[3] DAC - DATAN[1] G6 Function D ] G9 112 J10 E9 119 G7(1) PA25 GPIO 25 TWIMS0 - TWD TWIMS1 TWALM USART1 - DCD D9 120 F7(1)) PA26 GPIO 26 TWIMS0 - TWCK USART2 - CTS USART1 - DSR A4 26 A2 PA27 GPIO 27 MCI - CLK SSC - RX_DATA USART3 - RTS MSI - SCLK A3 28 A1 PA28 GPIO 28 MCI - CMD[0] SSC RX_CLOCK USART3 - CTS MSI - BS A6 23 B4 PA29 GPIO 29 MCI - DATA[0] USART3 - TXD TC0 - CLK0 MSI - DATA[0] 14 32072BS-AVR32-09/09 AT32UC3A3/A4 Table 4-4. GPIO Controller Function Multiplexing C7 14 A4 PA30 GPIO 30 MCI - DATA[1] USART3 - CLK DMACA DMAACK[0] MSI - DATA[1] B3 29 C2 PA31 GPIO 31 MCI - DATA[2] USART2 - RXD DMACA DMARQ[0] MSI - DATA[2] A2 30 B1 PB00 GPIO 32 MCI - DATA[3] USART2 - TXD ADC - TRIGGER MSI - DATA[3] C4 27 B2 PB01 GPIO 33 MCI - DATA[4] DAC - DATA[1] EIC - SCAN[0] MSI - INS B4 25 B3 PB02 GPIO 34 MCI - DATA[5] DAC - DATAN[1] EIC - SCAN[1] A5 24 C4 PB03 GPIO 35 MCI - DATA[6] USART2 - CLK EIC - SCAN[2] B6 22 A3 PB04 GPIO 36 MCI - DATA[7] USART3 - RXD EIC - SCAN[3] H12 121 F7(1) PB05 GPIO 37 USB - USB_ID TC0 - A0 EIC - SCAN[4] D12 134 D7 PB06 GPIO 38 USB USB_VBOF TC0 - B0 EIC - SCAN[5] D11 135 D6 PB07 GPIO 39 SPI1 - SCK SSC TX_CLOCK EIC - SCAN[6] C8 11 C6 PB08 GPIO 40 SPI1 - MISO SSC - TX_DATA EIC - SCAN[7] E7 17 C5 PB09 GPIO 41 SPI1 - NPCS[0] SSC - RX_DATA EBI - NCS[4] SPI1 - MOSI SSC RX_FRAME_SYN C EBI - NCS[5] USART1 - RXD SSC TX_FRAME_SYN C PM - GCLK[1] D7 16 D5 PB10 GPIO 42 B2 31 C1 PB11 GPIO 43 K5 98 K5(1) PC00 GPIO 45 H6 99 K6 PC01 GPIO 46 A7 18 A5 PC02 GPIO 47 B7 19 A6 PC03 GPIO 48 A8 13 B7 PC04 GPIO 49 A9 12 A7 PC05 GPIO 50 G1 55 G4 PX00 GPIO 51 EBI - DATA[10] USART0 - RXD USART1 - RI H1 59 G2 PX01 GPIO 52 EBI - DATA[9] USART0 - TXD USART1 - DTR J2 62 G3 PX02 GPIO 53 EBI - DATA[8] USART0 - CTS PM - GCLK[0] K1 63 J1 PX03 GPIO 54 EBI - DATA[7] USART0 - RTS J1 60 H1 PX04 GPIO 55 EBI - DATA[6] USART1 - RXD G2 58 G1 PX05 GPIO 56 EBI - DATA[5] USART1 - TXD F3 53 F3 PX06 GPIO 57 EBI - DATA[4] USART1 - CTS F2 54 F4 PX07 GPIO 58 EBI - DATA[3] USART1 - RTS D1 50 E3 PX08 GPIO 59 EBI - DATA[2] USART3 - RXD C1 49 E4 PX09 GPIO 60 EBI - DATA[1] USART3 - TXD B1 37 D2 PX10 GPIO 61 EBI - DATA[0] USART2 - RXD L1 67 K7(1) PX11 GPIO 62 EBI - NWE1 USART2 - TXD D6 34 D1 PX12 GPIO 63 EBI - NWE0 USART2 - CTS MCI - CLK C6 33 D3 PX13 GPIO 64 EBI - NRD USART2 - RTS MCI - CLK 15 32072BS-AVR32-09/09 AT32UC3A3/A4 Table 4-4. GPIO Controller Function Multiplexing M4 68 K5(1) PX14 GPIO 65 EBI - NCS[1] E6 40 K4(1) PX15 GPIO 66 EBI - ADDR[19] USART3 - RTS TC0 - B0 C5 32 D4(1) PX16 GPIO 67 EBI - ADDR[18] USART3 - CTS TC0 - A1 K6 83 J10(1) PX17 GPIO 68 EBI - ADDR[17] DMACA DMARQ[1] TC0 - B1 L6 84 H9(1) PX18 GPIO 69 EBI - ADDR[16] DMACA DMAACK[1] TC0 - A2 D5 35 F1(1) PX19 GPIO 70 EBI - ADDR[15] EIC - SCAN[0] TC0 - B2 L4 73 H6(1) PX20 GPIO 71 EBI - ADDR[14] EIC - SCAN[1] TC0 - CLK0 M5 80 H2 PX21 GPIO 72 EBI - ADDR[13] EIC - SCAN[2] TC0 - CLK1 M1 72 K10(1) PX22 GPIO 73 EBI - ADDR[12] EIC - SCAN[3] TC0 - CLK2 M6 85 K1 PX23 GPIO 74 EBI - ADDR[11] EIC - SCAN[4] SSC - TX_CLOCK M7 86 J2 PX24 GPIO 75 EBI - ADDR[10] EIC - SCAN[5] SSC - TX_DATA M8 92 H4 PX25 GPIO 76 EBI - ADDR[9] EIC - SCAN[6] SSC - RX_DATA TC0 - A0 L9 90 J3 PX26 GPIO 77 EBI - ADDR[8] EIC - SCAN[7] SSC RX_FRAME_SYN C K9 89 K2 PX27 GPIO 78 EBI - ADDR[7] SPI0 - MISO SSC TX_FRAME_SYNC L10 91 K3 PX28 GPIO 79 EBI - ADDR[6] SPI0 - MOSI SSC - RX_CLOCK K11 94 J4 PX29 GPIO 80 EBI - ADDR[5] SPI0 - SCK M11 96 G5 PX30 GPIO 81 EBI - ADDR[4] SPI0 - NPCS[0] M10 97 H5 PX31 GPIO 82 EBI - ADDR[3] SPI0 - NPCS[1] PX32 GPIO 83 EBI - ADDR[2] SPI0 - NPCS[2] M9 93 M12 95 PX33 GPIO 84 EBI - ADDR[1] SPI0 - NPCS[3] J3 61 PX34 GPIO 85 EBI - ADDR[0] SPI1 - MISO PM - GCLK[0] C2 38 PX35 GPIO 86 EBI - DATA[15] SPI1 - MOSI PM - GCLK[1] D3 44 PX36 GPIO 87 EBI - DATA[14] SPI1 - SCK PM - GCLK[2] D2 45 PX37 GPIO 88 EBI - DATA[13] SPI1 - NPCS[0] PM - GCLK[3] E1 51 PX38 GPIO 89 EBI - DATA[12] SPI1 - NPCS[1] USART1 - DCD F1 52 PX39 GPIO 90 EBI - DATA[11] SPI1 - NPCS[2] USART1 - DSR A1 36 PX40 GPIO 91 EBI - SDCS MCI - CLK M2 71 PX41 GPIO 92 EBI - CAS M3 69 PX42 GPIO 93 EBI - RAS L7 88 PX43 GPIO 94 EBI - SDA10 USART1 - RI K2 66 USART1 - DTR L3 K4 70 74 K4 (1) J7 PX44 GPIO 95 EBI - SDWE (1) PX45 GPIO 96 EBI - SDCK (1) PX46 GPIO 97 EBI - SDCKE (1) PX47 GPIO 98 EBI - NANDOE ADC - TRIGGER MCI - DATA[11] G6 D4 39 E1 F5 41 PX48 GPIO 99 EBI - ADDR[23] USB USB_VBOF MCI - DATA[10] F4 43 PX49 GPIO 100 EBI - CFRNW USB - USB_ID MCI - DATA[9] 16 32072BS-AVR32-09/09 AT32UC3A3/A4 Table 4-4. GPIO Controller Function Multiplexing G4 75 PX50 GPIO 101 EBI - CFCE2 TC1 - B2 MCI - DATA[8] G5 77 PX51 GPIO 102 EBI - CFCE1 DMACA DMAACK[0] MCI - DATA[15] K7 87 PX52 GPIO 103 EBI - NCS[3] DMACA DMARQ[0] MCI - DATA[14] E4 42 PX53 GPIO 104 EBI - NCS[2] E3 46 PX54 GPIO 105 EBI - NWAIT USART3 - TXD MCI - DATA[12] J5 79 PX55 GPIO 106 EBI - ADDR[22] EIC - SCAN[3] USART2 - RXD J4 78 PX56 GPIO 107 EBI - ADDR[21] EIC - SCAN[2] USART2 - TXD H4 76 PX57 GPIO 108 EBI - ADDR[20] EIC - SCAN[1] USART3 - RXD H3 57 PX58 GPIO 109 EBI - NCS[0] EIC - SCAN[0] USART3 - TXD G3 56 PX59 GPIO 110 EBI - NANDWE D4(1) F1(1) Note: 4.2.1 MCI - CMD[1] 1. Those balls are physically connected to 2 GPIOs. Software must managed carrefully the GPIO configuration to avoid electrical conflict Oscillator Pinout Table 4-5. Oscillator Pinout TBGA144 QFP144 VFBGA100 Pad Oscillator pin A7 18 A5 PC02 xin0 A8 13 B7 PC04 xin1 PC00 xin32 (1) K5 98 B7 19 A6 PC03 xout0 A9 12 A7 PC05 xout1 H6 99 K6 PC01 xout32 Note: 4.3 MCI - DATA[13] K5 1. This ball is physically connected to 2 GPIOs. Software must managed carrefully the GPIO configuration to avoid electrical conflict Signal Descriptions The following table gives details on signal name classified by peripheral. Table 4-6. Signal Description List Signal Name Function Type Active Level Comments Power VDDIO I/O Power Supply Power 3.0 to 3.6V VDDANA Analog Power Supply Power 3.0 to 3.6V VDDIN Voltage Regulator Input Supply Power 2.7 to 3.6V 17 32072BS-AVR32-09/09 AT32UC3A3/A4 Table 4-6. Signal Description List Signal Name Function Type ONREG Voltage Regulator ON/OFF Power Control VDDCORE Voltage Regulator Output for Digital Supply Power Output GNDANA Analog Ground Ground GNDIO I/O Ground Ground GNDCORE DIgital Ground Ground GNDPLL PLL Ground Ground Active Level Comments 1 2.7 to 3.6 V 1.65 to 1.95 V Clocks, Oscillators, and PLL's XIN0, XIN1, XIN32 Crystal 0, 1, 32 Input Analog XOUT0, XOUT1, XOUT32 Crystal 0, 1, 32 Output Analog JTAG TCK Test Clock Input TDI Test Data In Input TDO Test Data Out TMS Test Mode Select Output Input Auxiliary Port - AUX MCKO Trace Data Output Clock Output MDO[5:0] Trace Data Output Output MSEO[1:0] Trace Frame Control Output EVTI_N Event In Output Low EVTO_N Event Out Output Low Power Manager - PM GCLK[2:0] Generic Clock Pins RESET_N Reset Pin Output Input Low DMA Controller - DMACA (optional) DMAACK[1:0] DMA Acknowledge DMARQ[1:0] DMA Requests Output Input External Interrupt Module - EIM 18 32072BS-AVR32-09/09 AT32UC3A3/A4 Table 4-6. Signal Description List Signal Name Function Type EXTINT[7:0] External Interrupt Pins Input KPS0 - KPS7 Keypad Scan Pins NMI_N Non-Maskable Interrupt Pin Active Level Comments Output Input Low General Purpose Input/Output pin - GPIOA, GPIOB, GPIOC, GPIOX PA[31:0] Parallel I/O Controller GPIO port A I/O PB[11:0] Parallel I/O Controller GPIO port B I/O PC[5:0] Parallel I/O Controller GPIO port C I/O PX[59:0] Parallel I/O Controller GPIO port X I/O External Bus Interface - EBI ADDR[23:0] Address Bus Output CAS Column Signal Output Low CFCE1 Compact Flash 1 Chip Enable Output Low CFCE2 Compact Flash 2 Chip Enable Output Low CFRNW Compact Flash Read Not Write Output DATA[15:0] Data Bus NANDOE NAND Flash Output Enable Output Low NANDWE NAND Flash Write Enable Output Low NCS[5:0] Chip Select Output Low NRD Read Signal Output Low NWAIT External Wait Signal Input Low NWE0 Write Enable 0 Output Low NWE1 Write Enable 1 Output Low RAS Row Signal Output Low SDA10 SDRAM Address 10 Line Output SDCK SDRAM Clock Output SDCKE SDRAM Clock Enable Output SDCS SDRAM Chip Select Output Low SDWE SDRAM Write Enable Output Low I/O 19 32072BS-AVR32-09/09 AT32UC3A3/A4 Table 4-6. Signal Description List Signal Name Function Type Active Level Comments MultiMedia Card Interface - MCI CLK Multimedia Card Clock Output CMD[1:0] Multimedia Card Command I/O DATA[15:0] Multimedia Card Data I/O Serial Peripheral Interface - SPI0 MISO Master In Slave Out I/O MOSI Master Out Slave In I/O NPCS[3:0] SPI Peripheral Chip Select I/O SCK Clock Low Output Synchronous Serial Controller - SSC RX_CLOCK SSC Receive Clock I/O RX_DATA SSC Receive Data Input RX_FRAME_SYNC SSC Receive Frame Sync I/O TX_CLOCK SSC Transmit Clock I/O TX_DATA SSC Transmit Data Output TX_FRAME_SYNC SSC Transmit Frame Sync I/O Timer/Counter - TC0, TC1 A0 Channel 0 Line A I/O A1 Channel 1 Line A I/O A2 Channel 2 Line A I/O B0 Channel 0 Line B I/O B1 Channel 1 Line B I/O B2 Channel 2 Line B I/O CLK0 Channel 0 External Clock Input Input CLK1 Channel 1 External Clock Input Input CLK2 Channel 2 External Clock Input Input Two-wire Interface - TWI0, TWI1 SCL Serial Clock I/O 20 32072BS-AVR32-09/09 AT32UC3A3/A4 Table 4-6. Signal Description List Signal Name Function SDA Serial Data Type Active Level Comments I/O Universal Synchronous Asynchronous Receiver Transmitter - USART0, USART1, USART2, USART3 CLK Clock I/O CTS Clear To Send DCD Data Carrier Detect Only USART1 DSR Data Set Ready Only USART1 DTR Data Terminal Ready Only USART1 RI Ring Indicator Only USART1 RTS Request To Send RXD Receive Data Input RXDN Inverted Receive Data Input TXD Transmit Data Output TXDN Inverted Transmit Data Output Input Output Low Low Analog to Digital Converter - ADC AD0 - AD7 Analog input Analog input pins Audio Bitstream DAC (ABDAC) DATA0-DATA1 D/A Data out Output DATAN0-DATAN1 D/A Data inverted out Output Universal Serial Bus Device - USB FSDM USB Full Speed Data - Analog FSDP USB Full Speed Data + Analog HSDM USB High Speed Data - Analog HSDP USB High Speed Data + Analog USB_VBIAS USB VBIAS reference Analog USB_VBUS USB VBUS for OTG feature Output 4.3.1 Connect to the ground through a 6810 ohms (+/- 0.5%) resistor JTAG Pins TMS and TDI pins have pull-up resistors. TDO pin is an output, driven at up to VDDIO, and has no pull-up resistor. 21 32072BS-AVR32-09/09 AT32UC3A3/A4 4.3.2 RESET_N Pin The RESET_N pin is a schmitt input and integrates a permanent pull-up resistor to VDDIO. As the product integrates a power-on reset cell, the RESET_N pin can be left unconnected in case no reset from the system needs to be applied to the product. 4.3.3 TWI Pins When these pins are used for TWI, the pins are open-drain outputs with slew-rate limitation and inputs with inputs with spike filtering. When used as GPIO pins or used for other peripherals, the pins have the same characteristics as other GPIO pins. 4.3.4 GPIO Pins All the I/O lines integrate a programmable pull-up resistor. Programming of this pull-up resistor is performed independently for each I/O line through the I/O Controller. After reset, I/O lines default as inputs with pull-up resistors disabled, except when indicated otherwise in the column "Reset State" of the I/O Controller multiplexing tables. 22 32072BS-AVR32-09/09 AT32UC3A3/A4 4.4 4.4.1 Power Considerations Power Supplies The AT32UC3A3 has several types of power supply pins: * * * * VDDIO: Powers I/O lines. Voltage is 3.3V nominal VDDANA: Powers the ADC Voltage and provides the ADVREF voltage is 3.3V nominal VDDIN: Input voltage for the voltage regulator. Voltage is 3.3V nominal VDDCORE: Output voltage from regulator for filtering purpose and provides the supply to the core, memories, and peripherals. Voltage is 1.8V nominal The ground pins GNDCORE are common to VDDCORE and VDDIN. The ground pin for VDDANA is GNDANA. The ground pin for VDDIO is GNDIO. Refer to Electrical Characteristics chapter for power consumption on the various supply pins. 4.4.2 Voltage Regulator The AT32UC3A3 embeds a voltage regulator that converts from 3.3V to 1.8V with a load of up to 100 mA. The regulator takes its input voltage from VDDIN, and supplies the output voltage on VDDCORE and powers the core, memories and peripherals. Adequate output supply decoupling is mandatory for VDDCORE to reduce ripple and avoid oscillations. The best way to achieve this is to use two capacitors in parallel between VDDCORE and GNDCORE: * One external 470pF (or 1nF) NPO capacitor (COUT1) should be connected as close to the chip as possible. * One external 2.2F (or 3.3F) X7R capacitor (COUT2). Adequate input supply decoupling is mandatory for VDDIN in order to improve startup stability and reduce source voltage drop. The input decoupling capacitor should be placed close to the chip, e.g., two capacitors can be used in parallel (100nF NPO and 4.7F X7R). 3.3V VDDIN CIN2 CIN1 ONREG 1.8V 1.8V Regulator VDDCORE COUT2 COUT1 ONREG input must be tied to VDDIN. 23 32072BS-AVR32-09/09 AT32UC3A3/A4 5. Power Considerations 5.1 Power Supplies The AT32UC3A3/A4 has several types of power supply pins: * * * * VDDIO: Powers I/O lines. Voltage is 3.3V nominal VDDANA: Powers the ADC Voltage and provides the ADVREF voltage is 3.3V nominal VDDIN: Input voltage for the voltage regulator. Voltage is 3.3V nominal VDDCORE: Output voltage from regulator for filtering purpose and provides the supply to the core, memories, and peripherals. Voltage is 1.8V nominal The ground pins GNDCORE are common to VDDCORE and VDDIN. The ground pin for VDDANA is GNDANA. The ground pin for VDDIO is GNDIO Refer to Electrical Characteristics chapter for power consumption on the various supply pins. 5.2 Voltage Regulator The AT32UC3A3 embeds a voltage regulator that converts from 3.3V to 1.8V with a load of up to 100 mA. The regulator takes its input voltage from VDDIN, and supplies the output voltage on VDDCORE and powers the core, memories and peripherals. Adequate output supply decoupling is mandatory for VDDCORE to reduce ripple and avoid oscillations. The best way to achieve this is to use two capacitors in parallel between VDDCORE and GNDCORE: * One external 470pF (or 1nF) NPO capacitor (COUT1) should be connected as close to the chip as possible. * One external 2.2F (or 3.3F) X7R capacitor (COUT2). Adequate input supply decoupling is mandatory for VDDIN in order to improve startup stability and reduce source voltage drop. The input decoupling capacitor should be placed close to the chip, e.g., two capacitors can be used in parallel (100nF NPO and 4.7F X7R). 3.3V VDDIN CIN2 CIN1 ONREG 1.8 V 1.8V Regulator VDDCORE COUT2 COUT1 ONREG input must be tied to VDDIN. 24 32072BS-AVR32-09/09 AT32UC3A3/A4 6. I/O Line Considerations 6.1 JTAG Pins TMS and TDI pins have pull-up resistors. TDO pin is an output, driven at up to VDDIO, and has no pull-up resistor. 6.2 RESET_N Pin The RESET_N pin is a schmitt input and integrates a permanent pull-up resistor to VDDIO. As the product integrates a power-on reset cell, the RESET_N pin can be left unconnected in case no reset from the system needs to be applied to the product. 6.3 TWI Pins When these pins are used for TWI, the pins are open-drain outputs with slew-rate limitation and inputs with inputs with spike filtering. When used as GPIO pins or used for other peripherals, the pins have the same characteristics as other GPIO pins. 6.4 GPIO Pins All the I/O lines integrate a programmable pull-up resistor. Programming of this pull-up resistor is performed independently for each I/O line through the I/O Controller. After reset, I/O lines default as inputs with pull-up resistors disabled, except when indicated otherwise in the column "Reset State" of the I/O Controller multiplexing tables. 25 32072BS-AVR32-09/09 AT32UC3A3/A4 7. Memories 7.1 Embedded Memories * Internal High-Speed Flash - 256KBytes (AT32UC3A3256/S) - 128Kbytes (AT32UC3A3128/S) - 64Kbytes (AT32UC3A364/S) * 0 wait state access at up to 36MHz in worst case conditions * 1 wait state access at up to 66MHz in <orst case conditions * Pipelined Flash architecture, allowing burst reads from sequential Flash locations, hiding penalty of 1 wait state access * Pipelined Flash architecture typically reduces the cycle penalty of 1 wait state operation to only 15% compared to 0 wait state operation * 100 000 write cycles, 15-year data retention capability * Sector lock capabilities, Bootloader protection, Security Bit * 32 fuses, preserved during Chip Erase * User page for data to be preserved during Chip Erase * Internal High-Speed SRAM - 64KBytes, Single-cycle access at full speed on CPU Local Bus and accessible through the High Speed Bud (HSB) matrix - 2x32KBytes, accessible independently through the High Speed Bud (HSB) matrix 7.2 Physical Memory Map The System Bus is implemented as a bus matrix. All system bus addresses are fixed, and they are never remapped in any way, not even in boot. Note that AVR32UC CPU uses unsegmented translation, as described in the AVR32 Architecture Manual. The 32-bit physical address space is mapped as follows: Table 7-1. AT32UC3A3 Physical Memory Map Start Address Size Size Size AT32UC3A3256 AT32UC3A3128 AT32UC3A364 Embedded CPU SRAM 0x00000000 64KByte 64KByte 64KByte Embedded Flash 0x80000000 256KByte 128KByte 64KByte EBI SRAM CS0 0xC0000000 16MByte 16MByte 16MByte EBI SRAM CS2 0xC8000000 16MByte 16MByte 16MByte EBI SRAM CS3 0xCC000000 16MByte 16MByte 16MByte EBI SRAM CS4 0xD8000000 16MByte 16MByte 16MByte EBI SRAM CS5 0xDC000000 16MByte 16MByte 16MByte EBI SRAM CS1 /SDRAM CS0 0xD0000000 128MByte 128MByte 128MByte USB Data 0xE0000000 64KByte 64KByte 64KByte Embedded System SRAM 0 0xFF000000 32KByte 32KByte 32KByte Device 26 32072BS-AVR32-09/09 AT32UC3A3/A4 Table 7-1. AT32UC3A3 Physical Memory Map Start Address Size Size Size AT32UC3A3256 AT32UC3A3128 AT32UC3A364 Embedded System SRAM 1 0xFF008000 32KByte 32KByte 32KByte HSB-PB Bridge A 0xFFFF0000 64KByte 64KByte 64KByte HSB-PB Bridge B 0xFFFE0000 64KByte 64KByte 64KByte Device 7.3 Peripheral Address Map Table 7-2. Peripheral Address Mapping Address Peripheral Name Bus 0xFF100000 DMACA DMA Controller - DMACA 0xFF200000 RESERVED 0xFFFD0000 AES Advanced Encryption Standard - AES USB USB 2.0 OTG Interface - USB 0xFFFE0000 0xFFFE1000 HMATRIX HSB Matrix - HMATRIX FLASHC Flash Controller - FLASHC 0xFFFE1400 0xFFFE1C00 SMC Static Memory Controller - SMC 0xFFFE2000 SDRAMC SDRAM Controller - SDRAMC ECCHRS Error code corrector Hamming and Reed Solomon ECCHRS BUSMON Bus Monitor module - BUSMON MCI Mulitmedia Card Interface - MCI MSI Memory Stick Interface - MSI 0xFFFE2400 0xFFFE2800 0xFFFE4000 0xFFFE8000 0xFFFF0000 PDMA Peripheral DMA Controller - PDMA INTC Interrupt controller - INTC 0xFFFF0800 27 32072BS-AVR32-09/09 AT32UC3A3/A4 Table 7-2. Peripheral Address Mapping 0xFFFF0C00 PM Power Manager - PM RTC Real Time Counter - RTC WDT Watchdog Timer - WDT EIC External Interrupt Controller - EIC 0xFFFF0D00 0xFFFF0D30 0xFFFF0D80 0xFFFF1000 GPIO 0xFFFF1400 General Purpose Input/Output Controller - GPIO USART0 Universal Synchronous/Asynchronous Receiver/Transmitter - USART0 USART1 Universal Synchronous/Asynchronous Receiver/Transmitter - USART1 USART2 Universal Synchronous/Asynchronous Receiver/Transmitter - USART2 USART3 Universal Synchronous/Asynchronous Receiver/Transmitter - USART3 0xFFFF1800 0xFFFF1C00 0xFFFF2000 0xFFFF2400 SPI0 Serial Peripheral Interface - SPI0 SPI1 Serial Peripheral Interface - SPI1 0xFFFF2800 0xFFFF2C00 TWIM0 Two-wire Master Interface - TWIM0 TWIM1 Two-wire Master Interface - TWIM1 0xFFFF3000 0xFFFF3400 SSC Synchronous Serial Controller - SSC TC0 Timer/Counter - TC0 ADC Analog to Digital Converter - ADC DAC Audio Bitstream DAC - DAC TC1 Timer/Counter - TC1 0xFFFF3800 0xFFFF3C00 0xFFFF4000 0xFFFF4400 0xFFFF4800 RESERVED 28 32072BS-AVR32-09/09 AT32UC3A3/A4 Table 7-2. Peripheral Address Mapping 0xFFFF4c00 RESERVED 0xFFFF5000 TWIS0 Two-wire Slave Interface - TWIS0 TWIS1 Two-wire Slave Interface - TWIS1 0xFFFF5400 7.4 CPU Local Bus Mapping Some of the registers in the GPIO module are mapped onto the CPU local bus, in addition to being mapped on the Peripheral Bus. These registers can therefore be reached both by accesses on the Peripheral Bus, and by accesses on the local bus. Mapping these registers on the local bus allows cycle-deterministic toggling of GPIO pins since the CPU and GPIO are the only modules connected to this bus. Also, since the local bus runs at CPU speed, one write or read operation can be performed per clock cycle to the local busmapped GPIO registers. The following GPIO registers are mapped on the local bus: Table 7-3. Local Bus Mapped GPIO Registers Port Register Mode Local Bus Address Access A Output Driver Enable Register (ODER) WRITE 0x40000040 Write-only SET 0x40000044 Write-only CLEAR 0x40000048 Write-only TOGGLE 0x4000004C Write-only WRITE 0x40000050 Write-only SET 0x40000054 Write-only CLEAR 0x40000058 Write-only TOGGLE 0x4000005C Write-only Pin Value Register (PVR) - 0x40000060 Read-only Output Driver Enable Register (ODER) WRITE 0x40000240 Write-only SET 0x40000244 Write-only CLEAR 0x40000248 Write-only TOGGLE 0x4000024C Write-only WRITE 0x40000250 Write-only SET 0x40000254 Write-only CLEAR 0x40000258 Write-only TOGGLE 0x4000025C Write-only - 0x40000260 Read-only Output Value Register (OVR) B Output Value Register (OVR) Pin Value Register (PVR) 29 32072BS-AVR32-09/09 AT32UC3A3/A4 8. Peripherals 8.1 Clock Connections 8.1.1 Timer/Counters Each Timer/Counter channel can independently select an internal or external clock source for its counter: Table 8-1. Timer/Counter clock connections Source Name Connection Internal TIMER_CLOCK1 32 KHz clock TIMER_CLOCK2 PBA Clock / 2 TIMER_CLOCK3 PBA Clock / 8 TIMER_CLOCK4 PBA Clock / 32 TIMER_CLOCK5 PBA Clock / 128 XC0 See Table 8.2 on page 30 External XC1 XC2 8.2 Peripheral Multiplexing on I/O lines Each GPIO line can be assigned to one of 4 peripheral functions; A, B, C or D. The following table define how the I/O lines on the peripherals A, B, C or D are multiplexed by the GPIO. Table 8-2. GPIO Controller Function Multiplexing BGA144 QFP144 PIN GPIO Pin Function A Function B Function C G11 122 PA00 GPIO 0 USART0 - RTS TC0 - CLK1 SPI1 - NPCS[3] G12 123 PA01 GPIO 1 USART0 - CTS TC0 - A1 USART2 - RTS D8 15 PA02 GPIO 2 USART0 - CLK TC0 - B1 SPI0 - NPCS[0] G10 125 PA03 GPIO 3 USART0 - RXD EIC - EXTINT[4] DAC - DATA[0] F9 126 PA04 GPIO 4 USART0 - TXD EIC - EXTINT[5] DAC - DATAN[0] F10 124 PA05 GPIO 5 USART1 - RXD TC1 - CLK0 USB - USB_ID F8 127 PA06 GPIO 6 USART1 - TXD TC1 - CLK1 USB USB_VBOF E10 133 PA07 GPIO 7 SPI0 - NPCS[3] DAC - DATAN[0] USART1 - CLK C11 137 PA08 GPIO 8 SPI0 - SCK DAC - DATA[0] TC1 - B1 B12 139 PA09 GPIO 9 SPI0 - NPCS[0] EIC - EXTINT[6] TC1 - A1 C12 138 PA10 GPIO 10 SPI0 - MOSI USB USB_VBOF TC1 - B0 D10 136 PA11 GPIO 11 SPI0 - MISO USB - USB_ID TC1 - A2 E12 132 PA12 GPIO 12 USART1 - CTS SPI0 - NPCS[2] TC1 - A0 F11 129 PA13 GPIO 13 USART1 - RTS SPI0 - NPCS[1] EIC - EXTINT[7] Function D 30 32072BS-AVR32-09/09 AT32UC3A3/A4 Table 8-2. GPIO Controller Function Multiplexing J6 100 PA14 GPIO 14 SPI0 - NPCS[1] TWIMS0 TWALM TWIMS1 - TWCK J7 101 PA15 GPIO 15 MCI - CMD[1] SPI1 - SCK TWIMS1 - TWD F12 128 PA16 GPIO 16 MCI - DATA[11] SPI1 - MOSI TC1 - CLK2 H7 116 PA17 GPIO 17 MCI - DATA[10] SPI1 - NPCS[1] ADC - AD[7] K8 115 PA18 GPIO 18 MCI - DATA[9] SPI1 - NPCS[2] ADC - AD[6] J8 114 PA19 GPIO 19 MCI - DATA[8] SPI1 - MISO ADC - AD[5] ADC - AD[4] J9 113 PA20 GPIO 20 NMI SSC RX_FRAME_SYN C H9 109 PA21 GPIO 21 ADC - AD[0] EIC - EXTINT[0] USB - USB_ID H10 110 PA22 GPIO 22 ADC - AD[1] EIC - EXTINT[1] USB USB_VBOF G8 111 PA23 GPIO 23 ADC - AD[2] EIC - EXTINT[2] DAC - DATA[1] G9 112 PA24 GPIO 24 ADC - AD[3] EIC - EXTINT[3] DAC - DATAN[1] E9 119 PA25 GPIO 25 TWIMS0 - TWD TWIMS1 TWALM USART1 - DCD D9 120 PA26 GPIO 26 TWIMS0 - TWCK USART2 - CTS USART1 - DSR A4 26 PA27 GPIO 27 MCI - CLK SSC - RX_DATA USART3 - RTS MSI - SCLK A3 28 PA28 GPIO 28 MCI - CMD[0] SSC RX_CLOCK USART3 - CTS MSI - BS A6 23 PA29 GPIO 29 MCI - DATA[0] USART3 - TXD TC0 - CLK0 MSI - DATA[0] C7 14 PA30 GPIO 30 MCI - DATA[1] USART3 - CLK DMACA DMAACK[0] MSI - DATA[1] B3 29 PA31 GPIO 31 MCI - DATA[2] USART2 - RXD DMACA DMARQ[0] MSI - DATA[2] A2 30 PB00 GPIO 32 MCI - DATA[3] USART2 - TXD ADC - TRIGGER MSI - DATA[3] C4 27 PB01 GPIO 33 MCI - DATA[4] DAC - DATA[1] EIC - SCAN[0] MSI - INS B4 25 PB02 GPIO 34 MCI - DATA[5] DAC - DATAN[1] EIC - SCAN[1] A5 24 PB03 GPIO 35 MCI - DATA[6] USART2 - CLK EIC - SCAN[2] B6 22 PB04 GPIO 36 MCI - DATA[7] USART3 - RXD EIC - SCAN[3] H12 121 PB05 GPIO 37 USB - USB_ID TC0 - A0 EIC - SCAN[4] D12 134 PB06 GPIO 38 USB USB_VBOF TC0 - B0 EIC - SCAN[5] D11 135 PB07 GPIO 39 SPI1 - SCK SSC TX_CLOCK EIC - SCAN[6] C8 11 PB08 GPIO 40 SPI1 - MISO SSC - TX_DATA EIC - SCAN[7] E7 17 PB09 GPIO 41 SPI1 - NPCS[0] SSC - RX_DATA EBI - NCS[4] SPI1 - MOSI SSC RX_FRAME_SYN C EBI - NCS[5] USART1 - RXD SSC TX_FRAME_SYN C PM - GCLK[1] D7 16 PB10 GPIO 42 B2 31 PB11 GPIO 43 K5 98 PC00 GPIO 45 31 32072BS-AVR32-09/09 AT32UC3A3/A4 Table 8-2. GPIO Controller Function Multiplexing H6 99 PC01 GPIO 46 A7 18 PC02 GPIO 47 B7 19 PC03 GPIO 48 A8 13 PC04 GPIO 49 A9 12 PC05 GPIO 50 G1 55 PX00 GPIO 51 EBI - DATA[10] USART0 - RXD USART1 - RI H1 59 PX01 GPIO 52 EBI - DATA[9] USART0 - TXD USART1 - DTR J2 62 PX02 GPIO 53 EBI - DATA[8] USART0 - CTS PM - GCLK[0] K1 63 PX03 GPIO 54 EBI - DATA[7] USART0 - RTS J1 60 PX04 GPIO 55 EBI - DATA[6] USART1 - RXD G2 58 PX05 GPIO 56 EBI - DATA[5] USART1 - TXD F3 53 PX06 GPIO 57 EBI - DATA[4] USART1 - CTS F2 54 PX07 GPIO 58 EBI - DATA[3] USART1 - RTS D1 50 PX08 GPIO 59 EBI - DATA[2] USART3 - RXD C1 49 PX09 GPIO 60 EBI - DATA[1] USART3 - TXD B1 37 PX10 GPIO 61 EBI - DATA[0] USART2 - RXD L1 67 PX11 GPIO 62 EBI - NWE1 USART2 - TXD D6 34 PX12 GPIO 63 EBI - NWE0 USART2 - CTS C6 33 PX13 GPIO 64 EBI - NRD USART2 - RTS M4 68 PX14 GPIO 65 EBI - NCS[1] E6 40 PX15 GPIO 66 EBI - ADDR[19] USART3 - RTS TC0 - B0 C5 32 PX16 GPIO 67 EBI - ADDR[18] USART3 - CTS TC0 - A1 K6 83 PX17 GPIO 68 EBI - ADDR[17] DMACA DMARQ[1] TC0 - B1 L6 84 PX18 GPIO 69 EBI - ADDR[16] DMACA DMAACK[1] TC0 - A2 D5 35 PX19 GPIO 70 EBI - ADDR[15] EIC - SCAN[0] TC0 - B2 L4 73 PX20 GPIO 71 EBI - ADDR[14] EIC - SCAN[1] TC0 - CLK0 M5 80 PX21 GPIO 72 EBI - ADDR[13] EIC - SCAN[2] TC0 - CLK1 M1 72 PX22 GPIO 73 EBI - ADDR[12] EIC - SCAN[3] TC0 - CLK2 M6 85 PX23 GPIO 74 EBI - ADDR[11] EIC - SCAN[4] SSC TX_CLOCK M7 86 PX24 GPIO 75 EBI - ADDR[10] EIC - SCAN[5] SSC - TX_DATA M8 92 PX25 GPIO 76 EBI - ADDR[9] EIC - SCAN[6] SSC - RX_DATA EIC - SCAN[7] SSC RX_FRAME_SYN C L9 90 PX26 GPIO 77 EBI - ADDR[8] TC0 - A0 K9 89 PX27 GPIO 78 EBI - ADDR[7] SPI0 - MISO SSC TX_FRAME_SYN C L10 91 PX28 GPIO 79 EBI - ADDR[6] SPI0 - MOSI SSC RX_CLOCK 32 32072BS-AVR32-09/09 AT32UC3A3/A4 Table 8-2. 8.3 GPIO Controller Function Multiplexing K11 94 PX29 GPIO 80 EBI - ADDR[5] SPI0 - SCK M11 96 PX30 GPIO 81 EBI - ADDR[4] SPI0 - NPCS[0] M10 97 PX31 GPIO 82 EBI - ADDR[3] SPI0 - NPCS[1] M9 93 PX32 GPIO 83 EBI - ADDR[2] SPI0 - NPCS[2] M12 95 PX33 GPIO 84 EBI - ADDR[1] SPI0 - NPCS[3] J3 61 PX34 GPIO 85 EBI - ADDR[0] SPI1 - MISO PM - GCLK[0] C2 38 PX35 GPIO 86 EBI - DATA[15] SPI1 - MOSI PM - GCLK[1] D3 44 PX36 GPIO 87 EBI - DATA[14] SPI1 - SCK PM - GCLK[2] D2 45 PX37 GPIO 88 EBI - DATA[13] SPI1 - NPCS[0] PM - GCLK[3] E1 51 PX38 GPIO 89 EBI - DATA[12] SPI1 - NPCS[1] USART1 - DCD F1 52 PX39 GPIO 90 EBI - DATA[11] SPI1 - NPCS[2] USART1 - DSR A1 36 PX40 GPIO 91 EBI - SDCS M2 71 PX41 GPIO 92 EBI - CAS M3 69 PX42 GPIO 93 EBI - RAS L7 88 PX43 GPIO 94 EBI - SDA10 USART1 - RI K2 66 PX44 GPIO 95 EBI - SDWE USART1 - DTR L3 70 PX45 GPIO 96 EBI - SDCK K4 74 PX46 GPIO 97 EBI - SDCKE D4 39 PX47 GPIO 98 EBI - NANDOE ADC - TRIGGER MCI - DATA[11] F5 41 PX48 GPIO 99 EBI - ADDR[23] USB USB_VBOF MCI - DATA[10] F4 43 PX49 GPIO 100 EBI - CFRNW USB - USB_ID MCI - DATA[9] G4 75 PX50 GPIO 101 EBI - CFCE2 TC1 - B2 MCI - DATA[8] G5 77 PX51 GPIO 102 EBI - CFCE1 DMACA DMAACK[0] MCI - DATA[15] K7 87 PX52 GPIO 103 EBI - NCS[3] DMACA DMARQ[0] MCI - DATA[14] E4 42 PX53 GPIO 104 EBI - NCS[2] E3 46 PX54 GPIO 105 EBI - NWAIT USART3 - TXD MCI - DATA[12] J5 79 PX55 GPIO 106 EBI - ADDR[22] EIC - SCAN[3] USART2 - RXD J4 78 PX56 GPIO 107 EBI - ADDR[21] EIC - SCAN[2] USART2 - TXD H4 76 PX57 GPIO 108 EBI - ADDR[20] EIC - SCAN[1] USART3 - RXD H3 57 PX58 GPIO 109 EBI - NCS[0] EIC - SCAN[0] USART3 - TXD G3 56 PX59 GPIO 110 EBI - NANDWE MCI - DATA[13] MCI - CMD[1] Oscillator Pinout Table 8-3. Oscillator Pinout pin pin Pad Oscillator pin A7 18 PC02 xin0 A8 13 PC04 xin1 33 32072BS-AVR32-09/09 AT32UC3A3/A4 Table 8-3. Oscillator Pinout K5 98 PC00 xin32 B7 19 PC03 xout0 A9 12 PC05 xout1 H6 99 PC01 xout32 34 32072BS-AVR32-09/09 AT32UC3A3/A4 8.4 8.4.1 8.4.2 Peripheral overview Power Manager * * * * * * * * * * * * * Controls integrated oscillators and PLLs Generates clocks and resets for digital logic Supports 2 crystal oscillators 4MHZ-16MHz Supports 2 PLLs 48-150MHz Supports 32KHz ultra-low power oscillator Integrated low-power RC oscillator On-the fly frequency change of CPU, HSB, PBA, and PBB clocks Sleep modes allow simple disabling of logic clocks, PLLs, and oscillators Module-level clock gating through maskable peripheral clocks Wake-up from internal or external interrupts Generic clocks with wide frequency range provided Automatic identification of reset sources Controls brownout detector (BOD), RC oscillator, and bandgap voltage reference through control and calibration registers Real Time Counter * 32-bit real-time counter with 16-bit prescaler * Clocked from RC oscillator or 32KHz oscillator * Long delays * * * * - Max timeout 272years High resolution: Max count frequency 16KHz Extremely low power consumption Available in all sleep modes except Static Interrupt on wrap 8.4.3 Watchdog Timer * Watchdog timer counter with 32-bit prescaler * Clocked from the system RC oscillator (RCSYS) 8.4.4 Interrupt Controller * Autovectored low latency interrupt service with programmable priority - 4 priority levels for regular, maskable interrupts - One Non-Maskable Interrupt 35 32072BS-AVR32-09/09 AT32UC3A3/A4 * Up to 64 groups of interrupts with up to 32 interrupt requests in each group 8.4.5 External Interrupts Controller * Dedicated interrupt request for each interrupt * Individually maskable interrupts * Interrupt on rising or falling edge * Interrupt on high or low level * Asynchronous interrupts for sleep modes without clock * Filtering of interrupt lines * Maskable NMI interrupt * Keypad scan support * 8.4.6 Flash Controller * Controls flash block with dual read ports allowing staggered reads. * Supports 0 and 1 wait state bus access. * Allows interleaved burst reads for systems with one wait state, outputting one 32-bit word per clock cycle. * 32-bit HSB interface for reads from flash array and writes to page buffer. * 32-bit PB interface for issuing commands to and configuration of the controller. * 16 lock bits, each protecting a region consisting of (total number of pages in the flash block / 16) * * * * * * * 8.4.7 pages. Regions can be individually protected or unprotected. Additional protection of the Boot Loader pages. Supports reads and writes of general-purpose NVM bits. Supports reads and writes of additional NVM pages. Supports device protection through a security bit. Dedicated command for chip-erase, first erasing all on-chip volatile memories before erasing flash and clearing security bit. Interface to Power Manager for power-down of flash-blocks in sleep mode. HSB Bus Matrix * * * * * * * User Interface on peripheral bus Configurable Number of Masters (Up to sixteen) Configurable Number of Slaves (Up to sixteen) One Decoder for Each Master Three Different Memory Mappings for Each Master (Internal and External boot, Remap) One Remap Function for Each Master Programmable Arbitration for Each Slave - Round-Robin - Fixed Priority * Programmable Default Master for Each Slave - No Default Master - Last Accessed Default Master - Fixed Default Master 36 32072BS-AVR32-09/09 AT32UC3A3/A4 * One Cycle Latency for the First Access of a Burst * Zero Cycle Latency for Default Master * One Special Function Register for Each Slave (Not dedicated) 8.4.8 External Bus Interface * Optimized for application memory space support * Integrates three external memory controllers: - Static Memory Controller (SMC) - SDRAM Controller (SDRAMC) - Error Corrected Code (ECCHRS) controller * Additional logic for NAND Flash/SmartMediaTM and CompactFlashTM support - NAND Flash support: 8-bit as well as 16-bit devices are supported - CompactFlash support: all modes (Attribute Memory, Common Memory, I/O, True IDE) are supported but the signals _IOIS16 (I/O and True IDE modes) and _ATA SEL (True IDE mode) are not handled. * Optimized external bus:16-bit data bus - Up to 24-bit Address Bus, Up to 8-Mbytes Addressable - Optimized pin multiplexing to reduce latencies on external memories * Up to 6 Chip Selects, Configurable Assignment: - Static Memory Controller on Chip Select 0 - SDRAM Controller or Static Memory Controller on Chip Select 1 - Static Memory Controller on Chip Select 2, Optional NAND Flash support - Static Memory Controller on Chip Select 3, Optional NAND Flash support - Static Memory Controller on Chip Select 4, Optional CompactFlashTM support - Static Memory Controller on Chip Select 5, Optional CompactFlashTM support 8.4.9 Static Memory Controller * 6 chip selects available * 64-Mbytes address space per chip select * 8- or 16-bit data bus * Word, halfword, byte transfers * Byte write or byte select lines * Programmable setup, pulse and hold time for read signals per chip select * Programmable setup, pulse and hold time for write signals per chip select * Programmable data float time per chip select * Compliant with LCD module * External wait request * Automatic switch to slow clock mode * Asynchronous read in page mode supported: page size ranges from 4 to 32 bytes 8.4.10 SDRAM Controller * 128-Mbytes address space * Numerous configurations supported - 2K, 4K, 8K row address memory parts - SDRAM with two or four internal banks - SDRAM with 16-bit data path * Programming facilities - Word, halfword, byte access - Automatic page break when memory boundary has been reached - Multibank ping-pong access 37 32072BS-AVR32-09/09 AT32UC3A3/A4 * * * * * - Timing parameters specified by software - Automatic refresh operation, refresh rate is programmable - Automatic update of DS, TCR and PASR parameters (mobile SDRAM devices) Energy-saving capabilities - Self-refresh, power-down, and deep power-down modes supported - Supports mobile SDRAM devices Error detection - Refresh error interrupt SDRAM power-up initialization by software CAS latency of one, two, and three supported Auto Precharge command not used 8.4.11 Peripheral DMA Controller * Multiple channels * Generates transfers to/from peripherals such as USART and SPI * Two address pointers/counters per channel allowing double buffering * Performance monitors to measure average and maximum transfer latency 8.4.12 DMA Controller * 2 HSB Master Interfaces * 4 Channels * Software and Hardware Handshaking Interfaces - 9 Hardware Handshaking Interfaces * Memory/Non-Memory Peripherals to Memory/Non-Memory Peripherals Transfer * Single-block DMA Transfer * Multi-block DMA Transfer - Linked Lists - Auto-Reloading - Contiguous Blocks * DMA Controller is Always the Flow Controller * Additional Features - Scatter and Gather Operations - Channel Locking - Bus Locking - FIFO Mode - Pseudo Fly-by Operation 8.4.13 General-Purpose Input/Output Controller * * * * * Each I/O line of the GPIO features: Configurable pin-change, rising-edge or falling-edge interrupt on any I/O line A glitch filter providing rejection of pulses shorter than one clock cycle Input visibility and output control Multiplexing of up to four peripheral functions per I/O line Programmable internal pull-up resistor Serial Peripheral Interface * Compatible with an embedded 32-bit microcontroller * Supports communication with serial external devices - Four chip selects with external decoder support allow communication with up to 15 peripherals 38 32072BS-AVR32-09/09 AT32UC3A3/A4 - Serial memories, such as DataFlash and 3-wire EEPROMs - Serial peripherals, such as ADCs, DACs, LCD controllers, CAN controllers and Sensors - External co-processors * Master or Slave Serial Peripheral Bus Interface - 4 - to 16-bit programmable data length per chip select - Programmable phase and polarity per chip select - Programmable transfer delays between consecutive transfers and between clock and data per chip select - Programmable delay between consecutive transfers - Selectable mode fault detection * Connection to Peripheral DMA Controller channel capabilities optimizes data transfers - One channel for the receiver, one channel for the transmitter - Next buffer support - Four character FIFO in reception 8.4.14 Two-Wire Slave Interface * Compatible with IC standard * * * * * * 8.4.15 - 100 and 400 kbit/s transfer speeds - 7 and 10-bit and General Call addressing Compatible with SMBus standard - Hardware Packet Error Checking (CRC) generation and verification with ACK response - SMBALERT interface - 25 ms clock low timeout delay - 25 ms slave cumulative clock low extend time Compatible with PMBus DMA interface for reducing CPU load Arbitrary transfer lengths, including 0 data bytes Optional clock stretching if transmit or receive buffers not ready for data transfer 32-bit Peripheral Bus interface for configuration of the interface Two-Wire Master Interface * Compatible with IC standard - Multi-master support - 100 and 400 kbit/s transfer speeds - 7- and 10-bit and General Call addressing * Compatible with SMBus standard - Hardware Packet Error Checking (CRC) generation and verification with ACK control - SMBus ALERT interface - 25 ms clock low timeout delay - 10 ms master cumulative clock low extend time - 25 ms slave cumulative clock low extend time 39 32072BS-AVR32-09/09 AT32UC3A3/A4 * * * * * 8.4.16 Compatible with PMBus Compatible with Atmel Two-Wire Interface Serial Memories DMA interface for reducing CPU load Arbitrary transfer lengths, including 0 data bytes Optional clock stretching if transmit or receive buffers not ready for data transfer Synchronous Serial Controller * Provides serial synchronous communication links used in audio and telecom applications * Independent receiver and transmitter, common clock divider * Interfaced with two Peripheral DMA Controller channels to reduce processor overhead * Configurable frame sync and data length * Receiver and transmitter can be configured to start automatically or on detection of different events on the frame sync signal * Receiver and transmitter include a data signal, a clock signal and a frame synchronization signal 8.4.17 Universal Synchronous Asynchronous Receiver Transmitter * Programmable Baud Rate Generator * 5- to 9-bit Full-duplex Synchronous or Asynchronous Serial Communications * * * * * - 1, 1.5 or 2 Stop Bits in Asynchronous Mode or 1 or 2 Stop Bits in Synchronous Mode - Parity Generation and Error Detection - Framing Error Detection, Overrun Error Detection - MSB- or LSB-first - Optional Break Generation and Detection - By 8 or by 16 Over-sampling Receiver Frequency - Optional Hardware Handshaking RTS-CTS - Optional Modem Signal Management DTR-DSR-DCD-RI - Receiver Time-out and Transmitter Timeguard - Optional Multidrop Mode with Address Generation and Detection RS485 with Driver Control Signal ISO7816, T = 0 or T = 1 Protocols for Interfacing with Smart Cards - NACK Handling, Error Counter with Repetition and Iteration Limit IrDA Modulation and Demodulation - Communication at up to 115.2 Kbps SPI Mode - Master or Slave - Serial Clock Programmable Phase and Polarity - SPI Serial Clock (CLK) Frequency up to Internal Clock Frequency CLK_USART/4 LIN Mode - Compliant with LIN 1.3 and LIN 2.0 specifications - Master or Slave - Processing of frames with up to 256 data bytes - Response Data length can be configurable or defined automatically by the Identifier - Self synchronization in Slave node configuration - Automatic processing and verification of the "Synch Break" and the "Synch Field" - The "Synch Break" is detected even if it is partially superimposed with a data byte - Automatic Identifier parity calculation/sending and verification - Parity sending and verification can be disabled - Automatic Checksum calculation/sending and verification - Checksum sending and verification can be disabled - Support both "Classic" and "Enhanced" checksum types 40 32072BS-AVR32-09/09 AT32UC3A3/A4 - Full LIN error checking and reporting - Frame Slot Mode: the Master allocates slots to the scheduled frames automatically. - Generation of the Wakeup signal * Test Modes - Remote Loopback, Local Loopback, Automatic Echo * Supports Connection of Two Peripheral DMA Controller Channels (PDCA) - Offers Buffer Transfer without Processor Intervention 8.4.18 USB On-The-Go Interface * Compatible with the USB 2.0 specification * Supports High (480Mbps), Full (12Mbps) and Low (1.5Mbps) speed communication and On-TheGo * * * * * * 8.4.19 nine pipes/endpoints 2368 of Embedded Dual-Port RAM (DPRAM) for Pipes/Endpoints Up to 2 memory banks per Pipe/Endpoint (Not for Control Pipe/Endpoint) Flexible Pipe/Endpoint configuration and management with dedicated DMA channels On-Chip UTMI transceiver including Pull-Ups/Pull-downs On-Chip OTG pad including VBUS analog comparator Timer/Counter * Three 16-bit Timer Counter channels * A wide range of functions including: - Frequency measurement - Event counting - Interval measurement - Pulse generation - Delay timing - Pulse width modulation - Up/down capabilities * Each channel is user-configurable and contains: - Three external clock inputs - Five internal clock inputs - Two multi-purpose input/output signals * Internal interrupt signal * Two global registers that act on all three TC channels 8.4.20 Analog-to-Digital Converter * Integrated multiplexer offering up to eight independent analog inputs * Individual enable and disable of each channel * Hardware or software trigger - External trigger pin - Timer counter outputs (corresponding TIOA trigger) * PDCA support * Possibility of ADC timings configuration * Sleep mode and conversion sequencer - Automatic wakeup on trigger and back to sleep mode after conversions of all enabled channels 41 32072BS-AVR32-09/09 AT32UC3A3/A4 8.4.21 HSB Bus Performance Monitor * Allows performance monitoring of High Speed Bus master interfaces - Up to 4 masters can be monitored - Peripheral Bus access to monitor registers * The following is monitored - Data transfer cycles - Bus stall cycles - Maximum access latency for a single transfer * Automatic handling of event overflow 8.4.22 Multimedia Card Interface * Compatible with Multimedia Card specification version 4.2 * Compatible with SD Memory Card specification version 2.0 * Compatible with SDIO specification version 1.1 * Compatible with CE-ATA specification 1.1 * Cards clock rate up to master clock divided by two * High Speed mode support * Embedded power management to slow down clock rate when not used * Supports 2 Slots - Each slot for either a MultiMediaCard bus (up to 30 cards) or an SD Memory Card * Support for stream, block and multi-block data read and write * Supports connection to DMA Controller - Minimizes processor intervention for large buffer transfers * Built in FIFO (from 16 to 256 bytes) with large memory aperture supporting incremental access * Support for CE-ATA completion cignal disable command * Protection against unexpected modification on-the-Fly of the configuration registers 8.4.23 Error Corrected Code Controller * Hardware Error Corrected Code Generation with two methods : * * * * - Hamming code detection and correction by software (ECC-H) - Reed-Solomon code detection by hardware, correction by hardware or software (ECC-RS) Supports NAND Flash and SmartMediaTM devices with 8- or 16-bit data path for ECC-H, and with 8-bit data path for ECC-RS Supports NAND Flash and SmartMediaTM with page sizes of 528, 1056, 2112, and 4224 bytes (specified by software) ECC_H supports : - One bit correction per page of 512,1024,2048, or 4096 bytes - One bit correction per sector of 512 bytes of data for a page size of 512, 1024, 2048, or 4096 bytes - One bit correction per sector of 256 bytes of data for a page size of 512, 1024, 2048, or 4096 bytes ECC_RS supports : - 4 errors correction per sector of 512 bytes of data for a page size of 512, 1024, 2048, and 4096 bytes with 8-bit data path 42 32072BS-AVR32-09/09 AT32UC3A3/A4 8.4.24 Advanced Encryption Standart * Compliant with FIPS Publication 197, Advanced Encryption Standard (AES) * 128-bit/192-bit/256-bit cryptographic key * 12/14/16 clock cycles encryption/decryption processing time with a 128-bit/192-bit/256-bit cryptographic key * Support of the five standard modes of operation specified in the NIST Special Publication 800- * * * * 8.4.25 38A, Recommendation for Block Cipher Modes of Operation - Methods and Techniques: - Electronic Code Book (ECB) - Cipher Block Chaining (CBC) - Cipher Feedback (CFB) - Output Feedback (OFB) - Counter (CTR) 8-, 16-, 32-, 64- and 128-bit data size possible in CFB mode Last output data mode allows optimized Message Authentication Code (MAC) generation Hardware counter measures against differential power analysis attacks Connection to DMA Controller capabilities optimizes data transfers for all operating modes Audio Bitstream DAC * Digital Stereo DAC * Oversampled D/A conversion architecture - Oversampling ratio fixed 128x - FIR equalization filter - Digital interpolation filter: Comb4 - 3rd Order Sigma-Delta D/A converters * Digital bitstream outputs * Parallel interface * Connected to DMA Controller for background transfer without CPU intervention 8.4.26 8.4.27 On-Chip Debug * * * * * * * * Debug interface in compliance with IEEE-ISTO 5001-2003 (Nexus 2.0) Class 2+ JTAG access to all on-chip debug functions Advanced program, data, ownership, and watchpoint trace supported NanoTrace JTAG-based trace access Auxiliary port for high-speed trace information Hardware support for 6 program and 2 data breakpoints Unlimited number of software breakpoints supported Automatic CRC check of memory regions JTAG and Boundary Scan * IEEE1149.1 compliant JTAG Interface * Boundary-Scan Chain for board-level testing * Direct memory access and programming capabilities through JTAG Interface * 43 32072BS-AVR32-09/09 AT32UC3A3/A4 9. Boot Sequence This chapter summarizes the boot sequence of the AT32UC3A3. The behavior after power-up is controlled by the Power Manager. For specific details, refer to Section 8. "Power Manager (PM)" on page 37. 9.1 Starting of Clocks After power-up, the device will be held in a reset state by the Power-On Reset circuitry, until the power has stabilized throughout the device. Once the power has stabilized, the device will use the internal RC Oscillator as clock source. On system start-up, the PLLs are disabled. All clocks to all modules are running. No clocks have a divided frequency, all parts of the system receives a clock with the same frequency as the internal RC Oscillator. 9.2 Fetching of Initial Instructions After reset has been released, the AVR32 UC CPU starts fetching instructions from the reset address, which is 0x8000_0000. This address points to the first address in the internal Flash. The code read from the internal Flash is free to configure the system to use for example the PLLs, to divide the frequency of the clock routed to some of the peripherals, and to gate the clocks to unused peripherals. 44 32072BS-AVR32-09/09 AT32UC3A3/A4 10. Electrical Characteristics 10.1 Absolute Maximum Ratings* *NOTICE: Operating Temperature.................................... -40C to +85C Storage Temperature .......................................................... ....60C to +150C Voltage on Input Pin with respect to Ground ........................................-0.3V to 3.6V Maximum Operating Voltage (VDDCORE) ..................... 1.95V Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum Operating Voltage (VDDIO).............................. 3.6V Total DC Output Current on all I/O Pin for TQFP144 packag ................................................... 370 mA for TBGA144 package ................................................. 370 mA 10.2 DC Characteristics The following characteristics are applicable to the operating temperature range: TA = -40C to 85C, unless otherwise specified and are certified for a junction temperature up to TJ = 100C. Symbol Parameter VVDDIO DC Supply Peripheral I/Os VIL Condition Min. Typ. Max. Units 3.0 3.6 V Input Low-level Voltage -0.3 +0.8 V VIH Input High-level Voltage 2.0 VVDDIO+0.3 V VOL Output Low-level Voltage IOL=-2mA for Pin drive x1 IOL=-4mA for Pin drive x2 IOL=-8mA for Pin drive x3 VOH Output High-level Voltage IOL=2mA for Pin drive x1 IOL=4mA for Pin drive x2 IOL=8mA for Pin drive x3 ILEAK Input Leakage Current Pullup resistors disabled CIN Input Capacitance RPULLUP Pull-up Resistance IO Output Current Pin drive x1 Pin drive x2 Pin drive x3 See Table 10-1 ISC Static Current 0.4 VVDDIO-0.4 V A 7 9 On VVDDIN = 3.3V, CPU in static mode V 15 pF 25 Ohm 2.0 4.0 8.0 mA TA =25C TBD A TA =85C TBD A 45 32072BS-AVR32-09/09 AT32UC3A3/A4 Table 10-1. Pins drive capabilities PIN Drive PIN Drive PIN Drive PA00 x3 PB05 x1 PX24 x2 PA01 x1 PB06 x1 PX25 x2 PA02 x1 PB07 x3 PX26 x2 PA03 x1 PB08 x2 PX27 x2 PA04 x1 PB09 x2 PX28 x2 PA05 x1 PB10 x2 PX29 x2 PA06 x1 PB11 x1 PX30 x2 PA07 x1 PC00 x1 PX31 x2 PA08 x3 PC01 x1 PX32 x2 PA09 x2 PC02 x1 PX33 x2 PA10 x2 PC03 x1 PX34 x2 PA11 x2 PC04 x1 PX35 x2 PA12 x1 PC05 x1 PX36 x2 PA13 x1 PX00 x2 PX37 x2 PA14 x1 PX01 x2 PX38 x2 PA15 x1 PX02 x2 PX39 x2 PA16 x1 PX03 x2 PX40 x2 PA17 x1 PX04 x2 PX41 x2 PA18 x1 PX05 x2 PX42 x2 PA19 x1 PX06 x2 PX43 x2 PA20 x1 PX07 x2 PX44 x2 PA21 x1 PX08 x2 PX45 x3 PA22 x1 PX09 x2 PX46 x2 PA23 x1 PX10 x2 PX47 x2 PA24 x1 PX11 x2 PX48 x2 PA25 x1 PX12 x2 PX49 x2 PA26 x1 PX13 x2 PX50 x2 PA27 x2 PX14 x2 PX51 x2 PA28 x1 PX15 x2 PX52 x2 PA29 x1 PX16 x2 PX53 x2 PA30 x1 PX17 x2 PX54 x2 PA31 x1 PX18 x2 PX55 x2 PB00 x1 PX19 x2 PX56 x2 PB01 x1 PX20 x2 PX57 x2 PB02 x1 PX21 x2 PX58 x2 PB03 x1 PX22 x2 PX59 x2 PB04 x1 PX23 x2 46 32072BS-AVR32-09/09 AT32UC3A3/A4 10.3 Regulator characteristics 10.3.1 Electrical characteristics Symbol Parameter VVDDIN VVDDCORE IOUT 10.3.2 Condition Min. Typ. Max. Units Supply voltage (input) 2.7 3.3 3.6 V Supply voltage (output) 1.81 1.85 1.89 V Maximum DC output current with VVDDIN = 3.3V 100 mA Maximum DC output current with VVDDIN = 2.7V 90 mA Decoupling requirements Symbol Parameter CIN1 Typ. Techno. Units Input Regulator Capacitor 1 1 NPO nF CIN2 Input Regulator Capacitor 2 4.7 X7R uF COUT1 Output Regulator Capacitor 1 470 NPO pF COUT2 Output Regulator Capacitor 2 2.2 X7R uF 10.3.3 Condition BOD Table 10-2. BODLEVEL Values BODLEVEL Value Typ. Units. 111111b 1.58 V 101000b 1.62 V 100000b 1.67 V 011000b 1.77 V 000000b 1.92 V The values in Table 10-2 describes the values of the BODLEVEL in the flash FGPFRL register. 10.4 Power Consumption The values in Table 10-3 and Table 10-4 on page 49 are measured values of power consumption with operating conditions as follows: *VDDIO = 3.3V *TA = 25C, TA = 85C *I/Os are configured in input, pull-up enabled. 47 32072BS-AVR32-09/09 AT32UC3A3/A4 Figure 10-1. Measurement setup VDDANA Amp0 VDDIO Amp1 VDDIN Internal Voltage Regulator VDDCORE GNDCORE GNDPLL 48 32072BS-AVR32-09/09 AT32UC3A3/A4 These figures represent the power consumption measured on the power supplies. Table 10-3. Power Consumption for Different Modes(1) Mode Conditions Active CPU running from flash. CPU clocked from PLL0 at f MHz Voltage regulator is on. XIN0 : external clock. (1) XIN1 stopped. XIN32 stopped PLL0 running All peripheral clocks activated. GPIOs on internal pull-up. JTAG unconnected with ext pull-up. Typ : Ta = 25 C CPU is in static mode GPIOs on internal pull-up. All peripheral clocks de-activated. DM and DP pins connected to ground. XIN0,Xin1 and XIN2 are stopped Static Consumption Typ. Unit f = 12 MHz 10 mA f = 24 MHz 18 mA f = 36MHz 27 mA f = 50 MHz 34 mA f = 60 MHz 42 mA on Amp0 0 uA on Amp1 <100 uA 1. Core frequency is generated from XIN0 using the PLL so that 140 MHz < fpll0 < 160 MHz and 10 MHz < fxin0 < 12MHz Table 10-4. Power Consumption by Peripheral in Active Mode Peripheral 10.5 Consumption GPIO 37 SMC 10 SDRAMC 4 ADC 18 EBI 31 INTC 25 TWI 14 PDCA 30 RTC 7 SPI 13 SSC 13 TC 10 USART 35 Unit A/MHz Clock Characteristics These parameters are given in the following conditions: * VDDCORE = 1.8V 49 32072BS-AVR32-09/09 AT32UC3A3/A4 * Ambient Temperature = 25C 10.5.1 CPU/HSB Clock Characteristics Table 10-5. Core Clock Waveform Parameters Symbol Parameter 1/(tCPCPU) CPU Clock Frequency tCPCPU CPU Clock Period 10.5.2 Conditions Min Max Units 66 MHz 15.5 ns PBA Clock Characteristics Table 10-6. PBA Clock Waveform Parameters Symbol Parameter 1/(tCPPBA) PBA Clock Frequency tCPPBA PBA Clock Period 10.5.3 Conditions Min Max Units 66 MHz 15.5 ns PBB Clock Characteristics Table 10-7. PBB Clock Waveform Parameters Symbol Parameter 1/(tCPPBB) PBB Clock Frequency tCPPBB PBB Clock Period 10.5.4 Conditions Min Max Units 66 MHz 15.5 ns XIN Clock Characteristics Table 10-8. XIN Clock Electrical Characteristics Symbol Parameter 1/(tCPXIN) XIN Clock Frequency tCPXIN XIN Clock Period tCHXIN XIN Clock High Half-period tCLXIN XIN Clock Low Half-period CIN RIN Conditions Min Max 3 Units 24 20.0 MHz ns 0.4 x tCPXIN 0.6 x tCPXIN 0.4 x tCPXIN 0.6 x tCPXIN XIN Input Capacitance (1) TBD pF XIN Pulldown Resistor (1) TBD k Note: 1. These characteristics apply only when the Main Oscillator is in bypass mode (i.e., when MOSCEN = 0 and OSCBYPASS = 1 in the CKGR_MOR register.) 10.6 Crystal Oscillator Characteristis The following characteristics are applicable to the operating temperature range: TA = -40C to 85C and worst case of power supply, unless otherwise specified. 50 32072BS-AVR32-09/09 AT32UC3A3/A4 10.6.1 32 KHz Oscillator Characteristics Table 10-9. 32 KHz Oscillator Characteristics Symbol Parameter 1/(tCP32KHz) Crystal Oscillator Frequency CL Equivalent Load Capacitance Conditions Min Note: Max 32 768 Duty Cycle tST Typ Startup Time RS = TBD k , CL = TBD pF Unit Hz 6 12.5 pF TBD TBD % TBD ms Max Unit 16 MHz (1) 1. RS is the equivalent series resistance, CL is the equivalent load capacitance. 10.6.2 Main Oscillators Characteristics Table 10-10. Main Oscillator Characteristics Symbol Parameter 1/(tCPMAIN) Crystal Oscillator Frequency CL1, CL2 Internal Load Capacitance (CL1 = CL2) CL Equivalent Load Capacitance Conditions Startup Time IOSC Current Consumption Notes: Typ 3 Duty Cycle tST Min 40 12 pF TBD pF 50 60 % TBD ms Active mode @TBD MHz TBD A Standby mode @TBD V TBD A Max Unit 80 240 MHz TBD TBD MHz active mode TBD mA standby mode TBD A 1. CS is the shunt capacitance 10.6.3 PLL Characteristics Table 10-11. Phase Lock Loop Characteristics Symbol Parameter FOUT Output Frequency FIN Input Frequency IPLL Current Consumption Note: Conditions Min Typ 1. Startup time depends on PLL RC filter. A calculation tool is provided by Atmel. 51 32072BS-AVR32-09/09 AT32UC3A3/A4 10.7 ADC Characteristics Table 10-12. Channel Conversion Time and ADC Clock Parameter Conditions ADC Clock Frequency ADC Clock Frequency Startup Time Min Max Units 10-bit resolution mode 5 MHz 8-bit resolution mode 8 MHz Return from Idle Mode 20 s Track and Hold Acquisition Time Typ 600 ns Conversion Time ADC Clock = 5 MHz Conversion Time ADC Clock = 8 MHz 1.25 s Throughput Rate ADC Clock = 5 MHz 384(1) kSPS Throughput Rate ADC Clock = 8 MHz 533(2) kSPS Notes: 2 s 1. Corresponds to 13 clock cycles at 5 MHz: 3 clock cycles for track and hold acquisition time and 10 clock cycles for conversion. 2. Corresponds to 15 clock cycles at 8 MHz: 5 clock cycles for track and hold acquisition time and 10 clock cycles for conversion. Table 10-13. Analog Inputs Parameter Min Input Voltage Range Typ 0 Input Leakage Current Input Capacitance Max Units VDDANA TBD A 17 pF Table 10-14. Transfer Characteristics Parameter Conditions Min Resolution Typ Max 10 Absolute Accuracy f=5MHz Integral Non-linearity f=5MHz Differential Non-linearity f=5MHz Offset Error f=5MHz Gain Error f=5MHz Units Bit 0.8 LSB 0.35 0.5 LSB 0.3 0.5 LSB -0.5 0.5 LSB -0.5 0.5 LSB 52 32072BS-AVR32-09/09 AT32UC3A3/A4 10.8 USB Transceiver Characteristics 10.8.1 Electrical Characteristics Table 10-15. Electrical Parameters Symbol Parameter Conditions Min Typ Max Unit TBD V Input Levels VIL Low Level VIH High Level VDI Differential Input Sensivity VCM Differential Input Common Mode Range CIN Transceiver capacitance Capacitance to ground on each line I Hi-Z State Data Line Leakage 0V < VIN < 3.3V REXT Recommended External USB Series Resistor In series with each USB pin with 5% VOL Low Level Output Measured with RL of 1.425 k tied to 3.6V TBD TBD V VOH High Level Output Measured with RL of 14.25 k tied to GND TBD TBD V VCRS Output Signal Crossover Voltage TBD TBD V Max Unit |(D+) - (D-)| TBD V TBD V TBD TBD TBD V TBD pF TBD A TBD Output Levels 10.8.2 Switching Characteristics Table 10-16. In Low Speed Symbol Parameter Conditions Min Typ tFR Transition Rise Time CLOAD = 400 pF TBD TBD ns tFE Transition Fall Time CLOAD = 400 pF TBD TBD ns tFRFM Rise/Fall time Matching CLOAD = 400 pF TBD TBD % Max Unit Table 10-17. In Full Speed Symbol Parameter Conditions Min Typ tFR Transition Rise Time CLOAD = 50 pF TBD TBD ns tFE Transition Fall Time CLOAD = 50 pF TBD TBD ns tFRFM Rise/Fall time Matching TBD TBD % 53 32072BS-AVR32-09/09 AT32UC3A3/A4 10.9 EBI Timings These timings are given for worst case process, T = 85 C, VDDCORE = 1.65V, VDDIO = 3V and 40 pF load capacitance. Table 10-18. SMC Clock Signal. Symbol Parameter 1/(tCPSMC) SMC Controller Clock Frequency Note: Max(1) Units 1/(tcpcpu) MHz 1. The maximum frequency of the SMC interface is the same as the max frequency for the HSB. Table 10-19. SMC Read Signals with Hold Settings Symbol Parameter Min Units NRD Controlled (READ_MODE = 1) SMC1 Data Setup before NRD High SMC2 Data Hold after NRD High 12 0 SMC3 NRD High to NBS0/A0 Change SMC4 NRD High to NBS1 Change(1) (1) nrd hold length * tCPSMC - 1.3 (1) SMC5 NRD High to NBS2/A1 Change SMC7 NRD High to A2 - A23 Change(1) SMC8 NRD High to NCS Inactive SMC9 NRD Pulse Width nrd hold length * tCPSMC - 1.3 (1) nrd hold length * tCPSMC - 1.3 ns nrd hold length * tCPSMC - 1.3 (nrd hold length - ncs rd hold length) * tCPSMC - 2.3 nrd pulse length * tCPSMC - 1.4 NRD Controlled (READ_MODE = 0) SMC10 Data Setup before NCS High SMC11 Data Hold after NCS High SMC12 NCS High to NBS0/A0 Change(1) ncs rd hold length * tCPSMC - 2.3 SMC13 NCS High to NBS0/A0 Change (1) ncs rd hold length * tCPSMC - 2.3 SMC14 NCS High to NBS2/A1 Change(1) ncs rd hold length * tCPSMC - 2.3 SMC16 NCS High to A2 - A23 Change(1) ncs rd hold length * tCPSMC - 4 SMC17 NCS High to NRD Inactive(1) SMC18 NCS Pulse Width Note: 11.5 0 ns ncs rd hold length - nrd hold length)* tCPSMC - 1.3 ncs rd pulse length * tCPSMC - 3.6 1. hold length = total cycle duration - setup duration - pulse duration. "hold length" is for "ncs rd hold length" or "nrd hold length". 54 32072BS-AVR32-09/09 AT32UC3A3/A4 Table 10-20. SMC Read Signals with no Hold Settings Symbol Parameter Min Units NRD Controlled (READ_MODE = 1) SMC19 Data Setup before NRD High SMC20 Data Hold after NRD High 13.7 ns 1 NRD Controlled (READ_MODE = 0) SMC21 Data Setup before NCS High SMC22 Data Hold after NCS High 13.3 ns 0 Table 10-21. SMC Write Signals with Hold Settings Symbol Parameter Min Units NRD Controlled (READ_MODE = 1) SMC23 Data Out Valid before NWE High (nwe pulse length - 1) * tCPSMC - 0.9 SMC24 Data Out Valid after NWE High(1) nwe hold length * tCPSMC - 6 SMC25 NWE High to NBS0/A0 Change SMC26 NWE High to NBS1 Change(1) (1) nwe hold length * tCPSMC - 1.9 nwe hold length * tCPSMC - 1.9 (1) SMC29 NWE High to A1 Change SMC31 NWE High to A2 - A23 Change(1) ns nwe hold length * tCPSMC - 1.9 (1) SMC32 NWE High to NCS Inactive SMC33 NWE Pulse Width nwe hold length * tCPSMC - 1.7 (nwe hold length - ncs wr hold length)* tCPSMC - 2.9 nwe pulse length * tCPSMC - 0.9 NRD Controlled (READ_MODE = 0) SMC34 Data Out Valid before NCS High SMC35 Data Out Valid after NCS High (1) SMC36 NCS High to NWE Inactive(1) Note: (ncs wr pulse length - 1)* tCPSMC - 4.6 ncs wr hold length * tCPSMC - 5.8 ns (ncs wr hold length - nwe hold length)* tCPSMC - 0.6 1. hold length = total cycle duration - setup duration - pulse duration. "hold length" is for "ncs wr hold length" or "nwe hold length" 55 32072BS-AVR32-09/09 AT32UC3A3/A4 Table 10-22. SMC Write Signals with No Hold Settings (NWE Controlled only). Symbol Parameter Min SMC37 NWE Rising to A2-A25 Valid 5.4 SMC38 NWE Rising to NBS0/A0 Valid 5 SMC39 NWE Rising to NBS1 Change 5 SMC40 NWE Rising to A1/NBS2 Change 5 SMC41 NWE Rising to NBS3 Change 5 SMC42 NWE Rising to NCS Rising SMC43 Data Out Valid before NWE Rising SMC44 Data Out Valid after NWE Rising SMC45 NWE Pulse Width Units ns 5.1 (nwe pulse length - 1) * tCPSMC - 1.2 5 nwe pulse length * tCPSMC - 0.9 Figure 10-2. SMC Signals for NCS Controlled Accesses. SMC16 SMC16 SMC16 SMC12 SMC13 SMC14 SMC15 SMC12 SMC13 SMC14 SMC15 A2-A25 SMC12 SMC13 SMC14 SMC15 A0/A1/NBS[3:0] NRD SMC17 SMC17 NCS SMC21 SMC18 SMC18 SMC18 SMC22 SMC10 SMC11 SMC34 SMC35 D0 - D15 SMC36 NWE 56 32072BS-AVR32-09/09 AT32UC3A3/A4 Figure 10-3. SMC Signals for NRD and NRW Controlled Accesses. SMC37 SMC7 SMC7 SMC31 A2-A25 SMC25 SMC26 SMC29 SMC30 SMC3 SMC4 SMC5 SMC6 SMC38 SMC39 SMC40 SMC41 SMC3 SMC4 SMC5 SMC6 A0/A1/NBS[3:0] SMC42 SMC32 SMC8 NCS SMC8 SMC9 SMC9 NRD SMC19 SMC20 SMC43 SMC44 SMC1 SMC23 SMC2 SMC24 D0 - D15 SMC45 SMC33 NWE 10.9.1 SDRAM Signals These timings are given for 10 pF load on SDCK and 40 pF on other signals. Table 10-23. SDRAM Clock Signal. Symbol Parameter 1/(tCPSDCK) SDRAM Controller Clock Frequency Note: Max(1) Units 1/(tcpcpu) MHz 1. The maximum frequency of the SDRAMC interface is the same as the max frequency for the HSB. Table 10-24. SDRAM Clock Signal. Symbol Parameter Min Units SDRAMC1 SDCKE High before SDCK Rising Edge 7.4 ns SDRAMC2 SDCKE Low after SDCK Rising Edge 3.2 SDRAMC3 SDCKE Low before SDCK Rising Edge SDRAMC4 SDCKE High after SDCK Rising Edge 2.9 SDRAMC5 SDCS Low before SDCK Rising Edge 7.5 SDRAMC6 SDCS High after SDCK Rising Edge 1.6 SDRAMC7 RAS Low before SDCK Rising Edge 7.2 SDRAMC8 RAS High after SDCK Rising Edge 2.3 SDRAMC9 SDA10 Change before SDCK Rising Edge 7.6 SDRAMC10 SDA10 Change after SDCK Rising Edge 1.9 7 57 32072BS-AVR32-09/09 AT32UC3A3/A4 Table 10-24. SDRAM Clock Signal. Symbol Parameter Min SDRAMC11 Address Change before SDCK Rising Edge 6.2 SDRAMC12 Address Change after SDCK Rising Edge 2.2 SDRAMC13 Bank Change before SDCK Rising Edge 6.3 SDRAMC14 Bank Change after SDCK Rising Edge 2.4 SDRAMC15 CAS Low before SDCK Rising Edge 7.4 SDRAMC16 CAS High after SDCK Rising Edge 1.9 SDRAMC17 DQM Change before SDCK Rising Edge 6.4 SDRAMC18 DQM Change after SDCK Rising Edge 2.2 SDRAMC19 D0-D15 in Setup before SDCK Rising Edge 9 SDRAMC20 D0-D15 in Hold after SDCK Rising Edge 0 SDRAMC23 SDWE Low before SDCK Rising Edge 7.6 SDRAMC24 SDWE High after SDCK Rising Edge 1.8 SDRAMC25 D0-D15 Out Valid before SDCK Rising Edge 7.1 SDRAMC26 D0-D15 Out Valid after SDCK Rising Edge 1.5 Units ns 58 32072BS-AVR32-09/09 AT32UC3A3/A4 Figure 10-4. SDRAMC Signals relative to SDCK. SDCK SDRAMC1 SDRAMC2 SDRAMC3 SDRAMC4 SDCKE SDRAMC5 SDRAMC6 SDRAMC7 SDRAMC8 SDRAMC5 SDRAMC6 SDRAMC5 SDRAMC6 SDCS RAS SDRAMC15 SDRAMC16 SDRAMC15 SDRAMC16 CAS SDRAMC23 SDRAMC24 SDWE SDRAMC9 SDRAMC10 SDRAMC9 SDRAMC10 SDRAMC9 SDRAMC10 SDRAMC11 SDRAMC12 SDRAMC11 SDRAMC12 SDRAMC11 SDRAMC12 SDRAMC13 SDRAMC14 SDRAMC13 SDRAMC14 SDRAMC13 SDRAMC14 SDRAMC17 SDRAMC18 SDRAMC17 SDRAMC18 SDA10 A0 - A9, A11 - A13 BA0/BA1 DQM0 DQM3 SDRAMC19 SDRAMC20 D0 - D15 Read SDRAMC25 SDRAMC26 D0 - D15 to Write 59 32072BS-AVR32-09/09 AT32UC3A3/A4 10.10 JTAG Timings 10.10.1 JTAG Interface Signals Table 10-25. JTAG Interface Timing specification Symbol JTAG0 JTAG1 JTAG2 JTAG3 JTAG4 JTAG5 JTAG6 JTAG7 JTAG8 JTAG9 JTAG10 Note: Parameter Conditions Min TCK Low Half-period (1) Max 6 ns TCK High Half-period (1) 3 ns TCK Period (1) 9 ns TDI, TMS Setup before TCK High (1) 1 ns TDI, TMS Hold after TCK High (1) 0 ns TDO Hold Time (1) 4 ns TCK Low to TDO Valid (1) Device Inputs Setup Time (1) ns Device Inputs Hold Time (1) ns Device Outputs Hold Time (1) ns TCK to Device Outputs Valid (1) ns 6 Units ns 1. VVDDIO from 3.0V to 3.6V, maximum external capacitor = 40pF 60 32072BS-AVR32-09/09 AT32UC3A3/A4 Figure 10-5. JTAG Interface Signals JTAG2 TCK JTAG JTAG1 0 TMS/TDI JTAG3 JTAG4 JTAG7 JTAG8 TDO JTAG5 JTAG6 Device Inputs Device Outputs JTAG9 JTAG10 10.11 SPI Characteristics Figure 10-6. SPI Master mode with (CPOL = NCPHA = 0) or (CPOL= NCPHA= 1) SPCK SPI0 SPI1 MISO SPI2 MOSI 61 32072BS-AVR32-09/09 AT32UC3A3/A4 Figure 10-7. SPI Master mode with (CPOL=0 and NCPHA=1) or (CPOL=1 and NCPHA=0) SPCK SPI3 SPI4 MISO SPI5 MOSI Figure 10-8. SPI Slave mode with (CPOL=0 and NCPHA=1) or (CPOL=1 and NCPHA=0) SPCK SPI6 MISO SPI7 SPI8 MOSI Figure 10-9. SPI Slave mode with (CPOL = NCPHA = 0) or (CPOL= NCPHA= 1) SPCK SPI9 MISO SPI10 SPI11 MOSI 62 32072BS-AVR32-09/09 AT32UC3A3/A4 Table 10-26. SPI Timings Symbol SPI0 Parameter Conditions MISO Setup time before SPCK rises (master) SPI1 MISO Hold time after SPCK rises (master) SPI2 SPCK rising to MOSI Delay (master) (1) 3.3V domain (1) 3.3V domain 3.3V domain (1) (1) SPI3 MISO Setup time before SPCK falls (master) 3.3V domain SPI4 MISO Hold time after SPCK falls (master) 3.3V domain (1) SPI5 SPCK falling to MOSI Delay (master) 3.3V domain (1) SPI6 SPCK falling to MISO Delay (slave) SPI7 MOSI Setup time before SPCK rises (slave) SPI8 MOSI Hold time after SPCK rises (slave) SPI9 SPCK rising to MISO Delay (slave) SPI10 MOSI Setup time before SPCK falls (slave) SPI11 Notes: MOSI Hold time after SPCK falls (slave) Min Max (2) 22 + (tCPMCK)/2 Units ns 0 ns 7 (2) 22 + (tCPMCK)/2 ns ns 0 ns 7 ns 26.5 ns 3.3V domain (1) 3.3V domain (1) 0 ns 3.3V domain (1) 1.5 ns 3.3V domain (1) 3.3V domain (1) 0 ns 3.3V domain (1) 1 ns 27 ns 1. 3.3V domain: VVDDIO from 3.0V to 3.6V, maximum external capacitor = 40 pF. 2. tCPMCK: Master Clock period in ns. 10.12 Flash Characteristics The following table gives the device maximum operating frequency depending on the field FWS of the Flash FSR register. This field defines the number of wait states required to access the Flash Memory. Table 10-27. Flash Wait States FWS Read Operations Maximum Operating Frequency (MHz) 0 1 cycle 36 1 2 cycles 66 63 32072BS-AVR32-09/09 AT32UC3A3/A4 11. Mechanical Characteristics 11.1 11.1.1 Thermal Considerations Thermal Data Table 11-1 summarizes the thermal resistance data depending on the package. Table 11-1. 11.1.2 Thermal Resistance Data Symbol Parameter Condition Package Typ JA Junction-to-ambient thermal resistance Still Air TQFP144 TBD JC Junction-to-case thermal resistance TQFP144 TBD JA Junction-to-ambient thermal resistance TBGA144 TBD JC Junction-to-case thermal resistance TBGA144 TBD JA Junction-to-ambient thermal resistance VFBGA100 TBD JC Junction-to-case thermal resistance VFBGA100 TBD Still Air Still Air Unit C/W C/W C/W Junction Temperature The average chip-junction temperature, TJ, in C can be obtained from the following: 1. T J = T A + P D x JA( 2. TJ = TA + ( P D ( HEATSINK +x ) JC )) where: * JA = package thermal resistance, Junction-to-ambient (C/W), provided in Table 11-1 on page 64. * JC = package thermal resistance, Junction-to-case thermal resistance (C/W), provided in Table 11-1 on page 64. * HEAT SINK = cooling device thermal resistance (C/W), provided in the device datasheet. * PD = device power consumption (W) estimated from data provided in the section "Regulator characteristics" on page 47. * TA = ambient temperature (C). From the first equation, the user can derive the estimated lifetime of the chip and decide if a cooling device is necessary or not. If a cooling device is to be fitted on the chip, the second equation should be used to compute the resulting average chip-junction temperature TJ in C. 64 32072BS-AVR32-09/09 AT32UC3A3/A4 11.2 Package Drawings Figure 11-1. TBGA 144 package drawing 65 32072BS-AVR32-09/09 AT32UC3A3/A4 Figure 11-2. LQFP-144 package drawing Table 11-2. Device and Package Maximum Weight TBD Table 11-3. mg Package Characteristics Moisture Sensitivity Level Table 11-4. TBD Package Reference JEDEC Drawing Reference MS-026 JESD97 Classification E3 66 32072BS-AVR32-09/09 AT32UC3A3/A4 Table 11-5. Device and Package Maximum Weight TBD mg Figure 11-3. VFBGA-100 package drawing 67 32072BS-AVR32-09/09 AT32UC3A3/A4 11.3 Soldering Profile Table 11-6 gives the recommended soldering profile from J-STD-20. Table 11-6. Soldering Profile Profile Feature Green Package Average Ramp-up Rate (217C to Peak) TBD Preheat Temperature 175C 25C TBD Temperature Maintained Above 217C TBD Time within 5C of Actual Peak Temperature TBD Peak Temperature Range TBD Ramp-down Rate TBD Time 25C to Peak Temperature TBD Note: It is recommended to apply a soldering temperature higher than 250C. A maximum of three reflow passes is allowed per component. 68 32072BS-AVR32-09/09 AT32UC3A3/A4 12. Ordering Information Ordering Code Package Conditioning Temperature Operating Range AT32UC3A3256S-ALUT 144 lead LQFP Tray Industrial (-40C to 85C) AT32UC3A3256S-ALUR 144 lead LQFP Reels Industrial (-40C to 85C) AT32UC3A3256S-CTUT 144 balls TBGA Tray Industrial (-40C to 85C) AT32UC3A3256S-CTUR 144 balls TBGA Reels Industrial (-40C to 85C) AT32UC3A3256-ALUT 144 lead LQFP Tray Industrial (-40C to 85C) AT32UC3A3256-ALUR 144 lead LQFP Reels Industrial (-40C to 85C) AT32UC3A3256-CTUT 144 balls TBGA Tray Industrial (-40C to 85C) AT32UC3A3256-CTUR 144 balls TBGA Reels Industrial (-40C to 85C) AT32UC3A3128S-ALUT 144 lead LQFP Tray Industrial (-40C to 85C) AT32UC3A3128S-ALUR 144 lead LQFP Reels Industrial (-40C to 85C) AT32UC3A3128S-CTUT 144 balls TBGA Tray Industrial (-40C to 85C) AT32UC3A3128S-CTUR 144 balls TBGA Reels Industrial (-40C to 85C) AT32UC3A3128-ALUT 144 lead LQFP Tray Industrial (-40C to 85C) AT32UC3A3128-ALUR 144 lead LQFP Reels Industrial (-40C to 85C) AT32UC3A3128-CTUT 144 balls TBGA Tray Industrial (-40C to 85C) AT32UC3A3128-CTUR 144 balls TBGA Reels Industrial (-40C to 85C) AT32UC3A364S-ALUT 144 lead LQFP Tray Industrial (-40C to 85C) AT32UC3A364S-ALUR 144 lead LQFP Reels Industrial (-40C to 85C) AT32UC3A364S-CTUT 144 balls TBGA Tray Industrial (-40C to 85C) AT32UC3A364S-CTUR 144 balls TBGA Reels Industrial (-40C to 85C) AT32UC3A364-ALUT 144 lead LQFP Tray Industrial (-40C to 85C) AT32UC3A364-ALUR 144 lead LQFP Reels Industrial (-40C to 85C) AT32UC3A364-CTUT 144 balls TBGA Tray Industrial (-40C to 85C) AT32UC3A364-CTUR 144 balls TBGA Reels Industrial (-40C to 85C) AT32UC3A4256S AT32UC3A4256S-C1UT 100 balls VFBGA Tray Industrial (-40C to 85C) AT32UC3A4256S-C1UR 100 balls VFBGA Reels Industrial (-40C to 85C) AT32UC3A4256 AT32UC3A4256-C1UT 100 balls VFBGA Tray Industrial (-40C to 85C) AT32UC3A4256-C1UR 100 balls VFBGA Reels Industrial (-40C to 85C) AT32UC3A4128S AT32UC3A4128S-C1UT 100 balls VFBGA Tray Industrial (-40C to 85C) AT32UC3A4128S-C1UR 100 balls VFBGA Reels Industrial (-40C to 85C) AT32UC3A4128 AT32UC3A4128-C1UT 100 balls VFBGA Tray Industrial (-40C to 85C) AT32UC3A4128-C1UR 100 balls VFBGA Reels Industrial (-40C to 85C) AT32UC3A464S AT32UC3A464S-C1UT 100 balls VFBGA Tray Industrial (-40C to 85C) AT32UC3A464S-C1UR 100 balls VFBGA Reels Industrial (-40C to 85C) AT32UC3A464 AT32UC3A464-C1UT 100 balls VFBGA Tray Industrial (-40C to 85C) AT32UC3A464-C1UR 100 balls VFBGA Reels Industrial (-40C to 85C) Device AT32UC3A3256S AT32UC3A3256 AT32UC3A3128S AT32UC3A3128 AT32UC3A364S AT32UC3A364 69 32072BS-AVR32-09/09 AT32UC3A3/A4 13. Errata 13.1 13.1.1 Rev. E Processor and Architecture 1. LDM instruction with PC in the register list and without ++ increments Rp For LDM with PC in the register list: the instruction behaves as if the ++ field is always set, ie the pointer is always updated. This happens even if the ++ field is cleared. Specifically, the increment of the pointer is done in parallel with the testing of R12. Fix/Workaround None. 13.1.2 ADC 1. Sleep Mode activation needs additional A to D conversion If the ADC sleep mode is activated when the ADC is idle the ADC will not enter sleep mode before after the next AD conversion. Fix/Workaround Activate the sleep mode in the mode register and then perform an AD conversion. 13.1.3 SPI 1. SPI Bad Serial Clock Generation on 2nd chip_select when SCBR = 1, CPOL=1 and NCPHA=0 When multiple CS are in use, if one of the baudrate equals to 1 and one of the others doesn't equal to 1, and CPOL=1 and CPHA=0, then an additional pulse will be generated on SCK. Fix/workaround When multiple CS are in use, if one of the baudrate equals 1, the other must also equal 1 if CPOL=1 and CPHA=0. 2. SPI Disable does not work in Slave mode Fix/workaround Read the last received data then perform a Software reset. 13.2 13.2.1 Rev. D Processor and Architecture 1. LDM instruction with PC in the register list and without ++ increments Rp For LDM with PC in the register list: the instruction behaves as if the ++ field is always set, ie the pointer is always updated. This happens even if the ++ field is cleared. Specifically, the increment of the pointer is done in parallel with the testing of R12. Fix/Workaround None. 2. RETE instruction does not clear SREG[L] from interrupts. The RETE instruction clears SREG[L] as expected from exceptions. Fix/Workaround 70 32072BS-AVR32-09/09 AT32UC3A3/A4 When using the STCOND instruction, clear SREG[L] in the stacked value of SR before returning from interrupts with RETE. 3. Exceptions when system stack is protected by MPU RETS behaves incorrectly when MPU is enabled and MPU is configured so that system stack is not readable in unprivileged mode. Fix/Workaround Workaround 1: Make system stack readable in unprivileged mode, or Workaround 2: Return from supervisor mode using rete instead of rets. This requires : 1. Changing the mode bits from 001b to 110b before issuing the instruction. Updating the mode bits to the desired value must be done using a single mtsr instruction so it is done atomically. Even if this step is described in general as not safe in the UC technical reference guide, it is safe in this very specific case. 2. Execute the RETE instruction. 4. Multiply instructions do not work on RevD. All the multiply instructions do not work. Fix/Workaround Do not use the multiply instructions. 13.2.2 ADC 1. Sleep Mode activation needs additional A to D conversion If the ADC sleep mode is activated when the ADC is idle the ADC will not enter sleep mode before after the next AD conversion. Fix/Workaround Activate the sleep mode in the mode register and then perform an AD conversion. 13.2.3 SPI 1. SPI Bad Serial Clock Generation on 2nd chip_select when SCBR = 1, CPOL=1 and NCPHA=0 When multiple CS are in use, if one of the baudrate equals to 1 and one of the others doesn't equal to 1, and CPOL=1 and CPHA=0, then an additional pulse will be generated on SCK. Fix/workaround When multiple CS are in use, if one of the baudrate equals 1, the other must also equal 1 if CPOL=1 and CPHA=0. 2. SPI Disable does not work in Slave mode Fix/workaround Read the last received data then perform a Software reset. 13.2.4 TWI 1. TWIM Version Register is zero TWIM Version Register (VR) is zero instead of 0x100. Fix/Workaround None. 71 32072BS-AVR32-09/09 AT32UC3A3/A4 14. Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 14.1 14.2 Rev. B - 09/09 1. Updated the datasheet with new device AT32UC3A4. 1. Initial revision. Rev. A - 03/09 72 32072BS-AVR32-09/09 AT32UC3A3/A4 Table of Contents 1 Description ............................................................................................... 3 2 Blockdiagram ........................................................................................... 4 2.1 Processor and Architecture ...............................................................................5 3 Signals Description ................................................................................. 6 4 Package and Pinout ............................................................................... 11 5 6 7 8 9 4.1 Package ...........................................................................................................11 4.2 Peripheral Multiplexing on I/O lines .................................................................14 4.3 Signal Descriptions ..........................................................................................17 4.4 Power Considerations .....................................................................................23 Power Considerations ........................................................................... 24 5.1 Power Supplies ................................................................................................24 5.2 Voltage Regulator ............................................................................................24 I/O Line Considerations ......................................................................... 25 6.1 JTAG Pins .......................................................................................................25 6.2 RESET_N Pin ..................................................................................................25 6.3 TWI Pins ..........................................................................................................25 6.4 GPIO Pins ........................................................................................................25 Memories ................................................................................................ 26 7.1 Embedded Memories ......................................................................................26 7.2 Physical Memory Map .....................................................................................26 7.3 Peripheral Address Map ..................................................................................27 7.4 CPU Local Bus Mapping .................................................................................29 Peripherals ............................................................................................. 30 8.1 Clock Connections ...........................................................................................30 8.2 Peripheral Multiplexing on I/O lines .................................................................30 8.3 Oscillator Pinout ..............................................................................................33 8.4 Peripheral overview .........................................................................................35 Boot Sequence ....................................................................................... 44 9.1 Starting of Clocks ............................................................................................44 9.2 Fetching of Initial Instructions ..........................................................................44 10 Electrical Characteristics ...................................................................... 45 i 32072BS-AVR32-09/09 AT32UC3A3/A4 10.1 Absolute Maximum Ratings* ...........................................................................45 10.2 DC Characteristics ...........................................................................................45 10.3 Regulator characteristics .................................................................................47 10.4 Power Consumption ........................................................................................47 10.5 Clock Characteristics .......................................................................................49 10.6 Crystal Oscillator Characteristis ......................................................................50 10.7 ADC Characteristics ........................................................................................52 10.8 USB Transceiver Characteristics .....................................................................53 10.9 EBI Timings .....................................................................................................54 10.10 JTAG Timings ..................................................................................................60 10.11 SPI Characteristics ..........................................................................................61 10.12 Flash Characteristics .......................................................................................63 11 Mechanical Characteristics ................................................................... 64 11.1 Thermal Considerations ..................................................................................64 11.2 Package Drawings ...........................................................................................65 11.3 Soldering Profile ..............................................................................................68 12 Ordering Information ............................................................................. 69 13 Errata ....................................................................................................... 70 13.1 Rev. E ..............................................................................................................70 13.2 Rev. D ..............................................................................................................70 14 Datasheet Revision History .................................................................. 72 14.1 Rev. B - 09/09 .................................................................................................72 14.2 Rev. A - 03/09 .................................................................................................72 ii 32072BS-AVR32-09/09 Headquarters International Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Technical Support avr32@atmel.com Sales Contact www.atmel.com/contacts Product Contact Web Site www.atmel.com Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. 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