REVISIONS
LTR DESCRIPTION DATE (YR-MO-DA) APPROVED
A
Changes are in accordance with the notice of revision 5962-R217-94. - tvn 94-06-16 Monica L. Poelking
B
Changes are in accordance with the notice of revision 5962-R222-96. - tvn 96-09-30 Monica L. Poelking
C
Update the boilerplate to the current requirements of MIL-PRF-38535. - jak 08-01-28 Thomas M. Hess
D
Add footnote 8/ for test condition of total power supply current (ICCT) to table I.
Update boilerplate paragraphs to current requirements of MIL-PRF-38535.
- LTG
10-01-19 Thomas M. Hess
REV
SHEET
REV D D D
SHEET 15 16 17
REV STATUS REV D D D D D D D D D D D D D D
OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14
PMIC N/A PREPARED BY
Thanh V. Nguyen
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 4321 8-3990
http://www.dscc.dla.mil
STANDARD
MICROCIRCUIT
DRAWING
CHECKED BY
Thanh V. Nguyen
THIS DRAWING IS AVAILABLE
FOR USE BY ALL
DEPARTMENTS
APPROVED BY
Monica L. Poelking
MICROCIRCUIT, DIGITAL, FAST CMOS,
DUAL 1-OF-4 DECODER WITH ENABLE, TTL
COMPATIBLE INPUTS AND LIMITED OUTPUT
VOLTAGE SWING, MONOLITHIC SILICON
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
DRAWING APPROVAL DATE
94-03-04
AMSC N/A
REVISION LEVEL
D SIZE
A CAGE CODE
67268
5962-92202
SHEET
1 OF
17
DSCC FORM 2233
APR 97 5962-E142-10
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-92202
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
D SHEET 2
DSCC FORM 2234
APR 97
1. SCOPE
1.1 Scope. This drawing documents t wo product assur ance class levels consisting of high reliability (device classes Q and
M) and space application (de vice class V). A choice of case outlines and lead finishes ar e available and are reflected in the Part
or Identifying Number (PIN). When availa ble, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN.
1.2 PIN. The PIN is as shown in the following example:
5962 - 92202 01 M E A
Federal
stock class
designator
RHA
designator
(see 1.2.1)
Device
type
(see 1.2.2)
Device
class
designator
Case
outline
(see 1.2.4)
Lead
finish
(see 1.2.5)
\ / (see 1.2.3)
\/
Drawing number
1.2.1 RHA designator. Device classes Q and V RHA marked dev ices meet the MIL-PRF-38535 specified RHA levels and are
marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF- 38535, appendix A
specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a n on-RHA device.
1.2.2 Device type(s). The device type(s) identify the circuit function as follows:
Device type Generic number Circuit function
01, 02 54FCT139T Dual 1-of-4 decoder with enable, TTL compatible
inputs and limited output voltage swing
03, 04 54FCT139AT Dual 1-of-4 decoder with ena ble, T TL compatible
inputs and limited output voltage swing
05, 06 54FCT139CT Dual 1-of-4 decoder with enable, TTL compatible
inputs and limited output voltage swing
1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as
follows:
Device class Device requirements docum entation
M Vendor self-certification to the requireme nts for MIL-STD-883 compliant, non-
JAN class level B microcircuits in accordance with MIL-PRF-38535, append ix A
Q or V Certification and qualification to MIL-PRF-38535
1.2.4 Case outline(s). The case outline(s) are as desi gnated in MIL-STD-1835 and as foll ows:
Outline letter Descriptive designator Terminals Package style
E GDIP1-T16 or CDIP2-T16 16 Dual-in-line
F GDFP2-F16 or CDFP3-F16 16 Flat pack
2 CQCC1-N20 20 Leadless chip carrier
1.2.5 Lead finish. The lead finish is as speci fied in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535,
appendix A for device class M.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-92202
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
D SHEET 3
DSCC FORM 2234
APR 97
1.3 Absolute maximum ratings. 1/ 2/ 3/
Supply voltage range (VCC) ....................................................................... -0.5 V dc to +7.0 V dc
DC input voltage range (VIN) .................................................................... -0.5 V dc to VCC + 0.5 V dc 4/
DC output voltage range (VOUT) ................................................................ -0.5 V dc to VCC + 0.5 V dc 4/
DC input clamp current (IIK) (VIN = -0.5 V) ................................................. -20 mA
DC output clamp current (IOK) (VOUT -0.5 V and +7.0 V) ........................... 20 mA
DC output source current (IOH) (per output) ............................................ -30 mA
DC output sink current (IOL) (per output) ................................................. +70 mA
DC VCC current (ICC) ............................................................................... 260 mA
Ground current (IGND) .............................................................................. +550 mA
Storage temperature range (TSTG) ............................................................ -65C to +150C
Case temperature under bias (TBIAS) ...................................................... -65C to +135C
Lead temperature (soldering, 10 seconds) ............................................... +300 C
Thermal resistance, junction-to-case (JC) ................................................ See MIL-STD-1835
Junction temperature (TJ) ....................................................................... +175C
Maximum power dissipation (PD) .............................................................. 500 mW
1.4 Recommended operating conditions. 2/ 3/
Supply voltage range (VCC) ...................................................................... +4.5 V dc to +5.5 V dc
Input voltage range (VIN) .......................................................................... +0.0 V dc to VCC
Output voltage range (VOUT) ..................................................................... +0.0 V dc to VCC
Maximum low level input voltage (VIL) ..................................................... 0.8 V
Minimum high level input voltage (VIH) ..................................................... 2.0 V
Case operating temperature rang e (TC) ................................................... -55C to +125C
Maximum input rise or fall rate (t/V):
(from VIN = 0.3 V to 2.7 V, 2.7 V to 0.3 V) .............................................. 5 ns/V
Maximum high level output current (IOH):
Device types 01, 03, and 05 ................................................................. -12 mA
Device types 02, 04, and 06 ................................................................. -6 mA
Maximum low level output current (IOL) .................................................... 32 mA
1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the
maximum levels may degrade performance and affect reliability.
2/ Unless otherwise noted, all voltages ar e referenced to GND.
3/ The limits for the parameters specified herein shall apply over the full specified VCC rang e and case temperature range of
-55C to +125C.
4/ For VCC 6.5 V, the upper limit on the range is limited to 7.0 V.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-92202
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
D SHEET 4
DSCC FORM 2234
APR 97
2. APPLICABLE DOCUMENTS
2.1 Government specification, standards, and han dbooks. The following specification, standards, an d handbooks form a part
of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the
solicitation or contract.
DEPARTMENT OF DEFENSE SPECIFICATION
MIL-PRF-385 35 - Integrated Circuits, Manufacturing, General Specification for.
DEPARTMENT OF DEFENSE STANDARDS
MIL-STD-883 - Test Method Standard Microcircuits.
MIL-STD-1835 - Interface Standard Electronic Component Case Outlines.
DEPARTMENT OF DEFENSE HANDBOOKS
MIL-HDBK-103 - List of Standard Microcircuit Drawings.
MIL-HDBK-780 - Standard Microcircuit Drawings.
(Copies of these documents ar e available online at https://assist.daps.dla.mil/quicksearch/ or from the Standardization
Document Order Desk, 700 Robbins Avenue , Building 4D, Philadelphia, PA 19111-5094.)
2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text
of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a
specific exemption has been obtained.
3. REQUIREMENTS
3.1 Item requirements. The individual item requ irements for device classes Q and V shall be in accordance with
MIL-PRF-38535 and as specif ied herein or as modified in the device manufacturer's Quality Management (QM) plan. The
modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for
device class M shall be in acc ordance with MIL-PRF-38535, appendix A for non-JAN class level B dev ices and as specified
herein.
3.2 Design, construction, and physical dimensions. The design, construction, and ph ysical dimensions shall be as specified
in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M.
3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein.
3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1.
3.2.3 Truth table. The truth table shall be as specified on figure 2.
3.2.4 Logic diagram. The logic diagram shall be as specified on figur e 3.
3.2.5 Ground bounce load circ uit and waveforms. The ground bounce load circuit and waveforms shall be as specified on
figure 4.
3.2.6 Switching waveforms and test circuit. The switching waveforms and test circuit shall be as specified on figure 5.
3.3 Electrical performance characteristics and postirradiation par ameter limits. Unless otherwise specified herein, the
electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full
case operating temperature rang e.
3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical
tests for each subgroup are defined in table I.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-92202
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
D SHEET 5
DSCC FORM 2234
APR 97
3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be
marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer
has the option of not marking the "5962-" on the devic e. For RHA product using this option, the RHA designator shall still be
marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be
in accordance with MIL-PRF - 38535, appendix A.
3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in
MIL-PRF-38535. The compliance mark for device class M shall be a "C" as requ ired in MIL-PRF-38535, appendix A.
3.6 Certificate of compliance. For device classes Q and V, a certificate of complianc e shall be required from a QML-38535
listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of
compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103
(see 6.6.2 herein). The certificate of complia nce submitted to DSCC-VA prior to listing as an approved source of supply for this
drawing shall affirm that the manufacturer's product meets, for device classes Q and V, the requirements of MIL-PRF-3853 5 and
herein or for device class M, the requirement s of MIL-PRF-38535, appendix A and herein.
3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for
device class M in MIL-PRF-38 535, appendix A shall be provided with each lot of microcircuits delivere d to this drawing.
3.8 Notification of change for device class M. For device class M, notification to DSC C-VA of change of product
see 6.2 herein) involving d evices acquired to this drawing is required for any change that affects this drawing.
3.9 Verification and review for device class M. For device class M, DSCC, DSCC's agent, and the acqu iring activity retain the
option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made
available onshore at the optio n of the reviewer.
3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in
microcircuit group number 39 (see MIL-PRF-38535, appendix A).
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-92202
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
D SHEET 6
DSCC FORM 2234
APR 97
TABLE I. Electrical performance characteristi c s.
Test and
MIL-STD-883
test method 1/
Symbol Test conditions 2/
-55C TC +125C
+4.5 V VCC +5.5 V
unless otherwise specified
Device
type VCC Group A
subgroups Limits 3/ Unit
Min Max
High level output
voltage
3006
VOH1
4/ For all inputs affecting
output under test
VIH = 2.0 V
VIL = 0.8 V
For all other inputs
VIN = VCC or GND
IOH = -300 A All 4.5 V 1, 2, 3 2.7 VCC-0.5 V
VOH2 I
OH = -12 mA 01, 03,
05 4.5 V 1, 2, 3 2.4 VCC-0.5
IOH = -6 mA 02, 04,
06 2.4 VCC-0.5
IOH = -12 mA 2.0 VCC-0.5
Low level output
voltage
3007
VOL1
4/ I
OL = +300 A All 4.5 V 1, 2, 3 0.20 V
VOL2 I
OL = +32 mA 4.5 V 1, 2, 3 0.50
Negative input
clamp voltage
3022
VIC- For input under test, IIN = -15 mA 01, 03,
05 4.5 V 1, 2, 3 -1.3 V
For input under test, IIN = -18 mA 02, 04,
06 -1.2
Input current
high
3010
IIH For input under test, VIN = VCC
For all other inputs, VIN = VCC or GND All 5.5 V 1, 2 +1.0 A
3 +5.0
Input current low
3009 IIL For input under test, VIN = GND
For all other inputs, VIN = VCC or GND All 5.5 V 1, 2 -1.0 A
3 -5.0
Output short
circuit current
3011
IOS
5/ For all inputs, VIN = VCC or GND
VOUT = GND All 5.5 V 1, 2, 3 -60 -225 mA
Dynamic power
supply current ICCD
4/ 6/
Outputs open 01, 03,
05 5.5 V 4, 5, 6 0.25 mA/
MHz•Bit
02, 04,
06 0.30
Quiescent supply
current delta,
TTL input level
3005
ICC
7/ For input under test
VIN = 3.4 V
For all other inputs
VIN = VCC or GND
All 5.5 V 1, 2, 3 2.0 mA
Quiescent supply
current,
outputs high
3005
ICCH a = b = GND
For all other inputs
VIN = VCC or GND
All 5.5 V 1, 2, 3 1.5 mA
Quiescent supply
current,
outputs low
3005
ICCL All 5.5 V 1, 2, 3 1.5 mA
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-92202
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
D SHEET 7
DSCC FORM 2234
APR 97
TABLE I. Electrical performance characteristi c s - Continued.
Test and
MIL-STD-883
test method 1/
Symbol Test conditions 2/
-55C TC +125C
+4.5 V VCC +5.5 V
unless otherwise specified
Device
type VCC Group A
subgroups Limits 3/ Unit
Min Max
Total supply
current ICCT1
8/ 9/ Outputs open
One output toggling
fo = 10 MHz
50% duty cycle
For nonswitching input,
VIN = VCC or GND
For switching
inputs,
VIN = VCC or
GND
01, 03,
05 5.5 V 4, 5, 6 4.0 mA
02, 04,
06 4.5
For switching
inputs,
VIN = 3.4 V
or GND
01, 03,
05 5.5 V 4, 5, 6 5.0
02, 04,
06 5.5
ICCT2
4/ 8/ 9/ Outputs open
One output toggling
on each decoder
fo = 10 MHz
50% duty cycle
For nonswitching input,
VIN = VCC or GND
For switching
inputs,
VIN = VCC
or GND
01, 03,
05 5.5 V 4, 5, 6 6.5
02, 04,
06 7.5
For switching
inputs,
VIN = 3.4 V
or GND
01, 03,
05 5.5 V 4, 5, 6 8.5
02, 04,
06 9.5
Input capacitance
3012 CIN
10/ TC = +25C
See 4.4.1b All GND 4 10 pF
Output capacitance
3012 COUT
10/ All GND 4 12 pF
Low level ground
bounce noise VOLP
10/ 11/ VIH = 3.0 V, VIL = 0.0 V
TA = +25C
See figure 4
01, 03,
05 5.0 V 4 mV
02, 04,
06 1500
VOLV
10/ 11/ 01, 03,
05 5.0 V 4
02, 04,
06 -1700
High level VCC
bounce noise VOHP
10/ 11/ 01, 03,
05 5.0 V 4 mV
02, 04,
06 700
VOHV
10/ 11/ 01, 03,
05 5.0 V 4
02, 04,
06 -650
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-92202
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
D SHEET 8
DSCC FORM 2234
APR 97
TABLE I. Electrical performance characteristi c s - Continued.
Test and
MIL-STD-883
test method 1/
Symbol Test conditions 2/
-55C TC +125C
+4.5 V VCC +5.5 V
unless otherwise specified
Device
type VCC Group A
subgroups Limits 3/ Unit
Min Max
Functional test
3014 12/ VIH = 2.0 V, VIL = 0.8 V
Verify output VO
See 4.4.1c
All 4.5 V 7, 8 L H
5.5 V 7, 8 L H
Propagation delay
time, Anm to km
3003
tPLH1,
tPHL1
13/
CL = 50 pF minimum
RL = 500
See figure 5
01, 02 4.5 V 9, 10, 11 1.5 12.0 ns
03, 04 9, 10, 11 1.5 7.8
05, 06 9, 10, 11 1.5 6.2
Propagation delay
time, m to km
3003
tPLH2,
tPHL2
13/
01, 02 4.5 V 9, 10, 11 1.5 9.0 ns
03, 04 9, 10, 11 1.5 7.2
05, 06 9, 10, 11 1.5 5.8
1/ For tests not listed in the referenced MIL-STD-883 (e.g. ICC), utilize the general test procedure of 883 under the conditions
listed herein.
2/ Each input/output, as applicable, shall be tested at the specified temperature, for the specified limits, to the tests in table I
herein. Output terminals not designated sha ll be high level logic, low level logic, or open, except for all ICC and ICC tests,
the output terminals shall be open. When performing these tests, the current meter shall be placed in the circuit such that
all current flows through the meter.
3/ For negative and positive voltage and current values, the si gn designates the potential difference in reference to GND and
the direction of current flow, respectively; and the absolute value of the magnitude, not the sign, is relative to the minimum
and maximum limits, as applicabl e, listed herein. All devices shall meet or exceed the limi t s specified in table I at
4.5 V VCC 5.5 V.
4/ This parameter is guaranteed, if not tested, to the limits specified in table I herein.
5/ Not more than one output should be shorted at a time. The duration of the short circuit test should not exceed one second.
6/ ICCD may be verified by the following equation:
ICCT - ICC - DHNTICC
I
CCD = ─────────────────────
fCP/2 + foNo
where ICCT, ICC (ICCL or ICCH in table I), and ICC shall be the measured values of these parameters, for the devic e under test,
when tested as described in table I, herein. The values for DH, NT, fCP, fo, and No shall be as listed in the test conditions
column for ICCT in table I, herein.
7/ This test may be performed either one input at a time (preferred method) or with all input pins simultaneously at
VIN = VCC - 2.1 V (alternate method). Classes Q and V shall use the preferred method. When the test is performed using
the alternate test method, the maximum limit is equal to the number of inputs at a high TTL input level times 2.0 mA; and the
preferred method and limits are guaranteed.
8/ For ICC test in an ATE environment, the effect of parasitic output capacitive loading fro m the test environment must be taken
into account, as its effect is not intended to be included in the test results. The impact must be characterized and
appropriate offset factors must be applied to the test result.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-92202
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
D SHEET 9
DSCC FORM 2234
APR 97
TABLE I. Electrical performance characteristi c s - Continued.
9/ ICCT is calculated as follows:
I
CCT = ICC + DHNTICC + ICCD(fCP/2 + foNo)
where:
I
CC = Quiescent supply curren t (any ICCL or ICCH)
D
H = Duty cycle for TTL inputs at 3.4 V
N
T = Number of TTL inputs at 3.4 V
ICC = Quiescent supply current delta, TTL inputs at 3.4 V
I
CCD = Dynamic power supply current caused by an input transition pair (HLH or LHL)
f
CP = Clock frequency for registered devices (fCP = 0 for nonregistered devices)
f
o = Output frequency
N
o = Number of outputs at fo
10/ This test is required only for group A testing; see 4.4.1 h erei n.
11/ This test is for qualification only. Ground and VCC bounce t ests are performed on a non-switching (quiescent) output and
are used to measure the magnitude of induced noise caused by other simultan eously switching outputs. The test is
performed on a low noise bench test fixture. For the device under test, all outputs shall be loaded with 500 of load
resistance and a minimum of 50 pF of loa d capacitance (see figure 4). Only chip capacitors and res isto r s shall be used.
The output load components shall be located as close as possible to the device outputs. It is suggested, that whenever
possible, this distance be kept to less than 0.25 inches. Decoupling capacitors shal l be placed in parallel from VCC to
ground. The values of these decoupling capacitors shall be determined b y the device manufacturer. The low and high level
ground and VCC bounce noise is measure d at the quiet output using a 1 GHz minimum bandwidth oscilloscop e with a 50
input impedance.
The device in puts shall be conditioned such that all out puts are at a high nominal VOH level. The device inputs shall then be
conditioned such that they switch simultaneously and the output under test remains at VOH as all other outputs possible are
switched from VOH to VOL. VOHV and VOHP are then measured from the nominal VOH level to the largest negative and p ositive
peaks, respectively (see figure 4). This is then repeated with the same outputs not under test switching from VOL to VOH.
The device in puts shall be conditioned such that all out puts are at a low nominal VOL level. The device inputs shall then be
conditioned such that they switch simultaneously and the output under test remains at VOL as all other outputs possible are
switched from VOL to VOH. VOLP and VOLV are then measured from the nominal VOL level to the largest positive and negative
peaks, respectively (see figure 4). This is then repeated with the same outputs not under test switching from VOH to VOL.
For device types 01, 03, and 05, the limits for VCC and ground bounce tests were never supplied. Device types 01, 03, and
05 with IOH = -12 mA were never made available from an approved source of supply.
12/ Tests shall be performed in sequence, attributes data only. Functional tests shall include the truth table and other logic
patterns used for fault detection. The test vectors used to verify the truth table shall, at a minimum, test all functions of each
input and output. All possible input to output logic patterns per function shall be guaranteed, if not tested, to the truth table
in figure 2 herein. Functiona l tests shall be performed in sequence as approved by the qualifying activity on qualified
devices. For outputs, L < 1.5 V, H 1.5 V.
13/ AC limits at VCC = 5.5 V are equal to the limits at VCC = 4.5 V and guaranteed by testing at VCC = 4.5 V. Minimum
propagation delay time limits for VCC = 4.5 V and 5.5 V are guaranteed, if not tested, to the limits specified in table I, herein.
For propagation delay tests, all paths must be tested.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
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DEFENSE SUPPLY CENTER COLUMBUS
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D SHEET 10
DSCC FORM 2234
APR 97
Device types All
Case outlines E, F 2
Terminal
number Terminal symbol
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Ea
A0a
A1a
O0a
O1a
O2a
O3a
GND
O3b
O2b
O1b
O0b
A1b
A0b
Eb
VCC
---
---
---
---
NC
Ea
A0a
A1a
O0a
NC
O1a
O2a
O3a
GND
NC
O3b
O2b
O1b
O0b
NC
A1b
A0b
Eb
VCC
Terminal descriptions
Terminal symbol Description
Anm (n = 1 to 2, m = a and b) Address inputs
Okm (k = 0 to 3, m = a and b) Outputs (active low)
Em (m = a and b) Enable inputs (active low)
FIGURE 1. Terminal connections.
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D SHEET 11
DSCC FORM 2234
APR 97
Inputs Outputs
Em A0m A1m
O0m O1m O2m O3m
H
L
L
L
L
X
L
H
L
H
X
L
L
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
L
H = High voltage level
L = Low voltage level
X = Irrelevant
m = a or b
FIGURE 2. Truth table.
FIGURE 3. Block diagram.
STANDARD
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DSCC FORM 2234
APR 97
NOTES:
1. CL includes a 47 pF chip capacitor (-0 percen t, +20 percent) and at least 3 pF of equivalent capacitance from the test jig
and probe.
2. RL = 450 1 percent, chip resistor in series with a 50 termination. For monitored outputs, the 50 termination shall
be the 50 characteristic impeda nce of the coaxial connector to the oscilloscope.
3. Input signal to the device unde r test:
a. VIN = 0.0 V to 3.0 V; duty cycle = 50 percent; fIN 1 MHz.
b. tr, tf = 3.0 ns 1.0 ns. For input signal generators incapable of maintaining these values of tr and tf, the 3.0 ns limit
may be increased up to 10 ns, as needed, m aintaining the 1.0 ns tolerance and guaranteeing the results at 3.0 ns
1.0 ns; skew between any two switching inputs signals (tsk) 250 ps.
FIGURE 4. Ground bounce waveforms and test circuit.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-92202
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
D SHEET 13
DSCC FORM 2234
APR 97
NOTES:
1. CL = 50 pF (includes test jig and probe capacitance).
2. RL = 500 or equivalent, RT = 50 or equivalent
3. Input signal from pulse generator: VIN = 0.0 V to 3.0 V; PRR 10 MHz; duty cycle = 50 percent; tr 2.5 ns; tf 2.5 ns; tr
and tf shall be measured from 0.3 V to 2.7V and from 2.7 V to 0.3 V, respectively.
4. Timing parameters shall be tested at a minimum input frequenc y of 1 MHz.
5. The outputs are measured one at a time with one transition per measurement.
FIGURE 5. Switching waveforms and test circuit.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-92202
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
D SHEET 14
DSCC FORM 2234
APR 97
4. VERIFICATION
4.1 Sampling and i nspection. For device classes Q and V, sampling a nd inspection procedures shall be in accordance with
MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan
shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures sh all be in
accordance with MIL-PRF-38535, appendix A.
4.2 Screening. F or device cla sses Q and V, screening shall be in accorda nce with MIL-PRF-38535, and shall be condu c ted
on all devices prior to qualific ation and technology conformance inspection. For device class M, screening shal l be in
accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspectio n.
4.2.1 Additional criteria for device class M.
a. Burn-in test, method 1015 of MIL-STD-883.
(1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision
level control and shall be ma de available to the preparing or acquiring activity upon request. The test circuit shall
specify the inputs, outputs, biases, and power dissipation, as applicabl e, in accordanc e wit h the inte nt specified in
method 1015.
(2) TA = +125C, minimum.
b. Interim and final electrical test parameters shall be as specified in table II herein.
4.2.2 Additional criteria for device classes Q and V.
a. The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the
device manufacturer's QM plan in accordance with MIL-PRF-38535. T he burn-in test circuit shall be maintained unde r
document revision level contro l of the device manufacturer's Technolog y Review Board (TRB) in accorda nce with
MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall
specify the inputs, outputs, biases, and power dissipation, as applicabl e, in accordanc e wit h the inte nt specified in
method 1015 of MIL-STD-883.
b. Interim and final electrical test parameters shall be as specified in table II herein.
c. Additional screening for device class V beyond the requirements of device class Q shall be as specified in
MIL-PRF-38535, appendix B.
4.3 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be in
accordance with MIL-PRF-38535. Inspectio ns to be performed shall be those specified in MIL-PRF-38 535 and herein for groups
A, B, C, D, and E inspections (see 4.4.1 through 4.4.4).
4.4 Conformance inspection. Technology conformance inspectio n for cla sses Q and V shall be in accordance with
MIL-PRF-38535 including groups A, B, C, D, and E inspections and as specified herein. Quality conformance inspection for
device class M shall be in acc ordance with MIL-PRF-38535, appendix A and as specified herein. Inspections to be performed
for device class M shall be those specified in method 5005 of MIL-STD-883 and herein for groups A, B, C, D, and E inspections
(see 4.4.1 through 4.4.4).
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-92202
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
D SHEET 15
DSCC FORM 2234
APR 97
4.4.1 Group A inspection.
a. Tests shall be as specified in table II herein.
b. CIN, and COUT shall be measured on ly for initial qualification and after process or design changes which may affect
capacitance. CIN and shall be measured bet ween the designated terminal and GND at a frequency of 1 MHz. For CIN,
and COUT, test all applicable pins on five devices with zero failures.
For CIN and COUT, a device manufacturer may qualify devices by functional groups. A specific functional group shall
be composed of function types that by design will yiel d the same capacitance values when tested in accordance with
table I herein. The device manufacturer shall set a functional group limit for the CIN and COUT tests. The device
manufacturer may then test one device function from a functional group to the limits and conditions specified herein.
All other device functions in that particular functional group shall be g uaranteed, if not tested, to the limits and
conditions specified in table I herein. The device manufacturer shall submit to DSCC the device functions listed in
each functional group and the test results for each device tested.
c. For device class M, subgroups 7 and 8 tests shall be sufficient to verify the truth table in figure 2 herein. T he test
vectors used to verify the truth table shall, at a minimum, test all functions of each input and output. All possible input
to output logic patterns per function shall be guaranteed, if not tested, to the truth table in figure 2, herein. For device
classes Q and V, subgroups 7 and 8 shall i nclude verifying the functionality of the device.
d. Ground and VCC bounce tests are required for all device classes. These tests shall be performed only for initial
qualification, after process or design changes which may affect the performance of the device, and any changes to the
test fixture. VOLP, VOLV, VOHP, and VOHV shall be meas ured for the worst case outputs of the device. All other outputs
shall be guaranteed, if not tested, to the limits established f or the worst case outputs. The worst case outputs tested
are to be determined by the manufacturer. T est 5 devices assembled i n the worst case package type supplie d to this
document. All other package t ypes shall be guaranteed, if not tested, to the limits established for the worst case
package. The 5 devices to be tested shall be the worst case device type supplied to this drawing. All other device
types shall be guaranteed, if not tested, to the limits established for the worst case device type. The package type
and device type to be tested shall be d etermined by the manufacturer. The device manufacturer will submit to
DSCC-VA data that shall include all measured peak values for each device tested and detailed oscilloscope plots for
each VOLP, VOLV, VOHP, and VOHV from one sample part per function. The plot shall contain the waveforms of both a
switching output and the output under test.
Each device manufacturer shall test product on the fixtures they currently use. When a new fixture is us ed, the device
manufacturer shall inform DSCC-VA of this change and test the 5 devices on both the new and old test fixtures. The
device manufacturer shal l then submit to DSCC-VA data from testing on both fixtures, that shall inclu de all measured
peak values for each device tested and detailed oscilloscope plots for each VOLP, VOLV, VOHP, and VOHV from one
sample part per function. The plot shall contain the waveforms of both a switching output and the o utput under test.
For VOHP, VOHV, VOLP, and VOLV, a device manufacturer may qualify devices by functional groups. A specific function al
group shall be composed of function types that by design will yield the same test values when tested in accordance
with table I, herein. The device manufacturer shall set a fun ctional group limit for the VOHP, VOHV, VOLP, and VOLV tests.
The device manufacturer may then test one device function from a functional group, to th e limits and conditions
specified herein. All other device functions in that particular functional gro up shall be guaranteed, if not tested, to the
limits and conditions specified in table I, here in. T he device manufacturers shall submit to DSCC-VA the device
functions listed in each functional group and test results, along with the oscilloscop e plots, for each device tested.
4.4.2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table II herei n.
4.4.2.1 Additional criteria for device class M. Steady-state life test conditions, method 1005 of MIL-STD-883:
a. Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level
control and shall be made available to the preparing or acquiring activity upon re quest. The test circuit shall specify the
inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of
MIL-STD-883.
b. TA = +125C, minimum.
c. Test duration: 1,000 hours, except as permitted b y method 1005 of MIL-STD-883.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-92202
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
D SHEET 16
DSCC FORM 2234
APR 97
TABLE II. Electrical test requirements.
Test requirements Subgroups
(in accordance with
MIL-STD-883,
method 5005, table I)
Subgroups
(in accordance with
MIL-PRF-38535, table III)
Device
class M Device
class Q Device
class V
Interim electrical
parameters (see 4.2) - - - 1 1
Final electrical
parameters (see 4.2) 1/ 1, 2, 3, 4, 5, 6, 7,
8, 9, 10, 11 1/1, 2, 3, 4, 5, 6,
7, 8, 9, 10, 11 2/ 1, 2, 3, 4, 5,
6, 7, 8, 9, 10, 11
Group A test
requirements (see 4.4) 1, 2, 3, 4, 5, 6, 7, 8,
9, 10, 11 1, 2, 3, 4, 5, 6, 7,
8, 9, 10, 11 1, 2, 3, 4, 5, 6, 7,
8, 9, 10, 11
Group C end-point electrical
parameters (see 4.4) 1, 2, 3, 4, 5, 6 1, 2, 3, 4, 5, 6 1, 2, 3, 4, 5, 6, 7,
8, 9, 10, 11
Group D end-point electrical
parameters (see 4.4) 1, 2, 3 1, 2, 3 1, 2, 3
Group E end-point electrical
parameters (see 4.4) 1, 4, 7, 9 1, 4, 7, 9 1, 4, 7, 9
1/ PDA applies to subgroup 1.
2/ PDA applies to subgroups 1 and 7.
4.4.2.2 Additional criteria for device classes Q and V. The steady-state lif e te st duration, test condition and test temperature,
or approved alternativ es shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The
test circuit shall be maintained under docum ent revision level control by the device manufacturer's TRB in accordance with
MIL-PRF-38535 and shall be made available to the acquiring or preparing activit y upon request. The test circuit shall specify the
inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of
MIL-STD-883.
4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table II herei n.
4.4.4 Group E inspection. Group E inspection is required onl y for parts intended to be marked as radiation h ard ness assured
(see 3.5 herein).
a. End-point electrical parameters shall be as specified in table II herein.
b. For device classes Q and V, the devices or test vehicle shall be subject ed to radiation hardness ass ured tests as
specified in MIL-PRF-38535 for the RHA level being tested. For device cla ss M, the devices shall be subjected to
radiation hardness assured tests as specified in MIL-PRF - 38535, appendix A for the RHA level being tested. All device
classes must meet the postirradiation end-point electrical parameter limits as defined in table I at TA = +25C 5C,
after exposure, to the subgrou ps specified in table II herein.
5. PACKAGING
5.1 Packaging requirements. The requir eme nts for packaging shall be in accordance with MIL-PRF-38535 for device classes
Q and V or MIL-PRF-38535, appendix A for device class M.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-92202
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
D SHEET 17
DSCC FORM 2234
APR 97
6. NOTES
6.1 Intended use. Microcircuits conforming t o this drawing are intended for use for Government microcircuit application s
(original equipment), desig n applications, and logistics purposes.
6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor-
prepared specification or drawing.
6.1.2 Substitutability. Device class Q devices will replace device class M devices.
6.2 Configuration control of SMD's. All proposed chan ges to existing SMD's will be coordinated with the users of record for
the individual documents. This coordination will be accomplished usin g DD Form 1692, Engineering Change Proposal.
6.3 Record of users. Military and industrial users should inform Defense Supply Center Columbus (DSC C) when a system
application requires configuration control and which SMD's are applicable to that system. DSCC will maintain a record of users
and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering
microelectronic devices (FSC 5962) should contact DSCC-VA, telephone (614) 692-0544.
6.4 Comments. Comments on this drawing should be directed to DSCC-VA, Columbus, Ohio 43218-3990, or telephone
(614) 692-0547.
6.5 Abbreviations, symbols, and definitions. The abbreviations, s ymbo ls, and definitions used herein are defined in
MIL-PRF-38535 and MIL-HDBK-133 1.
6.6 Sources of supply.
6.6.1 Sources of supply for device classes Q and V. Sources of suppl y for device classes Q and V are listed in QML-38535.
The vendors listed in QML-38535 h ave su bmitted a certificate of compliance (see 3.6 her ein) to DSCC-VA and have agreed to
this drawing.
6.6.2 Approved sources of supply for device class M. Approved sources of supply for cla ss M are listed in MIL-HDBK-103.
The vendors listed in MIL-HDBK-103 h ave agreed to this drawing and a certificate of compliance (see 3.6 herein) has been
submitted to and accepted by DSCC-VA.
STANDARD MICROCIRCUIT DRAWING BULLETIN
DATE: 10-01-19
Approved sources of suppl y for SMD 5962-92202 are listed below for immediate acquisition information only and
shall be added to MIL-HDBK-103 an d QML-38535 during the ne xt revision. MIL-HDBK-103 and QML-38 535 will be
revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a
certificate of compliance has been subm itted to and accepted by DSCC-VA. This information b ulletin is superseded
by the next dated revision of MIL-HDBK-103 and QML-38535. DSCC maintains a n on line database of all current
sources of supply at http://www.dscc.dla.mil/Programs/Smcr/.
Standard
microcircuit drawing
PIN 1/
Vendor
CAGE
number
Vendor
similar
PIN 2/
5962-9220201M2A 3/
5962-9220201MEA 3/
5962-9220202M2A 0C7V7 IDT54FCT139TLB
5962-9220202MEA 0C7V7 IDT54FCT139TDB
5962-9220202MFA 0C7V7 IDT54FCT139TEB
5962-9220203MFA 3/
5962-9220203M2A 3/
5962-9220203MEA 3/
5962-9220204M2A 0C7V7 IDT54FCT139ATLB
5962-9220204MEA 0C7V7 IDT54FCT139ATDB
5962-9220204MFA 0C7V7 IDT54FCT139ATEB
5962-9220205MFA 3/
5962-9220205M2A 3/
5962-9220205MEA 3/
5962-9220206M2A 0C7V7 IDT54FCT139CTLB
5962-9220206MEA 0C7V7 IDT54FCT139CTDB
5962-9220206MFA 0C7V7 IDT54FCT139CTEB
1/ The lead finish shown for each PIN representing
a hermetic package is the most readily available
from the manufacturer listed for that part. If the
desired lead finish is not listed contact the vendor
to determine its availability.
2/ Caution. Do not use this number for item
acquisition. Items acquired to this number m ay not
satisfy the performance requirements of this drawing.
3/ Not available from an approved source of supply.
Vendor CAGE Vendor name
number and address
0C7V7 QP Semiconductor
2945 Oakmead Village Court
Santa Clara, CA 95051
The information contained herein is disseminated for convenience only and the
Government assumes no liability whatsoeve r for any inaccuracies in the
information bulletin.
