SEMICONDUCTOR
1
Features
• This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
• Exceeds 2kV ESD Protection MIL-STD-883, Method 3015
• Meets JEDEC Standard No. 20
• SCR - Latch-Up-Resistant CMOS Process and Circuit
Design
• Speed of Bipolar FAST/A/S with Significantly Reduced
Power Consumption
• Functionally and Pin-Compatible with Industry 54
Bipolar Types in the FAST, AS and S Series
• Balanced Propagation Delays
• Military Operating Temperature Range
- Ceramic (CERDIP) 54 Series: . . . . . . . . -55 to 125oC
•±24mA Output Drive Current, Drives 75Ω Lines with-
out Need for Terminations
• Fan Out (Over Temperature)
- ACL Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2400
- FAST Loads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
- AS Loads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
• Operation Voltage . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V
Functional Diagram
Description
The CD54ACT623F3A is an octal bus transceiver that uti-
lizes Harris Advanced CMOS Logic technology. It is a non-
inverting three-state bidirectional transceiver-buffer that
allows for two-way transmission from “A” bus to “B” bus or
“B” bus to “A” bus depending on the logic levels of the Output
Enable (OEAB, OEBA) inputs.
The dual Output Enable provision gives these devices the
capability to store data by simultaneously enabling OEAB
and OEBA. Each output reinforces its input under these con-
ditions, and when all other data sources to the bus lines are
at high-impedance, both sets of bus lines will remain in their
last states.
Pinout
18
17
16
15
13
11
12
14
2B0
B1
B2
B3
B4
B5
B6
B7
OEBA
OEAB 1
19
4
9
3
5
6
7
8
A0
A1
A2
A3
A4
A5
A6
A7
Ordering Information
PART NUMBER TEMP.
RANGE (oC) PACKAGE PKG.
NO.
CD54ACT623F3A -55 to 125 20 Ld CERDIP F20.3
NOTE:
1. Wafer and die for this part number is available which meets all elec-
trical specifications. Please contact your local sales office or Harris
customer service for ordering information.
11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1
OEAB
A0
A1
A2
A3
A4
A6
A5
A7
GND
VCC
B0
B1
B2
OEBA
B3
B4
B5
B6
B7
July 1998
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1998
CD54ACT623F3A
Octal Bus Transceiver
Three-State, Non-Inverting
File Number 3917.1
2
Absolute Maximum Ratings Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA
DC VCC or Ground Current, ICC or IGND (Note 2) . . . . . . . . .±100mA
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC (Note 3). . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Thermal Resistance (Typical, Note 4) θJA (oC/W) θJC (oC/W)
CERDIP Package . . . . . . . . . . . . . . . . 80 22
Maximum Junction Temperature (Hermetic P ac kage or Die) . . . 175oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
2. For up to 4 outputs per device, add ±25mA for each additional output.
3. Unless otherwise specified, all voltages are referenced to ground.
4. θJA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
PARAMETER SYMBOL
TEST
CONDITIONS VCC
(V)
25oC -55oC TO 125oC
UNITSVI(V) IO(mA) MIN MAX MIN MAX
High Level Input Voltage VIH - - 4.5 to 5.5 2
(Note 5) -2
(Note 5) -V
Low Level Input Voltage VIL - - 4.5 to 5.5 - 0.8
(Note 5) - 0.8
(Note 5) V
High Level Output Voltage VOH VIH or VIL -0.05 4.5 4.4 - 4.4 - V
-24 4.5 3.94
(Note 5) - 3.7
(Note 5) -V
-50
(Note 6, 7) 5.5 - - 3.85 - V
Low Level Output Voltage VOL VIH or VIL 0.05 4.5 - 0.1 - 0.1 V
24 4.5 - 0.36
(Note 5) - 0.5
(Note 5) V
50
(Note 6, 7) 5.5 - - - 1.65 V
Input Leakage Current IIVCC or
GND - 5.5 - ±0.1
(Note 5) -±1
(Note 5) µA
Three-State or Leakage
Current IOZ VIH or VIL
VO = VCC
or GND
- 5.5 - ±0.5
(Note 5) -±10
(Note 5) µA
Quiescent Device Current ICC VCC or
GND 0 5.5 - 8
(Note 5) - 160
(Note 5) µA
AdditionalSupplyCurrentper
Input Pin TTL Inputs High
1 Unit Load
∆ICC VCC
-2.1 - 4.5 to 5.5 - 2.4 - 3 mA
NOTES:
5. Tested 100%.
6. Test one output at a time for a 1-second maximum duration. Measurement is made by forcing current and measuring voltage to minimize
power dissipation.
7. Test verifies a minimum transmission-line-drive capability of 75Ω for 54ACT Series.
CD54ACT623F3A
3
ACT Input Load Table
INPUT UNIT LOAD
An, Bn 0.83
OEBA 0.64
OEAB 0.15
NOTE: Unit load is ∆ICC limit specified in DC Electrical Specifications
Table, e .g., 2.4mA max at 25oC.
Switching Specifications Input tr, tf = 3ns, CL= 50pF (Worst Case)
PARAMETER SYMBOL VCC (V)
-55oC TO 125oC
UNITSMIN TYP MAX
Propagation Delay, Data to Output tPLH, tPHL 5 (Note 10) 1.8 - 10.6 (Note 8 ns
Propagation Delay, Output Disable to Output tPLZ, tPHZ 5 2.5 - 14.4 (Note 8) ns
Propagation Delay, Output Enable to Output tPZL, tPZH 5 2.5 - 14.4 (Note 8) ns
Minimum (Valley) VOH During Switching of Other Outputs
(Output Under Test Not Switching) VOHV
See Figure 1 5 - 4 at 25oC- V
Maximum (Peak) VOL During Switching of Other Outputs
(Output Under Test Not Switching) VOLP
See Figure 1 5 - 1 at 25oC- V
Three-State Output Capacitance CO- - - 15 pF
Input Capacitance CI- - - 10 pF
Power Dissipation Capacitance CPD (Note 11) - - 79 - pF
NOTES:
8. Limits tested 100%.
9. 3.3V Min = 3.6V, Max = 3V.
10. 5V Min = 5.5V, Max = 4.5V
11. CPD is used to determine the dynamic power consumption per gate.
PD = VCC2 fi(CPD + CL) + VCC ∆ICC where fi = input frequency, CL = output load capacitance, VCC = supply voltage.
Burn-In Test Circuit Connections (Use DC II for F3A Burn-In and AC for Life Test)
DC
DC BURN-IN I DC BURN-IN II
OPEN GROUND VCC (6V) OPEN GROUND VCC (6V)
CD54ACT623 2-9 1, 10-19 20 11-18 10 1-9, 19, 20
AC OPEN GROUND 1/2 VCC (3V) VCC (6V)
OSCILLATOR
50kHz 25kHz
CD54ACT623 - 10 11-18 19, 20 2-9 1
NOTE: Each pin except VCC and Gnd will have a resistor of 2kΩ-47kΩ.
DUT
OUTPUT RL
OUTPUT
LOAD
500Ω
CL
50pF
FIGURE 1. PROPAGATION DELAY TIMES
CD54ACT
Input Level 3V
Input Switching Voltage, VS1.5V
Output Switching Voltage, VS0.5 VCC
CD54ACT623F3A
