74AUP2G14 Low-power dual Schmitt trigger inverter Rev. 6 -- 17 September 2015 Product data sheet 1. General description The 74AUP2G14 provides two inverting buffers with Schmitt trigger action which accept standard input signals. They are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. The inputs switch at different points for positive and negative-going signals. The difference between the positive voltage VT+ and the negative voltage VT is defined as the input hysteresis voltage VH. 2. Features and benefits Wide supply voltage range from 0.8 V to 3.6 V High noise immunity ESD protection: HBM JESD22-A114F Class 3A exceeds 5000 V MM JESD22-A115-A exceeds 200 V CDM JESD22-C101E exceeds 1000 V Low static power consumption; ICC = 0.9 A (maximum) Latch-up performance exceeds 100 mA per JESD 78 Class II Inputs accept voltages up to 3.6 V Low noise overshoot and undershoot < 10 % of VCC IOFF circuitry provides partial Power-down mode operation Multiple package options Specified from 40 C to +85 C and 40 C to +125 C 3. Applications Wave and pulse shaper Astable multivibrator Monostable multivibrator 74AUP2G14 NXP Semiconductors Low-power dual Schmitt trigger inverter 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AUP2G14GW 40 C to +125 C SC-88 plastic surface-mounted package; 6 leads SOT363 74AUP2G14GM 40 C to +125 C XSON6 plastic extremely thin small outline package; no leads; SOT886 6 terminals; body 1 1.45 0.5 mm 74AUP2G14GF 40 C to +125 C XSON6 plastic extremely thin small outline package; no leads; SOT891 6 terminals; body 1 1 0.5 mm 74AUP2G14GN 40 C to +125 C XSON6 extremely thin small outline package; no leads; 6 terminals; body 0.9 1.0 0.35 mm SOT1115 74AUP2G14GS 40 C to +125 C XSON6 extremely thin small outline package; no leads; 6 terminals; body 1.0 1.0 0.35 mm SOT1202 74AUP2G14GX 40 C to +125 C X2SON6 plastic thermal extremely thin small outline package; no leads; 6 terminals; body 1 0.8 0.35 mm SOT1255 5. Marking Table 2. Marking Type number Marking code[1] 74AUP2G14GW pK 74AUP2G14GM pK 74AUP2G14GF pK 74AUP2G14GN pK 74AUP2G14GS pK 74AUP2G14GX pK [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 6. Functional diagram $ $ < < Logic symbol 74AUP2G14 Product data sheet $ < $ < PQE PQE PQE Fig 1. Fig 2. IEC logic symbol All information provided in this document is subject to legal disclaimers. Rev. 6 -- 17 September 2015 Fig 3. Logic diagram (c) NXP Semiconductors N.V. 2015. All rights reserved. 2 of 23 74AUP2G14 NXP Semiconductors Low-power dual Schmitt trigger inverter 7. Pinning information 7.1 Pinning $83* $83* $ *1' 9&& $ < < $ < *1' 9&& $ < DDG 7UDQVSDUHQWWRSYLHZ DDG Fig 4. Pin configuration SOT363 Fig 5. Pin configuration SOT886 $83* $83* $ $ < *1' 9&& $ < *1' < $ < DDG DDD 7UDQVSDUHQWWRSYLHZ Fig 6. 9&& 7UDQVSDUHQWWRSYLHZ Pin configuration SOT891, SOT1115 and SOT1202 Fig 7. Pin configuration SOT1255 (X2SON6) 7.2 Pin description Table 3. Pin description Symbol Pin Description 1A 1 data input GND 2 ground (0 V) 2A 3 data input 2Y 4 data output VCC 5 supply voltage 1Y 6 data output 74AUP2G14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 -- 17 September 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 3 of 23 74AUP2G14 NXP Semiconductors Low-power dual Schmitt trigger inverter 8. Functional description Table 4. Function table[1] Input Output nA nY L H H L [1] H = HIGH voltage level; L = LOW voltage level. 9. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current Conditions VI < 0 V [1] VO < 0 V VO output voltage Active mode and Power-down mode IO output current VO = 0 V to VCC [1] Min Max Unit 0.5 +4.6 V 50 - 0.5 +4.6 50 - 0.5 +4.6 V - 20 mA mA V mA ICC supply current - 50 mA IGND ground current 50 - mA Tstg storage temperature 65 +150 C - 250 mW total power dissipation Ptot Tamb = 40 C to +125 C [2] [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For SC-88 packages: above 87.5 C the value of Ptot derates linearly with 4.0 mW/K. For X2SON6 and XSON6 packages: above 118 C the value of Ptot derates linearly with 7.8 mW/K. 10. Recommended operating conditions Table 6. Recommended operating conditions Symbol Parameter VCC supply voltage VI input voltage VO output voltage Tamb Conditions Min Max Unit 0.8 3.6 V 0 3.6 V Active mode 0 VCC V Power-down mode; VCC = 0 V 0 3.6 V 40 +125 C ambient temperature 74AUP2G14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 -- 17 September 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 4 of 23 74AUP2G14 NXP Semiconductors Low-power dual Schmitt trigger inverter 11. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit IO = 20 A; VCC = 0.8 V to 3.6 V VCC 0.1 - - V IO = 1.1 mA; VCC = 1.1 V 0.75 VCC - - V IO = 1.7 mA; VCC = 1.4 V 1.11 - - V IO = 1.9 mA; VCC = 1.65 V 1.32 - - V IO = 2.3 mA; VCC = 2.3 V 2.05 - - V IO = 3.1 mA; VCC = 2.3 V 1.9 - - V IO = 2.7 mA; VCC = 3.0 V 2.72 - - V IO = 4.0 mA; VCC = 3.0 V 2.6 - - V IO = 20 A; VCC = 0.8 V to 3.6 V - - 0.1 V IO = 1.1 mA; VCC = 1.1 V - - IO = 1.7 mA; VCC = 1.4 V - - 0.31 V IO = 1.9 mA; VCC = 1.65 V - - 0.31 V IO = 2.3 mA; VCC = 2.3 V - - 0.31 V IO = 3.1 mA; VCC = 2.3 V - - 0.44 V IO = 2.7 mA; VCC = 3.0 V - - 0.31 V IO = 4.0 mA; VCC = 3.0 V - - 0.44 V Tamb = 25 C VOH VOL HIGH-level output voltage LOW-level output voltage VI = VT+ or VT VI = VT+ or VT 0.3 VCC V II input leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V - - 0.1 A IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V - - 0.2 A IOFF additional power-off leakage VI or VO = 0 V to 3.6 V; current VCC = 0 V to 0.2 V - - 0.2 A ICC supply current VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V - - 0.5 A ICC additional supply current VI = VCC 0.6 V; IO = 0 A; VCC = 3.3 V - - 40 A CI input capacitance VI = GND or VCC; VCC = 0 V to 3.6 V - 1.1 - pF CO output capacitance VO = GND; VCC = 0 V - 1.7 - pF IO = 20 A; VCC = 0.8 V to 3.6 V VCC 0.1 - - V IO = 1.1 mA; VCC = 1.1 V 0.7 VCC - - V Tamb = 40 C to +85 C VOH HIGH-level output voltage 74AUP2G14 Product data sheet VI = VT+ or VT IO = 1.7 mA; VCC = 1.4 V 1.03 - - V IO = 1.9 mA; VCC = 1.65 V 1.30 - - V IO = 2.3 mA; VCC = 2.3 V 1.97 - - V IO = 3.1 mA; VCC = 2.3 V 1.85 - - V IO = 2.7 mA; VCC = 3.0 V 2.67 - - V IO = 4.0 mA; VCC = 3.0 V 2.55 - - V All information provided in this document is subject to legal disclaimers. Rev. 6 -- 17 September 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 5 of 23 74AUP2G14 NXP Semiconductors Low-power dual Schmitt trigger inverter Table 7. Static characteristics ...continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions VOL VI = VT+ or VT LOW-level output voltage Min Typ Max Unit IO = 20 A; VCC = 0.8 V to 3.6 V - - 0.1 V 0.3 VCC V IO = 1.1 mA; VCC = 1.1 V - - IO = 1.7 mA; VCC = 1.4 V - - 0.37 V IO = 1.9 mA; VCC = 1.65 V - - 0.35 V IO = 2.3 mA; VCC = 2.3 V - - 0.33 V IO = 3.1 mA; VCC = 2.3 V - - 0.45 V IO = 2.7 mA; VCC = 3.0 V - - 0.33 V IO = 4.0 mA; VCC = 3.0 V - - 0.45 V - - 0.5 A II input leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V VI or VO = 0 V to 3.6 V; VCC = 0 V IOFF power-off leakage current - - 0.5 A IOFF additional power-off leakage VI or VO = 0 V to 3.6 V; current VCC = 0 V to 0.2 V - - 0.6 A ICC supply current VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V - - 0.9 A ICC additional supply current VI = VCC 0.6 V; IO = 0 A; VCC = 3.3 V - - 50 A IO = 20 A; VCC = 0.8 V to 3.6 V VCC 0.11 - - V IO = 1.1 mA; VCC = 1.1 V 0.6 VCC - - V IO = 1.7 mA; VCC = 1.4 V 0.93 - - V IO = 1.9 mA; VCC = 1.65 V 1.17 - - V IO = 2.3 mA; VCC = 2.3 V 1.77 - - V IO = 3.1 mA; VCC = 2.3 V 1.67 - - V IO = 2.7 mA; VCC = 3.0 V 2.40 - - V IO = 4.0 mA; VCC = 3.0 V 2.30 - - V IO = 20 A; VCC = 0.8 V to 3.6 V - - 0.11 V IO = 1.1 mA; VCC = 1.1 V - - IO = 1.7 mA; VCC = 1.4 V - - 0.41 V IO = 1.9 mA; VCC = 1.65 V - - 0.39 V IO = 2.3 mA; VCC = 2.3 V - - 0.36 V IO = 3.1 mA; VCC = 2.3 V - - 0.50 V IO = 2.7 mA; VCC = 3.0 V - - 0.36 V IO = 4.0 mA; VCC = 3.0 V - - 0.50 V Tamb = 40 C to +125 C VOH VOL HIGH-level output voltage LOW-level output voltage VI = VT+ or VT VI = VT+ or VT 0.33 VCC V II input leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V - - 0.75 A IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V - - 0.75 A 74AUP2G14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 -- 17 September 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 6 of 23 74AUP2G14 NXP Semiconductors Low-power dual Schmitt trigger inverter Table 7. Static characteristics ...continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit IOFF additional power-off leakage VI or VO = 0 V to 3.6 V; current VCC = 0 V to 0.2 V - - 0.75 A ICC supply current VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V - - 1.4 A ICC additional supply current VI = VCC 0.6 V; IO = 0 A; VCC = 3.3 V - - 75 A 12. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9. Symbol Parameter 25 C Conditions 40 C to +125 C Unit Min Typ[1] Max Min Max (85 C) Max (125 C) - 19.9 - - - - ns VCC = 1.1 V to 1.3 V 2.7 5.9 11.0 2.4 11.1 11.2 ns VCC = 1.4 V to 1.6 V 2.6 4.3 6.6 2.4 7.1 7.4 ns VCC = 1.65 V to 1.95 V 2.1 3.7 5.4 2.0 6.0 6.2 ns VCC = 2.3 V to 2.7 V 2.0 3.0 4.1 1.7 4.5 4.7 ns VCC = 3.0 V to 3.6 V 1.9 2.8 3.6 1.5 3.9 4.0 ns - 23.4 - - - - ns VCC = 1.1 V to 1.3 V 2.9 6.8 12.7 2.8 12.8 12.9 ns VCC = 1.4 V to 1.6 V 2.8 5.0 7.7 2.6 8.2 8.6 ns VCC = 1.65 V to 1.95 V 2.7 4.2 6.2 2.5 6.7 7.1 ns VCC = 2.3 V to 2.7 V 2.3 3.6 4.8 2.1 5.2 5.5 ns VCC = 3.0 V to 3.6 V 2.1 3.3 4.3 2.0 4.5 4.7 ns - 26.9 - - - - ns VCC = 1.1 V to 1.3 V 3.3 7.6 14.3 3.0 14.5 14.7 ns VCC = 1.4 V to 1.6 V 3.3 5.5 8.6 2.9 9.4 9.8 ns VCC = 1.65 V to 1.95 V 2.8 4.7 7.0 2.8 7.7 8.1 ns VCC = 2.3 V to 2.7 V 2.7 4.0 5.5 2.4 5.9 6.2 ns VCC = 3.0 V to 3.6 V 2.6 3.8 4.8 2.2 5.2 5.4 ns CL = 5 pF tpd propagation delay nA to nY; see Figure 8 [2] VCC = 0.8 V CL = 10 pF tpd propagation delay nA to nY; see Figure 8 [2] VCC = 0.8 V CL = 15 pF tpd propagation delay nA to nY; see Figure 8 VCC = 0.8 V 74AUP2G14 Product data sheet [2] All information provided in this document is subject to legal disclaimers. Rev. 6 -- 17 September 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 7 of 23 74AUP2G14 NXP Semiconductors Low-power dual Schmitt trigger inverter Table 8. Dynamic characteristics ...continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9. Symbol Parameter 25 C Conditions 40 C to +125 C Unit Min Typ[1] Max Min Max (85 C) Max (125 C) - 37.3 - - - - ns 4.0 9.8 18.7 3.9 19.6 20.0 ns CL = 30 pF propagation delay nA to nY; see Figure 8 tpd [2] VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V 3.7 7.1 11.2 3.8 12.3 12.9 ns VCC = 1.65 V to 1.95 V 3.6 6.0 9.1 3.6 10.0 10.6 ns VCC = 2.3 V to 2.7 V 3.5 5.2 6.9 3.2 7.5 7.9 ns VCC = 3.0 V to 3.6 V 3.3 4.8 6.1 3.1 7.1 7.4 ns VCC = 0.8 V - 2.6 - - - - pF VCC = 1.1 V to 1.3 V - 2.7 - - - - pF VCC = 1.4 V to 1.6 V - 2.9 - - - - pF VCC = 1.65 V to 1.95 V - 3.1 - - - - pF VCC = 2.3 V to 2.7 V - 3.7 - - - - pF VCC = 3.0 V to 3.6 V - 4.3 - - - - pF CL = 5 pF, 10 pF, 15 pF and 30 pF power dissipation capacitance CPD fi = 1 MHz; VI = GND to VCC [3][4] [1] All typical values are measured at nominal VCC. [2] tpd is the same as tPLH and tPHL. [3] All specified values are the average typical values over all stated loads. [4] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD VCC2 fi N + (CL VCC2 fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL VCC2 fo) = sum of the outputs. 74AUP2G14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 -- 17 September 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 8 of 23 74AUP2G14 NXP Semiconductors Low-power dual Schmitt trigger inverter 13. Waveforms 9, 90 Q$LQSXW 90 *1' W 3+/ W 3/+ 92+ 90 Q<RXWSXW 90 92/ PQD Measurement points are given in Table 9. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 8. Table 9. The data input (nA) to output (nY) propagation delays Measurement points Supply voltage Output Input VCC VM VM VI tr = tf 0.8 V to 3.6 V 0.5 VCC 0.5 VCC VCC 3.0 ns 9&& 9(;7 N * 9, 92 '87 57 &/ 5/ DDF Test data is given in Table 10. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 9. Table 10. Test circuit for measuring switching times Test data Supply voltage Load VCC CL RL[1] tPLH, tPHL tPZH, tPHZ tPZL, tPLZ 0.8 V to 3.6 V 5 pF, 10 pF, 15 pF and 30 pF 5 k or 1 M open GND 2 VCC [1] VEXT For measuring enable and disable times RL = 5 k, for measuring propagation delays, set-up and hold times and pulse width RL = 1 M. 74AUP2G14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 -- 17 September 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 9 of 23 74AUP2G14 NXP Semiconductors Low-power dual Schmitt trigger inverter 14. Transfer characteristics Table 11. Transfer characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9. Symbol Parameter VT+ VT VH positive-going threshold voltage negative-going threshold voltage 25 C Conditions 40 C to +125 C Unit Min Typ Max Min Max (85 C) Max (125 C) VCC = 0.8 V 0.30 - 0.60 0.30 0.60 0.62 VCC = 1.1 V 0.53 - 0.90 0.53 0.90 0.92 V VCC = 1.4 V 0.74 - 1.11 0.74 1.11 1.13 V VCC = 1.65 V 0.91 - 1.29 0.91 1.29 1.31 V VCC = 2.3 V 1.37 - 1.77 1.37 1.77 1.80 V VCC = 3.0 V 1.88 - 2.29 1.88 2.29 2.32 V VCC = 0.8 V 0.10 - 0.60 0.10 0.60 0.60 V VCC = 1.1 V 0.26 - 0.65 0.26 0.65 0.65 V VCC = 1.4 V 0.39 - 0.75 0.39 0.75 0.75 V VCC = 1.65 V 0.47 - 0.84 0.47 0.84 0.84 V VCC = 2.3 V 0.69 - 1.04 0.69 1.04 1.04 V VCC = 3.0 V 0.88 - 1.24 0.88 1.24 1.24 V see Figure 10 and Figure 11 V see Figure 10 and Figure 11 hysteresis voltage (VT+ VT); see Figure 10, Figure 11, Figure 12 and Figure 13 74AUP2G14 Product data sheet VCC = 0.8 V 0.07 - 0.50 0.07 0.50 0.50 V VCC = 1.1 V 0.08 - 0.46 0.08 0.46 0.46 V VCC = 1.4 V 0.18 - 0.56 0.18 0.56 0.56 V VCC = 1.65 V 0.27 - 0.66 0.27 0.66 0.66 V VCC = 2.3 V 0.53 - 0.92 0.53 0.92 0.92 V VCC = 3.0 V 0.79 - 1.31 0.79 1.31 1.31 V All information provided in this document is subject to legal disclaimers. Rev. 6 -- 17 September 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 10 of 23 74AUP2G14 NXP Semiconductors Low-power dual Schmitt trigger inverter 15. Waveforms transfer characteristics 92 97 9, 97 9, 9+ 97 97 9+ 92 PQD PQD VT+ and VT limits at 70 % and 20 %. Fig 10. Transfer characteristic Fig 11. Definition of VT+, VT and VH DDG ,&& $ 9, 9 Fig 12. Typical transfer characteristics; VCC = 1.8 V 74AUP2G14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 -- 17 September 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 11 of 23 74AUP2G14 NXP Semiconductors Low-power dual Schmitt trigger inverter DDG ,&& $ 9, 9 Fig 13. Typical transfer characteristics; VCC = 3.0 V 16. Application information The slow input rise and fall times cause additional power dissipation, this can be calculated using the following formula: Padd = fi (tr ICC(AV) + tf ICC(AV)) VCC where: Padd = additional power dissipation (W); fi = input frequency (MHz); tr = rise time (ns); 10 % to 90 %; tf = fall time (ns); 90 % to 10 %; ICC(AV) = average additional supply current (A). Average ICC(AV) differs with positive or negative input transitions, as shown in Figure 14. An example of a relaxation circuit using the 74AUP2G14 is shown in Figure 15. 74AUP2G14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 -- 17 September 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 12 of 23 74AUP2G14 NXP Semiconductors Low-power dual Schmitt trigger inverter DDG ,&& $9 P$ 9&& 9 (1) Positive-going edge. (2) Negative-going edge. Fig 14. Average ICC as a function of VCC 5 & PQD 1 1 f = --- ----------------T a RC Average values for variable a are given in Table 12. Fig 15. Relaxation oscillator Table 12. Variable values Supply voltage Variable a 1.1 V 1.28 1.5 V 1.22 1.8 V 1.24 2.8 V 1.34 3.3 V 1.45 74AUP2G14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 -- 17 September 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 13 of 23 74AUP2G14 NXP Semiconductors Low-power dual Schmitt trigger inverter 17. Package outline 3ODVWLFVXUIDFHPRXQWHGSDFNDJHOHDGV 627 ' % $ ( \ ; +( Y 0 $ 4 SLQ LQGH[ $ $ H ES F /S Z 0 % H GHWDLO; PP VFDOH ',0(16,216 PPDUHWKHRULJLQDOGLPHQVLRQV 81,7 $ $ PD[ ES F ' ( H H +( /S 4 Y Z \ PP 287/,1( 9(56,21 5()(5(1&(6 ,(& -('(& -(,7$ 6& 627 (8523($1 352-(&7,21 ,668('$7( Fig 16. Package outline SOT363 (SC-88) 74AUP2G14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 -- 17 September 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 14 of 23 74AUP2G14 NXP Semiconductors Low-power dual Schmitt trigger inverter 627 ;621SODVWLFH[WUHPHO\WKLQVPDOORXWOLQHSDFNDJHQROHDGVWHUPLQDOVERG\[[PP E [ / / H H H [ $ $ ' ( WHUPLQDO LQGH[DUHD PP VFDOH 'LPHQVLRQV PPDUHWKHRULJLQDOGLPHQVLRQV 8QLW PP PD[ QRP PLQ $ $ E ' ( H H / / 1RWHV ,QFOXGLQJSODWLQJWKLFNQHVV &DQEHYLVLEOHLQVRPHPDQXIDFWXULQJSURFHVVHV 2XWOLQH YHUVLRQ 627 VRWBSR 5HIHUHQFHV ,(& -('(& -(,7$ (XURSHDQ SURMHFWLRQ ,VVXHGDWH 02 Fig 17. Package outline SOT886 (XSON6) 74AUP2G14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 -- 17 September 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 15 of 23 74AUP2G14 NXP Semiconductors Low-power dual Schmitt trigger inverter ;621SODVWLFH[WUHPHO\WKLQVPDOORXWOLQHSDFNDJHQROHDGVWHUPLQDOVERG\[[PP 627 E i / / H H H i $ $ ' ( WHUPLQDO LQGH[DUHD PP VFDOH ',0(16,216 PPDUHWKHRULJLQDOGLPHQVLRQV 81,7 $ PD[ $ PD[ E ' ( H H / / PP 1RWH &DQEHYLVLEOHLQVRPHPDQXIDFWXULQJSURFHVVHV 5()(5(1&(6 287/,1( 9(56,21 ,(& 627 -('(& -(,7$ (8523($1 352-(&7,21 ,668('$7( Fig 18. Package outline SOT891 (XSON6) 74AUP2G14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 -- 17 September 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 16 of 23 74AUP2G14 NXP Semiconductors Low-power dual Schmitt trigger inverter ;621H[WUHPHO\WKLQVPDOORXWOLQHSDFNDJHQROHDGV WHUPLQDOVERG\[[PP 627 E i / / H H H i $ $ ' ( WHUPLQDO LQGH[DUHD VFDOH 'LPHQVLRQV 8QLW PP PP $ $ E ' ( H / H PD[ QRP PLQ / 1RWH ,QFOXGLQJSODWLQJWKLFNQHVV 9LVLEOHGHSHQGLQJXSRQXVHGPDQXIDFWXULQJWHFKQRORJ\ VRWBSR 5HIHUHQFHV 2XWOLQH YHUVLRQ ,(& -('(& -(,7$ 627 (XURSHDQ SURMHFWLRQ ,VVXHGDWH Fig 19. Package outline SOT1115 (XSON6) 74AUP2G14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 -- 17 September 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 17 of 23 74AUP2G14 NXP Semiconductors Low-power dual Schmitt trigger inverter ;621H[WUHPHO\WKLQVPDOORXWOLQHSDFNDJHQROHDGV WHUPLQDOVERG\[[PP 627 E i / / H H H i $ $ ' ( WHUPLQDO LQGH[DUHD VFDOH 'LPHQVLRQV 8QLW PP PP $ $ E ' ( H / H / PD[ QRP PLQ 1RWH ,QFOXGLQJSODWLQJWKLFNQHVV 9LVLEOHGHSHQGLQJXSRQXVHGPDQXIDFWXULQJWHFKQRORJ\ VRWBSR 5HIHUHQFHV 2XWOLQH YHUVLRQ ,(& -('(& -(,7$ 627 (XURSHDQ SURMHFWLRQ ,VVXHGDWH Fig 20. Package outline SOT1202 (XSON6) 74AUP2G14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 -- 17 September 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 18 of 23 74AUP2G14 NXP Semiconductors Low-power dual Schmitt trigger inverter ;621SODVWLFWKHUPDOHQKDQFHGH[WUHPHO\WKLQVPDOORXWOLQHSDFNDJHQROHDGV WHUPLQDOVERG\[[PP 627 ; $ ' % $ SLQ ,'DUHD ( $ GHWDLO; & H E [ \ & $ % Y \ / [ 'K [ H PP VFDOH 'LPHQVLRQV PPDUHWKHRULJLQDOGLPHQVLRQV 8QLW PP $ $ ' 'K ( H H E / Y \ \ PD[ QRP PLQ VRWBSR 2XWOLQH YHUVLRQ 5HIHUHQFHV ,(& -('(& -(,7$ (XURSHDQ SURMHFWLRQ ,VVXHGDWH 627 Fig 21. Package outline SOT1255 (X2SON6) 74AUP2G14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 -- 17 September 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 19 of 23 74AUP2G14 NXP Semiconductors Low-power dual Schmitt trigger inverter 18. Abbreviations Table 13. Abbreviations Acronym Description CDM Charged Device Model DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 19. Revision history Table 14. Revision history Document ID Release date Data sheet status Change notice Supersedes 74AUP2G14 v.6 20150917 Product data sheet - 74AUP2G14 v.5 Modifications: 74AUP2G14 v.5 Modifications: * Added type number 74AUP2G14GX (SOT1255/X2SON6). 20121204 * Product data sheet - 74AUP2G14 v.4 Package outline drawing of SOT886 (Figure 17) modified. 74AUP2G14 v.4 20111201 Product data sheet - 74AUP2G14 v.3 74AUP2G14 v.3 20100722 Product data sheet - 74AUP2G14 v.2 74AUP2G14 v.2 20090703 Product data sheet - 74AUP2G14 v.1 74AUP2G14 v.1 20061219 Product data sheet - - 74AUP2G14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 -- 17 September 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 20 of 23 74AUP2G14 NXP Semiconductors Low-power dual Schmitt trigger inverter 20. Legal information 20.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term `short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 20.2 Definitions Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification -- The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 20.3 Disclaimers Limited warranty and liability -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors' aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. 74AUP2G14 Product data sheet Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer's sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer's applications and products planned, as well as for the planned application and use of customer's third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer's applications or products, or the application or use by customer's third party customer(s). Customer is responsible for doing all necessary testing for the customer's applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer's third party customer(s). NXP does not accept any liability in this respect. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer's general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 6 -- 17 September 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 21 of 23 74AUP2G14 NXP Semiconductors Low-power dual Schmitt trigger inverter Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products -- Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors' warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors' specifications such use shall be solely at customer's own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors' standard warranty and NXP Semiconductors' product specifications. Translations -- A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 20.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 21. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74AUP2G14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 -- 17 September 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 22 of 23 74AUP2G14 NXP Semiconductors Low-power dual Schmitt trigger inverter 22. Contents 1 2 3 4 5 6 7 7.1 7.2 8 9 10 11 12 13 14 15 16 17 18 19 20 20.1 20.2 20.3 20.4 21 22 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Transfer characteristics . . . . . . . . . . . . . . . . . 10 Waveforms transfer characteristics. . . . . . . . 11 Application information. . . . . . . . . . . . . . . . . . 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 20 Legal information. . . . . . . . . . . . . . . . . . . . . . . 21 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 21 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Contact information. . . . . . . . . . . . . . . . . . . . . 22 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'. (c) NXP Semiconductors N.V. 2015. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 17 September 2015 Document identifier: 74AUP2G14