LD4000
PR4/EPR4 Read/Write Controller
version 2.1
GENERAL DESCRIPTION
The part is a high performance BICMOS read channel IC that provides all of the functions needed to
implement an entire Partial Response Class 4 (PR4) read channel for zoned recording hard disk drive
systems with data rates from 67 to 212 Mbps.
Functional blocks include a serial port, an automatic gain control amplifier, a programmable filter, an
offset canceller, a peak detecting pulse qualifier, an adaptive transversal filter, a Viterbi qualifier, a 8/9
GCR ENDEC, a data synchronizer, a time base generator, an integrating servo demodulator, as shown in
figure 1.
The part requires a single +5V power supply. The part utilizes an advanced BiCMOS process technology
along with advanced circuit design techniques which results in a high performance device with low power
consumption.
FEATURES
GENERAL
• Register programmable data rates from 67 to
212 Mbit/s
• Sampled data read channel with Viterbi
qualification
• Programmable filter for PR4 equalization
• Five tap transversal filter with adaptive PR4
equalization
• 8/9 GCR ENDEC
• Data Scrambler / Descrambler
• Presettable Precoder state
• Programmable write precompensation
• Low operating power - 1000mW maximum
at 5.5V to allow use of TOFP packages.
Active power management is applied to
achieve this target
• Register programmable power management
(<5 mW power down mode)
• 4-bit nibble and byte wide bi-directional
NRZ data interface
• 8 bit direct write mode automatically
configured for CLK=VCO/8
• Serial Interface port for access to internal
program storage registers
• Single power supply (5V ± 10%)
• Small package footprint: 100 lead TOFP
AUTOMATIC GAIN CONTROL
• Dual mode AGC, continuous time during
acquisition, sampled during data reads
• Separate AGC level storage pins for data and
servo
• Dual rate attack and decay charge pump for
rapid AGC recovery in continuous time mode
• Programmable, symmetric, charge pump
currents for data reads in sampled mode
• Charge pump currents track programmable
data rate during data reads
• Low drift AGC hold circuitry
• Low-Z circuitry at AGC input provides for
rapid external coupling capacitor recovery
• AGC Amplifier squelch during Low-Z
• Wide bandwidth amplitude feedback circuit
to allow improved stability of AGC level vs.
frequency
• Programmable AGC controls
• Separate external input pins for AGC
hold, fast recovery, and Low-Z control
or
• Internal Low-Z and fast recovery timing
for rapid transient recovery and AGC
acquisition. Timing set with external
resistors (2). Ultra fast decay current set
with external resistor.
LD4000
PR4/EPR4 Read/Write Controller
Page 2version 2.1
FILTER / EQUALIZER
• Programmable, 7-pole, continuous time filter
with asymmetrical zeros
• Channel filter and pulse slimming
equalization for coarse equalization to PR4
• Programmable cutoff frequency from 10 to
56 MHz
• Programmable boost/equalization of 0 to 13
dB
• Programmable “zeros” equalization provides
asymmetry compensation
• ±30% group delay variation from 0.3Fc to
Fc with Fc=56 MHz
• Low-Z switch for fast offset recovery at the
filter output
• No external coupling capacitors required
• DC offset compensation provided at the filter
output
• Three or Five tap transversal filter for fine
equalization to PR4.
• Self adapting symmetric Inner taps
• Programmable symmetric outer taps with 4
bits of resolution
• Equalization hold input
• Asymmetry factor output and “zeros”
channel quality output
PULSE QUALIFICATION
• Sampled Viterbi qualification of signal
equalized to PR4
• Register programmable hysteresis or window
qualification peak detector for servo reads,
with programmable thresholds
• Selectable RDS pulse width for servo grey
code reads
• RDS and PPOL outputs are disabled during
burst capture to reduce noise generation
TIME BASE GENERATOR
• Better than 1% frequency resolution
• Up to 225 MHz frequency output
• Independent M and N divide-by registers
• No active external components required
DATA SEPARATOR
• Fully integrated data separator includes data
synchronizer and 8/9 GCR ENDEC
• Register programmable to 212 Mbps
• Fast Acquisition, sampled data phase locked
loop
• Decision directed clock recovery from data
samples
• Adaptive clock recovery thresholds
• Programmable damping ratio for data
synchronizer PLL is constant for all data
rates
• Data scrambler / descrambler to reduce fixed
pattern effects
• Byte wide NRZ data interface and 4 bits
nibble interface
• Time base tracking, programmable write
precompensation
• Differential PECL write data output
• Surface defect scan mode
• Direct Write modes
SERVO
• 6-burst servo capture with A-B, C-D, E-F
outputs
• Internal hold capacitors
• Separate, automatically selected, registers for
servo fc, boost, and threshold
• Wide bandwidth, high precision full-wave
rectifier is optimized for low-level linearity
• “Soft Landing” charge pump architecture
• Programmable selection of normal or
differentiated filter output to servo-capture
block
• Programmable gain with 2 external inputs
LD4000
PR4/EPR4 Read/Write Controller
Page 3version 2.1
PROGRAMMABLE 7th
ORDER LOW-PASS
FILTER
ASYMMETRIC 0's
DC OFFSET
CANCEL
LEVEL OR
HYSTERISIS
PULSE QUAL
TPE MUX
TPD
MUX
TPC
MUX
VIA
VIAB
98
97
OD+
OD-
ON+
ON-
CP
CN
DP
DN
SFWR
LOWZ
FASTREC
UFDC
RX
TPD
TPDB
TPC
TPCB
TPE
88 89 90 91 87
96
To SFC
5-TAP
EQUALIZER
2-ADAPTIVE
2-PROG
VITERBI
DETECTOR
TEST POINT
MUX
MUX
EN LOWZSFC
DSCLK ASYMM FACTOR
SSBYP
CHANQUAL
RDS/RDSB
PPOL
EQHOLD
TPAB
TPA
TPB
TPBB
VRDT
84 85 60 66 65 64 63 8
VNS
VNS
VNP
VNF
VNC
VNT
VND
VNA
69 67 55 54 14 18 37 86
VPS
VPS
VPP
VPF
VPC
VPT
VPD
VPA
62 68 58 47 12 15 38 95
CODE WORD
BOUNDARY
DETECTOR
SERIAL TO
PARALLEL
SYNC
FIELD
COUNTER
9/8
(0,4/4)
DECODER
8/9
(0,4/4)
ENCODER
DESCRAMBLER
SCRAMBLER
FROM
LEVEL QUAL
SFC
CWBD DSCLK
PARALLEL
INTERFACE
NIBBLE
INTERFACE
PARITY
GEN/CHK
DUAL "OR"
TYPE SYNC
BYTE
DETECTOR
AUTOMATIC
TRAINING & SYNC BYTE
GENERATOR
RCLK
WCLK
NRZ0-7
NRZP
PERR/NCLK
SBDB
30
31
32
33-36, 39-42
43
MUX
MUXMUX
PARALLEL
TO SERIAL PRECODER
VCO SYNC
PATTERN
GEN
WRITE
PRECOMP WRITE
FLIP-FLOP
TBGOUT
DWB
DW
WDB
WD
DWRB
19
20
21
22
45
FULL WAVE
RECTIFIER
FULL WAVE
RECTIFIER
DAC
CONV
AGC
CHARGE
PUMP
SAMPLED
AGC
CHARGE
PUMP
AGC CONTROL
LOGIC
SERVO
HOLD
FASTREC
LOWZ
SQUELCH
UFDC
LOWZ
FASTREC
6
7
94
93
WRDEL
AGCDEL
SERIAL
PORT &
CONTROL
REGISTERS
CONTROL
LOGIC
VREF
VREF
SDEN
SCLK
SDATA
SG
RG
WG
73
11
9
10
83
29
28
BYPS
BYPD
HOLDB
AGCRST UFDC
SFC
VCC
4
3
5
92
SG
HOLD
VMIN
SQUELCH
SFWR
E
C
A
DECODE
LOGIC
VREFS
E-F
C-D
A-B
AV1
AV0
VREFS
STROBE
RESETB
N/X
79808182716970
1/(M+1)
1/(N+1)
DECISION
DIRECTED
PHASE
DETECTOR
PHASE/
FREQ
DETECTOR
CHARGE
PUMP
PHASE/
FREQ
DETECTOR
CHARGE
PUMP VCO
VCO
DAMPING
CONTROL
RCLK
CLOCK
GEN
ATO
TEST
MUX
POWER
DOWN
CONTROL
DSCLK
TBGOUT
CWBD
DATA SYNCHRONIZER
TIME BASE GENERATOR
CHANQUAL
ASYMM FACTOR
VREFS
DACs
RCLK
ATO
RCLK 44
61
FREF
FLTR2
FLTR2B
PDWNB
FLTR1B
FLTR1
RR
13 72 16 17 57 56 46
AGC
AMP
SP SP
SP
SP SP
SP
SP
SP SFC
SP
TBGOUT
SP
SP
7877
SERVO
LEAKAGE
+
-SP
SP
SMS
SP
SP
Fig 1 LD4000 Block Diagram
SP
SP
SP
SP
LD4000
PR4/EPR4 Read/Write Controller
Page 54 version 2.1
N/C
N/C
RR
VREF
VREFS
RESETB
VPS
STROBE
VNS
TPA
TPB
TPAB
TPBB
VPS
EQHOLD
ATO
VNS
VPP
FLTR2B
FLTR2
VNP
VNC
N/C
N/C
N/C
N/C
N/C
RG
WG/WGB
SBDB
PERR
NRZ0
NRZP
NRZ1
NRZ2
VND
NRZ3
VPD
NRZ4
NRZ6
NRZ5
NRZ7
WCLK
DWRB
RCLK
PDWNB
VPC
N/C
N/C
N/C
N/C
N/C
WD
N/C
WDB
DW1
VNT
DW1B
FLTR1B
FLTR1
VNF
VPT
FREF
VPF
SDATA
SDEN
SCLK
VRDT
LOWZ
FASTREC
HOLDB
BYPS
N/C
BYPD
N/C
N/C
AV0
E-F
AV1
C-D
A-B
SG
N/X
RDS/RDSB
PPOL
TPE
VNA
TPD
TPDB
TPCB
TPC
AGCRST
AGCDEL
VPA
WRDEL
RX
VIAB
N/C
VIA
N/C
LD4000
75
74
72
73
71
70
68
69
67
66
64
65
63
62
60
61
59
58
56
57
55
54
52
53
51
26
27
29
28
30
31
33
32
34
35
37
36
38
39
41
40
42
43
45
44
46
47
49
48
50
25
24
22
23
21
20
18
19
17
16
14
15
13
12
10
11
9
8
6
7
5
4
2
3
1
76
77
79
78
80
81
83
82
84
85
87
86
88
89
91
90
92
93
95
94
96
97
99
98
100
100-Lead TQFP
