2004 Microchip Technology Inc. DS21226E-page 1
24LCS61/24LCS62
Device Selection Table
Features
• Low-power CMOS technology
- 1 mA active current typical
-10 µA standby current typical at 5.5V
• Software addressability allows up to 255 devices
on the same bus
• 2-wire serial interface bus, I2C compatible
• Automa tic bus arbitration
• Wakes up to control code 0110
• General purpose outp ut pin can b e used to en able
other cir cuitry
• 100 kHz and 400 kHz compatibility
• Page write buffer for up to 16 bytes
• 10 ms max write cycle time for byte or page write
• 1,000,000 erase/write cycles
• 8-pin PDIP, SOIC or TSSOP packages
• Temperature ranges supported:
Description
The Micro chip Technology In c. 24LCS61 /62 is a 1 K/2K
bit Serial EEPROM developed for applications that
require ma ny device s on the same bus but do not have
the I/O pins required to address each one individually.
These devices contain an 8 bit address register that is
set upon power-up and allows the connection of up to
255 devices on the same bus. When the process of
assi gning ID valu es to eac h device i s in prog ress, the
device will automatically handle bus arbitration if more
than one devic e is o perati ng on th e bus. In a dditio n, an
external open drain output pin is available that can be
used to enable other circuitry associated with each
individual system. Low current design permits
operation with typical standby and active currents of
only 10 µA and 1 mA respectively. The device has a
page write capability for up to 16 bytes of data. The
device is available in the standard 8-pin PDIP, SOIC
(150 mil), and TSSO P pa ckage s.
Package Types
Block Diagram
Pin Function Table
Device Array
Size Voltage
Range Software Write
Protection
24LCS51 1K bits 2.5V-5.5V Entire Array
24LCS62 2K bits 2.5V-5.5V Lower Half
- Industrial (I): -40°C to +85°C
Name Function
VSS Ground
SDA Serial Data
SCL Serial Clock
VCC +2.5V to 5.5V Power Supply
NC No Internal Connection
EDS External Device Select Output
PDIP NC
NC
EDS
Vss
Vcc
NC
SCL
SDA
24LCS61/62
1
2
3
4
8
7
6
5
NC
NC
EDS
Vss
VCC
NC
SCL
SDA
24LCS61/62
1
2
3
4
8
7
6
5
SOIC
TSSOP
24LCS61/62
NC
NC
EDS
VSS
Vcc
NC
SCL
SDA
1
2
3
4
8
7
6
5
I/O
Control
Logic
Memory
Control
Logic XDEC
HV Generator
EEPROM
Array
YDEC
VCC
VSS Sense Amp.
R/W Control
SDA SCL
EDS
ID Register
Serial Number
1K/2K Software Addressable I2C™ Serial EEPROM
I2C is a trademark of Philips Corporation.
Obsolete Device
24LCS61/24LCS62
DS21226E-page 2 2004 Microchip Technology Inc.
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings(†)
VCC.............................................................................................................................................................................7.0V
All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V
Storage temperature ............................................................................................................................... -65°C to +150°C
Ambient temperature with power applied................................................................................................-65°C to +125°C
ESD protection on all pins......................................................................................................................................................≥ 4 kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at those or any other conditions
above th ose indi cated in the opera tional li stings of this sp ecificati on is no t implie d. Exposu re to maxim um rating
conditions for extended periods may affect device reliability.
TABLE 1-1: DC CHARACTERISTICS
All parameters apply across the
specified operating ranges unless
otherwise noted.
VCC = +2.5V to +5.5V
Industrial (I): TA = -40°C to +85°C
Parameter Symbol Min. Max. Units Conditions
SCL and SDA pins:
High-level input voltage VIH 0.7 VCC —V
Low-level input voltage VIL —.3 VCC V
Hysteresis of Schmitt Trigger
inputs VHYS 0.05 VCC —V
Low-level output voltage
(SDA and EDS pins) VOL —.40VIOL = 12 mA, VCC = 4.5V
IOL = 8 mA, VCC = 2.5V
Input leakage current ILI —±1µAVIN = Vss or Vcc
Output lea kage curre nt ILO —±1µAVOUT = Vss or Vcc
Pin capacitance (all inputs/outputs) CIN,
COUT —10pFVCC = 5.0V (Note )
TA = 25°C, f = 1 MHz
Operati ng current ICC Write — 4 mA VCC = 5.5V
ICC Read — 1 mA VCC = 5.5V, SCL = 400 kHz
Standby current ICCS —50µAVCC = 5.5V, SDA = SCL = VCC
EDS = VCC
Note: This parameter is periodically sampled and not 100% tested.
2004 Microchip Technology Inc. DS21226E-page 3
24LCS61/24LCS62
TABLE 1-2: AC CHARACTERISTICS
FIGURE 1-1: BUS TIMING DATA
All parameters apply across the specified
operating ranges unless otherwise noted. Vcc = +2.5V to 5.5V
Industri al (I): TA = -40°C to +85°C
Parameter Symbol VCC = 2.5V - 5.5V
STD MODE Vcc = 4.5V - 5.5V
FAST MODE Units Remarks
Min. Max. Min. Max.
Clock frequency FCLK — 100 — 400 kHz
Clock high time THIGH 4000 — 600 — ns
Clock low time TLOW 4700 — 1300 — ns
SDA and SCL rise time TR— 1000 — 300 ns From VIL to VIH (Note 1)
SDA and SCL fall time TF— 300 — 300 ns From VIL to VIH (Note 1)
Start condition hold time THD:STA 4000 — 600 — ns After this period the first
clock pulse is generated
Start condition setup time TSU:STA 4700 — 600 — ns Only relevant for repeated
Start condition
Data input hold time THD:DAT 0—0—ns(Note 2)
Data input setup time TSU:DAT 250 — 100 — ns
Stop condition setup time TSU:STO 4000 — 600 — ns
Output valid from clock TAA — 3500 — 900 ns (Note 2)
Bus free time TBUF 4700 — 1300 — ns Time the bus must be free
before a new transmission
can start
Output fall time
(from 0.7 VCC to 0.3 V CC)TOF — 2 50 20 +0.1
CB250 ns (N ote 1), CB ≤ 100 pF
Input fil ter sp ik e s upp res si on
(SDA and SCL pi ns) TSP — 50 — 50 ns ( No tes 1, 3)
Write cycle time TWC — 10 — 10 ms Byte or Page mode
Endurance 1M — 1M — cycles 25°C , VCC = 5.0V, Block
mode (Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined TSP and VHYS specifications are due to Schmitt Trigger inputs which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but ensured by charac teri zation. For endura nce estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained from our web site.
SCL
SDA
IN
Tsu:sta
SDA
OUT
THD:STA
TLOW
THIGH TR
TBUF
TAA
THD:DAT TSU:DAT TSU:STO
TSP
TF
24LCS61/24LCS62
DS21226E-page 4 2004 Microchip Technology Inc.
2.0 PIN DESCRIPTIONS
2.1 SDA (Serial Data)
This is a bidirectional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pull-up
resistor to VCC (typical 10 kΩ for 100 kHz, 2 kΩ for
400 kHz).
For norma l data trans fer SDA is all owed to change only
during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
The SDA pin has Schmitt Trigger and filter circuits
which suppress noise spikes to assure proper device
operation even on a noisy bus
2.2 SCL (Serial Clock)
This i nput is u sed t o sy nchron ize the d ata trans fer fro m
and to the device. The SCL pin has Schmitt Trigger and
filter circuits which suppress noise spikes to assure
proper device operation even on a noisy bus.
2.3 EDS (External Device Select )
The Exter na l Devi ce S el ec t (EDS) pin is an op en drai n
output that is controlled by using the OE bit in the
control byte. It can be used to enable other circuitry
when th e de vi ce is sele ct ed. A p ull -up resistor must be
added to this pin for proper operation. This pin should
not be pulled up to a voltage higher than Vcc+1V. See
Section 9.0 “External Device Select (EDS) Pin and
Output Enable (OE) Bit” for more details.
3.0 BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stab le whene ver the cl ock lin e is high . Change s in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (Fig ure 3-1).
3.1 Bus not Busy (A)
Both data and clock lines remain high.
3.2 Start Data Transfer (B)
A hig h- to - lo w t ran si t i on of t h e SD A l in e whi l e t h e c lo ck
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
3.3 Stop Data Transfer (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.
3.4 Data Valid (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one bit of data per
clock pulse.
Each dat a transf er is initiated w ith a S tart condition an d
terminated with a Stop condition. The number of data
bytes transferred between the Start and Stop
conditions is determined by the master device and is
theoretically unlimited, although only the last sixteen
will be stored when doing a write operation. When an
overwri te d oes oc c ur it will repl ac e da t a i n a firs t in firs t
out fashion.
FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(A) (B) (D) (D) (A)(C)
SCL
SDA
START
CONDITION DATA OR
ACKNOWLEDGE
VALID
DATA
ALLOWED
TO CHANGE
STOP
CONDITION
2004 Microchip Technology Inc. DS21226E-page 5
24LCS61/24LCS62
3.5 Acknowledge
Each receiving device, when addressed, is required to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this Acknowledge bit.
The device that acknowledges has to pull down the
SDA line du ring the Acknow ledge cl ock pulse in s uch a
way that the SDA line is stable low during the high
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by no t g ene rati ng an Ackno wled ge bi t on the las t
byte that has been clocked out of the slave. In this
case, the slave must leave the data line high to enable
the maste r to gen erat e the Stop conditi on (Fi gure 3-2 ).
FIGURE 3-2: ACKNOWLEDGE TIMING
Note: The 24LCS61/62 does not generate any
Acknowledge bits if an internal program-
ming cycle is in progress.
SCL 987654321123
Transmitter must release the SDA line at this point
allowing the Receiver to pull the SDA line low to
acknowledge the previous eight bits of data.
Receiver must release the SDA line at this point
so the Transmitter can conti nue sending data.
Data from transmitter Data from transmitter
SDA
Acknowledge
Bit
24LCS61/24LCS62
DS21226E-page 6 2004 Microchip Technology Inc.
4.0 FUNCTIONAL DESCRIPTION
The 24LCS61/62 supports a bidirectional 2-wire bus
and data transmissio n protoco l c om p a tible with the I2C
protocol. The device is configured to reside on a
common I2C bus with up to 255 total 24LCS61/62
devices on the bus. Each device has a unique serial
number assigned to it when delivered from the factory.
In an actual system, this serial number will be used to
assign a separate 8-bit ID byte to each device in the
system. After an ID byte is assigned to each device in
the system, standard Read and Write commands can
be sent to each device individually.
4.1 Device Serial Number
The device serial number is stored in a 48-bit (6 byte)
register that is separate from the data array. The serial
number register is nonvolatile and cannot be changed
by the user. Before shipment from the factory, this
register is programmed with a unique value for every
device. The 48 bit register allows for 2.8•1014 different
combinations. The serial number is used at power-up
to assign the device an ID byte which is then used for
all standard Read and Write commands sent to that
specific device.
4.2 Device ID Byte
The Device ID byte is an 8-bit value that provides the
means for every device on the bus to be accessed
individually. The ID byte is stored in a RAM register
separate from the data array. The ID byte register will
always default to address 00 upon power-up.
4.3 Device Addressing
Each command to the device must begin with a Start
bit. A c ontrol byte is t he first byte receiv ed fo llowing the
Start condition from the master device (Figure 4-1).
The control byte consists of a four-bit control code, the
OE bit, and three command select bits. For the
24LCS6 1/62, the control code is se t to ‘0110’ bina ry for
all operations. The device will not acknowledge any
commands sent with any other control code. The next
bit is the Output Enable (OE) bit. This bit controls the
operation of the EDS pin. See Section 9.0 “External
Device Select (EDS) Pin and Output Enable (OE)
Bit” for more details. The last three bits of the control
byte are the command select bits (C0-C2). The
comma nd select bit s determine w hich command will be
executed. See Table 4-1. Following a valid control byt e,
the 24LCS61/62 will acknowledge the command.
FIGURE 4-1: CONTROL BYTE FORMAT
TABLE 4-1: COMMAND CODES
Command Command Select Bit s
(C2 C1 C0)
Set Write Protection Fuse 000
Read 001
Write (Byte or Page) 010
Assign Addre ss 100
Clear Addres s 110
1010OEC2C1SACK
Control Code Command Select
Bits
Acknowledge Bit
Start Bit
C0
Output Enable
Bit
2004 Microchip Technology Inc. DS21226E-page 7
24LCS61/24LCS62
5.0 ASSIGNING THE ID BYTE
The 24LCS61/62 device contains a special register
which holds an 8-bit ID by te that is used as an addres s
to communicate with a specific device on the bus. All
Read and Write commands to the device must include
this ID address byte. Upon power-up, the ID byte will
default to 00h. Communicating with the device using
the default address is typically done only at testing or
programming time and not when it is connected to a
bus with more than one device. Before the device can
be used on a common bus with other devices, a unique
ID byte address must be assigned to every device.
5.1 Assign Address Command
The ID by te is assigned by send ing the Assign Add ress
command. This command queries any device
connected to the bus and utilizing the automatic bus
arbit ration feature, assigns an ID byte to the d evice that
remains on the bus after arbitration is complete. Once
a device has been ass igned an ID by te, it will no longer
respond to Assign Address commands until power is
cycled or the Clear Address command is sent. The
Assign Address command must be repeated for each
devi ce on t he bus unti l all devi ce s have bee n as signed
an ID byte.
The format for the Assign Address command is shown
in Figure 5-1. The command consists of the control
byte, the ID byte to be assigned to the device remai ning
when the arbitration is complete, and 48 bits of data
being tra nsmitted by devices on the bus . If the OE b it is
set to a 1, th en any devi ce wh o ha s no t bee n as si gned
an address will assert their respective EDS pin after the
Acknow ledge bit fol lowing t he De vice ID byte. Af ter the
control byte and ID byte are sent, each device will
begin to transmit its unique 48-bit serial number.
The 24LCS61/62 must acknowledge the control byte
and the device ID byte, and the master must acknowl-
edge each by te of the s eria l n um ber transm it ted by th e
device. As each bit is clocked out, each device will
monitor the bus to detect if another device is also
transmi tting. If any devi ce is outputtin g a logic ‘1’ on th e
bus and it detects that the bus is at a logic ‘0’, then it
assumes that another device is controlling the bus. As
soon as any device detects that it is not controlling the
bus it will imme diately s top transm itting dat a and retu rn
to Standby mode. The master must end the command
by sending a no ACK after all 6 bytes of the serial
number have been transmitted, followed by a Stop bit.
Sending the Stop bit in any other position of the
command will result in the command aborting and all
devices releasing the bus with no address assigned. If
a device transmit s its entire 48 bit serial number without
releasing the bus to another device, then the ID byte
transmitted within the command is transferred to the
internal ID byte re gister up on recei pt of the S top bit and
it will now respond only to commands that contain this
ID byte (or the Clear Address command). Once a
device has been assigned an ID byte, it will no longer
respond to Assign Address commands until power is
cycled or the Clear Address command is sent.
This process of assigning ID bytes is repeated by the
controller until no more devices respond to the Assign
Address co mmand. At this poi nt, all device s on the bus
have be en assigned an ID byte an d standar d Read and
Write commands can be executed to each individual
device.
The ID byte is sto red in a vola tile SRAM reg ister, and if
power is remove d from the device or the Clear Addres s
command is sent, then the ID byte will default to
address 00 and the process of assigning an ID value
must be repeated.
FIGURE 5-1: ASSIGN ADDRESS COMMAND
SP
S
T
A
R
T
CONTROL
BYTE
S
T
O
P
Device ID Byt e
6 Bytes (48 Bits) of Device Serial Number
with each byte separated by an ACK bit
1010
A unique address must be assigned to each
device on the bus
A
C
K
A
C
K
A
C
K
A
C
K
O100
Stop bit must occur here
or command will abort
EN
O
A
C
K
24LCS61/24LCS62
DS21226E-page 8 2004 Microchip Technology Inc.
5.2 Clear Address Command
The Clear Address command will clear the device ID
byte from all devices on the bus and will enable all
devices to respond to the Assign Address command.
The master must end the command by sending a n ACK
after 8 don’t care bits have been transmitted, followed
by a S top bit. Sending the Stop bit in any other position
of the command will result in the command aborting
and the devic e relea si ng the bus .
FIGURE 5-2: CLEAR ADDRESS COMMAND
5.3 Operation State Diagram
The diagram below shows the state diagram for basic
operation of the 24LCS61/62. This diagram shows
possible states and operational flow once power is
applied to the device. Table 5-1 summarizes operation
of each command for the assigned and unassigned
states.
FIGURE 5-3: OPERATIONAL STATE DIAGRAM
SP
S
T
A
R
T
CONTROL
BYTE
S
T
O
P
A
C
K
Device ID Byte
1010
A
C
K
XXXXXXXX
011
O
E
Power
Off
Unassigned
State Assigned
State
Power Off
Power On
Power Off
Assign Address Command:
Device wins Arbitration
Clear Address
Command
Assign Address Command:
Device loses Arbitration
(ID byte not assigned yet) ( ID byte has bee n assign ed)
2004 Microchip Technology Inc. DS21226E-page 9
24LCS61/24LCS62
TABLE 5-1: COMMAND SUMMARY TABLE
Command Result if Device Has Not Yet
Been Assigned an ID Byte Result if Device Has Already Been
Assigned an ID Byte
Assign Addre ss
command If device wins arbitration, then ID
byte will become xxh. If device
loses arbitration, then ID byte will
revert back to 00h.
Device will not acknowledge command.
Clear Address
command Device will remain with ID byte set
to 00h. Device ID byte will revert back to 00h and will then
ackn owledge Assign Addr ess commands.
Read or Write
comma nd with
ID byte set to 00h
Since the default ID byte for the
device is 00h, the device will
execute the command.
Device will acknowledge the control byte, but it will not
acknowledge any further bytes and will not respond to
the command.
Read or Write
comma nd with
ID byte set to xxh
(other than 00h)
Device will acknowledge the
control byte, but it will not acknowl-
edge any further bytes and will not
respond to the command.
If the devic e ID byte matches the ID byt e in the command
(xxh), the device will execut e the com mand. If the dev ice
ID byte does not ma tch the ID byte in the command , then
the device will acknowledge the control byte, but it will
not acknowledge any further bytes and will not respond
to the command.
Set Write-Protect
comma nd with
ID byte set to 00h
Since the default ID address for the
device is 00h, the device will
execute the command.
Device will acknowledge the control byte, but it will not
acknowledge any further bytes and will not respond to
the command.
Set Write Protection
comma nd with
ID byte set to xxh
(other than 00h)
Device will acknowledge the
control byte, but it will not acknowl-
edge any further bytes and will not
respond to the command.
If the devic e ID byte matches the ID byt e in the command
(xxh), the device will execut e the com mand. If the dev ice
ID byte does not ma tch the ID byte in the command , then
the device will acknowledge the control byte, but it will
not acknowledge any further bytes and will not respond
to the command. Note: Once this command has been
executed successf ully for a device, the devi ce will no
longer acknowledge any part of this command again.
24LCS61/24LCS62
DS21226E-page 10 2004 Microchip Technology Inc.
6.0 WRITE OPERATIONS
6.1 Byte Write
Following the Start signal from the master, the control
byte for a Write command is sent by the master
transmitter. The device will acknowledge this control
byte during the ninth clock pulse. The next byte
transmitted by the master is the ID byte for the device.
After receiving another Acknowledge signal from the
24LCS61/62, the master device will transmit the
address and then the data word to be written into the
addressed memory location. The 24LCS61/62
acknowl edges between each byte, and the master then
generates a Stop condition. This initiates the internal
write cycle, and during this time the 24LCS61/62 will
not generate Acknowledge signals (Figure 6-1).
6.2 Page Write
The control byte, ID byte, word address, and the first
data byte are transmitted to the 24LCS61/62 in the
same way a s in a b yte w ri te. But, ins tea d of ge nerating
a Stop condition, the master transmits up to 15
additional data bytes to the 24LCS61/62, which are
tempora rily stored in the on-chip page buffer and will be
written into the memory after the master has transmit-
ted a Stop co ndition. If the master should transmit mo re
than 1 6 bytes p rior to gen erating the S top cond ition, the
address counter will roll over and the previously
receive d dat a wil l be overwri tten. As w ith the byte write
operation, once the Stop condition is received an
internal write cycle will begin (Figure 6-2) and the
24LCS61/62 will not generate acknowledge.
6.3 Low Voltage Write Protection
The 24LCS61/62 employs a VCC threshold detector
circuit which disables the internal erase/write logic, if
the VCC is below 1.5 vo lt s at nomin al con ditions.
6.4 Set Write Protection Command
The Set Write Protection command allows the user to
write-protect a portion of the array. For the 24LCS51
this comm and will wri te-protect t he entire array. For the
24LCS62 this command will protect the lower half of
the array. This command is illustrated in Figure 6-3.
This is a one time only command and cannot be
reversed once the protection fuse has been set.
Once th e write-pr otect featur e has been s et, the dev ice
will no longe r acknowl edge th e contr ol byte (or any of
the other bytes) of this command. The Stop bit of this
command initiates an internal write cycle, and during
this time the 24LCS61/62 will not generate
Acknowledge signals.
FIGURE 6-1: BYTE WRITE
Note: Page write opera tions are l imited to wri ting
bytes within a single physical page,
regardless of the numb er o f by tes ac tua ll y
being written. Physical page boundaries
start at addresses that are integer
multiples of the page buffer size (or ‘page
size’) and end at addresses that are
integer multiples of [page size - 1]. If a
Page Write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being w ritte n to th e nex t page as mi ght be
expected. It is therefore necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.
S
T
A
R
T
S
T
O
P
DEVICE
ID BYTE DATA
CONTROL
BYTE
A
C
K
A
C
K
A
C
K
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY A
C
K
ADDRESS
BYTE
1010
O010
SE
OE Bit = EDS Pin Output Enable; see Section 9.0 “External Device Select (EDS) Pin and Output Enable (OE) Bit”
P
2004 Microchip Technology Inc. DS21226E-page 11
24LCS61/24LCS62
FIGURE 6-2: PAGE WRITE
FIGURE 6-3: SET WRITE PROTECTION COMMAND
S
T
A
R
T
S
T
O
P
CONTROL
BYTE
A
C
K
A
C
K
A
C
K
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY A
C
K
ADDRESS
BYTE DATA BYTE 0
A
C
K
DATA BYTE 15
DEVICE
ID BYTE
1010010
SO
EP
S
S
T
A
R
T
CONTROL
BYTE
A
C
K
1010
A
C
K
000 P
S
T
O
P
A
C
K
XXXXXXXX A
C
K
XXXXXXXX
DEVICE
ID BYTE
O
E
ADDRESS
BYTE DATA BYTE
24LCS61/24LCS62
DS21226E-page 12 2004 Microchip Technology Inc.
7.0 ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the Stop condition for a Write
comma nd has been is sued from the master , the device
initiates the internally timed write cycle. ACK polling
can be initiated immediately. This involves the master
sending a Start condition followed by the control byte
for a Write command and then sending the Device ID
byte f o r tha t parti c ul ar de vi ce . If th e d ev i ce is st ill bu sy
with the write cycle, then no ACK will be returned after
the Device ID byte. If no ACK is returned, the n the S t art
bit, control byte and ID byte must be re-sent . If the cycle
is compl ete, then the dev ice will return the ACK and the
master can then proceed with the next command. See
Figure 7-1 for flow diagram.
FIGURE 7-1: ACKNOWLEDGE
POLLING FLOW
Send
Write Command
Send S top
Condition to
Initia te Wr ite C y cle
Send Start
Did Device
Acknowledge
(ACK = 0)?
Next
Operation
NO
YES
Send Control byte and
Device I D byte
Device ID
2004 Microchip Technology Inc. DS21226E-page 13
24LCS61/24LCS62
8.0 READ OPERATIONS
Read operations are initiated in a similar way as the
write operations. There are three basic types of read
operations: current address read, random read, and
sequential read.
8.1 Current Address Read
The 24LCS61/62 contains an address counter that
maintains the address of the last word accessed,
internally incremented by one. Therefore, if the
previous read access was to address n, the next
current address read operation would access dat a from
address n + 1. Upon receipt of the correct control byte
and ID byte, the 24LCS61/62 issues an acknowledge
and transmits the eight bit data word. The master will
not ackn owledge the transfer but does generat e a S top
condition and the 24LCS61/62 discontinues
transmission (Figure 8-1).
8.2 Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this typ e of re ad ope ration, first the wo rd address mus t
be set. This is done b y sending the word address to the
24LCS61/62 as part of a write operation.
After the ID byte and word address are sent, the master
generates a Start condition fo llo w ing the ac kn ow le dg e.
This terminates the write operation, but not before the
internal address pointer is set. Then the master sends
the contro l by te a nd ID by te for a R ea d co mm an d. Th e
24LCS61/62 will then issue an acknowledge and
transmits the eight bit data word. The master will not
acknowledge the transfer but does generate a Stop
condition and the 24LCS61/62 discontinues
transmission (Figure 8-2).
8.3 Sequential Read
Sequential reads are initiated in the same way as a
random re ad exce pt t hat a fter the 24 LC S61/ 62 tra ns-
mits the first data byte, the master issues an acknowl-
edge as opposed to a Stop condition in a random
read. This dire cts the 24LC S61/62 to tr ansm it the nex t
sequent ial ly ad dr ess ed 8-bi t w ord (F ig ur e 8-3) .
To provide sequential reads the 24LCS61/62 contains
an internal address pointer which is incremented by
one at the completion of each operation. This address
pointer all ows the entire memor y contents to be seriall y
read during one operation. The int ernal address pointer
will automatically roll over from address 7Fh
(24LCS51) or FFh (24LCS62) to address 00h.
FIGURE 8-1: CURRENT ADDRESS READ
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
P
S
S
T
O
P
CONTROL
BYTE
S
T
A
R
TDATA
A
C
K
A
C
K
DEVICE
ID BYTE
N
O
A
C
K
1
010O001
E
OE Bit = EDS Pin Output Enable; see Section 9.0 “External Device Sele ct (EDS) Pin an d Output Enab le (OE) Bit”
24LCS61/24LCS62
DS21226E-page 14 2004 Microchip Technology Inc.
FIGURE 8-2: RANDOM READ
FIGURE 8-3: SEQUENTIAL READ
CONTROL
BYTE
A
C
K
A
C
K
A
C
K
ADDRESS
BYTE CONTROL
BYTE
A
C
K
DATA
BYTE
DEVICE
ID BYTE
A
C
K
DEVICE
ID BYTE
S
T
A
R
T
S
T
A
R
T
S
T
O
P
N
O
A
C
K
1
010O010
SS1010
O001
E
E
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
ID
BYTE DATA n DATA n + 1 DATA n + 2 DATA n + X
A
C
K
A
C
K
A
C
K
A
C
K
P
N
O
A
C
K
S
T
O
P
2004 Microchip Technology Inc. DS21226E-page 15
24LCS61/24LCS62
9.0 EXTERNAL DEVICE SELECT
(EDS) PIN AND OUTPUT
ENABLE (OE) BIT
The External Device Select (EDS) pin i s an open drai n,
low active output and may be used by the system
designer for functions such as enabling other circuitry
when the 24 LCS61/ 62 is be ing acces sed. Be caus e the
pin is an open drain outpu t, a pull-up resist or is required
for proper operation of this pin. When the device is
powered up, the EDS pin will always be in the high-
impedance state (off). The EDS pin function is
controlled by using the output enable (OE) bit in the
control byte of eac h comma nd. If the O E bit is high , the
EDS pin is enabled and if the OE bit is low the pin is
disabled. For the Assign Address command and
standard Read or Write commands, the EDS pin will
pull low (providing that the O E bit is set h igh) on th e ris-
ing clock edge after the ack bit following the ID byte.
See Figure 9-1. For commands such as the Clear
Address command, the EDS pin will change states at
the rising clock edge just before the Stop bit. It is also
possible to control the EDS pin by sending a partial
command such as the control byte and ID byte for a
Write command followed by the Stop bit. The EDS pin
would change states just before the Stop bit as shown
in the lower portion of Figure 9-1. When the EDS pin
has changed states, it is latched and will remain in a
given s tat e until an other comm and is sen t to the device
with the OE bit set to change the state of the pin, or
power to the device is removed.
FIGURE 9-1: EDS PIN OPERATION
SCL 987654321 123
For commands such as the Assign Address command or standard read and
writes, the EDS pin will be asserted on this rising clock edge if the OE bit was set
to a one i n the control byte . If the OE bit is a zer o and the previou s command
assert ed it, then the EDS pin will be released by the device on this clock edge.
SDA
98765123
0110
Start
Bit Control
Byte ACK
BIT
4
ID Byte ACK
BIT
SCL 987654321 123
For comma nds such as the Clea r Address co mmand , the comm and i s ter-
minated at this point wi th a St op bit. The ED S pin will be asserted on this
rising clock edge if the OE bit was set to a one in the control byte. If the OE
bit is a zero and the previous command asserted it, then the EDS pin will be
released by the device at this point.
SDA
98765
0110
Start
Bit Control
Byte ACK
BIT
4
ID Byte ACK
BIT Stop
BIT
EDS
EDS
24LCS61/24LCS62
DS21226E-page 16 2004 Microchip Technology Inc.
APPENDIX A: REVISIO N HIST ORY
Revision D
Corrections to Section 1.0, Electrical Characteristics.
Revision E
Add “Obsolete Device” to document header.
2004 Microchip Technology Inc. DS21226E-page 17
24LCS61/24LCS62
ON-LINE SUPPORT
Microchip provides on-line support on the Microchip
World Wide Web site.
The web site is used b y Micr ochip as a me ans to mak e
files and information easily available to customers. To
view t he site, the user must have acce ss to the In ternet
and a web browser, such as Netscape® or Microsoft®
Internet Explorer. Files are also available for FTP
download from our FTP site.
Connecting to the Microchip Internet
Web S ite
The Microchip web site is available at the following
URL:
www.microchip.com
The file transfer site is available by using an FTP
service to connect to:
ftp://ftp.microchip.com
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
User's Guides, Articles and Sample Programs. A vari-
ety of Microchip specific business information is also
available, including listings of Microchip sales offices,
distributors and factory representatives. Other data
available for consideration is:
• Latest Microchip Press Releases
• Technical Support Section with Frequently Asked
Questions
• Design Tips
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• Mic rochip Consultant Pr ogra m Member List ing
• Links to other useful web sites related to
Microchip Products
• Confere nces for prod ucts, Dev elopment Systems,
technical information and more
• Listing of seminars and events
SYSTEMS INFORMATION AND
UPGRADE HOT LINE
The Systems Information and Upgrade Line provides
system users a listing of the latest versions of all of
Microchip's development systems software products.
Plus, this line provides information on how customers
can receive the mo st current upgrade kits. The Hot Line
Numbe rs are:
1-800-755-2345 for U.S. and most of Canada, and
1-480-792-7302 for the rest of the world.
042003
24LCS61/24LCS62
DS21226E-page 18 2004 Microchip Technology Inc.
READER RESPONSE
It is ou r intentio n to provide you with the b es t do cument a t ion po ss ib le to e ns ure suc c es sfu l u se of y ou r M icr oc hip pro d-
uct. If you wi sh to prov ide you r comment s on org anizatio n, clar ity, subj ect matte r , and ways i n which o ur docum entatio n
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DS21226E24LCS61/24LCS62
1. What are the be st fe atures of this d ocument?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
2004 Microchip Technology Inc. DS21226E-page 19
24LCS61/24LCS62
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and
recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Corporate Literature Center U.S. F AX: (480) 792-7277
3. The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Dat a Sheet (include Literature #) you are using.
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PART NO. X/XX XXX
PatternPackageTemperature
Range
Device
Device 24AA00 128 bit 1.8V I2C Serial EEPROM
24AA00T128 bit 1.8V K I2C Se ria l EEPROM (Tape and Reel)
24LC00 128 bit 2.5V I2C Serial EEPROM
24LC00T128 bit 2.5V K I2C Serial EEPROM (Tape and Reel)
24C00 128 bit 5.0V I2C Serial EEPROM
24C00T 128 bit 5.0V K I2C Serial EEPROM (Tape and Reel)
Temper atu re R ang e Blank = 0°C to +70°C
I=-40°C to +85°C
E= -40°C to +125°C
Packag e P = Plastic DIP (300 mi l Body ), 8-le ad
SN = Plastic SOIC (150 mil Body)
ST = TSSOP, 8-lead
OT = SOT-23, 5-lead
24LCS61/24LCS62
DS21226E-page 20 2004 Microchip Technology Inc.
NOTES:
2004 Microchip Technology Inc. DS21226E-page 21
Information contained in this publication regarding device
applications and the like is intended through sug gestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microc hip Technology Incorporated with respect
to the accuracy or use of such inf orm ation, or inf ringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical
components in life support systems is not authorized except
with express written approval by Microchip. No licenses are
conveyed, implicitly or otherwise, under any intellectual
property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICST ART ,
PRO MATE, PowerSmart, rfPIC, and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, MX DE V, MXLAB, PICMASTER, SEEV AL,
SmartSensor and The Embedded Control Solutions Company
are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, dsPICDEM,
dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,
FanSense, FlexROM, fuzzyLAB, In-Circuit Serial
Programming, ICSP, ICEPIC, Migratable Memory, MPASM,
MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net,
PICLAB, PICtail, PowerCal, PowerInfo, PowerMate,
PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial,
SmartTel and Total Endurance are trademarks of Microchip
Tec hnology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
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All other trademarks mentioned herein are property of their
respective companies.
© 2004, Microchip Technology Inco rporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that it s family of products is one of the most secure families of it s kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is c onstantly evolving. We a t Microchip are commit ted to continuously improving the code protect ion featur es of our
products. Attempts to break Microchip’ s code protection f eature may be a violati on of t he Digit al Millennium Copyright Act. If such act s
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2002 quality system certification for
its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in
October 2003. The Company’s quality system processes and
procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, micro peripherals, nonvolat ile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS21226E-page 22 2004 Microchip Technology Inc.
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