11640-843 - ON Semiconductor L.L.C.

FS6128-07

FS6128-07FS6128-07

FS6128-07

PLL Clock Generator IC with VCXO

PLL Clock Generator IC with VCXOPLL Clock Generator IC with VCXO

PLL Clock Generator IC with VCXO

1.0 Features

• Matches MK3727 center frequency characteristics

• Phase-locked loop (PLL) device synthesizes output

clock frequency from crystal oscillator or external ref-

erence clock

• On-chip tunable voltage-controlled crystal oscillator

(VCXO) allows precise system frequency tuning

• 3.3V supply voltage

• Very low phase noise PLL

• Use with “pullable” 14pF crystals – no external pad-

ding capacitors required

• Small circuit board footprint (8-pin 0.150″ SO IC)

• Custom frequency selections available - contact your

local AMI Sales Representative for more information

Figure 1: Pin Configuration

1 8

XIN

VDD

XTUNE

VSS

VDD

CLK

XOUT

FS6128-07

8-pin (0.150″) SOIC

2.0 Description

The FS6128 is a monolithic CMOS clock generator IC

designed to m inim ize cost a nd com ponen t count in digi tal

video/audio systems.

At the core of the FS6128 is circuitry that implements a

voltage-controlled crystal oscillator (VCXO) when an ex-

ternal resonator (nominally 13.5MHz) is attached. The

VCXO al lows devic e frequenc ies to b e prec isel y adjuste d

for use in systems that have frequency matching re-

quirements, such as digital satellite receivers.

A high-resolution phase-locked loop generates an output

clock (CLK) through a p ost-divi der. The C LK frequenc y is

ratiometrically derived from the VCXO frequency. The

locking of the CLK frequency to other system reference

frequencies can eliminate unpredictable artifacts in video

systems and reduce electromagnetic interference (EMI)

due to frequency harmonic stacking.

Table 1: Crystal / Output Frequencies

DEVICE fXIN (M Hz) CL K (MHz)

FS6128-07 13.500 27.000

NOTE: Contact AMI for custom PLL frequencies

Figure 2: Block Diagram

VCXO

FS6128-07

PLL

XOUT

XIN CLK

XTUNE

DIVIDER

FS6128-07

FS6128-07FS6128-07

FS6128-07

PLL Clock Generator IC with VCXO

PLL Clock Generator IC with VCXOPLL Clock Generator IC with VCXO

PLL Clock Generator IC with VCXO

Table 2: Pin Descriptions

Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DIU = Input with Internal Pull-Up; DID = Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input,

DO = Digital Output; P = Power/Ground; # = Active Low pin

PIN TYPE NAME DESCRIPTION

1 AI XIN VCXO Feedback

2 P VDD Power Supply (+3.3V)

3 AI XTUNE VCXO Tune

4 P VSS Ground

5 DO CLK Clock Output

6 P VDD Power Supply (+3.3V)

7 DO VSS Ground

8 A O XOUT VCXO Drive

3.0 Functional Bl ock Descripti on

3.1 Voltage-Controlled Crystal

Oscillator (VCXO)

The VCXO provides a tunable, low-jitter frequency refer-

ence for the rest of the FS6128 system components.

Loading capacitance for the crystal is internal to the

FS6128. No external components (other than the reso-

nator itself) are required for operation of the VCXO.

Continuous fine-tuning of the VCXO frequenc y is accom-

plished by varying the voltage on the XTUNE pin. The

value of this voltage controls the effective capacitance

presente d to the cryst al. T he ac tua l amount t hat t his loa d

capacitance change will alter the oscillator frequency de-

pends on the characteristics of the crystal as well as the

oscillator circuit itself.

It is important that the crystal load capacitance is speci-

fied correctly to “center” the tuning range. See Table 5.

A simple formula to obtain the “pulling” capability of a

crystal oscillator is:

()

()()

CCCC CCC

ppmf LL

1020

121

210

)( +×+× ×−×

=∆

where:

C0 = the shunt (or holder) capacitance of the crystal

C1 = the motional capacitance of the crystal

CL1 and CL2 = t he t wo ex tr emes (minimum and maxim um )

of the applied load capacitance presented by the

FS6128.

EXAMPLE: A crystal with the following parameters is

used: C1 = 0.025pF and C0 = 6pF. Using the minimum

and maximum CL1 = 10pF, and CL2 = 20pF, the tuning

range (peak-to-peak) is:

()

()()

ppm

f300

1062062 106

10200250 =

+×+× ×−×

=∆ .

3.2 Phase-Locked Loop (PLL)

The on-chip PLL is a standard frequency- and phase-

lock ed loop archi tec tur e. The PLL multip lies t he r ef er enc e

oscillator frequency to the desired output frequency by a

ratio of integers. The frequency multiplication is exact

with a zero synthesis error (unless otherwise specified).

FS6128-07

FS6128-07FS6128-07

FS6128-07

PLL Clock Generator IC with VCXO

PLL Clock Generator IC with VCXOPLL Clock Generator IC with VCXO

PLL Clock Generator IC with VCXO

4.0 Electrical Specifications

Table 3: Absolute Maximum Ratings

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress rating only, and functional operation of the device at

these or any other conditions above the operational limits noted in this specification is not implied. Exposure to maxi mum rating conditions for extended conditions may affect device performance,

functionality, and reliability.

PARAMETER SYMBOL MIN. MAX. UNITS

Supply Voltage (VSS = ground) VDD VSS-0.5 7 V

Input Voltage, dc VIVSS-0.5 VDD+0.5 V

Output Voltage, dc VOVSS-0.5 VDD+0.5 V

Input Clamp Current, dc (V I < 0 or VI > V DD)I

IK -50 50 mA

Output Clamp Current, dc (VI < 0 or VI > VDD)I

OK -50 50 mA

Storage Temperature Range (non-condensing) TS-65 150 °C

Ambient Temperature Range, Under Bias TA-55 125 °C

Junction Temperature TJ125 °C

Lead Temperature (soldering, 10s) 260 °C

Input Static Disc harge Voltage Protection (MIL-STD 883E, Method 3015.7) 2 kV

CAUTION: ELECTROSTATIC SENSITIVE DEVICE

Permanent damage res ulting in a loss of functi onality or performance may occur if this devic e is subjected to a high-energy elec-

trostatic discharge.

Table 4: Operating Conditions

PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS

Supply Voltage VDD 3.3V ± 10% 3.0 3.3 3.6 V

Ambient Operating Temperature Range TA070°C

Crystal Resonator Frequency fXTAL Fundam ental Mode 12 13.5 18 MHz

FS6128-07

FS6128-07FS6128-07

FS6128-07

PLL Clock Generator IC with VCXO

PLL Clock Generator IC with VCXOPLL Clock Generator IC with VCXO

PLL Clock Generator IC with VCXO

Table 5: DC Electrical Specifications

Unless otherwise stated, VDD = 3.3V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization

data and are not production tested to any specific limits. Where given, MIN and MAX characterization data are ± 3σ from typical. Negative currents indicate current flows out of the device.

PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS

Overall

Supply Current, Dynamic, with Loaded

Outputs IDD fXTAL = 13.5MHz; CL = 10pF, VDD = 3.6V 30 mA

Supply Current, Static IDD XIN = 0V , VDD = 3.6V 3 mA

Voltage Controlled Crystal Osci l lator (contact factory for approved crystal sources or other application assistance)

Crystal Loadi ng Capaci tance at Center

Tuning Voltage CL(xtal) Order crysta l for this capacitance (parallel

load) at desired center frequency 14 pF

Crystal Resonator Motional Capacit a nce C1Specified moti onal c apacitance of the

crystal will affect pullability (see text) 25 fF

XTUNE Effect i ve Range 03V

Synthesi zed Load Capacit ance Min. CL1 @V(XTUNE)=minimum value 10 pF

Synthesi zed Load Capacit ance Max. CL2 @V(XTUNE) =maximum value 20 pF

VCXO Tuning Range fXTAL = 13.5MHz; CL(xtal) = 14pF; C1(xtal) = 25fF

(peak-to-peak) 300 ppm

VCXO Tuning Characterist ic Note: positive change of XTUNE =

positive change of VCXO frequency 150 ppm/V

Crystal Dri ve Level RXTAL=20Ω; CL = 20pF 200 uW

Clock Output (CLK)

High-Level Output Sourc e Current * IOH VO = 2.0V -40 mA

Low-Level Output Sink Current * IOL VO = 0.4V 17 mA

zOH VO = 0.1VDD; output driving hi gh 25

Output Impedance * zOL VO = 0.1VDD; output driving l ow 25 Ω

Short Circuit S ource Current * IOSH VO = 0V; shorted for 30s, max. -55 mA

Short Circuit S i nk Current * IOSL VO = 3.3V; shorted for 30s, max. 55 mA

FS6128-07

FS6128-07FS6128-07

FS6128-07

PLL Clock Generator IC with VCXO

PLL Clock Generator IC with VCXOPLL Clock Generator IC with VCXO

PLL Clock Generator IC with VCXO

Table 6: AC Timing Specifications

Unless otherwise stated, VDD = 3.3V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization

data and are not production tested to any specific limits. Where given, MIN and MAX characterization data are ± 3σ from typical.

PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS

Overall

VCXO Stabilization Time * tVCXOSTB From power valid 10 ms

PLL Stabilization Time * tPLLSTB From V CXO stable 100 us

Synthesis Error (unless otherwise noted in Frequency Table) 0 ppm

Clock Output (CLK)

Duty Cycle * Ratio of high pulse width (as measured f rom rising

edge to next falling edge at VDD/2) to one clock period 45 55 %

Jitter, Period (peak-peak) * tj(∆P) From rising edge to next rising edge at VDD/2, CL =

10pF 200 ps

Jitter, Long Term (σy(τ)) * tj(LT) From 0-500µs at VDD/2, CL = 10pF

compared to ideal clock source 100 ps

Rise Time * trVDD = 3.3V; VO = 0.3V to 3.0V; CL = 10pF 1.7 ns

Fall Time * tfVDD = 3.3V; VO = 3.0V to 0.3V; CL = 10pF 1.7 ns

FS6128-07

FS6128-07FS6128-07

FS6128-07

PLL Clock Generator IC with VCXO

PLL Clock Generator IC with VCXOPLL Clock Generator IC with VCXO

PLL Clock Generator IC with VCXO

5.0 Package Information

Table 7: 8-pin SOIC (0.150") Package Dimensions

DIMENSIONS

INCHES MILLIMETERS

MIN. MAX. MIN. MAX.

A 0.061 0.068 1.55 1.73

A1 0.004 0.0098 0.102 0.249

A2 0.055 0.061 1.40 1.55

B 0.013 0.019 0.33 0.49

C 0.0075 0.0098 0.191 0.249

D 0.189 0.196 4.80 4.98

E 0.150 0.157 3.81 3.99

e 0.050 BSC 1.27 BSC

H 0.230 0.244 5.84 6.20

h 0.010 0.016 0.25 0.41

L 0.016 0.035 0.41 0.89

Θ0°8°0°8°

SEATING

PLANE

1ALL RADII:

0.005" TO 0.0 1"

BASE

PLANE

7° ty p.h x 45°

Table 8: 8-pin SOIC (0.150") Package Characteristics

PARAMETER SYMBOL CONDITIONS/DESCRIPTION TYP. UNITS

Thermal Impedance, Junction to Free-Air

8-pin 0.150” SOIC ΘJA Air flow = 0 m/s 110 °C/W

Corner lead 2.0

Lead Inductanc e, Self L11 Center lead 1.6 nH

Lead Inductanc e, Mutual L12 Any lead to any adjacent l ead 0.4 nH

Lead Capacitance, Bulk C11 Any lead to VSS 0.27 pF

FS6128-07

FS6128-07FS6128-07

FS6128-07

PLL Clock Generator IC with VCXO

PLL Clock Generator IC with VCXOPLL Clock Generator IC with VCXO

PLL Clock Generator IC with VCXO

6.0 Ordering Information

Table 9: Device Ordering Codes

ORDERING CODE DEVICE NUM BER PACKAGE TYPE OPERATING

TEMPERATURE R ANGE SHIPPING

CONFIGURATION

11640-843 FS6128-07 8-pin (0.150”) S OIC

(Small Outl i ne Package) 0°C to 70°C (Commercial) Tape and Reel

Devices sold by AMI are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. AMI

makes no warranty, express, statutory implied or by description, regarding the information set forth herein or regarding the freedom

of the described devices from patent infringement. AMI makes no warranty of merchantability or fitness for any purposes. AMI re-

serves the right to discontinue production and change specifications and prices at any time and without notice. AMI’s products are

intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental require-

ments, or high reliability applications, such as military, medical life-support or life-sustaining equipment, are specifically not rec om-

mended without additional processing by AMI for such applications.

American Microsystems, Inc., 2300 Buckskin Rd., Pocatello, ID 83201, (208) 233-4690, FAX (208) 234-6796,

WWW Address: http://www.amis.com E-mail: tgp@amis.com