National Semiconductor Programmable Array Logic (PAL) 20-Pin Small PAL Family General Description The 20-pin Small PAL family contains nine popular PAL ar- chitectures. The devices in the Small PAL family draw only 90 mA maximum supply current for standard power ver- sions, and as little as 45 mA for Series A2 as compared to 180 mA in the 20-pin Medium PAL devices. These devices offer speeds as fast as 25 ns maximum propagation delay. National Semiconductor's Schottky TTL process with titani- um tungsten fusible links provides high-speed user-pro- grammabla replacements for conventional SSI/MSI logic with significant chip-count reduction. Programmable logic devices provide convenient solutions for a wide variety of application-specific functions, including random logic, custom decoders, state machines, etc. By programming fusible links to configure AND/OR gate con- nections, the system designer can implement custom logic _ as convenient sum-of-products Boolean functions. System prototyping and design iterations can be performed quickly using these off-the-shelf praducts. A large variety of pro- gramming units and software makes design development and functional testing of PAL devices quick and easy. The Small PAL logic array has between 10 and 16 comple- mentary input pairs and up to 8 combinatorial outputs gener- ated by a single programmable AND-gate array with fixed OR-gate connections. The Small PAL family offers a variety of input/output combinations as shown in the Device Types table below. Security fuses can be programmed to prevent direct copying of proprietary logic patterns. Features @ As fast as 25 ns maximum propagation delay m User-programmable replacement for TTL logic @ Large variety of JEDEC-compatible programming equip- ment available a Fully supported by National PLANT development software w Security fuse prevents direct copying of logic patterns Device Types Device Dedicated Combinatorial Type inputs Outputs PAL10H8/PAL10L8 10 8 PAL12H6/PAL12L6 12 6 PAL14H4/PAL14L4 14 4 PAL16H2/PAL16L2 16 2 PAL16C1 16 1 Pair Speed/Power Versions Series Example Commercial Mititary tpep | 'cc | topo | 'cc Standard| PAL10H8 | 35ns | 90mA]| 45ns | 90mA A PALIOH8A | 25 ns* | 90 mA j 30 ns* | 90 mA A2 PALIOHBA2 | 35ns*|45mA! 45ns | 45mA Except PAL16C1A tpp = 30 ns Commercial, 35 ns Military. PAL16C1A2 tpp = 40 ns Commercial. Block DiagramPAL10H8 TL/L/9995-1 2-3 Apes TW IEWS Uld-0Z20-Pin Small PAL Family Standard Series (PAL10H8, PAL12H6, PAL14H4, PAL16H2, PAL10L8, PAL12L6, PAL14L4, PAL16L2, PAL16C1) Absolute Maximum Ratings (note 1) It Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specitications. Output Current (Io,) Storage Temperature Ambient Temperature +100 mA 65C to + 150C Supply Voltage (Vcc) (Note 2) 0.5 to +7.0V with Power Applied 65C to + 125C Input Voltage (Notes 2 and 3) ~1.5to +5.6V Junction Temperature ~65C to + 150C Off-State Output Voitage (Note 2) 1.5 to +5.5V Input Current (Note 2) ~30.0 mA to +5.0mA Recommended Operating Conditions Symbol Parameter Milltary Commercial Units Min Nom Max Min Nom Max Voc Supply Voltage 4.5 5 5.5 4.75 5 5.25 Vv TA Operating Free-Air Temperature 55 0 75 C Tc Operating Care Temperature 125 C Electrical Characteristics over Recommended Operating Conditions (Note 4) Symbol Parameter Test Conditions Min Typ Max | Units VIL Low Level Input Voltage (Note 5) 0.8 v Vie High Level Input Voltage (Note 5) 2 Vv Vic Input Clamp Voltage Voc = Min, | = 18mA -0.8 | -15 V IL Low Level Input Current Voc = Max, V; = 9.4V 0.02 | -0.25 | mA lH High Level Input Current Voc = Max, V; = 2.4V 25 pA If Maximum Input Current Voc = Max, V; = 5.5V 1 mA Vot Low Level Output Voltage Vcc = Min lo. = 8mA 0.3 0.5 Vv Vou High Level Output Voltage Voc = Min lon = 2mA MIL 24 29 Vv lon = 3.2 mA COM los Output Short-Circuit Current Voc = 5V, Vo = OV 30 | 70 | 130 | mA (Note 6) loc Supply Current Vcc = Max, Outputs Open 55 90 mA Note 1: Absolute maximum ratings are those values beyond which the device may be permanently damaged. Proper operation is not guaranteed outside the specified recommended operating conditions. Note 2: Some device pins may be raised above these limits during programming operations according to the applicable specification. Note 3: !t is recommended that precautions be taken to minimize electrostatic discharge when handling and testing this product. Pins 1 and #1 are connected directly to the sacurity fuses, and tha security fuses may be damaged preventing subsequent programming and verification operations. Note 4: All typical values are for Voc = 5.0V and Ta = 25C. Note 5: These are absolute voltages with respect to the ground pin on the device and include all overshoots due to system and/or tester noise. Do not attempt to test these values without suitable equipment. Note 6: To avoid Invalid readings in other parameter tests, it is praterable to conduct the los test last. To minimize internal heating, only one output should be shorted at a time with a maximum duration of 1.0 second each. Prolonged shorting of a high output may raise the chip temperature above normal and permanent damage may result. 2-4Standard Series (Pations, PAL12H6, PAL14H4, PAL16H2, PAL10L8, PAL12L6, PAL14L4, PAL16L2, PAL16C1) (Continued) Switching Characteristics over Recommended Operating Conditions Symbol Parameter Test Conditions Military : Commercial Units. Min Typ Max Min Typ Max tpp Input to Output CL = 50 pF 25 45 25 35 ns Test Load Test Waveform Sv Propagation Delay Ri INPUT OUTPUT MIL/COM IN-PHASE OUTPUT Cy Ro Ri = 560 R2 = 1.1K OUT OF PHASE OUTPUT ~ ~ TL/L/9998-2 TL/L/9995-3 Notes: Vr = 1.8V C_ includes probe and jig capacitance. In the examples above, the phase relationships between inputs and outputs have been chosen arbitrarily. Schematic of Inputs and Outputs EQUIVALENT INPUT TYPICAL OUTPUT Voc eo ec Sk NOM. 400 NOM. INPUT O- OUTPUT TL/L/9995-4 Ayiwey TWd ews Uld-0220-Pin Small PAL Family Series A (PAL10H8A, PAL12H6A, PAL14H4A, PALI6H2A, PAL1OL8A, PAL12L6A, PAL14L4A, PALI6L2A, PAL16C1A) Absolute Maximum Ratings (note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Oftice/Distributors for availability and specifications. Supply Voltage (Vcc) (Note 2) 0.5 to +7.0V Input Voltage (Notes 2 and 3) -1.5to +5.5V Off-State Output Voltage (Note 2) 1.5 to +5.5V Input Current (Note 2) 30.0 mA to +5.0 mA Output Current (Io,) Storage Temperature Ambient Temperature with Power Applied Junction Temperature Recommended Operating Conditions +100 mA 65C to + 150C 65C to + 125C 65C to + 150C Symbol Parameter Military Commercial Units Min Nom Max Min Nom Max Voo Supply Voltage 4.5 5 55 4.75 5 5.25 Vv Ta Operating Free-Air Temperature 55 0 75 i Tc Operating Case Temperature 125 C Electrical Characteristics over Recommended Operating Conditions (Note 4) Symbol Parameter Test Conditions Min Typ Max | Units VIL Low Level Input Voltage (Note 5) 0.8 Vv VIH High Level Input Voitage (Note 5) 2 Vv Vic Input Clamp Voltage Voc = Min, 1= 18mA 0.8 -1.5 Vv lit Low Level Input Current Voc = Max, V; = 0.4V 0.02 ) 0.25 |) mA liq High Level Input Current Voc = Max, Vj = 2.4V 25 BA 1 Maximum Input Current Voc = Max, V) = 5.5V 1 mA VoL Low Level Output Voltage Voc = Min lol = 8mA 0.3 0.5 Vv Vou High Level Output Voltage Voc = Min loo = 2mA MIL 24 29 V low = 3.2mA COM los Output Short-Circuit Current Voc = 5V, Vo = OV -30! 70 130 | ma (Note 6) lec Supply Current Voc = Max, Outputs Open 55 90 mA Note 1: Absolute maximum ratings are those values beyond which the device may be permanently damaged. Proper operation is net guaranteed outside the specified recommended operating conditions. Note 2: Same device pins may be raised above these limits during programming operations according to the applicable specification. Note 3: It is recommended that precautions be taken to minimize electrostatic discharge when handling and testing this product. Pins 1 and 11 are connected directly to the security fuses, and the security fuses may ba damaged preventing subsequent programming and verification operations. Note 4: All typical values are for Voc = 5.0V and Ta = 28C. Note 5: These are absolute voltages with respect fo the ground pin on the device and include all overshoots due to system and/or tester noise. Do not attempt to test these values without suitable equipment. Note 6: To avoid Invalid readings in other parameter tests, it is preferable to conduct the Iog test last. To minimize internal heating, only one output should be shorted at a time with a maximum duration of 1.0 second each. Prolonged shorting of a high output may raise the chip temperature above normal and permanent damage may result.Series A (PALIOHS8A, PAL12H6A, PAL14H4A, PAL16H2A, PAL10L8A, PAL12L6A, PAL14L4A, PALIGL2A, PAL16C1A) (Continued) Switching Characteristics over Recommended Operating Conditions Ames TW |TEWS Uldg-0Z Symbol Parameter Test Conditions Milltary Commercial Units Min Typ Max Min Typ Max tpp Input to Output CO. = 50 pF Except 16C1A 16 30 15 25 ns 16C1A 35 30 ns Test Load Test Waveform 5v Propagation Delay RI INPUT OUTPUT MIL/COM IN=PHASE at = 560 OUTPUT R2 = L TL R2 = 1.1K OUT OF PHASE OUTPUT ~ TL/L/9995-2 TL/L/9895-3 Notes: V7 = 1.5V C, includes probe and jig capacitance. In the examples above, the phase retationships between inputs and outputs have been chosen arbitrarily. Schematic of Inputs and Outputs EQUIVALENT INPUT TYPICAL OUTPUT Veco Voc S 5k0 NOM. 400. NOM. q q INPUT O =O OUTPUT x TL/L/9995-420-Pin Small PAL Family Series A2 (PAL10HBA2, PAL12H6A2, PAL14H4A2, PAL16H2A2, PAL10L8A2, PAL12L6A2, PAL14L4A2, PALI6GL2A2, PAL16C1A2) Absolute Maximum Ratings (note 1) if Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Output Current (lov) Storage Temperature Ambient Temperature +100 mA 65C to + 150C Supply Voltage (Vcc) (Note 2) 0.5 to +7.0V with Power Applied 65C to + 125C input Voltage (Notes 2 and 3) 1.5 to +5.5V Junction Temperature 65C to + 150C Off-State Output Voltage (Note 2) 1.5to + 5.5V Input Current (Note 2) 30.0 mA to + 5.0 mA Recommended Operating Conditions Symbol Parameter Mititary Commercial Units Min Nom Max Min Nom Max Voc Supply Voltage 4.5 5 5.5 4.75 5 5.25 Vv Ta Operating Free-Air Temperature 55 0 75 a Tc Operating Case Temperature 125 C Electrical Characteristics over Recommended Operating Conditions (Note 4) Symbol Parameter Teet Conditions Min Typ Max | Units VIL Low Level Input Voltage (Note 5) 0.8 Vv Vin High Level Input Voltage (Note 5) 2 V Vic Input Clamp Voltage Voc = Min,i = 18mA 0.8 1.5 Vv tie Low Level Input Current Voc = Max, V; = 0.4V 0.02 | -0.25| mA lin High Level Input Current Voc = Max, V| = 2.4V 25 pA \ Maximum Input Current Voc = Max, V, = 5.5V 1 mA VoL Low Level Output Voltage Voc = Min lo. = 8mA 0.3 0.5 Vv Vou High Level Output Voltage Veo = Min loo = 2mA MIL 24 29 Vv loH = 3.2mA COM los Output Short-Circuit Current Voc = 5V, Vo = OV 301 70 | 130 | mA (Note 6) loc Supply Current Voc = Max, Outputs Open 28 45 mA, Note 1: Absolute maximum ratings are those values beyond which the devica may be parmanently damaged. Proper operation is not guaranteed outside the specified recommended operating conditions. Note 2: Some device pins may be raised above these limits during programming operations according to the applicable specification. Note 3: It is recommended that precautions be taken to minimize electrostatic discharge when handling and testing this preduct. Pins 1 and 11 are connected directly to the security fuses, and the security fuses may be damaged preventing subsequent programming and verification operations. Note 4: All typical values are for Voc = 5.0V and Ta = 25C. Note 5: Thase are absolute voltages with respect to the ground pin on the device and include all overshoots due to system and/or tester noise. Do not attempt to test these values without suitable equipment. Note 6: To avoid invalid readings in other parameter tests, it is preferable to conduct the log test last. To minimize internal heating, onty one output should be shorted at a time with a maximum duration of 1.0 second each. Prolonged shorting of a high output may raise the chip temperature above nornal and permanent damage may result.Series A2 (PALt0H8A2, PAL12H6A2, PAL14H4A2, PAL16H2A2, PAL10L8A2, PAL12L6A2, PAL14L4A2, PALI6L2A2, PAL16C1A2) (Continued) Switching Characteristics over Recommended Operating Conditions Symbol Parameter Test Conditions Miltary Co t Units Min Typ Max Min Typ Max tpo Input to Output C, = 50 pF Except 16C1A2 25 45 25 36 ns 16C1A2 45 40 ns Test Load Test Waveform sy Propagation Delay INPUT Ri IN=PHASE QUTPUT MIL /COM OUTPUT R1 = S60 Gq L R2 R2 = 1.1K OUT OF RHASE = TL/L/9995-3 TL/L/9g95-2 Notes: Vr = 1.5V Schematic of Inputs and Outputs Vee 0 EQUIVALENT INPUT C_ includes probe and ji ig Capacitance. In the examples above, the phase relationships between inputs and outputs INPUT zt $s 5kO NOM. have been chosen arbitrarily. TYPICAL OUTPUT Voc 402 NOM. OUTPUT if iH TL/L/ 9995-4 Aljwe4 Wd HEWS Uld-0Z20-Pin Small PAL Family 20-Pin Small PAL Family Block DiagramsDIP Connections PAL10H8 C1) iC] 'E] LIe D] Ce] C] iP) E =} [e] = OL a] [J 7] [ey]. ] [J a] [+] a] [> a] [s] 'b] C #] [Je ~[] Le J Cd): 1 PIN I TL/L/9995-5 PAL14H4 OnE if) G b) G iT) GC T] iD) if) O ib) G iC) B ] [x] a] a} 7] [Jo a] [x] o a] [x] ] [Jo a} [J a} fe]: J oy: 0 1 L PIN | TL/L/9995~7 GND fio] 19 "1 PAL12H6 =] FJ ~ a] fo]: =] fv] > 7] [o] > ] fe] a] fe] > a) [J a) [ie] 6 ay fe): Cy): TL/L/9895-6 iL) ] E DJ iL) G 'f] iC) G iC] G if] & iL] B PAL16H2 LIC L] G L) G TIE L) L) if) G ib) G iP) GC oe a] Es] a] fe] 7) [e] =] [+] 0 =] [+] a) fe] a] fs) a} fe) my] fe}: TL/L#9995-8 2-1020-Pin Small PAL Family Biock DiagramsDIP Connections (continued PAL10L8 PAL12L6 Fe fC a] [2] Pe BY al fe oD a] [s]- he 9 E Tbs Ce EY [+] He [+] > +L J (J: 0] ble DY ] &): 0] At C16 a f] B Jt} fe 7] O)) Py | | PIN a _| TL/L/9895-9 TL/L/9995-19 if] 'E] C] if] LJ DJ 'C] PAL14L4 PAL16L2 ] [x] OC) 2] [s] Jb) al 0) a] ono} fle 7) bl) [+] > a] [4d a] [e] a] [4] 3] fs] =] fe]: Ion 3) [s] =) [: a) [3]: a) fe): J 0) TL/L/9995~11 TL/L/9995-12 2-11 Ajiwey Wd HEWS Uld-0Z20-Pin Small PAL Family 20-Pin Small PAL Family Block DiagramsDIP Connections (continuea) PAL16C1 'C] 'C] 'C] CT] T] [5] v [-]: [+]: [-): [+] fo [+] fo [J L) E [5]: L] B [) ef] B al DJ: | PIN | 20-Lead PLCC Connection Conversion Diagram* TL/L/9995-13 B-HOOG AHOAS TL/L19995-14 *Series-A parts are not available in this package. 2-12Functional Description The 20-pin Small PAL logic arrays consist of betwesn 10 and 16 complementary input lines and 16 product-term lines with a programmable fuse link at each intersection (up to 512 fuses). The family consists of nine device types with different numbers of combinatorial outputs. The 20-pin Small PAL Family Block Diagrams show the number of product terms allocated to each output for each device. All product terms allocated to each output connect into an OR- gate to produce the sum-of-preducts output logic function. An unprogrammed (intact) fuse establishes a connection between an input line (true or complement phase of an ar- ray input signal) and a product term; programming the fuse removes the connection. A product term is satisfied (logical- ly true) while all of the input lines connected to it (via unpro- grammed fuses) are in the high logic state. Therefore, if both the true and complement of at least one array input is left connected to a product line, that product term is always held in the low logic state (which is the state of all product terms in an unprogrammed device). Conversely, if all fuses on a product term were programmed, the product term and the resuiting logic function would be held in the high state. As with any TTL logic circuits, unused inputs to a PAL de- vice should be connected to ground, VoL, Vou, or resistive- ly to Voc. However, switching any input not connected to a product term or logic function has no effect on its output logic state. Security Fuse Security fuses are provided on all National PAL devices which, when programmed, inhibit any further programming Ordering Information r Ly PALIOH8 ANC *Series-A is not available in the V-package. or verifying operations. This feature prevents direct copying of proprietary logic patterns. The security fuses should be programmed only after programming and verifying all other device fuses. Design Development Support A variety of software tools and programming hardware is available to support the development of designs using PAL products. Typical software packages accept Boolean logic equations to define desired functions. Most are available to run on personal computers and generate JEDEC-compati- ble fuse maps. The industry-standard JEDEC format en- sures that the resulting fuse-map files can be down-loaded into a variety of programming equipment. Many seftware packages and programming units support a wide variety of programmable fogic products as well. The PLAN software package from National Semiconductor supports all pro- grammable logic products available from National and is ful- ly JEDEC-compatible. PLAN software also provides auto- matic device selection based on the designers Boolean logic equations. Detailed logic diagrams showing all JEDEC fuse-map ad- dresses for the 20-pin Small PAL family are provided for direct map editing and diagnostic purposes. Contact your local National Semiconductor sales representative or dis- tributor for a {ist of current software and programming sup- port tools available for these devices. Contact the National Semiconductor Programmable Device Support Department if detailed specifications of PAL programming algorithms are needed. Programmable Array Logic Family Number of Array Inputs Output Type: H =Active High L= Active Low C=Complementary R= Registered X =Exclusie-OR Registered P=Programmable Polarity Number of Outputs Spead/Power Version: No Symbol = 35 ns A =25ns A2=35ns, Haif Power ge Type: N=20=Pin Plastic DIP J=20-Pin Ceramic OIP V=20-Lead Plastic Chip Carrier Temperature Range: C =Commercial M= Military (=55C to #125C. 0C to #380q} TL/L/9995-15. Apuie4s Wd IEWS Uld-0220-Pin Small PAL Family Logic Diagram PAL10H8 DIP PIN NUMBERS PRODUCT LINE FIRST FUSE NUMBERS 1/3 7 13 Note: JEDEC Logic Array Fuse Number = Product Lina First Fuse Number + Input Line Number. 10 1 14 11 5 INPUT LINE NUMBERS 16 18 1 9 Ve DIP PIN NUMBERS o& 20 TL/L/9995- 16Logic Diagram PAL12H6 DIP PIN NUMBERS PRODUCT LINE FIRST FUSE NUMBERS 1/3 13 [15 Note: JEDEC Logic Array Fuse Number = Product Line First Fuse Number + Input Line Number. 46 8 10, 12. #14 1618 20 7|9 11 1719 [21 INPUT LINE = DIP PIN NUMBERS NUMBERS V Cr 20 TL/L/9995- 17 Aywie. Wd [TEWS Uld-0Z20-Pin Small PAL Family Logic Diagram PAL14H4 DIP PIN NUMBERS PRODUCT LINE FIRST FUSE NUMBERS O02 4 6 8 10 12 14 173 ]577 Y9ytt 13 15 9 10 4011 1 T1 1 113 15 Note: JEDEC Logic Array Fuse Number = Product Line First Fuse Number + Input Line Number. INPUT LINE NUMBERS 1618 2022 24.26 41 Yc 17)19 21 7 16 2 1719 2123 252? DIP PIN NUMBERS | o& 20 TFL/L/9995-18 2-16Logic Diagram PAL16H2 DIP PIN NUMBERS INPUT LINE PRODUCT LINE FIRST FUSE NUMBERS NUMBERS O 2 4 6 8 10 1214 1618 2022 2426 28 30 1ySy]5y7 79 yi 9 10 o12t 4161 8i10 ao1357911 13/15 [17419 [21]23 27 31 121141 161181 2 2 2 1345 1719 2123 2527 29 31 Note: JEDEC Logic Array Fuse Number = Product Line First Fuse Number + Input Line Number. DIP PIN NUMBERS Veg 20 TL/L/ 9995-19 2-17 Atwie4 Wd IBWS Uld-0220-Pin Small PAL Family Logic Diagram PAL10L8 DIP PIN NUMBERS PRODUCT LINE FIRST FUSE NUMBERS 0 4 6 100 12,14 1/3 7 (1 3 3 5 Note: JEDEC Logic Array Fuse Number = Producti Line First Fuse Number + Input Line Number. INPUT LINE DIP PIN NUMBERS NUMBERS 1618 17/19 Vec C 20 TL/L/9995~20 2-18Logie Diagram PAL12L6 DIP PIN NUMBERS INPUT LINE DIP PIN PRODUCT LINE FIRST FUSE NUMBERS NUMBERS NUMBERS 02 46 10 12. 14 1618 20 V 7 1101315 9 |2 Sp 20 9 10 Note: JEDEC Logic Array Fuse Number = Product Line First Fuse Number + input Line Number. TL/L/9995-21 2-19 Allied Wd NEWS Uld-0Z20-Pin Small PAL Family Logic Diagram PAL14L4 DIP PIN NUMBERS PRODUCT LINE FIRST FUSE NUMBERS 02 4 6 8 10 12 TJS {5 ]7 [9411 pts 1Of 12 11 13 14 15 1 15 INPUT LINE NUMBERS 8 48 2022 2426 e! Voc 7119 (21123 2527 16 2 1719 2123 2527 Note: JEDEC Logic Array Fuse Number = Product Line First Fuse Number + Input Line Number. DIP PIN NUMBERS | TL/L49995-22 2-20Logic Diagram PAL16L2 DIP PIN DIP PIN NUMBERS INPUT LINE NUMBERS PRODUCT LINE FIRST FUSE NUMBERS NUMBERS Vv O 2 4 6 8 10 1214 1618 2022 2426 28 30 cc TPS 7577 JO ytd 13piS p17 p19 21/23 7 [29)31 ct 9 10 o 24 4161 84101 121141 161 81 201221 241261 2 L 5 7 9 11 1315 1719 2123 2527 2931 TL/L/9995-23 Note: JEDEC Logic Array Fuse Number = Product Line First Fuse Number + Input Line Number. 2-21 A\wey Wed EWS Uld-0Z20-Pin Small PAL Family Logic Diagram PAL16C1 DIP PIN DIP PIN NUMBERS INPUT LINE NUMBERS PRODUCT LINE FIRST FUSE NUMBERS eed V, 02 4 6 8 10 1214 1618 2022 2426 28 30 c 1/3 [5] 7 [9 pit pists 19 421 7 31 c__20 9 O62) 4161 SH0l 1241161 2 10 LL 1395 7 911 1315 1719 2123 2527 29 31 TLL/999524 Note: JEDEC Logic Array Fuse Number = Product Line First Fuse Number + Input Line Number. 2-22