DC1594A-A - Linear Technology

LTC4219

4219fd

For more information www.linear.com/LTC4219

Typical applicaTion

FeaTures

applicaTions

DescripTion

5A Integrated

Hot Swap Controller

The LT C

4219 is an integrated solution for Hot Swap

applications that allows a board to be safely inserted and

removed from a live backplane. The part integrates a Hot

Swap controller, power MOSFET and current sense resis-

tor in a single package for small form factor applications.

The LTC4219 provides separate inrush current control

and a 10% accurate 5.6A current limit with foldback cur-

rent limiting. The current limit threshold can be adjusted

dynamically using an external pin. Additional features

include a current monitor output that amplifies the sense

resistor voltage for ground referenced current sensing

and a MOSFET temperature monitor output. Thermal limit

and power good monitoring are also provided. The power

good detection level and foldback current limit profile are

internally preset for 5V (LTC4219-5) and 12V (LTC4219-12)

applications.

L, LT , LT C , LT M , Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

12V, 5A Card Resident Application

n Small Footprint

n 33mΩ MOSFET with RSENSE

n Available in Preset 12V and 5V Versions

n Adjustable, 10% Accurate Current Limit

n Current and Temperature Monitor Outputs

n Overtemperature Protection

n Adjustable Current Limit Timer Before Fault

n Power Good and Fault Outputs

n Adjustable Inrush Current Control

n Available in 16-Lead 5mm × 3mm DFN Package

n RAID Systems

n Server I/O Cards

n Industrial

Power-Up Waveforms

12V

VOUT

12V

4219 TA01a

330µF

10k

VDD

TIMER

INTVCC

OUT

GND

F LT

ISET

IMON

LTC4219DHC-12

EN2

EN1

20k

1µF

*TVS: DIODES INC. SMAJ17A

10k

ADC

12V

200k200k

*VIN

10V/DIV

IIN

0.1A/DIV

VOUT

10V/DIV

20ms/DIV

CONTACT

BOUNCE

4219 TA01b

LTC4219

4219fd

For more information www.linear.com/LTC4219

SENSE

VDD

ISET

IMON

F LT

GATE

OUT

VDD

EN1

EN2

TIMER

INTVCC

GND

OUT

TOP VIEW

DHC PACKAGE

16-LEAD (5mm × 3mm) PLASTIC DFN

TJMAX = 125°C, qJA = 43°C/W

qJA = 43°C/W EXPOSED PAD SOLDERED, OTHERWISE qJA = 140°C/W

orDer inFormaTion

absoluTe maximum raTings

Supply Voltage (VDD) ................................. –0.3V to 28V

Input Voltages

FB, EN1, EN2 ...........................................–0.3V to 12V

TIMER ................................................... –0.3V to 3.5V

SENSE .............................VDD – 10V or – 0.3V to VDD

Output Voltages

ISET, IMON ................................................. –0.3V to 3V

PG, FLT ................................................... –0.3V to 35V

OUT ............................................ –0.3V to VDD + 0.3V

INTVCC .................................................. –0.3V to 3.5V

GATE (Note 3) ........................................ –0.3V to 33V

Operating Ambient Temperature Range

LTC4219C ................................................ 0°C to 70°C

LTC4219I .............................................–40°C to 85°C

Junction Temperature (Notes 4, 5) ........................ 125°C

Storage Temperature Range .................. –65°C to 150°C

(Notes 1, 2)

pin conFiguraTion

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC4219CDHC-12#PBF LTC4219CDHC-12#TRPBF 421912 16-Lead (5mm × 3mm) Plastic DFN 0°C to 70°C

LTC4219IDHC-12#PBF LTC4219IDHC-12#TRPBF 421912 16-Lead (5mm × 3mm) Plastic DFN –40°C to 85°C

LTC4219CDHC-5#PBF LTC4219CDHC-5#TRPBF 42195 16-Lead (5mm × 3mm) Plastic DFN 0°C to 70°C

LTC4219IDHC-5#PBF LTC4219IDHC-5#TRPBF 42195 16-Lead (5mm × 3mm) Plastic DFN –40°C to 85°C

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through

designated sales channels with #TRMPBF suffix.

LTC4219

4219fd

For more information www.linear.com/LTC4219

elecTrical characTerisTics

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. VDD = 12V unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

DC Characteristics

VDD Input Supply Range l2.9 15 V

IDD Input Supply Current MOSFET On, No Load l1.6 3 mA

VDD(UVL) Input Supply Undervoltage Lockout VDD Rising l2.65 2.73 2.85 V

VOUT(PGTH) Output Power Good Threshold LTC4219-12, VOUT Rising l10.2 10.5 10.8 V

LTC4219-5, VOUT Rising l4.2 4.35 4.5 V

DVOUT(PGHYST) Output Power Good Hysteresis LTC4219-12 l127 170 213 mV

LTC4219-5 l53 71 89 mV

IOUT OUT Leakage Current VOUT = VGATE = 0V, VDD = 15V l0 ±150 µA

VOUT = VGATE = 12V, LTC4219-12 l50 70 90 µA

VOUT = VGATE = 5V, LTC4219-5 l26 36 46.5 µA

dVGATE/dt GATE Pin Turn-On Ramp Rate l0.15 0.3 0.55 V/ms

RON MOSFET + Sense Resistor On Resistance l15 33 50 mW

ILIM(TH) Current Limit Threshold VFB = 1.23V l5.0 5.6 6.1 A

VFB = 0V l1.2 1.5 1.8 A

VFB = 1.23V, RSET = 20kΩ l2.6 2.9 3.3 A

Inputs

IIN EN1, EN2 Input Current VPIN = 1.2V l0 ±1 µA

RFB FB Input Resistance LTC4219-12

LTC4219-5

kΩ

VTH EN1, EN2, FB Threshold Voltage VPIN Rising l1.21 1.235 1.26 V

DVEN(HYST) EN1, EN2 Hysteresis l50 80 110 mV

DVFB(HYST) FB Power Good Hysteresis l10 20 30 mV

RISET ISET Internal Resistor l19 20 21 kW

LTC4219

4219fd

For more information www.linear.com/LTC4219

elecTrical characTerisTics

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: All currents into pins are positive, all voltages are referenced to

GND unless otherwise specified.

Note 3: An internal clamp limits the GATE pin to a maximum of 6.5V

above OUT. Driving this pin to voltages beyond the clamp may damage the

device.

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. VDD = 12V unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Outputs

VINTVCC INTVCC Output Voltage VDD = 5V, 15V

ILOAD = 0mA, –10mA

l2.8 3.1 3.2 V

VOL PG, F LT Output Low Voltage ISINK = 2mA l0.4 0.8 V

IOH PG, F LT Input Leakage Current VPIN = 30V l0 ±10 µA

VTIMER(H) TIMER High Threshold VTIMER Rising l1.2 1.235 1.28 V

VTIMER(L) TIMER Low Threshold VTIMER Falling l0.1 0.21 0.3 V

ITIMER(UP) TIMER Pull-Up Current VTIMER = 0V l–80 –100 –120 µA

ITIMER(DN) TIMER Pull-Down Current VTIMER = 1.2V l1.4 2 2.6 µA

ITIMER(RATIO) TIMER Current Ratio ITIMER(DN)/ITIMER(UP) l1.6 2 2.7 %

AIMON IMON Current Gain IOUT = 2.5A l18.5 20 21.5 µA/A

BWIMON IMON Bandwidth 250 kHz

IOFF(IMON) IMON Offset Current IOUT = 150mA l0 ±4.5 µA

IGATE(UP) Gate Pull-Up Current Gate Drive On, VGATE = VOUT = 12V l–19 –24 –29 µA

IGATE(DN) Gate Pull-Down Current Gate Drive Off, VGATE = 18V, VOUT = 12V l190 250 400 µA

IGATE(FST) Gate Fast Pull-Down Current Fast Turn Off, VGATE = 18V, VOUT = 12V 140 mA

AC Characteristics

tPHL(GATE) Input High (EN1, EN2) to Gate Low

Propagation Delay

VGATE < 16.5V Falling l8 10 µs

tPHL(ILIM) Short Circuit to Gate Low VFB = 0, Step ISENSE to 6A,

VGATE < 15V Falling

l1 5 µs

tD(ON) Turn-On Delay Step VEN1 and VEN2 to 0V, VGATE > 13V l50 100 150 ms

tD(FAULT) EN1 High to Clear Fault Latch Delay 5 µs

tD(CB) Circuit Breaker Filter Delay Time (Internal) VFB = 0V, Step ISENSE to 3A l1.5 2 2.7 ms

Note 4: This IC includes overtemperature protection that is intended

to protect the device during momentary overload conditions. Junction

temperature will exceed 125°C when overtemperature protection is active.

Continuous operation above the specified maximum operating junction

temperature may impair device reliability.

Note 5: TJ is calculated from the ambient temperature, TA, and power

dissipation, PD, according to the formula:

TJ = TA + (PD • 43°C/W)

LTC4219

4219fd

For more information www.linear.com/LTC4219

IDD vs VDD

INTVCC Load Regulation

EN1, EN2 Low Threshold

vs Temperature

VDD (V)

1.0

(mA)

1.2

1.4

1.6

1.8

2.0

5 10 15 20

4219 G01

25 30

–40°C

25°C

85°C

ILOAD (mA)

0.5

1.5

1.0

INTVCC (V)

3.5

2.0

2.5

3.0

4219 G02

–14–12–10–8–6–4–2

TEMPERATURE (°C)

–50

UV LOW-HIGH THRESHOLD (V)

1.234

1.232

1.230

1.228

1.226

–25 0 25

4219 G03

50 75 100

Typical perFormance characTerisTics

TA = 25°C, VDD = 12V unless otherwise noted.

EN1, EN2 Hysteresis

vs Temperature

Timer Pull-Up Current

vs Temperature

Current Limit Delay

(tPHL(ILIM) vs Overdrive)

Current Limit Threshold Foldback,

LTC4219-5

Current Limit Adjustment

(IOUT vs RSET)

TEMPERATURE (°C)

–50

UV HYSTERESIS (V)

0.10

0.08

0.06

0.04

–25 0 25

4219 G04

50 75 100

TEMPERATURE (°C)

–50

TIMER PULL-UP CURRENT (µA)

–110

–105

–100

–95

–90

–25 0 25

4219 G05

50 75 100

OUTPUT CURRENT (A)

CURRENT PROPAGATION DELAY (µs)

1000

100

0.1

4219 G06

20 30

VOUT (V)

CURRENT LIMIT VALUE (A)

1234

4219 G07

RSET (Ω)

CURRENT LIMIT THRESHOLD VALUE (A)

10k 100k

4219 G09

1M 10M

Current Limit Threshold Foldback,

LTC4219-12

VOUT (V)

CURRENT LIMIT VALUE (A)

369

4219 G08

LTC4219

4219fd

For more information www.linear.com/LTC4219

Typical perFormance characTerisTics

RISET vs Temperature

TA = 25°C, VDD = 12V unless otherwise noted.

TEMPERATURE (°C)

–50

ISET RESISTOR (kΩ)

–25 0 25

4219 G10

50 75 100

RON vs VDD and Temperature

MOSFET SOA Curve

TEMPERATURE (°C)

–50

–25 0 25

4219 G11

50 75 100

RON (mΩ)

VDD = 5V, 12V

VDS (V)

0.1

0.01

ID (A)

0.1

1 10 100

4219 G12

TA = 25°C

MULTIPLE PULSE

DUTY CYCLE = 0.2

10s

100ms

10ms

1ms

IMON vs Temperature and VDD

PG, F LT VOUT Low vs ILOAD

GATE Pull-Up Current

vs Temperature

ILOAD (mA)

PG, FLT V

OUT

LOW (V)

2468

4219 G13

10 12

FLT

TEMPERATURE (°C)

–50

105

100

–25 0 25

4219 G14

50 75 100

IMON (µA)

VDD = 5V, 12V

ILOAD = 5A

TEMPERATURE (°C)

–50

IGATE PULL-UP (µA)

–26.0

–25.5

–25.0

–24.5

–24.0

–25 0 25

4219 G15

50 75 100

LTC4219

4219fd

For more information www.linear.com/LTC4219

Typical perFormance characTerisTics

Gate Drive vs

Gate Pull-Up Current

TA = 25°C, VDD = 12V unless otherwise noted.

Gate Drive vs VDD

Gate Drive vs Temperature

VISET vs Temperature

IGATE (µA)

∆VGATE (VGATE – VOUT) (V)

–5 –10 –15 –20

4219 G16

–25 –30

VDD (V)

6.2

6.0

5.8

5.6

5.4

5.2

5 10 15

4219 G17

20 25 30

∆VGATE (VGATE – VOUT) (V)

TEMPERATURE (°C)

–50

6.15

6.14

6.13

6.12

6.11

6.10

–25 0 25

4219 G18

50 75 100

∆VGATE (VGATE – VOUT) (V)

TEMPERATURE (°C)

–50

0.9

0.8

0.7

0.6

0.5

0.4

0.3

–25 0 25

4219 G19

50 75 150125100

VISET (V)

LTC4219

4219fd

For more information www.linear.com/LTC4219

pin FuncTions

EN1: Inverted Enable 1 Input. Ground this pin to enable

the MOSFET to turn on after 100ms debounce delay. If

the voltage at this pin rises above 1.235V for longer than

10µs a turn-off command is detected, the overcurrent

fault is cleared and the MOSFET gate is discharged with

a 250µA current. Bringing this pin below 1.15V and EN2

low for 100ms begins GATE pin ramping.

EN2: Inverted Enable 2 Input. Ground this pin to enable

the MOSFET to turn on after 100ms debounce delay. If the

voltage at this pin rises above 1.235V for longer than 10µs

a turn-off command is detected and the MOSFET gate is

discharged with a 250µA current. Bringing this pin below

1.15V and EN1 low for 100ms begins GATE pin ramping.

Exposed Pad: SENSE.

FB: Foldback and Power Good Input. The FB pin is driven

from an internal resistive divider from OUT for both the

LTC4219-12 and LTC4219-5. These versions preset 12V

and 5V foldback and power good levels. If the OUT volt-

age falls below 2.5V (LTC4219-5) or 6V (LTC4219-12)

the current limit is reduced using a foldback profile (see

the Typical Performance Characteristics section). If the

FB voltage falls below 1.21V the PG pin will pull high to

indicate the power is bad.

F LT : Overcurrent Fault Indicator. Open-drain output pulls

low when an overcurrent fault has occurred and the circuit

breaker trips.

GATE: Gate Drive for Internal N-channel MOSFET. An inter-

nal 24µA current source charges the gate of the N-channel

MOSFET. At start-up the GATE pin ramps up at a 0.3V/ms

rate determined by internal circuitry. When either EN1 or

EN2 pin goes high, a 250µA pull-down current turns the

MOSFET off. During a short-circuit or undervoltage lockout

condition, a 140mA pull-down current source between

GATE and OUT is activated.

GND: Device Ground.

IMON: Current Monitor Output. The current in the internal

MOSFET switch is divided by 50,000 and sourced from this

pin. Placing a 20k resistor from this pin to GND creates a

0V to 2V voltage swing when current ranges from 0A to 5A.

INTVCC: Internal 3V Supply Decoupling Output. This pin

must have a 1µF or larger bypass capacitor. Overloading

this pin can disrupt internal operation.

ISET: Current Limit Adjustment Pin. For a 5.6A current limit

value open this pin. This pin is driven by a 20k resistor

in series with a voltage source. The pin voltage is used

to generate the current limit threshold. The internal 20k

resistor (RISET) and an external resistor (RSET) between

ISET and ground create an attenuator that lowers the cur-

rent limit value. Due to circuit tolerance RSET should not be

less than 2k. In order to match the temperature variation

of the sense resistor, the voltage on this pin increases at

the same rate as the sense resistance increases. Therefore

the voltage at ISET pin is proportional to temperature of

the MOSFET switch.

OUT: Output of Internal MOSFET Switch. Connect this pin

directly to the load. An internal resistive divider is con-

nected to this pin to drive the FB pin.

PG: Power Good Indicator. Open-drain output releases

the PG pin to go high when the FB pin drops below 1.21V

indicating the power is bad. If the FB pin rises above 1.23V

and the GATE to OUT voltage exceeds 4.2V, the open-drain

output pulls low indicating power is good.

SENSE: Current Sense Node and MOSFET Drain. The cur-

rent limit circuit controls the GATE pin to limit the sense

voltage between the VDD and SENSE pins to 42mV (5.6A)

or less depending on the voltage at the FB pin. The exposed

pad on the DHC package is connected to SENSE and must

be soldered to an electrically isolated printed circuit board

trace to properly transfer the heat out of the package.

TIMER: Timer Input. Connect a capacitor between this pin

and ground to set a 12ms/µF duration for current limit

before the switch is turned off. If the EN1 pin is toggled

first high then low while the MOSFET switch is off, the

switch will turn on again following a cooldown time of

518ms/µF duration. Tie this pin to INTVCC for a fixed 2ms

overcurrent delay.

VDD: Supply Voltage and Current Sense Input. This pin

has an undervoltage lockout threshold of 2.73V.

LTC4219

4219fd

For more information www.linear.com/LTC4219

FuncTional Diagram

4219 BD

VDD

EN1

OUT

GND

IMON

INTVCC

100µA

TIMER

F LT

–ISET

RISET

20k

GATE

6.15V

SENSE

(EXPOSED PAD)

CLAMP

0.6V POSITIVE

TEMPERATURE

COEFFICIENT

REFERENCE

INTERNAL 25mΩ

MOSFET

INTERNAL 7.5mΩ

SENSE RESISTOR

CHARGE

PUMP

AND GATE

DRIVER

f = 2MHz

OUT

3.1V

GEN

LOGIC

INRUSHCS

0.3V/ms

FOLDBACK

0.6V

2.65V

1.235V

+–

–

1.235V

–

EN1

0.21V

–

TM1

1.235V –

TM2

1.235V

–

EN2

VDD

2.73V +

–

UVLO1

EN2

2µA

–

UVLO2

OUT

* 100k (LTC4219-5)

150k (LTC4219-12)

** 40k (LTC4219-5)

20k (LTC4219-12)

LTC4219

4219fd

For more information www.linear.com/LTC4219

operaTion

The Functional Diagram displays the main circuits of the

device. The LTC4219 is designed to turn a board’s supply

voltage on and off in a controlled manner allowing the board

to be safely inserted and removed from a live backplane.

The LTC4219 includes a 25mW MOSFET and a 7.5mW

current sense resistor. During normal operation, the charge

pump and gate driver turn on the pass MOSFET’s gate to

provide power to the load. The inrush current control is

accomplished by the INRUSH circuit. This circuit limits

the GATE ramp rate to 0.3V/ms and hence controls the

voltage ramp rate of the output capacitor.

The current sense (CS) amplifier monitors the load current

using the voltage sensed across the current sense resistor.

The CS amplifier limits the current in the load by reduc-

ing the GATE-to-OUT voltage in an active control loop. It

is simple to adjust the current limit threshold using the

current limit adjustment (ISET) pin. This allows a different

threshold during other times such as start-up.

A short circuit on the output to ground causes significant

power dissipation during active current limiting. To limit

this power, the foldback amplifier reduces the current

limit value from 5.6A to 1.5A in a linear manner as the

FB pin drops below 0.6V (see the Typical Performance

Characteristics section).

If an overcurrent condition persists, the TIMER pin ramps

up with a 100µA current source until the pin voltage

exceeds 1.235V (comparator TM2). This indicates to the

logic that it is time to turn off the pass MOSFET to prevent

overheating. At this point the TIMER pin ramps down us-

ing the 2µA current source until the voltage drops below

0.21V (Comparator TM1) which tells the logic to start an

internal 100ms timer. After this delay, the pass transistor

has cooled and it is safe to turn it on again. It is suitable

for many applications to use an internal 2ms overcurrent

timer with a 100ms cooldown period. Tying the TIMER

pin to INTVCC sets this default timing.

The fixed 5V and 12V versions, LTC4219-5 and LTC4219-12,

use an internal divider from OUT to drive the FB pin. This

divider also sets the foldback current limit profile. The

output voltage is monitored using the FB pin and the PG

comparator to determine if the power is available for the

load. The power good condition is signaled by the PG pin

using an open-drain pull-down transistor.

The Functional Diagram also shows the monitoring blocks

of the LTC4219. The two comparators on the left side in-

clude the EN1 and EN2 comparators. These comparators

determine if the enable inputs are valid prior to turning on

the MOSFET. But first the undervoltage lockout circuits

UVLO1 and UVLO2 must validate the input supply and

the internally generated 3.1V supply (INTVCC) and gener-

ate the power up initialization to the logic circuits. If the

external conditions remain valid for 100ms the MOSFET

is allowed to turn on.

Other features include MOSFET current and temperature

monitoring. The current monitor (CM) outputs a current

proportional to the sense resistor current. This current can

drive an external resistor or other circuits for monitoring

purposes. A voltage proportional to the MOSFET tempera-

ture is output to the ISET pin. The MOSFET is protected by

a thermal shutdown circuit.

LTC4219

4219fd

For more information www.linear.com/LTC4219

applicaTions inFormaTion

This gate slope is designed to charge up a 1000µF capaci-

tor to 12V in 40ms, with an inrush current of 300mA. This

allows the inrush current to stay under the current limit

threshold (1.5A) for capacitors less than 1000µF. Included

in the Typical Performance Characteristics section is a

graph of the Safe Operating Area for the MOSFET. It is

evident from this graph that the power dissipation at 12V,

300mA for 40ms is in the safe region.

Adding the RGATE, CGATE and CCOMP network on the GATE

pin will lower the inrush current below the default value

set by the inrush circuit. The GATE is then charged with

a 24µA current source. The voltage at the GATE pin rises

with a slope equal to 24µA/CGATE and the supply inrush

current is set at:

IINRUSH =

GATE

•24µA

Figure 2. Supply Turn-On

Figure 1. 2A, 12V Card Resident Application with Auto-Retry

The typical LTC4219 application is in a high availability

system that uses a positive voltage supply to distribute

power to individual cards. A complete application circuit

is shown in Figure 1. External component selection is

discussed in detail in the following sections.

Turn-On Sequence

Several conditions must be present before the internal

pass MOSFET can be turned on. First the supply VDD must

exceed its undervoltage lockout level. Next the internally

generated supply INTVCC must cross its 2.65V under-

voltage threshold. This generates a 25µs power-on-reset

pulse which clears the fault register and initializes internal

latches. Finally, the enable inputs EN1 and EN2 both must

be below the 1.15V threshold. All of these conditions must

be satisfied for the duration of 100ms to ensure that any

contact bounce during the insertion has ended.

The MOSFET is turned on by charging up the GATE with

a charge pump generated 24µA current source whose

value is adjusted by shunting a portion of the pull-up cur-

rent to ground. The charging current is controlled by the

INRUSH circuit that maintains a constant slope of GATE

voltage versus time (Figure 2). The voltage at the GATE

pin rises with a slope of 0.3[V/ms] and the supply inrush

current is set at:

IINRUSH = CL • 0.3[V/ms]

ADC

1µF

12V

12V PG = 10.5V

4219 F01

10k

BSS84

0.1µF

330µF

CCOMP

3.3nF

VOUT

12V

VDD

EN1

OUT

GND

IMON

RSET

20k

RMON

20k

ISET

CGATE

0.1µF

RGATE

100k

GATE

LTC4219DHC-12

EN2

INTVCC

TIMER

F LT

*TVS Z1: DIODES INC. SMAJ17A

200k

R4 10k

Z1*

t1 t2

SLOPE = 0.3[V/ms]

GATE

OUT

VDD + 6.15V

VDD

4219 F02

LTC4219

4219fd

For more information www.linear.com/LTC4219

applicaTions inFormaTion

If VDD drops below 2.65V for greater than 5µs or INTVCC

drops below 2.5V for greater than 1µs, a fast shutdown

of the switch is initiated. The GATE is pulled down with a

140mA current to the OUT pin.

Overcurrent Fault

The LTC4219 features an adjustable current limit with

foldback that protects against short circuits and excessive

load current. To prevent excessive power dissipation in the

switch during active current limit, the available current is

reduced as a function of the output voltage sensed by the

FB pin. A graph in the Typical Performance Characteristics

curves shows the current limit versus FB voltage.

An overcurrent fault occurs when the current limit circuitry

has been engaged for longer than the time-out delay set

by the TIMER. Current limiting begins when the MOSFET

current reaches 1.5A to 5.6A (depending on the foldback).

The GATE pin is then brought down with a 140mA GATE-

to-OUT current. The voltage on the GATE is regulated in

order to limit the current to less than 5.6A. At this point,

a circuit breaker time delay starts by charging the external

timing capacitor with a 100µA pull-up current from the

TIMER pin. If the TIMER pin reaches its 1.235V threshold,

the internal switch turns off (with a 250µA current from

GATE to ground). Included in the Typical Performance

Characteristics curves is a graph of the Safe Operating

Area for the MOSFET. From this graph one can determine

the MOSFET’s maximum time in current limit for a given

output power.

Tying the TIMER pin to INTVCC will force the part to use

the internally generated (circuit breaker) delay of 2ms.

In either case the F LT pin is pulled low to indicate an

overcurrent fault has turned off the pass MOSFET. For a

given circuit breaker time delay, the equation for setting

the timing capacitor’s value is as follows:

CT = tCB • 0.083[µF/ms]

After the switch is turned off, the TIMER pin begins

discharging the timing capacitor with a 2µA pull-down

current. When the TIMER pin reaches its 0.21V threshold,

an internal 100ms timer is started. After the 100ms delay,

the switch is allowed to turn on again if the overcurrent

fault latch has been cleared. Bringing the EN1 pin above

When the GATE voltage reaches the MOSFET threshold

voltage, the switch begins to turn on and the OUT volt-

age follows the GATE voltage as it increases. Once OUT

reaches VDD, the GATE will ramp up until clamped by the

6.15V Zener between GATE and OUT.

As the OUT voltage rises, so will the FB pin which is moni-

toring it. Once the FB pin crosses its 1.235V threshold and

the GATE to OUT voltage exceeds 4.2V, the PG pin pulls

low indicating that the power is good.

Parasitic MOSFET Oscillation

When the N-channel MOSFET ramps up the output dur-

ing power-up it operates as a source follower. The source

follower configuration may self-oscillate in the range of

25kHz to 300kHz when the load capacitance is less than

10µF, especially if the wiring inductance from the supply

to the VDD pin is greater than 3µH. The possibility of oscil-

lation will increase as the load current (during power-up)

increases. There are two ways to prevent this type of

oscillation. The simplest way is to avoid load capacitances

below 10µF. For wiring inductance larger than 20µH, the

minimum load capacitance may extend to 100µF. A second

choice is to connect an external gate capacitor CP >1.5nF

as shown in Figure 3.

Turn-Off Sequence

The switch can be turned off by a variety of conditions. A

normal turn-off is initiated by either the EN1 or EN2 pins

going above their 1.235V threshold. Additionally, several

fault conditions will turn off the switch. These include over-

current circuit breaker (SENSE pin) or overtemperature.

Normally the switch is turned off with a 250µA current

pulling down the GATE pin to ground. With the switch

turned off, the OUT voltage drops which pulls the FB pin

below its threshold. PG then goes high to indicate output

power is no longer good.

Figure 3. Compensation for Small CLOAD

4219 F03

LTC4219

OPTIONAL

RC TO LOWER

INRUSH CURRENT

GATE

2.2nF

LTC4219

4219fd

For more information www.linear.com/LTC4219

applicaTions inFormaTion

1.235V for a minimum of 5µs and then low will clear the

fault latch. If the TIMER pin is tied to INTVCC then the

switch is allowed to turn on again (after an internal 100ms

delay), if the overcurrent fault latch is cleared.

Tying the P-channel MOSFET Q1 to the EN1 pin allows

the part to self-clear the fault and turn the MOSFET on as

soon as the TIMER pin has ramped below 0.21V. In the

auto-retry mode the LTC4219 repeatedly tries to turn on

after an overcurrent at a period determined by the capaci-

tor on the TIMER pin. The auto-retry mode also functions

when the TIMER pin is tied to INTVCC.

The waveform in Figure 4 shows how the output latches

off following a short-circuit. The current in the MOSFET

is 1.4A as the timer ramps up.

The overall current limit threshold precision is reduced to

±12% when using a 20k resistor to halve the threshold.

Using a switch (connected to ground) in series with RSET

allows the active current limit to change only when the

switch is closed. This feature can be used to program a

reduced running current while the maximum available

current limit is used at startup.

Monitor MOSFET Temperature

The voltage at the ISET pin increases linearly with increas-

ing temperature. The temperature profile of the ISET pin is

shown in the Typical Performance Characteristics section.

Using a comparator or ADC to measure the ISET voltage

provides an indicator of the MOSFET temperature.

The ISET voltage follows the formula:

ISET =

SET

RSET +RISET

•(T +273°C) •2.093[mV/°C]

The MOSFET temperature is calculated using RISET of 20k.

SET +

20k) •V

ISET

SET

•2.093[mV/°C] −273°C

when RSET is not present, T becomes:

ISET

2.093[mV/°C] −273°C

There is an overtemperature circuit in the LTC4219 that

monitors an internal voltage similar to the ISET pin voltage.

When the die temperature exceeds 145°C the circuit turns

off the MOSFET until the temperature drops to 125°C.

Monitor MOSFET Current

The current in the MOSFET passes through an internal

7.5mΩ sense resistor. The voltage on the sense resistor is

converted to a current that is sourced out of the IMON pin.

The gain of ISENSE amplifier is 20µA/A referenced from the

MOSFET current. This output current can be converted to

a voltage using an external resistor to drive a comparator

or ADC. The voltage compliance for the IMON pin is from

0V to INTVCC – 0.7V.

Figure 4. Short-Circuit Waveform

AVGATE

10V/DIV

IOUT

2A/DIV

VOUT

10V/DIV

TIMER

2V/DIV

1ms/DIV 4219 F04

Current Limit Adjustment

The default value of the active current limit is 5.6A. The

current limit threshold can be adjusted lower by placing

a resistor between the ISET pin and ground. As shown in

the Functional Block Diagram the voltage at the ISET pin

(via the clamp circuit) sets the CS amplifier’s built-in offset

voltage. This offset voltage directly determines the active

current limit value. With the ISET pin open, the voltage at

the ISET pin is determined by a positive temperature co-

efficient reference. This voltage is set to 0.618V at room

temperature which corresponds to a 5.6A current limit at

room temperature.

An external resistor RSET placed between the ISET pin and

ground forms a resistive divider with the internal 20k RISET

sourcing resistor. The divider acts to lower the voltage at

the ISET pin and therefore lower the current limit threshold.

LTC4219

4219fd

For more information www.linear.com/LTC4219

applicaTions inFormaTion

A microcontroller with a built-in comparator can build a

simple integrating single-slope ADC by resetting a capaci-

tor that is charged with this current. When the capacitor

voltage trips the comparator and the capacitor is reset, a

timer is started. The time between resets will indicate the

MOSFET current.

Power Good Indication

In addition to setting the foldback current limit threshold,

the FB pin is used to determine a power good condition.

The LTC4219-12 and LTC4219-5 use an internal resis-

tive divider on the OUT pin to drive the FB pin. On the

LTC4219-12, the PG comparator indicates logic high when

OUT pin rises above 10.5V. If the OUT pin subsequently

falls below 10.3V, the comparator toggles low. On the

LTC4219-5 the PG comparator drives high when the OUT

pin rises above 4.35V and low when OUT falls below 4.27V.

Once the PG comparator is high, the GATE pin voltage is

monitored with respect to the OUT pin. Once the GATE

minus OUT voltage exceeds 4.2V, the PG pin goes low.

This indicates to the system that it is safe to load the OUT

pin while the MOSFET is completely turned “on”. The PG

pin goes high when the GATE is commanded off (using

the EN1, EN2 or SENSE pins) or when the PG comparator

drives low.

Design Example

Consider the following design example (Figure 5): VIN = 12V,

IMAX = 5A. IINRUSH = 100mA, CL = 330µF, VPGTHRESHOLD

= 10.5V.

The inrush current is defined by the current required to

charge the output capacitor using the fixed 0.3V/ms GATE

charge up rate. The inrush current is defined as:

INRUSH =

•0.3[V/ms]

330µF •0.3[V/ms]

100mA

As mentioned previously, the charge up time is the out-

put voltage (12V) divided by the output rate of 0.3V/ms

resulting in 40ms. The peak power dissipation of 12V at

100mA (or 1.2W) is within the SOA of the pass MOSFET

for 40ms (see MOSFET SOA curve in the Typical Perfor-

mance Characteristics section).

Next the power dissipated in the MOSFET during overcur-

rent must be limited. The active current limit uses a timer

to prevent excessive energy dissipation in the MOSFET.

The worst-case power dissipation occurs when the voltage

versus current profile of the foldback current limit is at the

maximum. This occurs when the current is 6.1A and the

voltage is one half of the VIN or 6V. See the Current Limit

Threshold Foldback vs FB Voltage in the Typical Perfor-

mance Characteristics section to view this profile. In order

to survive 36W, the MOSFET SOA dictates a maximum

time of 10ms (see SOA graph). Use the internal 2ms timer

invoked by tying the TIMER pin to INTVCC.

Figure 5. 5A, 12V Card Resident Application

ADC

1µF

12V VOUT

12V

RMON

20k

4219 F05

10k

PG = 10.5V

12V

10k

330µF

VDD OUT

GATE

GND

IMON

ISET

LTC4219DHC-12

INTVCC

TIMER

EN1

EN2

F LT

Z1* R3

200k

*TVS Z1: DIODES INC. SMAJ17A

LTC4219

4219fd

For more information www.linear.com/LTC4219

applicaTions inFormaTion

The power good threshold using the internal resistive

divider on the FB pin matches the 10.5V requirement.

The final schematic in Figure 5 results in very few external

components. The pull-up resistors, R1 and R4, connect

to the F LT and PG pins while the 20k (RMON) converts the

IMON current to a voltage at a ratio:

IMON =

20 µA/A

[ ]

•20k •I

OUT =

0.4 V/A

[ ]

•I

In addition there is a 1µF bypass (C1) on the INTVCC pin.

Layout Considerations

In Hot Swap applications where load currents can be 5A,

narrow PCB tracks exhibit more resistance than wider tracks

and operate at elevated temperatures. The minimum trace

width for 1oz copper foil is 0.02" per amp to make sure

the trace stays at a reasonable temperature. Using 0.03"

per amp or wider is recommended. Note that 1oz copper

exhibits a sheet resistance of about 0.5mW/square. Small

resistances add up quickly in high current applications.

There are two VDD pins on opposite sides of the package

that connect to the sense resistor and MOSFET. The PCB

layout should be balanced and symmetrical to each VDD

pin to balance current in the MOSFET bond wires. Figure 6

shows a recommended layout for the LTC4219.

Although the MOSFET is self protected from overtem-

perature, it is recommended to solder the backside of the

package to a copper trace to provide a good heat sink.

Note that the backside is connected to the SENSE pin and

cannot be soldered to the ground plane. During normal

loads the power dissipated in the package is as high as

1.9W. A 10mm × 10mm area of 1oz copper should be suf-

ficient. This area of copper can be divided in many layers.

It is also important to put C1, the bypass capacitor for

the INTVCC pin as close as possible between the INTVCC

and GND.

Figure 6. Recommended Layout

4217 F06

HEAT SINK

VIA TO

SINK

GND

OUTVDD

1µF

RMON

20k 4219 F07

10k

PG = 4.35V

10k

100µF

VDD

EN1

EN2

OUT

GATE

GND

IMON

ISET

LTC4219DHC-5

INTVCC

TIMER

F LT

VOUT

ADC

* TVS Z1: DIODES INC. SMAJ17A

Z1* R3

200k

Additional Applications

The LTC4219 has a wide operating range from 2.9V to 15V.

The PG threshold is set with an internal resistive divider.

All other functions are independent of supply voltage.

Figure 7 shows a 5V application with a PG threshold of

4.35V.

In addition to Hot Swap applications, the LTC4219 also

functions as a backplane resident switch for removable

load cards (see the Typical Application section).

Figure 7. 5V, 5A Card Resident Application

LTC4219

4219fd

For more information www.linear.com/LTC4219

package DescripTion

DHC Package

16-Lead Plastic DFN (5mm × 3mm)

(Reference LTC DWG # 05-08-1706)

Please refer to http://www.linear.com/product/LTC4219#packaging for the most recent package drawings.

3.00 ±0.10

(2 SIDES)

5.00 ±0.10

(2 SIDES)

NOTE:

1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WJED-1) IN JEDEC

PACKAGE OUTLINE MO-229

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE

TOP AND BOTTOM OF PACKAGE

0.40 ±0.10

BOTTOM VIEW—EXPOSED PAD

1.65 ±0.10

(2 SIDES)

0.75 ±0.05

R = 0.115

TYP

R = 0.20

TYP

4.40 ±0.10

(2 SIDES)

169

PIN 1

TOP MARK

(SEE NOTE 6)

0.200 REF

0.00 – 0.05

(DHC16) DFN 1103

0.25 ±0.05

PIN 1

NOTCH

0.50 BSC

4.40 ±0.05

(2 SIDES)

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

1.65 ±0.05

(2 SIDES)2.20 ±0.05

0.50 BSC

0.65 ±0.05

3.50 ±0.05

PACKAGE

OUTLINE

0.25 ± 0.05

DHC Package

16-Lead Plastic DFN (5mm × 3mm)

(Reference LTC DWG # 05-08-1706 Rev Ø)

LTC4219

4219fd

For more information www.linear.com/LTC4219

revision hisTory

REV DATE DESCRIPTION PAGE NUMBER

A 8/10 Revised conditions for AIMON, IOFF(IMON), and tPHL(ILIM) in Electrical Characteristics section. 4

B 10/10 Revised VINTVCC TYP value from 3.0 to 3.1 in Electrical Characteristics section

Revised TIMER pin description in Pin Functions section

Revised TM1 + value from 0.2V to 0.21V in Functional Diagram

Revised voltages in 4th paragraph of Operation section

Revised 170mA to 140mA in Turn-Off Sequence section of the Applications Infomation

C 04/15 Typical Application: Added SMAJ22A and 200k EN Resistors

Increased Capacitance on INTVCC to 1µF from 0.1µF

Raised IGATE(DN) Maximum from 340µA to 400µA

Updated TPCs G02, G09, G11, G12, G14, G16

ISET Pin Function: Recommended Minimum Resistor Value to Be 2k

Figure 1: Added Auto-Retry (Q1), Z1, R2-R4, CCOMP; Updated C1, RGATE

Added Paragraph Explaining Auto-Retry with MOSFET Q1

Figures 5, 7: Added Z1, EN Pull-Up Resistors; Updated C1 Value

Typical Application: Added SMAJ22A; Raised INTVCC Capacitor to 1µF

Multiple

5, 6, 7

14, 15

D 10/15 Changed input TVS to SMAJ17A in application circuit.

Clarified that operating temperature range refers to ambient.

Added BWIMON and tD(FAULT) specifications.

Updated INTVCC and ISET pin functions.

Added equations to calculate MOSFET temperature.

1, 11, 14, 15, 18

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LTC4219

4219fd

For more information www.linear.com/LTC4219

relaTeD parTs

Typical applicaTion

PART NUMBER DESCRIPTION COMMENTS

LTC4210 Single Channel, Hot Swap Controller Operates from 2.7V to 16.5V, Active Current Limiting, SOT23-6

LTC4211 Single Channel, Hot Swap Controller Operates from 2.5V to 16.5V, Multifunction Current Control, MSOP-8 or MSOP-10

LTC4212 Single Channel, Hot Swap Controller Operates from 2.5V to 16.5V, Power-Up Timeout, MSOP-10

LTC4214 Negative Voltage, Hot Swap Controller Operates from 0V to –16V, MSOP-10

LTC4215 Hot Swap Controller with I2C Compatible

Monitoring

Operates from 2.9V to 15V, 8-Bit ADC Monitors Current and Voltage, SSOP-16 and

QFN-24

LTC4217 2A, Hot Swap Controller Operates from 2.9V to 26.5V, Integrated MOSFET and RSENSE, SSOP-20 or

5mm × 3mm DFN-16

LTC4218 Single Channel, Hot Swap Controller Operates from 2.9V to 26.5V, Adjustable Current Limit, SSOP-16 and DFN-16

LT4220 Positive and Negative Voltage, Dual Channels,

Hot Swap Controller

Operates from ±2.7V to ±16.5V, SSOP-16

LTC4221 Dual Hot Swap Controller/Sequencer Operates from 1V to 13.5V, Multifunction Current Control, SSOP-16

LTC4230 Triple Channels, Hot Swap Controller Operates from 1.7V to 16.5V, Multifunction Current Control, SSOP-20

LTC4352 0V to 18V Ideal Diode Controller Operates from 2.9V to 18V, 3mm × 3mm DFN-12 and MSOP-12

LTC4232 5A Integrated Hot Swap Controller Operates from 2.9V to 15V, Adjustable 10% Accurate Current Limit

LTC4233 10A Guaranteed SOA Hot Swap Controller Operates from 2.9V to 15V, Adjustable 11% Accurate Current Limit

LTC4234 20A Guaranteed SOA Hot Swap Controller Operates from 2.9V to 15V, Adjustable 11% Accurate Current Limit

12V, 5A Backplane Resident Application with Insertion Activated Turn-On

1µF

12V 12V

20k

10k

4219 TA02

12V

VDD

EN1

EN2

OUT

GATE

GND

IMON

ISET

LTC4219DHC-12

INTVCC

TIMER

F LT

VOUT

12V

PG = 10.5V

LOAD

ADC

*TVS Z1: DIODES INC. SMAJ17A

 LINEAR TECHNOLOGY CORPORATION 2010

LT 1015 REV D • PRINTED IN USA

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC4219