A4973SB-T - Allegro Microsystems

LOGIC

SUPPLY

LOAD

SUPPLY

PHASE

UVLO

& TSD

MODE

REF

OUT A

OUT B

ENABLE

SENSE

–

BRAKE

INPUT LOGIC

GROUND

PWM LATCH

+ –

BLANKING

SLEEP &

STANDBY MODES

VTH

GROUND

LOAD

SUPPLY

5 13

Description

Designed for bidirectional pulse width modulated (PWM)

current control of inductive loads, the A4973 is capable of

continuous output currents to ±1.5 A and operating voltages

to 50 V. Internal fixed off-time PWM current-control circuitry

can be used to regulate the maximum load current to a desired

value. The peak load current limit is set by the user’s selection

of an input reference voltage and external sensing resistor. The

fixed off-time pulse duration is set by a user- selected external

RC timing network. Internal circuit protection includes thermal

shutdown with hysteresis, transient-suppression diodes, and

crossover current protection. Special power-up sequencing is

not required.

With the ENABLE input held low, the PHASE input controls

load current polarity by selecting the appropriate source and

sink driver pair. The MODE input determines whether the

PWM current-control circuitry operates in a slow current-decay

mode (only the selected source driver switching) or in a fast

current-decay mode (selected source and sink switching). A

user-selectable blanking window prevents false triggering of

the PWM current-control circuitry. With the ENABLE input

held high, all output drivers are disabled. A sleep mode is

provided to reduce power consumption.

4973DS, Rev. 1

Features and Benefits

▪ ±1.5 A continuous output current

▪ 50 V output voltage rating

▪ 3 V to 5.5 V logic supply voltage

▪ Internal PWM current control

▪ Fast and slow current-decay modes

▪ Sleep (low current consumption) mode

▪ Internal transient-suppression diodes

▪ Internal thermal shutdown circuitry

▪ Crossover current and UVLO protection

Full-Bridge PWM Motor Driver

Continued on the next page…

Packages:

Functional Block Diagram

Not to scale

A4973

Package B, 16-pin DIP

with exposed tabs

Package LB, 16-pin SOIC

with internally fused pins

Full-Bridge PWM Motor Driver

A4973

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Description (continued)

Absolute Maximum Ratings

Characteristic Symbol Notes Rating Units

Load Supply Voltage VBB 50 V

Logic Supply Voltage VCC 6V

Logic/Reference Input Voltage Range VIN –0.3 to 6 V

Sense Voltage VSENSE 0.5 V

Output Current, Continuous IOUT

Output current rating may be limited by duty cycle, ambient

temperature, and heat sinking. Under any set of conditions, do

not exceed the speciﬁ ed current rating or a junction tempera-

ture of 150°C.

±1.5 A

Transient Output Current IOUT tW < 2 s6A

Package Power Dissipation PDSee graph W

Operating Ambient Temperature TARange S –20 to 85 ºC

Maximum Junction Temperature TJ(max)

Fault conditions that produce excessive junction temperature

will activate the device’s thermal shutdown circuitry. These

conditions can be tolerated but should be avoided.

150 ºC

Storage Temperature Tstg –55 to 150 ºC

Selection Guide

Part Number Package Packing

A4973SB-T 16-pin DIP with exposed thermal tabs 25 pieces per tube

A4973SLBTR-T 16-pin SOICW with internally-fused pins 1000 pieces per reel

When a logic low is applied to the BRAKE input, the braking

function is enabled. This overrides ENABLE and PHASE to turn

off both source drivers and turn on both sink drivers. The brake

function can be used to dynamically brake brush DC motors.

The A4973 is supplied in a choice of two power packages; a

16-pin dual-in-line plastic package with copper heat-sink tabs,

and a 16-pin plastic SOIC with copper heat-sink tabs. For both

package styles, the power tab is at ground potential and needs no

electrical isolation. Each package type is available in a lead (Pb)

free version (100% matte tin plated leadframe).

Thermal Characteristics

Characteristic Symbol Test Conditions* Value Units

Package Thermal Resistance, Junction

to Ambient RJA

B Package, single-layer PCB, 1 in.

2 2-oz. exposed copper 43 ºC/W

LB Package, 2-layer PCB, 0.3 in.

2 2-oz. exposed copper each

side 67 ºC/W

Package Thermal Resistance, Junction

to Tab RJT 6 ºC/W

*Additional thermal information available on Allegro website.

MODE

GROUND

LOGIC

SUPPLY

PHASE

GROUND

SENSE

LOAD

SUPPLY

Dwg. PP-056

BRAKE

REF

LOAD

SUPPLY

VCC

OUTB

OUTA

VBB

LOGIC

ENABLE

50 75 100 125 150

ALLOWABLE PACKAGE POWER DISSIPATION (W)

TEMPERATURE IN °C

R = 6.0°C/W

JT

SUFFIX 'B', R = 43°C/W

JA

SUFFIX 'LB', R = 67°C/W

JA

Note the A4973SB (DIP) and

the A4973SLB (SOIC) are

electrically identical and share

a common terminal number

assignment.

Full-Bridge PWM Motor Driver

A4973

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

ELECTRICAL CHARACTERISTICS at TJ = 25°C, VCC = 3.0 V to 5.5 V (unless otherwise noted.)

Characteristic Symbol Test Conditions Min. Typ. Max. Unit

Power Outputs

Load Supply Voltage Range VBB Operating 5 – 50 V

Output Leakage Current ICEX

VOUT = VBB – <1.0 50 A

VOUT = 0 V – <–1.0 –50 A

Output On Resistance RDS(on) Total sink and source, IOUT = 1.5 A, VBB > 8 V, TJ = 25°C – 1 1.4 

AC Timing

PWM RC Fixed Off-time tOFF RC CT = 680 pF, RT= 30 k, VCC = 3.3 V 18.3 20.4 22.5 s

PWM Minimum On Time tON(min)

VCC = 3.3 V, RT  12 k, CT = 680 pF 0.8 1.4 1.9 s

VCC = 5.0 V, RT  12 k, CT = 470 pF 0.8 1.6 2.0 s

Crossover Dead Time tCODT – 500 – ns

Maximum PWM Frequency fPWM(max) IOUT = 1.5 A 70 – – kHz

Control Circuitry

Thermal Shutdown Temperature TJ– 165 – °C

Thermal Shutdown Hysteresis TJ–15–°C

UVLO Enable Threshold 2.5 2.75 3.0 V

UVLO Hysteresis 0.12 0.17 0.25 V

Logic Supply Current ICC(ON) VENABLE = VIN(0) , VBRAKE = VIN(1) – 2.7 3.5 mA

ICC(Sleep) VENABLE = VMODE = VBRAKE = VIN(1) – 250 450 A

Motor Supply Current (No Load) IBB(ON) VENABLE = VIN(0) – 500 700 A

IBB(Sleep) VENABLE = VMODE = VBRAKE = VIN(1) – <1.0 3 A

Logic Supply Voltage Range VCC Operating 3.0 5.0 5.5 V

Logic Input Voltage

VIN(1)

VCC ×

0.55 ––V

VIN(0) ––

VCC ×

0.27 V

Logic Input Current IIN(1) VIN = VCC = 5 V — 0 –10 A

IIN(0) VIN = 0 V, VCC = 5 V — –106 –200 A

Reference Input Current IREF VREF = 0 V to 1 V – – ±5.0 A

Comparator Input Offset Volt. VIO VREF = 0 V – ±2.0 ±5.0 mV

Reference Input Voltage Range VREF REF Pin 0 – 1 V

Gain VREF = 1 V 1.9 2 2.1 –

Full-Bridge PWM Motor Driver

A4973

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

FUNCTIONAL DESCRIPTION

Internal PWM Current Control During Forward

and Reverse Operation. The A4973 contains a fixed

off-time pulse width modulated (PWM) current-control circuit

that can be used to limit the load current to a desired value. The

peak value of the current limiting (ITRIP) is set by the selection

of an external current sensing resistor (RS) and reference input

voltage (VREF). The internal circuitry compares the voltage

across the external sense resistor to the voltage on the reference

input terminal (REF) resulting in a transconductance function

approximated by:

In forward or reverse mode the current-control circuitry limits

the load current as follows: when the load current reaches ITRIP,

the comparator resets a latch that turns off the selected source

driver or selected sink and source driver pair depending on

whether the device is operating in slow or fast current-decay

mode, respectively.

In slow current-decay mode, the selected source driver is

disabled and both sinks are turned on. The load inductance

causes the current to recirculate through the sink drivers. In fast

current-decay mode, the selected sink and source driver pair are

disabled, then the opposite pair is turned on. The load inductance

causes the current to flow from ground to the load supply via the

motor winding and the opposite pair of transistors (see figure 1).

The user selects an external resistor (RT) and capacitor (CT) to

determine the time period (tOFF = RT x CT) during which the

drivers remain disabled (see RC Fixed Off-Time section, below).

At the end of the RC interval, the drivers are enabled allowing

the load current to increase again. The PWM cycle repeats,

maintaining the peak load current at the desired value (figure 2).

Figure 2

Fast and Slow Current-Decay Waveforms

Brake Operation. During braking, care should be taken

to ensure that the motor’s current does not exceed the ratings

of the device. The braking current can be measured by using

an oscilloscope with a current probe connected to one of the

motor’s leads, or if the back-EMF voltage of the motor is known,

approximated by:

VBEMF

RLOAD

IPEAK BRAKE ML 

RC Fixed Off-Time. The internal PWM current-control

circuitry uses a one shot to control the time the driver(s)

remain(s) off. The one-shot time, tOFF (fixed off-time), is

determined by the selection of an external resistor (RT) and

capacitor (CT) connected in parallel from the RC timing terminal

to ground. The fixed off-time, over a range of values of CT = 470

pF to 1500 pF and RT = 12 kΩ to 100 kΩ, is approximated by:

tOFF ≈ RT x CT

VREF

2 × RS

ITRIP 

Figure 1 — Load-Current Paths

VBB

Drive Current (Normal)

Recirculation (Fast Decay)

Recirculation (Slow Decay)

ENABLE

MODE

LOAD

CURRENT

TRIP

Dwg. WP-015-1

Full-Bridge PWM Motor Driver

A4973

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

TRUTH TABLE

BRAKE ENABLE PHASE MODE OUTAOUTBDESCRIPTION

H H X H Off Off Sleep Mode

H H X L Off Off Standby

H L H H H L Forward, Fast Current-Decay Mode

H L H L H L Forward, Slow Current-Decay Mode

H L L H L H Reverse, Fast Current-Decay Mode

H L L L L H Reverse, Slow Current-Decay Mode

L X X X L L Brake

X = Don’t care.

Full-Bridge PWM Motor Driver

A4973

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

The operation of the circuit is as follows: when the PWM latch is

reset by the current comparator, the voltage on the RC terminal

will begin to decay from approximately 0.60VCC. When the

voltage on the RC terminal reaches approximately 0.22VCC, the

PWM latch is set, thereby enabling the driver(s).

RC Blanking. In addition to determining the fixed off-time of

the PWM control circuit, the CT component sets the comparator

blanking time. This function blanks the output of the comparator

when the outputs are switched by the internal current-control

circuitry (or by the PHASE, BRAKE, or ENABLE inputs).

The comparator output is blanked to prevent false over-current

detections due to reverse recovery currents of the clamp diodes,

and/or switching transients related to distributed capacitance in

the load.

During internal PWM operation, at the end of the tOFF time, the

comparator’s output is blanked and CT begins to be charged

from approximately 0.22VCC by an internal current source of

approximately 1 mA. The comparator output remains blanked

until the voltage on CT reaches approximately 0.60VCC.

When a transition of the PHASE input occurs, CT is discharged

to near ground during the crossover delay time (the crossover

delay time is present to prevent simultaneous conduction of

the source and sink drivers). After the crossover delay, CT is

charged by an internal current source of approximately 1 mA.

The comparator output remains blanked until the voltage on CT

reaches approximately 0.60VCC.

When the device is disabled, via the ENABLE input, CT is

discharged to near ground. When the device is re-enabled, CT is

charged by an internal current source of approximately 1 mA.

The comparator output remains blanked until the voltage on CT

reaches approximately 0.60VCC.

For 3.3 V operation, the minimum recommended value

for CT is 680 pF ± 5 %. For 5.0 V operation, the minimum

recommended value for CT is 470 pF ± 5%. These values

ensure that the blanking time is sufficient to avoid false trips

of the comparator under normal operating conditions. For

optimal regulation of the load current, the above values for CT

are recommended and the value of RT can be sized to determine

tOFF. For more information regarding load current regulation, see

below.

LOAD CURRENT REGULATION

WITH INTERNAL PWM

CURRENT-CONTROL CIRCUITRY

When the device is operating in slow current-decay mode,

there is a limit to the lowest level that the PWM current-

control circuitry can regulate load current. The limitation is the

minimum duty cycle, which is a function of the user-selected

value of tOFF and the minimum on-time pulse tON(min) max that

occurs each time the PWM latch is reset. If the motor is not

rotating (as in the case of a stepper motor in hold/detent mode, a

brush dc motor when stalled, or at startup), the worst case value

of current regulation can be approximated by:

{ [ VBB – (2 × I × RDS) ] × tON(min)max } – [1.05 (I × RDS + VF) × tOFF ]

1.05 × (tON(min)max + tOFF) × RLOAD

IAVE 

where tOFF = RT x CT, RLOAD is the series resistance of the load,

VBB is the motor supply voltage and t ON(min)max is specified in

the Electrical Characteristics table. When the motor is rotating,

the back EMF generated will influence the above relationship.

For brush dc motor applications, the current regulation is

improved. For stepper motor applications, when the motor is

rotating, the effect is more complex. A discussion of this subject

is included in the section on stepper motors below.

The following procedure can be used to evaluate the worst-case

slow current-decay internal PWM load current regulation in the

system:

1. Set VREF to 0 volts. With the load connected and the PWM

current control operating in slow current-decay mode, use an

oscilloscope to measure the time the output is low (sink on) for

the output that is chopping. This is the typical minimum on time

(tON(min) typ) for the device.

2. The CT then should be increased until the measured value

of tON(min) is equal to tON(min) max as specified in the electrical

characteristics table.

3. When the new value of CT has been set, the value of RT should

be decreased so the value for tOFF = RT x CT (with the artificially

increased value of CT) is equal to the nominal design value.

4. The worst-case load-current regulation then can be measured

in the system under operating conditions.

Full-Bridge PWM Motor Driver

A4973

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

PWM of the PHASE and ENABLE Inputs. The

PHASE and ENABLE inputs can be pulse-width modulated

to regulate load current. If the internal PWM current control is

used, the comparator blanking function is active during phase

and enable transitions. This eliminates false tripping of the

over-current comparator caused by switching transients (see RC

Blanking section, above).

Enable PWM. With the MODE input low, toggling the

ENABLE input turns on and off the selected source and sink

drivers. The corresponding pair of intrinsic flyback and ground-

clamp diodes conduct after the drivers are disabled, resulting

in fast current decay. When the device is enabled the internal

current-control circuitry will be active and can be used to limit

the load current in a slow current-decay mode.

For applications that PWM the ENABLE input and desire the

internal current-limiting circuit to function in the fast decay

mode, the ENABLE input signal should be inverted and

connected to the MODE input. This prevents the device from

being switched into sleep mode when the ENABLE input is low.

Phase PWM. Toggling the PHASE terminal selects which

sink/source pair is enabled, producing a load current that varies

with the duty cycle and remains continuous at all times. This

can have added benefits in bidirectional brush dc servo motor

applications as the transfer function between the duty cycle on

the PHASE input and the average voltage applied to the motor is

more linear than in the case of ENABLE PWM control (which

produces a discontinuous current at low current levels). For more

information see DC Motor Applications section, below.

Synchronous Fixed-Frequency PWM. The internal

PWM current-control circuitry of multiple A4973 devices can

be synchronized by using the simple circuit shown in figure 3.

A 555 IC can be used to generate the reset pulse/blanking signal

(t1) for the device and the period of the PWM cycle (t2). The

value of t1 should be a minimum of 1.5 ms. When used in this

configuration, the RT and CT components should be omitted. The

PHASE and ENABLE inputs should not be PWMed with this

circuit configuration due to the absence of a blanking function

synchronous with their transitions.

Miscellaneous Information. A logic high applied to both

the ENABLE and MODE terminals puts the device into a sleep

mode to minimize current consumption when not in use.

An internally generated dead time prevents crossover currents

that can occur when switching phase or braking.

Thermal protection circuitry turns off all drivers should the

junction temperature reach 165°C (typical). This is intended

only to protect the device from failures due to excessive junction

temperatures and should not imply that output short circuits

are permitted. The hysteresis of the thermal shutdown circuit is

approximately 15°C.

APPLICATION NOTES

Current Sensing. The actual peak load current (IPEAK) will

be above the calculated value of ITRIP due to delays in the turn

off of the drivers. The amount of overshoot can be approximated

by:

(VBB – [(ITRIP x RLOAD) + VBEMF]) x tPWM(OFF)

LLOAD

IOS 

where VBB is the motor supply voltage, VBEMF is the back-EMF

voltage of the load, RLOAD and LLOAD are the resistance and

inductance of the load respectively, and tPWM(OFF) is specified in

the electrical characteristics table.

The reference terminal has a maximum input bias current

of ±5 μA. This current should be taken into account when

determining the impedance of the external circuit that sets the

reference voltage value.

To minimize current-sensing inaccuracies caused by ground

trace I x R drops, the current-sensing resistor should have a

separate return to the ground terminal of the device. For low-

value sense resistors, the I x R drops in the printed wiring board

can be significant and should be taken into account. The use of

sockets should be avoided as their contact resistance can cause

variations in the effective value of RS.

Generally, larger values of RS reduce the aforementioned effects

but can result in excessive heating and power loss in the sense

resistor. The selected value of RS should not cause the absolute

maximum voltage rating of 500 mV, for the SENSE terminal, to

be exceeded.

Dwg. EP-060

100 kΩ

20 kΩ

1N4001

2N2222

Figure 3

Synchronous Fixed-Frequency Control Circuit

Full-Bridge PWM Motor Driver

A4973

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

The current-sensing comparator functions down to ground

allowing the device to be used in microstepping, sinusoidal, and

other varying current-profile applications.

Thermal Considerations. For reliable operation it is

recommended that the maximum junction temperature be kept

below 110°C to 125°C. The junction temperature can be measured

best by attaching a thermocouple to the power tab/batwing of the

device and measuring the tab temperature, TTAB. The junction

temperature can then be approximated by using the formula:

TJ  TTAB + I2

LOAD × RDS(on) x RJT

The value for RθJT is given in the package thermal resistance table

for the appropriate package.

The power dissipation of the batwing packages can be improved

by 20% to 30% by adding a section of printed circuit board

copper (typically 6 to 18 square centimeters) connected to the

batwing terminals of the device.

PCB Layout. The load supply terminal, VBB, should

be decoupled with an electrolytic capacitor (>47 μF is

recommended) placed as close to the device as is physically

practical. To minimize the effect of system ground I x R drops on

the logic and reference input signals, the system ground should

have a low-resistance return to the motor supply voltage. See also

the Current Sensing and Thermal Considerations sections, above.

Fixed Off-Time Selection. With increasing values of tOFF,

switching losses will decrease, low-level load-current regulation

will improve, EMI will be reduced, the PWM frequency will

decrease, and ripple current will increase. The value of tOFF can

be chosen for optimization of these parameters. For applications

where audible noise is a concern, typical values of tOFF are chosen

to be in the range of 15 to 35 μs.

Stepper Motor Applications. The MODE terminal can be

used to optimize the performance of the device in microstepping/

sinusoidal stepper-motor drive applications. When the load

current is increasing, slow decay mode is used to limit the

switching losses in the device and iron losses in the motor. This

also improves the maximum rate at which the load current can

increase (as compared to fast decay) due to the slow rate of decay

during tOFF. When the load current is decreasing, fast-decay mode

is used to regulate the load current to the desired level. This

prevents tailing of the current profile caused by the back-EMF

voltage of the stepper motor.

In stepper-motor applications applying a constant current to

the load, slow-decay mode PWM is typically used to limit the

switching losses in the device and iron losses in the motor.

DC Motor Applications. In closed-loop systems, the

speed of a dc motor can be controlled by PWM of the PHASE

or ENABLE inputs, or by varying the reference input voltage

(REF). In digital systems (microprocessor controlled), PWM of

the PHASE or ENABLE input is used typically thus avoiding

the need to generate a variable analog voltage reference. In this

case, a dc voltage on the REF input is used typically to limit the

maximum load current.

In dc servo applications, which require accurate positioning

at low or zero speed, PWM of the PHASE input is selected

typically. This simplifies the servo control loop because the

transfer function between the duty cycle on the PHASE input and

the average voltage applied to the motor is more linear than in the

case of ENABLE PWM control (which produces a discontinuous

current at low current levels).

With bidirectional dc servo motors, the PHASE terminal can be

used for mechanical direction control. Similar to when braking

the motor dynamically, abrupt changes in the direction of a

rotating motor produces a current generated by the back-EMF.

The current generated will depend on the mode of operation. If

the internal current control circuitry is not being used, then the

maximum load current generated can be approximated by ILOAD =

(VBEMF + VBB)/RLOAD where VBEMF is proportional to the motor’s

speed. If the internal slow current-decay control circuitry is used,

then the maximum load current generated can be approximated

by ILOAD = VBEMF/RLOAD. For both cases care must be taken to

Full-Bridge PWM Motor Driver

A4973

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

ensure that the maximum ratings of the device are not exceeded.

If the internal fast current-decay control circuitry is used, then the

load current will regulate to a value given by:

ILOAD = VREF / (RS × 2)

CAUTION: In fast current-decay mode, when the direction of

the motor is changed abruptly, the kinetic energy stored in the

motor and load inertia will be converted into current that charges

the VBB supply bulk capacitance (power supply output and

decoupling capacitance). Care must be taken to ensure that the

capacitance is sufficient to absorb the energy without exceeding

the voltage rating of any devices connected to the motor supply.

See also the Brake Operation section, above.

Soldering Considerations. The lead (Pb) free (100%

matte tin) plating on lead terminations is 100% backward-

compatible for use with traditional tin-lead solders of any

composition, at any temperature of soldering that has been

traditionally used for that tin-lead solder alloy. Further, 100%

matte tin finishes solder well with tin-lead solders even at

temperatures below 232°C. This is because the matte tin dissolves

easily in the tin-lead. Additional information on soldering is

available on the Allegro Web site, www.allegromicro.com.

Figure 4 — Typical Application

VCC

VBB

LOGIC

47 MF

30 k 7

0.5 7

MODE

PHASE

ENABLE

BRAKE

470 pF

+5 V

REF

Full-Bridge PWM Motor Driver

A4973

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

LB package 16-pin SOICW

9.50

0.65

2.25

1.27

SEATING

PLANE

C0.10

16X

1.27

0.25

0.20 ±0.10

0.41 ±0.10 2.65 MAX

10.30±0.33

7.50±0.10

4° ±4

0.27 +0.07

–0.06

0.84 +0.44

–0.43

10.30±0.20

GAUGE PLANE

SEATING PLANE For Reference Only

Pins 4 and 5, and 12 and 13 internally fused

Dimensions in millimeters

(reference JEDEC MS-013 AA)

Dimensions exclusive of mold flash, gate burrs, and dambar protrusions

Exact case and lead configuration at supplier discretion within limits shown

ATerminal #1 mark area

BReference pad layout (reference IPC SOIC127P1030X265-16M)

All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary

to meet application process requirements and PCB layout tolerances

BPCB Layout Reference View

B package 16-pin DIP

19.05±0.25

5.33 MAX

0.46 ±0.12

1.27 MIN

Dimensions exclusive of mold flash, gate burrs, and dambar protrusions

Exact case and lead configuration at supplier discretion within limits shown

ATerminal #1 mark area

6.35 +0.76

–0.25

3.30 +0.51

–0.38

10.92 +0.38

–0.25

1.52 +0.25

–0.38

0.38 +0.10

–0.05

7.62

2.54

For Reference Only

(reference JEDEC MS-001 BB)

Dimensions in millimeters

Full-Bridge PWM Motor Driver

A4973

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per-

mit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the

information being relied upon is current.

Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the

failure of that life support device or system, or to affect the safety or effectiveness of that device or system.

The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its use;

nor for any in fringe ment of patents or other rights of third parties which may result from its use.

For the latest version of this document, visit our website:

www.allegromicro.com

Revision History

Revision Revision Date Description of Revision

Rev. 1 October 23, 2012 Update Absolute Maximum Ratings