NPN Silicon Planar
Epitaxial Transistor
This NPN Silicon Epitaxial transistor is designed for use in linear
and switching applications. The device is housed in the SOT-223
package which is designed for medium power surface mount
applications.
PNP Complement is PZT2907AT1
The SOT-223 package can be soldered using wave or reflow.
SOT-223 package ensures level mounting, resulting in improved
thermal conduction, and allows visual inspection of soldered joints.
The formed leads absorb thermal stress during soldering, eliminating
the possibility of damage to the die.
Available in 12 mm tape and reel
Use PZT2222AT1 to order the 7 inch/1000 unit reel.
Use PZT2222AT3 to order the 13 inch/4000 unit reel.
MAXIMUM RATINGS
Rating Symbol Value Unit
Collector-Emitter Voltage VCEO 40 Vdc
Collector-Base Voltage VCBO 75 Vdc
Emitter-Base Voltage (Open Collector) VEBO 6.0 Vdc
Collector Current IC600 mAdc
Total Power Dissipation up to TA = 25°C(1) PD1.5 Watts
Storage Temperature Range°Tstg 65 to +150 °C
Junction Temperature°TJ150 °C
THERMAL CHARACTERISTICS
Thermal Resistance from Junction to Ambient RθJA 83.3 °C/W
Lead Temperature for Soldering, 0.0625 from case
Time in Solder Bath TL260
10 °C
Sec
DEVICE MARKING
P1F
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Characteristic Symbol Min Max Unit
OFF CHARACTERISTICS
Collector-Emitter Breakdown Voltage (IC = 10 mAdc, IB = 0) V(BR)CEO 40 Vdc
Collector-Base Breakdown Voltage (IC = 10 µAdc, IE = 0) V(BR)CBO °75° °°Vdc
Emitter-Base Breakdown Voltage (IE = 10 µAdc, IC = 0) V(BR)EBO 6.0 Vdc
Base-Emitter Cutoff Current (VCE = 60 Vdc, VBE = – 3.0 Vdc) IBEX 20 nAdc
Collector-Emitter Cutoff Current (VCE = 60 Vdc, VBE = – 3.0 Vdc) ICEX 10 nAdc
Emitter-Base Cutoff Current (VEB = 3.0 Vdc, IC = 0) IEBO 100 nAdc
1. Device m ounted on a n epoxy printed circuit board 1.575 inches x 1.575 inches x 0.059 inches; mounting p ad for the co llector lead m in. 0.93 inches2.
Preferred devices are ON Semiconductor recommended choices for future use and best overall value.
ON Semiconductor
Semiconductor Components Industries, LLC, 2001
March, 2001 – Rev. 3 1Publication Order Number:
PZT2222AT1/D
BASE
1
COLLECTOR
2, 4
3
EMITTER
PZT2222AT1
SOT-223 PACKAGE
NPN SILICON
TRANSISTOR
SURFACE MOUNT
ON Semiconductor Preferred Device
CASE 318E-04, STYLE 1
TO-261AA
123
4
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ELECTRICAL CHARACTERISTICS — continued (TA = 25°C unless otherwise noted)
Characteristic Symbol Min Max Unit
OFF CHARACTERISTICS (continued)
Collector-Base Cutoff Current
(VCB = 60 Vdc, IE = 0)
(VCB = 60 Vdc, IE = 0, TA = 125°C)
ICBO
10
10 nAdc
µAdc
ON CHARACTERISTICS
DC Current Gain
(IC = 0.1 mAdc, VCE = 10 Vdc)
(IC = 1.0 mAdc, VCE = 10 Vdc)
(IC = 10 mAdc, VCE = 10 Vdc)
(IC = 10 mAdc, VCE = 10 Vdc, TA = – 55°C)
(IC = 150 mAdc, VCE = 10 Vdc)
(IC = 150 mAdc, VCE = 1.0 Vdc)
(IC = 500 mAdc, VCE = 10 Vdc)
hFE 35
50
70
35
100
50
40
300
Collector-Emitter Saturation Voltages
(IC = 150 mAdc, IB = 15 mAdc)
(IC = 500 mAdc, IB = 50 mAdc)
VCE(sat)
0.3
1.0
Vdc
Base-Emitter Saturation Voltages
(IC = 150 mAdc, IB = 15 mAdc)
(IC = 500 mAdc, IB = 50 mAdc)
VBE(sat) 0.6
1.2
2.0
Vdc
Input Impedance°
(VCE = 10 Vdc, IC = 1.0 mAdc, f = 1.0 kHz)
(VCE = 10 Vdc, IC = 10 mAdc, f = 1.0 kHz)
°hie°2.0
0.25 8.0
1.25
k
Voltage Feedback Ratio
(VCE = 10 Vdc, IC = 1.0 mAdc, f = 1.0 kHz)
(VCE = 10 Vdc, IC = 10 mAdc, f = 1.0 kHz)
hre
8.0x10-4
4.0x10-4
Small-Signal Current Gain
(VCE = 10 Vdc, IC = 1.0 mAdc, f = 1.0 kHz)
(VCE = 10 Vdc, IC = 10 mAdc, f = 1.0 kHz)
hfe50
75 300
375
Output Admittance°
(VCE = 10 Vdc, IC = 1.0 mAdc, f = 1.0 kHz)
(VCE = 10 Vdc, IC = 10 mAdc, f = 1.0 kHz)
°hoe°5.0
25 35
200
µmhos
Noise Figure (VCE = 10 Vdc, IC = 100 µAdc, f = 1.0 kHz) F 4.0 dB
DYNAMIC CHARACTERISTICS
Current-Gain — Bandwidth Product
(IC = 20 mAdc, VCE = 20 Vdc, f = 100 MHz) fT300 MHz
Output Capacitance
(VCB = 10 Vdc, IE = 0, f = 1.0 MHz) Cc 8.0 pF
Input Capacitance
(VEB = 0.5 Vdc, IC = 0, f = 1.0 MHz) Ce 25 pF
SWITCHING TIMES (TA = 25°C)
Delay Time (VCC = 30 Vdc, IC = 150 mAdc,
IB( ) = 15 mAdc VEB( ff) = 0 5 Vdc)
td 10 ns
Rise Time IB(on) = 15 mAdc, VEB(off) = 0.5 Vdc)
Figure 1 tr 25
Storage Time (VCC = 30 Vdc, IC = 150 mAdc,
IB( ) =I
B( ff) = 15 mAdc)
ts 225 ns
Fall Time IB(on) = IB(off) = 15 mAdc)
Figure 2 tf 60
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Vi
90%
10%
tp
tr
0
VCC
R2
R1
ViD.U.T.
Vo
Figure 1. Input Waveform and Test Circuit for Determining Delay Time and Rise Time
Figure 2. Input Waveform and Test Circuit for Determining Storage Time and Fall Time
Vi = – 0.5 V to +9.9 V, VCC = +30 V, R1 = 619 , R2 = 200 .
PULSE GENERATOR: OSCILLOSCOPE:
PULSE DURATION tp200 ns INPUT IMPEDANCE Zi> 100 k
RISE TIME tr2 ns INPUT CAPACITANCE Ci< 12 pF
DUTY FACTOR δ= 0.02 RISE TIME tr< 5 ns
tf100 µs
-13.8 V
0
+16.2 V
Vi
TIME
VCC
Vo
OSCILLOSCOPE
D.U.T.
Vi
R2
R3
R4
D1
R1
VBB
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INFORMATION FOR USING THE SOT-223 SURFACE MOUNT PACKAGE
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total
design. The footprint for the semiconductor packages must
be the correct size to insure proper solder connection
interface between the board and the package. With the
correct pad geometry, the packages will self align when
subjected to a solder reflow process.
SOT-223
0.079
2.0
0.15
3.8
0.248
6.3
0.079
2.0
0.059
1.5
0.059
1.5
0.059
1.5
0.091
2.3
0.091
2.3
mm
inches
SOT-223 POWER DISSIPATION
The power dissipation of the SOT-223 is a function of the
pad size. This can vary from the minimum pad size for
soldering to a pad size given for maximum power
dissipation. Power dissipation for a surface mount device is
determined by TJ(max), the maximum rated junction
temperature o f the die, RθJA, the thermal resistance from t h e
device junction to ambient, and the operating temperature,
TA. Using the values provided on the data sheet for the
SOT-223 package, PD can be calculated as follows:
PD = TJ(max) – TA
RθJA
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values into
the equation for an ambient temperature TA of 25°C, one can
calculate the power dissipation of the device which in this
case is 1.5 watts.
PD = 150°C – 25°C= 1.5 watts
83.3°C/W
The 83.3°C/W for the SOT-223 package assumes the use
of the recommended footprint on a glass epoxy printed
circuit board to achieve a power dissipation of 1.5 watts.
There are other alternatives to achieving higher power
dissipation from the SOT-223 package. One is to increase
the area of the collector pad. By increasing the area of the
collector pad, the power dissipation can be increased.
Although the power dissipation can almost be doubled with
this method, area is taken up on the printed circuit board
which can defeat the purpose of using surface mount
technology. A graph of RθJA versus collector pad area is
shown in Figure 3.
0.8 Watts
1.25 Watts* 1.5 Watts
R , Thermal Resistance, Junction
to Ambient (C/W)
θ
JA
°
A, Area (square inches)
0.0 0.2 0.4 0.6 0.8 1.0
160
140
120
100
80
Figure 3. Thermal Resistance versus Collector
Pad Area for the SOT-223 Package (Typical)
Board Material = 0.0625
G10/FR4, 2 oz Copper
TA = 25°C
*Mounted on the DPAK footprint
Another alternative would be to use a ceramic substrate or
an aluminum core board such as Thermal Clad. Using a
board material such as Thermal Clad, an aluminum core
board, the power dissipation can be doubled using the same
footprint.
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SOLDER STENCIL GUIDELINES
Prior to placing surface mount components onto a printed
circuit board, solder paste must be applied to the pads. A
solder stencil is required to screen the optimum amount of
solder paste onto the footprint. The stencil is made of brass
or stainless steel with a typical thickness of 0.008 inches.
The stencil opening size for the SOT-223 package should be
the same as the pad size on the printed circuit board, i.e., a
1:1 registration.
SOLDERING PRECAUTIONS
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within
a short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.
Always preheat the device.
The delta temperature between the preheat and
soldering should be 100°C or less.*
When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering
method, the difference should be a maximum of 10°C.
The soldering temperature and time should not exceed
260°C for more than 10 seconds.
When shifting from preheating to soldering, the
maximum temperature gradient should be 5°C or less.
After soldering has been completed, the device should
be allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and
result in latent failure due to mechanical stress.
Mechanical stress or shock should not be applied
during cooling
* Soldering a device without preheating can cause
excessive thermal shock and stress which can result in
damage to the device.
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TYPICAL SOLDER HEATING PROFILE
For any given circuit board, there will be a group of
control settings that will give the desired heat pattern. The
operator must set temperatures for several heating zones,
and a figure for belt speed. Taken together, these control
settings make up a heating “profile” for that particular
circuit board. On machines controlled by a computer, the
computer remembers these profiles from one operating
session to the next. Figure 4 shows a typical heating profile
for use when soldering a surface mount device to a printed
circuit board. This profile will vary among soldering
systems b u t i t i s a good starting point. Factors that can a ffect
the profile include the type of soldering system in use,
density and types of components on the board, type of solder
used, and the type of board or substrate material being used.
This profile shows temperature versus time. The line on the
graph shows the actual temperature that might be
experienced o n the surface of a test board at or near a central
solder joint. The two profiles are based on a high density an d
a low density board. The Vitronics SMD310
convection/infrared reflow soldering system was used to
generate this profile. The type of solder used was 62/36/2
Tin Lead Silver with a melting point between 177–189°C.
When this type of furnace is used for solder reflow work, the
circuit boards and solder joints tend to heat first. The
components o n the board are then heated by conduction. The
circuit board, because it has a lar ge surface area, absorbs the
thermal energy more efficiently, then distributes this energy
to the components. Because of this effect, the main body of
a component may be up to 30 degrees cooler than the
adjacent solder joints.
STEP 1
PREHEAT
ZONE 1
RAMP"
STEP 2
VENT
SOAK"
STEP 3
HEATING
ZONES 2 & 5
RAMP"
STEP 4
HEATING
ZONES 3 & 6
SOAK"
STEP 5
HEATING
ZONES 4 & 7
SPIKE"
STEP 6
VENT
STEP 7
COOLING
200°C
150°C
100°C
50°C
TIME (3 TO 7 MINUTES TOTAL) TMAX
SOLDER IS LIQUID FOR
40 TO 80 SECONDS
(DEPENDING ON
MASS OF ASSEMBLY)
205° TO
219°C
PEAK AT
SOLDER
JOINT
DESIRED CURVE FOR LOW
MASS ASSEMBLIES
DESIRED CURVE FOR HIGH
MASS ASSEMBLIES
100°C
150°C
160°C
170°C
140°C
Figure 4. Typical Solder Heating Profile
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PACKAGE DIMENSIONS
CASE 318E–04
ISSUE K
SOT–223 (TO–261)
H
S
F
A
B
D
G
L
4
123
0.08 (0003)
C
MK
J
DIM
A
MIN MAX MIN MAX
MILLIMETERS
0.249 0.263 6.30 6.70
INCHES
B0.130 0.145 3.30 3.70
C0.060 0.068 1.50 1.75
D0.024 0.035 0.60 0.89
F0.115 0.126 2.90 3.20
G0.087 0.094 2.20 2.40
H0.0008 0.0040 0.020 0.100
J0.009 0.014 0.24 0.35
K0.060 0.078 1.50 2.00
L0.033 0.041 0.85 1.05
M0 10 0 10
S0.264 0.287 6.70 7.30
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.

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PZT2222AT1/D
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