AC/DC TO LOGIC INTERFACE OPTOCOUPLER HCPL-3700 DESCRIPTION The HCPL-3700 voltage/current threshold detection optocoupler consists of an AlGaAs LED connected to a threshold sensing input buffer IC which are optically coupled to a high gain darlington output. The input buffer chip is capable of controlling threshold levels over a wide range of input voltages with a single resistor. The output is TTL and CMOS compatible. 8 1 FEATURES * * * * AC or DC input Programmable sense voltage Logic level compatibility Threshold guaranteed over temperature (0C to 70C) * OptoplanarTM construction for high common mode immunity * UL recognized (file # E90700) TRUTH TABLE (Positive Logic) APPLICATIONS * * * * * * Low voltage detection 5 V to 240 V AC/DC voltage sensing Relay contact monitor Current sensing Microprocessor Interface Industrial controls 8 Input Output H L L H 1 A 0.1 F bypass capacitor must be connected between pins 8 and 5. AC/DC POWER 8 1 AC 1 8 VCC DC+ 2 7 NC DC- 3 6 VO AC 4 5 GND RX HCPL-3700 GND 1 LOGIC GND 2 ABSOLUTE MAXIMUM RATINGS (No derating required up to 70C) Parameter Symbol Value Units Storage Temperature TSTG -55 to +125 C Operating Temperature TOPR -40 to +85 C Lead Solder Temperature TSOL 260 for 10 sec C EMITTER Average 50 (MAX) Input Current Surge 3 ms, 120 Hz Pulse Rate Transient 10 s, 120 Hz Pulse Rate Input Voltage (Pins 2-3) IIN 140 (MAX) mA 500 (MAX) VIN -0.5 (MIN) V Input Power Dissipation (Note 1) PIN 230 (MAX) mW Total Package Power Dissipation (Note 2) PT 305 (MAX) mW (Note 3) IO 30 (MAX) mA DETECTOR Output Current (Average) Supply Voltage (Pins 8-5) VCC -0.5 to 20 V Output Voltage (Pins 6-5) VO -0.5 to 20 V PO 210 (MAX) mW Output Power Dissipation (c) 2003 Fairchild Semiconductor Corporation (Note 4) Page 1 of 11 11/8/04 AC/DC TO LOGIC INTERFACE OPTOCOUPLER HCPL-3700 ELECTRICAL CHARACTERISTICS (TA = 0C to 70C Unless otherwise specified) Parameter Test Conditions Input Threshold Current DC (Pins 2,3) Input Threshold Voltage AC (Pins 1,4) Hysteresis Input Clamp Voltage Input Current Bridge Diode Forward Voltage Symbol Min Typ Max Unit (VIN = VTH+, VCC = 4.5 V) ITH+ 1.96 2.4 3.11 mA (VO = 0.4 V, IO 4.2 mA) (Note 5) ITH- 1.00 1.2 1.62 mA (VIN = V2 - V3, Pins 1 & 4 Open) (VCC = 4.5 V, VO = 0.4 V) (Note 5) (IO 4.2 mA) VTH+ 3.35 3.8 4.05 V (VIN = V2 - V3, Pins 1 & 4 Open) (VCC = 4.5 V, VO = 2.4 V) (Note 5) (IO 100 A) VTH- 2.01 2.5 2.86 V |VIN = V1 - V4| (Pins 2 & 3 Open) (VCC = 4.5 V, VO = 0.4 V) (Note 5) (IO 4.2 mA) VTH+ 4.23 5.0 5.50 V |VIN = |V1 - V4| (Pins 2 & 3 Open) (VCC = 4.5 V, VO = 2.4 V) (Note 5) (IO 100 A) VTH- 2.87 3.7 4.20 V (IHYS = ITH+ - ITH-) IHYS 1.2 mA 1.3 V (VHYS = VTH+ - VTH-) VHYS (VIHC1 = V2 - V3, V3 = GND) (IIN = 10 mA, Pins 1 & 4 Connected to Pin 3) VIHC1 5.4 6.3 6.6 V (VIHC2 = |V1 - V4|) (|IIN| = 10 mA) (Pins 2 & 3 Open) VIHC2 6.1 7.0 7.3 V (VIHC3 = V2 - V3, V3 = GND) (IIN = 15 mA; Pins 1 & 4 Open) VIHC3 12.5 13.4 V (VILC = V2 - V3, V3 = GND) (IIN = -10 mA) VILC -0.75 (VIN = V2 - V3 = 5.0 V) (Pins 1 & 4 Open) IIN 4.4 mA VD1,2 0.65 V (IIN = 3 mA) VD3,4 0.65 V 0.04 (VCC = 4.5 V; IOL = 4.2 mA) (Note 5) VOL Logic High Output Current (Note 5) (VOH = VCC = 18 V) IOH Logic Low Supply Current (V2 - V3 = 5.0 V; VO = Open) (VCC = 5 V) ICCL Logic High Supply Current (VCC = 18 V; VO = Open) (f = 1 MHz; VIN = 0V) (Pins 2 & 3, Pins 1 & 4 Open) (c) 2003 Fairchild Semiconductor Corporation 3.7 (IIN = 3 mA) Logic Low Output Voltage Input Capacitance 3.0 V Page 2 of 11 0.4 V 100 A 1.0 4 mA ICCH 0.01 4 A CIN 50 pF 11/8/04 AC/DC TO LOGIC INTERFACE OPTOCOUPLER HCPL-3700 RECOMMENDED OPERATING CONDITIONS Parameter Supply Voltage Operating Temperature Operating Frequency Symbol Min Max Units VCC 2 18 V TA 0 70 C f 0 4 kHz SWITCHING CHARACTERISTICS (TA = 25C, VCC = 5 V Unless otherwise specified) AC Characteristics Test Conditions Symbol Min Typ Max Unit Propagation Delay Time (to Output Low Level) (RL = 4.7 k, CL = 30 pF) (Note 6) TPHL 6.0 15 s Propagation Delay Time (to Output High Level) (RL = 4.7 k, CL = 30 pF) (Note 6) TPLH 25.0 40 s Output Rise Time (10-90%) (RL = 4.7 k, CL = 30 pF) tr 45 s Output Fall Time (90-10%) (RL = 4.7 k, CL = 30 pF) tf 0.5 s Common Mode Transient Immunity (at Output High Level) (IIN = 0 mA, RL = 4.7 k) (VO min = 2.0 V, VCM = 1400 V) (Notes 7,8) |CMH| 4000 V/s Common Mode Transient Immunity (at Output Low Level) (IN = 3.11 mA,RL = 4.7 k) (VO max = 0.8 V, VCM = 140 V) (Notes 7,8) |CML| 600 V/s PACKAGE CHARACTERISTICS (TA = 0C to 70C Unless otherwise specified) Characteristics Test Conditions Symbol Min 2500 Typ Max Unit Withstand Insulation Voltage (Relative humidity < 50%) (TA = 25C, t = 1 min) (Notes 9,10) VISO Resistance (input to output) (Note 9) (VIO = 500 Vdc) RI-O 1012 Capacitance (input to output) (f = 1 MHz, VIO = 0 Vdc) CI-O 0.6 pF (c) 2003 Fairchild Semiconductor Corporation Page 3 of 11 VRMS 11/8/04 AC/DC TO LOGIC INTERFACE OPTOCOUPLER HCPL-3700 NOTES 1. Derate linearly above 70C free-air temperature at a rate of 1.8 mW/C. 2. Derate linearly above 70C free-air temperature at a rate of 2.5 mW/C. 3. Derate linearly above 70C free-air temperature at a rate of 0.6 mA/C. 4. Derate linearly above 70C free-air temperature at a rate of 1.9 mW/C. 5. Logic low output level at pin 6 occurs when VINVTH+ and when VIN>VTH- once VIN exceeds VTH+. Logic high output level at pin 6 occurs when VINVTH- and when VIN<VTH+ once VIN decreases below VTH-. 6. TPHL propagation delay is measured from the 2.5 V level of the leading edge of a 5.0 V input pulse (1 s rise time) to the 1.5 V level on the leading edge of the output pulse. TPLH propagation delay is measured on the trailing edges of the input and output pulse. (Refer to Fig. 9) 7. Common mode transient immunity in logic high level is the maximum tolerable (positive) dVcm/dt on the leading edge of the common mode pulse signal VCM, to assure that the output will remain in a logic high state (i.e., VO>2.0 V). Common mode transient immunity in logic low level is the maximum tolerable (negative) dVcm/dt on the trailing edge of the common mode pulse signal, VCM, to assure that the output will remain in a logic low state (i.e., VO<0.8 V). (Refer to Fig.10) 8. In applications where dVcm/dt may exceed 50,000 V/s (Such as static discharge), a series resistor, RCC, should be included to protect the detector chip from destructive surge currents. The recommended value for RCC is 240 V per volt of allowable drop in VCC (between pin 8 and VCC) with a minimum value of 240 . 9. Device is considered a two terminal device: Pins 1, 2, 3 and 4 are shorted together and Pins 5, 6, 7 and 8 are shorted together. 10. The 2500 VRMS/1 min. capability is validated by a 3.0 kVRMS/1 sec. dielectric voltage withstand test. 11. AC voltage is instantaneous voltage for VTH+ & VTH-. 12. All typicals at TA = 25C, VCC = 5 V unless otherwise specified. (c) 2003 Fairchild Semiconductor Corporation Page 4 of 11 11/8/04 AC/DC TO LOGIC INTERFACE OPTOCOUPLER HCPL-3700 TYPICAL PERFORMANCE CURVES Fig. 2 Input Current vs. Input Voltage 4.0 50 3.5 45 DC (Pins 1,2 shorted together pins 3,4 shorted together) 40 IIN - INPUT CURRENT (mA) 3.0 2.5 2.0 1.5 1.0 30 25 20 15 10 5 0 0.5 AC (pins 2 & 3 Open) -5 0.0 -10 6 8 10 12 14 16 18 20 0 2 4 VCC - OPERATING SUPPLY VOLTAGE (V) 8 10 12 14 Fig. 4 Current Threshold/Voltage Threshold vs. Temperature Fig. 3 Input Current/Low Level Output Voltage vs. Temperature 120 4.2 3.2 4.0 110 4.0 3.0 3.8 100 3.6 90 IIN VIN = 5.0 V (PINS 2 and 3) VCC = 5.0 V 3.4 3.2 80 70 3.0 60 2.8 50 2.6 40 VOL VCC = 5.0 V IOL = 4.2 mA 2.4 2.2 30 20 2.0 1.8 -40 10 -20 0 25 45 VTH(DC) - VOLTAGE THRESHOLD (V) 4.2 VOL (mV) Input Current, IIN (mA) 6 VIN - INPUT VOLTAGE (V) VTH+ 3.6 2.6 3.4 2.4 3.2 2.2 ITH+ 3.0 2.0 2.8 1.8 2.6 1.6 VTH- 2.4 1.4 2.2 1.2 ITH- 2.0 1.0 1.8 0 85 65 2.8 3.8 ITH(DC) - CURRENT THRESHOLD (mA) 4 0.8 -40 -20 0 25 45 65 85 TA - TEMPERATURE (C) TA - TEMPERATURE (C) Fig. 5 Propagation Delay vs. Temperature Fig. 6 Rise and Fall Time vs. Temperature 70 100 0.8 90 60 0.7 Tf 80 0.6 50 Tr - RISE TIME (s) TP - PROPAGATION DELAY (s) DC (Pins 1 & 4 Open) 35 40 TPLH 30 TPHL 20 70 0.5 60 50 0.4 40 0.3 30 Tf - FALL TIME (s) ICCL - LOGIC LOW SUPPLY CURRENT (mA) Fig. 1 Logic Low Supply Current vs. Operating Supply Voltage 0.2 20 10 Tr 0.1 10 0 -60 -40 -20 0 20 40 60 80 100 0 -40 TA - TEMPERATURE (C) (c) 2003 Fairchild Semiconductor Corporation 0.0 -20 0 25 45 65 85 TA - TEMPERATURE (C) Page 5 of 11 11/8/04 AC/DC TO LOGIC INTERFACE OPTOCOUPLER HCPL-3700 Fig. 8 External Threshold Characteristics V+/V- vs. Rx V+/V- -EXTERNAL THRESHOLD VOLTAGE (V) Fig. 7 Logic High Supply Current vs. Temperature ICCH - LOGIC HIGH SUPPLY CURRENT (nA) 1000 VCC = 18 V VO = OPEN IIN = 0 mA 100 10 1 -60 -40 -20 0 20 40 60 80 100 V- (AC) V+ (AC) 250 200 V+ (DC) 150 100 V- (DC) 50 0 0 40 80 120 160 200 240 RX - EXTERNAL SERIES RESISTOR (K) TA - TEMPERATURE (C) (c) 2003 Fairchild Semiconductor Corporation 300 Page 6 of 11 11/8/04 AC/DC TO LOGIC INTERFACE OPTOCOUPLER HCPL-3700 +5V 5V 1 AC Pulse Generator tr = 5ns Z O= 50 VCC 8 2 DC+ 3 DC4 AC 7 VO .1uf bypass 2.5V Input (VIN) RL 0V t PHL Output 6 t PLH (VO ) VO Output (VO ) GND 5 90% 10% 90% 10% 1.5 V VOL tr tf VIN Pulse Amplitude = 50 V Pulse Width = 1 ms f = 100 Hz Tr = Tf = 1.0 s (10 - 90%) Fig. 9. Switching Test Circuit VCM H I IN RCC* 1 AC A B 2 DC+ 3 DC- VFF 4 AC VCM L +5V VCC 8 7 VO .1uf bypass RL VCM (VO ) GND 5 5V CM H VO CL** + 5V Output 6 Switching Pos. (A) I IN = 0 mA VO (Min) VCM * SEE NOTE 8 Pulse Gen VO (Max) ** CL IS 30 pF, WHICH INCLUDES PROBE AND STRAY WIRING CAPACITANCE VO Switching Pos. (B) I IN = 3.11 mA VOL CM L Fig. 10. Test Circuit for Common Mode Transient Immunity and Typical Waveforms (c) 2003 Fairchild Semiconductor Corporation Page 7 of 11 11/8/04 AC/DC TO LOGIC INTERFACE OPTOCOUPLER HCPL-3700 Package Dimensions (Through Hole) Package Dimensions (Surface Mount) 0.390 (9.91) 0.370 (9.40) PIN 1 ID. 4 4 3 2 3 2 1 1 0.270 (6.86) 0.250 (6.35) 5 6 7 0.270 (6.86) 0.250 (6.35) 8 5 SEATING PLANE 0.390 (9.91) 0.370 (9.40) 6 7 8 0.070 (1.78) 0.045 (1.14) 0.070 (1.78) 0.045 (1.14) 0.154 (3.90) 0.120 (3.05) 0.022 (0.56) 0.016 (0.41) 0.016 (0.40) 0.008 (0.20) 0.100 (2.54) TYP 0.022 (0.56) 0.016 (0.41) 15 MAX 0.100 (2.54) TYP 0.300 (7.62) TYP Lead Coplanarity : 0.004 (0.10) MAX Package Dimensions (0.4"Lead Spacing) 4 3 2 0.300 (7.62) TYP 0.020 (0.51) MIN 0.020 (0.51) MIN 0.200 (5.08) 0.140 (3.55) PIN 1 ID. 0.016 (0.41) 0.008 (0.20) 0.045 [1.14] 0.315 (8.00) MIN 0.405 (10.30) MIN NOTE All dimensions are in inches (millimeters) PIN 1 ID. 1 0.270 (6.86) 0.250 (6.35) 5 6 7 8 SEATING PLANE 0.390 (9.91) 0.370 (9.40) 0.070 (1.78) 0.045 (1.14) 0.004 (0.10) MIN 0.200 (5.08) 0.140 (3.55) 0.154 (3.90) 0.120 (3.05) 0.022 (0.56) 0.016 (0.41) 0.016 (0.40) 0.008 (0.20) 0.100 (2.54) TYP (c) 2003 Fairchild Semiconductor Corporation 0 to 15 0.400 (10.16) TYP Page 8 of 11 11/8/04 AC/DC TO LOGIC INTERFACE OPTOCOUPLER HCPL-3700 ORDERING INFORMATION Option Order Entry Identifier Description S .S Surface Mount Lead Bend SD .SD Surface Mount; Tape and reel W .W 0.4" Lead Spacing MARKING INFORMATION 1 V 3 3700 2 XX YY T1 6 4 5 Definitions 1 Fairchild logo 2 Device number 3 VDE mark (Note: Only appears on parts ordered with VDE option - See order entry table) 4 Two digit year code, e.g., `03' 5 Two digit work week ranging from `01' to `53' 6 Assembly package code (c) 2003 Fairchild Semiconductor Corporation Page 9 of 11 11/8/04 AC/DC TO LOGIC INTERFACE OPTOCOUPLER HCPL-3700 QT Carrier Tape Specifications ("D" Taping Orientation) 12.0 0.1 4.0 0.1 4.90 0.20 O1.55 0.05 4.0 0.1 0.30 0.05 1.75 0.10 7.5 0.1 16.0 0.3 13.2 0.2 10.30 0.20 O1.6 0.1 10.30 0.20 0.1 MAX User Direction of Feed Reflow Profile Temperature (C) 300 215 C, 10-30 s 250 225 C peak 200 150 Time above 183C, 60-150 sec 100 50 Ramp up = 3C/sec 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 Time (Minute) * Peak reflow temperature: 225C (package surface temperature) * Time of temperature higher than 183C for 60-150 seconds * One time soldering reflow is recommended (c) 2003 Fairchild Semiconductor Corporation Page 10 of 11 11/8/04 AC/DC TO LOGIC INTERFACE OPTOCOUPLER HCPL-3700 DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. (c) 2003 Fairchild Semiconductor Corporation 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Page 11 of 11 11/8/04